12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26
27 #include "precompiled.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "interp_masm_ppc.hpp"
30 #include "interpreter/interpreterRuntime.hpp"
31 #include "prims/jvmtiThreadState.hpp"
32 #include "runtime/sharedRuntime.hpp"
33
34 #ifdef PRODUCT
35 #define BLOCK_COMMENT(str) // nothing
36 #else
37 #define BLOCK_COMMENT(str) block_comment(str)
38 #endif
39
40 void InterpreterMacroAssembler::null_check_throw(Register a, int offset, Register temp_reg) {
41 address exception_entry = Interpreter::throw_NullPointerException_entry();
42 MacroAssembler::null_check_throw(a, offset, temp_reg, exception_entry);
43 }
44
45 void InterpreterMacroAssembler::jump_to_entry(address entry, Register Rscratch) {
46 assert(entry, "Entry must have been generated by now");
47 if (is_within_range_of_b(entry, pc())) {
48 b(entry);
49 } else {
50 load_const_optimized(Rscratch, entry, R0);
51 mtctr(Rscratch);
52 bctr();
53 }
54 }
55
56 void InterpreterMacroAssembler::dispatch_next(TosState state, int bcp_incr) {
57 Register bytecode = R12_scratch2;
58 if (bcp_incr != 0) {
59 lbzu(bytecode, bcp_incr, R14_bcp);
60 } else {
61 lbz(bytecode, 0, R14_bcp);
62 }
63
64 dispatch_Lbyte_code(state, bytecode, Interpreter::dispatch_table(state));
65 }
66
67 void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) {
68 // Load current bytecode.
69 Register bytecode = R12_scratch2;
70 lbz(bytecode, 0, R14_bcp);
71 dispatch_Lbyte_code(state, bytecode, table);
72 }
73
74 // Dispatch code executed in the prolog of a bytecode which does not do it's
75 // own dispatch. The dispatch address is computed and placed in R24_dispatch_addr.
76 void InterpreterMacroAssembler::dispatch_prolog(TosState state, int bcp_incr) {
77 Register bytecode = R12_scratch2;
78 lbz(bytecode, bcp_incr, R14_bcp);
79
80 load_dispatch_table(R24_dispatch_addr, Interpreter::dispatch_table(state));
81
82 sldi(bytecode, bytecode, LogBytesPerWord);
83 ldx(R24_dispatch_addr, R24_dispatch_addr, bytecode);
84 }
186 std(Rscratch2, in_bytes(JvmtiThreadState::earlyret_value_offset()), RjvmtiState);
187 // Set tos state field to illegal value.
188 li(Rscratch2, ilgl);
189 stw(Rscratch2, in_bytes(JvmtiThreadState::earlyret_tos_offset()), RjvmtiState);
190 }
191
192 // Common code to dispatch and dispatch_only.
193 // Dispatch value in Lbyte_code and increment Lbcp.
194
195 void InterpreterMacroAssembler::load_dispatch_table(Register dst, address* table) {
196 address table_base = (address)Interpreter::dispatch_table((TosState)0);
197 intptr_t table_offs = (intptr_t)table - (intptr_t)table_base;
198 if (is_simm16(table_offs)) {
199 addi(dst, R25_templateTableBase, (int)table_offs);
200 } else {
201 load_const_optimized(dst, table, R0);
202 }
203 }
204
205 void InterpreterMacroAssembler::dispatch_Lbyte_code(TosState state, Register bytecode,
206 address* table, bool verify) {
207 if (verify) {
208 unimplemented("dispatch_Lbyte_code: verify"); // See Sparc Implementation to implement this
209 }
210
211 assert_different_registers(bytecode, R11_scratch1);
212
213 // Calc dispatch table address.
214 load_dispatch_table(R11_scratch1, table);
215
216 sldi(R12_scratch2, bytecode, LogBytesPerWord);
217 ldx(R11_scratch1, R11_scratch1, R12_scratch2);
218
219 // Jump off!
220 mtctr(R11_scratch1);
221 bcctr(bcondAlways, 0, bhintbhBCCTRisNotPredictable);
222 }
223
224 void InterpreterMacroAssembler::load_receiver(Register Rparam_count, Register Rrecv_dst) {
225 sldi(Rrecv_dst, Rparam_count, Interpreter::logStackElementSize);
226 ldx(Rrecv_dst, Rrecv_dst, R15_esp);
227 }
228
229 // helpers for expression stack
230
231 void InterpreterMacroAssembler::pop_i(Register r) {
232 lwzu(r, Interpreter::stackElementSize, R15_esp);
233 }
234
|
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26
27 #include "precompiled.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "interp_masm_ppc.hpp"
30 #include "interpreter/interpreterRuntime.hpp"
31 #include "prims/jvmtiThreadState.hpp"
32 #include "runtime/safepointMechanism.hpp"
33 #include "runtime/sharedRuntime.hpp"
34
35 #ifdef PRODUCT
36 #define BLOCK_COMMENT(str) // nothing
37 #else
38 #define BLOCK_COMMENT(str) block_comment(str)
39 #endif
40
41 void InterpreterMacroAssembler::null_check_throw(Register a, int offset, Register temp_reg) {
42 address exception_entry = Interpreter::throw_NullPointerException_entry();
43 MacroAssembler::null_check_throw(a, offset, temp_reg, exception_entry);
44 }
45
46 void InterpreterMacroAssembler::jump_to_entry(address entry, Register Rscratch) {
47 assert(entry, "Entry must have been generated by now");
48 if (is_within_range_of_b(entry, pc())) {
49 b(entry);
50 } else {
51 load_const_optimized(Rscratch, entry, R0);
52 mtctr(Rscratch);
53 bctr();
54 }
55 }
56
57 void InterpreterMacroAssembler::dispatch_next(TosState state, int bcp_incr, bool generate_poll) {
58 Register bytecode = R12_scratch2;
59 if (bcp_incr != 0) {
60 lbzu(bytecode, bcp_incr, R14_bcp);
61 } else {
62 lbz(bytecode, 0, R14_bcp);
63 }
64
65 dispatch_Lbyte_code(state, bytecode, Interpreter::dispatch_table(state), generate_poll);
66 }
67
68 void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) {
69 // Load current bytecode.
70 Register bytecode = R12_scratch2;
71 lbz(bytecode, 0, R14_bcp);
72 dispatch_Lbyte_code(state, bytecode, table);
73 }
74
75 // Dispatch code executed in the prolog of a bytecode which does not do it's
76 // own dispatch. The dispatch address is computed and placed in R24_dispatch_addr.
77 void InterpreterMacroAssembler::dispatch_prolog(TosState state, int bcp_incr) {
78 Register bytecode = R12_scratch2;
79 lbz(bytecode, bcp_incr, R14_bcp);
80
81 load_dispatch_table(R24_dispatch_addr, Interpreter::dispatch_table(state));
82
83 sldi(bytecode, bytecode, LogBytesPerWord);
84 ldx(R24_dispatch_addr, R24_dispatch_addr, bytecode);
85 }
187 std(Rscratch2, in_bytes(JvmtiThreadState::earlyret_value_offset()), RjvmtiState);
188 // Set tos state field to illegal value.
189 li(Rscratch2, ilgl);
190 stw(Rscratch2, in_bytes(JvmtiThreadState::earlyret_tos_offset()), RjvmtiState);
191 }
192
193 // Common code to dispatch and dispatch_only.
194 // Dispatch value in Lbyte_code and increment Lbcp.
195
196 void InterpreterMacroAssembler::load_dispatch_table(Register dst, address* table) {
197 address table_base = (address)Interpreter::dispatch_table((TosState)0);
198 intptr_t table_offs = (intptr_t)table - (intptr_t)table_base;
199 if (is_simm16(table_offs)) {
200 addi(dst, R25_templateTableBase, (int)table_offs);
201 } else {
202 load_const_optimized(dst, table, R0);
203 }
204 }
205
206 void InterpreterMacroAssembler::dispatch_Lbyte_code(TosState state, Register bytecode,
207 address* table, bool generate_poll) {
208 assert_different_registers(bytecode, R11_scratch1);
209
210 // Calc dispatch table address.
211 load_dispatch_table(R11_scratch1, table);
212
213 if (SafepointMechanism::uses_thread_local_poll() && generate_poll) {
214 address *sfpt_tbl = Interpreter::safept_table(state);
215 if (table != sfpt_tbl) {
216 Label dispatch;
217 ld(R0, in_bytes(Thread::polling_page_offset()), R16_thread);
218 // Armed page has poll_bit set, if poll bit is cleared just continue.
219 andi_(R0, R0, SafepointMechanism::poll_bit());
220 beq(CCR0, dispatch);
221 load_dispatch_table(R11_scratch1, sfpt_tbl);
222 align(32, 16);
223 bind(dispatch);
224 }
225 }
226
227 sldi(R12_scratch2, bytecode, LogBytesPerWord);
228 ldx(R11_scratch1, R11_scratch1, R12_scratch2);
229
230 // Jump off!
231 mtctr(R11_scratch1);
232 bcctr(bcondAlways, 0, bhintbhBCCTRisNotPredictable);
233 }
234
235 void InterpreterMacroAssembler::load_receiver(Register Rparam_count, Register Rrecv_dst) {
236 sldi(Rrecv_dst, Rparam_count, Interpreter::logStackElementSize);
237 ldx(Rrecv_dst, Rrecv_dst, R15_esp);
238 }
239
240 // helpers for expression stack
241
242 void InterpreterMacroAssembler::pop_i(Register r) {
243 lwzu(r, Interpreter::stackElementSize, R15_esp);
244 }
245
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