8384 // INT unsigned
8385
8386 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8387 match(Set cr (CmpU op1 op2));
8388 size(2);
8389 format %{ "CLR $op1,$op2\t # unsigned" %}
8390 opcode(CLR_ZOPC);
8391 ins_encode(z_rrform(op1, op2));
8392 ins_pipe(pipe_class_dummy);
8393 %}
8394
8395 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8396 match(Set cr (CmpU op1 op2));
8397 size(6);
8398 format %{ "CLFI $op1,$op2\t # unsigned" %}
8399 opcode(CLFI_ZOPC);
8400 ins_encode(z_rilform_unsigned(op1, op2));
8401 ins_pipe(pipe_class_dummy);
8402 %}
8403
8404 instruct compU_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8405 match(Set cr (CmpU op1 zero));
8406 ins_cost(DEFAULT_COST_LOW);
8407 size(2);
8408 format %{ "LTR $op1,$op1\t # unsigned" %}
8409 opcode(LTR_ZOPC);
8410 ins_encode(z_rrform(op1, op1));
8411 ins_pipe(pipe_class_dummy);
8412 %}
8413
8414 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8415 match(Set cr (CmpU op1 (LoadI op2)));
8416 ins_cost(MEMORY_REF_COST);
8417 // TODO: s390 port size(VARIABLE_SIZE);
8418 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8419 opcode(CLY_ZOPC, CL_ZOPC);
8420 ins_encode(z_form_rt_mem_opt(op1, op2));
8421 ins_pipe(pipe_class_dummy);
8422 %}
8423
8424 // LONG signed
8425
8426 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8427 match(Set cr (CmpL op1 op2));
8428 size(4);
8429 format %{ "CGR $op1,$op2\t # long" %}
8430 opcode(CGR_ZOPC);
8431 ins_encode(z_rreform(op1, op2));
8432 ins_pipe(pipe_class_dummy);
8433 %}
|
8384 // INT unsigned
8385
8386 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8387 match(Set cr (CmpU op1 op2));
8388 size(2);
8389 format %{ "CLR $op1,$op2\t # unsigned" %}
8390 opcode(CLR_ZOPC);
8391 ins_encode(z_rrform(op1, op2));
8392 ins_pipe(pipe_class_dummy);
8393 %}
8394
8395 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8396 match(Set cr (CmpU op1 op2));
8397 size(6);
8398 format %{ "CLFI $op1,$op2\t # unsigned" %}
8399 opcode(CLFI_ZOPC);
8400 ins_encode(z_rilform_unsigned(op1, op2));
8401 ins_pipe(pipe_class_dummy);
8402 %}
8403
8404 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8405 match(Set cr (CmpU op1 (LoadI op2)));
8406 ins_cost(MEMORY_REF_COST);
8407 // TODO: s390 port size(VARIABLE_SIZE);
8408 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8409 opcode(CLY_ZOPC, CL_ZOPC);
8410 ins_encode(z_form_rt_mem_opt(op1, op2));
8411 ins_pipe(pipe_class_dummy);
8412 %}
8413
8414 // LONG signed
8415
8416 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8417 match(Set cr (CmpL op1 op2));
8418 size(4);
8419 format %{ "CGR $op1,$op2\t # long" %}
8420 opcode(CGR_ZOPC);
8421 ins_encode(z_rreform(op1, op2));
8422 ins_pipe(pipe_class_dummy);
8423 %}
|