# HG changeset patch
# User mdoerr
# Date 1566227444 -7200
#      Mon Aug 19 17:10:44 2019 +0200
# Node ID cc6002a0354a2341689e569dd0685e3c96818923
# Parent  1b68063404000c86656c49a47b5549945d392363
8229422: Taskqueue: Outdated selection of weak memory model platforms
Reviewed-by:

diff --git a/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp b/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp
--- a/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp
+++ b/src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp
@@ -34,6 +34,13 @@
 
 #define SUPPORTS_NATIVE_CX8
 
+// TODO: aarch64 is CPU_MULTI_COPY_ATOMIC
+// See: "Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8"
+// Should we define it here and remove the following lines?
+#define SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU false
+// Only used when previous define is true.
+#define IRIW_WITH_RELEASE_VOLATILE_IN_CONSTRUCTOR true
+
 // According to the ARMv8 ARM, "Concurrent modification and execution
 // of instructions can lead to the resulting instruction performing
 // any behavior that can be achieved by executing any sequence of
diff --git a/src/hotspot/cpu/arm/globalDefinitions_arm.hpp b/src/hotspot/cpu/arm/globalDefinitions_arm.hpp
--- a/src/hotspot/cpu/arm/globalDefinitions_arm.hpp
+++ b/src/hotspot/cpu/arm/globalDefinitions_arm.hpp
@@ -45,6 +45,12 @@
 #define SUPPORTS_NATIVE_CX8
 #endif
 
+// TODO: arm is not CPU_MULTI_COPY_ATOMIC
+// Should we implement support for IRIW? (Subject to JEP 188: Java Memory Model Update.)
+#define SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU false
+// Only used when previous define is true.
+#define IRIW_WITH_RELEASE_VOLATILE_IN_CONSTRUCTOR true
+
 #define STUBROUTINES_MD_HPP    "stubRoutines_arm.hpp"
 #define INTERP_MASM_MD_HPP     "interp_masm_arm.hpp"
 #define TEMPLATETABLE_MD_HPP   "templateTable_arm.hpp"
diff --git a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
--- a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
+++ b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
@@ -2671,7 +2671,7 @@
                 noreg, /*check without ldarx first*/true);
   }
 
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ isync();
   } else {
     __ sync();
diff --git a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp
--- a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp
+++ b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp
@@ -642,7 +642,7 @@
   new_value.load_item();
 
   // Volatile load may be followed by Unsafe CAS.
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ membar();
   } else {
     __ membar_release();
@@ -674,7 +674,7 @@
   value.load_item();
 
   // Volatile load may be followed by Unsafe CAS.
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ membar();
   } else {
     __ membar_release();
@@ -682,7 +682,7 @@
 
   __ xchg(addr, value.result(), result, tmp);
 
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ membar_acquire();
   } else {
     __ membar();
@@ -698,7 +698,7 @@
   value.load_item();
 
   // Volatile load may be followed by Unsafe CAS.
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ membar(); // To be safe. Unsafe semantics are unclear.
   } else {
     __ membar_release();
@@ -706,7 +706,7 @@
 
   __ xadd(addr, value.result(), result, tmp);
 
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ membar_acquire();
   } else {
     __ membar();
diff --git a/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp b/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp
--- a/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp
+++ b/src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp
@@ -41,8 +41,10 @@
 
 #define SUPPORTS_NATIVE_CX8
 
-// The PPC CPUs are NOT multiple-copy-atomic.
-#define CPU_NOT_MULTIPLE_COPY_ATOMIC
+// Decision if IRIW support is needed is subject to JEP 188: Java Memory Model Update.
+#define SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU SupportIRIW
+// Only used when previous define is true. Performance overhead is low.
+#define IRIW_WITH_RELEASE_VOLATILE_IN_CONSTRUCTOR true
 
 // The expected size in bytes of a cache line, used to pad data structures.
 #define DEFAULT_CACHE_LINE_SIZE 128
diff --git a/src/hotspot/cpu/ppc/globals_ppc.hpp b/src/hotspot/cpu/ppc/globals_ppc.hpp
--- a/src/hotspot/cpu/ppc/globals_ppc.hpp
+++ b/src/hotspot/cpu/ppc/globals_ppc.hpp
@@ -202,5 +202,9 @@
                                                                             \
   experimental(bool, UseRTMXendForLockBusy, true,                           \
           "Use RTM Xend instead of Xabort when lock busy")                  \
+                                                                            \
+  experimental(bool, SupportIRIW, true,                                     \
+          "Order Independent Reads of Independent Writes of volatile "      \
+          "variables (PPC64 CPUs are not multi-copy atomic)")               \
 
 #endif // CPU_PPC_GLOBALS_PPC_HPP
diff --git a/src/hotspot/cpu/ppc/jniFastGetField_ppc.cpp b/src/hotspot/cpu/ppc/jniFastGetField_ppc.cpp
--- a/src/hotspot/cpu/ppc/jniFastGetField_ppc.cpp
+++ b/src/hotspot/cpu/ppc/jniFastGetField_ppc.cpp
@@ -77,7 +77,7 @@
   __ andi_(R0, Rcounter, 1);
   __ bne(CCR0, slow);
 
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     // Field may be volatile.
     __ fence();
   } else {
diff --git a/src/hotspot/cpu/ppc/ppc.ad b/src/hotspot/cpu/ppc/ppc.ad
--- a/src/hotspot/cpu/ppc/ppc.ad
+++ b/src/hotspot/cpu/ppc/ppc.ad
@@ -7948,7 +7948,7 @@
     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 $res$$Register, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -7968,7 +7968,7 @@
     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 $res$$Register, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -7988,7 +7988,7 @@
     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 $res$$Register, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8008,7 +8008,7 @@
     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 $res$$Register, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8027,7 +8027,7 @@
     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 $res$$Register, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8046,7 +8046,7 @@
     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 $res$$Register, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8065,7 +8065,7 @@
     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 $res$$Register, NULL, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8084,7 +8084,7 @@
     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 $res$$Register, NULL, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8134,7 +8134,7 @@
     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
-                support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
+                SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
   %}
   ins_pipe(pipe_class_default);
@@ -8149,7 +8149,7 @@
     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
-                support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
+                SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
   %}
   ins_pipe(pipe_class_default);
@@ -8194,7 +8194,7 @@
     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
-                support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
+                SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
   %}
   ins_pipe(pipe_class_default);
@@ -8209,7 +8209,7 @@
     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
-                support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
+                SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
   %}
   ins_pipe(pipe_class_default);
@@ -8241,7 +8241,7 @@
     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
     // value is never passed to caller.
     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
-                support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
+                SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
   %}
   ins_pipe(pipe_class_default);
@@ -8273,7 +8273,7 @@
     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
     // value is never passed to caller.
     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
-                support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
+                SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
   %}
   ins_pipe(pipe_class_default);
@@ -8306,7 +8306,7 @@
     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
     // value is never passed to caller.
     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
-                support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
+                SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
   %}
   ins_pipe(pipe_class_default);
@@ -8338,7 +8338,7 @@
     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
     // value is never passed to caller.
     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
-                support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
+                SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
   %}
   ins_pipe(pipe_class_default);
@@ -8387,7 +8387,7 @@
     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 noreg, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
@@ -8408,7 +8408,7 @@
     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 noreg, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
@@ -8459,7 +8459,7 @@
     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 noreg, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
@@ -8480,7 +8480,7 @@
     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 noreg, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
@@ -8516,7 +8516,7 @@
     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 noreg, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
@@ -8552,7 +8552,7 @@
     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 noreg, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
@@ -8588,7 +8588,7 @@
     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 noreg, NULL, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
@@ -8624,7 +8624,7 @@
     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
                 noreg, NULL, true);
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
@@ -8644,7 +8644,7 @@
   ins_encode %{
     __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
                   R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8661,7 +8661,7 @@
   ins_encode %{
     __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8678,7 +8678,7 @@
   ins_encode %{
     __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
                   R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8695,7 +8695,7 @@
   ins_encode %{
     __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8711,7 +8711,7 @@
   ins_encode %{
     __ getandaddw($res$$Register, $src$$Register, $mem_ptr$$Register,
                   R0, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8727,7 +8727,7 @@
   ins_encode %{
     __ getandaddd($res$$Register, $src$$Register, $mem_ptr$$Register,
                   R0, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8744,7 +8744,7 @@
   ins_encode %{
     __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
                   noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8761,7 +8761,7 @@
   ins_encode %{
     __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8778,7 +8778,7 @@
   ins_encode %{
     __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
                   noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8795,7 +8795,7 @@
   ins_encode %{
     __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8811,7 +8811,7 @@
   ins_encode %{
     __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
                   MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8827,7 +8827,7 @@
   ins_encode %{
     __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
                   MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8843,7 +8843,7 @@
   ins_encode %{
     __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
                   MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
@@ -8859,7 +8859,7 @@
   ins_encode %{
     __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
                   MacroAssembler::cmpxchgx_hint_atomic_update());
-    if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+    if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
       __ isync();
     } else {
       __ sync();
diff --git a/src/hotspot/cpu/ppc/templateTable_ppc_64.cpp b/src/hotspot/cpu/ppc/templateTable_ppc_64.cpp
--- a/src/hotspot/cpu/ppc/templateTable_ppc_64.cpp
+++ b/src/hotspot/cpu/ppc/templateTable_ppc_64.cpp
@@ -2496,7 +2496,7 @@
   // Load from branch table and dispatch (volatile case: one instruction ahead).
   __ sldi(Rflags, Rflags, LogBytesPerWord);
   __ cmpwi(CCR6, Rscratch, 1); // Volatile?
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ sldi(Rscratch, Rscratch, exact_log2(BytesPerInstWord)); // Volatile ? size of 1 instruction : 0.
   }
   __ ldx(Rbtable, Rbtable, Rflags);
@@ -2508,7 +2508,7 @@
     __ verify_oop(Rclass_or_obj);
   }
 
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ subf(Rbtable, Rscratch, Rbtable); // Point to volatile/non-volatile entry point.
   }
   __ mtctr(Rbtable);
@@ -2833,7 +2833,7 @@
 
   // Load from branch table and dispatch (volatile case: one instruction ahead).
   __ sldi(Rflags, Rflags, LogBytesPerWord);
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ cmpwi(CR_is_vol, Rscratch, 1);  // Volatile?
   }
   __ sldi(Rscratch, Rscratch, exact_log2(BytesPerInstWord)); // Volatile? size of instruction 1 : 0.
@@ -2869,7 +2869,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_dputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
   }
   __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -2885,7 +2885,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_fputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
   }
   __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -2901,7 +2901,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_iputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
   }
   __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -2917,7 +2917,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_lputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
   }
   __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -2933,7 +2933,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_bputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
   }
   __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -2950,7 +2950,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_zputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
   }
   __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -2966,7 +2966,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_cputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
   }
   __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -2982,7 +2982,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_sputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
   }
   __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -2998,7 +2998,7 @@
   if (!is_static && rc == may_rewrite) {
     patch_bytecode(Bytecodes::_fast_aputfield, Rbc, Rscratch, true, byte_no);
   }
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ beq(CR_is_vol, Lvolatile); // Volatile?
     __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
 
@@ -3056,7 +3056,7 @@
 
   // Get volatile flag.
   __ rldicl_(Rscratch, Rflags, 64-ConstantPoolCacheEntry::is_volatile_shift, 63); // Extract volatile bit.
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) { __ cmpdi(CR_is_vol, Rscratch, 1); }
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ cmpdi(CR_is_vol, Rscratch, 1); }
   {
     Label LnotVolatile;
     __ beq(CCR0, LnotVolatile);
@@ -3103,7 +3103,7 @@
     default: ShouldNotReachHere();
   }
 
-  if (!support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (!SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     Label LVolatile;
     __ beq(CR_is_vol, LVolatile);
     __ dispatch_epilog(vtos, Bytecodes::length_for(bytecode()));
@@ -3148,7 +3148,7 @@
       __ dispatch_epilog(state, Bytecodes::length_for(bytecode()));
 
       __ bind(LisVolatile);
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       do_oop_load(_masm, Rclass_or_obj, Roffset, R17_tos, Rscratch, /* nv temp */ Rflags, IN_HEAP);
       __ verify_oop(R17_tos);
       __ twi_0(R17_tos);
@@ -3161,7 +3161,7 @@
       __ dispatch_epilog(state, Bytecodes::length_for(bytecode()));
 
       __ bind(LisVolatile);
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ lwax(R17_tos, Rclass_or_obj, Roffset);
       __ twi_0(R17_tos);
       __ isync();
@@ -3173,7 +3173,7 @@
       __ dispatch_epilog(state, Bytecodes::length_for(bytecode()));
 
       __ bind(LisVolatile);
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ ldx(R17_tos, Rclass_or_obj, Roffset);
       __ twi_0(R17_tos);
       __ isync();
@@ -3186,7 +3186,7 @@
       __ dispatch_epilog(state, Bytecodes::length_for(bytecode()));
 
       __ bind(LisVolatile);
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ lbzx(R17_tos, Rclass_or_obj, Roffset);
       __ twi_0(R17_tos);
       __ extsb(R17_tos, R17_tos);
@@ -3199,7 +3199,7 @@
       __ dispatch_epilog(state, Bytecodes::length_for(bytecode()));
 
       __ bind(LisVolatile);
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ lhzx(R17_tos, Rclass_or_obj, Roffset);
       __ twi_0(R17_tos);
       __ isync();
@@ -3211,7 +3211,7 @@
       __ dispatch_epilog(state, Bytecodes::length_for(bytecode()));
 
       __ bind(LisVolatile);
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ lhax(R17_tos, Rclass_or_obj, Roffset);
       __ twi_0(R17_tos);
       __ isync();
@@ -3224,7 +3224,7 @@
 
       __ bind(LisVolatile);
       Label Ldummy;
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ lfsx(F15_ftos, Rclass_or_obj, Roffset);
       __ fcmpu(CCR0, F15_ftos, F15_ftos); // Acquire by cmp-br-isync.
       __ bne_predict_not_taken(CCR0, Ldummy);
@@ -3239,7 +3239,7 @@
 
       __ bind(LisVolatile);
       Label Ldummy;
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ lfdx(F15_ftos, Rclass_or_obj, Roffset);
       __ fcmpu(CCR0, F15_ftos, F15_ftos); // Acquire by cmp-br-isync.
       __ bne_predict_not_taken(CCR0, Ldummy);
@@ -3288,7 +3288,7 @@
       __ dispatch_epilog(state, Bytecodes::length_for(bytecode()) - 1); // Undo bcp increment.
 
       __ bind(LisVolatile);
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       do_oop_load(_masm, Rclass_or_obj, Roffset, R17_tos, Rscratch, /* nv temp */ Rflags, IN_HEAP);
       __ verify_oop(R17_tos);
       __ twi_0(R17_tos);
@@ -3301,7 +3301,7 @@
       __ dispatch_epilog(state, Bytecodes::length_for(bytecode()) - 1); // Undo bcp increment.
 
       __ bind(LisVolatile);
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ lwax(R17_tos, Rclass_or_obj, Roffset);
       __ twi_0(R17_tos);
       __ isync();
@@ -3314,7 +3314,7 @@
 
       __ bind(LisVolatile);
       Label Ldummy;
-      if (support_IRIW_for_not_multiple_copy_atomic_cpu) { __ fence(); }
+      if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) { __ fence(); }
       __ lfsx(F15_ftos, Rclass_or_obj, Roffset);
       __ fcmpu(CCR0, F15_ftos, F15_ftos); // Acquire by cmp-br-isync.
       __ bne_predict_not_taken(CCR0, Ldummy);
diff --git a/src/hotspot/cpu/s390/globalDefinitions_s390.hpp b/src/hotspot/cpu/s390/globalDefinitions_s390.hpp
--- a/src/hotspot/cpu/s390/globalDefinitions_s390.hpp
+++ b/src/hotspot/cpu/s390/globalDefinitions_s390.hpp
@@ -42,6 +42,8 @@
 
 #define SUPPORTS_NATIVE_CX8
 
+#define CPU_MULTI_COPY_ATOMIC
+
 // Indicates whether the C calling conventions require that
 // 32-bit integer argument values are extended to 64 bits.
 // This is the case on z/Architecture.
diff --git a/src/hotspot/cpu/sparc/globalDefinitions_sparc.hpp b/src/hotspot/cpu/sparc/globalDefinitions_sparc.hpp
--- a/src/hotspot/cpu/sparc/globalDefinitions_sparc.hpp
+++ b/src/hotspot/cpu/sparc/globalDefinitions_sparc.hpp
@@ -36,6 +36,8 @@
 
 #define SUPPORTS_NATIVE_CX8
 
+#define CPU_MULTI_COPY_ATOMIC
+
 // The expected size in bytes of a cache line, used to pad data structures.
 #if defined(TIERED)
   // tiered, 64-bit, large machine
diff --git a/src/hotspot/cpu/x86/globalDefinitions_x86.hpp b/src/hotspot/cpu/x86/globalDefinitions_x86.hpp
--- a/src/hotspot/cpu/x86/globalDefinitions_x86.hpp
+++ b/src/hotspot/cpu/x86/globalDefinitions_x86.hpp
@@ -33,6 +33,8 @@
 
 #define SUPPORTS_NATIVE_CX8
 
+#define CPU_MULTI_COPY_ATOMIC
+
 // The expected size in bytes of a cache line, used to pad data structures.
 #if defined(TIERED)
   #ifdef _LP64
diff --git a/src/hotspot/cpu/zero/globalDefinitions_zero.hpp b/src/hotspot/cpu/zero/globalDefinitions_zero.hpp
--- a/src/hotspot/cpu/zero/globalDefinitions_zero.hpp
+++ b/src/hotspot/cpu/zero/globalDefinitions_zero.hpp
@@ -30,6 +30,9 @@
 #define SUPPORTS_NATIVE_CX8
 #endif
 
+// Not available.
+#define SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU false
+
 #include <ffi.h>
 
 // Indicates whether the C calling conventions require that
diff --git a/src/hotspot/share/c1/c1_GraphBuilder.cpp b/src/hotspot/share/c1/c1_GraphBuilder.cpp
--- a/src/hotspot/share/c1/c1_GraphBuilder.cpp
+++ b/src/hotspot/share/c1/c1_GraphBuilder.cpp
@@ -1470,7 +1470,9 @@
   bool need_mem_bar = false;
   if (method()->name() == ciSymbol::object_initializer_name() &&
       (scope()->wrote_final() || (AlwaysSafeConstructors && scope()->wrote_fields())
-                              || (support_IRIW_for_not_multiple_copy_atomic_cpu && scope()->wrote_volatile())
+                              || (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU &&
+                                  IRIW_WITH_RELEASE_VOLATILE_IN_CONSTRUCTOR &&
+                                  scope()->wrote_volatile())
      )){
     need_mem_bar = true;
   }
diff --git a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp
--- a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp
+++ b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp
@@ -159,7 +159,7 @@
     __ store(value, access.resolved_addr()->as_address_ptr(), access.access_emit_info(), patch_code);
   }
 
-  if (is_volatile && !support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (is_volatile && !SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     __ membar();
   }
 }
@@ -172,7 +172,7 @@
   bool mask_boolean = (decorators & C1_MASK_BOOLEAN) != 0;
   bool in_native = (decorators & IN_NATIVE) != 0;
 
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu && is_volatile) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU && is_volatile) {
     __ membar();
   }
 
diff --git a/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp b/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp
--- a/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp
+++ b/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp
@@ -198,7 +198,7 @@
       if (is_release) {
         _leading_membar = kit->insert_mem_bar(Op_MemBarRelease);
       } else if (is_volatile) {
-        if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+        if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
           _leading_membar = kit->insert_mem_bar(Op_MemBarVolatile);
         } else {
           _leading_membar = kit->insert_mem_bar(Op_MemBarRelease);
@@ -218,7 +218,7 @@
       // exception paths do not take memory state from the memory barrier,
       // so there's no problems making a strong assert about mixing users
       // of safe & unsafe memory.
-      if (is_volatile && support_IRIW_for_not_multiple_copy_atomic_cpu) {
+      if (is_volatile && SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
         assert(kit != NULL, "unsupported at optimization time");
         _leading_membar = kit->insert_mem_bar(Op_MemBarVolatile);
       }
@@ -269,7 +269,7 @@
       }
     } else if (is_write) {
       // If not multiple copy atomic, we do the MemBarVolatile before the load.
-      if (is_volatile && !support_IRIW_for_not_multiple_copy_atomic_cpu) {
+      if (is_volatile && !SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
         assert(kit != NULL, "unsupported at optimization time");
         Node* n = _access.raw_access();
         Node* mb = kit->insert_mem_bar(Op_MemBarVolatile, n); // Use fat membar
@@ -281,7 +281,7 @@
       if (is_volatile || is_acquire) {
         assert(kit != NULL, "unsupported at optimization time");
         Node* n = _access.raw_access();
-        assert(_leading_membar == NULL || support_IRIW_for_not_multiple_copy_atomic_cpu, "no leading membar expected");
+        assert(_leading_membar == NULL || SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU, "no leading membar expected");
         Node* mb = kit->insert_mem_bar(Op_MemBarAcquire, n);
         mb->as_MemBar()->set_trailing_load();
       }
diff --git a/src/hotspot/share/gc/shared/taskqueue.inline.hpp b/src/hotspot/share/gc/shared/taskqueue.inline.hpp
--- a/src/hotspot/share/gc/shared/taskqueue.inline.hpp
+++ b/src/hotspot/share/gc/shared/taskqueue.inline.hpp
@@ -207,7 +207,7 @@
   // Architectures with weak memory model require a barrier here
   // to guarantee that bottom is not older than age,
   // which is crucial for the correctness of the algorithm.
-#if !(defined SPARC || defined IA32 || defined AMD64)
+#ifndef CPU_MULTI_COPY_ATOMIC
   OrderAccess::fence();
 #endif
   uint localBot = OrderAccess::load_acquire(&_bottom);
diff --git a/src/hotspot/share/interpreter/bytecodeInterpreter.cpp b/src/hotspot/share/interpreter/bytecodeInterpreter.cpp
--- a/src/hotspot/share/interpreter/bytecodeInterpreter.cpp
+++ b/src/hotspot/share/interpreter/bytecodeInterpreter.cpp
@@ -1974,7 +1974,7 @@
           TosState tos_type = cache->flag_state();
           int field_offset = cache->f2_as_index();
           if (cache->is_volatile()) {
-            if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+            if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
               OrderAccess::fence();
             }
             if (tos_type == atos) {
diff --git a/src/hotspot/share/oops/accessBackend.inline.hpp b/src/hotspot/share/oops/accessBackend.inline.hpp
--- a/src/hotspot/share/oops/accessBackend.inline.hpp
+++ b/src/hotspot/share/oops/accessBackend.inline.hpp
@@ -131,7 +131,7 @@
 inline typename EnableIf<
   HasDecorator<ds, MO_SEQ_CST>::value, T>::type
 RawAccessBarrier<decorators>::load_internal(void* addr) {
-  if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
+  if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
     OrderAccess::fence();
   }
   return OrderAccess::load_acquire(reinterpret_cast<const volatile T*>(addr));
diff --git a/src/hotspot/share/opto/memnode.cpp b/src/hotspot/share/opto/memnode.cpp
--- a/src/hotspot/share/opto/memnode.cpp
+++ b/src/hotspot/share/opto/memnode.cpp
@@ -2855,7 +2855,7 @@
         trailing = u->as_MemBar();
 #ifdef ASSERT
         Node* leading = trailing->leading_membar();
-        assert(support_IRIW_for_not_multiple_copy_atomic_cpu || leading->Opcode() == Op_MemBarRelease, "incorrect membar");
+        assert(SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU || leading->Opcode() == Op_MemBarRelease, "incorrect membar");
         assert(leading->as_MemBar()->leading_load_store(), "incorrect membar pair");
         assert(leading->as_MemBar()->trailing_membar() == trailing, "incorrect membar pair");
 #endif
diff --git a/src/hotspot/share/opto/parse1.cpp b/src/hotspot/share/opto/parse1.cpp
--- a/src/hotspot/share/opto/parse1.cpp
+++ b/src/hotspot/share/opto/parse1.cpp
@@ -980,7 +980,7 @@
   //    to complete, we force all writes to complete.
   //
   // 2. On PPC64, also add MemBarRelease for constructors which write
-  //    volatile fields. As support_IRIW_for_not_multiple_copy_atomic_cpu
+  //    volatile fields. As SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU
   //    is set on PPC64, no sync instruction is issued after volatile
   //    stores. We want to guarantee the same behavior as on platforms
   //    with total store order, although this is not required by the Java
@@ -996,8 +996,12 @@
   //
   if (method()->is_initializer() &&
         (wrote_final() ||
-           PPC64_ONLY(wrote_volatile() ||)
-           (AlwaysSafeConstructors && wrote_fields()))) {
+           (AlwaysSafeConstructors && wrote_fields()) ||
+           (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU &&
+            IRIW_WITH_RELEASE_VOLATILE_IN_CONSTRUCTOR &&
+            wrote_volatile())
+        )
+     ) {
     _exits.insert_mem_bar(Op_MemBarRelease, alloc_with_final());
 
     // If Memory barrier is created for final fields write
diff --git a/src/hotspot/share/utilities/globalDefinitions.hpp b/src/hotspot/share/utilities/globalDefinitions.hpp
--- a/src/hotspot/share/utilities/globalDefinitions.hpp
+++ b/src/hotspot/share/utilities/globalDefinitions.hpp
@@ -481,10 +481,10 @@
 // assure their ordering, instead of after volatile stores.
 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
-#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
-const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
-#else
-const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
+#ifdef CPU_MULTI_COPY_ATOMIC
+// Not needed.
+#define SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU false
+#define IRIW_WITH_RELEASE_VOLATILE_IN_CONSTRUCTOR false
 #endif
 
 // The expected size in bytes of a cache line, used to pad data structures.