src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp

rev 56016 : 8229422: Taskqueue: Outdated selection of weak memory model platforms
Reviewed-by:

@@ -32,10 +32,17 @@
 // 32-bit integer argument values are extended to 64 bits.
 const bool CCallingConventionRequiresIntsAsLongs = false;
 
 #define SUPPORTS_NATIVE_CX8
 
+// TODO: aarch64 is CPU_MULTI_COPY_ATOMIC
+// See: "Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8"
+// Should we define it here and remove the following lines?
+#define SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU false
+// Only used when previous define is true.
+#define IRIW_WITH_RELEASE_VOLATILE_IN_CONSTRUCTOR true
+
 // According to the ARMv8 ARM, "Concurrent modification and execution
 // of instructions can lead to the resulting instruction performing
 // any behavior that can be achieved by executing any sequence of
 // instructions that can be executed from the same Exception level,
 // except where the instruction before modification and the