60   ResourceMark rm;
  61   BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE);
  62   CodeBuffer cbuf(blob);
  63   MacroAssembler* masm = new MacroAssembler(&cbuf);
  64   address fast_entry = __ function_entry();
  65 
  66   Label slow;
  67 
  68   const Register Rcounter_addr = R6_ARG4,
  69                  Rcounter      = R7_ARG5,
  70                  Robj          = R8_ARG6,
  71                  Rtmp          = R9_ARG7;
  72   const int counter_offs = __ load_const_optimized(Rcounter_addr,
  73                                                    SafepointSynchronize::safepoint_counter_addr(),
  74                                                    R0, true);
  75 
  76   __ ld(Rcounter, counter_offs, Rcounter_addr);
  77   __ andi_(R0, Rcounter, 1);
  78   __ bne(CCR0, slow);
  79 
  80   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
  81     // Field may be volatile.
  82     __ fence();
  83   } else {
  84     // Using acquire to order wrt. JVMTI check and load of result.
  85     __ isync(); // order wrt. to following load(s)
  86   }
  87 
  88   if (JvmtiExport::can_post_field_access()) {
  89     // Check to see if a field access watch has been set before we
  90     // take the fast path.
  91     int fac_offs = __ load_const_optimized(Rtmp, JvmtiExport::get_field_access_count_addr(),
  92                                            R0, true);
  93     __ lwa(Rtmp, fac_offs, Rtmp);
  94     __ cmpwi(CCR0, Rtmp, 0);
  95     __ bne(CCR0, slow);
  96   }
  97 
  98   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
  99   bs->try_resolve_jobject_in_native(masm, Robj, R3_ARG1, R4_ARG2, Rtmp, slow);
 100 

  60   ResourceMark rm;
  61   BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE);
  62   CodeBuffer cbuf(blob);
  63   MacroAssembler* masm = new MacroAssembler(&cbuf);
  64   address fast_entry = __ function_entry();
  65 
  66   Label slow;
  67 
  68   const Register Rcounter_addr = R6_ARG4,
  69                  Rcounter      = R7_ARG5,
  70                  Robj          = R8_ARG6,
  71                  Rtmp          = R9_ARG7;
  72   const int counter_offs = __ load_const_optimized(Rcounter_addr,
  73                                                    SafepointSynchronize::safepoint_counter_addr(),
  74                                                    R0, true);
  75 
  76   __ ld(Rcounter, counter_offs, Rcounter_addr);
  77   __ andi_(R0, Rcounter, 1);
  78   __ bne(CCR0, slow);
  79 
  80   if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
  81     // Field may be volatile.
  82     __ fence();
  83   } else {
  84     // Using acquire to order wrt. JVMTI check and load of result.
  85     __ isync(); // order wrt. to following load(s)
  86   }
  87 
  88   if (JvmtiExport::can_post_field_access()) {
  89     // Check to see if a field access watch has been set before we
  90     // take the fast path.
  91     int fac_offs = __ load_const_optimized(Rtmp, JvmtiExport::get_field_access_count_addr(),
  92                                            R0, true);
  93     __ lwa(Rtmp, fac_offs, Rtmp);
  94     __ cmpwi(CCR0, Rtmp, 0);
  95     __ bne(CCR0, slow);
  96   }
  97 
  98   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
  99   bs->try_resolve_jobject_in_native(masm, Robj, R3_ARG1, R4_ARG2, Rtmp, slow);
 100