< prev index next >
src/hotspot/cpu/ppc/ppc.ad
Print this page
rev 56016 : 8229422: Taskqueue: Outdated selection of weak memory model platforms
Reviewed-by:
*** 7946,7956 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 7946,7956 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 7966,7976 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 7966,7976 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 7986,7996 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 7986,7996 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8006,8016 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8006,8016 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8025,8035 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8025,8035 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8044,8054 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8044,8054 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8063,8073 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, NULL, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8063,8073 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, NULL, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8082,8092 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, NULL, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8082,8092 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
$res$$Register, NULL, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8132,8142 ****
format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
! support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
--- 8132,8142 ----
format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
! SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
*** 8147,8157 ****
format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
! support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
--- 8147,8157 ----
format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
! SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
*** 8192,8202 ****
format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
! support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
--- 8192,8202 ----
format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
! SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
*** 8207,8217 ****
format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
! support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
--- 8207,8217 ----
format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
! SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
*** 8239,8249 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
// Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
// value is never passed to caller.
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
! support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
--- 8239,8249 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
// Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
// value is never passed to caller.
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
! SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
*** 8271,8281 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
// Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
// value is never passed to caller.
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
! support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
--- 8271,8281 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
// Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
// value is never passed to caller.
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
! SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
*** 8304,8314 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
// Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
// value is never passed to caller.
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
! support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
--- 8304,8314 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
// Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
// value is never passed to caller.
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
! SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
*** 8336,8346 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
// Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
// value is never passed to caller.
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
! support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
--- 8336,8346 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
// Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
// value is never passed to caller.
__ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
! SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
%}
ins_pipe(pipe_class_default);
%}
*** 8385,8395 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
--- 8385,8395 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
*** 8406,8416 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
--- 8406,8416 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
*** 8457,8467 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
--- 8457,8467 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
*** 8478,8488 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
--- 8478,8488 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
*** 8514,8524 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
--- 8514,8524 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
*** 8550,8560 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
--- 8550,8560 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
*** 8586,8596 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, NULL, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
--- 8586,8596 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, NULL, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
*** 8622,8632 ****
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, NULL, true);
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
--- 8622,8632 ----
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
__ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
noreg, NULL, true);
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
// isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
__ sync();
}
*** 8642,8652 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndAddB $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8642,8652 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndAddB $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8659,8669 ****
effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
format %{ "GetAndAddB $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8659,8669 ----
effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
format %{ "GetAndAddB $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8676,8686 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndAddS $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8676,8686 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndAddS $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8693,8703 ****
effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
format %{ "GetAndAddS $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8693,8703 ----
effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
format %{ "GetAndAddS $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8709,8719 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndAddI $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddw($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8709,8719 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndAddI $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddw($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8725,8735 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndAddL $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddd($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8725,8735 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndAddL $res, $mem_ptr, $src" %}
ins_encode %{
__ getandaddd($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8742,8752 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetB $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8742,8752 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetB $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8759,8769 ****
effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
format %{ "GetAndSetB $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8759,8769 ----
effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
format %{ "GetAndSetB $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8776,8786 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetS $res, $mem_ptr, $src" %}
ins_encode %{
__ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8776,8786 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetS $res, $mem_ptr, $src" %}
ins_encode %{
__ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8793,8803 ****
effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
format %{ "GetAndSetS $res, $mem_ptr, $src" %}
ins_encode %{
__ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8793,8803 ----
effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
format %{ "GetAndSetS $res, $mem_ptr, $src" %}
ins_encode %{
__ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8809,8819 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetI $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8809,8819 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetI $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8825,8835 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetL $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8825,8835 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetL $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8841,8851 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetP $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8841,8851 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetP $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
*** 8857,8867 ****
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetN $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
MacroAssembler::cmpxchgx_hint_atomic_update());
! if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ isync();
} else {
__ sync();
}
%}
--- 8857,8867 ----
effect(TEMP_DEF res, TEMP cr0);
format %{ "GetAndSetN $res, $mem_ptr, $src" %}
ins_encode %{
__ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
MacroAssembler::cmpxchgx_hint_atomic_update());
! if (SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU) {
__ isync();
} else {
__ sync();
}
%}
< prev index next >