src/hotspot/share/utilities/globalDefinitions.hpp

rev 56016 : 8229422: Taskqueue: Outdated selection of weak memory model platforms
Reviewed-by:

*** 479,492 ****
  // To assure the IRIW property on processors that are not multiple copy
  // atomic, sync instructions must be issued between volatile reads to
  // assure their ordering, instead of after volatile stores.
  // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
  // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
! #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
! const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
! #else
! const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
  #endif
  
  // The expected size in bytes of a cache line, used to pad data structures.
  #ifndef DEFAULT_CACHE_LINE_SIZE
    #define DEFAULT_CACHE_LINE_SIZE 64
--- 479,492 ----
  // To assure the IRIW property on processors that are not multiple copy
  // atomic, sync instructions must be issued between volatile reads to
  // assure their ordering, instead of after volatile stores.
  // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
  // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
! #ifdef CPU_MULTI_COPY_ATOMIC
! // Not needed.
! #define SUPPORT_IRIW_FOR_NOT_MULTI_COPY_ATOMIC_CPU false
! #define IRIW_WITH_RELEASE_VOLATILE_IN_CONSTRUCTOR false
  #endif
  
  // The expected size in bytes of a cache line, used to pad data structures.
  #ifndef DEFAULT_CACHE_LINE_SIZE
    #define DEFAULT_CACHE_LINE_SIZE 64