1 //
2 // Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2017, SAP SE. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24
25 // z/Architecture Architecture Description File
26
27 // Major contributions by AS, JL, LS.
28
29 //
30 // Following information is derived from private mail communication
31 // (Oct. 2011).
32 //
33 // General branch target alignment considerations
34 //
35 // z/Architecture does not imply a general branch target alignment requirement.
36 // There are side effects and side considerations, though, which may
37 // provide some performance benefit. These are:
38 // - Align branch target on octoword (32-byte) boundary
39 // On more recent models (from z9 on), I-fetch is done on a Octoword
40 // (32 bytes at a time) basis. To avoid I-fetching unnecessary
41 // instructions, branch targets should be 32-byte aligend. If this
42 // exact alingment cannot be achieved, having the branch target in
43 // the first doubleword still provides some benefit.
44 // - Avoid branch targets at the end of cache lines (> 64 bytes distance).
45 // Sequential instruction prefetching after the branch target starts
46 // immediately after having fetched the octoword containing the
47 // branch target. When I-fetching crosses a cache line, there may be
48 // a small stall. The worst case: the branch target (at the end of
49 // a cache line) is a L1 I-cache miss and the next line as well.
50 // Then, the entire target line must be filled first (to contine at the
51 // branch target). Only then can the next sequential line be filled.
52 // - Avoid multiple poorly predicted branches in a row.
53 //
54
55 //----------REGISTER DEFINITION BLOCK------------------------------------------
56 // This information is used by the matcher and the register allocator to
57 // describe individual registers and classes of registers within the target
58 // architecture.
59
60 register %{
61
62 //----------Architecture Description Register Definitions----------------------
63 // General Registers
64 // "reg_def" name (register save type, C convention save type,
65 // ideal register type, encoding);
66 //
67 // Register Save Types:
68 //
69 // NS = No-Save: The register allocator assumes that these registers
70 // can be used without saving upon entry to the method, &
71 // that they do not need to be saved at call sites.
72 //
73 // SOC = Save-On-Call: The register allocator assumes that these registers
74 // can be used without saving upon entry to the method,
75 // but that they must be saved at call sites.
76 //
77 // SOE = Save-On-Entry: The register allocator assumes that these registers
78 // must be saved before using them upon entry to the
79 // method, but they do not need to be saved at call sites.
80 //
81 // AS = Always-Save: The register allocator assumes that these registers
82 // must be saved before using them upon entry to the
83 // method, & that they must be saved at call sites.
84 //
85 // Ideal Register Type is used to determine how to save & restore a
86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
88 //
89 // The encoding number is the actual bit-pattern placed into the opcodes.
90
91 // z/Architecture register definitions, based on the z/Architecture Principles
92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
93 // 5th Edition, March 2001.
94 //
95 // For each 64-bit register we must define two registers: the register
96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
98 // for stores, loads, etc.
99
100 // Integer/Long Registers
101 // ----------------------------
102
103 // z/Architecture has 16 64-bit integer registers.
104
105 // types: v = volatile, nv = non-volatile, s = system
106 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1
107 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
108 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2
109 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
110 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret
111 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
112 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2
113 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
114 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3
115 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
116 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4
117 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
118 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5
119 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
120 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg());
121 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
122 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg());
123 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
124 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg());
125 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
126 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
127 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
128 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
129 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
130 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
131 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
132 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
133 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
134 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc
135 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next());
136 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP
137 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next());
138
139 // Float/Double Registers
140
141 // The rules of ADL require that double registers be defined in pairs.
142 // Each pair must be two 32-bit values, but not necessarily a pair of
143 // single float registers. In each pair, ADLC-assigned register numbers
144 // must be adjacent, with the lower number even. Finally, when the
145 // CPU stores such a register pair to memory, the word associated with
146 // the lower ADLC-assigned number must be stored to the lower address.
147
148 // z/Architecture has 16 64-bit floating-point registers. Each can store a single
149 // or double precision floating-point value.
150
151 // types: v = volatile, nv = non-volatile, s = system
152 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret
153 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
154 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg());
155 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
156 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2
157 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
158 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg());
159 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
160 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3
161 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
162 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg());
163 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
164 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg());
165 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
166 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg());
167 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
168 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg());
169 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
170 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg());
171 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
172 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
173 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
174 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
175 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
176 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
177 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
178 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
179 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
180 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
181 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
182 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
183 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
184
185
186 // Special Registers
187
188 // Condition Codes Flag Registers
189
190 // z/Architecture has the PSW (program status word) that contains
191 // (among other information) the condition code. We treat this
192 // part of the PSW as a condition register CR. It consists of 4
193 // bits. Floating point instructions influence the same condition register CR.
194
195 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile
196
197
198 // Specify priority of register selection within phases of register
199 // allocation. Highest priority is first. A useful heuristic is to
200 // give registers a low priority when they are required by machine
201 // instructions, and choose no-save registers before save-on-call, and
202 // save-on-call before save-on-entry. Registers which participate in
203 // fix calling sequences should come last. Registers which are used
204 // as pairs must fall on an even boundary.
205
206 // It's worth about 1% on SPEC geomean to get this right.
207
208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
211 // the same as Z_R3->encoding()! Furthermore, we cannot make any
212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
213 // Additionally, the function
214 // static enum RC rc_class(OptoReg::Name reg)
215 // maps a given <register>_num value to its chunk type (except for flags)
216 // and its current implementation relies on chunk0 and chunk1 having a
217 // size of 64 each.
218
219 alloc_class chunk0(
220 // chunk0 contains *all* 32 integer registers halves.
221
222 // potential SOE regs
223 Z_R13,Z_R13_H,
224 Z_R12,Z_R12_H,
225 Z_R11,Z_R11_H,
226 Z_R10,Z_R10_H,
227
228 Z_R9,Z_R9_H,
229 Z_R8,Z_R8_H,
230 Z_R7,Z_R7_H,
231
232 Z_R1,Z_R1_H,
233 Z_R0,Z_R0_H,
234
235 // argument registers
236 Z_R6,Z_R6_H,
237 Z_R5,Z_R5_H,
238 Z_R4,Z_R4_H,
239 Z_R3,Z_R3_H,
240 Z_R2,Z_R2_H,
241
242 // special registers
243 Z_R14,Z_R14_H,
244 Z_R15,Z_R15_H
245 );
246
247 alloc_class chunk1(
248 // Chunk1 contains *all* 64 floating-point registers halves.
249
250 Z_F15,Z_F15_H,
251 Z_F14,Z_F14_H,
252 Z_F13,Z_F13_H,
253 Z_F12,Z_F12_H,
254 Z_F11,Z_F11_H,
255 Z_F10,Z_F10_H,
256 Z_F9,Z_F9_H,
257 Z_F8,Z_F8_H,
258 // scratch register
259 Z_F7,Z_F7_H,
260 Z_F5,Z_F5_H,
261 Z_F3,Z_F3_H,
262 Z_F1,Z_F1_H,
263 // argument registers
264 Z_F6,Z_F6_H,
265 Z_F4,Z_F4_H,
266 Z_F2,Z_F2_H,
267 Z_F0,Z_F0_H
268 );
269
270 alloc_class chunk2(
271 Z_CR
272 );
273
274
275 //-------Architecture Description Register Classes-----------------------
276
277 // Several register classes are automatically defined based upon
278 // information in this architecture description.
279
280 // 1) reg_class inline_cache_reg (as defined in frame section)
281 // 2) reg_class compiler_method_oop_reg (as defined in frame section)
282 // 2) reg_class interpreter_method_oop_reg (as defined in frame section)
283 // 3) reg_class stack_slots(/* one chunk of stack-based "registers" */)
284
285 // Integer Register Classes
286 reg_class z_int_reg(
287 /*Z_R0*/ // R0
288 /*Z_R1*/
289 Z_R2,
290 Z_R3,
291 Z_R4,
292 Z_R5,
293 Z_R6,
294 Z_R7,
295 /*Z_R8,*/ // Z_thread
296 Z_R9,
297 Z_R10,
298 Z_R11,
299 Z_R12,
300 Z_R13
301 /*Z_R14*/ // return_pc
302 /*Z_R15*/ // SP
303 );
304
305 reg_class z_no_odd_int_reg(
306 /*Z_R0*/ // R0
307 /*Z_R1*/
308 Z_R2,
309 Z_R3,
310 Z_R4,
311 /*Z_R5,*/ // odd part of fix register pair
312 Z_R6,
313 Z_R7,
314 /*Z_R8,*/ // Z_thread
315 Z_R9,
316 Z_R10,
317 Z_R11,
318 Z_R12,
319 Z_R13
320 /*Z_R14*/ // return_pc
321 /*Z_R15*/ // SP
322 );
323
324 reg_class z_no_arg_int_reg(
325 /*Z_R0*/ // R0
326 /*Z_R1*/ // scratch
327 /*Z_R2*/
328 /*Z_R3*/
329 /*Z_R4*/
330 /*Z_R5*/
331 /*Z_R6*/
332 Z_R7,
333 /*Z_R8*/ // Z_thread
334 Z_R9,
335 Z_R10,
336 Z_R11,
337 Z_R12,
338 Z_R13
339 /*Z_R14*/ // return_pc
340 /*Z_R15*/ // SP
341 );
342
343 reg_class z_rarg1_int_reg(Z_R2);
344 reg_class z_rarg2_int_reg(Z_R3);
345 reg_class z_rarg3_int_reg(Z_R4);
346 reg_class z_rarg4_int_reg(Z_R5);
347 reg_class z_rarg5_int_reg(Z_R6);
348
349 // Pointer Register Classes
350
351 // 64-bit build means 64-bit pointers means hi/lo pairs.
352
353 reg_class z_rarg5_ptrN_reg(Z_R6);
354
355 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
356 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
357 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
358 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
359 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
360 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
361
362 reg_class z_ptr_reg(
363 /*Z_R0_H,Z_R0*/ // R0
364 /*Z_R1_H,Z_R1*/
365 Z_R2_H,Z_R2,
366 Z_R3_H,Z_R3,
367 Z_R4_H,Z_R4,
368 Z_R5_H,Z_R5,
369 Z_R6_H,Z_R6,
370 Z_R7_H,Z_R7,
371 /*Z_R8_H,Z_R8,*/ // Z_thread
372 Z_R9_H,Z_R9,
373 Z_R10_H,Z_R10,
374 Z_R11_H,Z_R11,
375 Z_R12_H,Z_R12,
376 Z_R13_H,Z_R13
377 /*Z_R14_H,Z_R14*/ // return_pc
378 /*Z_R15_H,Z_R15*/ // SP
379 );
380
381 reg_class z_lock_ptr_reg(
382 /*Z_R0_H,Z_R0*/ // R0
383 /*Z_R1_H,Z_R1*/
384 Z_R2_H,Z_R2,
385 Z_R3_H,Z_R3,
386 Z_R4_H,Z_R4,
387 /*Z_R5_H,Z_R5,*/
388 /*Z_R6_H,Z_R6,*/
389 Z_R7_H,Z_R7,
390 /*Z_R8_H,Z_R8,*/ // Z_thread
391 Z_R9_H,Z_R9,
392 Z_R10_H,Z_R10,
393 Z_R11_H,Z_R11,
394 Z_R12_H,Z_R12,
395 Z_R13_H,Z_R13
396 /*Z_R14_H,Z_R14*/ // return_pc
397 /*Z_R15_H,Z_R15*/ // SP
398 );
399
400 reg_class z_no_arg_ptr_reg(
401 /*Z_R0_H,Z_R0*/ // R0
402 /*Z_R1_H,Z_R1*/ // scratch
403 /*Z_R2_H,Z_R2*/
404 /*Z_R3_H,Z_R3*/
405 /*Z_R4_H,Z_R4*/
406 /*Z_R5_H,Z_R5*/
407 /*Z_R6_H,Z_R6*/
408 Z_R7_H, Z_R7,
409 /*Z_R8_H,Z_R8*/ // Z_thread
410 Z_R9_H,Z_R9,
411 Z_R10_H,Z_R10,
412 Z_R11_H,Z_R11,
413 Z_R12_H,Z_R12,
414 Z_R13_H,Z_R13
415 /*Z_R14_H,Z_R14*/ // return_pc
416 /*Z_R15_H,Z_R15*/ // SP
417 );
418
419 // Special class for storeP instructions, which can store SP or RPC to
420 // TLS. (Note: Do not generalize this to "any_reg". If you add
421 // another register, such as FP, to this mask, the allocator may try
422 // to put a temp in it.)
423 // Register class for memory access base registers,
424 // This class is a superset of z_ptr_reg including Z_thread.
425 reg_class z_memory_ptr_reg(
426 /*Z_R0_H,Z_R0*/ // R0
427 /*Z_R1_H,Z_R1*/
428 Z_R2_H,Z_R2,
429 Z_R3_H,Z_R3,
430 Z_R4_H,Z_R4,
431 Z_R5_H,Z_R5,
432 Z_R6_H,Z_R6,
433 Z_R7_H,Z_R7,
434 Z_R8_H,Z_R8, // Z_thread
435 Z_R9_H,Z_R9,
436 Z_R10_H,Z_R10,
437 Z_R11_H,Z_R11,
438 Z_R12_H,Z_R12,
439 Z_R13_H,Z_R13
440 /*Z_R14_H,Z_R14*/ // return_pc
441 /*Z_R15_H,Z_R15*/ // SP
442 );
443
444 // Other special pointer regs.
445 reg_class z_r1_regP(Z_R1_H,Z_R1);
446 reg_class z_r9_regP(Z_R9_H,Z_R9);
447
448
449 // Long Register Classes
450
451 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
452 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
453 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
454 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
455 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
456
457 // Longs in 1 register. Aligned adjacent hi/lo pairs.
458 reg_class z_long_reg(
459 /*Z_R0_H,Z_R0*/ // R0
460 /*Z_R1_H,Z_R1*/
461 Z_R2_H,Z_R2,
462 Z_R3_H,Z_R3,
463 Z_R4_H,Z_R4,
464 Z_R5_H,Z_R5,
465 Z_R6_H,Z_R6,
466 Z_R7_H,Z_R7,
467 /*Z_R8_H,Z_R8,*/ // Z_thread
468 Z_R9_H,Z_R9,
469 Z_R10_H,Z_R10,
470 Z_R11_H,Z_R11,
471 Z_R12_H,Z_R12,
472 Z_R13_H,Z_R13
473 /*Z_R14_H,Z_R14,*/ // return_pc
474 /*Z_R15_H,Z_R15*/ // SP
475 );
476
477
478 // Special Class for Condition Code Flags Register
479
480 reg_class z_condition_reg(
481 Z_CR
482 );
483
484 // Scratch register for late profiling. Callee saved.
485 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
486
487
488 // Float Register Classes
489
490 reg_class z_flt_reg(
491 Z_F0,
492 /*Z_F1,*/ // scratch
493 Z_F2,
494 Z_F3,
495 Z_F4,
496 Z_F5,
497 Z_F6,
498 Z_F7,
499 Z_F8,
500 Z_F9,
501 Z_F10,
502 Z_F11,
503 Z_F12,
504 Z_F13,
505 Z_F14,
506 Z_F15
507 );
508 reg_class z_rscratch1_flt_reg(Z_F1);
509
510 // Double precision float registers have virtual `high halves' that
511 // are needed by the allocator.
512 reg_class z_dbl_reg(
513 Z_F0,Z_F0_H,
514 /*Z_F1,Z_F1_H,*/ // scratch
515 Z_F2,Z_F2_H,
516 Z_F3,Z_F3_H,
517 Z_F4,Z_F4_H,
518 Z_F5,Z_F5_H,
519 Z_F6,Z_F6_H,
520 Z_F7,Z_F7_H,
521 Z_F8,Z_F8_H,
522 Z_F9,Z_F9_H,
523 Z_F10,Z_F10_H,
524 Z_F11,Z_F11_H,
525 Z_F12,Z_F12_H,
526 Z_F13,Z_F13_H,
527 Z_F14,Z_F14_H,
528 Z_F15,Z_F15_H
529 );
530 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
531
532 %}
533
534 //----------DEFINITION BLOCK---------------------------------------------------
535 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
536 // Current support includes integer values in the range [0, 0x7FFFFFFF].
537 // Format:
538 // int_def <name> (<int_value>, <expression>);
539 // Generated Code in ad_<arch>.hpp
540 // #define <name> (<expression>)
541 // // value == <int_value>
542 // Generated code in ad_<arch>.cpp adlc_verification()
543 // assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
544 //
545 definitions %{
546 // The default cost (of an ALU instruction).
547 int_def DEFAULT_COST ( 100, 100);
548 int_def DEFAULT_COST_LOW ( 80, 80);
549 int_def DEFAULT_COST_HIGH ( 120, 120);
550 int_def HUGE_COST (1000000, 1000000);
551
552 // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
553 int_def ALU_REG_COST ( 100, DEFAULT_COST);
554 int_def ALU_MEMORY_COST ( 150, 150);
555
556 // Memory refs are twice as expensive as run-of-the-mill.
557 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20);
558 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST);
559 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20);
560
561 // Branches are even more expensive.
562 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
563 int_def CALL_COST ( 300, DEFAULT_COST * 3);
564 %}
565
566 source %{
567
568 #ifdef PRODUCT
569 #define BLOCK_COMMENT(str)
570 #define BIND(label) __ bind(label)
571 #else
572 #define BLOCK_COMMENT(str) __ block_comment(str)
573 #define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":")
574 #endif
575
576 #define __ _masm.
577
578 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6
579 #define Z_DISP3_SIZE 6
580
581 // Tertiary op of a LoadP or StoreP encoding.
582 #define REGP_OP true
583
584 // Given a register encoding, produce an Integer Register object.
585 static Register reg_to_register_object(int register_encoding);
586
587 // ****************************************************************************
588
589 // REQUIRED FUNCTIONALITY
590
591 // !!!!! Special hack to get all type of calls to specify the byte offset
592 // from the start of the call to the point where the return address
593 // will point.
594
595 int MachCallStaticJavaNode::ret_addr_offset() {
596 if (_method) {
597 return 8;
598 } else {
599 return MacroAssembler::call_far_patchable_ret_addr_offset();
600 }
601 }
602
603 int MachCallDynamicJavaNode::ret_addr_offset() {
604 // Consider size of receiver type profiling (C2 tiers).
605 int profile_receiver_type_size = 0;
606
607 int vtable_index = this->_vtable_index;
608 if (vtable_index == -4) {
609 return 14 + profile_receiver_type_size;
610 } else {
611 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
612 return 36 + profile_receiver_type_size;
613 }
614 }
615
616 int MachCallRuntimeNode::ret_addr_offset() {
617 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
618 }
619
620 // Compute padding required for nodes which need alignment
621 //
622 // The addresses of the call instructions needs to be 4-byte aligned to
623 // ensure that they don't span a cache line so that they are atomically patchable.
624 // The actual calls get emitted at different offsets within the node emitters.
625 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
626
627 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
628 return (0 - current_offset) & 2;
629 }
630
631 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
632 return (6 - current_offset) & 2;
633 }
634
635 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
636 return (12 - current_offset) & 2;
637 }
638
639 int CallLeafDirectNode::compute_padding(int current_offset) const {
640 return (12 - current_offset) & 2;
641 }
642
643 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
644 return (12 - current_offset) & 2;
645 }
646
647 // Indicate if the safepoint node needs the polling page as an input.
648 // Since z/Architecture does not have absolute addressing, it does.
649 bool SafePointNode::needs_polling_address_input() {
650 return true;
651 }
652
653 void emit_nop(CodeBuffer &cbuf) {
654 MacroAssembler _masm(&cbuf);
655 __ z_nop();
656 }
657
658 // Emit an interrupt that is caught by the debugger (for debugging compiler).
659 void emit_break(CodeBuffer &cbuf) {
660 MacroAssembler _masm(&cbuf);
661 __ z_illtrap();
662 }
663
664 #if !defined(PRODUCT)
665 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
666 os->print("TA");
667 }
668 #endif
669
670 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
671 emit_break(cbuf);
672 }
673
674 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
675 return MachNode::size(ra_);
676 }
677
678 static inline void z_emit16(CodeBuffer &cbuf, long value) {
679 // 32bit instructions may become sign extended.
680 assert(value >= 0, "unintended sign extension (int->long)");
681 assert(value < (1L << 16), "instruction too large");
682 *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value;
683 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short));
684 }
685
686 static inline void z_emit32(CodeBuffer &cbuf, long value) {
687 // 32bit instructions may become sign extended.
688 assert(value < (1L << 32), "instruction too large");
689 *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value;
690 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int));
691 }
692
693 static inline void z_emit48(CodeBuffer &cbuf, long value) {
694 // 32bit instructions may become sign extended.
695 assert(value >= 0, "unintended sign extension (int->long)");
696 assert(value < (1L << 48), "instruction too large");
697 value = value<<16;
698 memcpy(cbuf.insts_end(), (unsigned char*)&value, 6);
699 cbuf.set_insts_end(cbuf.insts_end() + 6);
700 }
701
702 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
703 if (value < 0) {
704 // There obviously has been an unintended sign extension (int->long). Revert it.
705 value = (long)((unsigned long)((unsigned int)value));
706 }
707
708 if (value < (1L << 16)) { // 2-byte instruction
709 z_emit16(cbuf, value);
710 return 2;
711 }
712
713 if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
714 z_emit32(cbuf, value);
715 return 4;
716 }
717
718 // 6-byte instruction, probably unaligned store.
719 z_emit48(cbuf, value);
720 return 6;
721 }
722
723 // Check effective address (at runtime) for required alignment.
724 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
725 MacroAssembler _masm(&cbuf);
726
727 __ z_lay(Z_R0, disp, index, base);
728 __ z_nill(Z_R0, alignment-1);
729 __ z_brc(Assembler::bcondEqual, +3);
730 __ z_illtrap();
731 }
732
733 int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype,
734 PhaseRegAlloc* ra_, bool is_native_call = false) {
735 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
736 address old_mark = __ inst_mark();
737 unsigned int start_off = __ offset();
738
739 if (is_native_call) {
740 ShouldNotReachHere();
741 }
742
743 if (rtype == relocInfo::runtime_call_w_cp_type) {
744 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
745 address call_addr = __ call_c_opt((address)entry_point);
746 if (call_addr == NULL) {
747 Compile::current()->env()->record_out_of_memory_failure();
748 return -1;
749 }
750 } else {
751 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
752 rtype == relocInfo::static_call_type, "unexpected rtype");
753 __ relocate(rtype);
754 // BRASL must be prepended with a nop to identify it in the instruction stream.
755 __ z_nop();
756 __ z_brasl(Z_R14, (address)entry_point);
757 }
758
759 unsigned int ret_off = __ offset();
760
761 return (ret_off - start_off);
762 }
763
764 static int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
765 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
766 address old_mark = __ inst_mark();
767 unsigned int start_off = __ offset();
768
769 relocInfo::relocType rtype = rspec.type();
770 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
771 "unexpected rtype");
772
773 __ relocate(rspec);
774 __ z_nop();
775 __ z_brasl(Z_R14, (address)entry_point);
776
777 unsigned int ret_off = __ offset();
778
779 return (ret_off - start_off);
780 }
781
782 //=============================================================================
783
784 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
785 int Compile::ConstantTable::calculate_table_base_offset() const {
786 return 0; // absolute addressing, no offset
787 }
788
789 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
790 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
791 ShouldNotReachHere();
792 }
793
794 // Even with PC-relative TOC addressing, we still need this node.
795 // Float loads/stores do not support PC-relative addresses.
796 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
797 MacroAssembler _masm(&cbuf);
798 Register Rtoc = as_Register(ra_->get_encode(this));
799 __ load_toc(Rtoc);
800 }
801
802 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
803 // PCrelative TOC access.
804 return 6; // sizeof(LARL)
805 }
806
807 #if !defined(PRODUCT)
808 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
809 Register r = as_Register(ra_->get_encode(this));
810 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
811 }
812 #endif
813
814 //=============================================================================
815
816 #if !defined(PRODUCT)
817 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
818 Compile* C = ra_->C;
819 st->print_cr("--- MachPrologNode ---");
820 st->print("\t");
821 for (int i = 0; i < OptoPrologueNops; i++) {
822 st->print_cr("NOP"); st->print("\t");
823 }
824
825 if (VerifyThread) {
826 st->print_cr("Verify_Thread");
827 st->print("\t");
828 }
829
830 long framesize = C->frame_size_in_bytes();
831 int bangsize = C->bang_size_in_bytes();
832
833 // Calls to C2R adapters often do not accept exceptional returns.
834 // We require that their callers must bang for them. But be
835 // careful, because some VM calls (such as call site linkage) can
836 // use several kilobytes of stack. But the stack safety zone should
837 // account for that. See bugs 4446381, 4468289, 4497237.
838 if (C->need_stack_bang(bangsize) && UseStackBanging) {
839 st->print_cr("# stack bang"); st->print("\t");
840 }
841 st->print_cr("push_frame %d", (int)-framesize);
842 st->print("\t");
843 }
844 #endif
845
846 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
847 Compile* C = ra_->C;
848 MacroAssembler _masm(&cbuf);
849
850 __ verify_thread();
851
852 size_t framesize = C->frame_size_in_bytes();
853 size_t bangsize = C->bang_size_in_bytes();
854
855 assert(framesize % wordSize == 0, "must preserve wordSize alignment");
856
857 // Calls to C2R adapters often do not accept exceptional returns.
858 // We require that their callers must bang for them. But be
859 // careful, because some VM calls (such as call site linkage) can
860 // use several kilobytes of stack. But the stack safety zone should
861 // account for that. See bugs 4446381, 4468289, 4497237.
862 if (C->need_stack_bang(bangsize) && UseStackBanging) {
863 __ generate_stack_overflow_check(bangsize);
864 }
865
866 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
867 __ save_return_pc();
868
869 // The z/Architecture abi is already accounted for in `framesize' via the
870 // 'out_preserve_stack_slots' declaration.
871 __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
872
873 if (C->has_mach_constant_base_node()) {
874 // NOTE: We set the table base offset here because users might be
875 // emitted before MachConstantBaseNode.
876 Compile::ConstantTable& constant_table = C->constant_table();
877 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
878 }
879
880 #ifndef PRODUCT
881 ciMethod *currMethod = C->method();
882 if (currMethod && currMethod->has_option("crashOnEntry")) {
883 __ z_illtrap();
884 }
885 #endif
886 }
887
888 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
889 // Variable size. Determine dynamically.
890 return MachNode::size(ra_);
891 }
892
893 int MachPrologNode::reloc() const {
894 // Return number of relocatable values contained in this instruction.
895 return 1; // One reloc entry for load_const(toc).
896 }
897
898 //=============================================================================
899
900 #if !defined(PRODUCT)
901 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
902 os->print_cr("epilog");
903 os->print("\t");
904 if (do_polling() && ra_->C->is_method_compilation()) {
905 os->print_cr("load_from_polling_page Z_R1_scratch");
906 os->print("\t");
907 }
908 }
909 #endif
910
911 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
912 MacroAssembler _masm(&cbuf);
913 Compile* C = ra_->C;
914
915 #ifndef PRODUCT
916 ciMethod *currMethod = C->method();
917 if (currMethod && currMethod->has_option("crashOnExit")) {
918 __ z_illtrap();
919 }
920 #endif
921
922 __ verify_thread();
923
924 // If this does safepoint polling, then do it here.
925 bool need_polling = do_polling() && C->is_method_compilation();
926
927 // Pop frame, restore return_pc, and all stuff needed by interpreter.
928 int frame_size_in_bytes = Assembler::align((C->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
929 __ pop_frame_restore_retPC(frame_size_in_bytes);
930
931 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
932 __ reserved_stack_check(Z_R14);
933 }
934
935 // Touch the polling page.
936 if (need_polling) {
937 if (SafepointMechanism::uses_thread_local_poll()) {
938 __ z_lg(Z_R1_scratch, Address(Z_thread, Thread::polling_page_offset()));
939 } else {
940 AddressLiteral pp(os::get_polling_page());
941 __ load_const_optimized(Z_R1_scratch, pp);
942 }
943 // We need to mark the code position where the load from the safepoint
944 // polling page was emitted as relocInfo::poll_return_type here.
945 __ relocate(relocInfo::poll_return_type);
946 __ load_from_polling_page(Z_R1_scratch);
947 }
948 }
949
950 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
951 // Variable size. determine dynamically.
952 return MachNode::size(ra_);
953 }
954
955 int MachEpilogNode::reloc() const {
956 // Return number of relocatable values contained in this instruction.
957 return 1; // One for load_from_polling_page.
958 }
959
960 const Pipeline * MachEpilogNode::pipeline() const {
961 return MachNode::pipeline_class();
962 }
963
964 int MachEpilogNode::safepoint_offset() const {
965 assert(do_polling(), "no return for this epilog node");
966 return 0;
967 }
968
969 //=============================================================================
970
971 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack.
972 enum RC { rc_bad, rc_int, rc_float, rc_stack };
973
974 static enum RC rc_class(OptoReg::Name reg) {
975 // Return the register class for the given register. The given register
976 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
977 // enumeration in adGlobals_s390.hpp.
978
979 if (reg == OptoReg::Bad) {
980 return rc_bad;
981 }
982
983 // We have 32 integer register halves, starting at index 0.
984 if (reg < 32) {
985 return rc_int;
986 }
987
988 // We have 32 floating-point register halves, starting at index 32.
989 if (reg < 32+32) {
990 return rc_float;
991 }
992
993 // Between float regs & stack are the flags regs.
994 assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
995 return rc_stack;
996 }
997
998 // Returns size as obtained from z_emit_instr.
999 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode,
1000 int reg, int offset, bool do_print, outputStream *os) {
1001
1002 if (cbuf) {
1003 if (opcode > (1L<<32)) {
1004 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
1005 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
1006 } else {
1007 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
1008 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1009 }
1010 }
1011
1012 #if !defined(PRODUCT)
1013 if (do_print) {
1014 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1015 }
1016 #endif
1017 return (opcode > (1L << 32)) ? 6 : 4;
1018 }
1019
1020 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1021 if (cbuf) {
1022 MacroAssembler _masm(cbuf);
1023 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1024 }
1025
1026 #if !defined(PRODUCT)
1027 else if (do_print) {
1028 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1029 }
1030 #endif
1031
1032 return 6;
1033 }
1034
1035 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1036 // Get registers to move.
1037 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1038 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1039 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1040 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1041
1042 enum RC src_hi_rc = rc_class(src_hi);
1043 enum RC src_lo_rc = rc_class(src_lo);
1044 enum RC dst_hi_rc = rc_class(dst_hi);
1045 enum RC dst_lo_rc = rc_class(dst_lo);
1046
1047 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1048 bool is64 = (src_hi_rc != rc_bad);
1049 assert(!is64 ||
1050 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1051 "expected aligned-adjacent pairs");
1052
1053 // Generate spill code!
1054
1055 if (src_lo == dst_lo && src_hi == dst_hi) {
1056 return 0; // Self copy, no move.
1057 }
1058
1059 int src_offset = ra_->reg2offset(src_lo);
1060 int dst_offset = ra_->reg2offset(dst_lo);
1061 bool print = !do_size;
1062 bool src12 = Immediate::is_uimm12(src_offset);
1063 bool dst12 = Immediate::is_uimm12(dst_offset);
1064
1065 const char *mnemo = NULL;
1066 unsigned long opc = 0;
1067
1068 // Memory->Memory Spill. Use Z_R0 to hold the value.
1069 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1070
1071 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1072 "expected same type of move for high parts");
1073
1074 if (src12 && dst12) {
1075 return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1076 }
1077
1078 int r0 = Z_R0_num;
1079 if (is64) {
1080 return z_ld_st_helper(cbuf, "LG ", LG_ZOPC, r0, src_offset, print, os) +
1081 z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1082 }
1083
1084 return z_ld_st_helper(cbuf, "LY ", LY_ZOPC, r0, src_offset, print, os) +
1085 z_ld_st_helper(cbuf, "STY ", STY_ZOPC, r0, dst_offset, print, os);
1086 }
1087
1088 // Check for float->int copy. Requires a trip through memory.
1089 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1090 Unimplemented(); // Unsafe, do not remove!
1091 }
1092
1093 // Check for integer reg-reg copy.
1094 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1095 if (cbuf) {
1096 MacroAssembler _masm(cbuf);
1097 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1098 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1099 __ z_lgr(Rdst, Rsrc);
1100 return 4;
1101 }
1102 #if !defined(PRODUCT)
1103 // else
1104 if (print) {
1105 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1106 }
1107 #endif
1108 return 4;
1109 }
1110
1111 // Check for integer store.
1112 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1113 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1114 "expected same type of move for high parts");
1115
1116 if (is64) {
1117 return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1118 }
1119
1120 // else
1121 mnemo = dst12 ? "ST " : "STY ";
1122 opc = dst12 ? ST_ZOPC : STY_ZOPC;
1123
1124 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1125 }
1126
1127 // Check for integer load
1128 // Always load cOops zero-extended. That doesn't hurt int loads.
1129 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1130
1131 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1132 "expected same type of move for high parts");
1133
1134 mnemo = is64 ? "LG " : "LLGF";
1135 opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1136
1137 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1138 }
1139
1140 // Check for float reg-reg copy.
1141 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1142 if (cbuf) {
1143 MacroAssembler _masm(cbuf);
1144 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1145 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1146 __ z_ldr(Rdst, Rsrc);
1147 return 2;
1148 }
1149 #if !defined(PRODUCT)
1150 // else
1151 if (print) {
1152 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1153 }
1154 #endif
1155 return 2;
1156 }
1157
1158 // Check for float store.
1159 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1160 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1161 "expected same type of move for high parts");
1162
1163 if (is64) {
1164 mnemo = dst12 ? "STD " : "STDY ";
1165 opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1166 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1167 }
1168 // else
1169
1170 mnemo = dst12 ? "STE " : "STEY ";
1171 opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1172 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1173 }
1174
1175 // Check for float load.
1176 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1177 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1178 "expected same type of move for high parts");
1179
1180 if (is64) {
1181 mnemo = src12 ? "LD " : "LDY ";
1182 opc = src12 ? LD_ZOPC : LDY_ZOPC;
1183 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1184 }
1185 // else
1186
1187 mnemo = src12 ? "LE " : "LEY ";
1188 opc = src12 ? LE_ZOPC : LEY_ZOPC;
1189 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1190 }
1191
1192 // --------------------------------------------------------------------
1193 // Check for hi bits still needing moving. Only happens for misaligned
1194 // arguments to native calls.
1195 if (src_hi == dst_hi) {
1196 return 0; // Self copy, no move.
1197 }
1198
1199 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1200 Unimplemented(); // Unsafe, do not remove!
1201
1202 return 0; // never reached, but make the compiler shut up!
1203 }
1204
1205 #if !defined(PRODUCT)
1206 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1207 if (ra_ && ra_->node_regs_max_index() > 0) {
1208 implementation(NULL, ra_, false, os);
1209 } else {
1210 if (req() == 2 && in(1)) {
1211 os->print("N%d = N%d\n", _idx, in(1)->_idx);
1212 } else {
1213 const char *c = "(";
1214 os->print("N%d = ", _idx);
1215 for (uint i = 1; i < req(); ++i) {
1216 os->print("%sN%d", c, in(i)->_idx);
1217 c = ", ";
1218 }
1219 os->print(")");
1220 }
1221 }
1222 }
1223 #endif
1224
1225 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1226 implementation(&cbuf, ra_, false, NULL);
1227 }
1228
1229 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1230 return implementation(NULL, ra_, true, NULL);
1231 }
1232
1233 //=============================================================================
1234
1235 #if !defined(PRODUCT)
1236 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1237 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1238 }
1239 #endif
1240
1241 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const {
1242 MacroAssembler _masm(&cbuf);
1243
1244 int rem_space = 0;
1245 if (!(ra_->C->in_scratch_emit_size())) {
1246 rem_space = cbuf.insts()->remaining();
1247 if (rem_space <= _count*2 + 8) {
1248 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1249 }
1250 }
1251
1252 for (int i = 0; i < _count; i++) {
1253 __ z_nop();
1254 }
1255
1256 if (!(ra_->C->in_scratch_emit_size())) {
1257 if (rem_space <= _count*2 + 8) {
1258 int rem_space2 = cbuf.insts()->remaining();
1259 tty->print_cr(", after = %d", rem_space2);
1260 }
1261 }
1262 }
1263
1264 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1265 return 2 * _count;
1266 }
1267
1268 #if !defined(PRODUCT)
1269 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1270 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1271 if (ra_ && ra_->node_regs_max_index() > 0) {
1272 int reg = ra_->get_reg_first(this);
1273 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1274 } else {
1275 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset);
1276 }
1277 }
1278 #endif
1279
1280 // Take care of the size function, if you make changes here!
1281 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1282 MacroAssembler _masm(&cbuf);
1283
1284 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1285 int reg = ra_->get_encode(this);
1286 __ z_lay(as_Register(reg), offset, Z_SP);
1287 }
1288
1289 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1290 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1291 return 6;
1292 }
1293
1294 %} // end source section
1295
1296 //----------SOURCE BLOCK-------------------------------------------------------
1297 // This is a block of C++ code which provides values, functions, and
1298 // definitions necessary in the rest of the architecture description
1299
1300 source_hpp %{
1301
1302 // Header information of the source block.
1303 // Method declarations/definitions which are used outside
1304 // the ad-scope can conveniently be defined here.
1305 //
1306 // To keep related declarations/definitions/uses close together,
1307 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1308
1309 //--------------------------------------------------------------
1310 // Used for optimization in Compile::Shorten_branches
1311 //--------------------------------------------------------------
1312
1313 class CallStubImpl {
1314 public:
1315
1316 // call trampolines
1317 // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1318 static uint size_call_trampoline() {
1319 return 0; // no call trampolines on this platform
1320 }
1321
1322 // call trampolines
1323 // Number of relocations needed by a call trampoline stub.
1324 static uint reloc_call_trampoline() {
1325 return 0; // No call trampolines on this platform.
1326 }
1327 };
1328
1329 %} // end source_hpp section
1330
1331 source %{
1332
1333 #if !defined(PRODUCT)
1334 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1335 os->print_cr("---- MachUEPNode ----");
1336 os->print_cr("\tTA");
1337 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1338 os->print_cr("\tBR(Z_R1)");
1339 os->print_cr("\tTA # pad with illtraps");
1340 os->print_cr("\t...");
1341 os->print_cr("\tTA");
1342 os->print_cr("\tLTGR Z_R2, Z_R2");
1343 os->print_cr("\tBRU ic_miss");
1344 }
1345 #endif
1346
1347 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1348 MacroAssembler _masm(&cbuf);
1349 const int ic_miss_offset = 2;
1350
1351 // Inline_cache contains a klass.
1352 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1353 // ARG1 is the receiver oop.
1354 Register R2_receiver = Z_ARG1;
1355 int klass_offset = oopDesc::klass_offset_in_bytes();
1356 AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
1357 Register R1_ic_miss_stub_addr = Z_R1_scratch;
1358
1359 // Null check of receiver.
1360 // This is the null check of the receiver that actually should be
1361 // done in the caller. It's here because in case of implicit null
1362 // checks we get it for free.
1363 assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()),
1364 "second word in oop should not require explicit null check.");
1365 if (!ImplicitNullChecks) {
1366 Label valid;
1367 if (VM_Version::has_CompareBranch()) {
1368 __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid);
1369 } else {
1370 __ z_ltgr(R2_receiver, R2_receiver);
1371 __ z_bre(valid);
1372 }
1373 // The ic_miss_stub will handle the null pointer exception.
1374 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1375 __ z_br(R1_ic_miss_stub_addr);
1376 __ bind(valid);
1377 }
1378
1379 // Check whether this method is the proper implementation for the class of
1380 // the receiver (ic miss check).
1381 {
1382 Label valid;
1383 // Compare cached class against klass from receiver.
1384 // This also does an implicit null check!
1385 __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false);
1386 __ z_bre(valid);
1387 // The inline cache points to the wrong method. Call the
1388 // ic_miss_stub to find the proper method.
1389 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1390 __ z_br(R1_ic_miss_stub_addr);
1391 __ bind(valid);
1392 }
1393
1394 }
1395
1396 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1397 // Determine size dynamically.
1398 return MachNode::size(ra_);
1399 }
1400
1401 //=============================================================================
1402
1403 %} // interrupt source section
1404
1405 source_hpp %{ // Header information of the source block.
1406
1407 class HandlerImpl {
1408 public:
1409
1410 static int emit_exception_handler(CodeBuffer &cbuf);
1411 static int emit_deopt_handler(CodeBuffer& cbuf);
1412
1413 static uint size_exception_handler() {
1414 return NativeJump::max_instruction_size();
1415 }
1416
1417 static uint size_deopt_handler() {
1418 return NativeCall::max_instruction_size();
1419 }
1420 };
1421
1422 %} // end source_hpp section
1423
1424 source %{
1425
1426 // This exception handler code snippet is placed after the method's
1427 // code. It is the return point if an exception occurred. it jumps to
1428 // the exception blob.
1429 //
1430 // If the method gets deoptimized, the method and this code snippet
1431 // get patched.
1432 //
1433 // 1) Trampoline code gets patched into the end of this exception
1434 // handler. the trampoline code jumps to the deoptimization blob.
1435 //
1436 // 2) The return address in the method's code will get patched such
1437 // that it jumps to the trampoline.
1438 //
1439 // 3) The handler will get patched such that it does not jump to the
1440 // exception blob, but to an entry in the deoptimization blob being
1441 // aware of the exception.
1442 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1443 Register temp_reg = Z_R1;
1444 MacroAssembler _masm(&cbuf);
1445
1446 address base = __ start_a_stub(size_exception_handler());
1447 if (base == NULL) {
1448 return 0; // CodeBuffer::expand failed
1449 }
1450
1451 int offset = __ offset();
1452 // Use unconditional pc-relative jump with 32-bit range here.
1453 __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin());
1454 __ z_br(temp_reg);
1455
1456 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1457
1458 __ end_a_stub();
1459
1460 return offset;
1461 }
1462
1463 // Emit deopt handler code.
1464 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1465 MacroAssembler _masm(&cbuf);
1466 address base = __ start_a_stub(size_deopt_handler());
1467
1468 if (base == NULL) {
1469 return 0; // CodeBuffer::expand failed
1470 }
1471
1472 int offset = __ offset();
1473
1474 // Size_deopt_handler() must be exact on zarch, so for simplicity
1475 // we do not use load_const_opt here.
1476 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1477 __ call(Z_R1);
1478 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1479
1480 __ end_a_stub();
1481 return offset;
1482 }
1483
1484 //=============================================================================
1485
1486
1487 // Given a register encoding, produce an Integer Register object.
1488 static Register reg_to_register_object(int register_encoding) {
1489 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1490 return as_Register(register_encoding);
1491 }
1492
1493 const bool Matcher::match_rule_supported(int opcode) {
1494 if (!has_match_rule(opcode)) return false;
1495
1496 switch (opcode) {
1497 case Op_CountLeadingZerosI:
1498 case Op_CountLeadingZerosL:
1499 case Op_CountTrailingZerosI:
1500 case Op_CountTrailingZerosL:
1501 // Implementation requires FLOGR instruction, which is available since z9.
1502 return true;
1503
1504 case Op_ReverseBytesI:
1505 case Op_ReverseBytesL:
1506 return UseByteReverseInstruction;
1507
1508 // PopCount supported by H/W from z/Architecture G5 (z196) on.
1509 case Op_PopCountI:
1510 case Op_PopCountL:
1511 return UsePopCountInstruction && VM_Version::has_PopCount();
1512
1513 case Op_StrComp:
1514 return SpecialStringCompareTo;
1515 case Op_StrEquals:
1516 return SpecialStringEquals;
1517 case Op_StrIndexOf:
1518 case Op_StrIndexOfChar:
1519 return SpecialStringIndexOf;
1520
1521 case Op_GetAndAddI:
1522 case Op_GetAndAddL:
1523 return true;
1524 // return VM_Version::has_AtomicMemWithImmALUOps();
1525 case Op_GetAndSetI:
1526 case Op_GetAndSetL:
1527 case Op_GetAndSetP:
1528 case Op_GetAndSetN:
1529 return true; // General CAS implementation, always available.
1530
1531 default:
1532 return true; // Per default match rules are supported.
1533 // BUT: make sure match rule is not disabled by a false predicate!
1534 }
1535
1536 return true; // Per default match rules are supported.
1537 // BUT: make sure match rule is not disabled by a false predicate!
1538 }
1539
1540 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1541 // TODO
1542 // Identify extra cases that we might want to provide match rules for
1543 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen.
1544 bool ret_value = match_rule_supported(opcode);
1545 // Add rules here.
1546
1547 return ret_value; // Per default match rules are supported.
1548 }
1549
1550 int Matcher::regnum_to_fpu_offset(int regnum) {
1551 ShouldNotReachHere();
1552 return regnum - 32; // The FP registers are in the second chunk.
1553 }
1554
1555 const bool Matcher::has_predicated_vectors(void) {
1556 return false;
1557 }
1558
1559 const int Matcher::float_pressure(int default_pressure_threshold) {
1560 return default_pressure_threshold;
1561 }
1562
1563 const bool Matcher::convL2FSupported(void) {
1564 return true; // False means that conversion is done by runtime call.
1565 }
1566
1567 //----------SUPERWORD HELPERS----------------------------------------
1568
1569 // Vector width in bytes.
1570 const int Matcher::vector_width_in_bytes(BasicType bt) {
1571 assert(MaxVectorSize == 8, "");
1572 return 8;
1573 }
1574
1575 // Vector ideal reg.
1576 const uint Matcher::vector_ideal_reg(int size) {
1577 assert(MaxVectorSize == 8 && size == 8, "");
1578 return Op_RegL;
1579 }
1580
1581 // Limits on vector size (number of elements) loaded into vector.
1582 const int Matcher::max_vector_size(const BasicType bt) {
1583 assert(is_java_primitive(bt), "only primitive type vectors");
1584 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1585 }
1586
1587 const int Matcher::min_vector_size(const BasicType bt) {
1588 return max_vector_size(bt); // Same as max.
1589 }
1590
1591 const uint Matcher::vector_shift_count_ideal_reg(int size) {
1592 fatal("vector shift is not supported");
1593 return Node::NotAMachineReg;
1594 }
1595
1596 // z/Architecture does support misaligned store/load at minimal extra cost.
1597 const bool Matcher::misaligned_vectors_ok() {
1598 return true;
1599 }
1600
1601 // Not yet ported to z/Architecture.
1602 const bool Matcher::pass_original_key_for_aes() {
1603 return false;
1604 }
1605
1606 // RETURNS: whether this branch offset is short enough that a short
1607 // branch can be used.
1608 //
1609 // If the platform does not provide any short branch variants, then
1610 // this method should return `false' for offset 0.
1611 //
1612 // `Compile::Fill_buffer' will decide on basis of this information
1613 // whether to do the pass `Compile::Shorten_branches' at all.
1614 //
1615 // And `Compile::Shorten_branches' will decide on basis of this
1616 // information whether to replace particular branch sites by short
1617 // ones.
1618 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1619 // On zarch short branches use a 16 bit signed immediate that
1620 // is the pc-relative offset in halfword (= 2 bytes) units.
1621 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1622 }
1623
1624 const bool Matcher::isSimpleConstant64(jlong value) {
1625 // Probably always true, even if a temp register is required.
1626 return true;
1627 }
1628
1629 // Should correspond to setting above
1630 const bool Matcher::init_array_count_is_in_bytes = false;
1631
1632 // Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1633 const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; }
1634
1635 // Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1636 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1637
1638 // Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)?
1639 const bool Matcher::require_postalloc_expand = false;
1640
1641 // Do we need to mask the count passed to shift instructions or does
1642 // the cpu only look at the lower 5/6 bits anyway?
1643 // 32bit shifts mask in emitter, 64bit shifts need no mask.
1644 // Constant shift counts are handled in Ideal phase.
1645 const bool Matcher::need_masked_shift_count = false;
1646
1647 // Set this as clone_shift_expressions.
1648 bool Matcher::narrow_oop_use_complex_address() {
1649 if (Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0) return true;
1650 return false;
1651 }
1652
1653 bool Matcher::narrow_klass_use_complex_address() {
1654 NOT_LP64(ShouldNotCallThis());
1655 assert(UseCompressedClassPointers, "only for compressed klass code");
1656 // TODO HS25: z port if (MatchDecodeNodes) return true;
1657 return false;
1658 }
1659
1660 bool Matcher::const_oop_prefer_decode() {
1661 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
1662 return Universe::narrow_oop_base() == NULL;
1663 }
1664
1665 bool Matcher::const_klass_prefer_decode() {
1666 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1667 return Universe::narrow_klass_base() == NULL;
1668 }
1669
1670 // Is it better to copy float constants, or load them directly from memory?
1671 // Most RISCs will have to materialize an address into a
1672 // register first, so they would do better to copy the constant from stack.
1673 const bool Matcher::rematerialize_float_constants = false;
1674
1675 // If CPU can load and store mis-aligned doubles directly then no fixup is
1676 // needed. Else we split the double into 2 integer pieces and move it
1677 // piece-by-piece. Only happens when passing doubles into C code as the
1678 // Java calling convention forces doubles to be aligned.
1679 const bool Matcher::misaligned_doubles_ok = true;
1680
1681 // Advertise here if the CPU requires explicit rounding operations
1682 // to implement the UseStrictFP mode.
1683 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1684
1685 // Do floats take an entire double register or just half?
1686 //
1687 // A float in resides in a zarch double register. When storing it by
1688 // z_std, it cannot be restored in C-code by reloading it as a double
1689 // and casting it into a float afterwards.
1690 bool Matcher::float_in_double() { return false; }
1691
1692 // Do ints take an entire long register or just half?
1693 // The relevant question is how the int is callee-saved:
1694 // the whole long is written but de-opt'ing will have to extract
1695 // the relevant 32 bits.
1696 const bool Matcher::int_in_long = true;
1697
1698 // Constants for c2c and c calling conventions.
1699
1700 const MachRegisterNumbers z_iarg_reg[5] = {
1701 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1702 };
1703
1704 const MachRegisterNumbers z_farg_reg[4] = {
1705 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1706 };
1707
1708 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1709
1710 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1711
1712 // Return whether or not this register is ever used as an argument. This
1713 // function is used on startup to build the trampoline stubs in generateOptoStub.
1714 // Registers not mentioned will be killed by the VM call in the trampoline, and
1715 // arguments in those registers not be available to the callee.
1716 bool Matcher::can_be_java_arg(int reg) {
1717 // We return true for all registers contained in z_iarg_reg[] and
1718 // z_farg_reg[] and their virtual halves.
1719 // We must include the virtual halves in order to get STDs and LDs
1720 // instead of STWs and LWs in the trampoline stubs.
1721
1722 if (reg == Z_R2_num || reg == Z_R2_H_num ||
1723 reg == Z_R3_num || reg == Z_R3_H_num ||
1724 reg == Z_R4_num || reg == Z_R4_H_num ||
1725 reg == Z_R5_num || reg == Z_R5_H_num ||
1726 reg == Z_R6_num || reg == Z_R6_H_num) {
1727 return true;
1728 }
1729
1730 if (reg == Z_F0_num || reg == Z_F0_H_num ||
1731 reg == Z_F2_num || reg == Z_F2_H_num ||
1732 reg == Z_F4_num || reg == Z_F4_H_num ||
1733 reg == Z_F6_num || reg == Z_F6_H_num) {
1734 return true;
1735 }
1736
1737 return false;
1738 }
1739
1740 bool Matcher::is_spillable_arg(int reg) {
1741 return can_be_java_arg(reg);
1742 }
1743
1744 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
1745 return false;
1746 }
1747
1748 // Register for DIVI projection of divmodI
1749 RegMask Matcher::divI_proj_mask() {
1750 return _Z_RARG4_INT_REG_mask;
1751 }
1752
1753 // Register for MODI projection of divmodI
1754 RegMask Matcher::modI_proj_mask() {
1755 return _Z_RARG3_INT_REG_mask;
1756 }
1757
1758 // Register for DIVL projection of divmodL
1759 RegMask Matcher::divL_proj_mask() {
1760 return _Z_RARG4_LONG_REG_mask;
1761 }
1762
1763 // Register for MODL projection of divmodL
1764 RegMask Matcher::modL_proj_mask() {
1765 return _Z_RARG3_LONG_REG_mask;
1766 }
1767
1768 // Copied from sparc.
1769 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1770 return RegMask();
1771 }
1772
1773 const bool Matcher::convi2l_type_required = true;
1774
1775 // Should the Matcher clone shifts on addressing modes, expecting them
1776 // to be subsumed into complex addressing expressions or compute them
1777 // into registers?
1778 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1779 return clone_base_plus_offset_address(m, mstack, address_visited);
1780 }
1781
1782 void Compile::reshape_address(AddPNode* addp) {
1783 }
1784
1785 %} // source
1786
1787 //----------ENCODING BLOCK-----------------------------------------------------
1788 // This block specifies the encoding classes used by the compiler to output
1789 // byte streams. Encoding classes are parameterized macros used by
1790 // Machine Instruction Nodes in order to generate the bit encoding of the
1791 // instruction. Operands specify their base encoding interface with the
1792 // interface keyword. There are currently supported four interfaces,
1793 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1794 // operand to generate a function which returns its register number when
1795 // queried. CONST_INTER causes an operand to generate a function which
1796 // returns the value of the constant when queried. MEMORY_INTER causes an
1797 // operand to generate four functions which return the Base Register, the
1798 // Index Register, the Scale Value, and the Offset Value of the operand when
1799 // queried. COND_INTER causes an operand to generate six functions which
1800 // return the encoding code (ie - encoding bits for the instruction)
1801 // associated with each basic boolean condition for a conditional instruction.
1802 //
1803 // Instructions specify two basic values for encoding. Again, a function
1804 // is available to check if the constant displacement is an oop. They use the
1805 // ins_encode keyword to specify their encoding classes (which must be
1806 // a sequence of enc_class names, and their parameters, specified in
1807 // the encoding block), and they use the
1808 // opcode keyword to specify, in order, their primary, secondary, and
1809 // tertiary opcode. Only the opcode sections which a particular instruction
1810 // needs for encoding need to be specified.
1811 encode %{
1812 enc_class enc_unimplemented %{
1813 MacroAssembler _masm(&cbuf);
1814 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
1815 %}
1816
1817 enc_class enc_untested %{
1818 #ifdef ASSERT
1819 MacroAssembler _masm(&cbuf);
1820 __ untested("Untested mach node encoding in AD file.");
1821 #endif
1822 %}
1823
1824 enc_class z_rrform(iRegI dst, iRegI src) %{
1825 assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
1826 assert( ($primary >> 16) == 0, "Instruction format error");
1827 z_emit16(cbuf, $primary |
1828 Assembler::reg($dst$$reg,8,16) |
1829 Assembler::reg($src$$reg,12,16));
1830 %}
1831
1832 enc_class z_rreform(iRegI dst1, iRegI src2) %{
1833 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1834 z_emit32(cbuf, $primary |
1835 Assembler::reg($dst1$$reg,24,32) |
1836 Assembler::reg($src2$$reg,28,32));
1837 %}
1838
1839 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
1840 assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1841 z_emit32(cbuf, $primary |
1842 Assembler::reg($dst1$$reg,24,32) |
1843 Assembler::reg($src2$$reg,28,32) |
1844 Assembler::reg($src3$$reg,16,32));
1845 %}
1846
1847 enc_class z_riform_signed(iRegI dst, immI16 src) %{
1848 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1849 z_emit32(cbuf, $primary |
1850 Assembler::reg($dst$$reg,8,32) |
1851 Assembler::simm16($src$$constant,16,32));
1852 %}
1853
1854 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
1855 assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1856 z_emit32(cbuf, $primary |
1857 Assembler::reg($dst$$reg,8,32) |
1858 Assembler::uimm16($src$$constant,16,32));
1859 %}
1860
1861 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
1862 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1863 z_emit48(cbuf, $primary |
1864 Assembler::reg($dst1$$reg,8,48) |
1865 Assembler::reg($src3$$reg,12,48) |
1866 Assembler::simm16($src2$$constant,16,48));
1867 %}
1868
1869 enc_class z_rilform_signed(iRegI dst, immL32 src) %{
1870 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1871 z_emit48(cbuf, $primary |
1872 Assembler::reg($dst$$reg,8,48) |
1873 Assembler::simm32($src$$constant,16,48));
1874 %}
1875
1876 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
1877 assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1878 z_emit48(cbuf, $primary |
1879 Assembler::reg($dst$$reg,8,48) |
1880 Assembler::uimm32($src$$constant,16,48));
1881 %}
1882
1883 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
1884 z_emit48(cbuf, $primary |
1885 Assembler::reg($dst$$reg,8,48) |
1886 Assembler::reg($src1$$reg,12,48) |
1887 Assembler::simm20($src2$$constant));
1888 %}
1889
1890 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
1891 z_emit48(cbuf, $primary |
1892 Assembler::reg($dst$$reg,8,48) |
1893 Assembler::reg($src$$reg,12,48) |
1894 Assembler::reg($shft$$reg,16,48) |
1895 Assembler::simm20(0));
1896 %}
1897
1898 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1899 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1900 z_emit32(cbuf, $primary |
1901 Assembler::reg($dst$$reg,8,32) |
1902 Assembler::reg($src1$$reg,12,32) |
1903 Assembler::reg($src2$$reg,16,32) |
1904 Assembler::uimm12($con$$constant,20,32));
1905 %}
1906
1907 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
1908 assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1909 z_emit32(cbuf, $primary |
1910 Assembler::reg($dst$$reg,8,32) |
1911 Assembler::reg($src$$reg,16,32) |
1912 Assembler::uimm12($con$$constant,20,32));
1913 %}
1914
1915 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1916 z_emit48(cbuf, $primary |
1917 Assembler::reg($dst$$reg,8,48) |
1918 Assembler::reg($src1$$reg,12,48) |
1919 Assembler::reg($src2$$reg,16,48) |
1920 Assembler::simm20($con$$constant));
1921 %}
1922
1923 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
1924 z_emit48(cbuf, $primary |
1925 Assembler::reg($dst$$reg,8,48) |
1926 Assembler::reg($src$$reg,16,48) |
1927 Assembler::simm20($con$$constant));
1928 %}
1929
1930 // Direct memory arithmetic.
1931 enc_class z_siyform(memoryRSY mem, immI8 src) %{
1932 int disp = $mem$$disp;
1933 Register base = reg_to_register_object($mem$$base);
1934 int con = $src$$constant;
1935
1936 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
1937 z_emit_inst(cbuf, $primary |
1938 Assembler::regz(base,16,48) |
1939 Assembler::simm20(disp) |
1940 Assembler::simm8(con,8,48));
1941 %}
1942
1943 enc_class z_silform(memoryRS mem, immI16 src) %{
1944 z_emit_inst(cbuf, $primary |
1945 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
1946 Assembler::uimm12($mem$$disp,20,48) |
1947 Assembler::simm16($src$$constant,32,48));
1948 %}
1949
1950 // Encoder for FP ALU reg/mem instructions (support only short displacements).
1951 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
1952 Register Ridx = $mem$$index$$Register;
1953 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1954 if ($primary > (1L << 32)) {
1955 z_emit_inst(cbuf, $primary |
1956 Assembler::reg($dst$$reg, 8, 48) |
1957 Assembler::uimm12($mem$$disp, 20, 48) |
1958 Assembler::reg(Ridx, 12, 48) |
1959 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1960 } else {
1961 z_emit_inst(cbuf, $primary |
1962 Assembler::reg($dst$$reg, 8, 32) |
1963 Assembler::uimm12($mem$$disp, 20, 32) |
1964 Assembler::reg(Ridx, 12, 32) |
1965 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1966 }
1967 %}
1968
1969 enc_class z_form_rt_mem(iRegI dst, memory mem) %{
1970 Register Ridx = $mem$$index$$Register;
1971 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1972 if ($primary > (1L<<32)) {
1973 z_emit_inst(cbuf, $primary |
1974 Assembler::reg($dst$$reg, 8, 48) |
1975 Assembler::simm20($mem$$disp) |
1976 Assembler::reg(Ridx, 12, 48) |
1977 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1978 } else {
1979 z_emit_inst(cbuf, $primary |
1980 Assembler::reg($dst$$reg, 8, 32) |
1981 Assembler::uimm12($mem$$disp, 20, 32) |
1982 Assembler::reg(Ridx, 12, 32) |
1983 Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1984 }
1985 %}
1986
1987 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
1988 int isize = $secondary > 1L << 32 ? 48 : 32;
1989 Register Ridx = $mem$$index$$Register;
1990 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1991
1992 if (Displacement::is_shortDisp((long)$mem$$disp)) {
1993 z_emit_inst(cbuf, $secondary |
1994 Assembler::reg($dst$$reg, 8, isize) |
1995 Assembler::uimm12($mem$$disp, 20, isize) |
1996 Assembler::reg(Ridx, 12, isize) |
1997 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
1998 } else if (Displacement::is_validDisp((long)$mem$$disp)) {
1999 z_emit_inst(cbuf, $primary |
2000 Assembler::reg($dst$$reg, 8, 48) |
2001 Assembler::simm20($mem$$disp) |
2002 Assembler::reg(Ridx, 12, 48) |
2003 Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2004 } else {
2005 MacroAssembler _masm(&cbuf);
2006 __ load_const_optimized(Z_R1_scratch, $mem$$disp);
2007 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
2008 z_emit_inst(cbuf, $secondary |
2009 Assembler::reg($dst$$reg, 8, isize) |
2010 Assembler::uimm12(0, 20, isize) |
2011 Assembler::reg(Z_R1_scratch, 12, isize) |
2012 Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2013 }
2014 %}
2015
2016 enc_class z_enc_brul(Label lbl) %{
2017 MacroAssembler _masm(&cbuf);
2018 Label* p = $lbl$$label;
2019
2020 // 'p' is `NULL' when this encoding class is used only to
2021 // determine the size of the encoded instruction.
2022 // Use a bound dummy label in that case.
2023 Label d;
2024 __ bind(d);
2025 Label& l = (NULL == p) ? d : *(p);
2026 __ z_brul(l);
2027 %}
2028
2029 enc_class z_enc_bru(Label lbl) %{
2030 MacroAssembler _masm(&cbuf);
2031 Label* p = $lbl$$label;
2032
2033 // 'p' is `NULL' when this encoding class is used only to
2034 // determine the size of the encoded instruction.
2035 // Use a bound dummy label in that case.
2036 Label d;
2037 __ bind(d);
2038 Label& l = (NULL == p) ? d : *(p);
2039 __ z_bru(l);
2040 %}
2041
2042 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2043 MacroAssembler _masm(&cbuf);
2044 Label* p = $lbl$$label;
2045
2046 // 'p' is `NULL' when this encoding class is used only to
2047 // determine the size of the encoded instruction.
2048 // Use a bound dummy label in that case.
2049 Label d;
2050 __ bind(d);
2051 Label& l = (NULL == p) ? d : *(p);
2052 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2053 %}
2054
2055 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2056 MacroAssembler _masm(&cbuf);
2057 Label* p = $lbl$$label;
2058
2059 // 'p' is `NULL' when this encoding class is used only to
2060 // determine the size of the encoded instruction.
2061 // Use a bound dummy label in that case.
2062 Label d;
2063 __ bind(d);
2064 Label& l = (NULL == p) ? d : *(p);
2065 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2066 %}
2067
2068 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2069 MacroAssembler _masm(&cbuf);
2070 Label* p = $lbl$$label;
2071
2072 // 'p' is `NULL' when this encoding class is used only to
2073 // determine the size of the encoded instruction.
2074 // Use a bound dummy label in that case.
2075 Label d;
2076 __ bind(d);
2077 Label& l = (NULL == p) ? d : *(p);
2078 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2079 unsigned long instr = $primary;
2080 if (instr == CRJ_ZOPC) {
2081 __ z_crj($src1$$Register, $src2$$Register, cc, l);
2082 } else if (instr == CLRJ_ZOPC) {
2083 __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2084 } else if (instr == CGRJ_ZOPC) {
2085 __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2086 } else {
2087 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2088 __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2089 }
2090 %}
2091
2092 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2093 MacroAssembler _masm(&cbuf);
2094 Label* p = $lbl$$label;
2095
2096 // 'p' is `NULL' when this encoding class is used only to
2097 // determine the size of the encoded instruction.
2098 // Use a bound dummy label in that case.
2099 Label d;
2100 __ bind(d);
2101 Label& l = (NULL == p) ? d : *(p);
2102
2103 unsigned long instr = $primary;
2104 if (instr == CR_ZOPC) {
2105 __ z_cr($src1$$Register, $src2$$Register);
2106 } else if (instr == CLR_ZOPC) {
2107 __ z_clr($src1$$Register, $src2$$Register);
2108 } else if (instr == CGR_ZOPC) {
2109 __ z_cgr($src1$$Register, $src2$$Register);
2110 } else {
2111 guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2112 __ z_clgr($src1$$Register, $src2$$Register);
2113 }
2114
2115 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2116 %}
2117
2118 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2119 MacroAssembler _masm(&cbuf);
2120 Label* p = $lbl$$label;
2121
2122 // 'p' is `NULL' when this encoding class is used only to
2123 // determine the size of the encoded instruction.
2124 // Use a bound dummy label in that case.
2125 Label d;
2126 __ bind(d);
2127 Label& l = (NULL == p) ? d : *(p);
2128
2129 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2130 unsigned long instr = $primary;
2131 if (instr == CIJ_ZOPC) {
2132 __ z_cij($src1$$Register, $src2$$constant, cc, l);
2133 } else if (instr == CLIJ_ZOPC) {
2134 __ z_clij($src1$$Register, $src2$$constant, cc, l);
2135 } else if (instr == CGIJ_ZOPC) {
2136 __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2137 } else {
2138 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2139 __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2140 }
2141 %}
2142
2143 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2144 MacroAssembler _masm(&cbuf);
2145 Label* p = $lbl$$label;
2146
2147 // 'p' is `NULL' when this encoding class is used only to
2148 // determine the size of the encoded instruction.
2149 // Use a bound dummy label in that case.
2150 Label d;
2151 __ bind(d);
2152 Label& l = (NULL == p) ? d : *(p);
2153
2154 unsigned long instr = $primary;
2155 if (instr == CHI_ZOPC) {
2156 __ z_chi($src1$$Register, $src2$$constant);
2157 } else if (instr == CLFI_ZOPC) {
2158 __ z_clfi($src1$$Register, $src2$$constant);
2159 } else if (instr == CGHI_ZOPC) {
2160 __ z_cghi($src1$$Register, $src2$$constant);
2161 } else {
2162 guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2163 __ z_clgfi($src1$$Register, $src2$$constant);
2164 }
2165
2166 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2167 %}
2168
2169 // Call from Java to runtime.
2170 enc_class z_enc_java_to_runtime_call(method meth) %{
2171 MacroAssembler _masm(&cbuf);
2172
2173 // Save return pc before call to the place where we need it, since
2174 // callee doesn't.
2175 unsigned int start_off = __ offset();
2176 // Compute size of "larl + stg + call_c_opt".
2177 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
2178 __ get_PC(Z_R14, size_of_code);
2179 __ save_return_pc();
2180 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2181
2182 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2183 address call_addr = __ call_c_opt((address)$meth$$method);
2184 if (call_addr == NULL) {
2185 Compile::current()->env()->record_out_of_memory_failure();
2186 return;
2187 }
2188
2189 #ifdef ASSERT
2190 // Plausibility check for size_of_code assumptions.
2191 unsigned int actual_ret_off = __ offset();
2192 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
2193 #endif
2194 %}
2195
2196 enc_class z_enc_java_static_call(method meth) %{
2197 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2198 // whom we intended to call.
2199 MacroAssembler _masm(&cbuf);
2200 int ret_offset = 0;
2201
2202 if (!_method) {
2203 ret_offset = emit_call_reloc(_masm, $meth$$method,
2204 relocInfo::runtime_call_w_cp_type, ra_);
2205 } else {
2206 int method_index = resolved_method_index(cbuf);
2207 if (_optimized_virtual) {
2208 ret_offset = emit_call_reloc(_masm, $meth$$method,
2209 opt_virtual_call_Relocation::spec(method_index));
2210 } else {
2211 ret_offset = emit_call_reloc(_masm, $meth$$method,
2212 static_call_Relocation::spec(method_index));
2213 }
2214 }
2215 assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()");
2216
2217 if (_method) { // Emit stub for static call.
2218 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2219 if (stub == NULL) {
2220 ciEnv::current()->record_failure("CodeCache is full");
2221 return;
2222 }
2223 }
2224 %}
2225
2226 // Java dynamic call
2227 enc_class z_enc_java_dynamic_call(method meth) %{
2228 MacroAssembler _masm(&cbuf);
2229 unsigned int start_off = __ offset();
2230
2231 int vtable_index = this->_vtable_index;
2232 if (vtable_index == -4) {
2233 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2234 address virtual_call_oop_addr = NULL;
2235
2236 AddressLiteral empty_ic((address) Universe::non_oop_word());
2237 virtual_call_oop_addr = __ pc();
2238 bool success = __ load_const_from_toc(ic_reg, empty_ic);
2239 if (!success) {
2240 Compile::current()->env()->record_out_of_memory_failure();
2241 return;
2242 }
2243
2244 // Call to fixup routine. Fixup routine uses ScopeDesc info
2245 // to determine who we intended to call.
2246 int method_index = resolved_method_index(cbuf);
2247 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2248 unsigned int ret_off = __ offset();
2249 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2250 ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_);
2251 assert(_method, "lazy_constant may be wrong when _method==null");
2252 } else {
2253 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2254 // Go through the vtable. Get receiver klass. Receiver already
2255 // checked for non-null. If we'll go thru a C2I adapter, the
2256 // interpreter expects method in Z_method.
2257 // Use Z_method to temporarily hold the klass oop.
2258 // Z_R1_scratch is destroyed.
2259 __ load_klass(Z_method, Z_R2);
2260
2261 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2262 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2263
2264 if (Displacement::is_validDisp(v_off) ) {
2265 // Can use load instruction with large offset.
2266 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2267 } else {
2268 // Worse case, must load offset into register.
2269 __ load_const(Z_R1_scratch, v_off);
2270 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2271 }
2272 // NOTE: for vtable dispatches, the vtable entry will never be
2273 // null. However it may very well end up in handle_wrong_method
2274 // if the method is abstract for the particular class.
2275 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2276 // Call target. Either compiled code or C2I adapter.
2277 __ z_basr(Z_R14, Z_R1_scratch);
2278 unsigned int ret_off = __ offset();
2279 }
2280 %}
2281
2282 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2283 MacroAssembler _masm(&cbuf);
2284 Register Rdst = reg_to_register_object($dst$$reg);
2285 Register Rsrc = reg_to_register_object($src$$reg);
2286
2287 // Don't emit code if operands are identical (same register).
2288 if (Rsrc != Rdst) {
2289 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2290
2291 if (VM_Version::has_LoadStoreConditional()) {
2292 __ z_locgr(Rdst, Rsrc, cc);
2293 } else {
2294 // Branch if not (cmp cr).
2295 Label done;
2296 __ z_brc(Assembler::inverse_condition(cc), done);
2297 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2298 __ bind(done);
2299 }
2300 }
2301 %}
2302
2303 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2304 MacroAssembler _masm(&cbuf);
2305 Register Rdst = reg_to_register_object($dst$$reg);
2306 int Csrc = $src$$constant;
2307 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2308 Label done;
2309 // Branch if not (cmp cr).
2310 __ z_brc(Assembler::inverse_condition(cc), done);
2311 if (Csrc == 0) {
2312 // Don't set CC.
2313 __ clear_reg(Rdst, true, false); // Use for int, long & ptr.
2314 } else {
2315 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2316 }
2317 __ bind(done);
2318 %}
2319
2320 enc_class z_enc_cctobool(iRegI res) %{
2321 MacroAssembler _masm(&cbuf);
2322 Register Rres = reg_to_register_object($res$$reg);
2323
2324 if (VM_Version::has_LoadStoreConditional()) {
2325 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2326 __ load_const_optimized(Rres, 1L); // true (succeed)
2327 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2328 } else {
2329 Label done;
2330 __ load_const_optimized(Rres, 0L); // false (failed)
2331 __ z_brne(done); // Assume true to be the common case.
2332 __ load_const_optimized(Rres, 1L); // true (succeed)
2333 __ bind(done);
2334 }
2335 %}
2336
2337 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2338 MacroAssembler _masm(&cbuf);
2339 Register Rcomp = reg_to_register_object($compare_value$$reg);
2340 Register Rnew = reg_to_register_object($exchange_value$$reg);
2341 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2342
2343 __ z_cs(Rcomp, Rnew, 0, Raddr);
2344 %}
2345
2346 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2347 MacroAssembler _masm(&cbuf);
2348 Register Rcomp = reg_to_register_object($compare_value$$reg);
2349 Register Rnew = reg_to_register_object($exchange_value$$reg);
2350 Register Raddr = reg_to_register_object($addr_ptr$$reg);
2351
2352 __ z_csg(Rcomp, Rnew, 0, Raddr);
2353 %}
2354
2355 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2356 MacroAssembler _masm(&cbuf);
2357 Register Rdst = reg_to_register_object($dst$$reg);
2358 Register Rtmp = reg_to_register_object($tmp$$reg);
2359 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2360 Label retry;
2361
2362 // Iterate until swap succeeds.
2363 __ z_llgf(Rtmp, $mem$$Address); // current contents
2364 __ bind(retry);
2365 // Calculate incremented value.
2366 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2367 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2368 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2369 %}
2370
2371 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2372 MacroAssembler _masm(&cbuf);
2373 Register Rdst = reg_to_register_object($dst$$reg);
2374 Register Rtmp = reg_to_register_object($tmp$$reg);
2375 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2376 Label retry;
2377
2378 // Iterate until swap succeeds.
2379 __ z_lg(Rtmp, $mem$$Address); // current contents
2380 __ bind(retry);
2381 // Calculate incremented value.
2382 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2383 __ z_brne(retry); // Yikes, concurrent update, need to retry.
2384 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value.
2385 %}
2386
2387 %} // encode
2388
2389 source %{
2390
2391 // Check whether outs are all Stores. If so, we can omit clearing the upper
2392 // 32 bits after encoding.
2393 static bool all_outs_are_Stores(const Node *n) {
2394 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2395 Node *out = n->fast_out(k);
2396 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2397 // Most other outs are SpillCopy, but there are various other.
2398 // jvm98 has arond 9% Encodes where we return false.
2399 return false;
2400 }
2401 }
2402 return true;
2403 }
2404
2405 %} // source
2406
2407
2408 //----------FRAME--------------------------------------------------------------
2409 // Definition of frame structure and management information.
2410
2411 frame %{
2412 // What direction does stack grow in (assumed to be same for native & Java).
2413 stack_direction(TOWARDS_LOW);
2414
2415 // These two registers define part of the calling convention between
2416 // compiled code and the interpreter.
2417
2418 // Inline Cache Register
2419 inline_cache_reg(Z_R9); // Z_inline_cache
2420
2421 // Argument pointer for I2C adapters
2422 //
2423 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2424 // interpreter_arg_ptr_reg(Z_R6);
2425
2426 // Temporary in compiled entry-points
2427 // compiler_method_oop_reg(Z_R1);//Z_R1_scratch
2428
2429 // Method Oop Register when calling interpreter
2430 interpreter_method_oop_reg(Z_R9);//Z_method
2431
2432 // Optional: name the operand used by cisc-spilling to access
2433 // [stack_pointer + offset].
2434 cisc_spilling_operand_name(indOffset12);
2435
2436 // Number of stack slots consumed by a Monitor enter.
2437 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2438
2439 // Compiled code's Frame Pointer
2440 //
2441 // z/Architecture stack pointer
2442 frame_pointer(Z_R15); // Z_SP
2443
2444 // Interpreter stores its frame pointer in a register which is
2445 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
2446 // interpreted java to compiled java.
2447 //
2448 // Z_state holds pointer to caller's cInterpreter.
2449 interpreter_frame_pointer(Z_R7); // Z_state
2450
2451 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2452 stack_alignment(frame::alignment_in_bytes);
2453
2454 in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units);
2455
2456 // A `slot' is assumed 4 bytes here!
2457 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2458
2459 // Number of outgoing stack slots killed above the
2460 // out_preserve_stack_slots for calls to C. Supports the var-args
2461 // backing area for register parms.
2462 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2463
2464 // The after-PROLOG location of the return address. Location of
2465 // return address specifies a type (REG or STACK) and a number
2466 // representing the register number (i.e. - use a register name) or
2467 // stack slot.
2468 return_addr(REG Z_R14);
2469
2470 // This is the body of the function
2471 //
2472 // void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */,
2473 // uint length /* length of array */,
2474 // bool is_outgoing)
2475 //
2476 // The `sig' array is to be updated. Sig[j] represents the location
2477 // of the j-th argument, either a register or a stack slot.
2478
2479 // Body of function which returns an integer array locating
2480 // arguments either in registers or in stack slots. Passed an array
2481 // of ideal registers called "sig" and a "length" count. Stack-slot
2482 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2483 // arguments for a CALLEE. Incoming stack arguments are
2484 // automatically biased by the preserve_stack_slots field above.
2485 calling_convention %{
2486 // No difference between ingoing/outgoing just pass false.
2487 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2488 %}
2489
2490 // Body of function which returns an integer array locating
2491 // arguments either in registers or in stack slots. Passed an array
2492 // of ideal registers called "sig" and a "length" count. Stack-slot
2493 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2494 // arguments for a CALLEE. Incoming stack arguments are
2495 // automatically biased by the preserve_stack_slots field above.
2496 c_calling_convention %{
2497 // This is obviously always outgoing.
2498 // C argument must be in register AND stack slot.
2499 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2500 %}
2501
2502 // Location of native (C/C++) and interpreter return values. This
2503 // is specified to be the same as Java. In the 32-bit VM, long
2504 // values are actually returned from native calls in O0:O1 and
2505 // returned to the interpreter in I0:I1. The copying to and from
2506 // the register pairs is done by the appropriate call and epilog
2507 // opcodes. This simplifies the register allocator.
2508 //
2509 // Use register pair for c return value.
2510 c_return_value %{
2511 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2512 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2513 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2514 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2515 %}
2516
2517 // Use register pair for return value.
2518 // Location of compiled Java return values. Same as C
2519 return_value %{
2520 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2521 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2522 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2523 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2524 %}
2525 %}
2526
2527
2528 //----------ATTRIBUTES---------------------------------------------------------
2529
2530 //----------Operand Attributes-------------------------------------------------
2531 op_attrib op_cost(1); // Required cost attribute
2532
2533 //----------Instruction Attributes---------------------------------------------
2534
2535 // Cost attribute. required.
2536 ins_attrib ins_cost(DEFAULT_COST);
2537
2538 // Is this instruction a non-matching short branch variant of some
2539 // long branch? Not required.
2540 ins_attrib ins_short_branch(0);
2541
2542 // Indicates this is a trap based check node and final control-flow fixup
2543 // must generate a proper fall through.
2544 ins_attrib ins_is_TrapBasedCheckNode(true);
2545
2546 // Attribute of instruction to tell how many constants the instruction will generate.
2547 // (optional attribute). Default: 0.
2548 ins_attrib ins_num_consts(0);
2549
2550 // Required alignment attribute (must be a power of 2)
2551 // specifies the alignment that some part of the instruction (not
2552 // necessarily the start) requires. If > 1, a compute_padding()
2553 // function must be provided for the instruction.
2554 //
2555 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2556 // instructions which depend on the proper alignment, because the
2557 // desired alignment isn't guaranteed for the call to "emit()" during
2558 // the size computation.
2559 ins_attrib ins_alignment(1);
2560
2561 // Enforce/prohibit rematerializations.
2562 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2563 // then rematerialization of that instruction is prohibited and the
2564 // instruction's value will be spilled if necessary.
2565 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2566 // then rematerialization is enforced and the instruction's value will
2567 // never get spilled. a copy of the instruction will be inserted if
2568 // necessary.
2569 // Note: this may result in rematerializations in front of every use.
2570 // (optional attribute)
2571 ins_attrib ins_cannot_rematerialize(false);
2572 ins_attrib ins_should_rematerialize(false);
2573
2574 //----------OPERANDS-----------------------------------------------------------
2575 // Operand definitions must precede instruction definitions for correct
2576 // parsing in the ADLC because operands constitute user defined types
2577 // which are used in instruction definitions.
2578
2579 //----------Simple Operands----------------------------------------------------
2580 // Immediate Operands
2581 // Please note:
2582 // Formats are generated automatically for constants and base registers.
2583
2584 //----------------------------------------------
2585 // SIGNED (shorter than INT) immediate operands
2586 //----------------------------------------------
2587
2588 // Byte Immediate: constant 'int -1'
2589 operand immB_minus1() %{
2590 // sign-ext constant zero-ext constant
2591 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2592 match(ConI);
2593 op_cost(1);
2594 format %{ %}
2595 interface(CONST_INTER);
2596 %}
2597
2598 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2599 operand immB_n0m1() %{
2600 // sign-ext constant zero-ext constant
2601 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2602 match(ConI);
2603 op_cost(1);
2604 format %{ %}
2605 interface(CONST_INTER);
2606 %}
2607
2608 // Short Immediate: constant 'int -1'
2609 operand immS_minus1() %{
2610 // sign-ext constant zero-ext constant
2611 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2612 match(ConI);
2613 op_cost(1);
2614 format %{ %}
2615 interface(CONST_INTER);
2616 %}
2617
2618 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2619 operand immS_n0m1() %{
2620 // sign-ext constant zero-ext constant
2621 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2622 match(ConI);
2623 op_cost(1);
2624 format %{ %}
2625 interface(CONST_INTER);
2626 %}
2627
2628 //-----------------------------------------
2629 // SIGNED INT immediate operands
2630 //-----------------------------------------
2631
2632 // Integer Immediate: 32-bit
2633 operand immI() %{
2634 match(ConI);
2635 op_cost(1);
2636 format %{ %}
2637 interface(CONST_INTER);
2638 %}
2639
2640 // Int Immediate: 20-bit
2641 operand immI20() %{
2642 predicate(Immediate::is_simm20(n->get_int()));
2643 match(ConI);
2644 op_cost(1);
2645 format %{ %}
2646 interface(CONST_INTER);
2647 %}
2648
2649 // Integer Immediate: 16-bit
2650 operand immI16() %{
2651 predicate(Immediate::is_simm16(n->get_int()));
2652 match(ConI);
2653 op_cost(1);
2654 format %{ %}
2655 interface(CONST_INTER);
2656 %}
2657
2658 // Integer Immediate: 8-bit
2659 operand immI8() %{
2660 predicate(Immediate::is_simm8(n->get_int()));
2661 match(ConI);
2662 op_cost(1);
2663 format %{ %}
2664 interface(CONST_INTER);
2665 %}
2666
2667 // Integer Immediate: constant 'int 0'
2668 operand immI_0() %{
2669 predicate(n->get_int() == 0);
2670 match(ConI);
2671 op_cost(1);
2672 format %{ %}
2673 interface(CONST_INTER);
2674 %}
2675
2676 // Integer Immediate: constant 'int -1'
2677 operand immI_minus1() %{
2678 predicate(n->get_int() == -1);
2679 match(ConI);
2680 op_cost(1);
2681 format %{ %}
2682 interface(CONST_INTER);
2683 %}
2684
2685 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2686 operand immI_n0m1() %{
2687 predicate(n->get_int() != 0 && n->get_int() != -1);
2688 match(ConI);
2689 op_cost(1);
2690 format %{ %}
2691 interface(CONST_INTER);
2692 %}
2693
2694 //-------------------------------------------
2695 // UNSIGNED INT immediate operands
2696 //-------------------------------------------
2697
2698 // Unsigned Integer Immediate: 32-bit
2699 operand uimmI() %{
2700 match(ConI);
2701 op_cost(1);
2702 format %{ %}
2703 interface(CONST_INTER);
2704 %}
2705
2706 // Unsigned Integer Immediate: 16-bit
2707 operand uimmI16() %{
2708 predicate(Immediate::is_uimm16(n->get_int()));
2709 match(ConI);
2710 op_cost(1);
2711 format %{ %}
2712 interface(CONST_INTER);
2713 %}
2714
2715 // Unsigned Integer Immediate: 12-bit
2716 operand uimmI12() %{
2717 predicate(Immediate::is_uimm12(n->get_int()));
2718 match(ConI);
2719 op_cost(1);
2720 format %{ %}
2721 interface(CONST_INTER);
2722 %}
2723
2724 // Unsigned Integer Immediate: 12-bit
2725 operand uimmI8() %{
2726 predicate(Immediate::is_uimm8(n->get_int()));
2727 match(ConI);
2728 op_cost(1);
2729 format %{ %}
2730 interface(CONST_INTER);
2731 %}
2732
2733 // Integer Immediate: 6-bit
2734 operand uimmI6() %{
2735 predicate(Immediate::is_uimm(n->get_int(), 6));
2736 match(ConI);
2737 op_cost(1);
2738 format %{ %}
2739 interface(CONST_INTER);
2740 %}
2741
2742 // Integer Immediate: 5-bit
2743 operand uimmI5() %{
2744 predicate(Immediate::is_uimm(n->get_int(), 5));
2745 match(ConI);
2746 op_cost(1);
2747 format %{ %}
2748 interface(CONST_INTER);
2749 %}
2750
2751 // Length for SS instructions, given in DWs,
2752 // possible range [1..512], i.e. [8..4096] Bytes
2753 // used range [1..256], i.e. [8..2048] Bytes
2754 // operand type int
2755 // Unsigned Integer Immediate: 9-bit
2756 operand SSlenDW() %{
2757 predicate(Immediate::is_uimm8(n->get_long()-1));
2758 match(ConL);
2759 op_cost(1);
2760 format %{ %}
2761 interface(CONST_INTER);
2762 %}
2763
2764 //------------------------------------------
2765 // (UN)SIGNED INT specific values
2766 //------------------------------------------
2767
2768 // Integer Immediate: the value 1
2769 operand immI_1() %{
2770 predicate(n->get_int() == 1);
2771 match(ConI);
2772 op_cost(1);
2773 format %{ %}
2774 interface(CONST_INTER);
2775 %}
2776
2777 // Integer Immediate: the value 16.
2778 operand immI_16() %{
2779 predicate(n->get_int() == 16);
2780 match(ConI);
2781 op_cost(1);
2782 format %{ %}
2783 interface(CONST_INTER);
2784 %}
2785
2786 // Integer Immediate: the value 24.
2787 operand immI_24() %{
2788 predicate(n->get_int() == 24);
2789 match(ConI);
2790 op_cost(1);
2791 format %{ %}
2792 interface(CONST_INTER);
2793 %}
2794
2795 // Integer Immediate: the value 255
2796 operand immI_255() %{
2797 predicate(n->get_int() == 255);
2798 match(ConI);
2799 op_cost(1);
2800 format %{ %}
2801 interface(CONST_INTER);
2802 %}
2803
2804 // Integer Immediate: the values 32-63
2805 operand immI_32_63() %{
2806 predicate(n->get_int() >= 32 && n->get_int() <= 63);
2807 match(ConI);
2808 op_cost(1);
2809 format %{ %}
2810 interface(CONST_INTER);
2811 %}
2812
2813 // Unsigned Integer Immediate: LL-part, extended by 1s.
2814 operand uimmI_LL1() %{
2815 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
2816 match(ConI);
2817 op_cost(1);
2818 format %{ %}
2819 interface(CONST_INTER);
2820 %}
2821
2822 // Unsigned Integer Immediate: LH-part, extended by 1s.
2823 operand uimmI_LH1() %{
2824 predicate((n->get_int() & 0xFFFF) == 0xFFFF);
2825 match(ConI);
2826 op_cost(1);
2827 format %{ %}
2828 interface(CONST_INTER);
2829 %}
2830
2831 //------------------------------------------
2832 // SIGNED LONG immediate operands
2833 //------------------------------------------
2834
2835 operand immL() %{
2836 match(ConL);
2837 op_cost(1);
2838 format %{ %}
2839 interface(CONST_INTER);
2840 %}
2841
2842 // Long Immediate: 32-bit
2843 operand immL32() %{
2844 predicate(Immediate::is_simm32(n->get_long()));
2845 match(ConL);
2846 op_cost(1);
2847 format %{ %}
2848 interface(CONST_INTER);
2849 %}
2850
2851 // Long Immediate: 20-bit
2852 operand immL20() %{
2853 predicate(Immediate::is_simm20(n->get_long()));
2854 match(ConL);
2855 op_cost(1);
2856 format %{ %}
2857 interface(CONST_INTER);
2858 %}
2859
2860 // Long Immediate: 16-bit
2861 operand immL16() %{
2862 predicate(Immediate::is_simm16(n->get_long()));
2863 match(ConL);
2864 op_cost(1);
2865 format %{ %}
2866 interface(CONST_INTER);
2867 %}
2868
2869 // Long Immediate: 8-bit
2870 operand immL8() %{
2871 predicate(Immediate::is_simm8(n->get_long()));
2872 match(ConL);
2873 op_cost(1);
2874 format %{ %}
2875 interface(CONST_INTER);
2876 %}
2877
2878 //--------------------------------------------
2879 // UNSIGNED LONG immediate operands
2880 //--------------------------------------------
2881
2882 operand uimmL32() %{
2883 predicate(Immediate::is_uimm32(n->get_long()));
2884 match(ConL);
2885 op_cost(1);
2886 format %{ %}
2887 interface(CONST_INTER);
2888 %}
2889
2890 // Unsigned Long Immediate: 16-bit
2891 operand uimmL16() %{
2892 predicate(Immediate::is_uimm16(n->get_long()));
2893 match(ConL);
2894 op_cost(1);
2895 format %{ %}
2896 interface(CONST_INTER);
2897 %}
2898
2899 // Unsigned Long Immediate: 12-bit
2900 operand uimmL12() %{
2901 predicate(Immediate::is_uimm12(n->get_long()));
2902 match(ConL);
2903 op_cost(1);
2904 format %{ %}
2905 interface(CONST_INTER);
2906 %}
2907
2908 // Unsigned Long Immediate: 8-bit
2909 operand uimmL8() %{
2910 predicate(Immediate::is_uimm8(n->get_long()));
2911 match(ConL);
2912 op_cost(1);
2913 format %{ %}
2914 interface(CONST_INTER);
2915 %}
2916
2917 //-------------------------------------------
2918 // (UN)SIGNED LONG specific values
2919 //-------------------------------------------
2920
2921 // Long Immediate: the value FF
2922 operand immL_FF() %{
2923 predicate(n->get_long() == 0xFFL);
2924 match(ConL);
2925 op_cost(1);
2926 format %{ %}
2927 interface(CONST_INTER);
2928 %}
2929
2930 // Long Immediate: the value FFFF
2931 operand immL_FFFF() %{
2932 predicate(n->get_long() == 0xFFFFL);
2933 match(ConL);
2934 op_cost(1);
2935 format %{ %}
2936 interface(CONST_INTER);
2937 %}
2938
2939 // Long Immediate: the value FFFFFFFF
2940 operand immL_FFFFFFFF() %{
2941 predicate(n->get_long() == 0xFFFFFFFFL);
2942 match(ConL);
2943 op_cost(1);
2944 format %{ %}
2945 interface(CONST_INTER);
2946 %}
2947
2948 operand immL_0() %{
2949 predicate(n->get_long() == 0L);
2950 match(ConL);
2951 op_cost(1);
2952 format %{ %}
2953 interface(CONST_INTER);
2954 %}
2955
2956 // Unsigned Long Immediate: LL-part, extended by 1s.
2957 operand uimmL_LL1() %{
2958 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
2959 match(ConL);
2960 op_cost(1);
2961 format %{ %}
2962 interface(CONST_INTER);
2963 %}
2964
2965 // Unsigned Long Immediate: LH-part, extended by 1s.
2966 operand uimmL_LH1() %{
2967 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
2968 match(ConL);
2969 op_cost(1);
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 // Unsigned Long Immediate: HL-part, extended by 1s.
2975 operand uimmL_HL1() %{
2976 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
2977 match(ConL);
2978 op_cost(1);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 // Unsigned Long Immediate: HH-part, extended by 1s.
2984 operand uimmL_HH1() %{
2985 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
2986 match(ConL);
2987 op_cost(1);
2988 format %{ %}
2989 interface(CONST_INTER);
2990 %}
2991
2992 // Long Immediate: low 32-bit mask
2993 operand immL_32bits() %{
2994 predicate(n->get_long() == 0xFFFFFFFFL);
2995 match(ConL);
2996 op_cost(1);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 //--------------------------------------
3002 // POINTER immediate operands
3003 //--------------------------------------
3004
3005 // Pointer Immediate: 64-bit
3006 operand immP() %{
3007 match(ConP);
3008 op_cost(1);
3009 format %{ %}
3010 interface(CONST_INTER);
3011 %}
3012
3013 // Pointer Immediate: 32-bit
3014 operand immP32() %{
3015 predicate(Immediate::is_uimm32(n->get_ptr()));
3016 match(ConP);
3017 op_cost(1);
3018 format %{ %}
3019 interface(CONST_INTER);
3020 %}
3021
3022 // Pointer Immediate: 16-bit
3023 operand immP16() %{
3024 predicate(Immediate::is_uimm16(n->get_ptr()));
3025 match(ConP);
3026 op_cost(1);
3027 format %{ %}
3028 interface(CONST_INTER);
3029 %}
3030
3031 // Pointer Immediate: 8-bit
3032 operand immP8() %{
3033 predicate(Immediate::is_uimm8(n->get_ptr()));
3034 match(ConP);
3035 op_cost(1);
3036 format %{ %}
3037 interface(CONST_INTER);
3038 %}
3039
3040 //-----------------------------------
3041 // POINTER specific values
3042 //-----------------------------------
3043
3044 // Pointer Immediate: NULL
3045 operand immP0() %{
3046 predicate(n->get_ptr() == 0);
3047 match(ConP);
3048 op_cost(1);
3049 format %{ %}
3050 interface(CONST_INTER);
3051 %}
3052
3053 //---------------------------------------------
3054 // NARROW POINTER immediate operands
3055 //---------------------------------------------
3056
3057 // Narrow Pointer Immediate
3058 operand immN() %{
3059 match(ConN);
3060 op_cost(1);
3061 format %{ %}
3062 interface(CONST_INTER);
3063 %}
3064
3065 operand immNKlass() %{
3066 match(ConNKlass);
3067 op_cost(1);
3068 format %{ %}
3069 interface(CONST_INTER);
3070 %}
3071
3072 // Narrow Pointer Immediate
3073 operand immN8() %{
3074 predicate(Immediate::is_uimm8(n->get_narrowcon()));
3075 match(ConN);
3076 op_cost(1);
3077 format %{ %}
3078 interface(CONST_INTER);
3079 %}
3080
3081 // Narrow NULL Pointer Immediate
3082 operand immN0() %{
3083 predicate(n->get_narrowcon() == 0);
3084 match(ConN);
3085 op_cost(1);
3086 format %{ %}
3087 interface(CONST_INTER);
3088 %}
3089
3090 // FLOAT and DOUBLE immediate operands
3091
3092 // Double Immediate
3093 operand immD() %{
3094 match(ConD);
3095 op_cost(1);
3096 format %{ %}
3097 interface(CONST_INTER);
3098 %}
3099
3100 // Double Immediate: +-0
3101 operand immDpm0() %{
3102 predicate(n->getd() == 0);
3103 match(ConD);
3104 op_cost(1);
3105 format %{ %}
3106 interface(CONST_INTER);
3107 %}
3108
3109 // Double Immediate: +0
3110 operand immDp0() %{
3111 predicate(jlong_cast(n->getd()) == 0);
3112 match(ConD);
3113 op_cost(1);
3114 format %{ %}
3115 interface(CONST_INTER);
3116 %}
3117
3118 // Float Immediate
3119 operand immF() %{
3120 match(ConF);
3121 op_cost(1);
3122 format %{ %}
3123 interface(CONST_INTER);
3124 %}
3125
3126 // Float Immediate: +-0
3127 operand immFpm0() %{
3128 predicate(n->getf() == 0);
3129 match(ConF);
3130 op_cost(1);
3131 format %{ %}
3132 interface(CONST_INTER);
3133 %}
3134
3135 // Float Immediate: +0
3136 operand immFp0() %{
3137 predicate(jint_cast(n->getf()) == 0);
3138 match(ConF);
3139 op_cost(1);
3140 format %{ %}
3141 interface(CONST_INTER);
3142 %}
3143
3144 // End of Immediate Operands
3145
3146 // Integer Register Operands
3147 // Integer Register
3148 operand iRegI() %{
3149 constraint(ALLOC_IN_RC(z_int_reg));
3150 match(RegI);
3151 match(noArg_iRegI);
3152 match(rarg1RegI);
3153 match(rarg2RegI);
3154 match(rarg3RegI);
3155 match(rarg4RegI);
3156 match(rarg5RegI);
3157 match(noOdd_iRegI);
3158 match(revenRegI);
3159 match(roddRegI);
3160 format %{ %}
3161 interface(REG_INTER);
3162 %}
3163
3164 operand noArg_iRegI() %{
3165 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3166 match(RegI);
3167 format %{ %}
3168 interface(REG_INTER);
3169 %}
3170
3171 // revenRegI and roddRegI constitute and even-odd-pair.
3172 operand revenRegI() %{
3173 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3174 match(iRegI);
3175 format %{ %}
3176 interface(REG_INTER);
3177 %}
3178
3179 // revenRegI and roddRegI constitute and even-odd-pair.
3180 operand roddRegI() %{
3181 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3182 match(iRegI);
3183 format %{ %}
3184 interface(REG_INTER);
3185 %}
3186
3187 operand rarg1RegI() %{
3188 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3189 match(iRegI);
3190 format %{ %}
3191 interface(REG_INTER);
3192 %}
3193
3194 operand rarg2RegI() %{
3195 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3196 match(iRegI);
3197 format %{ %}
3198 interface(REG_INTER);
3199 %}
3200
3201 operand rarg3RegI() %{
3202 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3203 match(iRegI);
3204 format %{ %}
3205 interface(REG_INTER);
3206 %}
3207
3208 operand rarg4RegI() %{
3209 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3210 match(iRegI);
3211 format %{ %}
3212 interface(REG_INTER);
3213 %}
3214
3215 operand rarg5RegI() %{
3216 constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3217 match(iRegI);
3218 format %{ %}
3219 interface(REG_INTER);
3220 %}
3221
3222 operand noOdd_iRegI() %{
3223 constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3224 match(RegI);
3225 match(revenRegI);
3226 format %{ %}
3227 interface(REG_INTER);
3228 %}
3229
3230 // Pointer Register
3231 operand iRegP() %{
3232 constraint(ALLOC_IN_RC(z_ptr_reg));
3233 match(RegP);
3234 match(noArg_iRegP);
3235 match(rarg1RegP);
3236 match(rarg2RegP);
3237 match(rarg3RegP);
3238 match(rarg4RegP);
3239 match(rarg5RegP);
3240 match(revenRegP);
3241 match(roddRegP);
3242 format %{ %}
3243 interface(REG_INTER);
3244 %}
3245
3246 // thread operand
3247 operand threadRegP() %{
3248 constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3249 match(RegP);
3250 format %{ "Z_THREAD" %}
3251 interface(REG_INTER);
3252 %}
3253
3254 operand noArg_iRegP() %{
3255 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3256 match(iRegP);
3257 format %{ %}
3258 interface(REG_INTER);
3259 %}
3260
3261 operand rarg1RegP() %{
3262 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3263 match(iRegP);
3264 format %{ %}
3265 interface(REG_INTER);
3266 %}
3267
3268 operand rarg2RegP() %{
3269 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3270 match(iRegP);
3271 format %{ %}
3272 interface(REG_INTER);
3273 %}
3274
3275 operand rarg3RegP() %{
3276 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3277 match(iRegP);
3278 format %{ %}
3279 interface(REG_INTER);
3280 %}
3281
3282 operand rarg4RegP() %{
3283 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3284 match(iRegP);
3285 format %{ %}
3286 interface(REG_INTER);
3287 %}
3288
3289 operand rarg5RegP() %{
3290 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3291 match(iRegP);
3292 format %{ %}
3293 interface(REG_INTER);
3294 %}
3295
3296 operand memoryRegP() %{
3297 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3298 match(RegP);
3299 match(iRegP);
3300 match(threadRegP);
3301 format %{ %}
3302 interface(REG_INTER);
3303 %}
3304
3305 // revenRegP and roddRegP constitute and even-odd-pair.
3306 operand revenRegP() %{
3307 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3308 match(iRegP);
3309 format %{ %}
3310 interface(REG_INTER);
3311 %}
3312
3313 // revenRegP and roddRegP constitute and even-odd-pair.
3314 operand roddRegP() %{
3315 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3316 match(iRegP);
3317 format %{ %}
3318 interface(REG_INTER);
3319 %}
3320
3321 operand lock_ptr_RegP() %{
3322 constraint(ALLOC_IN_RC(z_lock_ptr_reg));
3323 match(RegP);
3324 format %{ %}
3325 interface(REG_INTER);
3326 %}
3327
3328 operand rscratch2RegP() %{
3329 constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg));
3330 match(RegP);
3331 format %{ %}
3332 interface(REG_INTER);
3333 %}
3334
3335 operand iRegN() %{
3336 constraint(ALLOC_IN_RC(z_int_reg));
3337 match(RegN);
3338 match(noArg_iRegN);
3339 match(rarg1RegN);
3340 match(rarg2RegN);
3341 match(rarg3RegN);
3342 match(rarg4RegN);
3343 match(rarg5RegN);
3344 format %{ %}
3345 interface(REG_INTER);
3346 %}
3347
3348 operand noArg_iRegN() %{
3349 constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3350 match(iRegN);
3351 format %{ %}
3352 interface(REG_INTER);
3353 %}
3354
3355 operand rarg1RegN() %{
3356 constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3357 match(iRegN);
3358 format %{ %}
3359 interface(REG_INTER);
3360 %}
3361
3362 operand rarg2RegN() %{
3363 constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3364 match(iRegN);
3365 format %{ %}
3366 interface(REG_INTER);
3367 %}
3368
3369 operand rarg3RegN() %{
3370 constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3371 match(iRegN);
3372 format %{ %}
3373 interface(REG_INTER);
3374 %}
3375
3376 operand rarg4RegN() %{
3377 constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3378 match(iRegN);
3379 format %{ %}
3380 interface(REG_INTER);
3381 %}
3382
3383 operand rarg5RegN() %{
3384 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3385 match(iRegN);
3386 format %{ %}
3387 interface(REG_INTER);
3388 %}
3389
3390 // Long Register
3391 operand iRegL() %{
3392 constraint(ALLOC_IN_RC(z_long_reg));
3393 match(RegL);
3394 match(revenRegL);
3395 match(roddRegL);
3396 match(rarg1RegL);
3397 match(rarg5RegL);
3398 format %{ %}
3399 interface(REG_INTER);
3400 %}
3401
3402 // revenRegL and roddRegL constitute and even-odd-pair.
3403 operand revenRegL() %{
3404 constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3405 match(iRegL);
3406 format %{ %}
3407 interface(REG_INTER);
3408 %}
3409
3410 // revenRegL and roddRegL constitute and even-odd-pair.
3411 operand roddRegL() %{
3412 constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3413 match(iRegL);
3414 format %{ %}
3415 interface(REG_INTER);
3416 %}
3417
3418 operand rarg1RegL() %{
3419 constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3420 match(iRegL);
3421 format %{ %}
3422 interface(REG_INTER);
3423 %}
3424
3425 operand rarg5RegL() %{
3426 constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3427 match(iRegL);
3428 format %{ %}
3429 interface(REG_INTER);
3430 %}
3431
3432 // Condition Code Flag Registers
3433 operand flagsReg() %{
3434 constraint(ALLOC_IN_RC(z_condition_reg));
3435 match(RegFlags);
3436 format %{ "CR" %}
3437 interface(REG_INTER);
3438 %}
3439
3440 // Condition Code Flag Registers for rules with result tuples
3441 operand TD_flagsReg() %{
3442 constraint(ALLOC_IN_RC(z_condition_reg));
3443 match(RegFlags);
3444 format %{ "CR" %}
3445 interface(REG_TUPLE_DEST_INTER);
3446 %}
3447
3448 operand regD() %{
3449 constraint(ALLOC_IN_RC(z_dbl_reg));
3450 match(RegD);
3451 format %{ %}
3452 interface(REG_INTER);
3453 %}
3454
3455 operand rscratchRegD() %{
3456 constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg));
3457 match(RegD);
3458 format %{ %}
3459 interface(REG_INTER);
3460 %}
3461
3462 operand regF() %{
3463 constraint(ALLOC_IN_RC(z_flt_reg));
3464 match(RegF);
3465 format %{ %}
3466 interface(REG_INTER);
3467 %}
3468
3469 operand rscratchRegF() %{
3470 constraint(ALLOC_IN_RC(z_rscratch1_flt_reg));
3471 match(RegF);
3472 format %{ %}
3473 interface(REG_INTER);
3474 %}
3475
3476 // Special Registers
3477
3478 // Method Register
3479 operand inline_cache_regP(iRegP reg) %{
3480 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3481 match(reg);
3482 format %{ %}
3483 interface(REG_INTER);
3484 %}
3485
3486 operand compiler_method_oop_regP(iRegP reg) %{
3487 constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg
3488 match(reg);
3489 format %{ %}
3490 interface(REG_INTER);
3491 %}
3492
3493 operand interpreter_method_oop_regP(iRegP reg) %{
3494 constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg
3495 match(reg);
3496 format %{ %}
3497 interface(REG_INTER);
3498 %}
3499
3500 // Operands to remove register moves in unscaled mode.
3501 // Match read/write registers with an EncodeP node if neither shift nor add are required.
3502 operand iRegP2N(iRegP reg) %{
3503 predicate(Universe::narrow_oop_shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL);
3504 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3505 match(EncodeP reg);
3506 format %{ "$reg" %}
3507 interface(REG_INTER)
3508 %}
3509
3510 operand iRegN2P(iRegN reg) %{
3511 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0 &&
3512 _leaf->as_DecodeN()->in(0) == NULL);
3513 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3514 match(DecodeN reg);
3515 format %{ "$reg" %}
3516 interface(REG_INTER)
3517 %}
3518
3519
3520 //----------Complex Operands---------------------------------------------------
3521
3522 // Indirect Memory Reference
3523 operand indirect(memoryRegP base) %{
3524 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3525 match(base);
3526 op_cost(1);
3527 format %{ "#0[,$base]" %}
3528 interface(MEMORY_INTER) %{
3529 base($base);
3530 index(0xffffFFFF); // noreg
3531 scale(0x0);
3532 disp(0x0);
3533 %}
3534 %}
3535
3536 // Indirect with Offset (long)
3537 operand indOffset20(memoryRegP base, immL20 offset) %{
3538 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3539 match(AddP base offset);
3540 op_cost(1);
3541 format %{ "$offset[,$base]" %}
3542 interface(MEMORY_INTER) %{
3543 base($base);
3544 index(0xffffFFFF); // noreg
3545 scale(0x0);
3546 disp($offset);
3547 %}
3548 %}
3549
3550 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3551 predicate(Matcher::narrow_oop_use_complex_address());
3552 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3553 match(AddP (DecodeN base) offset);
3554 op_cost(1);
3555 format %{ "$offset[,$base]" %}
3556 interface(MEMORY_INTER) %{
3557 base($base);
3558 index(0xffffFFFF); // noreg
3559 scale(0x0);
3560 disp($offset);
3561 %}
3562 %}
3563
3564 // Indirect with Offset (short)
3565 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3566 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3567 match(AddP base offset);
3568 op_cost(1);
3569 format %{ "$offset[[,$base]]" %}
3570 interface(MEMORY_INTER) %{
3571 base($base);
3572 index(0xffffFFFF); // noreg
3573 scale(0x0);
3574 disp($offset);
3575 %}
3576 %}
3577
3578 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3579 predicate(Matcher::narrow_oop_use_complex_address());
3580 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3581 match(AddP (DecodeN base) offset);
3582 op_cost(1);
3583 format %{ "$offset[[,$base]]" %}
3584 interface(MEMORY_INTER) %{
3585 base($base);
3586 index(0xffffFFFF); // noreg
3587 scale(0x0);
3588 disp($offset);
3589 %}
3590 %}
3591
3592 // Indirect with Register Index
3593 operand indIndex(memoryRegP base, iRegL index) %{
3594 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3595 match(AddP base index);
3596 op_cost(1);
3597 format %{ "#0[($index,$base)]" %}
3598 interface(MEMORY_INTER) %{
3599 base($base);
3600 index($index);
3601 scale(0x0);
3602 disp(0x0);
3603 %}
3604 %}
3605
3606 // Indirect with Offset (long) and index
3607 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3608 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3609 match(AddP (AddP base index) offset);
3610 op_cost(1);
3611 format %{ "$offset[($index,$base)]" %}
3612 interface(MEMORY_INTER) %{
3613 base($base);
3614 index($index);
3615 scale(0x0);
3616 disp($offset);
3617 %}
3618 %}
3619
3620 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3621 predicate(Matcher::narrow_oop_use_complex_address());
3622 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3623 match(AddP (AddP (DecodeN base) index) offset);
3624 op_cost(1);
3625 format %{ "$offset[($index,$base)]" %}
3626 interface(MEMORY_INTER) %{
3627 base($base);
3628 index($index);
3629 scale(0x0);
3630 disp($offset);
3631 %}
3632 %}
3633
3634 // Indirect with Offset (short) and index
3635 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3636 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3637 match(AddP (AddP base index) offset);
3638 op_cost(1);
3639 format %{ "$offset[[($index,$base)]]" %}
3640 interface(MEMORY_INTER) %{
3641 base($base);
3642 index($index);
3643 scale(0x0);
3644 disp($offset);
3645 %}
3646 %}
3647
3648 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3649 predicate(Matcher::narrow_oop_use_complex_address());
3650 constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3651 match(AddP (AddP (DecodeN base) index) offset);
3652 op_cost(1);
3653 format %{ "$offset[[($index,$base)]]" %}
3654 interface(MEMORY_INTER) %{
3655 base($base);
3656 index($index);
3657 scale(0x0);
3658 disp($offset);
3659 %}
3660 %}
3661
3662 //----------Special Memory Operands--------------------------------------------
3663
3664 // Stack Slot Operand
3665 // This operand is used for loading and storing temporary values on
3666 // the stack where a match requires a value to flow through memory.
3667 operand stackSlotI(sRegI reg) %{
3668 constraint(ALLOC_IN_RC(stack_slots));
3669 op_cost(1);
3670 format %{ "[$reg(stackSlotI)]" %}
3671 interface(MEMORY_INTER) %{
3672 base(0xf); // Z_SP
3673 index(0xffffFFFF); // noreg
3674 scale(0x0);
3675 disp($reg); // stack offset
3676 %}
3677 %}
3678
3679 operand stackSlotP(sRegP reg) %{
3680 constraint(ALLOC_IN_RC(stack_slots));
3681 op_cost(1);
3682 format %{ "[$reg(stackSlotP)]" %}
3683 interface(MEMORY_INTER) %{
3684 base(0xf); // Z_SP
3685 index(0xffffFFFF); // noreg
3686 scale(0x0);
3687 disp($reg); // Stack Offset
3688 %}
3689 %}
3690
3691 operand stackSlotF(sRegF reg) %{
3692 constraint(ALLOC_IN_RC(stack_slots));
3693 op_cost(1);
3694 format %{ "[$reg(stackSlotF)]" %}
3695 interface(MEMORY_INTER) %{
3696 base(0xf); // Z_SP
3697 index(0xffffFFFF); // noreg
3698 scale(0x0);
3699 disp($reg); // Stack Offset
3700 %}
3701 %}
3702
3703 operand stackSlotD(sRegD reg) %{
3704 constraint(ALLOC_IN_RC(stack_slots));
3705 op_cost(1);
3706 //match(RegD);
3707 format %{ "[$reg(stackSlotD)]" %}
3708 interface(MEMORY_INTER) %{
3709 base(0xf); // Z_SP
3710 index(0xffffFFFF); // noreg
3711 scale(0x0);
3712 disp($reg); // Stack Offset
3713 %}
3714 %}
3715
3716 operand stackSlotL(sRegL reg) %{
3717 constraint(ALLOC_IN_RC(stack_slots));
3718 op_cost(1); //match(RegL);
3719 format %{ "[$reg(stackSlotL)]" %}
3720 interface(MEMORY_INTER) %{
3721 base(0xf); // Z_SP
3722 index(0xffffFFFF); // noreg
3723 scale(0x0);
3724 disp($reg); // Stack Offset
3725 %}
3726 %}
3727
3728 // Operands for expressing Control Flow
3729 // NOTE: Label is a predefined operand which should not be redefined in
3730 // the AD file. It is generically handled within the ADLC.
3731
3732 //----------Conditional Branch Operands----------------------------------------
3733 // Comparison Op - This is the operation of the comparison, and is limited to
3734 // the following set of codes:
3735 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3736 //
3737 // Other attributes of the comparison, such as unsignedness, are specified
3738 // by the comparison instruction that sets a condition code flags register.
3739 // That result is represented by a flags operand whose subtype is appropriate
3740 // to the unsignedness (etc.) of the comparison.
3741 //
3742 // Later, the instruction which matches both the Comparison Op (a Bool) and
3743 // the flags (produced by the Cmp) specifies the coding of the comparison op
3744 // by matching a specific subtype of Bool operand below.
3745
3746 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3747 // have mask bit #3 set.
3748 operand cmpOpT() %{
3749 match(Bool);
3750 format %{ "" %}
3751 interface(COND_INTER) %{
3752 equal(0x8); // Assembler::bcondEqual
3753 not_equal(0x6); // Assembler::bcondNotEqual
3754 less(0x4); // Assembler::bcondLow
3755 greater_equal(0xa); // Assembler::bcondNotLow
3756 less_equal(0xc); // Assembler::bcondNotHigh
3757 greater(0x2); // Assembler::bcondHigh
3758 overflow(0x1); // Assembler::bcondOverflow
3759 no_overflow(0xe); // Assembler::bcondNotOverflow
3760 %}
3761 %}
3762
3763 // When used for floating point comparisons: unordered is treated as less.
3764 operand cmpOpF() %{
3765 match(Bool);
3766 format %{ "" %}
3767 interface(COND_INTER) %{
3768 equal(0x8);
3769 not_equal(0x7); // Includes 'unordered'.
3770 less(0x5); // Includes 'unordered'.
3771 greater_equal(0xa);
3772 less_equal(0xd); // Includes 'unordered'.
3773 greater(0x2);
3774 overflow(0x0); // Not meaningful on z/Architecture.
3775 no_overflow(0x0); // leave unchanged (zero) therefore
3776 %}
3777 %}
3778
3779 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3780 operand cmpOp() %{
3781 match(Bool);
3782 format %{ "" %}
3783 interface(COND_INTER) %{
3784 equal(0x8);
3785 not_equal(0x7); // Includes 'unordered'.
3786 less(0x5); // Includes 'unordered'.
3787 greater_equal(0xa);
3788 less_equal(0xd); // Includes 'unordered'.
3789 greater(0x2);
3790 overflow(0x1); // Assembler::bcondOverflow
3791 no_overflow(0xe); // Assembler::bcondNotOverflow
3792 %}
3793 %}
3794
3795 //----------OPERAND CLASSES----------------------------------------------------
3796 // Operand Classes are groups of operands that are used to simplify
3797 // instruction definitions by not requiring the AD writer to specify
3798 // seperate instructions for every form of operand when the
3799 // instruction accepts multiple operand types with the same basic
3800 // encoding and format. The classic case of this is memory operands.
3801 // Indirect is not included since its use is limited to Compare & Swap
3802
3803 // Most general memory operand, allows base, index, and long displacement.
3804 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3805 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3806
3807 // General memory operand, allows base, index, and short displacement.
3808 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3809
3810 // Memory operand, allows only base and long displacement.
3811 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3812
3813 // Memory operand, allows only base and short displacement.
3814 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3815
3816 // Operand classes to match encode and decode.
3817 opclass iRegN_P2N(iRegN);
3818 opclass iRegP_N2P(iRegP);
3819
3820
3821 //----------PIPELINE-----------------------------------------------------------
3822 pipeline %{
3823
3824 //----------ATTRIBUTES---------------------------------------------------------
3825 attributes %{
3826 // z/Architecture instructions are of length 2, 4, or 6 bytes.
3827 variable_size_instructions;
3828 instruction_unit_size = 2;
3829
3830 // Meaningless on z/Architecture.
3831 max_instructions_per_bundle = 1;
3832
3833 // The z/Architecture processor fetches 64 bytes...
3834 instruction_fetch_unit_size = 64;
3835
3836 // ...in one line.
3837 instruction_fetch_units = 1
3838 %}
3839
3840 //----------RESOURCES----------------------------------------------------------
3841 // Resources are the functional units available to the machine.
3842 resources(
3843 Z_BR, // branch unit
3844 Z_CR, // condition unit
3845 Z_FX1, // integer arithmetic unit 1
3846 Z_FX2, // integer arithmetic unit 2
3847 Z_LDST1, // load/store unit 1
3848 Z_LDST2, // load/store unit 2
3849 Z_FP1, // float arithmetic unit 1
3850 Z_FP2, // float arithmetic unit 2
3851 Z_LDST = Z_LDST1 | Z_LDST2,
3852 Z_FX = Z_FX1 | Z_FX2,
3853 Z_FP = Z_FP1 | Z_FP2
3854 );
3855
3856 //----------PIPELINE DESCRIPTION-----------------------------------------------
3857 // Pipeline Description specifies the stages in the machine's pipeline.
3858 pipe_desc(
3859 // TODO: adapt
3860 Z_IF, // instruction fetch
3861 Z_IC,
3862 Z_D0, // decode
3863 Z_D1, // decode
3864 Z_D2, // decode
3865 Z_D3, // decode
3866 Z_Xfer1,
3867 Z_GD, // group definition
3868 Z_MP, // map
3869 Z_ISS, // issue
3870 Z_RF, // resource fetch
3871 Z_EX1, // execute (all units)
3872 Z_EX2, // execute (FP, LDST)
3873 Z_EX3, // execute (FP, LDST)
3874 Z_EX4, // execute (FP)
3875 Z_EX5, // execute (FP)
3876 Z_EX6, // execute (FP)
3877 Z_WB, // write back
3878 Z_Xfer2,
3879 Z_CP
3880 );
3881
3882 //----------PIPELINE CLASSES---------------------------------------------------
3883 // Pipeline Classes describe the stages in which input and output are
3884 // referenced by the hardware pipeline.
3885
3886 // Providing the `ins_pipe' declarations in the instruction
3887 // specifications seems to be of little use. So we use
3888 // `pipe_class_dummy' for all our instructions at present.
3889 pipe_class pipe_class_dummy() %{
3890 single_instruction;
3891 fixed_latency(4);
3892 %}
3893
3894 // SIGTRAP based implicit range checks in compiled code.
3895 // Currently, no pipe classes are used on z/Architecture.
3896 pipe_class pipe_class_trap() %{
3897 single_instruction;
3898 %}
3899
3900 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
3901 single_instruction;
3902 dst : Z_EX1(write);
3903 src1 : Z_RF(read);
3904 src2 : Z_RF(read);
3905 Z_FX : Z_RF;
3906 %}
3907
3908 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
3909 single_instruction;
3910 mem : Z_RF(read);
3911 dst : Z_WB(write);
3912 Z_LDST : Z_RF;
3913 %}
3914
3915 define %{
3916 MachNop = pipe_class_dummy;
3917 %}
3918
3919 %}
3920
3921 //----------INSTRUCTIONS-------------------------------------------------------
3922
3923 //---------- Chain stack slots between similar types --------
3924
3925 // Load integer from stack slot.
3926 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
3927 match(Set dst src);
3928 ins_cost(MEMORY_REF_COST);
3929 // TODO: s390 port size(FIXED_SIZE);
3930 format %{ "L $dst,$src\t # stk reload int" %}
3931 opcode(L_ZOPC);
3932 ins_encode(z_form_rt_mem(dst, src));
3933 ins_pipe(pipe_class_dummy);
3934 %}
3935
3936 // Store integer to stack slot.
3937 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
3938 match(Set dst src);
3939 ins_cost(MEMORY_REF_COST);
3940 // TODO: s390 port size(FIXED_SIZE);
3941 format %{ "ST $src,$dst\t # stk spill int" %}
3942 opcode(ST_ZOPC);
3943 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3944 ins_pipe(pipe_class_dummy);
3945 %}
3946
3947 // Load long from stack slot.
3948 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
3949 match(Set dst src);
3950 ins_cost(MEMORY_REF_COST);
3951 // TODO: s390 port size(FIXED_SIZE);
3952 format %{ "LG $dst,$src\t # stk reload long" %}
3953 opcode(LG_ZOPC);
3954 ins_encode(z_form_rt_mem(dst, src));
3955 ins_pipe(pipe_class_dummy);
3956 %}
3957
3958 // Store long to stack slot.
3959 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
3960 match(Set dst src);
3961 ins_cost(MEMORY_REF_COST);
3962 size(6);
3963 format %{ "STG $src,$dst\t # stk spill long" %}
3964 opcode(STG_ZOPC);
3965 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3966 ins_pipe(pipe_class_dummy);
3967 %}
3968
3969 // Load pointer from stack slot, 64-bit encoding.
3970 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
3971 match(Set dst src);
3972 ins_cost(MEMORY_REF_COST);
3973 // TODO: s390 port size(FIXED_SIZE);
3974 format %{ "LG $dst,$src\t # stk reload ptr" %}
3975 opcode(LG_ZOPC);
3976 ins_encode(z_form_rt_mem(dst, src));
3977 ins_pipe(pipe_class_dummy);
3978 %}
3979
3980 // Store pointer to stack slot.
3981 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
3982 match(Set dst src);
3983 ins_cost(MEMORY_REF_COST);
3984 // TODO: s390 port size(FIXED_SIZE);
3985 format %{ "STG $src,$dst\t # stk spill ptr" %}
3986 opcode(STG_ZOPC);
3987 ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3988 ins_pipe(pipe_class_dummy);
3989 %}
3990
3991 // Float types
3992
3993 // Load float value from stack slot.
3994 instruct stkF_to_regF(regF dst, stackSlotF src) %{
3995 match(Set dst src);
3996 ins_cost(MEMORY_REF_COST);
3997 size(4);
3998 format %{ "LE(Y) $dst,$src\t # stk reload float" %}
3999 opcode(LE_ZOPC);
4000 ins_encode(z_form_rt_mem(dst, src));
4001 ins_pipe(pipe_class_dummy);
4002 %}
4003
4004 // Store float value to stack slot.
4005 instruct regF_to_stkF(stackSlotF dst, regF src) %{
4006 match(Set dst src);
4007 ins_cost(MEMORY_REF_COST);
4008 size(4);
4009 format %{ "STE(Y) $src,$dst\t # stk spill float" %}
4010 opcode(STE_ZOPC);
4011 ins_encode(z_form_rt_mem(src, dst));
4012 ins_pipe(pipe_class_dummy);
4013 %}
4014
4015 // Load double value from stack slot.
4016 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4017 match(Set dst src);
4018 ins_cost(MEMORY_REF_COST);
4019 // TODO: s390 port size(FIXED_SIZE);
4020 format %{ "LD(Y) $dst,$src\t # stk reload double" %}
4021 opcode(LD_ZOPC);
4022 ins_encode(z_form_rt_mem(dst, src));
4023 ins_pipe(pipe_class_dummy);
4024 %}
4025
4026 // Store double value to stack slot.
4027 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4028 match(Set dst src);
4029 ins_cost(MEMORY_REF_COST);
4030 size(4);
4031 format %{ "STD(Y) $src,$dst\t # stk spill double" %}
4032 opcode(STD_ZOPC);
4033 ins_encode(z_form_rt_mem(src, dst));
4034 ins_pipe(pipe_class_dummy);
4035 %}
4036
4037 //----------Load/Store/Move Instructions---------------------------------------
4038
4039 //----------Load Instructions--------------------------------------------------
4040
4041 //------------------
4042 // MEMORY
4043 //------------------
4044
4045 // BYTE
4046 // Load Byte (8bit signed)
4047 instruct loadB(iRegI dst, memory mem) %{
4048 match(Set dst (LoadB mem));
4049 ins_cost(MEMORY_REF_COST);
4050 size(Z_DISP3_SIZE);
4051 format %{ "LB $dst, $mem\t # sign-extend byte to int" %}
4052 opcode(LB_ZOPC, LB_ZOPC);
4053 ins_encode(z_form_rt_mem_opt(dst, mem));
4054 ins_pipe(pipe_class_dummy);
4055 %}
4056
4057 // Load Byte (8bit signed)
4058 instruct loadB2L(iRegL dst, memory mem) %{
4059 match(Set dst (ConvI2L (LoadB mem)));
4060 ins_cost(MEMORY_REF_COST);
4061 size(Z_DISP3_SIZE);
4062 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %}
4063 opcode(LGB_ZOPC, LGB_ZOPC);
4064 ins_encode(z_form_rt_mem_opt(dst, mem));
4065 ins_pipe(pipe_class_dummy);
4066 %}
4067
4068 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4069 instruct loadUB(iRegI dst, memory mem) %{
4070 match(Set dst (LoadUB mem));
4071 ins_cost(MEMORY_REF_COST);
4072 size(Z_DISP3_SIZE);
4073 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %}
4074 opcode(LLGC_ZOPC, LLGC_ZOPC);
4075 ins_encode(z_form_rt_mem_opt(dst, mem));
4076 ins_pipe(pipe_class_dummy);
4077 %}
4078
4079 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4080 instruct loadUB2L(iRegL dst, memory mem) %{
4081 match(Set dst (ConvI2L (LoadUB mem)));
4082 ins_cost(MEMORY_REF_COST);
4083 size(Z_DISP3_SIZE);
4084 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %}
4085 opcode(LLGC_ZOPC, LLGC_ZOPC);
4086 ins_encode(z_form_rt_mem_opt(dst, mem));
4087 ins_pipe(pipe_class_dummy);
4088 %}
4089
4090 // CHAR/SHORT
4091
4092 // Load Short (16bit signed)
4093 instruct loadS(iRegI dst, memory mem) %{
4094 match(Set dst (LoadS mem));
4095 ins_cost(MEMORY_REF_COST);
4096 size(Z_DISP_SIZE);
4097 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %}
4098 opcode(LHY_ZOPC, LH_ZOPC);
4099 ins_encode(z_form_rt_mem_opt(dst, mem));
4100 ins_pipe(pipe_class_dummy);
4101 %}
4102
4103 // Load Short (16bit signed)
4104 instruct loadS2L(iRegL dst, memory mem) %{
4105 match(Set dst (ConvI2L (LoadS mem)));
4106 ins_cost(MEMORY_REF_COST);
4107 size(Z_DISP3_SIZE);
4108 format %{ "LGH $dst,$mem\t # sign-extend short to long" %}
4109 opcode(LGH_ZOPC, LGH_ZOPC);
4110 ins_encode(z_form_rt_mem_opt(dst, mem));
4111 ins_pipe(pipe_class_dummy);
4112 %}
4113
4114 // Load Char (16bit Unsigned)
4115 instruct loadUS(iRegI dst, memory mem) %{
4116 match(Set dst (LoadUS mem));
4117 ins_cost(MEMORY_REF_COST);
4118 size(Z_DISP3_SIZE);
4119 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %}
4120 opcode(LLGH_ZOPC, LLGH_ZOPC);
4121 ins_encode(z_form_rt_mem_opt(dst, mem));
4122 ins_pipe(pipe_class_dummy);
4123 %}
4124
4125 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4126 instruct loadUS2L(iRegL dst, memory mem) %{
4127 match(Set dst (ConvI2L (LoadUS mem)));
4128 ins_cost(MEMORY_REF_COST);
4129 size(Z_DISP3_SIZE);
4130 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %}
4131 opcode(LLGH_ZOPC, LLGH_ZOPC);
4132 ins_encode(z_form_rt_mem_opt(dst, mem));
4133 ins_pipe(pipe_class_dummy);
4134 %}
4135
4136 // INT
4137
4138 // Load Integer
4139 instruct loadI(iRegI dst, memory mem) %{
4140 match(Set dst (LoadI mem));
4141 ins_cost(MEMORY_REF_COST);
4142 size(Z_DISP_SIZE);
4143 format %{ "L(Y) $dst,$mem\t #" %}
4144 opcode(LY_ZOPC, L_ZOPC);
4145 ins_encode(z_form_rt_mem_opt(dst, mem));
4146 ins_pipe(pipe_class_dummy);
4147 %}
4148
4149 // Load and convert to long.
4150 instruct loadI2L(iRegL dst, memory mem) %{
4151 match(Set dst (ConvI2L (LoadI mem)));
4152 ins_cost(MEMORY_REF_COST);
4153 size(Z_DISP3_SIZE);
4154 format %{ "LGF $dst,$mem\t #" %}
4155 opcode(LGF_ZOPC, LGF_ZOPC);
4156 ins_encode(z_form_rt_mem_opt(dst, mem));
4157 ins_pipe(pipe_class_dummy);
4158 %}
4159
4160 // Load Unsigned Integer into a Long Register
4161 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4162 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4163 ins_cost(MEMORY_REF_COST);
4164 size(Z_DISP3_SIZE);
4165 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %}
4166 opcode(LLGF_ZOPC, LLGF_ZOPC);
4167 ins_encode(z_form_rt_mem_opt(dst, mem));
4168 ins_pipe(pipe_class_dummy);
4169 %}
4170
4171 // range = array length (=jint)
4172 // Load Range
4173 instruct loadRange(iRegI dst, memory mem) %{
4174 match(Set dst (LoadRange mem));
4175 ins_cost(MEMORY_REF_COST);
4176 size(Z_DISP_SIZE);
4177 format %{ "L(Y) $dst,$mem\t # range" %}
4178 opcode(LY_ZOPC, L_ZOPC);
4179 ins_encode(z_form_rt_mem_opt(dst, mem));
4180 ins_pipe(pipe_class_dummy);
4181 %}
4182
4183 // LONG
4184
4185 // Load Long - aligned
4186 instruct loadL(iRegL dst, memory mem) %{
4187 match(Set dst (LoadL mem));
4188 ins_cost(MEMORY_REF_COST);
4189 size(Z_DISP3_SIZE);
4190 format %{ "LG $dst,$mem\t # long" %}
4191 opcode(LG_ZOPC, LG_ZOPC);
4192 ins_encode(z_form_rt_mem_opt(dst, mem));
4193 ins_pipe(pipe_class_dummy);
4194 %}
4195
4196 // Load Long - UNaligned
4197 instruct loadL_unaligned(iRegL dst, memory mem) %{
4198 match(Set dst (LoadL_unaligned mem));
4199 ins_cost(MEMORY_REF_COST);
4200 size(Z_DISP3_SIZE);
4201 format %{ "LG $dst,$mem\t # unaligned long" %}
4202 opcode(LG_ZOPC, LG_ZOPC);
4203 ins_encode(z_form_rt_mem_opt(dst, mem));
4204 ins_pipe(pipe_class_dummy);
4205 %}
4206
4207
4208 // PTR
4209
4210 // Load Pointer
4211 instruct loadP(iRegP dst, memory mem) %{
4212 match(Set dst (LoadP mem));
4213 ins_cost(MEMORY_REF_COST);
4214 size(Z_DISP3_SIZE);
4215 format %{ "LG $dst,$mem\t # ptr" %}
4216 opcode(LG_ZOPC, LG_ZOPC);
4217 ins_encode(z_form_rt_mem_opt(dst, mem));
4218 ins_pipe(pipe_class_dummy);
4219 %}
4220
4221 // LoadP + CastP2L
4222 instruct castP2X_loadP(iRegL dst, memory mem) %{
4223 match(Set dst (CastP2X (LoadP mem)));
4224 ins_cost(MEMORY_REF_COST);
4225 size(Z_DISP3_SIZE);
4226 format %{ "LG $dst,$mem\t # ptr + p2x" %}
4227 opcode(LG_ZOPC, LG_ZOPC);
4228 ins_encode(z_form_rt_mem_opt(dst, mem));
4229 ins_pipe(pipe_class_dummy);
4230 %}
4231
4232 // Load Klass Pointer
4233 instruct loadKlass(iRegP dst, memory mem) %{
4234 match(Set dst (LoadKlass mem));
4235 ins_cost(MEMORY_REF_COST);
4236 size(Z_DISP3_SIZE);
4237 format %{ "LG $dst,$mem\t # klass ptr" %}
4238 opcode(LG_ZOPC, LG_ZOPC);
4239 ins_encode(z_form_rt_mem_opt(dst, mem));
4240 ins_pipe(pipe_class_dummy);
4241 %}
4242
4243 instruct loadTOC(iRegL dst) %{
4244 effect(DEF dst);
4245 ins_cost(DEFAULT_COST);
4246 // TODO: s390 port size(FIXED_SIZE);
4247 // TODO: check why this attribute causes many unnecessary rematerializations.
4248 //
4249 // The graphs I saw just had high register pressure. Further the
4250 // register TOC is loaded to is overwritten by the constant short
4251 // after. Here something as round robin register allocation might
4252 // help. But rematerializing seems not to hurt, jack even seems to
4253 // improve slightly.
4254 //
4255 // Without this flag we get spill-split recycle sanity check
4256 // failures in
4257 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4258 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4259 // tlsLoadP has a huge amount of outs and forces the TOC down to the
4260 // stack. Later tlsLoadP is rematerialized, leaving the register
4261 // allocator with TOC on the stack and a badly placed reload.
4262 ins_should_rematerialize(true);
4263 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %}
4264 ins_encode %{ __ load_toc($dst$$Register); %}
4265 ins_pipe(pipe_class_dummy);
4266 %}
4267
4268 // FLOAT
4269
4270 // Load Float
4271 instruct loadF(regF dst, memory mem) %{
4272 match(Set dst (LoadF mem));
4273 ins_cost(MEMORY_REF_COST);
4274 size(Z_DISP_SIZE);
4275 format %{ "LE(Y) $dst,$mem" %}
4276 opcode(LEY_ZOPC, LE_ZOPC);
4277 ins_encode(z_form_rt_mem_opt(dst, mem));
4278 ins_pipe(pipe_class_dummy);
4279 %}
4280
4281 // DOUBLE
4282
4283 // Load Double
4284 instruct loadD(regD dst, memory mem) %{
4285 match(Set dst (LoadD mem));
4286 ins_cost(MEMORY_REF_COST);
4287 size(Z_DISP_SIZE);
4288 format %{ "LD(Y) $dst,$mem" %}
4289 opcode(LDY_ZOPC, LD_ZOPC);
4290 ins_encode(z_form_rt_mem_opt(dst, mem));
4291 ins_pipe(pipe_class_dummy);
4292 %}
4293
4294 // Load Double - UNaligned
4295 instruct loadD_unaligned(regD dst, memory mem) %{
4296 match(Set dst (LoadD_unaligned mem));
4297 ins_cost(MEMORY_REF_COST);
4298 size(Z_DISP_SIZE);
4299 format %{ "LD(Y) $dst,$mem" %}
4300 opcode(LDY_ZOPC, LD_ZOPC);
4301 ins_encode(z_form_rt_mem_opt(dst, mem));
4302 ins_pipe(pipe_class_dummy);
4303 %}
4304
4305
4306 //----------------------
4307 // IMMEDIATES
4308 //----------------------
4309
4310 instruct loadConI(iRegI dst, immI src) %{
4311 match(Set dst src);
4312 ins_cost(DEFAULT_COST);
4313 size(6);
4314 format %{ "LGFI $dst,$src\t # (int)" %}
4315 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4316 ins_pipe(pipe_class_dummy);
4317 %}
4318
4319 instruct loadConI16(iRegI dst, immI16 src) %{
4320 match(Set dst src);
4321 ins_cost(DEFAULT_COST_LOW);
4322 size(4);
4323 format %{ "LGHI $dst,$src\t # (int)" %}
4324 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4325 ins_pipe(pipe_class_dummy);
4326 %}
4327
4328 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4329 match(Set dst src);
4330 effect(KILL cr);
4331 ins_cost(DEFAULT_COST_LOW);
4332 size(4);
4333 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4334 opcode(XGR_ZOPC);
4335 ins_encode(z_rreform(dst, dst));
4336 ins_pipe(pipe_class_dummy);
4337 %}
4338
4339 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4340 match(Set dst src);
4341 // TODO: s390 port size(FIXED_SIZE);
4342 format %{ "LLILL $dst,$src" %}
4343 opcode(LLILL_ZOPC);
4344 ins_encode(z_riform_unsigned(dst, src) );
4345 ins_pipe(pipe_class_dummy);
4346 %}
4347
4348 // Load long constant from TOC with pcrelative address.
4349 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4350 match(Set dst src);
4351 ins_cost(MEMORY_REF_COST_LO);
4352 size(6);
4353 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %}
4354 ins_encode %{
4355 address long_address = __ long_constant($src$$constant);
4356 if (long_address == NULL) {
4357 Compile::current()->env()->record_out_of_memory_failure();
4358 return;
4359 }
4360 __ load_long_pcrelative($dst$$Register, long_address);
4361 %}
4362 ins_pipe(pipe_class_dummy);
4363 %}
4364
4365 instruct loadConL32(iRegL dst, immL32 src) %{
4366 match(Set dst src);
4367 ins_cost(DEFAULT_COST);
4368 size(6);
4369 format %{ "LGFI $dst,$src\t # (long)" %}
4370 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4371 ins_pipe(pipe_class_dummy);
4372 %}
4373
4374 instruct loadConL16(iRegL dst, immL16 src) %{
4375 match(Set dst src);
4376 ins_cost(DEFAULT_COST_LOW);
4377 size(4);
4378 format %{ "LGHI $dst,$src\t # (long)" %}
4379 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost.
4380 ins_pipe(pipe_class_dummy);
4381 %}
4382
4383 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4384 match(Set dst src);
4385 effect(KILL cr);
4386 ins_cost(DEFAULT_COST_LOW);
4387 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %}
4388 opcode(XGR_ZOPC);
4389 ins_encode(z_rreform(dst, dst));
4390 ins_pipe(pipe_class_dummy);
4391 %}
4392
4393 // Load ptr constant from TOC with pc relative address.
4394 // Special handling for oop constants required.
4395 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4396 match(Set dst src);
4397 ins_cost(MEMORY_REF_COST_LO);
4398 size(6);
4399 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %}
4400 ins_encode %{
4401 relocInfo::relocType constant_reloc = $src->constant_reloc();
4402 if (constant_reloc == relocInfo::oop_type) {
4403 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4404 bool success = __ load_oop_from_toc($dst$$Register, a);
4405 if (!success) {
4406 Compile::current()->env()->record_out_of_memory_failure();
4407 return;
4408 }
4409 } else if (constant_reloc == relocInfo::metadata_type) {
4410 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4411 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4412 if (const_toc_addr == NULL) {
4413 Compile::current()->env()->record_out_of_memory_failure();
4414 return;
4415 }
4416 __ load_long_pcrelative($dst$$Register, const_toc_addr);
4417 } else { // Non-oop pointers, e.g. card mark base, heap top.
4418 address long_address = __ long_constant((jlong)$src$$constant);
4419 if (long_address == NULL) {
4420 Compile::current()->env()->record_out_of_memory_failure();
4421 return;
4422 }
4423 __ load_long_pcrelative($dst$$Register, long_address);
4424 }
4425 %}
4426 ins_pipe(pipe_class_dummy);
4427 %}
4428
4429 // We don't use immP16 to avoid problems with oops.
4430 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4431 match(Set dst src);
4432 effect(KILL cr);
4433 size(4);
4434 format %{ "XGR $dst,$dst\t # NULL ptr" %}
4435 opcode(XGR_ZOPC);
4436 ins_encode(z_rreform(dst, dst));
4437 ins_pipe(pipe_class_dummy);
4438 %}
4439
4440 //----------Load Float Constant Instructions-------------------------------------------------
4441
4442 // We may not specify this instruction via an `expand' rule. If we do,
4443 // code selection will forget that this instruction needs a floating
4444 // point constant inserted into the code buffer. So `Shorten_branches'
4445 // will fail.
4446 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4447 match(Set dst src);
4448 effect(KILL cr);
4449 ins_cost(MEMORY_REF_COST);
4450 size(6);
4451 // If this instruction rematerializes, it prolongs the live range
4452 // of the toc node, causing illegal graphs.
4453 ins_cannot_rematerialize(true);
4454 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4455 ins_encode %{
4456 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4457 %}
4458 ins_pipe(pipe_class_dummy);
4459 %}
4460
4461 // E may not specify this instruction via an `expand' rule. If we do,
4462 // code selection will forget that this instruction needs a floating
4463 // point constant inserted into the code buffer. So `Shorten_branches'
4464 // will fail.
4465 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4466 match(Set dst src);
4467 effect(KILL cr);
4468 ins_cost(MEMORY_REF_COST);
4469 size(6);
4470 // If this instruction rematerializes, it prolongs the live range
4471 // of the toc node, causing illegal graphs.
4472 ins_cannot_rematerialize(true);
4473 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4474 ins_encode %{
4475 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4476 %}
4477 ins_pipe(pipe_class_dummy);
4478 %}
4479
4480 // Special case: Load Const 0.0F
4481
4482 // There's a special instr to clear a FP register.
4483 instruct loadConF0(regF dst, immFp0 src) %{
4484 match(Set dst src);
4485 ins_cost(DEFAULT_COST_LOW);
4486 size(4);
4487 format %{ "LZER $dst,$src\t # clear to zero" %}
4488 opcode(LZER_ZOPC);
4489 ins_encode(z_rreform(dst, Z_F0));
4490 ins_pipe(pipe_class_dummy);
4491 %}
4492
4493 // There's a special instr to clear a FP register.
4494 instruct loadConD0(regD dst, immDp0 src) %{
4495 match(Set dst src);
4496 ins_cost(DEFAULT_COST_LOW);
4497 size(4);
4498 format %{ "LZDR $dst,$src\t # clear to zero" %}
4499 opcode(LZDR_ZOPC);
4500 ins_encode(z_rreform(dst, Z_F0));
4501 ins_pipe(pipe_class_dummy);
4502 %}
4503
4504
4505 //----------Store Instructions-------------------------------------------------
4506
4507 // BYTE
4508
4509 // Store Byte
4510 instruct storeB(memory mem, iRegI src) %{
4511 match(Set mem (StoreB mem src));
4512 ins_cost(MEMORY_REF_COST);
4513 size(Z_DISP_SIZE);
4514 format %{ "STC(Y) $src,$mem\t # byte" %}
4515 opcode(STCY_ZOPC, STC_ZOPC);
4516 ins_encode(z_form_rt_mem_opt(src, mem));
4517 ins_pipe(pipe_class_dummy);
4518 %}
4519
4520 instruct storeCM(memory mem, immI_0 src) %{
4521 match(Set mem (StoreCM mem src));
4522 ins_cost(MEMORY_REF_COST);
4523 // TODO: s390 port size(VARIABLE_SIZE);
4524 format %{ "STC(Y) $src,$mem\t # CMS card-mark byte (must be 0!)" %}
4525 ins_encode %{
4526 guarantee($mem$$index$$Register != Z_R0, "content will not be used.");
4527 if ($mem$$index$$Register != noreg) {
4528 // Can't use clear_mem --> load const zero and store character.
4529 __ load_const_optimized(Z_R0_scratch, (long)0);
4530 if (Immediate::is_uimm12($mem$$disp)) {
4531 __ z_stc(Z_R0_scratch, $mem$$Address);
4532 } else {
4533 __ z_stcy(Z_R0_scratch, $mem$$Address);
4534 }
4535 } else {
4536 __ clear_mem(Address($mem$$Address), 1);
4537 }
4538 %}
4539 ins_pipe(pipe_class_dummy);
4540 %}
4541
4542 // CHAR/SHORT
4543
4544 // Store Char/Short
4545 instruct storeC(memory mem, iRegI src) %{
4546 match(Set mem (StoreC mem src));
4547 ins_cost(MEMORY_REF_COST);
4548 size(Z_DISP_SIZE);
4549 format %{ "STH(Y) $src,$mem\t # short" %}
4550 opcode(STHY_ZOPC, STH_ZOPC);
4551 ins_encode(z_form_rt_mem_opt(src, mem));
4552 ins_pipe(pipe_class_dummy);
4553 %}
4554
4555 // INT
4556
4557 // Store Integer
4558 instruct storeI(memory mem, iRegI src) %{
4559 match(Set mem (StoreI mem src));
4560 ins_cost(MEMORY_REF_COST);
4561 size(Z_DISP_SIZE);
4562 format %{ "ST(Y) $src,$mem\t # int" %}
4563 opcode(STY_ZOPC, ST_ZOPC);
4564 ins_encode(z_form_rt_mem_opt(src, mem));
4565 ins_pipe(pipe_class_dummy);
4566 %}
4567
4568 // LONG
4569
4570 // Store Long
4571 instruct storeL(memory mem, iRegL src) %{
4572 match(Set mem (StoreL mem src));
4573 ins_cost(MEMORY_REF_COST);
4574 size(Z_DISP3_SIZE);
4575 format %{ "STG $src,$mem\t # long" %}
4576 opcode(STG_ZOPC, STG_ZOPC);
4577 ins_encode(z_form_rt_mem_opt(src, mem));
4578 ins_pipe(pipe_class_dummy);
4579 %}
4580
4581 // PTR
4582
4583 // Store Pointer
4584 instruct storeP(memory dst, memoryRegP src) %{
4585 match(Set dst (StoreP dst src));
4586 ins_cost(MEMORY_REF_COST);
4587 size(Z_DISP3_SIZE);
4588 format %{ "STG $src,$dst\t # ptr" %}
4589 opcode(STG_ZOPC, STG_ZOPC);
4590 ins_encode(z_form_rt_mem_opt(src, dst));
4591 ins_pipe(pipe_class_dummy);
4592 %}
4593
4594 // FLOAT
4595
4596 // Store Float
4597 instruct storeF(memory mem, regF src) %{
4598 match(Set mem (StoreF mem src));
4599 ins_cost(MEMORY_REF_COST);
4600 size(Z_DISP_SIZE);
4601 format %{ "STE(Y) $src,$mem\t # float" %}
4602 opcode(STEY_ZOPC, STE_ZOPC);
4603 ins_encode(z_form_rt_mem_opt(src, mem));
4604 ins_pipe(pipe_class_dummy);
4605 %}
4606
4607 // DOUBLE
4608
4609 // Store Double
4610 instruct storeD(memory mem, regD src) %{
4611 match(Set mem (StoreD mem src));
4612 ins_cost(MEMORY_REF_COST);
4613 size(Z_DISP_SIZE);
4614 format %{ "STD(Y) $src,$mem\t # double" %}
4615 opcode(STDY_ZOPC, STD_ZOPC);
4616 ins_encode(z_form_rt_mem_opt(src, mem));
4617 ins_pipe(pipe_class_dummy);
4618 %}
4619
4620 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4621
4622 // Should support match rule for PrefetchAllocation.
4623 // Still needed after 8068977 for PrefetchAllocate.
4624 instruct prefetchAlloc(memory mem) %{
4625 match(PrefetchAllocation mem);
4626 predicate(VM_Version::has_Prefetch());
4627 ins_cost(DEFAULT_COST);
4628 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4629 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4630 ins_pipe(pipe_class_dummy);
4631 %}
4632
4633 //----------Memory init instructions------------------------------------------
4634
4635 // Move Immediate to 1-byte memory.
4636 instruct memInitB(memoryRSY mem, immI8 src) %{
4637 match(Set mem (StoreB mem src));
4638 ins_cost(MEMORY_REF_COST);
4639 // TODO: s390 port size(VARIABLE_SIZE);
4640 format %{ "MVI $mem,$src\t # direct mem init 1" %}
4641 ins_encode %{
4642 if (Immediate::is_uimm12((long)$mem$$disp)) {
4643 __ z_mvi($mem$$Address, $src$$constant);
4644 } else {
4645 __ z_mviy($mem$$Address, $src$$constant);
4646 }
4647 %}
4648 ins_pipe(pipe_class_dummy);
4649 %}
4650
4651 // Move Immediate to 2-byte memory.
4652 instruct memInitC(memoryRS mem, immI16 src) %{
4653 match(Set mem (StoreC mem src));
4654 ins_cost(MEMORY_REF_COST);
4655 size(6);
4656 format %{ "MVHHI $mem,$src\t # direct mem init 2" %}
4657 opcode(MVHHI_ZOPC);
4658 ins_encode(z_silform(mem, src));
4659 ins_pipe(pipe_class_dummy);
4660 %}
4661
4662 // Move Immediate to 4-byte memory.
4663 instruct memInitI(memoryRS mem, immI16 src) %{
4664 match(Set mem (StoreI mem src));
4665 ins_cost(MEMORY_REF_COST);
4666 size(6);
4667 format %{ "MVHI $mem,$src\t # direct mem init 4" %}
4668 opcode(MVHI_ZOPC);
4669 ins_encode(z_silform(mem, src));
4670 ins_pipe(pipe_class_dummy);
4671 %}
4672
4673
4674 // Move Immediate to 8-byte memory.
4675 instruct memInitL(memoryRS mem, immL16 src) %{
4676 match(Set mem (StoreL mem src));
4677 ins_cost(MEMORY_REF_COST);
4678 size(6);
4679 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4680 opcode(MVGHI_ZOPC);
4681 ins_encode(z_silform(mem, src));
4682 ins_pipe(pipe_class_dummy);
4683 %}
4684
4685 // Move Immediate to 8-byte memory.
4686 instruct memInitP(memoryRS mem, immP16 src) %{
4687 match(Set mem (StoreP mem src));
4688 ins_cost(MEMORY_REF_COST);
4689 size(6);
4690 format %{ "MVGHI $mem,$src\t # direct mem init 8" %}
4691 opcode(MVGHI_ZOPC);
4692 ins_encode(z_silform(mem, src));
4693 ins_pipe(pipe_class_dummy);
4694 %}
4695
4696
4697 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4698
4699 // See cOop encoding classes for elaborate comment.
4700
4701 // Moved here because it is needed in expand rules for encode.
4702 // Long negation.
4703 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4704 match(Set dst (SubL zero src));
4705 effect(KILL cr);
4706 size(4);
4707 format %{ "NEG $dst, $src\t # long" %}
4708 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4709 ins_pipe(pipe_class_dummy);
4710 %}
4711
4712 // Load Compressed Pointer
4713
4714 // Load narrow oop
4715 instruct loadN(iRegN dst, memory mem) %{
4716 match(Set dst (LoadN mem));
4717 ins_cost(MEMORY_REF_COST);
4718 size(Z_DISP3_SIZE);
4719 format %{ "LoadN $dst,$mem\t# (cOop)" %}
4720 opcode(LLGF_ZOPC, LLGF_ZOPC);
4721 ins_encode(z_form_rt_mem_opt(dst, mem));
4722 ins_pipe(pipe_class_dummy);
4723 %}
4724
4725 // Load narrow Klass Pointer
4726 instruct loadNKlass(iRegN dst, memory mem) %{
4727 match(Set dst (LoadNKlass mem));
4728 ins_cost(MEMORY_REF_COST);
4729 size(Z_DISP3_SIZE);
4730 format %{ "LoadNKlass $dst,$mem\t# (klass cOop)" %}
4731 opcode(LLGF_ZOPC, LLGF_ZOPC);
4732 ins_encode(z_form_rt_mem_opt(dst, mem));
4733 ins_pipe(pipe_class_dummy);
4734 %}
4735
4736 // Load constant Compressed Pointer
4737
4738 instruct loadConN(iRegN dst, immN src) %{
4739 match(Set dst src);
4740 ins_cost(DEFAULT_COST);
4741 size(6);
4742 format %{ "loadConN $dst,$src\t # (cOop)" %}
4743 ins_encode %{
4744 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4745 __ relocate(cOop.rspec(), 1);
4746 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4747 %}
4748 ins_pipe(pipe_class_dummy);
4749 %}
4750
4751 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4752 match(Set dst src);
4753 effect(KILL cr);
4754 ins_cost(DEFAULT_COST_LOW);
4755 size(4);
4756 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4757 opcode(XGR_ZOPC);
4758 ins_encode(z_rreform(dst, dst));
4759 ins_pipe(pipe_class_dummy);
4760 %}
4761
4762 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4763 match(Set dst src);
4764 ins_cost(DEFAULT_COST);
4765 size(6);
4766 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4767 ins_encode %{
4768 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4769 __ relocate(NKlass.rspec(), 1);
4770 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4771 %}
4772 ins_pipe(pipe_class_dummy);
4773 %}
4774
4775 // Load and Decode Compressed Pointer
4776 // optimized variants for Unscaled cOops
4777
4778 instruct decodeLoadN(iRegP dst, memory mem) %{
4779 match(Set dst (DecodeN (LoadN mem)));
4780 predicate(false && (Universe::narrow_oop_base()==NULL)&&(Universe::narrow_oop_shift()==0));
4781 ins_cost(MEMORY_REF_COST);
4782 size(Z_DISP3_SIZE);
4783 format %{ "DecodeLoadN $dst,$mem\t# (cOop Load+Decode)" %}
4784 opcode(LLGF_ZOPC, LLGF_ZOPC);
4785 ins_encode(z_form_rt_mem_opt(dst, mem));
4786 ins_pipe(pipe_class_dummy);
4787 %}
4788
4789 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4790 match(Set dst (DecodeNKlass (LoadNKlass mem)));
4791 predicate(false && (Universe::narrow_klass_base()==NULL)&&(Universe::narrow_klass_shift()==0));
4792 ins_cost(MEMORY_REF_COST);
4793 size(Z_DISP3_SIZE);
4794 format %{ "DecodeLoadNKlass $dst,$mem\t# (load/decode NKlass)" %}
4795 opcode(LLGF_ZOPC, LLGF_ZOPC);
4796 ins_encode(z_form_rt_mem_opt(dst, mem));
4797 ins_pipe(pipe_class_dummy);
4798 %}
4799
4800 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4801 match(Set dst (DecodeNKlass src));
4802 ins_cost(3 * DEFAULT_COST);
4803 size(12);
4804 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %}
4805 ins_encode %{
4806 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4807 __ relocate(NKlass.rspec(), 1);
4808 __ load_const($dst$$Register, (Klass*)NKlass.value());
4809 %}
4810 ins_pipe(pipe_class_dummy);
4811 %}
4812
4813 // Decode Compressed Pointer
4814
4815 // General decoder
4816 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4817 match(Set dst (DecodeN src));
4818 effect(KILL cr);
4819 predicate(Universe::narrow_oop_base() == NULL || !ExpandLoadingBaseDecode);
4820 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4821 // TODO: s390 port size(VARIABLE_SIZE);
4822 format %{ "decodeN $dst,$src\t# (decode cOop)" %}
4823 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %}
4824 ins_pipe(pipe_class_dummy);
4825 %}
4826
4827 // General Klass decoder
4828 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4829 match(Set dst (DecodeNKlass src));
4830 effect(KILL cr);
4831 ins_cost(3 * DEFAULT_COST);
4832 format %{ "decode_klass $dst,$src" %}
4833 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4834 ins_pipe(pipe_class_dummy);
4835 %}
4836
4837 // General decoder
4838 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4839 match(Set dst (DecodeN src));
4840 effect(KILL cr);
4841 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4842 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4843 (Universe::narrow_oop_base()== NULL || !ExpandLoadingBaseDecode_NN));
4844 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4845 // TODO: s390 port size(VARIABLE_SIZE);
4846 format %{ "decodeN $dst,$src\t# (decode cOop NN)" %}
4847 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4848 ins_pipe(pipe_class_dummy);
4849 %}
4850
4851 instruct loadBase(iRegL dst, immL baseImm) %{
4852 effect(DEF dst, USE baseImm);
4853 predicate(false);
4854 format %{ "llihl $dst=$baseImm \t// load heap base" %}
4855 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4856 ins_pipe(pipe_class_dummy);
4857 %}
4858
4859 // Decoder for heapbased mode peeling off loading the base.
4860 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4861 match(Set dst (DecodeN src base));
4862 // Note: Effect TEMP dst was used with the intention to get
4863 // different regs for dst and base, but this has caused ADLC to
4864 // generate wrong code. Oop_decoder generates additional lgr when
4865 // dst==base.
4866 effect(KILL cr);
4867 predicate(false);
4868 // TODO: s390 port size(VARIABLE_SIZE);
4869 format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t# (decode cOop)" %}
4870 ins_encode %{
4871 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4872 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base()));
4873 %}
4874 ins_pipe(pipe_class_dummy);
4875 %}
4876
4877 // Decoder for heapbased mode peeling off loading the base.
4878 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4879 match(Set dst (DecodeN src base));
4880 effect(KILL cr);
4881 predicate(false);
4882 // TODO: s390 port size(VARIABLE_SIZE);
4883 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t# (decode cOop)" %}
4884 ins_encode %{
4885 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
4886 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base()));
4887 %}
4888 ins_pipe(pipe_class_dummy);
4889 %}
4890
4891 // Decoder for heapbased mode peeling off loading the base.
4892 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4893 match(Set dst (DecodeN src));
4894 predicate(Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode);
4895 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4896 // TODO: s390 port size(VARIABLE_SIZE);
4897 expand %{
4898 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
4899 iRegL base;
4900 loadBase(base, baseImm);
4901 decodeN_base(dst, src, base, cr);
4902 %}
4903 %}
4904
4905 // Decoder for heapbased mode peeling off loading the base.
4906 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4907 match(Set dst (DecodeN src));
4908 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4909 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4910 Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode_NN);
4911 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4912 // TODO: s390 port size(VARIABLE_SIZE);
4913 expand %{
4914 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
4915 iRegL base;
4916 loadBase(base, baseImm);
4917 decodeN_NN_base(dst, src, base, cr);
4918 %}
4919 %}
4920
4921 // Encode Compressed Pointer
4922
4923 // General encoder
4924 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
4925 match(Set dst (EncodeP src));
4926 effect(KILL cr);
4927 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
4928 (Universe::narrow_oop_base() == 0 ||
4929 Universe::narrow_oop_base_disjoint() ||
4930 !ExpandLoadingBaseEncode));
4931 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4932 // TODO: s390 port size(VARIABLE_SIZE);
4933 format %{ "encodeP $dst,$src\t# (encode cOop)" %}
4934 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4935 ins_pipe(pipe_class_dummy);
4936 %}
4937
4938 // General class encoder
4939 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
4940 match(Set dst (EncodePKlass src));
4941 effect(KILL cr);
4942 format %{ "encode_klass $dst,$src" %}
4943 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
4944 ins_pipe(pipe_class_dummy);
4945 %}
4946
4947 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
4948 match(Set dst (EncodeP src));
4949 effect(KILL cr);
4950 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
4951 (Universe::narrow_oop_base() == 0 ||
4952 Universe::narrow_oop_base_disjoint() ||
4953 !ExpandLoadingBaseEncode_NN));
4954 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4955 // TODO: s390 port size(VARIABLE_SIZE);
4956 format %{ "encodeP $dst,$src\t# (encode cOop)" %}
4957 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4958 ins_pipe(pipe_class_dummy);
4959 %}
4960
4961 // Encoder for heapbased mode peeling off loading the base.
4962 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
4963 match(Set dst (EncodeP src (Binary base dst)));
4964 effect(TEMP_DEF dst);
4965 predicate(false);
4966 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4967 // TODO: s390 port size(VARIABLE_SIZE);
4968 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t# (encode cOop)" %}
4969 ins_encode %{
4970 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
4971 (((uint64_t)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift());
4972 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
4973 %}
4974 ins_pipe(pipe_class_dummy);
4975 %}
4976
4977 // Encoder for heapbased mode peeling off loading the base.
4978 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
4979 match(Set dst (EncodeP src base));
4980 effect(USE pow2_offset);
4981 predicate(false);
4982 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4983 // TODO: s390 port size(VARIABLE_SIZE);
4984 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t# (encode cOop)" %}
4985 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
4986 ins_pipe(pipe_class_dummy);
4987 %}
4988
4989 // Encoder for heapbased mode peeling off loading the base.
4990 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
4991 match(Set dst (EncodeP src));
4992 effect(KILL cr);
4993 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
4994 (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode));
4995 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4996 // TODO: s390 port size(VARIABLE_SIZE);
4997 expand %{
4998 immL baseImm %{ ((jlong)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift() %}
4999 immL_0 zero %{ (0) %}
5000 flagsReg ccr;
5001 iRegL base;
5002 iRegL negBase;
5003 loadBase(base, baseImm);
5004 negL_reg_reg(negBase, zero, base, ccr);
5005 encodeP_base(dst, src, negBase);
5006 %}
5007 %}
5008
5009 // Encoder for heapbased mode peeling off loading the base.
5010 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5011 match(Set dst (EncodeP src));
5012 effect(KILL cr);
5013 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5014 (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode_NN));
5015 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5016 // TODO: s390 port size(VARIABLE_SIZE);
5017 expand %{
5018 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %}
5019 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)Universe::narrow_oop_base())) %}
5020 immL_0 zero %{ 0 %}
5021 flagsReg ccr;
5022 iRegL base;
5023 iRegL negBase;
5024 loadBase(base, baseImm);
5025 negL_reg_reg(negBase, zero, base, ccr);
5026 encodeP_NN_base(dst, src, negBase, pow2_offset);
5027 %}
5028 %}
5029
5030 // Store Compressed Pointer
5031
5032 // Store Compressed Pointer
5033 instruct storeN(memory mem, iRegN_P2N src) %{
5034 match(Set mem (StoreN mem src));
5035 ins_cost(MEMORY_REF_COST);
5036 size(Z_DISP_SIZE);
5037 format %{ "ST $src,$mem\t# (cOop)" %}
5038 opcode(STY_ZOPC, ST_ZOPC);
5039 ins_encode(z_form_rt_mem_opt(src, mem));
5040 ins_pipe(pipe_class_dummy);
5041 %}
5042
5043 // Store Compressed Klass pointer
5044 instruct storeNKlass(memory mem, iRegN src) %{
5045 match(Set mem (StoreNKlass mem src));
5046 ins_cost(MEMORY_REF_COST);
5047 size(Z_DISP_SIZE);
5048 format %{ "ST $src,$mem\t# (cKlass)" %}
5049 opcode(STY_ZOPC, ST_ZOPC);
5050 ins_encode(z_form_rt_mem_opt(src, mem));
5051 ins_pipe(pipe_class_dummy);
5052 %}
5053
5054 // Compare Compressed Pointers
5055
5056 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5057 match(Set cr (CmpN src1 src2));
5058 ins_cost(DEFAULT_COST);
5059 size(2);
5060 format %{ "CLR $src1,$src2\t# (cOop)" %}
5061 opcode(CLR_ZOPC);
5062 ins_encode(z_rrform(src1, src2));
5063 ins_pipe(pipe_class_dummy);
5064 %}
5065
5066 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5067 match(Set cr (CmpN src1 src2));
5068 ins_cost(DEFAULT_COST);
5069 size(6);
5070 format %{ "CLFI $src1,$src2\t# (cOop) compare immediate narrow" %}
5071 ins_encode %{
5072 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5073 __ relocate(cOop.rspec(), 1);
5074 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5075 %}
5076 ins_pipe(pipe_class_dummy);
5077 %}
5078
5079 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5080 match(Set cr (CmpN src1 src2));
5081 ins_cost(DEFAULT_COST);
5082 size(6);
5083 format %{ "CLFI $src1,$src2\t# (NKlass) compare immediate narrow" %}
5084 ins_encode %{
5085 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5086 __ relocate(NKlass.rspec(), 1);
5087 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5088 %}
5089 ins_pipe(pipe_class_dummy);
5090 %}
5091
5092 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5093 match(Set cr (CmpN src1 src2));
5094 ins_cost(DEFAULT_COST);
5095 size(2);
5096 format %{ "LTR $src1,$src2\t# (cOop) LTR because comparing against zero" %}
5097 opcode(LTR_ZOPC);
5098 ins_encode(z_rrform(src1, src1));
5099 ins_pipe(pipe_class_dummy);
5100 %}
5101
5102
5103 //----------MemBar Instructions-----------------------------------------------
5104
5105 // Memory barrier flavors
5106
5107 instruct membar_acquire() %{
5108 match(MemBarAcquire);
5109 match(LoadFence);
5110 ins_cost(4*MEMORY_REF_COST);
5111 size(0);
5112 format %{ "MEMBAR-acquire" %}
5113 ins_encode %{ __ z_acquire(); %}
5114 ins_pipe(pipe_class_dummy);
5115 %}
5116
5117 instruct membar_acquire_lock() %{
5118 match(MemBarAcquireLock);
5119 ins_cost(0);
5120 size(0);
5121 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5122 ins_encode(/*empty*/);
5123 ins_pipe(pipe_class_dummy);
5124 %}
5125
5126 instruct membar_release() %{
5127 match(MemBarRelease);
5128 match(StoreFence);
5129 ins_cost(4 * MEMORY_REF_COST);
5130 size(0);
5131 format %{ "MEMBAR-release" %}
5132 ins_encode %{ __ z_release(); %}
5133 ins_pipe(pipe_class_dummy);
5134 %}
5135
5136 instruct membar_release_lock() %{
5137 match(MemBarReleaseLock);
5138 ins_cost(0);
5139 size(0);
5140 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5141 ins_encode(/*empty*/);
5142 ins_pipe(pipe_class_dummy);
5143 %}
5144
5145 instruct membar_volatile() %{
5146 match(MemBarVolatile);
5147 ins_cost(4 * MEMORY_REF_COST);
5148 size(2);
5149 format %{ "MEMBAR-volatile" %}
5150 ins_encode %{ __ z_fence(); %}
5151 ins_pipe(pipe_class_dummy);
5152 %}
5153
5154 instruct unnecessary_membar_volatile() %{
5155 match(MemBarVolatile);
5156 predicate(Matcher::post_store_load_barrier(n));
5157 ins_cost(0);
5158 size(0);
5159 format %{ "# MEMBAR-volatile (empty)" %}
5160 ins_encode(/*empty*/);
5161 ins_pipe(pipe_class_dummy);
5162 %}
5163
5164 instruct membar_CPUOrder() %{
5165 match(MemBarCPUOrder);
5166 ins_cost(0);
5167 // TODO: s390 port size(FIXED_SIZE);
5168 format %{ "MEMBAR-CPUOrder (empty)" %}
5169 ins_encode(/*empty*/);
5170 ins_pipe(pipe_class_dummy);
5171 %}
5172
5173 instruct membar_storestore() %{
5174 match(MemBarStoreStore);
5175 ins_cost(0);
5176 size(0);
5177 format %{ "MEMBAR-storestore (empty)" %}
5178 ins_encode();
5179 ins_pipe(pipe_class_dummy);
5180 %}
5181
5182
5183 //----------Register Move Instructions-----------------------------------------
5184 instruct roundDouble_nop(regD dst) %{
5185 match(Set dst (RoundDouble dst));
5186 ins_cost(0);
5187 // TODO: s390 port size(FIXED_SIZE);
5188 // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5189 ins_encode();
5190 ins_pipe(pipe_class_dummy);
5191 %}
5192
5193 instruct roundFloat_nop(regF dst) %{
5194 match(Set dst (RoundFloat dst));
5195 ins_cost(0);
5196 // TODO: s390 port size(FIXED_SIZE);
5197 // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5198 ins_encode();
5199 ins_pipe(pipe_class_dummy);
5200 %}
5201
5202 // Cast Long to Pointer for unsafe natives.
5203 instruct castX2P(iRegP dst, iRegL src) %{
5204 match(Set dst (CastX2P src));
5205 // TODO: s390 port size(VARIABLE_SIZE);
5206 format %{ "LGR $dst,$src\t # CastX2P" %}
5207 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5208 ins_pipe(pipe_class_dummy);
5209 %}
5210
5211 // Cast Pointer to Long for unsafe natives.
5212 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5213 match(Set dst (CastP2X src));
5214 // TODO: s390 port size(VARIABLE_SIZE);
5215 format %{ "LGR $dst,$src\t # CastP2X" %}
5216 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5217 ins_pipe(pipe_class_dummy);
5218 %}
5219
5220 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5221 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5222 match(Set stkSlot src); // chain rule
5223 ins_cost(MEMORY_REF_COST);
5224 // TODO: s390 port size(FIXED_SIZE);
5225 format %{ " STD $src,$stkSlot\t # stk" %}
5226 opcode(STD_ZOPC);
5227 ins_encode(z_form_rt_mem(src, stkSlot));
5228 ins_pipe(pipe_class_dummy);
5229 %}
5230
5231 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5232 // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5233 match(Set stkSlot src); // chain rule
5234 ins_cost(MEMORY_REF_COST);
5235 // TODO: s390 port size(FIXED_SIZE);
5236 format %{ "STE $src,$stkSlot\t # stk" %}
5237 opcode(STE_ZOPC);
5238 ins_encode(z_form_rt_mem(src, stkSlot));
5239 ins_pipe(pipe_class_dummy);
5240 %}
5241
5242 //----------Conditional Move---------------------------------------------------
5243
5244 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5245 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5246 ins_cost(DEFAULT_COST + BRANCH_COST);
5247 // TODO: s390 port size(VARIABLE_SIZE);
5248 format %{ "CMoveN,$cmp $dst,$src" %}
5249 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5250 ins_pipe(pipe_class_dummy);
5251 %}
5252
5253 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5254 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5255 ins_cost(DEFAULT_COST + BRANCH_COST);
5256 // TODO: s390 port size(VARIABLE_SIZE);
5257 format %{ "CMoveN,$cmp $dst,$src" %}
5258 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5259 ins_pipe(pipe_class_dummy);
5260 %}
5261
5262 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5263 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5264 ins_cost(DEFAULT_COST + BRANCH_COST);
5265 // TODO: s390 port size(VARIABLE_SIZE);
5266 format %{ "CMoveI,$cmp $dst,$src" %}
5267 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5268 ins_pipe(pipe_class_dummy);
5269 %}
5270
5271 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5272 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5273 ins_cost(DEFAULT_COST + BRANCH_COST);
5274 // TODO: s390 port size(VARIABLE_SIZE);
5275 format %{ "CMoveI,$cmp $dst,$src" %}
5276 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5277 ins_pipe(pipe_class_dummy);
5278 %}
5279
5280 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5281 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5282 ins_cost(DEFAULT_COST + BRANCH_COST);
5283 // TODO: s390 port size(VARIABLE_SIZE);
5284 format %{ "CMoveP,$cmp $dst,$src" %}
5285 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5286 ins_pipe(pipe_class_dummy);
5287 %}
5288
5289 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5290 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5291 ins_cost(DEFAULT_COST + BRANCH_COST);
5292 // TODO: s390 port size(VARIABLE_SIZE);
5293 format %{ "CMoveP,$cmp $dst,$src" %}
5294 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5295 ins_pipe(pipe_class_dummy);
5296 %}
5297
5298 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5299 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5300 ins_cost(DEFAULT_COST + BRANCH_COST);
5301 // TODO: s390 port size(VARIABLE_SIZE);
5302 format %{ "CMoveF,$cmp $dst,$src" %}
5303 ins_encode %{
5304 // Don't emit code if operands are identical (same register).
5305 if ($dst$$FloatRegister != $src$$FloatRegister) {
5306 Label done;
5307 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5308 __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5309 __ bind(done);
5310 }
5311 %}
5312 ins_pipe(pipe_class_dummy);
5313 %}
5314
5315 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5316 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5317 ins_cost(DEFAULT_COST + BRANCH_COST);
5318 // TODO: s390 port size(VARIABLE_SIZE);
5319 format %{ "CMoveD,$cmp $dst,$src" %}
5320 ins_encode %{
5321 // Don't emit code if operands are identical (same register).
5322 if ($dst$$FloatRegister != $src$$FloatRegister) {
5323 Label done;
5324 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5325 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5326 __ bind(done);
5327 }
5328 %}
5329 ins_pipe(pipe_class_dummy);
5330 %}
5331
5332 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5333 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5334 ins_cost(DEFAULT_COST + BRANCH_COST);
5335 // TODO: s390 port size(VARIABLE_SIZE);
5336 format %{ "CMoveL,$cmp $dst,$src" %}
5337 ins_encode(z_enc_cmov_reg(cmp,dst,src));
5338 ins_pipe(pipe_class_dummy);
5339 %}
5340
5341 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5342 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5343 ins_cost(DEFAULT_COST + BRANCH_COST);
5344 // TODO: s390 port size(VARIABLE_SIZE);
5345 format %{ "CMoveL,$cmp $dst,$src" %}
5346 ins_encode(z_enc_cmov_imm(cmp,dst,src));
5347 ins_pipe(pipe_class_dummy);
5348 %}
5349
5350 //----------OS and Locking Instructions----------------------------------------
5351
5352 // This name is KNOWN by the ADLC and cannot be changed.
5353 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5354 // for this guy.
5355 instruct tlsLoadP(threadRegP dst) %{
5356 match(Set dst (ThreadLocal));
5357 ins_cost(0);
5358 size(0);
5359 ins_should_rematerialize(true);
5360 format %{ "# $dst=ThreadLocal" %}
5361 ins_encode(/* empty */);
5362 ins_pipe(pipe_class_dummy);
5363 %}
5364
5365 instruct checkCastPP(iRegP dst) %{
5366 match(Set dst (CheckCastPP dst));
5367 size(0);
5368 format %{ "# checkcastPP of $dst" %}
5369 ins_encode(/*empty*/);
5370 ins_pipe(pipe_class_dummy);
5371 %}
5372
5373 instruct castPP(iRegP dst) %{
5374 match(Set dst (CastPP dst));
5375 size(0);
5376 format %{ "# castPP of $dst" %}
5377 ins_encode(/*empty*/);
5378 ins_pipe(pipe_class_dummy);
5379 %}
5380
5381 instruct castII(iRegI dst) %{
5382 match(Set dst (CastII dst));
5383 size(0);
5384 format %{ "# castII of $dst" %}
5385 ins_encode(/*empty*/);
5386 ins_pipe(pipe_class_dummy);
5387 %}
5388
5389
5390 //----------Conditional_store--------------------------------------------------
5391 // Conditional-store of the updated heap-top.
5392 // Used during allocation of the shared heap.
5393 // Sets flags (EQ) on success.
5394
5395 // Implement LoadPLocked. Must be ordered against changes of the memory location
5396 // by storePConditional.
5397 // Don't know whether this is ever used.
5398 instruct loadPLocked(iRegP dst, memory mem) %{
5399 match(Set dst (LoadPLocked mem));
5400 ins_cost(MEMORY_REF_COST);
5401 size(Z_DISP3_SIZE);
5402 format %{ "LG $dst,$mem\t # LoadPLocked" %}
5403 opcode(LG_ZOPC, LG_ZOPC);
5404 ins_encode(z_form_rt_mem_opt(dst, mem));
5405 ins_pipe(pipe_class_dummy);
5406 %}
5407
5408 // As compareAndSwapP, but return flag register instead of boolean value in
5409 // int register.
5410 // This instruction is matched if UseTLAB is off. Needed to pass
5411 // option tests. Mem_ptr must be a memory operand, else this node
5412 // does not get Flag_needs_anti_dependence_check set by adlc. If this
5413 // is not set this node can be rematerialized which leads to errors.
5414 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
5415 match(Set cr (StorePConditional mem_ptr (Binary oldval newval)));
5416 effect(KILL oldval);
5417 // TODO: s390 port size(FIXED_SIZE);
5418 format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5419 ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5420 ins_pipe(pipe_class_dummy);
5421 %}
5422
5423 // As compareAndSwapL, but return flag register instead of boolean value in
5424 // int register.
5425 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory
5426 // operand, else this node does not get
5427 // Flag_needs_anti_dependence_check set by adlc. If this is not set
5428 // this node can be rematerialized which leads to errors.
5429 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{
5430 match(Set cr (StoreLConditional mem_ptr (Binary oldval newval)));
5431 effect(KILL oldval);
5432 // TODO: s390 port size(FIXED_SIZE);
5433 format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5434 ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5435 ins_pipe(pipe_class_dummy);
5436 %}
5437
5438 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5439
5440 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5441 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5442 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5443 size(16);
5444 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5445 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5446 z_enc_cctobool(res));
5447 ins_pipe(pipe_class_dummy);
5448 %}
5449
5450 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5451 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5452 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5453 size(18);
5454 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5455 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5456 z_enc_cctobool(res));
5457 ins_pipe(pipe_class_dummy);
5458 %}
5459
5460 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5461 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5462 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5463 size(18);
5464 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5465 ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5466 z_enc_cctobool(res));
5467 ins_pipe(pipe_class_dummy);
5468 %}
5469
5470 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5471 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5472 effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5473 size(16);
5474 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5475 ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5476 z_enc_cctobool(res));
5477 ins_pipe(pipe_class_dummy);
5478 %}
5479
5480 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5481
5482 // Exploit: direct memory arithmetic
5483 // Prereqs: - instructions available
5484 // - instructions guarantee atomicity
5485 // - immediate operand to be added
5486 // - immediate operand is small enough (8-bit signed).
5487 // - result of instruction is not used
5488 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5489 match(Set dummy (GetAndAddI mem src));
5490 effect(KILL cr);
5491 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5492 ins_cost(MEMORY_REF_COST);
5493 size(6);
5494 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %}
5495 opcode(ASI_ZOPC);
5496 ins_encode(z_siyform(mem, src));
5497 ins_pipe(pipe_class_dummy);
5498 %}
5499
5500 // Fallback: direct memory arithmetic not available
5501 // Disadvantages: - CS-Loop required, very expensive.
5502 // - more code generated (26 to xx bytes vs. 6 bytes)
5503 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5504 match(Set dst (GetAndAddI mem src));
5505 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5506 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5507 format %{ "BEGIN ATOMIC {\n\t"
5508 " LGF $dst,[$mem]\n\t"
5509 " AHIK $tmp,$dst,$src\n\t"
5510 " CSY $dst,$tmp,$mem\n\t"
5511 " retry if failed\n\t"
5512 "} END ATOMIC"
5513 %}
5514 ins_encode %{
5515 Register Rdst = $dst$$Register;
5516 Register Rtmp = $tmp$$Register;
5517 int Isrc = $src$$constant;
5518 Label retry;
5519
5520 // Iterate until update with incremented value succeeds.
5521 __ z_lgf(Rdst, $mem$$Address); // current contents
5522 __ bind(retry);
5523 // Calculate incremented value.
5524 if (VM_Version::has_DistinctOpnds()) {
5525 __ z_ahik(Rtmp, Rdst, Isrc);
5526 } else {
5527 __ z_lr(Rtmp, Rdst);
5528 __ z_ahi(Rtmp, Isrc);
5529 }
5530 // Swap into memory location.
5531 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5532 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5533 %}
5534 ins_pipe(pipe_class_dummy);
5535 %}
5536
5537 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5538 match(Set dst (GetAndAddI mem src));
5539 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5540 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5541 format %{ "BEGIN ATOMIC {\n\t"
5542 " LGF $dst,[$mem]\n\t"
5543 " LGR $tmp,$dst\n\t"
5544 " AFI $tmp,$src\n\t"
5545 " CSY $dst,$tmp,$mem\n\t"
5546 " retry if failed\n\t"
5547 "} END ATOMIC"
5548 %}
5549 ins_encode %{
5550 Register Rdst = $dst$$Register;
5551 Register Rtmp = $tmp$$Register;
5552 int Isrc = $src$$constant;
5553 Label retry;
5554
5555 // Iterate until update with incremented value succeeds.
5556 __ z_lgf(Rdst, $mem$$Address); // current contents
5557 __ bind(retry);
5558 // Calculate incremented value.
5559 __ z_lr(Rtmp, Rdst);
5560 __ z_afi(Rtmp, Isrc);
5561 // Swap into memory location.
5562 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5563 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5564 %}
5565 ins_pipe(pipe_class_dummy);
5566 %}
5567
5568 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5569 match(Set dst (GetAndAddI mem src));
5570 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5571 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5572 format %{ "BEGIN ATOMIC {\n\t"
5573 " LGF $dst,[$mem]\n\t"
5574 " ARK $tmp,$dst,$src\n\t"
5575 " CSY $dst,$tmp,$mem\n\t"
5576 " retry if failed\n\t"
5577 "} END ATOMIC"
5578 %}
5579 ins_encode %{
5580 Register Rsrc = $src$$Register;
5581 Register Rdst = $dst$$Register;
5582 Register Rtmp = $tmp$$Register;
5583 Label retry;
5584
5585 // Iterate until update with incremented value succeeds.
5586 __ z_lgf(Rdst, $mem$$Address); // current contents
5587 __ bind(retry);
5588 // Calculate incremented value.
5589 if (VM_Version::has_DistinctOpnds()) {
5590 __ z_ark(Rtmp, Rdst, Rsrc);
5591 } else {
5592 __ z_lr(Rtmp, Rdst);
5593 __ z_ar(Rtmp, Rsrc);
5594 }
5595 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5596 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5597 %}
5598 ins_pipe(pipe_class_dummy);
5599 %}
5600
5601
5602 // Exploit: direct memory arithmetic
5603 // Prereqs: - instructions available
5604 // - instructions guarantee atomicity
5605 // - immediate operand to be added
5606 // - immediate operand is small enough (8-bit signed).
5607 // - result of instruction is not used
5608 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5609 match(Set dummy (GetAndAddL mem src));
5610 effect(KILL cr);
5611 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5612 ins_cost(MEMORY_REF_COST);
5613 size(6);
5614 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %}
5615 opcode(AGSI_ZOPC);
5616 ins_encode(z_siyform(mem, src));
5617 ins_pipe(pipe_class_dummy);
5618 %}
5619
5620 // Fallback: direct memory arithmetic not available
5621 // Disadvantages: - CS-Loop required, very expensive.
5622 // - more code generated (26 to xx bytes vs. 6 bytes)
5623 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5624 match(Set dst (GetAndAddL mem src));
5625 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5626 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5627 format %{ "BEGIN ATOMIC {\n\t"
5628 " LG $dst,[$mem]\n\t"
5629 " AGHIK $tmp,$dst,$src\n\t"
5630 " CSG $dst,$tmp,$mem\n\t"
5631 " retry if failed\n\t"
5632 "} END ATOMIC"
5633 %}
5634 ins_encode %{
5635 Register Rdst = $dst$$Register;
5636 Register Rtmp = $tmp$$Register;
5637 int Isrc = $src$$constant;
5638 Label retry;
5639
5640 // Iterate until update with incremented value succeeds.
5641 __ z_lg(Rdst, $mem$$Address); // current contents
5642 __ bind(retry);
5643 // Calculate incremented value.
5644 if (VM_Version::has_DistinctOpnds()) {
5645 __ z_aghik(Rtmp, Rdst, Isrc);
5646 } else {
5647 __ z_lgr(Rtmp, Rdst);
5648 __ z_aghi(Rtmp, Isrc);
5649 }
5650 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5651 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5652 %}
5653 ins_pipe(pipe_class_dummy);
5654 %}
5655
5656 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5657 match(Set dst (GetAndAddL mem src));
5658 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5659 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5660 format %{ "BEGIN ATOMIC {\n\t"
5661 " LG $dst,[$mem]\n\t"
5662 " LGR $tmp,$dst\n\t"
5663 " AGFI $tmp,$src\n\t"
5664 " CSG $dst,$tmp,$mem\n\t"
5665 " retry if failed\n\t"
5666 "} END ATOMIC"
5667 %}
5668 ins_encode %{
5669 Register Rdst = $dst$$Register;
5670 Register Rtmp = $tmp$$Register;
5671 int Isrc = $src$$constant;
5672 Label retry;
5673
5674 // Iterate until update with incremented value succeeds.
5675 __ z_lg(Rdst, $mem$$Address); // current contents
5676 __ bind(retry);
5677 // Calculate incremented value.
5678 __ z_lgr(Rtmp, Rdst);
5679 __ z_agfi(Rtmp, Isrc);
5680 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5681 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5682 %}
5683 ins_pipe(pipe_class_dummy);
5684 %}
5685
5686 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5687 match(Set dst (GetAndAddL mem src));
5688 effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5689 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5690 format %{ "BEGIN ATOMIC {\n\t"
5691 " LG $dst,[$mem]\n\t"
5692 " AGRK $tmp,$dst,$src\n\t"
5693 " CSG $dst,$tmp,$mem\n\t"
5694 " retry if failed\n\t"
5695 "} END ATOMIC"
5696 %}
5697 ins_encode %{
5698 Register Rsrc = $src$$Register;
5699 Register Rdst = $dst$$Register;
5700 Register Rtmp = $tmp$$Register;
5701 Label retry;
5702
5703 // Iterate until update with incremented value succeeds.
5704 __ z_lg(Rdst, $mem$$Address); // current contents
5705 __ bind(retry);
5706 // Calculate incremented value.
5707 if (VM_Version::has_DistinctOpnds()) {
5708 __ z_agrk(Rtmp, Rdst, Rsrc);
5709 } else {
5710 __ z_lgr(Rtmp, Rdst);
5711 __ z_agr(Rtmp, Rsrc);
5712 }
5713 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5714 __ z_brne(retry); // Yikes, concurrent update, need to retry.
5715 %}
5716 ins_pipe(pipe_class_dummy);
5717 %}
5718
5719 // Increment value in memory, save old value in dst.
5720 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5721 match(Set dst (GetAndAddI mem src));
5722 predicate(VM_Version::has_LoadAndALUAtomicV1());
5723 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5724 size(6);
5725 format %{ "LAA $dst,$src,[$mem]" %}
5726 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5727 ins_pipe(pipe_class_dummy);
5728 %}
5729
5730 // Increment value in memory, save old value in dst.
5731 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5732 match(Set dst (GetAndAddL mem src));
5733 predicate(VM_Version::has_LoadAndALUAtomicV1());
5734 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5735 size(6);
5736 format %{ "LAAG $dst,$src,[$mem]" %}
5737 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5738 ins_pipe(pipe_class_dummy);
5739 %}
5740
5741
5742 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5743 match(Set dst (GetAndSetI mem dst));
5744 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5745 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5746 ins_encode(z_enc_SwapI(mem, dst, tmp));
5747 ins_pipe(pipe_class_dummy);
5748 %}
5749
5750 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5751 match(Set dst (GetAndSetL mem dst));
5752 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5753 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5754 ins_encode(z_enc_SwapL(mem, dst, tmp));
5755 ins_pipe(pipe_class_dummy);
5756 %}
5757
5758 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5759 match(Set dst (GetAndSetN mem dst));
5760 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5761 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5762 ins_encode(z_enc_SwapI(mem, dst, tmp));
5763 ins_pipe(pipe_class_dummy);
5764 %}
5765
5766 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5767 match(Set dst (GetAndSetP mem dst));
5768 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5769 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5770 ins_encode(z_enc_SwapL(mem, dst, tmp));
5771 ins_pipe(pipe_class_dummy);
5772 %}
5773
5774
5775 //----------Arithmetic Instructions--------------------------------------------
5776
5777 // The rules are sorted by right operand type and operand length. Please keep
5778 // it that way.
5779 // Left operand type is always reg. Left operand len is I, L, P
5780 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5781 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5782
5783 // ADD
5784
5785 // REG = REG + REG
5786
5787 // Register Addition
5788 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5789 match(Set dst (AddI dst src));
5790 effect(KILL cr);
5791 // TODO: s390 port size(FIXED_SIZE);
5792 format %{ "AR $dst,$src\t # int CISC ALU" %}
5793 opcode(AR_ZOPC);
5794 ins_encode(z_rrform(dst, src));
5795 ins_pipe(pipe_class_dummy);
5796 %}
5797
5798 // Avoid use of LA(Y) for general ALU operation.
5799 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5800 match(Set dst (AddI src1 src2));
5801 effect(KILL cr);
5802 predicate(VM_Version::has_DistinctOpnds());
5803 ins_cost(DEFAULT_COST);
5804 size(4);
5805 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %}
5806 opcode(ARK_ZOPC);
5807 ins_encode(z_rrfform(dst, src1, src2));
5808 ins_pipe(pipe_class_dummy);
5809 %}
5810
5811 // REG = REG + IMM
5812
5813 // Avoid use of LA(Y) for general ALU operation.
5814 // Immediate Addition
5815 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5816 match(Set dst (AddI dst con));
5817 effect(KILL cr);
5818 ins_cost(DEFAULT_COST);
5819 // TODO: s390 port size(FIXED_SIZE);
5820 format %{ "AHI $dst,$con\t # int CISC ALU" %}
5821 opcode(AHI_ZOPC);
5822 ins_encode(z_riform_signed(dst, con));
5823 ins_pipe(pipe_class_dummy);
5824 %}
5825
5826 // Avoid use of LA(Y) for general ALU operation.
5827 // Immediate Addition
5828 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5829 match(Set dst (AddI src con));
5830 effect(KILL cr);
5831 predicate( VM_Version::has_DistinctOpnds());
5832 ins_cost(DEFAULT_COST);
5833 // TODO: s390 port size(FIXED_SIZE);
5834 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %}
5835 opcode(AHIK_ZOPC);
5836 ins_encode(z_rieform_d(dst, src, con));
5837 ins_pipe(pipe_class_dummy);
5838 %}
5839
5840 // Immediate Addition
5841 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5842 match(Set dst (AddI dst src));
5843 effect(KILL cr);
5844 ins_cost(DEFAULT_COST_HIGH);
5845 size(6);
5846 format %{ "AFI $dst,$src" %}
5847 opcode(AFI_ZOPC);
5848 ins_encode(z_rilform_signed(dst, src));
5849 ins_pipe(pipe_class_dummy);
5850 %}
5851
5852 // Immediate Addition
5853 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
5854 match(Set dst (AddI src con));
5855 predicate(PreferLAoverADD);
5856 ins_cost(DEFAULT_COST_LOW);
5857 size(4);
5858 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %}
5859 opcode(LA_ZOPC);
5860 ins_encode(z_rxform_imm_reg(dst, con, src));
5861 ins_pipe(pipe_class_dummy);
5862 %}
5863
5864 // Immediate Addition
5865 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
5866 match(Set dst (AddI src con));
5867 predicate(PreferLAoverADD);
5868 ins_cost(DEFAULT_COST);
5869 size(6);
5870 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %}
5871 opcode(LAY_ZOPC);
5872 ins_encode(z_rxyform_imm_reg(dst, con, src));
5873 ins_pipe(pipe_class_dummy);
5874 %}
5875
5876 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
5877 match(Set dst (AddI (AddI src1 src2) con));
5878 predicate( PreferLAoverADD);
5879 ins_cost(DEFAULT_COST_LOW);
5880 size(4);
5881 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %}
5882 opcode(LA_ZOPC);
5883 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
5884 ins_pipe(pipe_class_dummy);
5885 %}
5886
5887 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
5888 match(Set dst (AddI (AddI src1 src2) con));
5889 predicate(PreferLAoverADD);
5890 ins_cost(DEFAULT_COST);
5891 size(6);
5892 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %}
5893 opcode(LAY_ZOPC);
5894 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
5895 ins_pipe(pipe_class_dummy);
5896 %}
5897
5898 // REG = REG + MEM
5899
5900 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
5901 match(Set dst (AddI dst (LoadI src)));
5902 effect(KILL cr);
5903 ins_cost(MEMORY_REF_COST);
5904 // TODO: s390 port size(VARIABLE_SIZE);
5905 format %{ "A(Y) $dst, $src\t # int" %}
5906 opcode(AY_ZOPC, A_ZOPC);
5907 ins_encode(z_form_rt_mem_opt(dst, src));
5908 ins_pipe(pipe_class_dummy);
5909 %}
5910
5911 // MEM = MEM + IMM
5912
5913 // Add Immediate to 4-byte memory operand and result
5914 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
5915 match(Set mem (StoreI mem (AddI (LoadI mem) src)));
5916 effect(KILL cr);
5917 predicate(VM_Version::has_MemWithImmALUOps());
5918 ins_cost(MEMORY_REF_COST);
5919 size(6);
5920 format %{ "ASI $mem,$src\t # direct mem add 4" %}
5921 opcode(ASI_ZOPC);
5922 ins_encode(z_siyform(mem, src));
5923 ins_pipe(pipe_class_dummy);
5924 %}
5925
5926
5927 //
5928
5929 // REG = REG + REG
5930
5931 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
5932 match(Set dst (AddL dst (ConvI2L src)));
5933 effect(KILL cr);
5934 size(4);
5935 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %}
5936 opcode(AGFR_ZOPC);
5937 ins_encode(z_rreform(dst, src));
5938 ins_pipe(pipe_class_dummy);
5939 %}
5940
5941 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
5942 match(Set dst (AddL dst src));
5943 effect(KILL cr);
5944 // TODO: s390 port size(FIXED_SIZE);
5945 format %{ "AGR $dst, $src\t # long CISC ALU" %}
5946 opcode(AGR_ZOPC);
5947 ins_encode(z_rreform(dst, src));
5948 ins_pipe(pipe_class_dummy);
5949 %}
5950
5951 // Avoid use of LA(Y) for general ALU operation.
5952 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
5953 match(Set dst (AddL src1 src2));
5954 effect(KILL cr);
5955 predicate(VM_Version::has_DistinctOpnds());
5956 ins_cost(DEFAULT_COST);
5957 size(4);
5958 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %}
5959 opcode(AGRK_ZOPC);
5960 ins_encode(z_rrfform(dst, src1, src2));
5961 ins_pipe(pipe_class_dummy);
5962 %}
5963
5964 // REG = REG + IMM
5965
5966 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
5967 match(Set dst (AddL src con));
5968 predicate( PreferLAoverADD);
5969 ins_cost(DEFAULT_COST_LOW);
5970 size(4);
5971 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %}
5972 opcode(LA_ZOPC);
5973 ins_encode(z_rxform_imm_reg(dst, con, src));
5974 ins_pipe(pipe_class_dummy);
5975 %}
5976
5977 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
5978 match(Set dst (AddL src con));
5979 predicate(PreferLAoverADD);
5980 ins_cost(DEFAULT_COST);
5981 size(6);
5982 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %}
5983 opcode(LAY_ZOPC);
5984 ins_encode(z_rxyform_imm_reg(dst, con, src));
5985 ins_pipe(pipe_class_dummy);
5986 %}
5987
5988 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
5989 match(Set dst (AddL dst con));
5990 effect(KILL cr);
5991 ins_cost(DEFAULT_COST_HIGH);
5992 size(6);
5993 format %{ "AGFI $dst,$con\t # long CISC ALU" %}
5994 opcode(AGFI_ZOPC);
5995 ins_encode(z_rilform_signed(dst, con));
5996 ins_pipe(pipe_class_dummy);
5997 %}
5998
5999 // Avoid use of LA(Y) for general ALU operation.
6000 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
6001 match(Set dst (AddL dst con));
6002 effect(KILL cr);
6003 ins_cost(DEFAULT_COST);
6004 // TODO: s390 port size(FIXED_SIZE);
6005 format %{ "AGHI $dst,$con\t # long CISC ALU" %}
6006 opcode(AGHI_ZOPC);
6007 ins_encode(z_riform_signed(dst, con));
6008 ins_pipe(pipe_class_dummy);
6009 %}
6010
6011 // Avoid use of LA(Y) for general ALU operation.
6012 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6013 match(Set dst (AddL src con));
6014 effect(KILL cr);
6015 predicate( VM_Version::has_DistinctOpnds());
6016 ins_cost(DEFAULT_COST);
6017 size(6);
6018 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %}
6019 opcode(AGHIK_ZOPC);
6020 ins_encode(z_rieform_d(dst, src, con));
6021 ins_pipe(pipe_class_dummy);
6022 %}
6023
6024 // REG = REG + MEM
6025
6026 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6027 match(Set dst (AddL dst (ConvI2L (LoadI src))));
6028 effect(KILL cr);
6029 ins_cost(MEMORY_REF_COST);
6030 size(Z_DISP3_SIZE);
6031 format %{ "AGF $dst, $src\t # long/int" %}
6032 opcode(AGF_ZOPC, AGF_ZOPC);
6033 ins_encode(z_form_rt_mem_opt(dst, src));
6034 ins_pipe(pipe_class_dummy);
6035 %}
6036
6037 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6038 match(Set dst (AddL dst (LoadL src)));
6039 effect(KILL cr);
6040 ins_cost(MEMORY_REF_COST);
6041 size(Z_DISP3_SIZE);
6042 format %{ "AG $dst, $src\t # long" %}
6043 opcode(AG_ZOPC, AG_ZOPC);
6044 ins_encode(z_form_rt_mem_opt(dst, src));
6045 ins_pipe(pipe_class_dummy);
6046 %}
6047
6048 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6049 match(Set dst (AddL (AddL src1 src2) con));
6050 predicate( PreferLAoverADD);
6051 ins_cost(DEFAULT_COST_LOW);
6052 size(4);
6053 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6054 opcode(LA_ZOPC);
6055 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6056 ins_pipe(pipe_class_dummy);
6057 %}
6058
6059 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6060 match(Set dst (AddL (AddL src1 src2) con));
6061 predicate(PreferLAoverADD);
6062 ins_cost(DEFAULT_COST);
6063 size(6);
6064 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6065 opcode(LAY_ZOPC);
6066 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6067 ins_pipe(pipe_class_dummy);
6068 %}
6069
6070 // MEM = MEM + IMM
6071
6072 // Add Immediate to 8-byte memory operand and result.
6073 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6074 match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6075 effect(KILL cr);
6076 predicate(VM_Version::has_MemWithImmALUOps());
6077 ins_cost(MEMORY_REF_COST);
6078 size(6);
6079 format %{ "AGSI $mem,$src\t # direct mem add 8" %}
6080 opcode(AGSI_ZOPC);
6081 ins_encode(z_siyform(mem, src));
6082 ins_pipe(pipe_class_dummy);
6083 %}
6084
6085
6086 // REG = REG + REG
6087
6088 // Ptr Addition
6089 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6090 match(Set dst (AddP src1 src2));
6091 predicate( PreferLAoverADD);
6092 ins_cost(DEFAULT_COST);
6093 size(4);
6094 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6095 opcode(LA_ZOPC);
6096 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6097 ins_pipe(pipe_class_dummy);
6098 %}
6099
6100 // Ptr Addition
6101 // Avoid use of LA(Y) for general ALU operation.
6102 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6103 match(Set dst (AddP dst src));
6104 effect(KILL cr);
6105 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6106 ins_cost(DEFAULT_COST);
6107 // TODO: s390 port size(FIXED_SIZE);
6108 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %}
6109 opcode(ALGR_ZOPC);
6110 ins_encode(z_rreform(dst, src));
6111 ins_pipe(pipe_class_dummy);
6112 %}
6113
6114 // Ptr Addition
6115 // Avoid use of LA(Y) for general ALU operation.
6116 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6117 match(Set dst (AddP src1 src2));
6118 effect(KILL cr);
6119 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6120 ins_cost(DEFAULT_COST);
6121 // TODO: s390 port size(FIXED_SIZE);
6122 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %}
6123 opcode(ALGRK_ZOPC);
6124 ins_encode(z_rrfform(dst, src1, src2));
6125 ins_pipe(pipe_class_dummy);
6126 %}
6127
6128 // REG = REG + IMM
6129
6130 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6131 match(Set dst (AddP src con));
6132 predicate( PreferLAoverADD);
6133 ins_cost(DEFAULT_COST_LOW);
6134 size(4);
6135 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %}
6136 opcode(LA_ZOPC);
6137 ins_encode(z_rxform_imm_reg(dst, con, src));
6138 ins_pipe(pipe_class_dummy);
6139 %}
6140
6141 // Avoid use of LA(Y) for general ALU operation.
6142 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6143 match(Set dst (AddP dst src));
6144 effect(KILL cr);
6145 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6146 ins_cost(DEFAULT_COST);
6147 // TODO: s390 port size(FIXED_SIZE);
6148 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %}
6149 opcode(AGHI_ZOPC);
6150 ins_encode(z_riform_signed(dst, src));
6151 ins_pipe(pipe_class_dummy);
6152 %}
6153
6154 // Avoid use of LA(Y) for general ALU operation.
6155 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6156 match(Set dst (AddP src con));
6157 effect(KILL cr);
6158 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6159 ins_cost(DEFAULT_COST);
6160 // TODO: s390 port size(FIXED_SIZE);
6161 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6162 opcode(ALGHSIK_ZOPC);
6163 ins_encode(z_rieform_d(dst, src, con));
6164 ins_pipe(pipe_class_dummy);
6165 %}
6166
6167 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6168 match(Set dst (AddP src con));
6169 predicate(PreferLAoverADD);
6170 ins_cost(DEFAULT_COST);
6171 size(6);
6172 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %}
6173 opcode(LAY_ZOPC);
6174 ins_encode(z_rxyform_imm_reg(dst, con, src));
6175 ins_pipe(pipe_class_dummy);
6176 %}
6177
6178 // Pointer Immediate Addition
6179 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6180 match(Set dst (AddP dst src));
6181 effect(KILL cr);
6182 ins_cost(DEFAULT_COST_HIGH);
6183 // TODO: s390 port size(FIXED_SIZE);
6184 format %{ "AGFI $dst,$src\t # ptr" %}
6185 opcode(AGFI_ZOPC);
6186 ins_encode(z_rilform_signed(dst, src));
6187 ins_pipe(pipe_class_dummy);
6188 %}
6189
6190 // REG = REG1 + REG2 + IMM
6191
6192 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6193 match(Set dst (AddP (AddP src1 src2) con));
6194 predicate( PreferLAoverADD);
6195 ins_cost(DEFAULT_COST_LOW);
6196 size(4);
6197 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6198 opcode(LA_ZOPC);
6199 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6200 ins_pipe(pipe_class_dummy);
6201 %}
6202
6203 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6204 match(Set dst (AddP (AddP src1 src2) con));
6205 predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6206 ins_cost(DEFAULT_COST_LOW);
6207 size(4);
6208 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6209 opcode(LA_ZOPC);
6210 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6211 ins_pipe(pipe_class_dummy);
6212 %}
6213
6214 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6215 match(Set dst (AddP (AddP src1 src2) con));
6216 predicate(PreferLAoverADD);
6217 ins_cost(DEFAULT_COST);
6218 // TODO: s390 port size(FIXED_SIZE);
6219 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6220 opcode(LAY_ZOPC);
6221 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6222 ins_pipe(pipe_class_dummy);
6223 %}
6224
6225 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6226 match(Set dst (AddP (AddP src1 src2) con));
6227 predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6228 ins_cost(DEFAULT_COST);
6229 // TODO: s390 port size(FIXED_SIZE);
6230 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6231 opcode(LAY_ZOPC);
6232 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6233 ins_pipe(pipe_class_dummy);
6234 %}
6235
6236 // MEM = MEM + IMM
6237
6238 // Add Immediate to 8-byte memory operand and result
6239 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6240 match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6241 effect(KILL cr);
6242 predicate(VM_Version::has_MemWithImmALUOps());
6243 ins_cost(MEMORY_REF_COST);
6244 size(6);
6245 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %}
6246 opcode(AGSI_ZOPC);
6247 ins_encode(z_siyform(mem, src));
6248 ins_pipe(pipe_class_dummy);
6249 %}
6250
6251 // SUB
6252
6253 // Register Subtraction
6254 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6255 match(Set dst (SubI dst src));
6256 effect(KILL cr);
6257 // TODO: s390 port size(FIXED_SIZE);
6258 format %{ "SR $dst,$src\t # int CISC ALU" %}
6259 opcode(SR_ZOPC);
6260 ins_encode(z_rrform(dst, src));
6261 ins_pipe(pipe_class_dummy);
6262 %}
6263
6264 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6265 match(Set dst (SubI src1 src2));
6266 effect(KILL cr);
6267 predicate(VM_Version::has_DistinctOpnds());
6268 ins_cost(DEFAULT_COST);
6269 size(4);
6270 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %}
6271 opcode(SRK_ZOPC);
6272 ins_encode(z_rrfform(dst, src1, src2));
6273 ins_pipe(pipe_class_dummy);
6274 %}
6275
6276 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6277 match(Set dst (SubI dst (LoadI src)));
6278 effect(KILL cr);
6279 ins_cost(MEMORY_REF_COST);
6280 // TODO: s390 port size(VARIABLE_SIZE);
6281 format %{ "S(Y) $dst, $src\t # int" %}
6282 opcode(SY_ZOPC, S_ZOPC);
6283 ins_encode(z_form_rt_mem_opt(dst, src));
6284 ins_pipe(pipe_class_dummy);
6285 %}
6286
6287 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6288 match(Set dst (SubI zero src));
6289 effect(KILL cr);
6290 size(2);
6291 format %{ "NEG $dst, $src" %}
6292 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6293 ins_pipe(pipe_class_dummy);
6294 %}
6295
6296 //
6297
6298 // Long subtraction
6299 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6300 match(Set dst (SubL dst src));
6301 effect(KILL cr);
6302 // TODO: s390 port size(FIXED_SIZE);
6303 format %{ "SGR $dst,$src\t # int CISC ALU" %}
6304 opcode(SGR_ZOPC);
6305 ins_encode(z_rreform(dst, src));
6306 ins_pipe(pipe_class_dummy);
6307 %}
6308
6309 // Avoid use of LA(Y) for general ALU operation.
6310 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6311 match(Set dst (SubL src1 src2));
6312 effect(KILL cr);
6313 predicate(VM_Version::has_DistinctOpnds());
6314 ins_cost(DEFAULT_COST);
6315 size(4);
6316 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %}
6317 opcode(SGRK_ZOPC);
6318 ins_encode(z_rrfform(dst, src1, src2));
6319 ins_pipe(pipe_class_dummy);
6320 %}
6321
6322 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6323 match(Set dst (SubL dst (ConvI2L src)));
6324 effect(KILL cr);
6325 size(4);
6326 format %{ "SGFR $dst, $src\t # int CISC ALU" %}
6327 opcode(SGFR_ZOPC);
6328 ins_encode(z_rreform(dst, src));
6329 ins_pipe(pipe_class_dummy);
6330 %}
6331
6332 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6333 match(Set dst (SubL dst (ConvI2L (LoadI src))));
6334 effect(KILL cr);
6335 ins_cost(MEMORY_REF_COST);
6336 size(Z_DISP3_SIZE);
6337 format %{ "SGF $dst, $src\t # long/int" %}
6338 opcode(SGF_ZOPC, SGF_ZOPC);
6339 ins_encode(z_form_rt_mem_opt(dst, src));
6340 ins_pipe(pipe_class_dummy);
6341 %}
6342
6343 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6344 match(Set dst (SubL dst (LoadL src)));
6345 effect(KILL cr);
6346 ins_cost(MEMORY_REF_COST);
6347 size(Z_DISP3_SIZE);
6348 format %{ "SG $dst, $src\t # long" %}
6349 opcode(SG_ZOPC, SG_ZOPC);
6350 ins_encode(z_form_rt_mem_opt(dst, src));
6351 ins_pipe(pipe_class_dummy);
6352 %}
6353
6354 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6355
6356 // MUL
6357
6358 // Register Multiplication
6359 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6360 match(Set dst (MulI dst src));
6361 ins_cost(DEFAULT_COST);
6362 size(4);
6363 format %{ "MSR $dst, $src" %}
6364 opcode(MSR_ZOPC);
6365 ins_encode(z_rreform(dst, src));
6366 ins_pipe(pipe_class_dummy);
6367 %}
6368
6369 // Immediate Multiplication
6370 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6371 match(Set dst (MulI dst con));
6372 ins_cost(DEFAULT_COST);
6373 // TODO: s390 port size(FIXED_SIZE);
6374 format %{ "MHI $dst,$con" %}
6375 opcode(MHI_ZOPC);
6376 ins_encode(z_riform_signed(dst,con));
6377 ins_pipe(pipe_class_dummy);
6378 %}
6379
6380 // Immediate (32bit) Multiplication
6381 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6382 match(Set dst (MulI dst con));
6383 ins_cost(DEFAULT_COST);
6384 size(6);
6385 format %{ "MSFI $dst,$con" %}
6386 opcode(MSFI_ZOPC);
6387 ins_encode(z_rilform_signed(dst,con));
6388 ins_pipe(pipe_class_dummy);
6389 %}
6390
6391 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6392 match(Set dst (MulI dst (LoadI src)));
6393 ins_cost(MEMORY_REF_COST);
6394 // TODO: s390 port size(VARIABLE_SIZE);
6395 format %{ "MS(Y) $dst, $src\t # int" %}
6396 opcode(MSY_ZOPC, MS_ZOPC);
6397 ins_encode(z_form_rt_mem_opt(dst, src));
6398 ins_pipe(pipe_class_dummy);
6399 %}
6400
6401 //
6402
6403 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6404 match(Set dst (MulL dst (ConvI2L src)));
6405 ins_cost(DEFAULT_COST);
6406 // TODO: s390 port size(FIXED_SIZE);
6407 format %{ "MSGFR $dst $src\t # long/int" %}
6408 opcode(MSGFR_ZOPC);
6409 ins_encode(z_rreform(dst, src));
6410 ins_pipe(pipe_class_dummy);
6411 %}
6412
6413 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6414 match(Set dst (MulL dst src));
6415 ins_cost(DEFAULT_COST);
6416 size(4);
6417 format %{ "MSGR $dst $src\t # long" %}
6418 opcode(MSGR_ZOPC);
6419 ins_encode(z_rreform(dst, src));
6420 ins_pipe(pipe_class_dummy);
6421 %}
6422
6423 // Immediate Multiplication
6424 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6425 match(Set dst (MulL dst src));
6426 ins_cost(DEFAULT_COST);
6427 // TODO: s390 port size(FIXED_SIZE);
6428 format %{ "MGHI $dst,$src\t # long" %}
6429 opcode(MGHI_ZOPC);
6430 ins_encode(z_riform_signed(dst, src));
6431 ins_pipe(pipe_class_dummy);
6432 %}
6433
6434 // Immediate (32bit) Multiplication
6435 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6436 match(Set dst (MulL dst con));
6437 ins_cost(DEFAULT_COST);
6438 size(6);
6439 format %{ "MSGFI $dst,$con" %}
6440 opcode(MSGFI_ZOPC);
6441 ins_encode(z_rilform_signed(dst,con));
6442 ins_pipe(pipe_class_dummy);
6443 %}
6444
6445 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6446 match(Set dst (MulL dst (ConvI2L (LoadI src))));
6447 ins_cost(MEMORY_REF_COST);
6448 size(Z_DISP3_SIZE);
6449 format %{ "MSGF $dst, $src\t # long" %}
6450 opcode(MSGF_ZOPC, MSGF_ZOPC);
6451 ins_encode(z_form_rt_mem_opt(dst, src));
6452 ins_pipe(pipe_class_dummy);
6453 %}
6454
6455 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6456 match(Set dst (MulL dst (LoadL src)));
6457 ins_cost(MEMORY_REF_COST);
6458 size(Z_DISP3_SIZE);
6459 format %{ "MSG $dst, $src\t # long" %}
6460 opcode(MSG_ZOPC, MSG_ZOPC);
6461 ins_encode(z_form_rt_mem_opt(dst, src));
6462 ins_pipe(pipe_class_dummy);
6463 %}
6464
6465 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
6466 match(Set Rdst (MulHiL Rsrc1 Rsrc2));
6467 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
6468 ins_cost(7*DEFAULT_COST);
6469 // TODO: s390 port size(VARIABLE_SIZE);
6470 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
6471 ins_encode%{
6472 Register dst = $Rdst$$Register;
6473 Register src1 = $Rsrc1$$Register;
6474 Register src2 = $Rsrc2$$Register;
6475 Register tmp1 = $Rtmp1$$Register;
6476 Register tmp2 = $Rdst$$Register;
6477 // z/Architecture has only unsigned multiply (64 * 64 -> 128).
6478 // implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63))
6479 __ z_srag(tmp2, src1, 63); // a>>63
6480 __ z_srag(tmp1, src2, 63); // b>>63
6481 __ z_ngr(tmp2, src2); // b & (a>>63)
6482 __ z_ngr(tmp1, src1); // a & (b>>63)
6483 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63)))
6484 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1),
6485 // multiplicand is taken from oddReg (src1), multiplier in src2.
6486 __ z_sgr(dst, tmp1);
6487 %}
6488 ins_pipe(pipe_class_dummy);
6489 %}
6490
6491 // DIV
6492
6493 // Integer DIVMOD with Register, both quotient and mod results
6494 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6495 match(DivModI dst1src1 src2);
6496 effect(KILL cr);
6497 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6498 size(VM_Version::has_CompareBranch() ? 24 : 26);
6499 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6500 ins_encode %{
6501 Register d1s1 = $dst1src1$$Register;
6502 Register d2 = $dst2$$Register;
6503 Register s2 = $src2$$Register;
6504
6505 assert_different_registers(d1s1, s2);
6506
6507 Label do_div, done_div;
6508 if (VM_Version::has_CompareBranch()) {
6509 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6510 } else {
6511 __ z_chi(s2, -1);
6512 __ z_brne(do_div);
6513 }
6514 __ z_lcr(d1s1, d1s1);
6515 __ clear_reg(d2, false, false);
6516 __ z_bru(done_div);
6517 __ bind(do_div);
6518 __ z_lgfr(d1s1, d1s1);
6519 __ z_dsgfr(d2, s2);
6520 __ bind(done_div);
6521 %}
6522 ins_pipe(pipe_class_dummy);
6523 %}
6524
6525
6526 // Register Division
6527 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6528 match(Set dst (DivI src1 src2));
6529 effect(KILL tmp, KILL cr);
6530 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6531 size(VM_Version::has_CompareBranch() ? 20 : 22);
6532 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6533 ins_encode %{
6534 Register a = $src1$$Register;
6535 Register b = $src2$$Register;
6536 Register t = $dst$$Register;
6537
6538 assert_different_registers(t, b);
6539
6540 Label do_div, done_div;
6541 if (VM_Version::has_CompareBranch()) {
6542 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6543 } else {
6544 __ z_chi(b, -1);
6545 __ z_brne(do_div);
6546 }
6547 __ z_lcr(t, a);
6548 __ z_bru(done_div);
6549 __ bind(do_div);
6550 __ z_lgfr(t, a);
6551 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6552 __ bind(done_div);
6553 %}
6554 ins_pipe(pipe_class_dummy);
6555 %}
6556
6557 // Immediate Division
6558 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6559 match(Set dst (DivI src1 src2));
6560 effect(KILL tmp, KILL cr); // R0 is killed, too.
6561 ins_cost(2 * DEFAULT_COST);
6562 // TODO: s390 port size(VARIABLE_SIZE);
6563 format %{ "DIV_const $dst,$src1,$src2" %}
6564 ins_encode %{
6565 // No sign extension of Rdividend needed here.
6566 if ($src2$$constant != -1) {
6567 __ z_lghi(Z_R0_scratch, $src2$$constant);
6568 __ z_lgfr($dst$$Register, $src1$$Register);
6569 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6570 } else {
6571 __ z_lcr($dst$$Register, $src1$$Register);
6572 }
6573 %}
6574 ins_pipe(pipe_class_dummy);
6575 %}
6576
6577 // Long DIVMOD with Register, both quotient and mod results
6578 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6579 match(DivModL dst1src1 src2);
6580 effect(KILL cr);
6581 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6582 size(VM_Version::has_CompareBranch() ? 22 : 24);
6583 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6584 ins_encode %{
6585 Register d1s1 = $dst1src1$$Register;
6586 Register d2 = $dst2$$Register;
6587 Register s2 = $src2$$Register;
6588
6589 Label do_div, done_div;
6590 if (VM_Version::has_CompareBranch()) {
6591 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6592 } else {
6593 __ z_cghi(s2, -1);
6594 __ z_brne(do_div);
6595 }
6596 __ z_lcgr(d1s1, d1s1);
6597 // indicate unused result
6598 (void) __ clear_reg(d2, true, false);
6599 __ z_bru(done_div);
6600 __ bind(do_div);
6601 __ z_dsgr(d2, s2);
6602 __ bind(done_div);
6603 %}
6604 ins_pipe(pipe_class_dummy);
6605 %}
6606
6607 // Register Long Division
6608 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6609 match(Set dst (DivL dst src));
6610 effect(KILL tmp, KILL cr);
6611 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6612 size(VM_Version::has_CompareBranch() ? 18 : 20);
6613 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
6614 ins_encode %{
6615 Register b = $src$$Register;
6616 Register t = $dst$$Register;
6617
6618 Label done_div;
6619 __ z_lcgr(t, t); // Does no harm. divisor is in other register.
6620 if (VM_Version::has_CompareBranch()) {
6621 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6622 } else {
6623 __ z_cghi(b, -1);
6624 __ z_bre(done_div);
6625 }
6626 __ z_lcgr(t, t); // Restore sign.
6627 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6628 __ bind(done_div);
6629 %}
6630 ins_pipe(pipe_class_dummy);
6631 %}
6632
6633 // Immediate Long Division
6634 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6635 match(Set dst (DivL src1 src2));
6636 effect(KILL tmp, KILL cr); // R0 is killed, too.
6637 ins_cost(2 * DEFAULT_COST);
6638 // TODO: s390 port size(VARIABLE_SIZE);
6639 format %{ "DIVG_const $dst,$src1,$src2\t # long" %}
6640 ins_encode %{
6641 if ($src2$$constant != -1) {
6642 __ z_lghi(Z_R0_scratch, $src2$$constant);
6643 __ lgr_if_needed($dst$$Register, $src1$$Register);
6644 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6645 } else {
6646 __ z_lcgr($dst$$Register, $src1$$Register);
6647 }
6648 %}
6649 ins_pipe(pipe_class_dummy);
6650 %}
6651
6652 // REM
6653
6654 // Integer Remainder
6655 // Register Remainder
6656 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6657 match(Set dst (ModI src1 src2));
6658 effect(KILL tmp, KILL cr);
6659 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6660 // TODO: s390 port size(VARIABLE_SIZE);
6661 format %{ "MOD_checked $dst,$src1,$src2" %}
6662 ins_encode %{
6663 Register a = $src1$$Register;
6664 Register b = $src2$$Register;
6665 Register t = $dst$$Register;
6666 assert_different_registers(t->successor(), b);
6667
6668 Label do_div, done_div;
6669
6670 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6671 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs.
6672 if (VM_Version::has_CompareBranch()) {
6673 __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6674 } else {
6675 __ z_chi(b, -1);
6676 __ z_bre(done_div);
6677 }
6678 __ z_lgfr(t->successor(), a);
6679 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6680 } else {
6681 if (VM_Version::has_CompareBranch()) {
6682 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6683 } else {
6684 __ z_chi(b, -1);
6685 __ z_brne(do_div);
6686 }
6687 __ clear_reg(t, true, false);
6688 __ z_bru(done_div);
6689 __ bind(do_div);
6690 __ z_lgfr(t->successor(), a);
6691 __ z_dsgfr(t/* t is even part of a register pair. */, b);
6692 }
6693 __ bind(done_div);
6694 %}
6695 ins_pipe(pipe_class_dummy);
6696 %}
6697
6698 // Immediate Remainder
6699 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6700 match(Set dst (ModI src1 src2));
6701 effect(KILL tmp, KILL cr); // R0 is killed, too.
6702 ins_cost(3 * DEFAULT_COST);
6703 // TODO: s390 port size(VARIABLE_SIZE);
6704 format %{ "MOD_const $dst,src1,$src2" %}
6705 ins_encode %{
6706 assert_different_registers($dst$$Register, $src1$$Register);
6707 assert_different_registers($dst$$Register->successor(), $src1$$Register);
6708 int divisor = $src2$$constant;
6709
6710 if (divisor != -1) {
6711 __ z_lghi(Z_R0_scratch, divisor);
6712 __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6713 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6714 } else {
6715 __ clear_reg($dst$$Register, true, false);
6716 }
6717 %}
6718 ins_pipe(pipe_class_dummy);
6719 %}
6720
6721 // Register Long Remainder
6722 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6723 match(Set dst (ModL src1 src2));
6724 effect(KILL src1, KILL cr); // R0 is killed, too.
6725 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6726 // TODO: s390 port size(VARIABLE_SIZE);
6727 format %{ "MODG_checked $dst,$src1,$src2" %}
6728 ins_encode %{
6729 Register a = $src1$$Register;
6730 Register b = $src2$$Register;
6731 Register t = $dst$$Register;
6732 assert(t->successor() == a, "(t,a) is an even-odd pair" );
6733
6734 Label do_div, done_div;
6735 if (t->encoding() != b->encoding()) {
6736 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6737 if (VM_Version::has_CompareBranch()) {
6738 __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6739 } else {
6740 __ z_cghi(b, -1);
6741 __ z_bre(done_div);
6742 }
6743 __ z_dsgr(t, b);
6744 } else {
6745 if (VM_Version::has_CompareBranch()) {
6746 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6747 } else {
6748 __ z_cghi(b, -1);
6749 __ z_brne(do_div);
6750 }
6751 __ clear_reg(t, true, false);
6752 __ z_bru(done_div);
6753 __ bind(do_div);
6754 __ z_dsgr(t, b);
6755 }
6756 __ bind(done_div);
6757 %}
6758 ins_pipe(pipe_class_dummy);
6759 %}
6760
6761 // Register Long Remainder
6762 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
6763 match(Set dst (ModL src1 src2));
6764 effect(KILL tmp, KILL cr); // R0 is killed, too.
6765 ins_cost(3 * DEFAULT_COST);
6766 // TODO: s390 port size(VARIABLE_SIZE);
6767 format %{ "MODG_const $dst,src1,$src2\t # long" %}
6768 ins_encode %{
6769 int divisor = $src2$$constant;
6770 if (divisor != -1) {
6771 __ z_lghi(Z_R0_scratch, divisor);
6772 __ z_lgr($dst$$Register->successor(), $src1$$Register);
6773 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6774 } else {
6775 __ clear_reg($dst$$Register, true, false);
6776 }
6777 %}
6778 ins_pipe(pipe_class_dummy);
6779 %}
6780
6781 // SHIFT
6782
6783 // Shift left logical
6784
6785 // Register Shift Left variable
6786 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
6787 match(Set dst (LShiftI src nbits));
6788 effect(KILL cr); // R1 is killed, too.
6789 ins_cost(3 * DEFAULT_COST);
6790 size(14);
6791 format %{ "SLL $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %}
6792 ins_encode %{
6793 __ z_lgr(Z_R1_scratch, $nbits$$Register);
6794 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6795 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6796 %}
6797 ins_pipe(pipe_class_dummy);
6798 %}
6799
6800 // Register Shift Left Immediate
6801 // Constant shift count is masked in ideal graph already.
6802 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6803 match(Set dst (LShiftI src nbits));
6804 size(6);
6805 format %{ "SLL $dst,$src,$nbits\t# use RISC-like SLLG also for int" %}
6806 ins_encode %{
6807 int Nbit = $nbits$$constant;
6808 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6809 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6810 %}
6811 ins_pipe(pipe_class_dummy);
6812 %}
6813
6814 // Register Shift Left Immediate by 1bit
6815 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6816 match(Set dst (LShiftI src nbits));
6817 predicate(PreferLAoverADD);
6818 ins_cost(DEFAULT_COST_LOW);
6819 size(4);
6820 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6821 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6822 ins_pipe(pipe_class_dummy);
6823 %}
6824
6825 // Register Shift Left Long
6826 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
6827 match(Set dst (LShiftL src1 nbits));
6828 size(6);
6829 format %{ "SLLG $dst,$src1,[$nbits]" %}
6830 opcode(SLLG_ZOPC);
6831 ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
6832 ins_pipe(pipe_class_dummy);
6833 %}
6834
6835 // Register Shift Left Long Immediate
6836 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
6837 match(Set dst (LShiftL src1 nbits));
6838 size(6);
6839 format %{ "SLLG $dst,$src1,$nbits" %}
6840 opcode(SLLG_ZOPC);
6841 ins_encode(z_rsyform_const(dst, src1, nbits));
6842 ins_pipe(pipe_class_dummy);
6843 %}
6844
6845 // Register Shift Left Long Immediate by 1bit
6846 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
6847 match(Set dst (LShiftL src1 nbits));
6848 predicate(PreferLAoverADD);
6849 ins_cost(DEFAULT_COST_LOW);
6850 size(4);
6851 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
6852 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
6853 ins_pipe(pipe_class_dummy);
6854 %}
6855
6856 // Shift right arithmetic
6857
6858 // Register Arithmetic Shift Right
6859 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6860 match(Set dst (RShiftI dst src));
6861 effect(KILL cr); // R1 is killed, too.
6862 ins_cost(3 * DEFAULT_COST);
6863 size(12);
6864 format %{ "SRA $dst,[$src] & 31" %}
6865 ins_encode %{
6866 __ z_lgr(Z_R1_scratch, $src$$Register);
6867 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6868 __ z_sra($dst$$Register, 0, Z_R1_scratch);
6869 %}
6870 ins_pipe(pipe_class_dummy);
6871 %}
6872
6873 // Register Arithmetic Shift Right Immediate
6874 // Constant shift count is masked in ideal graph already.
6875 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
6876 match(Set dst (RShiftI dst src));
6877 effect(KILL cr);
6878 size(4);
6879 format %{ "SRA $dst,$src" %}
6880 ins_encode %{
6881 int Nbit = $src$$constant;
6882 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6883 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6884 %}
6885 ins_pipe(pipe_class_dummy);
6886 %}
6887
6888 // Register Arithmetic Shift Right Long
6889 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
6890 match(Set dst (RShiftL src1 src2));
6891 effect(KILL cr);
6892 size(6);
6893 format %{ "SRAG $dst,$src1,[$src2]" %}
6894 opcode(SRAG_ZOPC);
6895 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6896 ins_pipe(pipe_class_dummy);
6897 %}
6898
6899 // Register Arithmetic Shift Right Long Immediate
6900 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
6901 match(Set dst (RShiftL src1 src2));
6902 effect(KILL cr);
6903 size(6);
6904 format %{ "SRAG $dst,$src1,$src2" %}
6905 opcode(SRAG_ZOPC);
6906 ins_encode(z_rsyform_const(dst, src1, src2));
6907 ins_pipe(pipe_class_dummy);
6908 %}
6909
6910 // Shift right logical
6911
6912 // Register Shift Right
6913 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6914 match(Set dst (URShiftI dst src));
6915 effect(KILL cr); // R1 is killed, too.
6916 ins_cost(3 * DEFAULT_COST);
6917 size(12);
6918 format %{ "SRL $dst,[$src] & 31" %}
6919 ins_encode %{
6920 __ z_lgr(Z_R1_scratch, $src$$Register);
6921 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6922 __ z_srl($dst$$Register, 0, Z_R1_scratch);
6923 %}
6924 ins_pipe(pipe_class_dummy);
6925 %}
6926
6927 // Register Shift Right Immediate
6928 // Constant shift count is masked in ideal graph already.
6929 instruct srlI_reg_imm(iRegI dst, immI src) %{
6930 match(Set dst (URShiftI dst src));
6931 size(4);
6932 format %{ "SRL $dst,$src" %}
6933 ins_encode %{
6934 int Nbit = $src$$constant;
6935 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6936 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6937 %}
6938 ins_pipe(pipe_class_dummy);
6939 %}
6940
6941 // Register Shift Right Long
6942 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
6943 match(Set dst (URShiftL src1 src2));
6944 size(6);
6945 format %{ "SRLG $dst,$src1,[$src2]" %}
6946 opcode(SRLG_ZOPC);
6947 ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6948 ins_pipe(pipe_class_dummy);
6949 %}
6950
6951 // Register Shift Right Long Immediate
6952 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
6953 match(Set dst (URShiftL src1 src2));
6954 size(6);
6955 format %{ "SRLG $dst,$src1,$src2" %}
6956 opcode(SRLG_ZOPC);
6957 ins_encode(z_rsyform_const(dst, src1, src2));
6958 ins_pipe(pipe_class_dummy);
6959 %}
6960
6961 // Register Shift Right Immediate with a CastP2X
6962 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
6963 match(Set dst (URShiftL (CastP2X src1) src2));
6964 size(6);
6965 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
6966 opcode(SRLG_ZOPC);
6967 ins_encode(z_rsyform_const(dst, src1, src2));
6968 ins_pipe(pipe_class_dummy);
6969 %}
6970
6971 //----------Rotate Instructions------------------------------------------------
6972
6973 // Rotate left 32bit.
6974 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
6975 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
6976 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
6977 size(6);
6978 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %}
6979 opcode(RLL_ZOPC);
6980 ins_encode(z_rsyform_const(dst, src, lshift));
6981 ins_pipe(pipe_class_dummy);
6982 %}
6983
6984 // Rotate left 64bit.
6985 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
6986 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
6987 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
6988 size(6);
6989 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %}
6990 opcode(RLLG_ZOPC);
6991 ins_encode(z_rsyform_const(dst, src, lshift));
6992 ins_pipe(pipe_class_dummy);
6993 %}
6994
6995 // Rotate right 32bit.
6996 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
6997 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
6998 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
6999 // TODO: s390 port size(FIXED_SIZE);
7000 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %}
7001 opcode(RLL_ZOPC);
7002 ins_encode(z_rsyform_const(dst, src, rshift));
7003 ins_pipe(pipe_class_dummy);
7004 %}
7005
7006 // Rotate right 64bit.
7007 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
7008 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
7009 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7010 // TODO: s390 port size(FIXED_SIZE);
7011 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %}
7012 opcode(RLLG_ZOPC);
7013 ins_encode(z_rsyform_const(dst, src, rshift));
7014 ins_pipe(pipe_class_dummy);
7015 %}
7016
7017
7018 //----------Overflow Math Instructions-----------------------------------------
7019
7020 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7021 match(Set cr (OverflowAddI op1 op2));
7022 effect(DEF cr, USE op1, USE op2);
7023 // TODO: s390 port size(FIXED_SIZE);
7024 format %{ "AR $op1,$op2\t # overflow check int" %}
7025 ins_encode %{
7026 __ z_lr(Z_R0_scratch, $op1$$Register);
7027 __ z_ar(Z_R0_scratch, $op2$$Register);
7028 %}
7029 ins_pipe(pipe_class_dummy);
7030 %}
7031
7032 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7033 match(Set cr (OverflowAddI op1 op2));
7034 effect(DEF cr, USE op1, USE op2);
7035 // TODO: s390 port size(VARIABLE_SIZE);
7036 format %{ "AR $op1,$op2\t # overflow check int" %}
7037 ins_encode %{
7038 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7039 __ z_ar(Z_R0_scratch, $op1$$Register);
7040 %}
7041 ins_pipe(pipe_class_dummy);
7042 %}
7043
7044 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7045 match(Set cr (OverflowAddL op1 op2));
7046 effect(DEF cr, USE op1, USE op2);
7047 // TODO: s390 port size(FIXED_SIZE);
7048 format %{ "AGR $op1,$op2\t # overflow check long" %}
7049 ins_encode %{
7050 __ z_lgr(Z_R0_scratch, $op1$$Register);
7051 __ z_agr(Z_R0_scratch, $op2$$Register);
7052 %}
7053 ins_pipe(pipe_class_dummy);
7054 %}
7055
7056 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7057 match(Set cr (OverflowAddL op1 op2));
7058 effect(DEF cr, USE op1, USE op2);
7059 // TODO: s390 port size(VARIABLE_SIZE);
7060 format %{ "AGR $op1,$op2\t # overflow check long" %}
7061 ins_encode %{
7062 __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7063 __ z_agr(Z_R0_scratch, $op1$$Register);
7064 %}
7065 ins_pipe(pipe_class_dummy);
7066 %}
7067
7068 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7069 match(Set cr (OverflowSubI op1 op2));
7070 effect(DEF cr, USE op1, USE op2);
7071 // TODO: s390 port size(FIXED_SIZE);
7072 format %{ "SR $op1,$op2\t # overflow check int" %}
7073 ins_encode %{
7074 __ z_lr(Z_R0_scratch, $op1$$Register);
7075 __ z_sr(Z_R0_scratch, $op2$$Register);
7076 %}
7077 ins_pipe(pipe_class_dummy);
7078 %}
7079
7080 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7081 match(Set cr (OverflowSubI op1 op2));
7082 effect(DEF cr, USE op1, USE op2);
7083 // TODO: s390 port size(VARIABLE_SIZE);
7084 format %{ "SR $op1,$op2\t # overflow check int" %}
7085 ins_encode %{
7086 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7087 __ z_lr(Z_R0_scratch, $op1$$Register);
7088 __ z_sr(Z_R0_scratch, Z_R1_scratch);
7089 %}
7090 ins_pipe(pipe_class_dummy);
7091 %}
7092
7093 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7094 match(Set cr (OverflowSubL op1 op2));
7095 effect(DEF cr, USE op1, USE op2);
7096 // TODO: s390 port size(FIXED_SIZE);
7097 format %{ "SGR $op1,$op2\t # overflow check long" %}
7098 ins_encode %{
7099 __ z_lgr(Z_R0_scratch, $op1$$Register);
7100 __ z_sgr(Z_R0_scratch, $op2$$Register);
7101 %}
7102 ins_pipe(pipe_class_dummy);
7103 %}
7104
7105 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7106 match(Set cr (OverflowSubL op1 op2));
7107 effect(DEF cr, USE op1, USE op2);
7108 // TODO: s390 port size(VARIABLE_SIZE);
7109 format %{ "SGR $op1,$op2\t # overflow check long" %}
7110 ins_encode %{
7111 __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7112 __ z_lgr(Z_R0_scratch, $op1$$Register);
7113 __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7114 %}
7115 ins_pipe(pipe_class_dummy);
7116 %}
7117
7118 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7119 match(Set cr (OverflowSubI zero op2));
7120 effect(DEF cr, USE op2);
7121 format %{ "NEG $op2\t# overflow check int" %}
7122 ins_encode %{
7123 __ clear_reg(Z_R0_scratch, false, false);
7124 __ z_sr(Z_R0_scratch, $op2$$Register);
7125 %}
7126 ins_pipe(pipe_class_dummy);
7127 %}
7128
7129 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7130 match(Set cr (OverflowSubL zero op2));
7131 effect(DEF cr, USE op2);
7132 format %{ "NEGG $op2\t# overflow check long" %}
7133 ins_encode %{
7134 __ clear_reg(Z_R0_scratch, true, false);
7135 __ z_sgr(Z_R0_scratch, $op2$$Register);
7136 %}
7137 ins_pipe(pipe_class_dummy);
7138 %}
7139
7140 // No intrinsics for multiplication, since there is no easy way
7141 // to check for overflow.
7142
7143
7144 //----------Floating Point Arithmetic Instructions-----------------------------
7145
7146 // ADD
7147
7148 // Add float single precision
7149 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7150 match(Set dst (AddF dst src));
7151 effect(KILL cr);
7152 ins_cost(ALU_REG_COST);
7153 size(4);
7154 format %{ "AEBR $dst,$src" %}
7155 opcode(AEBR_ZOPC);
7156 ins_encode(z_rreform(dst, src));
7157 ins_pipe(pipe_class_dummy);
7158 %}
7159
7160 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7161 match(Set dst (AddF dst (LoadF src)));
7162 effect(KILL cr);
7163 ins_cost(ALU_MEMORY_COST);
7164 size(6);
7165 format %{ "AEB $dst,$src\t # floatMemory" %}
7166 opcode(AEB_ZOPC);
7167 ins_encode(z_form_rt_memFP(dst, src));
7168 ins_pipe(pipe_class_dummy);
7169 %}
7170
7171 // Add float double precision
7172 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7173 match(Set dst (AddD dst src));
7174 effect(KILL cr);
7175 ins_cost(ALU_REG_COST);
7176 size(4);
7177 format %{ "ADBR $dst,$src" %}
7178 opcode(ADBR_ZOPC);
7179 ins_encode(z_rreform(dst, src));
7180 ins_pipe(pipe_class_dummy);
7181 %}
7182
7183 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7184 match(Set dst (AddD dst (LoadD src)));
7185 effect(KILL cr);
7186 ins_cost(ALU_MEMORY_COST);
7187 size(6);
7188 format %{ "ADB $dst,$src\t # doubleMemory" %}
7189 opcode(ADB_ZOPC);
7190 ins_encode(z_form_rt_memFP(dst, src));
7191 ins_pipe(pipe_class_dummy);
7192 %}
7193
7194 // SUB
7195
7196 // Sub float single precision
7197 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7198 match(Set dst (SubF dst src));
7199 effect(KILL cr);
7200 ins_cost(ALU_REG_COST);
7201 size(4);
7202 format %{ "SEBR $dst,$src" %}
7203 opcode(SEBR_ZOPC);
7204 ins_encode(z_rreform(dst, src));
7205 ins_pipe(pipe_class_dummy);
7206 %}
7207
7208 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7209 match(Set dst (SubF dst (LoadF src)));
7210 effect(KILL cr);
7211 ins_cost(ALU_MEMORY_COST);
7212 size(6);
7213 format %{ "SEB $dst,$src\t # floatMemory" %}
7214 opcode(SEB_ZOPC);
7215 ins_encode(z_form_rt_memFP(dst, src));
7216 ins_pipe(pipe_class_dummy);
7217 %}
7218
7219 // Sub float double precision
7220 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7221 match(Set dst (SubD dst src));
7222 effect(KILL cr);
7223 ins_cost(ALU_REG_COST);
7224 size(4);
7225 format %{ "SDBR $dst,$src" %}
7226 opcode(SDBR_ZOPC);
7227 ins_encode(z_rreform(dst, src));
7228 ins_pipe(pipe_class_dummy);
7229 %}
7230
7231 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7232 match(Set dst (SubD dst (LoadD src)));
7233 effect(KILL cr);
7234 ins_cost(ALU_MEMORY_COST);
7235 size(6);
7236 format %{ "SDB $dst,$src\t # doubleMemory" %}
7237 opcode(SDB_ZOPC);
7238 ins_encode(z_form_rt_memFP(dst, src));
7239 ins_pipe(pipe_class_dummy);
7240 %}
7241
7242 // MUL
7243
7244 // Mul float single precision
7245 instruct mulF_reg_reg(regF dst, regF src) %{
7246 match(Set dst (MulF dst src));
7247 // CC unchanged by MUL.
7248 ins_cost(ALU_REG_COST);
7249 size(4);
7250 format %{ "MEEBR $dst,$src" %}
7251 opcode(MEEBR_ZOPC);
7252 ins_encode(z_rreform(dst, src));
7253 ins_pipe(pipe_class_dummy);
7254 %}
7255
7256 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7257 match(Set dst (MulF dst (LoadF src)));
7258 // CC unchanged by MUL.
7259 ins_cost(ALU_MEMORY_COST);
7260 size(6);
7261 format %{ "MEEB $dst,$src\t # floatMemory" %}
7262 opcode(MEEB_ZOPC);
7263 ins_encode(z_form_rt_memFP(dst, src));
7264 ins_pipe(pipe_class_dummy);
7265 %}
7266
7267 // Mul float double precision
7268 instruct mulD_reg_reg(regD dst, regD src) %{
7269 match(Set dst (MulD dst src));
7270 // CC unchanged by MUL.
7271 ins_cost(ALU_REG_COST);
7272 size(4);
7273 format %{ "MDBR $dst,$src" %}
7274 opcode(MDBR_ZOPC);
7275 ins_encode(z_rreform(dst, src));
7276 ins_pipe(pipe_class_dummy);
7277 %}
7278
7279 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7280 match(Set dst (MulD dst (LoadD src)));
7281 // CC unchanged by MUL.
7282 ins_cost(ALU_MEMORY_COST);
7283 size(6);
7284 format %{ "MDB $dst,$src\t # doubleMemory" %}
7285 opcode(MDB_ZOPC);
7286 ins_encode(z_form_rt_memFP(dst, src));
7287 ins_pipe(pipe_class_dummy);
7288 %}
7289
7290 // Multiply-Accumulate
7291 // src1 * src2 + dst
7292 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7293 match(Set dst (FmaF dst (Binary src1 src2)));
7294 // CC unchanged by MUL-ADD.
7295 ins_cost(ALU_REG_COST);
7296 size(4);
7297 format %{ "MAEBR $dst, $src1, $src2" %}
7298 ins_encode %{
7299 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7300 %}
7301 ins_pipe(pipe_class_dummy);
7302 %}
7303
7304 // src1 * src2 + dst
7305 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7306 match(Set dst (FmaD dst (Binary src1 src2)));
7307 // CC unchanged by MUL-ADD.
7308 ins_cost(ALU_REG_COST);
7309 size(4);
7310 format %{ "MADBR $dst, $src1, $src2" %}
7311 ins_encode %{
7312 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7313 %}
7314 ins_pipe(pipe_class_dummy);
7315 %}
7316
7317 // src1 * src2 - dst
7318 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7319 match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7320 // CC unchanged by MUL-SUB.
7321 ins_cost(ALU_REG_COST);
7322 size(4);
7323 format %{ "MSEBR $dst, $src1, $src2" %}
7324 ins_encode %{
7325 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7326 %}
7327 ins_pipe(pipe_class_dummy);
7328 %}
7329
7330 // src1 * src2 - dst
7331 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7332 match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7333 // CC unchanged by MUL-SUB.
7334 ins_cost(ALU_REG_COST);
7335 size(4);
7336 format %{ "MSDBR $dst, $src1, $src2" %}
7337 ins_encode %{
7338 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7339 %}
7340 ins_pipe(pipe_class_dummy);
7341 %}
7342
7343 // src1 * src2 + dst
7344 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7345 match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7346 // CC unchanged by MUL-ADD.
7347 ins_cost(ALU_MEMORY_COST);
7348 size(6);
7349 format %{ "MAEB $dst, $src1, $src2" %}
7350 ins_encode %{
7351 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7352 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7353 %}
7354 ins_pipe(pipe_class_dummy);
7355 %}
7356
7357 // src1 * src2 + dst
7358 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7359 match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7360 // CC unchanged by MUL-ADD.
7361 ins_cost(ALU_MEMORY_COST);
7362 size(6);
7363 format %{ "MADB $dst, $src1, $src2" %}
7364 ins_encode %{
7365 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7366 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7367 %}
7368 ins_pipe(pipe_class_dummy);
7369 %}
7370
7371 // src1 * src2 - dst
7372 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7373 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7374 // CC unchanged by MUL-SUB.
7375 ins_cost(ALU_MEMORY_COST);
7376 size(6);
7377 format %{ "MSEB $dst, $src1, $src2" %}
7378 ins_encode %{
7379 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7380 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7381 %}
7382 ins_pipe(pipe_class_dummy);
7383 %}
7384
7385 // src1 * src2 - dst
7386 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7387 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7388 // CC unchanged by MUL-SUB.
7389 ins_cost(ALU_MEMORY_COST);
7390 size(6);
7391 format %{ "MSDB $dst, $src1, $src2" %}
7392 ins_encode %{
7393 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7394 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7395 %}
7396 ins_pipe(pipe_class_dummy);
7397 %}
7398
7399 // src1 * src2 + dst
7400 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7401 match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7402 // CC unchanged by MUL-ADD.
7403 ins_cost(ALU_MEMORY_COST);
7404 size(6);
7405 format %{ "MAEB $dst, $src1, $src2" %}
7406 ins_encode %{
7407 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7408 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7409 %}
7410 ins_pipe(pipe_class_dummy);
7411 %}
7412
7413 // src1 * src2 + dst
7414 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7415 match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7416 // CC unchanged by MUL-ADD.
7417 ins_cost(ALU_MEMORY_COST);
7418 size(6);
7419 format %{ "MADB $dst, $src1, $src2" %}
7420 ins_encode %{
7421 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7422 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7423 %}
7424 ins_pipe(pipe_class_dummy);
7425 %}
7426
7427 // src1 * src2 - dst
7428 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7429 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7430 // CC unchanged by MUL-SUB.
7431 ins_cost(ALU_MEMORY_COST);
7432 size(6);
7433 format %{ "MSEB $dst, $src1, $src2" %}
7434 ins_encode %{
7435 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7436 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7437 %}
7438 ins_pipe(pipe_class_dummy);
7439 %}
7440
7441 // src1 * src2 - dst
7442 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7443 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7444 // CC unchanged by MUL-SUB.
7445 ins_cost(ALU_MEMORY_COST);
7446 size(6);
7447 format %{ "MSDB $dst, $src1, $src2" %}
7448 ins_encode %{
7449 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7450 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7451 %}
7452 ins_pipe(pipe_class_dummy);
7453 %}
7454
7455 // DIV
7456
7457 // Div float single precision
7458 instruct divF_reg_reg(regF dst, regF src) %{
7459 match(Set dst (DivF dst src));
7460 // CC unchanged by DIV.
7461 ins_cost(ALU_REG_COST);
7462 size(4);
7463 format %{ "DEBR $dst,$src" %}
7464 opcode(DEBR_ZOPC);
7465 ins_encode(z_rreform(dst, src));
7466 ins_pipe(pipe_class_dummy);
7467 %}
7468
7469 instruct divF_reg_mem(regF dst, memoryRX src)%{
7470 match(Set dst (DivF dst (LoadF src)));
7471 // CC unchanged by DIV.
7472 ins_cost(ALU_MEMORY_COST);
7473 size(6);
7474 format %{ "DEB $dst,$src\t # floatMemory" %}
7475 opcode(DEB_ZOPC);
7476 ins_encode(z_form_rt_memFP(dst, src));
7477 ins_pipe(pipe_class_dummy);
7478 %}
7479
7480 // Div float double precision
7481 instruct divD_reg_reg(regD dst, regD src) %{
7482 match(Set dst (DivD dst src));
7483 // CC unchanged by DIV.
7484 ins_cost(ALU_REG_COST);
7485 size(4);
7486 format %{ "DDBR $dst,$src" %}
7487 opcode(DDBR_ZOPC);
7488 ins_encode(z_rreform(dst, src));
7489 ins_pipe(pipe_class_dummy);
7490 %}
7491
7492 instruct divD_reg_mem(regD dst, memoryRX src)%{
7493 match(Set dst (DivD dst (LoadD src)));
7494 // CC unchanged by DIV.
7495 ins_cost(ALU_MEMORY_COST);
7496 size(6);
7497 format %{ "DDB $dst,$src\t # doubleMemory" %}
7498 opcode(DDB_ZOPC);
7499 ins_encode(z_form_rt_memFP(dst, src));
7500 ins_pipe(pipe_class_dummy);
7501 %}
7502
7503 // ABS
7504
7505 // Absolute float single precision
7506 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7507 match(Set dst (AbsF src));
7508 effect(KILL cr);
7509 size(4);
7510 format %{ "LPEBR $dst,$src\t float" %}
7511 opcode(LPEBR_ZOPC);
7512 ins_encode(z_rreform(dst, src));
7513 ins_pipe(pipe_class_dummy);
7514 %}
7515
7516 // Absolute float double precision
7517 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7518 match(Set dst (AbsD src));
7519 effect(KILL cr);
7520 size(4);
7521 format %{ "LPDBR $dst,$src\t double" %}
7522 opcode(LPDBR_ZOPC);
7523 ins_encode(z_rreform(dst, src));
7524 ins_pipe(pipe_class_dummy);
7525 %}
7526
7527 // NEG(ABS)
7528
7529 // Negative absolute float single precision
7530 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7531 match(Set dst (NegF (AbsF src)));
7532 effect(KILL cr);
7533 size(4);
7534 format %{ "LNEBR $dst,$src\t float" %}
7535 opcode(LNEBR_ZOPC);
7536 ins_encode(z_rreform(dst, src));
7537 ins_pipe(pipe_class_dummy);
7538 %}
7539
7540 // Negative absolute float double precision
7541 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7542 match(Set dst (NegD (AbsD src)));
7543 effect(KILL cr);
7544 size(4);
7545 format %{ "LNDBR $dst,$src\t double" %}
7546 opcode(LNDBR_ZOPC);
7547 ins_encode(z_rreform(dst, src));
7548 ins_pipe(pipe_class_dummy);
7549 %}
7550
7551 // NEG
7552
7553 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7554 match(Set dst (NegF src));
7555 effect(KILL cr);
7556 size(4);
7557 format %{ "NegF $dst,$src\t float" %}
7558 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7559 ins_pipe(pipe_class_dummy);
7560 %}
7561
7562 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7563 match(Set dst (NegD src));
7564 effect(KILL cr);
7565 size(4);
7566 format %{ "NegD $dst,$src\t double" %}
7567 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7568 ins_pipe(pipe_class_dummy);
7569 %}
7570
7571 // SQRT
7572
7573 // Sqrt float precision
7574 instruct sqrtF_reg(regF dst, regF src) %{
7575 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7576 // CC remains unchanged.
7577 ins_cost(ALU_REG_COST);
7578 size(4);
7579 format %{ "SQEBR $dst,$src" %}
7580 opcode(SQEBR_ZOPC);
7581 ins_encode(z_rreform(dst, src));
7582 ins_pipe(pipe_class_dummy);
7583 %}
7584
7585 // Sqrt double precision
7586 instruct sqrtD_reg(regD dst, regD src) %{
7587 match(Set dst (SqrtD src));
7588 // CC remains unchanged.
7589 ins_cost(ALU_REG_COST);
7590 size(4);
7591 format %{ "SQDBR $dst,$src" %}
7592 opcode(SQDBR_ZOPC);
7593 ins_encode(z_rreform(dst, src));
7594 ins_pipe(pipe_class_dummy);
7595 %}
7596
7597 instruct sqrtF_mem(regF dst, memoryRX src) %{
7598 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7599 // CC remains unchanged.
7600 ins_cost(ALU_MEMORY_COST);
7601 size(6);
7602 format %{ "SQEB $dst,$src\t # floatMemory" %}
7603 opcode(SQEB_ZOPC);
7604 ins_encode(z_form_rt_memFP(dst, src));
7605 ins_pipe(pipe_class_dummy);
7606 %}
7607
7608 instruct sqrtD_mem(regD dst, memoryRX src) %{
7609 match(Set dst (SqrtD src));
7610 // CC remains unchanged.
7611 ins_cost(ALU_MEMORY_COST);
7612 // TODO: s390 port size(FIXED_SIZE);
7613 format %{ "SQDB $dst,$src\t # doubleMemory" %}
7614 opcode(SQDB_ZOPC);
7615 ins_encode(z_form_rt_memFP(dst, src));
7616 ins_pipe(pipe_class_dummy);
7617 %}
7618
7619 //----------Logical Instructions-----------------------------------------------
7620
7621 // Register And
7622 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7623 match(Set dst (AndI dst src));
7624 effect(KILL cr);
7625 ins_cost(DEFAULT_COST_LOW);
7626 size(2);
7627 format %{ "NR $dst,$src\t # int" %}
7628 opcode(NR_ZOPC);
7629 ins_encode(z_rrform(dst, src));
7630 ins_pipe(pipe_class_dummy);
7631 %}
7632
7633 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7634 match(Set dst (AndI dst (LoadI src)));
7635 effect(KILL cr);
7636 ins_cost(MEMORY_REF_COST);
7637 // TODO: s390 port size(VARIABLE_SIZE);
7638 format %{ "N(Y) $dst, $src\t # int" %}
7639 opcode(NY_ZOPC, N_ZOPC);
7640 ins_encode(z_form_rt_mem_opt(dst, src));
7641 ins_pipe(pipe_class_dummy);
7642 %}
7643
7644 // Immediate And
7645 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7646 match(Set dst (AndI dst src));
7647 effect(KILL cr);
7648 ins_cost(DEFAULT_COST_HIGH);
7649 size(6);
7650 format %{ "NILF $dst,$src" %}
7651 opcode(NILF_ZOPC);
7652 ins_encode(z_rilform_unsigned(dst, src));
7653 ins_pipe(pipe_class_dummy);
7654 %}
7655
7656 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7657 match(Set dst (AndI dst src));
7658 effect(KILL cr);
7659 ins_cost(DEFAULT_COST);
7660 size(4);
7661 format %{ "NILH $dst,$src" %}
7662 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7663 ins_pipe(pipe_class_dummy);
7664 %}
7665
7666 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7667 match(Set dst (AndI dst src));
7668 effect(KILL cr);
7669 ins_cost(DEFAULT_COST);
7670 size(4);
7671 format %{ "NILL $dst,$src" %}
7672 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7673 ins_pipe(pipe_class_dummy);
7674 %}
7675
7676 // Register And Long
7677 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7678 match(Set dst (AndL dst src));
7679 effect(KILL cr);
7680 ins_cost(DEFAULT_COST);
7681 size(4);
7682 format %{ "NGR $dst,$src\t # long" %}
7683 opcode(NGR_ZOPC);
7684 ins_encode(z_rreform(dst, src));
7685 ins_pipe(pipe_class_dummy);
7686 %}
7687
7688 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7689 match(Set dst (AndL dst (LoadL src)));
7690 effect(KILL cr);
7691 ins_cost(MEMORY_REF_COST);
7692 size(Z_DISP3_SIZE);
7693 format %{ "NG $dst, $src\t # long" %}
7694 opcode(NG_ZOPC, NG_ZOPC);
7695 ins_encode(z_form_rt_mem_opt(dst, src));
7696 ins_pipe(pipe_class_dummy);
7697 %}
7698
7699 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7700 match(Set dst (AndL dst src));
7701 effect(KILL cr);
7702 ins_cost(DEFAULT_COST);
7703 size(4);
7704 format %{ "NILL $dst,$src\t # long" %}
7705 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7706 ins_pipe(pipe_class_dummy);
7707 %}
7708
7709 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7710 match(Set dst (AndL dst src));
7711 effect(KILL cr);
7712 ins_cost(DEFAULT_COST);
7713 size(4);
7714 format %{ "NILH $dst,$src\t # long" %}
7715 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7716 ins_pipe(pipe_class_dummy);
7717 %}
7718
7719 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7720 match(Set dst (AndL dst src));
7721 effect(KILL cr);
7722 ins_cost(DEFAULT_COST);
7723 size(4);
7724 format %{ "NIHL $dst,$src\t # long" %}
7725 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7726 ins_pipe(pipe_class_dummy);
7727 %}
7728
7729 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7730 match(Set dst (AndL dst src));
7731 effect(KILL cr);
7732 ins_cost(DEFAULT_COST);
7733 size(4);
7734 format %{ "NIHH $dst,$src\t # long" %}
7735 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7736 ins_pipe(pipe_class_dummy);
7737 %}
7738
7739 // OR
7740
7741 // Or Instructions
7742 // Register Or
7743 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7744 match(Set dst (OrI dst src));
7745 effect(KILL cr);
7746 size(2);
7747 format %{ "OR $dst,$src" %}
7748 opcode(OR_ZOPC);
7749 ins_encode(z_rrform(dst, src));
7750 ins_pipe(pipe_class_dummy);
7751 %}
7752
7753 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7754 match(Set dst (OrI dst (LoadI src)));
7755 effect(KILL cr);
7756 ins_cost(MEMORY_REF_COST);
7757 // TODO: s390 port size(VARIABLE_SIZE);
7758 format %{ "O(Y) $dst, $src\t # int" %}
7759 opcode(OY_ZOPC, O_ZOPC);
7760 ins_encode(z_form_rt_mem_opt(dst, src));
7761 ins_pipe(pipe_class_dummy);
7762 %}
7763
7764 // Immediate Or
7765 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
7766 match(Set dst (OrI dst con));
7767 effect(KILL cr);
7768 size(4);
7769 format %{ "OILL $dst,$con" %}
7770 opcode(OILL_ZOPC);
7771 ins_encode(z_riform_unsigned(dst,con));
7772 ins_pipe(pipe_class_dummy);
7773 %}
7774
7775 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
7776 match(Set dst (OrI dst con));
7777 effect(KILL cr);
7778 ins_cost(DEFAULT_COST_HIGH);
7779 size(6);
7780 format %{ "OILF $dst,$con" %}
7781 opcode(OILF_ZOPC);
7782 ins_encode(z_rilform_unsigned(dst,con));
7783 ins_pipe(pipe_class_dummy);
7784 %}
7785
7786 // Register Or Long
7787 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7788 match(Set dst (OrL dst src));
7789 effect(KILL cr);
7790 ins_cost(DEFAULT_COST);
7791 size(4);
7792 format %{ "OGR $dst,$src\t # long" %}
7793 opcode(OGR_ZOPC);
7794 ins_encode(z_rreform(dst, src));
7795 ins_pipe(pipe_class_dummy);
7796 %}
7797
7798 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7799 match(Set dst (OrL dst (LoadL src)));
7800 effect(KILL cr);
7801 ins_cost(MEMORY_REF_COST);
7802 size(Z_DISP3_SIZE);
7803 format %{ "OG $dst, $src\t # long" %}
7804 opcode(OG_ZOPC, OG_ZOPC);
7805 ins_encode(z_form_rt_mem_opt(dst, src));
7806 ins_pipe(pipe_class_dummy);
7807 %}
7808
7809 // Immediate Or long
7810 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
7811 match(Set dst (OrL dst con));
7812 effect(KILL cr);
7813 ins_cost(DEFAULT_COST);
7814 size(4);
7815 format %{ "OILL $dst,$con\t # long" %}
7816 opcode(OILL_ZOPC);
7817 ins_encode(z_riform_unsigned(dst,con));
7818 ins_pipe(pipe_class_dummy);
7819 %}
7820
7821 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
7822 match(Set dst (OrI dst con));
7823 effect(KILL cr);
7824 ins_cost(DEFAULT_COST_HIGH);
7825 // TODO: s390 port size(FIXED_SIZE);
7826 format %{ "OILF $dst,$con\t # long" %}
7827 opcode(OILF_ZOPC);
7828 ins_encode(z_rilform_unsigned(dst,con));
7829 ins_pipe(pipe_class_dummy);
7830 %}
7831
7832 // XOR
7833
7834 // Register Xor
7835 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7836 match(Set dst (XorI dst src));
7837 effect(KILL cr);
7838 size(2);
7839 format %{ "XR $dst,$src" %}
7840 opcode(XR_ZOPC);
7841 ins_encode(z_rrform(dst, src));
7842 ins_pipe(pipe_class_dummy);
7843 %}
7844
7845 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7846 match(Set dst (XorI dst (LoadI src)));
7847 effect(KILL cr);
7848 ins_cost(MEMORY_REF_COST);
7849 // TODO: s390 port size(VARIABLE_SIZE);
7850 format %{ "X(Y) $dst, $src\t # int" %}
7851 opcode(XY_ZOPC, X_ZOPC);
7852 ins_encode(z_form_rt_mem_opt(dst, src));
7853 ins_pipe(pipe_class_dummy);
7854 %}
7855
7856 // Immediate Xor
7857 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7858 match(Set dst (XorI dst src));
7859 effect(KILL cr);
7860 ins_cost(DEFAULT_COST_HIGH);
7861 size(6);
7862 format %{ "XILF $dst,$src" %}
7863 opcode(XILF_ZOPC);
7864 ins_encode(z_rilform_unsigned(dst, src));
7865 ins_pipe(pipe_class_dummy);
7866 %}
7867
7868 // Register Xor Long
7869 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7870 match(Set dst (XorL dst src));
7871 effect(KILL cr);
7872 ins_cost(DEFAULT_COST);
7873 size(4);
7874 format %{ "XGR $dst,$src\t # long" %}
7875 opcode(XGR_ZOPC);
7876 ins_encode(z_rreform(dst, src));
7877 ins_pipe(pipe_class_dummy);
7878 %}
7879
7880 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7881 match(Set dst (XorL dst (LoadL src)));
7882 effect(KILL cr);
7883 ins_cost(MEMORY_REF_COST);
7884 size(Z_DISP3_SIZE);
7885 format %{ "XG $dst, $src\t # long" %}
7886 opcode(XG_ZOPC, XG_ZOPC);
7887 ins_encode(z_form_rt_mem_opt(dst, src));
7888 ins_pipe(pipe_class_dummy);
7889 %}
7890
7891 // Immediate Xor Long
7892 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
7893 match(Set dst (XorL dst con));
7894 effect(KILL cr);
7895 ins_cost(DEFAULT_COST_HIGH);
7896 size(6);
7897 format %{ "XILF $dst,$con\t # long" %}
7898 opcode(XILF_ZOPC);
7899 ins_encode(z_rilform_unsigned(dst,con));
7900 ins_pipe(pipe_class_dummy);
7901 %}
7902
7903 //----------Convert to Boolean-------------------------------------------------
7904
7905 // Convert integer to boolean.
7906 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
7907 match(Set dst (Conv2B src));
7908 effect(KILL cr);
7909 ins_cost(3 * DEFAULT_COST);
7910 size(6);
7911 format %{ "convI2B $dst,$src" %}
7912 ins_encode %{
7913 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
7914 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest)
7915 %}
7916 ins_pipe(pipe_class_dummy);
7917 %}
7918
7919 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
7920 match(Set dst (Conv2B src));
7921 effect(KILL cr);
7922 ins_cost(3 * DEFAULT_COST);
7923 size(10);
7924 format %{ "convP2B $dst,$src" %}
7925 ins_encode %{
7926 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
7927 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
7928 %}
7929 ins_pipe(pipe_class_dummy);
7930 %}
7931
7932 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7933 match(Set dst (CmpLTMask dst src));
7934 effect(KILL cr);
7935 ins_cost(2 * DEFAULT_COST);
7936 size(18);
7937 format %{ "Set $dst CmpLTMask $dst,$src" %}
7938 ins_encode %{
7939 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
7940 __ z_lgfr(Z_R0_scratch, $src$$Register);
7941 __ z_lgfr($dst$$Register, $dst$$Register);
7942 __ z_sgr($dst$$Register, Z_R0_scratch);
7943 __ z_srag($dst$$Register, $dst$$Register, 63);
7944 %}
7945 ins_pipe(pipe_class_dummy);
7946 %}
7947
7948 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
7949 match(Set dst (CmpLTMask dst zero));
7950 effect(KILL cr);
7951 ins_cost(DEFAULT_COST);
7952 size(4);
7953 format %{ "Set $dst CmpLTMask $dst,$zero" %}
7954 ins_encode %{ __ z_sra($dst$$Register, 31); %}
7955 ins_pipe(pipe_class_dummy);
7956 %}
7957
7958
7959 //----------Arithmetic Conversion Instructions---------------------------------
7960 // The conversions operations are all Alpha sorted. Please keep it that way!
7961
7962 instruct convD2F_reg(regF dst, regD src) %{
7963 match(Set dst (ConvD2F src));
7964 // CC remains unchanged.
7965 size(4);
7966 format %{ "LEDBR $dst,$src" %}
7967 opcode(LEDBR_ZOPC);
7968 ins_encode(z_rreform(dst, src));
7969 ins_pipe(pipe_class_dummy);
7970 %}
7971
7972 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
7973 match(Set dst (ConvF2I src));
7974 effect(KILL cr);
7975 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7976 size(16);
7977 format %{ "convF2I $dst,$src" %}
7978 ins_encode %{
7979 Label done;
7980 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
7981 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
7982 __ z_brno(done); // Result is zero if unordered argument.
7983 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
7984 __ bind(done);
7985 %}
7986 ins_pipe(pipe_class_dummy);
7987 %}
7988
7989 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
7990 match(Set dst (ConvD2I src));
7991 effect(KILL cr);
7992 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7993 size(16);
7994 format %{ "convD2I $dst,$src" %}
7995 ins_encode %{
7996 Label done;
7997 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0.
7998 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
7999 __ z_brno(done); // Result is zero if unordered argument.
8000 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8001 __ bind(done);
8002 %}
8003 ins_pipe(pipe_class_dummy);
8004 %}
8005
8006 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
8007 match(Set dst (ConvF2L src));
8008 effect(KILL cr);
8009 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8010 size(16);
8011 format %{ "convF2L $dst,$src" %}
8012 ins_encode %{
8013 Label done;
8014 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8015 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round.
8016 __ z_brno(done); // Result is zero if unordered argument.
8017 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8018 __ bind(done);
8019 %}
8020 ins_pipe(pipe_class_dummy);
8021 %}
8022
8023 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
8024 match(Set dst (ConvD2L src));
8025 effect(KILL cr);
8026 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8027 size(16);
8028 format %{ "convD2L $dst,$src" %}
8029 ins_encode %{
8030 Label done;
8031 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0.
8032 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round.
8033 __ z_brno(done); // Result is zero if unordered argument.
8034 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8035 __ bind(done);
8036 %}
8037 ins_pipe(pipe_class_dummy);
8038 %}
8039
8040 instruct convF2D_reg(regD dst, regF src) %{
8041 match(Set dst (ConvF2D src));
8042 // CC remains unchanged.
8043 size(4);
8044 format %{ "LDEBR $dst,$src" %}
8045 opcode(LDEBR_ZOPC);
8046 ins_encode(z_rreform(dst, src));
8047 ins_pipe(pipe_class_dummy);
8048 %}
8049
8050 instruct convF2D_mem(regD dst, memoryRX src) %{
8051 match(Set dst (ConvF2D src));
8052 // CC remains unchanged.
8053 size(6);
8054 format %{ "LDEB $dst,$src" %}
8055 opcode(LDEB_ZOPC);
8056 ins_encode(z_form_rt_memFP(dst, src));
8057 ins_pipe(pipe_class_dummy);
8058 %}
8059
8060 instruct convI2D_reg(regD dst, iRegI src) %{
8061 match(Set dst (ConvI2D src));
8062 // CC remains unchanged.
8063 ins_cost(DEFAULT_COST);
8064 size(4);
8065 format %{ "CDFBR $dst,$src" %}
8066 opcode(CDFBR_ZOPC);
8067 ins_encode(z_rreform(dst, src));
8068 ins_pipe(pipe_class_dummy);
8069 %}
8070
8071 // Optimization that saves up to two memory operations for each conversion.
8072 instruct convI2F_ireg(regF dst, iRegI src) %{
8073 match(Set dst (ConvI2F src));
8074 // CC remains unchanged.
8075 ins_cost(DEFAULT_COST);
8076 size(4);
8077 format %{ "CEFBR $dst,$src\t # convert int to float" %}
8078 opcode(CEFBR_ZOPC);
8079 ins_encode(z_rreform(dst, src));
8080 ins_pipe(pipe_class_dummy);
8081 %}
8082
8083 instruct convI2L_reg(iRegL dst, iRegI src) %{
8084 match(Set dst (ConvI2L src));
8085 size(4);
8086 format %{ "LGFR $dst,$src\t # int->long" %}
8087 opcode(LGFR_ZOPC);
8088 ins_encode(z_rreform(dst, src));
8089 ins_pipe(pipe_class_dummy);
8090 %}
8091
8092 // Zero-extend convert int to long.
8093 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8094 match(Set dst (AndL (ConvI2L src) mask));
8095 size(4);
8096 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %}
8097 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8098 ins_pipe(pipe_class_dummy);
8099 %}
8100
8101 // Zero-extend convert int to long.
8102 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8103 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8104 // Uses load_const_optmized, so size can vary.
8105 // TODO: s390 port size(VARIABLE_SIZE);
8106 format %{ "LLGF $dst, $src \t # zero-extend int to long" %}
8107 opcode(LLGF_ZOPC, LLGF_ZOPC);
8108 ins_encode(z_form_rt_mem_opt(dst, src));
8109 ins_pipe(pipe_class_dummy);
8110 %}
8111
8112 // Zero-extend long
8113 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8114 match(Set dst (AndL src mask));
8115 size(4);
8116 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %}
8117 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8118 ins_pipe(pipe_class_dummy);
8119 %}
8120
8121 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8122 match(Set dst (RShiftI (LShiftI src amount) amount));
8123 size(4);
8124 format %{ "LHR $dst,$src\t short->int" %}
8125 opcode(LHR_ZOPC);
8126 ins_encode(z_rreform(dst, src));
8127 ins_pipe(pipe_class_dummy);
8128 %}
8129
8130 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8131 match(Set dst (RShiftI (LShiftI src amount) amount));
8132 size(4);
8133 format %{ "LBR $dst,$src\t byte->int" %}
8134 opcode(LBR_ZOPC);
8135 ins_encode(z_rreform(dst, src));
8136 ins_pipe(pipe_class_dummy);
8137 %}
8138
8139 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8140 match(Set dst (MoveF2I src));
8141 ins_cost(MEMORY_REF_COST);
8142 size(4);
8143 format %{ "L $dst,$src\t # MoveF2I" %}
8144 opcode(L_ZOPC);
8145 ins_encode(z_form_rt_mem(dst, src));
8146 ins_pipe(pipe_class_dummy);
8147 %}
8148
8149 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8150 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8151 match(Set dst (MoveI2F src));
8152 ins_cost(MEMORY_REF_COST);
8153 // TODO: s390 port size(FIXED_SIZE);
8154 format %{ "LE $dst,$src\t # MoveI2F" %}
8155 opcode(LE_ZOPC);
8156 ins_encode(z_form_rt_mem(dst, src));
8157 ins_pipe(pipe_class_dummy);
8158 %}
8159
8160 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8161 match(Set dst (MoveD2L src));
8162 ins_cost(MEMORY_REF_COST);
8163 size(6);
8164 format %{ "LG $src,$dst\t # MoveD2L" %}
8165 opcode(LG_ZOPC);
8166 ins_encode(z_form_rt_mem(dst, src));
8167 ins_pipe(pipe_class_dummy);
8168 %}
8169
8170 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8171 match(Set dst (MoveL2D src));
8172 ins_cost(MEMORY_REF_COST);
8173 size(4);
8174 format %{ "LD $dst,$src\t # MoveL2D" %}
8175 opcode(LD_ZOPC);
8176 ins_encode(z_form_rt_mem(dst, src));
8177 ins_pipe(pipe_class_dummy);
8178 %}
8179
8180 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8181 match(Set dst (MoveI2F src));
8182 ins_cost(MEMORY_REF_COST);
8183 size(4);
8184 format %{ "ST $src,$dst\t # MoveI2F" %}
8185 opcode(ST_ZOPC);
8186 ins_encode(z_form_rt_mem(src, dst));
8187 ins_pipe(pipe_class_dummy);
8188 %}
8189
8190 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8191 match(Set dst (MoveD2L src));
8192 effect(DEF dst, USE src);
8193 ins_cost(MEMORY_REF_COST);
8194 size(4);
8195 format %{ "STD $src,$dst\t # MoveD2L" %}
8196 opcode(STD_ZOPC);
8197 ins_encode(z_form_rt_mem(src,dst));
8198 ins_pipe(pipe_class_dummy);
8199 %}
8200
8201 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8202 match(Set dst (MoveL2D src));
8203 ins_cost(MEMORY_REF_COST);
8204 size(6);
8205 format %{ "STG $src,$dst\t # MoveL2D" %}
8206 opcode(STG_ZOPC);
8207 ins_encode(z_form_rt_mem(src,dst));
8208 ins_pipe(pipe_class_dummy);
8209 %}
8210
8211 instruct convL2F_reg(regF dst, iRegL src) %{
8212 match(Set dst (ConvL2F src));
8213 // CC remains unchanged.
8214 ins_cost(DEFAULT_COST);
8215 size(4);
8216 format %{ "CEGBR $dst,$src" %}
8217 opcode(CEGBR_ZOPC);
8218 ins_encode(z_rreform(dst, src));
8219 ins_pipe(pipe_class_dummy);
8220 %}
8221
8222 instruct convL2D_reg(regD dst, iRegL src) %{
8223 match(Set dst (ConvL2D src));
8224 // CC remains unchanged.
8225 ins_cost(DEFAULT_COST);
8226 size(4);
8227 format %{ "CDGBR $dst,$src" %}
8228 opcode(CDGBR_ZOPC);
8229 ins_encode(z_rreform(dst, src));
8230 ins_pipe(pipe_class_dummy);
8231 %}
8232
8233 instruct convL2I_reg(iRegI dst, iRegL src) %{
8234 match(Set dst (ConvL2I src));
8235 // TODO: s390 port size(VARIABLE_SIZE);
8236 format %{ "LR $dst,$src\t # long->int (if needed)" %}
8237 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8238 ins_pipe(pipe_class_dummy);
8239 %}
8240
8241 // Register Shift Right Immediate
8242 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8243 match(Set dst (ConvL2I (RShiftL src cnt)));
8244 effect(KILL cr);
8245 size(6);
8246 format %{ "SRAG $dst,$src,$cnt" %}
8247 opcode(SRAG_ZOPC);
8248 ins_encode(z_rsyform_const(dst, src, cnt));
8249 ins_pipe(pipe_class_dummy);
8250 %}
8251
8252 //----------TRAP based zero checks and range checks----------------------------
8253
8254 // SIGTRAP based implicit range checks in compiled code.
8255 // A range check in the ideal world has one of the following shapes:
8256 // - (If le (CmpU length index)), (IfTrue throw exception)
8257 // - (If lt (CmpU index length)), (IfFalse throw exception)
8258 //
8259 // Match range check 'If le (CmpU length index)'
8260 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8261 match(If cmp (CmpU length index));
8262 effect(USE labl);
8263 predicate(TrapBasedRangeChecks &&
8264 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8265 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8266 Matcher::branches_to_uncommon_trap(_leaf));
8267 ins_cost(1);
8268 // TODO: s390 port size(FIXED_SIZE);
8269
8270 ins_is_TrapBasedCheckNode(true);
8271
8272 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8273 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8274 ins_pipe(pipe_class_trap);
8275 %}
8276
8277 // Match range check 'If lt (CmpU index length)'
8278 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8279 match(If cmp (CmpU index length));
8280 effect(USE labl, KILL cr);
8281 predicate(TrapBasedRangeChecks &&
8282 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8283 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8284 Matcher::branches_to_uncommon_trap(_leaf));
8285 ins_cost(1);
8286 // TODO: s390 port size(FIXED_SIZE);
8287
8288 ins_is_TrapBasedCheckNode(true);
8289
8290 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8291 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8292 ins_pipe(pipe_class_trap);
8293 %}
8294
8295 // Match range check 'If lt (CmpU index length)'
8296 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8297 match(If cmp (CmpU index length));
8298 effect(USE labl);
8299 predicate(TrapBasedRangeChecks &&
8300 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8301 _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8302 Matcher::branches_to_uncommon_trap(_leaf));
8303 ins_cost(1);
8304 // TODO: s390 port size(FIXED_SIZE);
8305
8306 ins_is_TrapBasedCheckNode(true);
8307
8308 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8309 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8310 ins_pipe(pipe_class_trap);
8311 %}
8312
8313 // Implicit zero checks (more implicit null checks).
8314 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8315 match(If cmp (CmpP value zero));
8316 effect(USE labl);
8317 predicate(TrapBasedNullChecks &&
8318 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8319 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8320 Matcher::branches_to_uncommon_trap(_leaf));
8321 size(6);
8322
8323 ins_is_TrapBasedCheckNode(true);
8324
8325 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8326 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8327 ins_pipe(pipe_class_trap);
8328 %}
8329
8330 // Implicit zero checks (more implicit null checks).
8331 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8332 match(If cmp (CmpN value zero));
8333 effect(USE labl);
8334 predicate(TrapBasedNullChecks &&
8335 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8336 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8337 Matcher::branches_to_uncommon_trap(_leaf));
8338 size(6);
8339
8340 ins_is_TrapBasedCheckNode(true);
8341
8342 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8343 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8344 ins_pipe(pipe_class_trap);
8345 %}
8346
8347 //----------Compare instructions-----------------------------------------------
8348
8349 // INT signed
8350
8351 // Compare Integers
8352 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8353 match(Set cr (CmpI op1 op2));
8354 size(2);
8355 format %{ "CR $op1,$op2" %}
8356 opcode(CR_ZOPC);
8357 ins_encode(z_rrform(op1, op2));
8358 ins_pipe(pipe_class_dummy);
8359 %}
8360
8361 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8362 match(Set cr (CmpI op1 op2));
8363 size(6);
8364 format %{ "CFI $op1,$op2" %}
8365 opcode(CFI_ZOPC);
8366 ins_encode(z_rilform_signed(op1, op2));
8367 ins_pipe(pipe_class_dummy);
8368 %}
8369
8370 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8371 match(Set cr (CmpI op1 op2));
8372 size(4);
8373 format %{ "CHI $op1,$op2" %}
8374 opcode(CHI_ZOPC);
8375 ins_encode(z_riform_signed(op1, op2));
8376 ins_pipe(pipe_class_dummy);
8377 %}
8378
8379 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8380 match(Set cr (CmpI op1 zero));
8381 ins_cost(DEFAULT_COST_LOW);
8382 size(2);
8383 format %{ "LTR $op1,$op1" %}
8384 opcode(LTR_ZOPC);
8385 ins_encode(z_rrform(op1, op1));
8386 ins_pipe(pipe_class_dummy);
8387 %}
8388
8389 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8390 match(Set cr (CmpI op1 (LoadI op2)));
8391 ins_cost(MEMORY_REF_COST);
8392 // TODO: s390 port size(VARIABLE_SIZE);
8393 format %{ "C(Y) $op1, $op2\t # int" %}
8394 opcode(CY_ZOPC, C_ZOPC);
8395 ins_encode(z_form_rt_mem_opt(op1, op2));
8396 ins_pipe(pipe_class_dummy);
8397 %}
8398
8399 // INT unsigned
8400
8401 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8402 match(Set cr (CmpU op1 op2));
8403 size(2);
8404 format %{ "CLR $op1,$op2\t # unsigned" %}
8405 opcode(CLR_ZOPC);
8406 ins_encode(z_rrform(op1, op2));
8407 ins_pipe(pipe_class_dummy);
8408 %}
8409
8410 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8411 match(Set cr (CmpU op1 op2));
8412 size(6);
8413 format %{ "CLFI $op1,$op2\t # unsigned" %}
8414 opcode(CLFI_ZOPC);
8415 ins_encode(z_rilform_unsigned(op1, op2));
8416 ins_pipe(pipe_class_dummy);
8417 %}
8418
8419 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8420 match(Set cr (CmpU op1 (LoadI op2)));
8421 ins_cost(MEMORY_REF_COST);
8422 // TODO: s390 port size(VARIABLE_SIZE);
8423 format %{ "CL(Y) $op1, $op2\t # unsigned" %}
8424 opcode(CLY_ZOPC, CL_ZOPC);
8425 ins_encode(z_form_rt_mem_opt(op1, op2));
8426 ins_pipe(pipe_class_dummy);
8427 %}
8428
8429 // LONG signed
8430
8431 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8432 match(Set cr (CmpL op1 op2));
8433 size(4);
8434 format %{ "CGR $op1,$op2\t # long" %}
8435 opcode(CGR_ZOPC);
8436 ins_encode(z_rreform(op1, op2));
8437 ins_pipe(pipe_class_dummy);
8438 %}
8439
8440 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8441 match(Set cr (CmpL op1 (ConvI2L op2)));
8442 size(4);
8443 format %{ "CGFR $op1,$op2\t # long/int" %}
8444 opcode(CGFR_ZOPC);
8445 ins_encode(z_rreform(op1, op2));
8446 ins_pipe(pipe_class_dummy);
8447 %}
8448
8449 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8450 match(Set cr (CmpL op1 con));
8451 size(6);
8452 format %{ "CGFI $op1,$con" %}
8453 opcode(CGFI_ZOPC);
8454 ins_encode(z_rilform_signed(op1, con));
8455 ins_pipe(pipe_class_dummy);
8456 %}
8457
8458 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8459 match(Set cr (CmpL op1 con));
8460 size(4);
8461 format %{ "CGHI $op1,$con" %}
8462 opcode(CGHI_ZOPC);
8463 ins_encode(z_riform_signed(op1, con));
8464 ins_pipe(pipe_class_dummy);
8465 %}
8466
8467 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8468 match(Set cr (CmpL op1 con));
8469 ins_cost(DEFAULT_COST_LOW);
8470 size(4);
8471 format %{ "LTGR $op1,$op1" %}
8472 opcode(LTGR_ZOPC);
8473 ins_encode(z_rreform(op1, op1));
8474 ins_pipe(pipe_class_dummy);
8475 %}
8476
8477 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8478 match(Set cr (CmpL (ConvI2L op1) con));
8479 ins_cost(DEFAULT_COST_LOW);
8480 size(4);
8481 format %{ "LTGFR $op1,$op1" %}
8482 opcode(LTGFR_ZOPC);
8483 ins_encode(z_rreform(op1, op1));
8484 ins_pipe(pipe_class_dummy);
8485 %}
8486
8487 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8488 match(Set cr (CmpL dst (LoadL src)));
8489 ins_cost(MEMORY_REF_COST);
8490 size(Z_DISP3_SIZE);
8491 format %{ "CG $dst, $src\t # long" %}
8492 opcode(CG_ZOPC, CG_ZOPC);
8493 ins_encode(z_form_rt_mem_opt(dst, src));
8494 ins_pipe(pipe_class_dummy);
8495 %}
8496
8497 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8498 match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8499 ins_cost(MEMORY_REF_COST);
8500 size(Z_DISP3_SIZE);
8501 format %{ "CGF $dst, $src\t # long/int" %}
8502 opcode(CGF_ZOPC, CGF_ZOPC);
8503 ins_encode(z_form_rt_mem_opt(dst, src));
8504 ins_pipe(pipe_class_dummy);
8505 %}
8506
8507 // LONG unsigned
8508 // Added CmpUL for LoopPredicate.
8509 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8510 match(Set cr (CmpUL op1 op2));
8511 size(4);
8512 format %{ "CLGR $op1,$op2\t # long" %}
8513 opcode(CLGR_ZOPC);
8514 ins_encode(z_rreform(op1, op2));
8515 ins_pipe(pipe_class_dummy);
8516 %}
8517
8518 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
8519 match(Set cr (CmpUL op1 con));
8520 size(6);
8521 format %{ "CLGFI $op1,$con" %}
8522 opcode(CLGFI_ZOPC);
8523 ins_encode(z_rilform_unsigned(op1, con));
8524 ins_pipe(pipe_class_dummy);
8525 %}
8526
8527 // PTR unsigned
8528
8529 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8530 match(Set cr (CmpP op1 op2));
8531 size(4);
8532 format %{ "CLGR $op1,$op2\t # ptr" %}
8533 opcode(CLGR_ZOPC);
8534 ins_encode(z_rreform(op1, op2));
8535 ins_pipe(pipe_class_dummy);
8536 %}
8537
8538 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8539 match(Set cr (CmpP op1 op2));
8540 ins_cost(DEFAULT_COST_LOW);
8541 size(4);
8542 format %{ "LTGR $op1, $op1\t # ptr" %}
8543 opcode(LTGR_ZOPC);
8544 ins_encode(z_rreform(op1, op1));
8545 ins_pipe(pipe_class_dummy);
8546 %}
8547
8548 // Don't use LTGFR which performs sign extend.
8549 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8550 match(Set cr (CmpP (DecodeN op1) op2));
8551 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
8552 ins_cost(DEFAULT_COST_LOW);
8553 size(2);
8554 format %{ "LTR $op1, $op1\t # ptr" %}
8555 opcode(LTR_ZOPC);
8556 ins_encode(z_rrform(op1, op1));
8557 ins_pipe(pipe_class_dummy);
8558 %}
8559
8560 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8561 match(Set cr (CmpP dst (LoadP src)));
8562 ins_cost(MEMORY_REF_COST);
8563 size(Z_DISP3_SIZE);
8564 format %{ "CLG $dst, $src\t # ptr" %}
8565 opcode(CLG_ZOPC, CLG_ZOPC);
8566 ins_encode(z_form_rt_mem_opt(dst, src));
8567 ins_pipe(pipe_class_dummy);
8568 %}
8569
8570 //----------Max and Min--------------------------------------------------------
8571
8572 // Max Register with Register
8573 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8574 match(Set dst (MinI src1 src2));
8575 effect(KILL cr);
8576 predicate(VM_Version::has_LoadStoreConditional());
8577 ins_cost(3 * DEFAULT_COST);
8578 // TODO: s390 port size(VARIABLE_SIZE);
8579 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8580 ins_encode %{
8581 Register Rdst = $dst$$Register;
8582 Register Rsrc1 = $src1$$Register;
8583 Register Rsrc2 = $src2$$Register;
8584
8585 if (Rsrc1 == Rsrc2) {
8586 if (Rdst != Rsrc1) {
8587 __ z_lgfr(Rdst, Rsrc1);
8588 }
8589 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8590 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow.
8591 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8592 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8593 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow.
8594 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8595 } else {
8596 // Rdst is disjoint from operands, move in either case.
8597 __ z_cr(Rsrc1, Rsrc2);
8598 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8599 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8600 }
8601 %}
8602 ins_pipe(pipe_class_dummy);
8603 %}
8604
8605 // Min Register with Register.
8606 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8607 match(Set dst (MinI src1 src2));
8608 effect(KILL cr);
8609 predicate(VM_Version::has_CompareBranch());
8610 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8611 // TODO: s390 port size(VARIABLE_SIZE);
8612 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8613 ins_encode %{
8614 Register Rdst = $dst$$Register;
8615 Register Rsrc1 = $src1$$Register;
8616 Register Rsrc2 = $src2$$Register;
8617 Label done;
8618
8619 if (Rsrc1 == Rsrc2) {
8620 if (Rdst != Rsrc1) {
8621 __ z_lgfr(Rdst, Rsrc1);
8622 }
8623 } else if (Rdst == Rsrc1) {
8624 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8625 __ z_lgfr(Rdst, Rsrc2);
8626 } else if (Rdst == Rsrc2) {
8627 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8628 __ z_lgfr(Rdst, Rsrc1);
8629 } else {
8630 __ z_lgfr(Rdst, Rsrc1);
8631 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8632 __ z_lgfr(Rdst, Rsrc2);
8633 }
8634 __ bind(done);
8635 %}
8636 ins_pipe(pipe_class_dummy);
8637 %}
8638
8639 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8640 match(Set dst (MinI src1 src2));
8641 effect(KILL cr);
8642 predicate(!VM_Version::has_CompareBranch());
8643 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8644 // TODO: s390 port size(VARIABLE_SIZE);
8645 format %{ "MinI $dst $src1,$src2\t MinI" %}
8646 ins_encode %{
8647 Register Rdst = $dst$$Register;
8648 Register Rsrc1 = $src1$$Register;
8649 Register Rsrc2 = $src2$$Register;
8650 Label done;
8651
8652 if (Rsrc1 == Rsrc2) {
8653 if (Rdst != Rsrc1) {
8654 __ z_lgfr(Rdst, Rsrc1);
8655 }
8656 } else if (Rdst == Rsrc1) {
8657 __ z_cr(Rsrc1, Rsrc2);
8658 __ z_brl(done);
8659 __ z_lgfr(Rdst, Rsrc2);
8660 } else if (Rdst == Rsrc2) {
8661 __ z_cr(Rsrc2, Rsrc1);
8662 __ z_brl(done);
8663 __ z_lgfr(Rdst, Rsrc1);
8664 } else {
8665 __ z_lgfr(Rdst, Rsrc1);
8666 __ z_cr(Rsrc1, Rsrc2);
8667 __ z_brl(done);
8668 __ z_lgfr(Rdst, Rsrc2);
8669 }
8670 __ bind(done);
8671 %}
8672 ins_pipe(pipe_class_dummy);
8673 %}
8674
8675 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8676 match(Set dst (MinI src1 src2));
8677 effect(KILL cr);
8678 predicate(VM_Version::has_LoadStoreConditional());
8679 ins_cost(3 * DEFAULT_COST);
8680 // TODO: s390 port size(VARIABLE_SIZE);
8681 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8682 ins_encode %{
8683 Register Rdst = $dst$$Register;
8684 Register Rsrc1 = $src1$$Register;
8685 int Isrc2 = $src2$$constant;
8686
8687 if (Rdst == Rsrc1) {
8688 __ load_const_optimized(Z_R0_scratch, Isrc2);
8689 __ z_cfi(Rsrc1, Isrc2);
8690 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8691 } else {
8692 __ load_const_optimized(Rdst, Isrc2);
8693 __ z_cfi(Rsrc1, Isrc2);
8694 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8695 }
8696 %}
8697 ins_pipe(pipe_class_dummy);
8698 %}
8699
8700 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8701 match(Set dst (MinI src1 src2));
8702 effect(KILL cr);
8703 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8704 // TODO: s390 port size(VARIABLE_SIZE);
8705 format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8706 ins_encode %{
8707 Label done;
8708 if ($dst$$Register != $src1$$Register) {
8709 __ z_lgfr($dst$$Register, $src1$$Register);
8710 }
8711 __ z_cfi($src1$$Register, $src2$$constant);
8712 __ z_brl(done);
8713 __ z_lgfi($dst$$Register, $src2$$constant);
8714 __ bind(done);
8715 %}
8716 ins_pipe(pipe_class_dummy);
8717 %}
8718
8719 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8720 match(Set dst (MinI src1 src2));
8721 effect(KILL cr);
8722 predicate(VM_Version::has_LoadStoreConditional());
8723 ins_cost(3 * DEFAULT_COST);
8724 // TODO: s390 port size(VARIABLE_SIZE);
8725 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8726 ins_encode %{
8727 Register Rdst = $dst$$Register;
8728 Register Rsrc1 = $src1$$Register;
8729 int Isrc2 = $src2$$constant;
8730
8731 if (Rdst == Rsrc1) {
8732 __ load_const_optimized(Z_R0_scratch, Isrc2);
8733 __ z_chi(Rsrc1, Isrc2);
8734 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8735 } else {
8736 __ load_const_optimized(Rdst, Isrc2);
8737 __ z_chi(Rsrc1, Isrc2);
8738 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8739 }
8740 %}
8741 ins_pipe(pipe_class_dummy);
8742 %}
8743
8744 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8745 match(Set dst (MinI src1 src2));
8746 effect(KILL cr);
8747 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8748 // TODO: s390 port size(VARIABLE_SIZE);
8749 format %{ "MinI $dst $src1,$src2\t MinI const16" %}
8750 ins_encode %{
8751 Label done;
8752 if ($dst$$Register != $src1$$Register) {
8753 __ z_lgfr($dst$$Register, $src1$$Register);
8754 }
8755 __ z_chi($src1$$Register, $src2$$constant);
8756 __ z_brl(done);
8757 __ z_lghi($dst$$Register, $src2$$constant);
8758 __ bind(done);
8759 %}
8760 ins_pipe(pipe_class_dummy);
8761 %}
8762
8763 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8764 match(Set dst (MinI src1 src2));
8765 effect(KILL cr);
8766 predicate(VM_Version::has_CompareBranch());
8767 ins_cost(DEFAULT_COST + BRANCH_COST);
8768 // TODO: s390 port size(VARIABLE_SIZE);
8769 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
8770 ins_encode %{
8771 Label done;
8772 if ($dst$$Register != $src1$$Register) {
8773 __ z_lgfr($dst$$Register, $src1$$Register);
8774 }
8775 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
8776 __ z_lghi($dst$$Register, $src2$$constant);
8777 __ bind(done);
8778 %}
8779 ins_pipe(pipe_class_dummy);
8780 %}
8781
8782 // Max Register with Register
8783 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8784 match(Set dst (MaxI src1 src2));
8785 effect(KILL cr);
8786 predicate(VM_Version::has_LoadStoreConditional());
8787 ins_cost(3 * DEFAULT_COST);
8788 // TODO: s390 port size(VARIABLE_SIZE);
8789 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
8790 ins_encode %{
8791 Register Rdst = $dst$$Register;
8792 Register Rsrc1 = $src1$$Register;
8793 Register Rsrc2 = $src2$$Register;
8794
8795 if (Rsrc1 == Rsrc2) {
8796 if (Rdst != Rsrc1) {
8797 __ z_lgfr(Rdst, Rsrc1);
8798 }
8799 } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8800 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh.
8801 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8802 } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8803 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh.
8804 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
8805 } else { // Rdst is disjoint from operands, move in either case.
8806 __ z_cr(Rsrc1, Rsrc2);
8807 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8808 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8809 }
8810 %}
8811 ins_pipe(pipe_class_dummy);
8812 %}
8813
8814 // Max Register with Register
8815 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8816 match(Set dst (MaxI src1 src2));
8817 effect(KILL cr);
8818 predicate(VM_Version::has_CompareBranch());
8819 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8820 // TODO: s390 port size(VARIABLE_SIZE);
8821 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
8822 ins_encode %{
8823 Register Rdst = $dst$$Register;
8824 Register Rsrc1 = $src1$$Register;
8825 Register Rsrc2 = $src2$$Register;
8826 Label done;
8827
8828 if (Rsrc1 == Rsrc2) {
8829 if (Rdst != Rsrc1) {
8830 __ z_lgfr(Rdst, Rsrc1);
8831 }
8832 } else if (Rdst == Rsrc1) {
8833 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8834 __ z_lgfr(Rdst, Rsrc2);
8835 } else if (Rdst == Rsrc2) {
8836 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
8837 __ z_lgfr(Rdst, Rsrc1);
8838 } else {
8839 __ z_lgfr(Rdst, Rsrc1);
8840 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8841 __ z_lgfr(Rdst, Rsrc2);
8842 }
8843 __ bind(done);
8844 %}
8845 ins_pipe(pipe_class_dummy);
8846 %}
8847
8848 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8849 match(Set dst (MaxI src1 src2));
8850 effect(KILL cr);
8851 predicate(!VM_Version::has_CompareBranch());
8852 ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8853 // TODO: s390 port size(VARIABLE_SIZE);
8854 format %{ "MaxI $dst $src1,$src2\t MaxI" %}
8855 ins_encode %{
8856 Register Rdst = $dst$$Register;
8857 Register Rsrc1 = $src1$$Register;
8858 Register Rsrc2 = $src2$$Register;
8859 Label done;
8860
8861 if (Rsrc1 == Rsrc2) {
8862 if (Rdst != Rsrc1) {
8863 __ z_lgfr(Rdst, Rsrc1);
8864 }
8865 } else if (Rdst == Rsrc1) {
8866 __ z_cr(Rsrc1, Rsrc2);
8867 __ z_brh(done);
8868 __ z_lgfr(Rdst, Rsrc2);
8869 } else if (Rdst == Rsrc2) {
8870 __ z_cr(Rsrc2, Rsrc1);
8871 __ z_brh(done);
8872 __ z_lgfr(Rdst, Rsrc1);
8873 } else {
8874 __ z_lgfr(Rdst, Rsrc1);
8875 __ z_cr(Rsrc1, Rsrc2);
8876 __ z_brh(done);
8877 __ z_lgfr(Rdst, Rsrc2);
8878 }
8879
8880 __ bind(done);
8881 %}
8882
8883 ins_pipe(pipe_class_dummy);
8884 %}
8885
8886 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8887 match(Set dst (MaxI src1 src2));
8888 effect(KILL cr);
8889 predicate(VM_Version::has_LoadStoreConditional());
8890 ins_cost(3 * DEFAULT_COST);
8891 // TODO: s390 port size(VARIABLE_SIZE);
8892 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
8893 ins_encode %{
8894 Register Rdst = $dst$$Register;
8895 Register Rsrc1 = $src1$$Register;
8896 int Isrc2 = $src2$$constant;
8897
8898 if (Rdst == Rsrc1) {
8899 __ load_const_optimized(Z_R0_scratch, Isrc2);
8900 __ z_cfi(Rsrc1, Isrc2);
8901 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8902 } else {
8903 __ load_const_optimized(Rdst, Isrc2);
8904 __ z_cfi(Rsrc1, Isrc2);
8905 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8906 }
8907 %}
8908 ins_pipe(pipe_class_dummy);
8909 %}
8910
8911 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8912 match(Set dst (MaxI src1 src2));
8913 effect(KILL cr);
8914 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8915 // TODO: s390 port size(VARIABLE_SIZE);
8916 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
8917 ins_encode %{
8918 Label done;
8919 if ($dst$$Register != $src1$$Register) {
8920 __ z_lgfr($dst$$Register, $src1$$Register);
8921 }
8922 __ z_cfi($src1$$Register, $src2$$constant);
8923 __ z_brh(done);
8924 __ z_lgfi($dst$$Register, $src2$$constant);
8925 __ bind(done);
8926 %}
8927 ins_pipe(pipe_class_dummy);
8928 %}
8929
8930 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8931 match(Set dst (MaxI src1 src2));
8932 effect(KILL cr);
8933 predicate(VM_Version::has_LoadStoreConditional());
8934 ins_cost(3 * DEFAULT_COST);
8935 // TODO: s390 port size(VARIABLE_SIZE);
8936 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
8937 ins_encode %{
8938 Register Rdst = $dst$$Register;
8939 Register Rsrc1 = $src1$$Register;
8940 int Isrc2 = $src2$$constant;
8941 if (Rdst == Rsrc1) {
8942 __ load_const_optimized(Z_R0_scratch, Isrc2);
8943 __ z_chi(Rsrc1, Isrc2);
8944 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8945 } else {
8946 __ load_const_optimized(Rdst, Isrc2);
8947 __ z_chi(Rsrc1, Isrc2);
8948 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8949 }
8950 %}
8951 ins_pipe(pipe_class_dummy);
8952 %}
8953
8954 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8955 match(Set dst (MaxI src1 src2));
8956 effect(KILL cr);
8957 ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8958 // TODO: s390 port size(VARIABLE_SIZE);
8959 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
8960 ins_encode %{
8961 Label done;
8962 if ($dst$$Register != $src1$$Register) {
8963 __ z_lgfr($dst$$Register, $src1$$Register);
8964 }
8965 __ z_chi($src1$$Register, $src2$$constant);
8966 __ z_brh(done);
8967 __ z_lghi($dst$$Register, $src2$$constant);
8968 __ bind(done);
8969 %}
8970 ins_pipe(pipe_class_dummy);
8971 %}
8972
8973 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8974 match(Set dst (MaxI src1 src2));
8975 effect(KILL cr);
8976 predicate(VM_Version::has_CompareBranch());
8977 ins_cost(DEFAULT_COST + BRANCH_COST);
8978 // TODO: s390 port size(VARIABLE_SIZE);
8979 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
8980 ins_encode %{
8981 Label done;
8982 if ($dst$$Register != $src1$$Register) {
8983 __ z_lgfr($dst$$Register, $src1$$Register);
8984 }
8985 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
8986 __ z_lghi($dst$$Register, $src2$$constant);
8987 __ bind(done);
8988 %}
8989 ins_pipe(pipe_class_dummy);
8990 %}
8991
8992 //----------Abs---------------------------------------------------------------
8993
8994 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
8995 match(Set dst (AbsI src));
8996 effect(KILL cr);
8997 ins_cost(DEFAULT_COST_LOW);
8998 // TODO: s390 port size(FIXED_SIZE);
8999 format %{ "LPR $dst, $src" %}
9000 opcode(LPR_ZOPC);
9001 ins_encode(z_rrform(dst, src));
9002 ins_pipe(pipe_class_dummy);
9003 %}
9004
9005 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
9006 match(Set dst (SubI zero (AbsI src)));
9007 effect(KILL cr);
9008 ins_cost(DEFAULT_COST_LOW);
9009 // TODO: s390 port size(FIXED_SIZE);
9010 format %{ "LNR $dst, $src" %}
9011 opcode(LNR_ZOPC);
9012 ins_encode(z_rrform(dst, src));
9013 ins_pipe(pipe_class_dummy);
9014 %}
9015
9016 //----------Float Compares----------------------------------------------------
9017
9018 // Compare floating, generate condition code.
9019 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
9020 match(Set cr (CmpF src1 src2));
9021 ins_cost(ALU_REG_COST);
9022 size(4);
9023 format %{ "FCMPcc $src1,$src2\t # float" %}
9024 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
9025 ins_pipe(pipe_class_dummy);
9026 %}
9027
9028 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
9029 match(Set cr (CmpD src1 src2));
9030 ins_cost(ALU_REG_COST);
9031 size(4);
9032 format %{ "FCMPcc $src1,$src2 \t # double" %}
9033 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
9034 ins_pipe(pipe_class_dummy);
9035 %}
9036
9037 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
9038 match(Set cr (CmpF src1 (LoadF src2)));
9039 ins_cost(ALU_MEMORY_COST);
9040 size(6);
9041 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
9042 opcode(CEB_ZOPC);
9043 ins_encode(z_form_rt_memFP(src1, src2));
9044 ins_pipe(pipe_class_dummy);
9045 %}
9046
9047 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9048 match(Set cr (CmpD src1 (LoadD src2)));
9049 ins_cost(ALU_MEMORY_COST);
9050 size(6);
9051 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9052 opcode(CDB_ZOPC);
9053 ins_encode(z_form_rt_memFP(src1, src2));
9054 ins_pipe(pipe_class_dummy);
9055 %}
9056
9057 // Compare floating, generate condition code
9058 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9059 match(Set cr (CmpF src1 src2));
9060 ins_cost(DEFAULT_COST);
9061 size(4);
9062 format %{ "LTEBR $src1,$src1\t # float" %}
9063 opcode(LTEBR_ZOPC);
9064 ins_encode(z_rreform(src1, src1));
9065 ins_pipe(pipe_class_dummy);
9066 %}
9067
9068 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9069 match(Set cr (CmpD src1 src2));
9070 ins_cost(DEFAULT_COST);
9071 size(4);
9072 format %{ "LTDBR $src1,$src1 \t # double" %}
9073 opcode(LTDBR_ZOPC);
9074 ins_encode(z_rreform(src1, src1));
9075 ins_pipe(pipe_class_dummy);
9076 %}
9077
9078 // Compare floating, generate -1,0,1
9079 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9080 match(Set dst (CmpF3 src1 src2));
9081 effect(KILL cr);
9082 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9083 size(24);
9084 format %{ "CmpF3 $dst,$src1,$src2" %}
9085 ins_encode %{
9086 // compare registers
9087 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9088 // Convert condition code into -1,0,1, where
9089 // -1 means unordered or less
9090 // 0 means equal
9091 // 1 means greater.
9092 if (VM_Version::has_LoadStoreConditional()) {
9093 Register one = Z_R0_scratch;
9094 Register minus_one = Z_R1_scratch;
9095 __ z_lghi(minus_one, -1);
9096 __ z_lghi(one, 1);
9097 __ z_lghi( $dst$$Register, 0);
9098 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9099 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9100 } else {
9101 Label done;
9102 __ clear_reg($dst$$Register, true, false);
9103 __ z_bre(done);
9104 __ z_lhi($dst$$Register, 1);
9105 __ z_brh(done);
9106 __ z_lhi($dst$$Register, -1);
9107 __ bind(done);
9108 }
9109 %}
9110 ins_pipe(pipe_class_dummy);
9111 %}
9112
9113 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9114 match(Set dst (CmpD3 src1 src2));
9115 effect(KILL cr);
9116 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9117 size(24);
9118 format %{ "CmpD3 $dst,$src1,$src2" %}
9119 ins_encode %{
9120 // compare registers
9121 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9122 // Convert condition code into -1,0,1, where
9123 // -1 means unordered or less
9124 // 0 means equal
9125 // 1 means greater.
9126 if (VM_Version::has_LoadStoreConditional()) {
9127 Register one = Z_R0_scratch;
9128 Register minus_one = Z_R1_scratch;
9129 __ z_lghi(minus_one, -1);
9130 __ z_lghi(one, 1);
9131 __ z_lghi( $dst$$Register, 0);
9132 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9133 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9134 } else {
9135 Label done;
9136 // indicate unused result
9137 (void) __ clear_reg($dst$$Register, true, false);
9138 __ z_bre(done);
9139 __ z_lhi($dst$$Register, 1);
9140 __ z_brh(done);
9141 __ z_lhi($dst$$Register, -1);
9142 __ bind(done);
9143 }
9144 %}
9145 ins_pipe(pipe_class_dummy);
9146 %}
9147
9148 //----------Branches---------------------------------------------------------
9149 // Jump
9150
9151 // Direct Branch.
9152 instruct branch(label labl) %{
9153 match(Goto);
9154 effect(USE labl);
9155 ins_cost(BRANCH_COST);
9156 size(4);
9157 format %{ "BRU $labl" %}
9158 ins_encode(z_enc_bru(labl));
9159 ins_pipe(pipe_class_dummy);
9160 // If set to 1 this indicates that the current instruction is a
9161 // short variant of a long branch. This avoids using this
9162 // instruction in first-pass matching. It will then only be used in
9163 // the `Shorten_branches' pass.
9164 ins_short_branch(1);
9165 %}
9166
9167 // Direct Branch.
9168 instruct branchFar(label labl) %{
9169 match(Goto);
9170 effect(USE labl);
9171 ins_cost(BRANCH_COST);
9172 size(6);
9173 format %{ "BRUL $labl" %}
9174 ins_encode(z_enc_brul(labl));
9175 ins_pipe(pipe_class_dummy);
9176 // This is not a short variant of a branch, but the long variant.
9177 ins_short_branch(0);
9178 %}
9179
9180 // Conditional Near Branch
9181 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9182 // Same match rule as `branchConFar'.
9183 match(If cmp cr);
9184 effect(USE lbl);
9185 ins_cost(BRANCH_COST);
9186 size(4);
9187 format %{ "branch_con_short,$cmp $cr, $lbl" %}
9188 ins_encode(z_enc_branch_con_short(cmp, lbl));
9189 ins_pipe(pipe_class_dummy);
9190 // If set to 1 this indicates that the current instruction is a
9191 // short variant of a long branch. This avoids using this
9192 // instruction in first-pass matching. It will then only be used in
9193 // the `Shorten_branches' pass.
9194 ins_short_branch(1);
9195 %}
9196
9197 // This is for cases when the z/Architecture conditional branch instruction
9198 // does not reach far enough. So we emit a far branch here, which is
9199 // more expensive.
9200 //
9201 // Conditional Far Branch
9202 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9203 // Same match rule as `branchCon'.
9204 match(If cmp cr);
9205 effect(USE cr, USE lbl);
9206 // Make more expensive to prefer compare_and_branch over separate instructions.
9207 ins_cost(2 * BRANCH_COST);
9208 size(6);
9209 format %{ "branch_con_far,$cmp $cr, $lbl" %}
9210 ins_encode(z_enc_branch_con_far(cmp, lbl));
9211 ins_pipe(pipe_class_dummy);
9212 // This is not a short variant of a branch, but the long variant..
9213 ins_short_branch(0);
9214 %}
9215
9216 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9217 match(CountedLoopEnd cmp cr);
9218 effect(USE labl);
9219 ins_cost(BRANCH_COST);
9220 size(4);
9221 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %}
9222 ins_encode(z_enc_branch_con_short(cmp, labl));
9223 ins_pipe(pipe_class_dummy);
9224 // If set to 1 this indicates that the current instruction is a
9225 // short variant of a long branch. This avoids using this
9226 // instruction in first-pass matching. It will then only be used in
9227 // the `Shorten_branches' pass.
9228 ins_short_branch(1);
9229 %}
9230
9231 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9232 match(CountedLoopEnd cmp cr);
9233 effect(USE labl);
9234 ins_cost(BRANCH_COST);
9235 size(6);
9236 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %}
9237 ins_encode(z_enc_branch_con_far(cmp, labl));
9238 ins_pipe(pipe_class_dummy);
9239 // This is not a short variant of a branch, but the long variant.
9240 ins_short_branch(0);
9241 %}
9242
9243 //----------Compare and Branch (short distance)------------------------------
9244
9245 // INT REG operands for loop counter processing.
9246 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9247 match(CountedLoopEnd boolnode (CmpI src1 src2));
9248 effect(USE labl, KILL cr);
9249 predicate(VM_Version::has_CompareBranch());
9250 ins_cost(BRANCH_COST);
9251 // TODO: s390 port size(FIXED_SIZE);
9252 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9253 opcode(CRJ_ZOPC);
9254 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9255 ins_pipe(pipe_class_dummy);
9256 ins_short_branch(1);
9257 %}
9258
9259 // INT REG operands.
9260 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9261 match(If boolnode (CmpI src1 src2));
9262 effect(USE labl, KILL cr);
9263 predicate(VM_Version::has_CompareBranch());
9264 ins_cost(BRANCH_COST);
9265 // TODO: s390 port size(FIXED_SIZE);
9266 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9267 opcode(CRJ_ZOPC);
9268 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9269 ins_pipe(pipe_class_dummy);
9270 ins_short_branch(1);
9271 %}
9272
9273 // Unsigned INT REG operands
9274 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9275 match(If boolnode (CmpU src1 src2));
9276 effect(USE labl, KILL cr);
9277 predicate(VM_Version::has_CompareBranch());
9278 ins_cost(BRANCH_COST);
9279 // TODO: s390 port size(FIXED_SIZE);
9280 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9281 opcode(CLRJ_ZOPC);
9282 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9283 ins_pipe(pipe_class_dummy);
9284 ins_short_branch(1);
9285 %}
9286
9287 // LONG REG operands
9288 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9289 match(If boolnode (CmpL src1 src2));
9290 effect(USE labl, KILL cr);
9291 predicate(VM_Version::has_CompareBranch());
9292 ins_cost(BRANCH_COST);
9293 // TODO: s390 port size(FIXED_SIZE);
9294 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9295 opcode(CGRJ_ZOPC);
9296 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9297 ins_pipe(pipe_class_dummy);
9298 ins_short_branch(1);
9299 %}
9300
9301 // PTR REG operands
9302
9303 // Separate rules for regular and narrow oops. ADLC can't recognize
9304 // rules with polymorphic operands to be sisters -> shorten_branches
9305 // will not shorten.
9306
9307 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9308 match(If boolnode (CmpP src1 src2));
9309 effect(USE labl, KILL cr);
9310 predicate(VM_Version::has_CompareBranch());
9311 ins_cost(BRANCH_COST);
9312 // TODO: s390 port size(FIXED_SIZE);
9313 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9314 opcode(CLGRJ_ZOPC);
9315 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9316 ins_pipe(pipe_class_dummy);
9317 ins_short_branch(1);
9318 %}
9319
9320 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9321 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9322 effect(USE labl, KILL cr);
9323 predicate(VM_Version::has_CompareBranch());
9324 ins_cost(BRANCH_COST);
9325 // TODO: s390 port size(FIXED_SIZE);
9326 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9327 opcode(CLGRJ_ZOPC);
9328 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9329 ins_pipe(pipe_class_dummy);
9330 ins_short_branch(1);
9331 %}
9332
9333 // INT REG/IMM operands for loop counter processing
9334 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9335 match(CountedLoopEnd boolnode (CmpI src1 src2));
9336 effect(USE labl, KILL cr);
9337 predicate(VM_Version::has_CompareBranch());
9338 ins_cost(BRANCH_COST);
9339 // TODO: s390 port size(FIXED_SIZE);
9340 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %}
9341 opcode(CIJ_ZOPC);
9342 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9343 ins_pipe(pipe_class_dummy);
9344 ins_short_branch(1);
9345 %}
9346
9347 // INT REG/IMM operands
9348 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9349 match(If boolnode (CmpI src1 src2));
9350 effect(USE labl, KILL cr);
9351 predicate(VM_Version::has_CompareBranch());
9352 ins_cost(BRANCH_COST);
9353 // TODO: s390 port size(FIXED_SIZE);
9354 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9355 opcode(CIJ_ZOPC);
9356 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9357 ins_pipe(pipe_class_dummy);
9358 ins_short_branch(1);
9359 %}
9360
9361 // INT REG/IMM operands
9362 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9363 match(If boolnode (CmpU src1 src2));
9364 effect(USE labl, KILL cr);
9365 predicate(VM_Version::has_CompareBranch());
9366 ins_cost(BRANCH_COST);
9367 // TODO: s390 port size(FIXED_SIZE);
9368 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9369 opcode(CLIJ_ZOPC);
9370 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9371 ins_pipe(pipe_class_dummy);
9372 ins_short_branch(1);
9373 %}
9374
9375 // LONG REG/IMM operands
9376 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9377 match(If boolnode (CmpL src1 src2));
9378 effect(USE labl, KILL cr);
9379 predicate(VM_Version::has_CompareBranch());
9380 ins_cost(BRANCH_COST);
9381 // TODO: s390 port size(FIXED_SIZE);
9382 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9383 opcode(CGIJ_ZOPC);
9384 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9385 ins_pipe(pipe_class_dummy);
9386 ins_short_branch(1);
9387 %}
9388
9389 // PTR REG-imm operands
9390
9391 // Separate rules for regular and narrow oops. ADLC can't recognize
9392 // rules with polymorphic operands to be sisters -> shorten_branches
9393 // will not shorten.
9394
9395 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9396 match(If boolnode (CmpP src1 src2));
9397 effect(USE labl, KILL cr);
9398 predicate(VM_Version::has_CompareBranch());
9399 ins_cost(BRANCH_COST);
9400 // TODO: s390 port size(FIXED_SIZE);
9401 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9402 opcode(CLGIJ_ZOPC);
9403 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9404 ins_pipe(pipe_class_dummy);
9405 ins_short_branch(1);
9406 %}
9407
9408 // Compare against zero only, do not mix N and P oops (encode/decode required).
9409 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9410 match(If boolnode (CmpP (DecodeN src1) src2));
9411 effect(USE labl, KILL cr);
9412 predicate(VM_Version::has_CompareBranch());
9413 ins_cost(BRANCH_COST);
9414 // TODO: s390 port size(FIXED_SIZE);
9415 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9416 opcode(CLGIJ_ZOPC);
9417 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9418 ins_pipe(pipe_class_dummy);
9419 ins_short_branch(1);
9420 %}
9421
9422 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9423 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9424 effect(USE labl, KILL cr);
9425 predicate(VM_Version::has_CompareBranch());
9426 ins_cost(BRANCH_COST);
9427 // TODO: s390 port size(FIXED_SIZE);
9428 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9429 opcode(CLGIJ_ZOPC);
9430 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9431 ins_pipe(pipe_class_dummy);
9432 ins_short_branch(1);
9433 %}
9434
9435
9436 //----------Compare and Branch (far distance)------------------------------
9437
9438 // INT REG operands for loop counter processing
9439 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9440 match(CountedLoopEnd boolnode (CmpI src1 src2));
9441 effect(USE labl, KILL cr);
9442 predicate(VM_Version::has_CompareBranch());
9443 ins_cost(BRANCH_COST+DEFAULT_COST);
9444 // TODO: s390 port size(FIXED_SIZE);
9445 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9446 opcode(CR_ZOPC, BRCL_ZOPC);
9447 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9448 ins_pipe(pipe_class_dummy);
9449 ins_short_branch(0);
9450 %}
9451
9452 // INT REG operands
9453 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9454 match(If boolnode (CmpI src1 src2));
9455 effect(USE labl, KILL cr);
9456 predicate(VM_Version::has_CompareBranch());
9457 ins_cost(BRANCH_COST+DEFAULT_COST);
9458 // TODO: s390 port size(FIXED_SIZE);
9459 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9460 opcode(CR_ZOPC, BRCL_ZOPC);
9461 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9462 ins_pipe(pipe_class_dummy);
9463 ins_short_branch(0);
9464 %}
9465
9466 // INT REG operands
9467 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9468 match(If boolnode (CmpU src1 src2));
9469 effect(USE labl, KILL cr);
9470 predicate(VM_Version::has_CompareBranch());
9471 ins_cost(BRANCH_COST+DEFAULT_COST);
9472 // TODO: s390 port size(FIXED_SIZE);
9473 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9474 opcode(CLR_ZOPC, BRCL_ZOPC);
9475 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9476 ins_pipe(pipe_class_dummy);
9477 ins_short_branch(0);
9478 %}
9479
9480 // LONG REG operands
9481 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9482 match(If boolnode (CmpL src1 src2));
9483 effect(USE labl, KILL cr);
9484 predicate(VM_Version::has_CompareBranch());
9485 ins_cost(BRANCH_COST+DEFAULT_COST);
9486 // TODO: s390 port size(FIXED_SIZE);
9487 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9488 opcode(CGR_ZOPC, BRCL_ZOPC);
9489 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9490 ins_pipe(pipe_class_dummy);
9491 ins_short_branch(0);
9492 %}
9493
9494 // PTR REG operands
9495
9496 // Separate rules for regular and narrow oops. ADLC can't recognize
9497 // rules with polymorphic operands to be sisters -> shorten_branches
9498 // will not shorten.
9499
9500 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9501 match(If boolnode (CmpP src1 src2));
9502 effect(USE labl, KILL cr);
9503 predicate(VM_Version::has_CompareBranch());
9504 ins_cost(BRANCH_COST+DEFAULT_COST);
9505 // TODO: s390 port size(FIXED_SIZE);
9506 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9507 opcode(CLGR_ZOPC, BRCL_ZOPC);
9508 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9509 ins_pipe(pipe_class_dummy);
9510 ins_short_branch(0);
9511 %}
9512
9513 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9514 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9515 effect(USE labl, KILL cr);
9516 predicate(VM_Version::has_CompareBranch());
9517 ins_cost(BRANCH_COST+DEFAULT_COST);
9518 // TODO: s390 port size(FIXED_SIZE);
9519 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9520 opcode(CLGR_ZOPC, BRCL_ZOPC);
9521 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9522 ins_pipe(pipe_class_dummy);
9523 ins_short_branch(0);
9524 %}
9525
9526 // INT REG/IMM operands for loop counter processing
9527 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9528 match(CountedLoopEnd boolnode (CmpI src1 src2));
9529 effect(USE labl, KILL cr);
9530 predicate(VM_Version::has_CompareBranch());
9531 ins_cost(BRANCH_COST+DEFAULT_COST);
9532 // TODO: s390 port size(FIXED_SIZE);
9533 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %}
9534 opcode(CHI_ZOPC, BRCL_ZOPC);
9535 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9536 ins_pipe(pipe_class_dummy);
9537 ins_short_branch(0);
9538 %}
9539
9540 // INT REG/IMM operands
9541 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9542 match(If boolnode (CmpI src1 src2));
9543 effect(USE labl, KILL cr);
9544 predicate(VM_Version::has_CompareBranch());
9545 ins_cost(BRANCH_COST+DEFAULT_COST);
9546 // TODO: s390 port size(FIXED_SIZE);
9547 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9548 opcode(CHI_ZOPC, BRCL_ZOPC);
9549 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9550 ins_pipe(pipe_class_dummy);
9551 ins_short_branch(0);
9552 %}
9553
9554 // INT REG/IMM operands
9555 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9556 match(If boolnode (CmpU src1 src2));
9557 effect(USE labl, KILL cr);
9558 predicate(VM_Version::has_CompareBranch());
9559 ins_cost(BRANCH_COST+DEFAULT_COST);
9560 // TODO: s390 port size(FIXED_SIZE);
9561 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9562 opcode(CLFI_ZOPC, BRCL_ZOPC);
9563 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9564 ins_pipe(pipe_class_dummy);
9565 ins_short_branch(0);
9566 %}
9567
9568 // LONG REG/IMM operands
9569 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9570 match(If boolnode (CmpL src1 src2));
9571 effect(USE labl, KILL cr);
9572 predicate(VM_Version::has_CompareBranch());
9573 ins_cost(BRANCH_COST+DEFAULT_COST);
9574 // TODO: s390 port size(FIXED_SIZE);
9575 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9576 opcode(CGHI_ZOPC, BRCL_ZOPC);
9577 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9578 ins_pipe(pipe_class_dummy);
9579 ins_short_branch(0);
9580 %}
9581
9582 // PTR REG-imm operands
9583
9584 // Separate rules for regular and narrow oops. ADLC can't recognize
9585 // rules with polymorphic operands to be sisters -> shorten_branches
9586 // will not shorten.
9587
9588 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9589 match(If boolnode (CmpP src1 src2));
9590 effect(USE labl, KILL cr);
9591 predicate(VM_Version::has_CompareBranch());
9592 ins_cost(BRANCH_COST+DEFAULT_COST);
9593 // TODO: s390 port size(FIXED_SIZE);
9594 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9595 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9596 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9597 ins_pipe(pipe_class_dummy);
9598 ins_short_branch(0);
9599 %}
9600
9601 // Compare against zero only, do not mix N and P oops (encode/decode required).
9602 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9603 match(If boolnode (CmpP (DecodeN src1) src2));
9604 effect(USE labl, KILL cr);
9605 predicate(VM_Version::has_CompareBranch());
9606 ins_cost(BRANCH_COST+DEFAULT_COST);
9607 // TODO: s390 port size(FIXED_SIZE);
9608 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9609 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9610 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9611 ins_pipe(pipe_class_dummy);
9612 ins_short_branch(0);
9613 %}
9614
9615 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9616 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9617 effect(USE labl, KILL cr);
9618 predicate(VM_Version::has_CompareBranch());
9619 ins_cost(BRANCH_COST+DEFAULT_COST);
9620 // TODO: s390 port size(FIXED_SIZE);
9621 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %}
9622 opcode(CLGFI_ZOPC, BRCL_ZOPC);
9623 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9624 ins_pipe(pipe_class_dummy);
9625 ins_short_branch(0);
9626 %}
9627
9628 // ============================================================================
9629 // Long Compare
9630
9631 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9632 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9633 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9634 // are collapsed internally in the ADLC's dfa-gen code. The match for
9635 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9636 // foo match ends up with the wrong leaf. One fix is to not match both
9637 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9638 // both forms beat the trinary form of long-compare and both are very useful
9639 // on platforms which have few registers.
9640
9641 // Manifest a CmpL3 result in an integer register. Very painful.
9642 // This is the test to avoid.
9643 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9644 match(Set dst (CmpL3 src1 src2));
9645 effect(KILL cr);
9646 ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9647 size(24);
9648 format %{ "CmpL3 $dst,$src1,$src2" %}
9649 ins_encode %{
9650 Label done;
9651 // compare registers
9652 __ z_cgr($src1$$Register, $src2$$Register);
9653 // Convert condition code into -1,0,1, where
9654 // -1 means less
9655 // 0 means equal
9656 // 1 means greater.
9657 if (VM_Version::has_LoadStoreConditional()) {
9658 Register one = Z_R0_scratch;
9659 Register minus_one = Z_R1_scratch;
9660 __ z_lghi(minus_one, -1);
9661 __ z_lghi(one, 1);
9662 __ z_lghi( $dst$$Register, 0);
9663 __ z_locgr($dst$$Register, one, Assembler::bcondHigh);
9664 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9665 } else {
9666 __ clear_reg($dst$$Register, true, false);
9667 __ z_bre(done);
9668 __ z_lhi($dst$$Register, 1);
9669 __ z_brh(done);
9670 __ z_lhi($dst$$Register, -1);
9671 }
9672 __ bind(done);
9673 %}
9674 ins_pipe(pipe_class_dummy);
9675 %}
9676
9677 // ============================================================================
9678 // Safepoint Instruction
9679
9680 instruct safePoint() %{
9681 match(SafePoint);
9682 predicate(false);
9683 // TODO: s390 port size(FIXED_SIZE);
9684 format %{ "UNIMPLEMENTED Safepoint_ " %}
9685 ins_encode(enc_unimplemented());
9686 ins_pipe(pipe_class_dummy);
9687 %}
9688
9689 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9690 match(SafePoint poll);
9691 effect(USE poll, KILL cr); // R0 is killed, too.
9692 // TODO: s390 port size(FIXED_SIZE);
9693 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %}
9694 ins_encode %{
9695 // Mark the code position where the load from the safepoint
9696 // polling page was emitted as relocInfo::poll_type.
9697 __ relocate(relocInfo::poll_type);
9698 __ load_from_polling_page($poll$$Register);
9699 %}
9700 ins_pipe(pipe_class_dummy);
9701 %}
9702
9703 // ============================================================================
9704
9705 // Call Instructions
9706
9707 // Call Java Static Instruction
9708 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9709 match(CallStaticJava);
9710 effect(USE meth);
9711 ins_cost(CALL_COST);
9712 // TODO: s390 port size(VARIABLE_SIZE);
9713 format %{ "CALL,static dynTOC $meth; ==> " %}
9714 ins_encode( z_enc_java_static_call(meth) );
9715 ins_pipe(pipe_class_dummy);
9716 ins_alignment(2);
9717 %}
9718
9719 // Call Java Dynamic Instruction
9720 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9721 match(CallDynamicJava);
9722 effect(USE meth);
9723 ins_cost(CALL_COST);
9724 // TODO: s390 port size(VARIABLE_SIZE);
9725 format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9726 ins_encode(z_enc_java_dynamic_call(meth));
9727 ins_pipe(pipe_class_dummy);
9728 ins_alignment(2);
9729 %}
9730
9731 // Call Runtime Instruction
9732 instruct CallRuntimeDirect(method meth) %{
9733 match(CallRuntime);
9734 effect(USE meth);
9735 ins_cost(CALL_COST);
9736 // TODO: s390 port size(VARIABLE_SIZE);
9737 ins_num_consts(1);
9738 ins_alignment(2);
9739 format %{ "CALL,runtime" %}
9740 ins_encode( z_enc_java_to_runtime_call(meth) );
9741 ins_pipe(pipe_class_dummy);
9742 %}
9743
9744 // Call runtime without safepoint - same as CallRuntime
9745 instruct CallLeafDirect(method meth) %{
9746 match(CallLeaf);
9747 effect(USE meth);
9748 ins_cost(CALL_COST);
9749 // TODO: s390 port size(VARIABLE_SIZE);
9750 ins_num_consts(1);
9751 ins_alignment(2);
9752 format %{ "CALL,runtime leaf $meth" %}
9753 ins_encode( z_enc_java_to_runtime_call(meth) );
9754 ins_pipe(pipe_class_dummy);
9755 %}
9756
9757 // Call runtime without safepoint - same as CallLeaf
9758 instruct CallLeafNoFPDirect(method meth) %{
9759 match(CallLeafNoFP);
9760 effect(USE meth);
9761 ins_cost(CALL_COST);
9762 // TODO: s390 port size(VARIABLE_SIZE);
9763 ins_num_consts(1);
9764 format %{ "CALL,runtime leaf nofp $meth" %}
9765 ins_encode( z_enc_java_to_runtime_call(meth) );
9766 ins_pipe(pipe_class_dummy);
9767 ins_alignment(2);
9768 %}
9769
9770 // Tail Call; Jump from runtime stub to Java code.
9771 // Also known as an 'interprocedural jump'.
9772 // Target of jump will eventually return to caller.
9773 // TailJump below removes the return address.
9774 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{
9775 match(TailCall jump_target method_oop);
9776 ins_cost(CALL_COST);
9777 size(2);
9778 format %{ "Jmp $jump_target\t# $method_oop holds method oop" %}
9779 ins_encode %{ __ z_br($jump_target$$Register); %}
9780 ins_pipe(pipe_class_dummy);
9781 %}
9782
9783 // Return Instruction
9784 instruct Ret() %{
9785 match(Return);
9786 size(2);
9787 format %{ "BR(Z_R14) // branch to link register" %}
9788 ins_encode %{ __ z_br(Z_R14); %}
9789 ins_pipe(pipe_class_dummy);
9790 %}
9791
9792 // Tail Jump; remove the return address; jump to target.
9793 // TailCall above leaves the return address around.
9794 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9795 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9796 // "restore" before this instruction (in Epilogue), we need to materialize it
9797 // in %i0.
9798 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
9799 match(TailJump jump_target ex_oop);
9800 ins_cost(CALL_COST);
9801 size(8);
9802 format %{ "TailJump $jump_target" %}
9803 ins_encode %{
9804 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
9805 __ z_br($jump_target$$Register);
9806 %}
9807 ins_pipe(pipe_class_dummy);
9808 %}
9809
9810 // Create exception oop: created by stack-crawling runtime code.
9811 // Created exception is now available to this handler, and is setup
9812 // just prior to jumping to this handler. No code emitted.
9813 instruct CreateException(rarg1RegP ex_oop) %{
9814 match(Set ex_oop (CreateEx));
9815 ins_cost(0);
9816 size(0);
9817 format %{ "# exception oop; no code emitted" %}
9818 ins_encode(/*empty*/);
9819 ins_pipe(pipe_class_dummy);
9820 %}
9821
9822 // Rethrow exception: The exception oop will come in the first
9823 // argument position. Then JUMP (not call) to the rethrow stub code.
9824 instruct RethrowException() %{
9825 match(Rethrow);
9826 ins_cost(CALL_COST);
9827 // TODO: s390 port size(VARIABLE_SIZE);
9828 format %{ "Jmp rethrow_stub" %}
9829 ins_encode %{
9830 cbuf.set_insts_mark();
9831 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
9832 __ z_br(Z_R1_scratch);
9833 %}
9834 ins_pipe(pipe_class_dummy);
9835 %}
9836
9837 // Die now.
9838 instruct ShouldNotReachHere() %{
9839 match(Halt);
9840 ins_cost(CALL_COST);
9841 size(2);
9842 format %{ "ILLTRAP; ShouldNotReachHere" %}
9843 ins_encode %{ __ z_illtrap(); %}
9844 ins_pipe(pipe_class_dummy);
9845 %}
9846
9847 // ============================================================================
9848 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9849 // array for an instance of the superklass. Set a hidden internal cache on a
9850 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9851 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9852 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
9853 rarg4RegP scratch1, rarg5RegP scratch2) %{
9854 match(Set index (PartialSubtypeCheck sub super));
9855 effect(KILL pcc, KILL scratch1, KILL scratch2);
9856 ins_cost(10 * DEFAULT_COST);
9857 // TODO: s390 port size(FIXED_SIZE);
9858 format %{ " CALL PartialSubtypeCheck\n" %}
9859 ins_encode %{
9860 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9861 __ load_const_optimized(Z_ARG4, stub_address);
9862 __ z_basr(Z_R14, Z_ARG4);
9863 %}
9864 ins_pipe(pipe_class_dummy);
9865 %}
9866
9867 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero,
9868 rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{
9869 match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero));
9870 effect(KILL scratch1, KILL scratch2, KILL index);
9871 ins_cost(10 * DEFAULT_COST);
9872 // TODO: s390 port size(FIXED_SIZE);
9873 format %{ "CALL PartialSubtypeCheck_vs_zero\n" %}
9874 ins_encode %{
9875 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9876 __ load_const_optimized(Z_ARG4, stub_address);
9877 __ z_basr(Z_R14, Z_ARG4);
9878 %}
9879 ins_pipe(pipe_class_dummy);
9880 %}
9881
9882 // ============================================================================
9883 // inlined locking and unlocking
9884
9885 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9886 match(Set pcc (FastLock oop box));
9887 effect(TEMP tmp1, TEMP tmp2);
9888 ins_cost(100);
9889 // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized.
9890 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9891 ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9892 UseBiasedLocking && !UseOptoBiasInlining); %}
9893 ins_pipe(pipe_class_dummy);
9894 %}
9895
9896 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9897 match(Set pcc (FastUnlock oop box));
9898 effect(TEMP tmp1, TEMP tmp2);
9899 ins_cost(100);
9900 // TODO: s390 port size(FIXED_SIZE); // emitted code depends on UseBiasedLocking being on/off.
9901 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9902 ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9903 UseBiasedLocking && !UseOptoBiasInlining); %}
9904 ins_pipe(pipe_class_dummy);
9905 %}
9906
9907 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
9908 match(Set dummy (ClearArray cnt base));
9909 effect(KILL cr);
9910 ins_cost(100);
9911 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions.
9912 format %{ "ClearArrayConst $cnt,$base" %}
9913 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
9914 ins_pipe(pipe_class_dummy);
9915 %}
9916
9917 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{
9918 match(Set dummy (ClearArray cnt base));
9919 effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too.
9920 ins_cost(200);
9921 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader.
9922 format %{ "ClearArrayConstBig $cnt,$base" %}
9923 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $srcA$$Register, $srcL$$Register); %}
9924 ins_pipe(pipe_class_dummy);
9925 %}
9926
9927 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{
9928 match(Set dummy (ClearArray cnt base));
9929 effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too.
9930 ins_cost(300);
9931 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
9932 format %{ "ClearArrayVar $cnt,$base" %}
9933 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $srcA$$Register, $srcL$$Register); %}
9934 ins_pipe(pipe_class_dummy);
9935 %}
9936
9937 // ============================================================================
9938 // CompactStrings
9939
9940 // String equals
9941 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9942 match(Set result (StrEquals (Binary str1 str2) cnt));
9943 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9944 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
9945 ins_cost(300);
9946 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9947 ins_encode %{
9948 __ array_equals(false, $str1$$Register, $str2$$Register,
9949 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9950 $result$$Register, true /* byte */);
9951 %}
9952 ins_pipe(pipe_class_dummy);
9953 %}
9954
9955 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9956 match(Set result (StrEquals (Binary str1 str2) cnt));
9957 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9958 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
9959 ins_cost(300);
9960 format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %}
9961 ins_encode %{
9962 __ array_equals(false, $str1$$Register, $str2$$Register,
9963 $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9964 $result$$Register, false /* byte */);
9965 %}
9966 ins_pipe(pipe_class_dummy);
9967 %}
9968
9969 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
9970 match(Set result (StrEquals (Binary str1 str2) cnt));
9971 effect(KILL cr); // R0 is killed, too.
9972 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
9973 ins_cost(100);
9974 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9975 ins_encode %{
9976 const int cnt_imm = $cnt$$constant;
9977 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
9978 __ z_lhi($result$$Register, 1);
9979 if (cnt_imm) {
9980 if (VM_Version::has_LoadStoreConditional()) {
9981 __ z_lhi(Z_R0_scratch, 0);
9982 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
9983 } else {
9984 Label Lskip;
9985 __ z_bre(Lskip);
9986 __ clear_reg($result$$Register);
9987 __ bind(Lskip);
9988 }
9989 }
9990 %}
9991 ins_pipe(pipe_class_dummy);
9992 %}
9993
9994 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
9995 match(Set result (StrEquals (Binary str1 str2) cnt));
9996 effect(KILL cr); // R0 is killed, too.
9997 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
9998 ins_cost(100);
9999 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
10000 ins_encode %{
10001 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
10002 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
10003 __ z_lhi($result$$Register, 1);
10004 if (cnt_imm) {
10005 if (VM_Version::has_LoadStoreConditional()) {
10006 __ z_lhi(Z_R0_scratch, 0);
10007 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10008 } else {
10009 Label Lskip;
10010 __ z_bre(Lskip);
10011 __ clear_reg($result$$Register);
10012 __ bind(Lskip);
10013 }
10014 }
10015 %}
10016 ins_pipe(pipe_class_dummy);
10017 %}
10018
10019 // Array equals
10020 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10021 match(Set result (AryEq ary1 ary2));
10022 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10023 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10024 ins_cost(300);
10025 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10026 ins_encode %{
10027 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10028 noreg, $oddReg$$Register, $evenReg$$Register,
10029 $result$$Register, true /* byte */);
10030 %}
10031 ins_pipe(pipe_class_dummy);
10032 %}
10033
10034 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10035 match(Set result (AryEq ary1 ary2));
10036 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10037 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10038 ins_cost(300);
10039 format %{ "Array Equals $ary1,$ary2 -> $result" %}
10040 ins_encode %{
10041 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10042 noreg, $oddReg$$Register, $evenReg$$Register,
10043 $result$$Register, false /* byte */);
10044 %}
10045 ins_pipe(pipe_class_dummy);
10046 %}
10047
10048 // String CompareTo
10049 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10050 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10051 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10052 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10053 ins_cost(300);
10054 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10055 ins_encode %{
10056 __ string_compare($str1$$Register, $str2$$Register,
10057 $cnt1$$Register, $cnt2$$Register,
10058 $oddReg$$Register, $evenReg$$Register,
10059 $result$$Register, StrIntrinsicNode::LL);
10060 %}
10061 ins_pipe(pipe_class_dummy);
10062 %}
10063
10064 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10065 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10066 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10067 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10068 ins_cost(300);
10069 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10070 ins_encode %{
10071 __ string_compare($str1$$Register, $str2$$Register,
10072 $cnt1$$Register, $cnt2$$Register,
10073 $oddReg$$Register, $evenReg$$Register,
10074 $result$$Register, StrIntrinsicNode::UU);
10075 %}
10076 ins_pipe(pipe_class_dummy);
10077 %}
10078
10079 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10080 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10081 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10082 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10083 ins_cost(300);
10084 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10085 ins_encode %{
10086 __ string_compare($str1$$Register, $str2$$Register,
10087 $cnt1$$Register, $cnt2$$Register,
10088 $oddReg$$Register, $evenReg$$Register,
10089 $result$$Register, StrIntrinsicNode::LU);
10090 %}
10091 ins_pipe(pipe_class_dummy);
10092 %}
10093
10094 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10095 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10096 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10097 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10098 ins_cost(300);
10099 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10100 ins_encode %{
10101 __ string_compare($str2$$Register, $str1$$Register,
10102 $cnt2$$Register, $cnt1$$Register,
10103 $oddReg$$Register, $evenReg$$Register,
10104 $result$$Register, StrIntrinsicNode::UL);
10105 %}
10106 ins_pipe(pipe_class_dummy);
10107 %}
10108
10109 // String IndexOfChar
10110 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10111 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10112 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10113 ins_cost(200);
10114 format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10115 ins_encode %{
10116 __ string_indexof_char($result$$Register,
10117 $haystack$$Register, $haycnt$$Register,
10118 $ch$$Register, 0 /* unused, ch is in register */,
10119 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10120 %}
10121 ins_pipe(pipe_class_dummy);
10122 %}
10123
10124 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10125 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10126 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10127 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10128 ins_cost(200);
10129 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10130 ins_encode %{
10131 immPOper *needleOper = (immPOper *)$needle;
10132 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10133 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10134 jchar chr;
10135 #ifdef VM_LITTLE_ENDIAN
10136 Unimplemented();
10137 #else
10138 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10139 ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10140 #endif
10141 __ string_indexof_char($result$$Register,
10142 $haystack$$Register, $haycnt$$Register,
10143 noreg, chr,
10144 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10145 %}
10146 ins_pipe(pipe_class_dummy);
10147 %}
10148
10149 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10150 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10151 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10152 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10153 ins_cost(200);
10154 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10155 ins_encode %{
10156 immPOper *needleOper = (immPOper *)$needle;
10157 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10158 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10159 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10160 __ string_indexof_char($result$$Register,
10161 $haystack$$Register, $haycnt$$Register,
10162 noreg, chr,
10163 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10164 %}
10165 ins_pipe(pipe_class_dummy);
10166 %}
10167
10168 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10169 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10170 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10171 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10172 ins_cost(200);
10173 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10174 ins_encode %{
10175 immPOper *needleOper = (immPOper *)$needle;
10176 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10177 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10178 jchar chr = (jchar)needle_values->element_value(0).as_byte();
10179 __ string_indexof_char($result$$Register,
10180 $haystack$$Register, $haycnt$$Register,
10181 noreg, chr,
10182 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10183 %}
10184 ins_pipe(pipe_class_dummy);
10185 %}
10186
10187 // String IndexOf
10188 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10189 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10190 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10191 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10192 ins_cost(250);
10193 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10194 ins_encode %{
10195 __ string_indexof($result$$Register,
10196 $haystack$$Register, $haycnt$$Register,
10197 $needle$$Register, noreg, $needlecntImm$$constant,
10198 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10199 %}
10200 ins_pipe(pipe_class_dummy);
10201 %}
10202
10203 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10204 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10205 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10206 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10207 ins_cost(250);
10208 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10209 ins_encode %{
10210 __ string_indexof($result$$Register,
10211 $haystack$$Register, $haycnt$$Register,
10212 $needle$$Register, noreg, $needlecntImm$$constant,
10213 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10214 %}
10215 ins_pipe(pipe_class_dummy);
10216 %}
10217
10218 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10219 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10220 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10221 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10222 ins_cost(250);
10223 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10224 ins_encode %{
10225 __ string_indexof($result$$Register,
10226 $haystack$$Register, $haycnt$$Register,
10227 $needle$$Register, noreg, $needlecntImm$$constant,
10228 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10229 %}
10230 ins_pipe(pipe_class_dummy);
10231 %}
10232
10233 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10234 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10235 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10236 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10237 ins_cost(300);
10238 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10239 ins_encode %{
10240 __ string_indexof($result$$Register,
10241 $haystack$$Register, $haycnt$$Register,
10242 $needle$$Register, $needlecnt$$Register, 0,
10243 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10244 %}
10245 ins_pipe(pipe_class_dummy);
10246 %}
10247
10248 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10249 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10250 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10251 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10252 ins_cost(300);
10253 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10254 ins_encode %{
10255 __ string_indexof($result$$Register,
10256 $haystack$$Register, $haycnt$$Register,
10257 $needle$$Register, $needlecnt$$Register, 0,
10258 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10259 %}
10260 ins_pipe(pipe_class_dummy);
10261 %}
10262
10263 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10264 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10265 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10266 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10267 ins_cost(300);
10268 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10269 ins_encode %{
10270 __ string_indexof($result$$Register,
10271 $haystack$$Register, $haycnt$$Register,
10272 $needle$$Register, $needlecnt$$Register, 0,
10273 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10274 %}
10275 ins_pipe(pipe_class_dummy);
10276 %}
10277
10278 // char[] to byte[] compression
10279 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10280 match(Set result (StrCompressedCopy src (Binary dst len)));
10281 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10282 ins_cost(300);
10283 format %{ "String Compress $src->$dst($len) -> $result" %}
10284 ins_encode %{
10285 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10286 $tmp$$Register, false);
10287 %}
10288 ins_pipe(pipe_class_dummy);
10289 %}
10290
10291 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10292 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10293 // match(Set dummy (StrInflatedCopy src (Binary dst len)));
10294 // effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10295 // predicate(VM_Version::has_ETF2Enhancements());
10296 // ins_cost(300);
10297 // format %{ "String Inflate (trot) $dst,$src($len)" %}
10298 // ins_encode %{
10299 // __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10300 // %}
10301 // ins_pipe(pipe_class_dummy);
10302 //%}
10303
10304 // byte[] to char[] inflation
10305 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{
10306 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10307 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10308 ins_cost(300);
10309 format %{ "String Inflate $src->$dst($len)" %}
10310 ins_encode %{
10311 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10312 %}
10313 ins_pipe(pipe_class_dummy);
10314 %}
10315
10316 // byte[] to char[] inflation
10317 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{
10318 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10319 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10320 ins_cost(300);
10321 format %{ "String Inflate (constLen) $src->$dst($len)" %}
10322 ins_encode %{
10323 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant);
10324 %}
10325 ins_pipe(pipe_class_dummy);
10326 %}
10327
10328 // StringCoding.java intrinsics
10329 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10330 match(Set result (HasNegatives ary1 len));
10331 effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10332 ins_cost(300);
10333 format %{ "has negatives byte[] $ary1($len) -> $result" %}
10334 ins_encode %{
10335 __ has_negatives($result$$Register, $ary1$$Register, $len$$Register,
10336 $oddReg$$Register, $evenReg$$Register, $tmp$$Register);
10337 %}
10338 ins_pipe(pipe_class_dummy);
10339 %}
10340
10341 // encode char[] to byte[] in ISO_8859_1
10342 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10343 match(Set result (EncodeISOArray src (Binary dst len)));
10344 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10345 ins_cost(300);
10346 format %{ "Encode array $src->$dst($len) -> $result" %}
10347 ins_encode %{
10348 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10349 $tmp$$Register, true);
10350 %}
10351 ins_pipe(pipe_class_dummy);
10352 %}
10353
10354
10355 //----------PEEPHOLE RULES-----------------------------------------------------
10356 // These must follow all instruction definitions as they use the names
10357 // defined in the instructions definitions.
10358 //
10359 // peepmatch (root_instr_name [preceeding_instruction]*);
10360 //
10361 // peepconstraint %{
10362 // (instruction_number.operand_name relational_op instruction_number.operand_name
10363 // [, ...]);
10364 // // instruction numbers are zero-based using left to right order in peepmatch
10365 //
10366 // peepreplace (instr_name([instruction_number.operand_name]*));
10367 // // provide an instruction_number.operand_name for each operand that appears
10368 // // in the replacement instruction's match rule
10369 //
10370 // ---------VM FLAGS---------------------------------------------------------
10371 //
10372 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10373 //
10374 // Each peephole rule is given an identifying number starting with zero and
10375 // increasing by one in the order seen by the parser. An individual peephole
10376 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10377 // on the command-line.
10378 //
10379 // ---------CURRENT LIMITATIONS----------------------------------------------
10380 //
10381 // Only match adjacent instructions in same basic block
10382 // Only equality constraints
10383 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10384 // Only one replacement instruction
10385 //
10386 // ---------EXAMPLE----------------------------------------------------------
10387 //
10388 // // pertinent parts of existing instructions in architecture description
10389 // instruct movI(eRegI dst, eRegI src) %{
10390 // match(Set dst (CopyI src));
10391 // %}
10392 //
10393 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10394 // match(Set dst (AddI dst src));
10395 // effect(KILL cr);
10396 // %}
10397 //
10398 // // Change (inc mov) to lea
10399 // peephole %{
10400 // // increment preceeded by register-register move
10401 // peepmatch (incI_eReg movI);
10402 // // require that the destination register of the increment
10403 // // match the destination register of the move
10404 // peepconstraint (0.dst == 1.dst);
10405 // // construct a replacement instruction that sets
10406 // // the destination to (move's source register + one)
10407 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10408 // %}
10409 //
10410 // Implementation no longer uses movX instructions since
10411 // machine-independent system no longer uses CopyX nodes.
10412 //
10413 // peephole %{
10414 // peepmatch (incI_eReg movI);
10415 // peepconstraint (0.dst == 1.dst);
10416 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10417 // %}
10418 //
10419 // peephole %{
10420 // peepmatch (decI_eReg movI);
10421 // peepconstraint (0.dst == 1.dst);
10422 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10423 // %}
10424 //
10425 // peephole %{
10426 // peepmatch (addI_eReg_imm movI);
10427 // peepconstraint (0.dst == 1.dst);
10428 // peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10429 // %}
10430 //
10431 // peephole %{
10432 // peepmatch (addP_eReg_imm movP);
10433 // peepconstraint (0.dst == 1.dst);
10434 // peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10435 // %}
10436
10437
10438 // This peephole rule does not work, probably because ADLC can't handle two effects:
10439 // Effect 1 is defining 0.op1 and effect 2 is setting CC
10440 // condense a load from memory and subsequent test for zero
10441 // into a single, more efficient ICM instruction.
10442 // peephole %{
10443 // peepmatch (compI_iReg_imm0 loadI);
10444 // peepconstraint (1.dst == 0.op1);
10445 // peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10446 // %}
10447
10448 // // Change load of spilled value to only a spill
10449 // instruct storeI(memory mem, eRegI src) %{
10450 // match(Set mem (StoreI mem src));
10451 // %}
10452 //
10453 // instruct loadI(eRegI dst, memory mem) %{
10454 // match(Set dst (LoadI mem));
10455 // %}
10456 //
10457 peephole %{
10458 peepmatch (loadI storeI);
10459 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10460 peepreplace (storeI(1.mem 1.mem 1.src));
10461 %}
10462
10463 peephole %{
10464 peepmatch (loadL storeL);
10465 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10466 peepreplace (storeL(1.mem 1.mem 1.src));
10467 %}
10468
10469 peephole %{
10470 peepmatch (loadP storeP);
10471 peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10472 peepreplace (storeP(1.dst 1.dst 1.src));
10473 %}
10474
10475 //----------SUPERWORD RULES---------------------------------------------------
10476
10477 // Expand rules for special cases
10478
10479 instruct expand_storeF(stackSlotF mem, regF src) %{
10480 // No match rule, false predicate, for expand only.
10481 effect(DEF mem, USE src);
10482 predicate(false);
10483 ins_cost(MEMORY_REF_COST);
10484 // TODO: s390 port size(FIXED_SIZE);
10485 format %{ "STE $src,$mem\t # replicate(float2stack)" %}
10486 opcode(STE_ZOPC, STE_ZOPC);
10487 ins_encode(z_form_rt_mem(src, mem));
10488 ins_pipe(pipe_class_dummy);
10489 %}
10490
10491 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10492 // No match rule, false predicate, for expand only.
10493 effect(DEF dst, USE mem);
10494 predicate(false);
10495 ins_cost(MEMORY_REF_COST);
10496 // TODO: s390 port size(FIXED_SIZE);
10497 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10498 opcode(LLGF_ZOPC, LLGF_ZOPC);
10499 ins_encode(z_form_rt_mem(dst, mem));
10500 ins_pipe(pipe_class_dummy);
10501 %}
10502
10503 // Replicate scalar int to packed int values (8 Bytes)
10504 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10505 // Dummy match rule, false predicate, for expand only.
10506 match(Set dst (ConvI2L src));
10507 predicate(false);
10508 ins_cost(DEFAULT_COST);
10509 // TODO: s390 port size(FIXED_SIZE);
10510 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10511 ins_encode %{
10512 if ($dst$$Register == $src$$Register) {
10513 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10514 __ z_ogr($dst$$Register, Z_R0_scratch);
10515 } else {
10516 __ z_sllg($dst$$Register, $src$$Register, 64-32);
10517 __ z_ogr( $dst$$Register, $src$$Register);
10518 }
10519 %}
10520 ins_pipe(pipe_class_dummy);
10521 %}
10522
10523 // Replication
10524
10525 // Exploit rotate_then_insert, if available
10526 // Replicate scalar byte to packed byte values (8 Bytes).
10527 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10528 match(Set dst (ReplicateB src));
10529 effect(KILL cr);
10530 predicate((n->as_Vector()->length() == 8));
10531 format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10532 ins_encode %{
10533 if ($dst$$Register != $src$$Register) {
10534 __ z_lgr($dst$$Register, $src$$Register);
10535 }
10536 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false);
10537 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10538 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10539 %}
10540 ins_pipe(pipe_class_dummy);
10541 %}
10542
10543 // Replicate scalar byte to packed byte values (8 Bytes).
10544 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10545 match(Set dst (ReplicateB src));
10546 predicate(n->as_Vector()->length() == 8);
10547 ins_should_rematerialize(true);
10548 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10549 ins_encode %{
10550 int64_t Isrc8 = $src$$constant & 0x000000ff;
10551 int64_t Isrc16 = Isrc8 << 8 | Isrc8;
10552 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10553 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10554
10555 __ z_llilf($dst$$Register, Isrc32);
10556 __ z_iihf($dst$$Register, Isrc32);
10557 %}
10558 ins_pipe(pipe_class_dummy);
10559 %}
10560
10561 // Replicate scalar byte to packed byte values (8 Bytes).
10562 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10563 match(Set dst (ReplicateB src));
10564 predicate(n->as_Vector()->length() == 8);
10565 ins_should_rematerialize(true);
10566 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10567 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10568 ins_pipe(pipe_class_dummy);
10569 %}
10570
10571 // Replicate scalar byte to packed byte values (8 Bytes).
10572 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10573 match(Set dst (ReplicateB src));
10574 predicate(n->as_Vector()->length() == 8);
10575 ins_should_rematerialize(true);
10576 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10577 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10578 ins_pipe(pipe_class_dummy);
10579 %}
10580
10581 // Exploit rotate_then_insert, if available
10582 // Replicate scalar short to packed short values (8 Bytes).
10583 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10584 match(Set dst (ReplicateS src));
10585 effect(KILL cr);
10586 predicate((n->as_Vector()->length() == 4));
10587 format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10588 ins_encode %{
10589 if ($dst$$Register != $src$$Register) {
10590 __ z_lgr($dst$$Register, $src$$Register);
10591 }
10592 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10593 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10594 %}
10595 ins_pipe(pipe_class_dummy);
10596 %}
10597
10598 // Replicate scalar short to packed short values (8 Bytes).
10599 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10600 match(Set dst (ReplicateS src));
10601 predicate(n->as_Vector()->length() == 4);
10602 ins_should_rematerialize(true);
10603 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10604 ins_encode %{
10605 int64_t Isrc16 = $src$$constant & 0x0000ffff;
10606 int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10607 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10608 ") should be handled by other match rules.", $src$$constant);
10609
10610 __ z_llilf($dst$$Register, Isrc32);
10611 __ z_iihf($dst$$Register, Isrc32);
10612 %}
10613 ins_pipe(pipe_class_dummy);
10614 %}
10615
10616 // Replicate scalar short to packed short values (8 Bytes).
10617 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10618 match(Set dst (ReplicateS src));
10619 predicate(n->as_Vector()->length() == 4);
10620 ins_should_rematerialize(true);
10621 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10622 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10623 ins_pipe(pipe_class_dummy);
10624 %}
10625
10626 // Replicate scalar short to packed short values (8 Bytes).
10627 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10628 match(Set dst (ReplicateS src));
10629 predicate(n->as_Vector()->length() == 4);
10630 ins_should_rematerialize(true);
10631 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10632 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10633 ins_pipe(pipe_class_dummy);
10634 %}
10635
10636 // Exploit rotate_then_insert, if available.
10637 // Replicate scalar int to packed int values (8 Bytes).
10638 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10639 match(Set dst (ReplicateI src));
10640 effect(KILL cr);
10641 predicate((n->as_Vector()->length() == 2));
10642 format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10643 ins_encode %{
10644 if ($dst$$Register != $src$$Register) {
10645 __ z_lgr($dst$$Register, $src$$Register);
10646 }
10647 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10648 %}
10649 ins_pipe(pipe_class_dummy);
10650 %}
10651
10652 // Replicate scalar int to packed int values (8 Bytes).
10653 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10654 match(Set dst (ReplicateI src));
10655 predicate(n->as_Vector()->length() == 2);
10656 ins_should_rematerialize(true);
10657 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10658 ins_encode %{
10659 int64_t Isrc32 = $src$$constant;
10660 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10661
10662 __ z_llilf($dst$$Register, Isrc32);
10663 __ z_iihf($dst$$Register, Isrc32);
10664 %}
10665 ins_pipe(pipe_class_dummy);
10666 %}
10667
10668 // Replicate scalar int to packed int values (8 Bytes).
10669 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
10670 match(Set dst (ReplicateI src));
10671 predicate(n->as_Vector()->length() == 2);
10672 ins_should_rematerialize(true);
10673 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
10674 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10675 ins_pipe(pipe_class_dummy);
10676 %}
10677
10678 // Replicate scalar int to packed int values (8 Bytes).
10679 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
10680 match(Set dst (ReplicateI src));
10681 predicate(n->as_Vector()->length() == 2);
10682 ins_should_rematerialize(true);
10683 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
10684 ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10685 ins_pipe(pipe_class_dummy);
10686 %}
10687
10688 //
10689
10690 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
10691 match(Set dst (ReplicateF src));
10692 effect(KILL cr);
10693 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10694 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
10695 expand %{
10696 stackSlotF tmp;
10697 iRegL tmp2;
10698 expand_storeF(tmp, src);
10699 expand_LoadLogical_I2L(tmp2, tmp);
10700 expand_Repl2I_reg(dst, tmp2);
10701 %}
10702 %}
10703
10704 // Replicate scalar float to packed float values in GREG (8 Bytes).
10705 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
10706 match(Set dst (ReplicateF src));
10707 effect(KILL cr);
10708 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10709 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
10710 ins_encode %{
10711 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
10712 __ z_lgdr($dst$$Register, $src$$FloatRegister);
10713
10714 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg.
10715 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall.
10716 __ z_ogr($dst$$Register, Z_R0_scratch);
10717 %}
10718 ins_pipe(pipe_class_dummy);
10719 %}
10720
10721 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
10722 instruct Repl2F_imm(iRegL dst, immF src) %{
10723 match(Set dst (ReplicateF src));
10724 predicate(n->as_Vector()->length() == 2);
10725 ins_should_rematerialize(true);
10726 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
10727 ins_encode %{
10728 union {
10729 int Isrc32;
10730 float Fsrc32;
10731 };
10732 Fsrc32 = $src$$constant;
10733 __ z_llilf($dst$$Register, Isrc32);
10734 __ z_iihf($dst$$Register, Isrc32);
10735 %}
10736 ins_pipe(pipe_class_dummy);
10737 %}
10738
10739 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
10740 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
10741 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
10742 match(Set dst (ReplicateF src));
10743 predicate(n->as_Vector()->length() == 2);
10744 ins_should_rematerialize(true);
10745 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
10746 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10747 ins_pipe(pipe_class_dummy);
10748 %}
10749
10750 // Store
10751
10752 // Store Aligned Packed Byte register to memory (8 Bytes).
10753 instruct storeA8B(memory mem, iRegL src) %{
10754 match(Set mem (StoreVector mem src));
10755 predicate(n->as_StoreVector()->memory_size() == 8);
10756 ins_cost(MEMORY_REF_COST);
10757 // TODO: s390 port size(VARIABLE_SIZE);
10758 format %{ "STG $src,$mem\t # ST(packed8B)" %}
10759 opcode(STG_ZOPC, STG_ZOPC);
10760 ins_encode(z_form_rt_mem_opt(src, mem));
10761 ins_pipe(pipe_class_dummy);
10762 %}
10763
10764 // Load
10765
10766 instruct loadV8(iRegL dst, memory mem) %{
10767 match(Set dst (LoadVector mem));
10768 predicate(n->as_LoadVector()->memory_size() == 8);
10769 ins_cost(MEMORY_REF_COST);
10770 // TODO: s390 port size(VARIABLE_SIZE);
10771 format %{ "LG $dst,$mem\t # L(packed8B)" %}
10772 opcode(LG_ZOPC, LG_ZOPC);
10773 ins_encode(z_form_rt_mem_opt(dst, mem));
10774 ins_pipe(pipe_class_dummy);
10775 %}
10776
10777 //----------POPULATION COUNT RULES--------------------------------------------
10778
10779 // Byte reverse
10780
10781 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
10782 match(Set dst (ReverseBytesI src));
10783 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
10784 ins_cost(DEFAULT_COST);
10785 size(4);
10786 format %{ "LRVR $dst,$src\t# byte reverse int" %}
10787 opcode(LRVR_ZOPC);
10788 ins_encode(z_rreform(dst, src));
10789 ins_pipe(pipe_class_dummy);
10790 %}
10791
10792 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
10793 match(Set dst (ReverseBytesL src));
10794 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported
10795 ins_cost(DEFAULT_COST);
10796 // TODO: s390 port size(FIXED_SIZE);
10797 format %{ "LRVGR $dst,$src\t# byte reverse long" %}
10798 opcode(LRVGR_ZOPC);
10799 ins_encode(z_rreform(dst, src));
10800 ins_pipe(pipe_class_dummy);
10801 %}
10802
10803 // Leading zeroes
10804
10805 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
10806 // returns the bit position of the leftmost 1 in the 64bit source register.
10807 // As the bits are numbered from left to right (0..63), the returned
10808 // position index is equivalent to the number of leading zeroes.
10809 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction
10810 // returns position 64. That's exactly what we need.
10811
10812 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10813 match(Set dst (CountLeadingZerosI src));
10814 effect(KILL tmp, KILL cr);
10815 ins_cost(3 * DEFAULT_COST);
10816 size(14);
10817 format %{ "SLLG $dst,$src,32\t# no need to always count 32 zeroes first\n\t"
10818 "IILH $dst,0x8000 \t# insert \"stop bit\" to force result 32 for zero src.\n\t"
10819 "FLOGR $dst,$dst"
10820 %}
10821 ins_encode %{
10822 // Performance experiments indicate that "FLOGR" is using some kind of
10823 // iteration to find the leftmost "1" bit.
10824 //
10825 // The prior implementation zero-extended the 32-bit argument to 64 bit,
10826 // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
10827 // We could gain measurable speedup in micro benchmark:
10828 //
10829 // leading trailing
10830 // z10: int 2.04 1.68
10831 // long 1.00 1.02
10832 // z196: int 0.99 1.23
10833 // long 1.00 1.11
10834 //
10835 // By shifting the argument into the high-word instead of zero-extending it.
10836 // The add'l branch on condition (taken for a zero argument, very infrequent,
10837 // good prediction) is well compensated for by the savings.
10838 //
10839 // We leave the previous implementation in for some time in the future when
10840 // the "FLOGR" instruction may become less iterative.
10841
10842 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
10843 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
10844 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src.
10845 __ z_flogr($dst$$Register, $dst$$Register);
10846 %}
10847 ins_pipe(pipe_class_dummy);
10848 %}
10849
10850 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
10851 match(Set dst (CountLeadingZerosL src));
10852 effect(KILL tmp, KILL cr);
10853 ins_cost(DEFAULT_COST);
10854 size(4);
10855 format %{ "FLOGR $dst,$src \t# count leading zeros (long)\n\t" %}
10856 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
10857 ins_pipe(pipe_class_dummy);
10858 %}
10859
10860 // trailing zeroes
10861
10862 // We transform the trailing zeroes problem to a leading zeroes problem
10863 // such that can use the FLOGR instruction to our advantage.
10864
10865 // With
10866 // tmp1 = src - 1
10867 // we flip all trailing zeroes to ones and the rightmost one to zero.
10868 // All other bits remain unchanged.
10869 // With the complement
10870 // tmp2 = ~src
10871 // we get all ones in the trailing zeroes positions. Thus,
10872 // tmp3 = tmp1 & tmp2
10873 // yields ones in the trailing zeroes positions and zeroes elsewhere.
10874 // Now we can apply FLOGR and get 64-(trailing zeroes).
10875 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10876 match(Set dst (CountTrailingZerosI src));
10877 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10878 ins_cost(8 * DEFAULT_COST);
10879 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
10880 format %{ "LLGFR $dst,$src \t# clear upper 32 bits (we are dealing with int)\n\t"
10881 "LCGFR $tmp,$src \t# load 2's complement (32->64 bit)\n\t"
10882 "AGHI $dst,-1 \t# tmp1 = src-1\n\t"
10883 "AGHI $tmp,-1 \t# tmp2 = -src-1 = ~src\n\t"
10884 "NGR $dst,$tmp \t# tmp3 = tmp1&tmp2\n\t"
10885 "FLOGR $dst,$dst \t# count trailing zeros (int)\n\t"
10886 "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t"
10887 "LCR $dst,$dst \t# res = -tmp4"
10888 %}
10889 ins_encode %{
10890 Register Rdst = $dst$$Register;
10891 Register Rsrc = $src$$Register;
10892 // Rtmp only needed for for zero-argument shortcut. With kill effect in
10893 // match rule Rsrc = roddReg would be possible, saving one register.
10894 Register Rtmp = $tmp$$Register;
10895
10896 assert_different_registers(Rdst, Rsrc, Rtmp);
10897
10898 // Algorithm:
10899 // - Isolate the least significant (rightmost) set bit using (src & (-src)).
10900 // All other bits in the result are zero.
10901 // - Find the "leftmost one" bit position in the single-bit result from previous step.
10902 // - 63-("leftmost one" bit position) gives the # of trailing zeros.
10903
10904 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
10905 Label done;
10906 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
10907 __ z_lcgfr(Rtmp, Rsrc);
10908 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry.
10909
10910 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit.
10911 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones.
10912 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
10913 // into upper half of reg. Not relevant with sllg below.
10914 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register.
10915 __ z_bre(done); // Shortcut for argument = 1, result will be 0.
10916 // Depends on CC set by ahi above.
10917 // Taken very infrequently, good prediction, no BHT entry.
10918 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
10919 // after SLLG Rdst == 0(64bit)).
10920 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10921 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros
10922 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10923 __ bind(done);
10924 %}
10925 ins_pipe(pipe_class_dummy);
10926 %}
10927
10928 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
10929 match(Set dst (CountTrailingZerosL src));
10930 effect(TEMP_DEF dst, KILL tmp, KILL cr);
10931 ins_cost(8 * DEFAULT_COST);
10932 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off.
10933 format %{ "LCGR $dst,$src \t# preserve src\n\t"
10934 "NGR $dst,$src \t#"
10935 "AGHI $dst,-1 \t# tmp1 = src-1\n\t"
10936 "FLOGR $dst,$dst \t# count trailing zeros (long), kill $tmp\n\t"
10937 "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t"
10938 "LCR $dst,$dst \t#"
10939 %}
10940 ins_encode %{
10941 Register Rdst = $dst$$Register;
10942 Register Rsrc = $src$$Register;
10943 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
10944
10945 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
10946 __ z_lcgr(Rdst, Rsrc);
10947 __ z_ngr(Rdst, Rsrc);
10948 __ add2reg(Rdst, -1);
10949 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10950 __ add2reg(Rdst, -64);
10951 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10952 %}
10953 ins_pipe(pipe_class_dummy);
10954 %}
10955
10956
10957 // bit count
10958
10959 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10960 match(Set dst (PopCountI src));
10961 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10962 predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10963 ins_cost(DEFAULT_COST);
10964 size(24);
10965 format %{ "POPCNT $dst,$src\t# pop count int" %}
10966 ins_encode %{
10967 Register Rdst = $dst$$Register;
10968 Register Rsrc = $src$$Register;
10969 Register Rtmp = $tmp$$Register;
10970
10971 // Prefer compile-time assertion over run-time SIGILL.
10972 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10973 assert_different_registers(Rdst, Rtmp);
10974
10975 // Version 2: shows 10%(z196) improvement over original.
10976 __ z_popcnt(Rdst, Rsrc);
10977 __ z_srlg(Rtmp, Rdst, 16); // calc byte4+byte6 and byte5+byte7
10978 __ z_alr(Rdst, Rtmp); // into byte6 and byte7
10979 __ z_srlg(Rtmp, Rdst, 8); // calc (byte4+byte6) + (byte5+byte7)
10980 __ z_alr(Rdst, Rtmp); // into byte7
10981 __ z_llgcr(Rdst, Rdst); // zero-extend sum
10982 %}
10983 ins_pipe(pipe_class_dummy);
10984 %}
10985
10986 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
10987 match(Set dst (PopCountL src));
10988 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10989 predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10990 ins_cost(DEFAULT_COST);
10991 // TODO: s390 port size(FIXED_SIZE);
10992 format %{ "POPCNT $dst,$src\t# pop count long" %}
10993 ins_encode %{
10994 Register Rdst = $dst$$Register;
10995 Register Rsrc = $src$$Register;
10996 Register Rtmp = $tmp$$Register;
10997
10998 // Prefer compile-time assertion over run-time SIGILL.
10999 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
11000 assert_different_registers(Rdst, Rtmp);
11001
11002 // Original version. Using LA instead of algr seems to be a really bad idea (-35%).
11003 __ z_popcnt(Rdst, Rsrc);
11004 __ z_ahhlr(Rdst, Rdst, Rdst);
11005 __ z_sllg(Rtmp, Rdst, 16);
11006 __ z_algr(Rdst, Rtmp);
11007 __ z_sllg(Rtmp, Rdst, 8);
11008 __ z_algr(Rdst, Rtmp);
11009 __ z_srlg(Rdst, Rdst, 56);
11010 %}
11011 ins_pipe(pipe_class_dummy);
11012 %}
11013
11014 //----------SMARTSPILL RULES---------------------------------------------------
11015 // These must follow all instruction definitions as they use the names
11016 // defined in the instructions definitions.
11017
11018 // ============================================================================
11019 // TYPE PROFILING RULES
11020