1 /*
   2  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/assembler.hpp"
  27 #include "asm/assembler.inline.hpp"
  28 #include "compiler/disassembler.hpp"
  29 #include "gc_interface/collectedHeap.inline.hpp"
  30 #include "interpreter/interpreter.hpp"
  31 #include "memory/cardTableModRefBS.hpp"
  32 #include "memory/resourceArea.hpp"
  33 #include "memory/universe.hpp"
  34 #include "prims/methodHandles.hpp"
  35 #include "runtime/biasedLocking.hpp"
  36 #include "runtime/interfaceSupport.hpp"
  37 #include "runtime/objectMonitor.hpp"
  38 #include "runtime/os.hpp"
  39 #include "runtime/sharedRuntime.hpp"
  40 #include "runtime/stubRoutines.hpp"
  41 #include "utilities/macros.hpp"
  42 #if INCLUDE_ALL_GCS
  43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
  44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
  45 #include "gc_implementation/g1/heapRegion.hpp"
  46 #endif // INCLUDE_ALL_GCS
  47 
  48 #ifdef PRODUCT
  49 #define BLOCK_COMMENT(str) /* nothing */
  50 #define STOP(error) stop(error)
  51 #else
  52 #define BLOCK_COMMENT(str) block_comment(str)
  53 #define STOP(error) block_comment(error); stop(error)
  54 #endif
  55 
  56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  57 
  58 
  59 #ifdef ASSERT
  60 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  61 #endif
  62 
  63 static Assembler::Condition reverse[] = {
  64     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  65     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  66     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  67     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  68     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  69     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  70     Assembler::above          /* belowEqual    = 0x6 */ ,
  71     Assembler::belowEqual     /* above         = 0x7 */ ,
  72     Assembler::positive       /* negative      = 0x8 */ ,
  73     Assembler::negative       /* positive      = 0x9 */ ,
  74     Assembler::noParity       /* parity        = 0xa */ ,
  75     Assembler::parity         /* noParity      = 0xb */ ,
  76     Assembler::greaterEqual   /* less          = 0xc */ ,
  77     Assembler::less           /* greaterEqual  = 0xd */ ,
  78     Assembler::greater        /* lessEqual     = 0xe */ ,
  79     Assembler::lessEqual      /* greater       = 0xf, */
  80 
  81 };
  82 
  83 
  84 // Implementation of MacroAssembler
  85 
  86 // First all the versions that have distinct versions depending on 32/64 bit
  87 // Unless the difference is trivial (1 line or so).
  88 
  89 #ifndef _LP64
  90 
  91 // 32bit versions
  92 
  93 Address MacroAssembler::as_Address(AddressLiteral adr) {
  94   return Address(adr.target(), adr.rspec());
  95 }
  96 
  97 Address MacroAssembler::as_Address(ArrayAddress adr) {
  98   return Address::make_array(adr);
  99 }
 100 
 101 int MacroAssembler::biased_locking_enter(Register lock_reg,
 102                                          Register obj_reg,
 103                                          Register swap_reg,
 104                                          Register tmp_reg,
 105                                          bool swap_reg_contains_mark,
 106                                          Label& done,
 107                                          Label* slow_case,
 108                                          BiasedLockingCounters* counters) {
 109   assert(UseBiasedLocking, "why call this otherwise?");
 110   assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
 111   assert_different_registers(lock_reg, obj_reg, swap_reg);
 112 
 113   if (PrintBiasedLockingStatistics && counters == NULL)
 114     counters = BiasedLocking::counters();
 115 
 116   bool need_tmp_reg = false;
 117   if (tmp_reg == noreg) {
 118     need_tmp_reg = true;
 119     tmp_reg = lock_reg;
 120   } else {
 121     assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
 122   }
 123   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
 124   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
 125   Address klass_addr     (obj_reg, oopDesc::klass_offset_in_bytes());
 126   Address saved_mark_addr(lock_reg, 0);
 127 
 128   // Biased locking
 129   // See whether the lock is currently biased toward our thread and
 130   // whether the epoch is still valid
 131   // Note that the runtime guarantees sufficient alignment of JavaThread
 132   // pointers to allow age to be placed into low bits
 133   // First check to see whether biasing is even enabled for this object
 134   Label cas_label;
 135   int null_check_offset = -1;
 136   if (!swap_reg_contains_mark) {
 137     null_check_offset = offset();
 138     movl(swap_reg, mark_addr);
 139   }
 140   if (need_tmp_reg) {
 141     push(tmp_reg);
 142   }
 143   movl(tmp_reg, swap_reg);
 144   andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
 145   cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
 146   if (need_tmp_reg) {
 147     pop(tmp_reg);
 148   }
 149   jcc(Assembler::notEqual, cas_label);
 150   // The bias pattern is present in the object's header. Need to check
 151   // whether the bias owner and the epoch are both still current.
 152   // Note that because there is no current thread register on x86 we
 153   // need to store off the mark word we read out of the object to
 154   // avoid reloading it and needing to recheck invariants below. This
 155   // store is unfortunate but it makes the overall code shorter and
 156   // simpler.
 157   movl(saved_mark_addr, swap_reg);
 158   if (need_tmp_reg) {
 159     push(tmp_reg);
 160   }
 161   get_thread(tmp_reg);
 162   xorl(swap_reg, tmp_reg);
 163   if (swap_reg_contains_mark) {
 164     null_check_offset = offset();
 165   }
 166   movl(tmp_reg, klass_addr);
 167   xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset()));
 168   andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
 169   if (need_tmp_reg) {
 170     pop(tmp_reg);
 171   }
 172   if (counters != NULL) {
 173     cond_inc32(Assembler::zero,
 174                ExternalAddress((address)counters->biased_lock_entry_count_addr()));
 175   }
 176   jcc(Assembler::equal, done);
 177 
 178   Label try_revoke_bias;
 179   Label try_rebias;
 180 
 181   // At this point we know that the header has the bias pattern and
 182   // that we are not the bias owner in the current epoch. We need to
 183   // figure out more details about the state of the header in order to
 184   // know what operations can be legally performed on the object's
 185   // header.
 186 
 187   // If the low three bits in the xor result aren't clear, that means
 188   // the prototype header is no longer biased and we have to revoke
 189   // the bias on this object.
 190   testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
 191   jcc(Assembler::notZero, try_revoke_bias);
 192 
 193   // Biasing is still enabled for this data type. See whether the
 194   // epoch of the current bias is still valid, meaning that the epoch
 195   // bits of the mark word are equal to the epoch bits of the
 196   // prototype header. (Note that the prototype header's epoch bits
 197   // only change at a safepoint.) If not, attempt to rebias the object
 198   // toward the current thread. Note that we must be absolutely sure
 199   // that the current epoch is invalid in order to do this because
 200   // otherwise the manipulations it performs on the mark word are
 201   // illegal.
 202   testl(swap_reg, markOopDesc::epoch_mask_in_place);
 203   jcc(Assembler::notZero, try_rebias);
 204 
 205   // The epoch of the current bias is still valid but we know nothing
 206   // about the owner; it might be set or it might be clear. Try to
 207   // acquire the bias of the object using an atomic operation. If this
 208   // fails we will go in to the runtime to revoke the object's bias.
 209   // Note that we first construct the presumed unbiased header so we
 210   // don't accidentally blow away another thread's valid bias.
 211   movl(swap_reg, saved_mark_addr);
 212   andl(swap_reg,
 213        markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
 214   if (need_tmp_reg) {
 215     push(tmp_reg);
 216   }
 217   get_thread(tmp_reg);
 218   orl(tmp_reg, swap_reg);
 219   if (os::is_MP()) {
 220     lock();
 221   }
 222   cmpxchgptr(tmp_reg, Address(obj_reg, 0));
 223   if (need_tmp_reg) {
 224     pop(tmp_reg);
 225   }
 226   // If the biasing toward our thread failed, this means that
 227   // another thread succeeded in biasing it toward itself and we
 228   // need to revoke that bias. The revocation will occur in the
 229   // interpreter runtime in the slow case.
 230   if (counters != NULL) {
 231     cond_inc32(Assembler::zero,
 232                ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
 233   }
 234   if (slow_case != NULL) {
 235     jcc(Assembler::notZero, *slow_case);
 236   }
 237   jmp(done);
 238 
 239   bind(try_rebias);
 240   // At this point we know the epoch has expired, meaning that the
 241   // current "bias owner", if any, is actually invalid. Under these
 242   // circumstances _only_, we are allowed to use the current header's
 243   // value as the comparison value when doing the cas to acquire the
 244   // bias in the current epoch. In other words, we allow transfer of
 245   // the bias from one thread to another directly in this situation.
 246   //
 247   // FIXME: due to a lack of registers we currently blow away the age
 248   // bits in this situation. Should attempt to preserve them.
 249   if (need_tmp_reg) {
 250     push(tmp_reg);
 251   }
 252   get_thread(tmp_reg);
 253   movl(swap_reg, klass_addr);
 254   orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset()));
 255   movl(swap_reg, saved_mark_addr);
 256   if (os::is_MP()) {
 257     lock();
 258   }
 259   cmpxchgptr(tmp_reg, Address(obj_reg, 0));
 260   if (need_tmp_reg) {
 261     pop(tmp_reg);
 262   }
 263   // If the biasing toward our thread failed, then another thread
 264   // succeeded in biasing it toward itself and we need to revoke that
 265   // bias. The revocation will occur in the runtime in the slow case.
 266   if (counters != NULL) {
 267     cond_inc32(Assembler::zero,
 268                ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
 269   }
 270   if (slow_case != NULL) {
 271     jcc(Assembler::notZero, *slow_case);
 272   }
 273   jmp(done);
 274 
 275   bind(try_revoke_bias);
 276   // The prototype mark in the klass doesn't have the bias bit set any
 277   // more, indicating that objects of this data type are not supposed
 278   // to be biased any more. We are going to try to reset the mark of
 279   // this object to the prototype value and fall through to the
 280   // CAS-based locking scheme. Note that if our CAS fails, it means
 281   // that another thread raced us for the privilege of revoking the
 282   // bias of this particular object, so it's okay to continue in the
 283   // normal locking code.
 284   //
 285   // FIXME: due to a lack of registers we currently blow away the age
 286   // bits in this situation. Should attempt to preserve them.
 287   movl(swap_reg, saved_mark_addr);
 288   if (need_tmp_reg) {
 289     push(tmp_reg);
 290   }
 291   movl(tmp_reg, klass_addr);
 292   movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset()));
 293   if (os::is_MP()) {
 294     lock();
 295   }
 296   cmpxchgptr(tmp_reg, Address(obj_reg, 0));
 297   if (need_tmp_reg) {
 298     pop(tmp_reg);
 299   }
 300   // Fall through to the normal CAS-based lock, because no matter what
 301   // the result of the above CAS, some thread must have succeeded in
 302   // removing the bias bit from the object's header.
 303   if (counters != NULL) {
 304     cond_inc32(Assembler::zero,
 305                ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
 306   }
 307 
 308   bind(cas_label);
 309 
 310   return null_check_offset;
 311 }
 312 void MacroAssembler::call_VM_leaf_base(address entry_point,
 313                                        int number_of_arguments) {
 314   call(RuntimeAddress(entry_point));
 315   increment(rsp, number_of_arguments * wordSize);
 316 }
 317 
 318 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 319   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 320 }
 321 
 322 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 323   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 324 }
 325 
 326 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 327   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 328 }
 329 
 330 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 331   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 332 }
 333 
 334 void MacroAssembler::extend_sign(Register hi, Register lo) {
 335   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 336   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 337     cdql();
 338   } else {
 339     movl(hi, lo);
 340     sarl(hi, 31);
 341   }
 342 }
 343 
 344 void MacroAssembler::jC2(Register tmp, Label& L) {
 345   // set parity bit if FPU flag C2 is set (via rax)
 346   save_rax(tmp);
 347   fwait(); fnstsw_ax();
 348   sahf();
 349   restore_rax(tmp);
 350   // branch
 351   jcc(Assembler::parity, L);
 352 }
 353 
 354 void MacroAssembler::jnC2(Register tmp, Label& L) {
 355   // set parity bit if FPU flag C2 is set (via rax)
 356   save_rax(tmp);
 357   fwait(); fnstsw_ax();
 358   sahf();
 359   restore_rax(tmp);
 360   // branch
 361   jcc(Assembler::noParity, L);
 362 }
 363 
 364 // 32bit can do a case table jump in one instruction but we no longer allow the base
 365 // to be installed in the Address class
 366 void MacroAssembler::jump(ArrayAddress entry) {
 367   jmp(as_Address(entry));
 368 }
 369 
 370 // Note: y_lo will be destroyed
 371 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 372   // Long compare for Java (semantics as described in JVM spec.)
 373   Label high, low, done;
 374 
 375   cmpl(x_hi, y_hi);
 376   jcc(Assembler::less, low);
 377   jcc(Assembler::greater, high);
 378   // x_hi is the return register
 379   xorl(x_hi, x_hi);
 380   cmpl(x_lo, y_lo);
 381   jcc(Assembler::below, low);
 382   jcc(Assembler::equal, done);
 383 
 384   bind(high);
 385   xorl(x_hi, x_hi);
 386   increment(x_hi);
 387   jmp(done);
 388 
 389   bind(low);
 390   xorl(x_hi, x_hi);
 391   decrementl(x_hi);
 392 
 393   bind(done);
 394 }
 395 
 396 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 397     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 398 }
 399 
 400 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 401   // leal(dst, as_Address(adr));
 402   // see note in movl as to why we must use a move
 403   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 404 }
 405 
 406 void MacroAssembler::leave() {
 407   mov(rsp, rbp);
 408   pop(rbp);
 409 }
 410 
 411 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 412   // Multiplication of two Java long values stored on the stack
 413   // as illustrated below. Result is in rdx:rax.
 414   //
 415   // rsp ---> [  ??  ] \               \
 416   //            ....    | y_rsp_offset  |
 417   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 418   //          [ y_hi ]                  | (in bytes)
 419   //            ....                    |
 420   //          [ x_lo ]                 /
 421   //          [ x_hi ]
 422   //            ....
 423   //
 424   // Basic idea: lo(result) = lo(x_lo * y_lo)
 425   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 426   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 427   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 428   Label quick;
 429   // load x_hi, y_hi and check if quick
 430   // multiplication is possible
 431   movl(rbx, x_hi);
 432   movl(rcx, y_hi);
 433   movl(rax, rbx);
 434   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 435   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 436   // do full multiplication
 437   // 1st step
 438   mull(y_lo);                                    // x_hi * y_lo
 439   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 440   // 2nd step
 441   movl(rax, x_lo);
 442   mull(rcx);                                     // x_lo * y_hi
 443   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 444   // 3rd step
 445   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 446   movl(rax, x_lo);
 447   mull(y_lo);                                    // x_lo * y_lo
 448   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 449 }
 450 
 451 void MacroAssembler::lneg(Register hi, Register lo) {
 452   negl(lo);
 453   adcl(hi, 0);
 454   negl(hi);
 455 }
 456 
 457 void MacroAssembler::lshl(Register hi, Register lo) {
 458   // Java shift left long support (semantics as described in JVM spec., p.305)
 459   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 460   // shift value is in rcx !
 461   assert(hi != rcx, "must not use rcx");
 462   assert(lo != rcx, "must not use rcx");
 463   const Register s = rcx;                        // shift count
 464   const int      n = BitsPerWord;
 465   Label L;
 466   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 467   cmpl(s, n);                                    // if (s < n)
 468   jcc(Assembler::less, L);                       // else (s >= n)
 469   movl(hi, lo);                                  // x := x << n
 470   xorl(lo, lo);
 471   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 472   bind(L);                                       // s (mod n) < n
 473   shldl(hi, lo);                                 // x := x << s
 474   shll(lo);
 475 }
 476 
 477 
 478 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 479   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 480   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 481   assert(hi != rcx, "must not use rcx");
 482   assert(lo != rcx, "must not use rcx");
 483   const Register s = rcx;                        // shift count
 484   const int      n = BitsPerWord;
 485   Label L;
 486   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 487   cmpl(s, n);                                    // if (s < n)
 488   jcc(Assembler::less, L);                       // else (s >= n)
 489   movl(lo, hi);                                  // x := x >> n
 490   if (sign_extension) sarl(hi, 31);
 491   else                xorl(hi, hi);
 492   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 493   bind(L);                                       // s (mod n) < n
 494   shrdl(lo, hi);                                 // x := x >> s
 495   if (sign_extension) sarl(hi);
 496   else                shrl(hi);
 497 }
 498 
 499 void MacroAssembler::movoop(Register dst, jobject obj) {
 500   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 501 }
 502 
 503 void MacroAssembler::movoop(Address dst, jobject obj) {
 504   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 505 }
 506 
 507 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 508   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 509 }
 510 
 511 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 512   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 513 }
 514 
 515 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
 516   if (src.is_lval()) {
 517     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 518   } else {
 519     movl(dst, as_Address(src));
 520   }
 521 }
 522 
 523 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 524   movl(as_Address(dst), src);
 525 }
 526 
 527 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 528   movl(dst, as_Address(src));
 529 }
 530 
 531 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 532 void MacroAssembler::movptr(Address dst, intptr_t src) {
 533   movl(dst, src);
 534 }
 535 
 536 
 537 void MacroAssembler::pop_callee_saved_registers() {
 538   pop(rcx);
 539   pop(rdx);
 540   pop(rdi);
 541   pop(rsi);
 542 }
 543 
 544 void MacroAssembler::pop_fTOS() {
 545   fld_d(Address(rsp, 0));
 546   addl(rsp, 2 * wordSize);
 547 }
 548 
 549 void MacroAssembler::push_callee_saved_registers() {
 550   push(rsi);
 551   push(rdi);
 552   push(rdx);
 553   push(rcx);
 554 }
 555 
 556 void MacroAssembler::push_fTOS() {
 557   subl(rsp, 2 * wordSize);
 558   fstp_d(Address(rsp, 0));
 559 }
 560 
 561 
 562 void MacroAssembler::pushoop(jobject obj) {
 563   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 564 }
 565 
 566 void MacroAssembler::pushklass(Metadata* obj) {
 567   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 568 }
 569 
 570 void MacroAssembler::pushptr(AddressLiteral src) {
 571   if (src.is_lval()) {
 572     push_literal32((int32_t)src.target(), src.rspec());
 573   } else {
 574     pushl(as_Address(src));
 575   }
 576 }
 577 
 578 void MacroAssembler::set_word_if_not_zero(Register dst) {
 579   xorl(dst, dst);
 580   set_byte_if_not_zero(dst);
 581 }
 582 
 583 static void pass_arg0(MacroAssembler* masm, Register arg) {
 584   masm->push(arg);
 585 }
 586 
 587 static void pass_arg1(MacroAssembler* masm, Register arg) {
 588   masm->push(arg);
 589 }
 590 
 591 static void pass_arg2(MacroAssembler* masm, Register arg) {
 592   masm->push(arg);
 593 }
 594 
 595 static void pass_arg3(MacroAssembler* masm, Register arg) {
 596   masm->push(arg);
 597 }
 598 
 599 #ifndef PRODUCT
 600 extern "C" void findpc(intptr_t x);
 601 #endif
 602 
 603 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 604   // In order to get locks to work, we need to fake a in_VM state
 605   JavaThread* thread = JavaThread::current();
 606   JavaThreadState saved_state = thread->thread_state();
 607   thread->set_thread_state(_thread_in_vm);
 608   if (ShowMessageBoxOnError) {
 609     JavaThread* thread = JavaThread::current();
 610     JavaThreadState saved_state = thread->thread_state();
 611     thread->set_thread_state(_thread_in_vm);
 612     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 613       ttyLocker ttyl;
 614       BytecodeCounter::print();
 615     }
 616     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 617     // This is the value of eip which points to where verify_oop will return.
 618     if (os::message_box(msg, "Execution stopped, print registers?")) {
 619       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 620       BREAKPOINT;
 621     }
 622   } else {
 623     ttyLocker ttyl;
 624     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
 625   }
 626   // Don't assert holding the ttyLock
 627     assert(false, err_msg("DEBUG MESSAGE: %s", msg));
 628   ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 629 }
 630 
 631 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 632   ttyLocker ttyl;
 633   FlagSetting fs(Debugging, true);
 634   tty->print_cr("eip = 0x%08x", eip);
 635 #ifndef PRODUCT
 636   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 637     tty->cr();
 638     findpc(eip);
 639     tty->cr();
 640   }
 641 #endif
 642 #define PRINT_REG(rax) \
 643   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 644   PRINT_REG(rax);
 645   PRINT_REG(rbx);
 646   PRINT_REG(rcx);
 647   PRINT_REG(rdx);
 648   PRINT_REG(rdi);
 649   PRINT_REG(rsi);
 650   PRINT_REG(rbp);
 651   PRINT_REG(rsp);
 652 #undef PRINT_REG
 653   // Print some words near top of staack.
 654   int* dump_sp = (int*) rsp;
 655   for (int col1 = 0; col1 < 8; col1++) {
 656     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 657     os::print_location(tty, *dump_sp++);
 658   }
 659   for (int row = 0; row < 16; row++) {
 660     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 661     for (int col = 0; col < 8; col++) {
 662       tty->print(" 0x%08x", *dump_sp++);
 663     }
 664     tty->cr();
 665   }
 666   // Print some instructions around pc:
 667   Disassembler::decode((address)eip-64, (address)eip);
 668   tty->print_cr("--------");
 669   Disassembler::decode((address)eip, (address)eip+32);
 670 }
 671 
 672 void MacroAssembler::stop(const char* msg) {
 673   ExternalAddress message((address)msg);
 674   // push address of message
 675   pushptr(message.addr());
 676   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 677   pusha();                                            // push registers
 678   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 679   hlt();
 680 }
 681 
 682 void MacroAssembler::warn(const char* msg) {
 683   push_CPU_state();
 684 
 685   ExternalAddress message((address) msg);
 686   // push address of message
 687   pushptr(message.addr());
 688 
 689   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 690   addl(rsp, wordSize);       // discard argument
 691   pop_CPU_state();
 692 }
 693 
 694 void MacroAssembler::print_state() {
 695   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 696   pusha();                                            // push registers
 697 
 698   push_CPU_state();
 699   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 700   pop_CPU_state();
 701 
 702   popa();
 703   addl(rsp, wordSize);
 704 }
 705 
 706 #else // _LP64
 707 
 708 // 64 bit versions
 709 
 710 Address MacroAssembler::as_Address(AddressLiteral adr) {
 711   // amd64 always does this as a pc-rel
 712   // we can be absolute or disp based on the instruction type
 713   // jmp/call are displacements others are absolute
 714   assert(!adr.is_lval(), "must be rval");
 715   assert(reachable(adr), "must be");
 716   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 717 
 718 }
 719 
 720 Address MacroAssembler::as_Address(ArrayAddress adr) {
 721   AddressLiteral base = adr.base();
 722   lea(rscratch1, base);
 723   Address index = adr.index();
 724   assert(index._disp == 0, "must not have disp"); // maybe it can?
 725   Address array(rscratch1, index._index, index._scale, index._disp);
 726   return array;
 727 }
 728 
 729 int MacroAssembler::biased_locking_enter(Register lock_reg,
 730                                          Register obj_reg,
 731                                          Register swap_reg,
 732                                          Register tmp_reg,
 733                                          bool swap_reg_contains_mark,
 734                                          Label& done,
 735                                          Label* slow_case,
 736                                          BiasedLockingCounters* counters) {
 737   assert(UseBiasedLocking, "why call this otherwise?");
 738   assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
 739   assert(tmp_reg != noreg, "tmp_reg must be supplied");
 740   assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
 741   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
 742   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
 743   Address saved_mark_addr(lock_reg, 0);
 744 
 745   if (PrintBiasedLockingStatistics && counters == NULL)
 746     counters = BiasedLocking::counters();
 747 
 748   // Biased locking
 749   // See whether the lock is currently biased toward our thread and
 750   // whether the epoch is still valid
 751   // Note that the runtime guarantees sufficient alignment of JavaThread
 752   // pointers to allow age to be placed into low bits
 753   // First check to see whether biasing is even enabled for this object
 754   Label cas_label;
 755   int null_check_offset = -1;
 756   if (!swap_reg_contains_mark) {
 757     null_check_offset = offset();
 758     movq(swap_reg, mark_addr);
 759   }
 760   movq(tmp_reg, swap_reg);
 761   andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
 762   cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
 763   jcc(Assembler::notEqual, cas_label);
 764   // The bias pattern is present in the object's header. Need to check
 765   // whether the bias owner and the epoch are both still current.
 766   load_prototype_header(tmp_reg, obj_reg);
 767   orq(tmp_reg, r15_thread);
 768   xorq(tmp_reg, swap_reg);
 769   andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
 770   if (counters != NULL) {
 771     cond_inc32(Assembler::zero,
 772                ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
 773   }
 774   jcc(Assembler::equal, done);
 775 
 776   Label try_revoke_bias;
 777   Label try_rebias;
 778 
 779   // At this point we know that the header has the bias pattern and
 780   // that we are not the bias owner in the current epoch. We need to
 781   // figure out more details about the state of the header in order to
 782   // know what operations can be legally performed on the object's
 783   // header.
 784 
 785   // If the low three bits in the xor result aren't clear, that means
 786   // the prototype header is no longer biased and we have to revoke
 787   // the bias on this object.
 788   testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
 789   jcc(Assembler::notZero, try_revoke_bias);
 790 
 791   // Biasing is still enabled for this data type. See whether the
 792   // epoch of the current bias is still valid, meaning that the epoch
 793   // bits of the mark word are equal to the epoch bits of the
 794   // prototype header. (Note that the prototype header's epoch bits
 795   // only change at a safepoint.) If not, attempt to rebias the object
 796   // toward the current thread. Note that we must be absolutely sure
 797   // that the current epoch is invalid in order to do this because
 798   // otherwise the manipulations it performs on the mark word are
 799   // illegal.
 800   testq(tmp_reg, markOopDesc::epoch_mask_in_place);
 801   jcc(Assembler::notZero, try_rebias);
 802 
 803   // The epoch of the current bias is still valid but we know nothing
 804   // about the owner; it might be set or it might be clear. Try to
 805   // acquire the bias of the object using an atomic operation. If this
 806   // fails we will go in to the runtime to revoke the object's bias.
 807   // Note that we first construct the presumed unbiased header so we
 808   // don't accidentally blow away another thread's valid bias.
 809   andq(swap_reg,
 810        markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
 811   movq(tmp_reg, swap_reg);
 812   orq(tmp_reg, r15_thread);
 813   if (os::is_MP()) {
 814     lock();
 815   }
 816   cmpxchgq(tmp_reg, Address(obj_reg, 0));
 817   // If the biasing toward our thread failed, this means that
 818   // another thread succeeded in biasing it toward itself and we
 819   // need to revoke that bias. The revocation will occur in the
 820   // interpreter runtime in the slow case.
 821   if (counters != NULL) {
 822     cond_inc32(Assembler::zero,
 823                ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
 824   }
 825   if (slow_case != NULL) {
 826     jcc(Assembler::notZero, *slow_case);
 827   }
 828   jmp(done);
 829 
 830   bind(try_rebias);
 831   // At this point we know the epoch has expired, meaning that the
 832   // current "bias owner", if any, is actually invalid. Under these
 833   // circumstances _only_, we are allowed to use the current header's
 834   // value as the comparison value when doing the cas to acquire the
 835   // bias in the current epoch. In other words, we allow transfer of
 836   // the bias from one thread to another directly in this situation.
 837   //
 838   // FIXME: due to a lack of registers we currently blow away the age
 839   // bits in this situation. Should attempt to preserve them.
 840   load_prototype_header(tmp_reg, obj_reg);
 841   orq(tmp_reg, r15_thread);
 842   if (os::is_MP()) {
 843     lock();
 844   }
 845   cmpxchgq(tmp_reg, Address(obj_reg, 0));
 846   // If the biasing toward our thread failed, then another thread
 847   // succeeded in biasing it toward itself and we need to revoke that
 848   // bias. The revocation will occur in the runtime in the slow case.
 849   if (counters != NULL) {
 850     cond_inc32(Assembler::zero,
 851                ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
 852   }
 853   if (slow_case != NULL) {
 854     jcc(Assembler::notZero, *slow_case);
 855   }
 856   jmp(done);
 857 
 858   bind(try_revoke_bias);
 859   // The prototype mark in the klass doesn't have the bias bit set any
 860   // more, indicating that objects of this data type are not supposed
 861   // to be biased any more. We are going to try to reset the mark of
 862   // this object to the prototype value and fall through to the
 863   // CAS-based locking scheme. Note that if our CAS fails, it means
 864   // that another thread raced us for the privilege of revoking the
 865   // bias of this particular object, so it's okay to continue in the
 866   // normal locking code.
 867   //
 868   // FIXME: due to a lack of registers we currently blow away the age
 869   // bits in this situation. Should attempt to preserve them.
 870   load_prototype_header(tmp_reg, obj_reg);
 871   if (os::is_MP()) {
 872     lock();
 873   }
 874   cmpxchgq(tmp_reg, Address(obj_reg, 0));
 875   // Fall through to the normal CAS-based lock, because no matter what
 876   // the result of the above CAS, some thread must have succeeded in
 877   // removing the bias bit from the object's header.
 878   if (counters != NULL) {
 879     cond_inc32(Assembler::zero,
 880                ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
 881   }
 882 
 883   bind(cas_label);
 884 
 885   return null_check_offset;
 886 }
 887 
 888 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 889   Label L, E;
 890 
 891 #ifdef _WIN64
 892   // Windows always allocates space for it's register args
 893   assert(num_args <= 4, "only register arguments supported");
 894   subq(rsp,  frame::arg_reg_save_area_bytes);
 895 #endif
 896 
 897   // Align stack if necessary
 898   testl(rsp, 15);
 899   jcc(Assembler::zero, L);
 900 
 901   subq(rsp, 8);
 902   {
 903     call(RuntimeAddress(entry_point));
 904   }
 905   addq(rsp, 8);
 906   jmp(E);
 907 
 908   bind(L);
 909   {
 910     call(RuntimeAddress(entry_point));
 911   }
 912 
 913   bind(E);
 914 
 915 #ifdef _WIN64
 916   // restore stack pointer
 917   addq(rsp, frame::arg_reg_save_area_bytes);
 918 #endif
 919 
 920 }
 921 
 922 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 923   assert(!src2.is_lval(), "should use cmpptr");
 924 
 925   if (reachable(src2)) {
 926     cmpq(src1, as_Address(src2));
 927   } else {
 928     lea(rscratch1, src2);
 929     Assembler::cmpq(src1, Address(rscratch1, 0));
 930   }
 931 }
 932 
 933 int MacroAssembler::corrected_idivq(Register reg) {
 934   // Full implementation of Java ldiv and lrem; checks for special
 935   // case as described in JVM spec., p.243 & p.271.  The function
 936   // returns the (pc) offset of the idivl instruction - may be needed
 937   // for implicit exceptions.
 938   //
 939   //         normal case                           special case
 940   //
 941   // input : rax: dividend                         min_long
 942   //         reg: divisor   (may not be eax/edx)   -1
 943   //
 944   // output: rax: quotient  (= rax idiv reg)       min_long
 945   //         rdx: remainder (= rax irem reg)       0
 946   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 947   static const int64_t min_long = 0x8000000000000000;
 948   Label normal_case, special_case;
 949 
 950   // check for special case
 951   cmp64(rax, ExternalAddress((address) &min_long));
 952   jcc(Assembler::notEqual, normal_case);
 953   xorl(rdx, rdx); // prepare rdx for possible special case (where
 954                   // remainder = 0)
 955   cmpq(reg, -1);
 956   jcc(Assembler::equal, special_case);
 957 
 958   // handle normal case
 959   bind(normal_case);
 960   cdqq();
 961   int idivq_offset = offset();
 962   idivq(reg);
 963 
 964   // normal and special case exit
 965   bind(special_case);
 966 
 967   return idivq_offset;
 968 }
 969 
 970 void MacroAssembler::decrementq(Register reg, int value) {
 971   if (value == min_jint) { subq(reg, value); return; }
 972   if (value <  0) { incrementq(reg, -value); return; }
 973   if (value == 0) {                        ; return; }
 974   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 975   /* else */      { subq(reg, value)       ; return; }
 976 }
 977 
 978 void MacroAssembler::decrementq(Address dst, int value) {
 979   if (value == min_jint) { subq(dst, value); return; }
 980   if (value <  0) { incrementq(dst, -value); return; }
 981   if (value == 0) {                        ; return; }
 982   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 983   /* else */      { subq(dst, value)       ; return; }
 984 }
 985 
 986 void MacroAssembler::incrementq(Register reg, int value) {
 987   if (value == min_jint) { addq(reg, value); return; }
 988   if (value <  0) { decrementq(reg, -value); return; }
 989   if (value == 0) {                        ; return; }
 990   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 991   /* else */      { addq(reg, value)       ; return; }
 992 }
 993 
 994 void MacroAssembler::incrementq(Address dst, int value) {
 995   if (value == min_jint) { addq(dst, value); return; }
 996   if (value <  0) { decrementq(dst, -value); return; }
 997   if (value == 0) {                        ; return; }
 998   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 999   /* else */      { addq(dst, value)       ; return; }
1000 }
1001 
1002 // 32bit can do a case table jump in one instruction but we no longer allow the base
1003 // to be installed in the Address class
1004 void MacroAssembler::jump(ArrayAddress entry) {
1005   lea(rscratch1, entry.base());
1006   Address dispatch = entry.index();
1007   assert(dispatch._base == noreg, "must be");
1008   dispatch._base = rscratch1;
1009   jmp(dispatch);
1010 }
1011 
1012 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
1013   ShouldNotReachHere(); // 64bit doesn't use two regs
1014   cmpq(x_lo, y_lo);
1015 }
1016 
1017 void MacroAssembler::lea(Register dst, AddressLiteral src) {
1018     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
1019 }
1020 
1021 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
1022   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
1023   movptr(dst, rscratch1);
1024 }
1025 
1026 void MacroAssembler::leave() {
1027   // %%% is this really better? Why not on 32bit too?
1028   emit_int8((unsigned char)0xC9); // LEAVE
1029 }
1030 
1031 void MacroAssembler::lneg(Register hi, Register lo) {
1032   ShouldNotReachHere(); // 64bit doesn't use two regs
1033   negq(lo);
1034 }
1035 
1036 void MacroAssembler::movoop(Register dst, jobject obj) {
1037   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
1038 }
1039 
1040 void MacroAssembler::movoop(Address dst, jobject obj) {
1041   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
1042   movq(dst, rscratch1);
1043 }
1044 
1045 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
1046   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
1047 }
1048 
1049 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
1050   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
1051   movq(dst, rscratch1);
1052 }
1053 
1054 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
1055   if (src.is_lval()) {
1056     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
1057   } else {
1058     if (reachable(src)) {
1059       movq(dst, as_Address(src));
1060     } else {
1061       lea(rscratch1, src);
1062       movq(dst, Address(rscratch1,0));
1063     }
1064   }
1065 }
1066 
1067 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
1068   movq(as_Address(dst), src);
1069 }
1070 
1071 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
1072   movq(dst, as_Address(src));
1073 }
1074 
1075 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
1076 void MacroAssembler::movptr(Address dst, intptr_t src) {
1077   mov64(rscratch1, src);
1078   movq(dst, rscratch1);
1079 }
1080 
1081 // These are mostly for initializing NULL
1082 void MacroAssembler::movptr(Address dst, int32_t src) {
1083   movslq(dst, src);
1084 }
1085 
1086 void MacroAssembler::movptr(Register dst, int32_t src) {
1087   mov64(dst, (intptr_t)src);
1088 }
1089 
1090 void MacroAssembler::pushoop(jobject obj) {
1091   movoop(rscratch1, obj);
1092   push(rscratch1);
1093 }
1094 
1095 void MacroAssembler::pushklass(Metadata* obj) {
1096   mov_metadata(rscratch1, obj);
1097   push(rscratch1);
1098 }
1099 
1100 void MacroAssembler::pushptr(AddressLiteral src) {
1101   lea(rscratch1, src);
1102   if (src.is_lval()) {
1103     push(rscratch1);
1104   } else {
1105     pushq(Address(rscratch1, 0));
1106   }
1107 }
1108 
1109 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
1110                                            bool clear_pc) {
1111   // we must set sp to zero to clear frame
1112   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
1113   // must clear fp, so that compiled frames are not confused; it is
1114   // possible that we need it only for debugging
1115   if (clear_fp) {
1116     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
1117   }
1118 
1119   if (clear_pc) {
1120     movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
1121   }
1122 }
1123 
1124 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
1125                                          Register last_java_fp,
1126                                          address  last_java_pc) {
1127   // determine last_java_sp register
1128   if (!last_java_sp->is_valid()) {
1129     last_java_sp = rsp;
1130   }
1131 
1132   // last_java_fp is optional
1133   if (last_java_fp->is_valid()) {
1134     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
1135            last_java_fp);
1136   }
1137 
1138   // last_java_pc is optional
1139   if (last_java_pc != NULL) {
1140     Address java_pc(r15_thread,
1141                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
1142     lea(rscratch1, InternalAddress(last_java_pc));
1143     movptr(java_pc, rscratch1);
1144   }
1145 
1146   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
1147 }
1148 
1149 static void pass_arg0(MacroAssembler* masm, Register arg) {
1150   if (c_rarg0 != arg ) {
1151     masm->mov(c_rarg0, arg);
1152   }
1153 }
1154 
1155 static void pass_arg1(MacroAssembler* masm, Register arg) {
1156   if (c_rarg1 != arg ) {
1157     masm->mov(c_rarg1, arg);
1158   }
1159 }
1160 
1161 static void pass_arg2(MacroAssembler* masm, Register arg) {
1162   if (c_rarg2 != arg ) {
1163     masm->mov(c_rarg2, arg);
1164   }
1165 }
1166 
1167 static void pass_arg3(MacroAssembler* masm, Register arg) {
1168   if (c_rarg3 != arg ) {
1169     masm->mov(c_rarg3, arg);
1170   }
1171 }
1172 
1173 void MacroAssembler::stop(const char* msg) {
1174   address rip = pc();
1175   pusha(); // get regs on stack
1176   lea(c_rarg0, ExternalAddress((address) msg));
1177   lea(c_rarg1, InternalAddress(rip));
1178   movq(c_rarg2, rsp); // pass pointer to regs array
1179   andq(rsp, -16); // align stack as required by ABI
1180   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
1181   hlt();
1182 }
1183 
1184 void MacroAssembler::warn(const char* msg) {
1185   push(rbp);
1186   movq(rbp, rsp);
1187   andq(rsp, -16);     // align stack as required by push_CPU_state and call
1188   push_CPU_state();   // keeps alignment at 16 bytes
1189   lea(c_rarg0, ExternalAddress((address) msg));
1190   call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
1191   pop_CPU_state();
1192   mov(rsp, rbp);
1193   pop(rbp);
1194 }
1195 
1196 void MacroAssembler::print_state() {
1197   address rip = pc();
1198   pusha();            // get regs on stack
1199   push(rbp);
1200   movq(rbp, rsp);
1201   andq(rsp, -16);     // align stack as required by push_CPU_state and call
1202   push_CPU_state();   // keeps alignment at 16 bytes
1203 
1204   lea(c_rarg0, InternalAddress(rip));
1205   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
1206   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
1207 
1208   pop_CPU_state();
1209   mov(rsp, rbp);
1210   pop(rbp);
1211   popa();
1212 }
1213 
1214 #ifndef PRODUCT
1215 extern "C" void findpc(intptr_t x);
1216 #endif
1217 
1218 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
1219   // In order to get locks to work, we need to fake a in_VM state
1220   if (ShowMessageBoxOnError) {
1221     JavaThread* thread = JavaThread::current();
1222     JavaThreadState saved_state = thread->thread_state();
1223     thread->set_thread_state(_thread_in_vm);
1224 #ifndef PRODUCT
1225     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
1226       ttyLocker ttyl;
1227       BytecodeCounter::print();
1228     }
1229 #endif
1230     // To see where a verify_oop failed, get $ebx+40/X for this frame.
1231     // XXX correct this offset for amd64
1232     // This is the value of eip which points to where verify_oop will return.
1233     if (os::message_box(msg, "Execution stopped, print registers?")) {
1234       print_state64(pc, regs);
1235       BREAKPOINT;
1236       assert(false, "start up GDB");
1237     }
1238     ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
1239   } else {
1240     ttyLocker ttyl;
1241     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
1242                     msg);
1243     assert(false, err_msg("DEBUG MESSAGE: %s", msg));
1244   }
1245 }
1246 
1247 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
1248   ttyLocker ttyl;
1249   FlagSetting fs(Debugging, true);
1250   tty->print_cr("rip = 0x%016lx", pc);
1251 #ifndef PRODUCT
1252   tty->cr();
1253   findpc(pc);
1254   tty->cr();
1255 #endif
1256 #define PRINT_REG(rax, value) \
1257   { tty->print("%s = ", #rax); os::print_location(tty, value); }
1258   PRINT_REG(rax, regs[15]);
1259   PRINT_REG(rbx, regs[12]);
1260   PRINT_REG(rcx, regs[14]);
1261   PRINT_REG(rdx, regs[13]);
1262   PRINT_REG(rdi, regs[8]);
1263   PRINT_REG(rsi, regs[9]);
1264   PRINT_REG(rbp, regs[10]);
1265   PRINT_REG(rsp, regs[11]);
1266   PRINT_REG(r8 , regs[7]);
1267   PRINT_REG(r9 , regs[6]);
1268   PRINT_REG(r10, regs[5]);
1269   PRINT_REG(r11, regs[4]);
1270   PRINT_REG(r12, regs[3]);
1271   PRINT_REG(r13, regs[2]);
1272   PRINT_REG(r14, regs[1]);
1273   PRINT_REG(r15, regs[0]);
1274 #undef PRINT_REG
1275   // Print some words near top of staack.
1276   int64_t* rsp = (int64_t*) regs[11];
1277   int64_t* dump_sp = rsp;
1278   for (int col1 = 0; col1 < 8; col1++) {
1279     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
1280     os::print_location(tty, *dump_sp++);
1281   }
1282   for (int row = 0; row < 25; row++) {
1283     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
1284     for (int col = 0; col < 4; col++) {
1285       tty->print(" 0x%016lx", *dump_sp++);
1286     }
1287     tty->cr();
1288   }
1289   // Print some instructions around pc:
1290   Disassembler::decode((address)pc-64, (address)pc);
1291   tty->print_cr("--------");
1292   Disassembler::decode((address)pc, (address)pc+32);
1293 }
1294 
1295 #endif // _LP64
1296 
1297 // Now versions that are common to 32/64 bit
1298 
1299 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1300   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1301 }
1302 
1303 void MacroAssembler::addptr(Register dst, Register src) {
1304   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1305 }
1306 
1307 void MacroAssembler::addptr(Address dst, Register src) {
1308   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1309 }
1310 
1311 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
1312   if (reachable(src)) {
1313     Assembler::addsd(dst, as_Address(src));
1314   } else {
1315     lea(rscratch1, src);
1316     Assembler::addsd(dst, Address(rscratch1, 0));
1317   }
1318 }
1319 
1320 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
1321   if (reachable(src)) {
1322     addss(dst, as_Address(src));
1323   } else {
1324     lea(rscratch1, src);
1325     addss(dst, Address(rscratch1, 0));
1326   }
1327 }
1328 
1329 void MacroAssembler::align(int modulus) {
1330   if (offset() % modulus != 0) {
1331     nop(modulus - (offset() % modulus));
1332   }
1333 }
1334 
1335 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
1336   // Used in sign-masking with aligned address.
1337   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1338   if (reachable(src)) {
1339     Assembler::andpd(dst, as_Address(src));
1340   } else {
1341     lea(rscratch1, src);
1342     Assembler::andpd(dst, Address(rscratch1, 0));
1343   }
1344 }
1345 
1346 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1347   // Used in sign-masking with aligned address.
1348   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1349   if (reachable(src)) {
1350     Assembler::andps(dst, as_Address(src));
1351   } else {
1352     lea(rscratch1, src);
1353     Assembler::andps(dst, Address(rscratch1, 0));
1354   }
1355 }
1356 
1357 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1358   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1359 }
1360 
1361 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
1362   pushf();
1363   if (os::is_MP())
1364     lock();
1365   incrementl(counter_addr);
1366   popf();
1367 }
1368 
1369 // Writes to stack successive pages until offset reached to check for
1370 // stack overflow + shadow pages.  This clobbers tmp.
1371 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1372   movptr(tmp, rsp);
1373   // Bang stack for total size given plus shadow page size.
1374   // Bang one page at a time because large size can bang beyond yellow and
1375   // red zones.
1376   Label loop;
1377   bind(loop);
1378   movl(Address(tmp, (-os::vm_page_size())), size );
1379   subptr(tmp, os::vm_page_size());
1380   subl(size, os::vm_page_size());
1381   jcc(Assembler::greater, loop);
1382 
1383   // Bang down shadow pages too.
1384   // The -1 because we already subtracted 1 page.
1385   for (int i = 0; i< StackShadowPages-1; i++) {
1386     // this could be any sized move but this is can be a debugging crumb
1387     // so the bigger the better.
1388     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1389   }
1390 }
1391 
1392 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1393   assert(UseBiasedLocking, "why call this otherwise?");
1394 
1395   // Check for biased locking unlock case, which is a no-op
1396   // Note: we do not have to check the thread ID for two reasons.
1397   // First, the interpreter checks for IllegalMonitorStateException at
1398   // a higher level. Second, if the bias was revoked while we held the
1399   // lock, the object could not be rebiased toward another thread, so
1400   // the bias bit would be clear.
1401   movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1402   andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1403   cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1404   jcc(Assembler::equal, done);
1405 }
1406 
1407 void MacroAssembler::c2bool(Register x) {
1408   // implements x == 0 ? 0 : 1
1409   // note: must only look at least-significant byte of x
1410   //       since C-style booleans are stored in one byte
1411   //       only! (was bug)
1412   andl(x, 0xFF);
1413   setb(Assembler::notZero, x);
1414 }
1415 
1416 // Wouldn't need if AddressLiteral version had new name
1417 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1418   Assembler::call(L, rtype);
1419 }
1420 
1421 void MacroAssembler::call(Register entry) {
1422   Assembler::call(entry);
1423 }
1424 
1425 void MacroAssembler::call(AddressLiteral entry) {
1426   if (reachable(entry)) {
1427     Assembler::call_literal(entry.target(), entry.rspec());
1428   } else {
1429     lea(rscratch1, entry);
1430     Assembler::call(rscratch1);
1431   }
1432 }
1433 
1434 void MacroAssembler::ic_call(address entry) {
1435   RelocationHolder rh = virtual_call_Relocation::spec(pc());
1436   movptr(rax, (intptr_t)Universe::non_oop_word());
1437   call(AddressLiteral(entry, rh));
1438 }
1439 
1440 // Implementation of call_VM versions
1441 
1442 void MacroAssembler::call_VM(Register oop_result,
1443                              address entry_point,
1444                              bool check_exceptions) {
1445   Label C, E;
1446   call(C, relocInfo::none);
1447   jmp(E);
1448 
1449   bind(C);
1450   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1451   ret(0);
1452 
1453   bind(E);
1454 }
1455 
1456 void MacroAssembler::call_VM(Register oop_result,
1457                              address entry_point,
1458                              Register arg_1,
1459                              bool check_exceptions) {
1460   Label C, E;
1461   call(C, relocInfo::none);
1462   jmp(E);
1463 
1464   bind(C);
1465   pass_arg1(this, arg_1);
1466   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1467   ret(0);
1468 
1469   bind(E);
1470 }
1471 
1472 void MacroAssembler::call_VM(Register oop_result,
1473                              address entry_point,
1474                              Register arg_1,
1475                              Register arg_2,
1476                              bool check_exceptions) {
1477   Label C, E;
1478   call(C, relocInfo::none);
1479   jmp(E);
1480 
1481   bind(C);
1482 
1483   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1484 
1485   pass_arg2(this, arg_2);
1486   pass_arg1(this, arg_1);
1487   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1488   ret(0);
1489 
1490   bind(E);
1491 }
1492 
1493 void MacroAssembler::call_VM(Register oop_result,
1494                              address entry_point,
1495                              Register arg_1,
1496                              Register arg_2,
1497                              Register arg_3,
1498                              bool check_exceptions) {
1499   Label C, E;
1500   call(C, relocInfo::none);
1501   jmp(E);
1502 
1503   bind(C);
1504 
1505   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1506   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1507   pass_arg3(this, arg_3);
1508 
1509   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1510   pass_arg2(this, arg_2);
1511 
1512   pass_arg1(this, arg_1);
1513   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1514   ret(0);
1515 
1516   bind(E);
1517 }
1518 
1519 void MacroAssembler::call_VM(Register oop_result,
1520                              Register last_java_sp,
1521                              address entry_point,
1522                              int number_of_arguments,
1523                              bool check_exceptions) {
1524   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1525   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1526 }
1527 
1528 void MacroAssembler::call_VM(Register oop_result,
1529                              Register last_java_sp,
1530                              address entry_point,
1531                              Register arg_1,
1532                              bool check_exceptions) {
1533   pass_arg1(this, arg_1);
1534   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1535 }
1536 
1537 void MacroAssembler::call_VM(Register oop_result,
1538                              Register last_java_sp,
1539                              address entry_point,
1540                              Register arg_1,
1541                              Register arg_2,
1542                              bool check_exceptions) {
1543 
1544   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1545   pass_arg2(this, arg_2);
1546   pass_arg1(this, arg_1);
1547   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1548 }
1549 
1550 void MacroAssembler::call_VM(Register oop_result,
1551                              Register last_java_sp,
1552                              address entry_point,
1553                              Register arg_1,
1554                              Register arg_2,
1555                              Register arg_3,
1556                              bool check_exceptions) {
1557   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1558   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1559   pass_arg3(this, arg_3);
1560   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1561   pass_arg2(this, arg_2);
1562   pass_arg1(this, arg_1);
1563   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1564 }
1565 
1566 void MacroAssembler::super_call_VM(Register oop_result,
1567                                    Register last_java_sp,
1568                                    address entry_point,
1569                                    int number_of_arguments,
1570                                    bool check_exceptions) {
1571   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1572   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1573 }
1574 
1575 void MacroAssembler::super_call_VM(Register oop_result,
1576                                    Register last_java_sp,
1577                                    address entry_point,
1578                                    Register arg_1,
1579                                    bool check_exceptions) {
1580   pass_arg1(this, arg_1);
1581   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1582 }
1583 
1584 void MacroAssembler::super_call_VM(Register oop_result,
1585                                    Register last_java_sp,
1586                                    address entry_point,
1587                                    Register arg_1,
1588                                    Register arg_2,
1589                                    bool check_exceptions) {
1590 
1591   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1592   pass_arg2(this, arg_2);
1593   pass_arg1(this, arg_1);
1594   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1595 }
1596 
1597 void MacroAssembler::super_call_VM(Register oop_result,
1598                                    Register last_java_sp,
1599                                    address entry_point,
1600                                    Register arg_1,
1601                                    Register arg_2,
1602                                    Register arg_3,
1603                                    bool check_exceptions) {
1604   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1605   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1606   pass_arg3(this, arg_3);
1607   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1608   pass_arg2(this, arg_2);
1609   pass_arg1(this, arg_1);
1610   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1611 }
1612 
1613 void MacroAssembler::call_VM_base(Register oop_result,
1614                                   Register java_thread,
1615                                   Register last_java_sp,
1616                                   address  entry_point,
1617                                   int      number_of_arguments,
1618                                   bool     check_exceptions) {
1619   // determine java_thread register
1620   if (!java_thread->is_valid()) {
1621 #ifdef _LP64
1622     java_thread = r15_thread;
1623 #else
1624     java_thread = rdi;
1625     get_thread(java_thread);
1626 #endif // LP64
1627   }
1628   // determine last_java_sp register
1629   if (!last_java_sp->is_valid()) {
1630     last_java_sp = rsp;
1631   }
1632   // debugging support
1633   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
1634   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1635 #ifdef ASSERT
1636   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1637   // r12 is the heapbase.
1638   LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1639 #endif // ASSERT
1640 
1641   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
1642   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1643 
1644   // push java thread (becomes first argument of C function)
1645 
1646   NOT_LP64(push(java_thread); number_of_arguments++);
1647   LP64_ONLY(mov(c_rarg0, r15_thread));
1648 
1649   // set last Java frame before call
1650   assert(last_java_sp != rbp, "can't use ebp/rbp");
1651 
1652   // Only interpreter should have to set fp
1653   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
1654 
1655   // do the call, remove parameters
1656   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1657 
1658   // restore the thread (cannot use the pushed argument since arguments
1659   // may be overwritten by C code generated by an optimizing compiler);
1660   // however can use the register value directly if it is callee saved.
1661   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1662     // rdi & rsi (also r15) are callee saved -> nothing to do
1663 #ifdef ASSERT
1664     guarantee(java_thread != rax, "change this code");
1665     push(rax);
1666     { Label L;
1667       get_thread(rax);
1668       cmpptr(java_thread, rax);
1669       jcc(Assembler::equal, L);
1670       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1671       bind(L);
1672     }
1673     pop(rax);
1674 #endif
1675   } else {
1676     get_thread(java_thread);
1677   }
1678   // reset last Java frame
1679   // Only interpreter should have to clear fp
1680   reset_last_Java_frame(java_thread, true, false);
1681 
1682 #ifndef CC_INTERP
1683    // C++ interp handles this in the interpreter
1684   check_and_handle_popframe(java_thread);
1685   check_and_handle_earlyret(java_thread);
1686 #endif /* CC_INTERP */
1687 
1688   if (check_exceptions) {
1689     // check for pending exceptions (java_thread is set upon return)
1690     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
1691 #ifndef _LP64
1692     jump_cc(Assembler::notEqual,
1693             RuntimeAddress(StubRoutines::forward_exception_entry()));
1694 #else
1695     // This used to conditionally jump to forward_exception however it is
1696     // possible if we relocate that the branch will not reach. So we must jump
1697     // around so we can always reach
1698 
1699     Label ok;
1700     jcc(Assembler::equal, ok);
1701     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1702     bind(ok);
1703 #endif // LP64
1704   }
1705 
1706   // get oop result if there is one and reset the value in the thread
1707   if (oop_result->is_valid()) {
1708     get_vm_result(oop_result, java_thread);
1709   }
1710 }
1711 
1712 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1713 
1714   // Calculate the value for last_Java_sp
1715   // somewhat subtle. call_VM does an intermediate call
1716   // which places a return address on the stack just under the
1717   // stack pointer as the user finsihed with it. This allows
1718   // use to retrieve last_Java_pc from last_Java_sp[-1].
1719   // On 32bit we then have to push additional args on the stack to accomplish
1720   // the actual requested call. On 64bit call_VM only can use register args
1721   // so the only extra space is the return address that call_VM created.
1722   // This hopefully explains the calculations here.
1723 
1724 #ifdef _LP64
1725   // We've pushed one address, correct last_Java_sp
1726   lea(rax, Address(rsp, wordSize));
1727 #else
1728   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1729 #endif // LP64
1730 
1731   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1732 
1733 }
1734 
1735 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1736   call_VM_leaf_base(entry_point, number_of_arguments);
1737 }
1738 
1739 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1740   pass_arg0(this, arg_0);
1741   call_VM_leaf(entry_point, 1);
1742 }
1743 
1744 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1745 
1746   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1747   pass_arg1(this, arg_1);
1748   pass_arg0(this, arg_0);
1749   call_VM_leaf(entry_point, 2);
1750 }
1751 
1752 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1753   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1754   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1755   pass_arg2(this, arg_2);
1756   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1757   pass_arg1(this, arg_1);
1758   pass_arg0(this, arg_0);
1759   call_VM_leaf(entry_point, 3);
1760 }
1761 
1762 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1763   pass_arg0(this, arg_0);
1764   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1765 }
1766 
1767 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1768 
1769   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1770   pass_arg1(this, arg_1);
1771   pass_arg0(this, arg_0);
1772   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1773 }
1774 
1775 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1776   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1777   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1778   pass_arg2(this, arg_2);
1779   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1780   pass_arg1(this, arg_1);
1781   pass_arg0(this, arg_0);
1782   MacroAssembler::call_VM_leaf_base(entry_point, 3);
1783 }
1784 
1785 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1786   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
1787   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1788   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1789   pass_arg3(this, arg_3);
1790   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1791   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1792   pass_arg2(this, arg_2);
1793   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1794   pass_arg1(this, arg_1);
1795   pass_arg0(this, arg_0);
1796   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1797 }
1798 
1799 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1800   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1801   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1802   verify_oop(oop_result, "broken oop in call_VM_base");
1803 }
1804 
1805 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1806   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1807   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1808 }
1809 
1810 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1811 }
1812 
1813 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1814 }
1815 
1816 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
1817   if (reachable(src1)) {
1818     cmpl(as_Address(src1), imm);
1819   } else {
1820     lea(rscratch1, src1);
1821     cmpl(Address(rscratch1, 0), imm);
1822   }
1823 }
1824 
1825 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
1826   assert(!src2.is_lval(), "use cmpptr");
1827   if (reachable(src2)) {
1828     cmpl(src1, as_Address(src2));
1829   } else {
1830     lea(rscratch1, src2);
1831     cmpl(src1, Address(rscratch1, 0));
1832   }
1833 }
1834 
1835 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1836   Assembler::cmpl(src1, imm);
1837 }
1838 
1839 void MacroAssembler::cmp32(Register src1, Address src2) {
1840   Assembler::cmpl(src1, src2);
1841 }
1842 
1843 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1844   ucomisd(opr1, opr2);
1845 
1846   Label L;
1847   if (unordered_is_less) {
1848     movl(dst, -1);
1849     jcc(Assembler::parity, L);
1850     jcc(Assembler::below , L);
1851     movl(dst, 0);
1852     jcc(Assembler::equal , L);
1853     increment(dst);
1854   } else { // unordered is greater
1855     movl(dst, 1);
1856     jcc(Assembler::parity, L);
1857     jcc(Assembler::above , L);
1858     movl(dst, 0);
1859     jcc(Assembler::equal , L);
1860     decrementl(dst);
1861   }
1862   bind(L);
1863 }
1864 
1865 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1866   ucomiss(opr1, opr2);
1867 
1868   Label L;
1869   if (unordered_is_less) {
1870     movl(dst, -1);
1871     jcc(Assembler::parity, L);
1872     jcc(Assembler::below , L);
1873     movl(dst, 0);
1874     jcc(Assembler::equal , L);
1875     increment(dst);
1876   } else { // unordered is greater
1877     movl(dst, 1);
1878     jcc(Assembler::parity, L);
1879     jcc(Assembler::above , L);
1880     movl(dst, 0);
1881     jcc(Assembler::equal , L);
1882     decrementl(dst);
1883   }
1884   bind(L);
1885 }
1886 
1887 
1888 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
1889   if (reachable(src1)) {
1890     cmpb(as_Address(src1), imm);
1891   } else {
1892     lea(rscratch1, src1);
1893     cmpb(Address(rscratch1, 0), imm);
1894   }
1895 }
1896 
1897 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
1898 #ifdef _LP64
1899   if (src2.is_lval()) {
1900     movptr(rscratch1, src2);
1901     Assembler::cmpq(src1, rscratch1);
1902   } else if (reachable(src2)) {
1903     cmpq(src1, as_Address(src2));
1904   } else {
1905     lea(rscratch1, src2);
1906     Assembler::cmpq(src1, Address(rscratch1, 0));
1907   }
1908 #else
1909   if (src2.is_lval()) {
1910     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1911   } else {
1912     cmpl(src1, as_Address(src2));
1913   }
1914 #endif // _LP64
1915 }
1916 
1917 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
1918   assert(src2.is_lval(), "not a mem-mem compare");
1919 #ifdef _LP64
1920   // moves src2's literal address
1921   movptr(rscratch1, src2);
1922   Assembler::cmpq(src1, rscratch1);
1923 #else
1924   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1925 #endif // _LP64
1926 }
1927 
1928 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
1929   if (reachable(adr)) {
1930     if (os::is_MP())
1931       lock();
1932     cmpxchgptr(reg, as_Address(adr));
1933   } else {
1934     lea(rscratch1, adr);
1935     if (os::is_MP())
1936       lock();
1937     cmpxchgptr(reg, Address(rscratch1, 0));
1938   }
1939 }
1940 
1941 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1942   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1943 }
1944 
1945 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
1946   if (reachable(src)) {
1947     Assembler::comisd(dst, as_Address(src));
1948   } else {
1949     lea(rscratch1, src);
1950     Assembler::comisd(dst, Address(rscratch1, 0));
1951   }
1952 }
1953 
1954 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
1955   if (reachable(src)) {
1956     Assembler::comiss(dst, as_Address(src));
1957   } else {
1958     lea(rscratch1, src);
1959     Assembler::comiss(dst, Address(rscratch1, 0));
1960   }
1961 }
1962 
1963 
1964 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
1965   Condition negated_cond = negate_condition(cond);
1966   Label L;
1967   jcc(negated_cond, L);
1968   atomic_incl(counter_addr);
1969   bind(L);
1970 }
1971 
1972 int MacroAssembler::corrected_idivl(Register reg) {
1973   // Full implementation of Java idiv and irem; checks for
1974   // special case as described in JVM spec., p.243 & p.271.
1975   // The function returns the (pc) offset of the idivl
1976   // instruction - may be needed for implicit exceptions.
1977   //
1978   //         normal case                           special case
1979   //
1980   // input : rax,: dividend                         min_int
1981   //         reg: divisor   (may not be rax,/rdx)   -1
1982   //
1983   // output: rax,: quotient  (= rax, idiv reg)       min_int
1984   //         rdx: remainder (= rax, irem reg)       0
1985   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1986   const int min_int = 0x80000000;
1987   Label normal_case, special_case;
1988 
1989   // check for special case
1990   cmpl(rax, min_int);
1991   jcc(Assembler::notEqual, normal_case);
1992   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1993   cmpl(reg, -1);
1994   jcc(Assembler::equal, special_case);
1995 
1996   // handle normal case
1997   bind(normal_case);
1998   cdql();
1999   int idivl_offset = offset();
2000   idivl(reg);
2001 
2002   // normal and special case exit
2003   bind(special_case);
2004 
2005   return idivl_offset;
2006 }
2007 
2008 
2009 
2010 void MacroAssembler::decrementl(Register reg, int value) {
2011   if (value == min_jint) {subl(reg, value) ; return; }
2012   if (value <  0) { incrementl(reg, -value); return; }
2013   if (value == 0) {                        ; return; }
2014   if (value == 1 && UseIncDec) { decl(reg) ; return; }
2015   /* else */      { subl(reg, value)       ; return; }
2016 }
2017 
2018 void MacroAssembler::decrementl(Address dst, int value) {
2019   if (value == min_jint) {subl(dst, value) ; return; }
2020   if (value <  0) { incrementl(dst, -value); return; }
2021   if (value == 0) {                        ; return; }
2022   if (value == 1 && UseIncDec) { decl(dst) ; return; }
2023   /* else */      { subl(dst, value)       ; return; }
2024 }
2025 
2026 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2027   assert (shift_value > 0, "illegal shift value");
2028   Label _is_positive;
2029   testl (reg, reg);
2030   jcc (Assembler::positive, _is_positive);
2031   int offset = (1 << shift_value) - 1 ;
2032 
2033   if (offset == 1) {
2034     incrementl(reg);
2035   } else {
2036     addl(reg, offset);
2037   }
2038 
2039   bind (_is_positive);
2040   sarl(reg, shift_value);
2041 }
2042 
2043 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2044   if (reachable(src)) {
2045     Assembler::divsd(dst, as_Address(src));
2046   } else {
2047     lea(rscratch1, src);
2048     Assembler::divsd(dst, Address(rscratch1, 0));
2049   }
2050 }
2051 
2052 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2053   if (reachable(src)) {
2054     Assembler::divss(dst, as_Address(src));
2055   } else {
2056     lea(rscratch1, src);
2057     Assembler::divss(dst, Address(rscratch1, 0));
2058   }
2059 }
2060 
2061 // !defined(COMPILER2) is because of stupid core builds
2062 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2063 void MacroAssembler::empty_FPU_stack() {
2064   if (VM_Version::supports_mmx()) {
2065     emms();
2066   } else {
2067     for (int i = 8; i-- > 0; ) ffree(i);
2068   }
2069 }
2070 #endif // !LP64 || C1 || !C2
2071 
2072 
2073 // Defines obj, preserves var_size_in_bytes
2074 void MacroAssembler::eden_allocate(Register obj,
2075                                    Register var_size_in_bytes,
2076                                    int con_size_in_bytes,
2077                                    Register t1,
2078                                    Label& slow_case) {
2079   assert(obj == rax, "obj must be in rax, for cmpxchg");
2080   assert_different_registers(obj, var_size_in_bytes, t1);
2081   if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
2082     jmp(slow_case);
2083   } else {
2084     Register end = t1;
2085     Label retry;
2086     bind(retry);
2087     ExternalAddress heap_top((address) Universe::heap()->top_addr());
2088     movptr(obj, heap_top);
2089     if (var_size_in_bytes == noreg) {
2090       lea(end, Address(obj, con_size_in_bytes));
2091     } else {
2092       lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2093     }
2094     // if end < obj then we wrapped around => object too long => slow case
2095     cmpptr(end, obj);
2096     jcc(Assembler::below, slow_case);
2097     cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2098     jcc(Assembler::above, slow_case);
2099     // Compare obj with the top addr, and if still equal, store the new top addr in
2100     // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2101     // it otherwise. Use lock prefix for atomicity on MPs.
2102     locked_cmpxchgptr(end, heap_top);
2103     jcc(Assembler::notEqual, retry);
2104   }
2105 }
2106 
2107 void MacroAssembler::enter() {
2108   push(rbp);
2109   mov(rbp, rsp);
2110 }
2111 
2112 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2113 void MacroAssembler::fat_nop() {
2114   if (UseAddressNop) {
2115     addr_nop_5();
2116   } else {
2117     emit_int8(0x26); // es:
2118     emit_int8(0x2e); // cs:
2119     emit_int8(0x64); // fs:
2120     emit_int8(0x65); // gs:
2121     emit_int8((unsigned char)0x90);
2122   }
2123 }
2124 
2125 void MacroAssembler::fcmp(Register tmp) {
2126   fcmp(tmp, 1, true, true);
2127 }
2128 
2129 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2130   assert(!pop_right || pop_left, "usage error");
2131   if (VM_Version::supports_cmov()) {
2132     assert(tmp == noreg, "unneeded temp");
2133     if (pop_left) {
2134       fucomip(index);
2135     } else {
2136       fucomi(index);
2137     }
2138     if (pop_right) {
2139       fpop();
2140     }
2141   } else {
2142     assert(tmp != noreg, "need temp");
2143     if (pop_left) {
2144       if (pop_right) {
2145         fcompp();
2146       } else {
2147         fcomp(index);
2148       }
2149     } else {
2150       fcom(index);
2151     }
2152     // convert FPU condition into eflags condition via rax,
2153     save_rax(tmp);
2154     fwait(); fnstsw_ax();
2155     sahf();
2156     restore_rax(tmp);
2157   }
2158   // condition codes set as follows:
2159   //
2160   // CF (corresponds to C0) if x < y
2161   // PF (corresponds to C2) if unordered
2162   // ZF (corresponds to C3) if x = y
2163 }
2164 
2165 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2166   fcmp2int(dst, unordered_is_less, 1, true, true);
2167 }
2168 
2169 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2170   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2171   Label L;
2172   if (unordered_is_less) {
2173     movl(dst, -1);
2174     jcc(Assembler::parity, L);
2175     jcc(Assembler::below , L);
2176     movl(dst, 0);
2177     jcc(Assembler::equal , L);
2178     increment(dst);
2179   } else { // unordered is greater
2180     movl(dst, 1);
2181     jcc(Assembler::parity, L);
2182     jcc(Assembler::above , L);
2183     movl(dst, 0);
2184     jcc(Assembler::equal , L);
2185     decrementl(dst);
2186   }
2187   bind(L);
2188 }
2189 
2190 void MacroAssembler::fld_d(AddressLiteral src) {
2191   fld_d(as_Address(src));
2192 }
2193 
2194 void MacroAssembler::fld_s(AddressLiteral src) {
2195   fld_s(as_Address(src));
2196 }
2197 
2198 void MacroAssembler::fld_x(AddressLiteral src) {
2199   Assembler::fld_x(as_Address(src));
2200 }
2201 
2202 void MacroAssembler::fldcw(AddressLiteral src) {
2203   Assembler::fldcw(as_Address(src));
2204 }
2205 
2206 void MacroAssembler::pow_exp_core_encoding() {
2207   // kills rax, rcx, rdx
2208   subptr(rsp,sizeof(jdouble));
2209   // computes 2^X. Stack: X ...
2210   // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
2211   // keep it on the thread's stack to compute 2^int(X) later
2212   // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
2213   // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
2214   fld_s(0);                 // Stack: X X ...
2215   frndint();                // Stack: int(X) X ...
2216   fsuba(1);                 // Stack: int(X) X-int(X) ...
2217   fistp_s(Address(rsp,0));  // move int(X) as integer to thread's stack. Stack: X-int(X) ...
2218   f2xm1();                  // Stack: 2^(X-int(X))-1 ...
2219   fld1();                   // Stack: 1 2^(X-int(X))-1 ...
2220   faddp(1);                 // Stack: 2^(X-int(X))
2221   // computes 2^(int(X)): add exponent bias (1023) to int(X), then
2222   // shift int(X)+1023 to exponent position.
2223   // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
2224   // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
2225   // values so detect them and set result to NaN.
2226   movl(rax,Address(rsp,0));
2227   movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
2228   addl(rax, 1023);
2229   movl(rdx,rax);
2230   shll(rax,20);
2231   // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
2232   addl(rdx,1);
2233   // Check that 1 < int(X)+1023+1 < 2048
2234   // in 3 steps:
2235   // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
2236   // 2- (int(X)+1023+1)&-2048 != 0
2237   // 3- (int(X)+1023+1)&-2048 != 1
2238   // Do 2- first because addl just updated the flags.
2239   cmov32(Assembler::equal,rax,rcx);
2240   cmpl(rdx,1);
2241   cmov32(Assembler::equal,rax,rcx);
2242   testl(rdx,rcx);
2243   cmov32(Assembler::notEqual,rax,rcx);
2244   movl(Address(rsp,4),rax);
2245   movl(Address(rsp,0),0);
2246   fmul_d(Address(rsp,0));   // Stack: 2^X ...
2247   addptr(rsp,sizeof(jdouble));
2248 }
2249 
2250 void MacroAssembler::increase_precision() {
2251   subptr(rsp, BytesPerWord);
2252   fnstcw(Address(rsp, 0));
2253   movl(rax, Address(rsp, 0));
2254   orl(rax, 0x300);
2255   push(rax);
2256   fldcw(Address(rsp, 0));
2257   pop(rax);
2258 }
2259 
2260 void MacroAssembler::restore_precision() {
2261   fldcw(Address(rsp, 0));
2262   addptr(rsp, BytesPerWord);
2263 }
2264 
2265 void MacroAssembler::fast_pow() {
2266   // computes X^Y = 2^(Y * log2(X))
2267   // if fast computation is not possible, result is NaN. Requires
2268   // fallback from user of this macro.
2269   // increase precision for intermediate steps of the computation
2270   increase_precision();
2271   fyl2x();                 // Stack: (Y*log2(X)) ...
2272   pow_exp_core_encoding(); // Stack: exp(X) ...
2273   restore_precision();
2274 }
2275 
2276 void MacroAssembler::fast_exp() {
2277   // computes exp(X) = 2^(X * log2(e))
2278   // if fast computation is not possible, result is NaN. Requires
2279   // fallback from user of this macro.
2280   // increase precision for intermediate steps of the computation
2281   increase_precision();
2282   fldl2e();                // Stack: log2(e) X ...
2283   fmulp(1);                // Stack: (X*log2(e)) ...
2284   pow_exp_core_encoding(); // Stack: exp(X) ...
2285   restore_precision();
2286 }
2287 
2288 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
2289   // kills rax, rcx, rdx
2290   // pow and exp needs 2 extra registers on the fpu stack.
2291   Label slow_case, done;
2292   Register tmp = noreg;
2293   if (!VM_Version::supports_cmov()) {
2294     // fcmp needs a temporary so preserve rdx,
2295     tmp = rdx;
2296   }
2297   Register tmp2 = rax;
2298   Register tmp3 = rcx;
2299 
2300   if (is_exp) {
2301     // Stack: X
2302     fld_s(0);                   // duplicate argument for runtime call. Stack: X X
2303     fast_exp();                 // Stack: exp(X) X
2304     fcmp(tmp, 0, false, false); // Stack: exp(X) X
2305     // exp(X) not equal to itself: exp(X) is NaN go to slow case.
2306     jcc(Assembler::parity, slow_case);
2307     // get rid of duplicate argument. Stack: exp(X)
2308     if (num_fpu_regs_in_use > 0) {
2309       fxch();
2310       fpop();
2311     } else {
2312       ffree(1);
2313     }
2314     jmp(done);
2315   } else {
2316     // Stack: X Y
2317     Label x_negative, y_odd;
2318 
2319     fldz();                     // Stack: 0 X Y
2320     fcmp(tmp, 1, true, false);  // Stack: X Y
2321     jcc(Assembler::above, x_negative);
2322 
2323     // X >= 0
2324 
2325     fld_s(1);                   // duplicate arguments for runtime call. Stack: Y X Y
2326     fld_s(1);                   // Stack: X Y X Y
2327     fast_pow();                 // Stack: X^Y X Y
2328     fcmp(tmp, 0, false, false); // Stack: X^Y X Y
2329     // X^Y not equal to itself: X^Y is NaN go to slow case.
2330     jcc(Assembler::parity, slow_case);
2331     // get rid of duplicate arguments. Stack: X^Y
2332     if (num_fpu_regs_in_use > 0) {
2333       fxch(); fpop();
2334       fxch(); fpop();
2335     } else {
2336       ffree(2);
2337       ffree(1);
2338     }
2339     jmp(done);
2340 
2341     // X <= 0
2342     bind(x_negative);
2343 
2344     fld_s(1);                   // Stack: Y X Y
2345     frndint();                  // Stack: int(Y) X Y
2346     fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
2347     jcc(Assembler::notEqual, slow_case);
2348 
2349     subptr(rsp, 8);
2350 
2351     // For X^Y, when X < 0, Y has to be an integer and the final
2352     // result depends on whether it's odd or even. We just checked
2353     // that int(Y) == Y.  We move int(Y) to gp registers as a 64 bit
2354     // integer to test its parity. If int(Y) is huge and doesn't fit
2355     // in the 64 bit integer range, the integer indefinite value will
2356     // end up in the gp registers. Huge numbers are all even, the
2357     // integer indefinite number is even so it's fine.
2358 
2359 #ifdef ASSERT
2360     // Let's check we don't end up with an integer indefinite number
2361     // when not expected. First test for huge numbers: check whether
2362     // int(Y)+1 == int(Y) which is true for very large numbers and
2363     // those are all even. A 64 bit integer is guaranteed to not
2364     // overflow for numbers where y+1 != y (when precision is set to
2365     // double precision).
2366     Label y_not_huge;
2367 
2368     fld1();                     // Stack: 1 int(Y) X Y
2369     fadd(1);                    // Stack: 1+int(Y) int(Y) X Y
2370 
2371 #ifdef _LP64
2372     // trip to memory to force the precision down from double extended
2373     // precision
2374     fstp_d(Address(rsp, 0));
2375     fld_d(Address(rsp, 0));
2376 #endif
2377 
2378     fcmp(tmp, 1, true, false);  // Stack: int(Y) X Y
2379 #endif
2380 
2381     // move int(Y) as 64 bit integer to thread's stack
2382     fistp_d(Address(rsp,0));    // Stack: X Y
2383 
2384 #ifdef ASSERT
2385     jcc(Assembler::notEqual, y_not_huge);
2386 
2387     // Y is huge so we know it's even. It may not fit in a 64 bit
2388     // integer and we don't want the debug code below to see the
2389     // integer indefinite value so overwrite int(Y) on the thread's
2390     // stack with 0.
2391     movl(Address(rsp, 0), 0);
2392     movl(Address(rsp, 4), 0);
2393 
2394     bind(y_not_huge);
2395 #endif
2396 
2397     fld_s(1);                   // duplicate arguments for runtime call. Stack: Y X Y
2398     fld_s(1);                   // Stack: X Y X Y
2399     fabs();                     // Stack: abs(X) Y X Y
2400     fast_pow();                 // Stack: abs(X)^Y X Y
2401     fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
2402     // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
2403 
2404     pop(tmp2);
2405     NOT_LP64(pop(tmp3));
2406     jcc(Assembler::parity, slow_case);
2407 
2408 #ifdef ASSERT
2409     // Check that int(Y) is not integer indefinite value (int
2410     // overflow). Shouldn't happen because for values that would
2411     // overflow, 1+int(Y)==Y which was tested earlier.
2412 #ifndef _LP64
2413     {
2414       Label integer;
2415       testl(tmp2, tmp2);
2416       jcc(Assembler::notZero, integer);
2417       cmpl(tmp3, 0x80000000);
2418       jcc(Assembler::notZero, integer);
2419       STOP("integer indefinite value shouldn't be seen here");
2420       bind(integer);
2421     }
2422 #else
2423     {
2424       Label integer;
2425       mov(tmp3, tmp2); // preserve tmp2 for parity check below
2426       shlq(tmp3, 1);
2427       jcc(Assembler::carryClear, integer);
2428       jcc(Assembler::notZero, integer);
2429       STOP("integer indefinite value shouldn't be seen here");
2430       bind(integer);
2431     }
2432 #endif
2433 #endif
2434 
2435     // get rid of duplicate arguments. Stack: X^Y
2436     if (num_fpu_regs_in_use > 0) {
2437       fxch(); fpop();
2438       fxch(); fpop();
2439     } else {
2440       ffree(2);
2441       ffree(1);
2442     }
2443 
2444     testl(tmp2, 1);
2445     jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
2446     // X <= 0, Y even: X^Y = -abs(X)^Y
2447 
2448     fchs();                     // Stack: -abs(X)^Y Y
2449     jmp(done);
2450   }
2451 
2452   // slow case: runtime call
2453   bind(slow_case);
2454 
2455   fpop();                       // pop incorrect result or int(Y)
2456 
2457   fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
2458                       is_exp ? 1 : 2, num_fpu_regs_in_use);
2459 
2460   // Come here with result in F-TOS
2461   bind(done);
2462 }
2463 
2464 void MacroAssembler::fpop() {
2465   ffree();
2466   fincstp();
2467 }
2468 
2469 void MacroAssembler::fremr(Register tmp) {
2470   save_rax(tmp);
2471   { Label L;
2472     bind(L);
2473     fprem();
2474     fwait(); fnstsw_ax();
2475 #ifdef _LP64
2476     testl(rax, 0x400);
2477     jcc(Assembler::notEqual, L);
2478 #else
2479     sahf();
2480     jcc(Assembler::parity, L);
2481 #endif // _LP64
2482   }
2483   restore_rax(tmp);
2484   // Result is in ST0.
2485   // Note: fxch & fpop to get rid of ST1
2486   // (otherwise FPU stack could overflow eventually)
2487   fxch(1);
2488   fpop();
2489 }
2490 
2491 
2492 void MacroAssembler::incrementl(AddressLiteral dst) {
2493   if (reachable(dst)) {
2494     incrementl(as_Address(dst));
2495   } else {
2496     lea(rscratch1, dst);
2497     incrementl(Address(rscratch1, 0));
2498   }
2499 }
2500 
2501 void MacroAssembler::incrementl(ArrayAddress dst) {
2502   incrementl(as_Address(dst));
2503 }
2504 
2505 void MacroAssembler::incrementl(Register reg, int value) {
2506   if (value == min_jint) {addl(reg, value) ; return; }
2507   if (value <  0) { decrementl(reg, -value); return; }
2508   if (value == 0) {                        ; return; }
2509   if (value == 1 && UseIncDec) { incl(reg) ; return; }
2510   /* else */      { addl(reg, value)       ; return; }
2511 }
2512 
2513 void MacroAssembler::incrementl(Address dst, int value) {
2514   if (value == min_jint) {addl(dst, value) ; return; }
2515   if (value <  0) { decrementl(dst, -value); return; }
2516   if (value == 0) {                        ; return; }
2517   if (value == 1 && UseIncDec) { incl(dst) ; return; }
2518   /* else */      { addl(dst, value)       ; return; }
2519 }
2520 
2521 void MacroAssembler::jump(AddressLiteral dst) {
2522   if (reachable(dst)) {
2523     jmp_literal(dst.target(), dst.rspec());
2524   } else {
2525     lea(rscratch1, dst);
2526     jmp(rscratch1);
2527   }
2528 }
2529 
2530 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2531   if (reachable(dst)) {
2532     InstructionMark im(this);
2533     relocate(dst.reloc());
2534     const int short_size = 2;
2535     const int long_size = 6;
2536     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2537     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2538       // 0111 tttn #8-bit disp
2539       emit_int8(0x70 | cc);
2540       emit_int8((offs - short_size) & 0xFF);
2541     } else {
2542       // 0000 1111 1000 tttn #32-bit disp
2543       emit_int8(0x0F);
2544       emit_int8((unsigned char)(0x80 | cc));
2545       emit_int32(offs - long_size);
2546     }
2547   } else {
2548 #ifdef ASSERT
2549     warning("reversing conditional branch");
2550 #endif /* ASSERT */
2551     Label skip;
2552     jccb(reverse[cc], skip);
2553     lea(rscratch1, dst);
2554     Assembler::jmp(rscratch1);
2555     bind(skip);
2556   }
2557 }
2558 
2559 void MacroAssembler::ldmxcsr(AddressLiteral src) {
2560   if (reachable(src)) {
2561     Assembler::ldmxcsr(as_Address(src));
2562   } else {
2563     lea(rscratch1, src);
2564     Assembler::ldmxcsr(Address(rscratch1, 0));
2565   }
2566 }
2567 
2568 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2569   int off;
2570   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2571     off = offset();
2572     movsbl(dst, src); // movsxb
2573   } else {
2574     off = load_unsigned_byte(dst, src);
2575     shll(dst, 24);
2576     sarl(dst, 24);
2577   }
2578   return off;
2579 }
2580 
2581 // Note: load_signed_short used to be called load_signed_word.
2582 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2583 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2584 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2585 int MacroAssembler::load_signed_short(Register dst, Address src) {
2586   int off;
2587   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2588     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2589     // version but this is what 64bit has always done. This seems to imply
2590     // that users are only using 32bits worth.
2591     off = offset();
2592     movswl(dst, src); // movsxw
2593   } else {
2594     off = load_unsigned_short(dst, src);
2595     shll(dst, 16);
2596     sarl(dst, 16);
2597   }
2598   return off;
2599 }
2600 
2601 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2602   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2603   // and "3.9 Partial Register Penalties", p. 22).
2604   int off;
2605   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2606     off = offset();
2607     movzbl(dst, src); // movzxb
2608   } else {
2609     xorl(dst, dst);
2610     off = offset();
2611     movb(dst, src);
2612   }
2613   return off;
2614 }
2615 
2616 // Note: load_unsigned_short used to be called load_unsigned_word.
2617 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2618   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2619   // and "3.9 Partial Register Penalties", p. 22).
2620   int off;
2621   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2622     off = offset();
2623     movzwl(dst, src); // movzxw
2624   } else {
2625     xorl(dst, dst);
2626     off = offset();
2627     movw(dst, src);
2628   }
2629   return off;
2630 }
2631 
2632 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2633   switch (size_in_bytes) {
2634 #ifndef _LP64
2635   case  8:
2636     assert(dst2 != noreg, "second dest register required");
2637     movl(dst,  src);
2638     movl(dst2, src.plus_disp(BytesPerInt));
2639     break;
2640 #else
2641   case  8:  movq(dst, src); break;
2642 #endif
2643   case  4:  movl(dst, src); break;
2644   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2645   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2646   default:  ShouldNotReachHere();
2647   }
2648 }
2649 
2650 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2651   switch (size_in_bytes) {
2652 #ifndef _LP64
2653   case  8:
2654     assert(src2 != noreg, "second source register required");
2655     movl(dst,                        src);
2656     movl(dst.plus_disp(BytesPerInt), src2);
2657     break;
2658 #else
2659   case  8:  movq(dst, src); break;
2660 #endif
2661   case  4:  movl(dst, src); break;
2662   case  2:  movw(dst, src); break;
2663   case  1:  movb(dst, src); break;
2664   default:  ShouldNotReachHere();
2665   }
2666 }
2667 
2668 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2669   if (reachable(dst)) {
2670     movl(as_Address(dst), src);
2671   } else {
2672     lea(rscratch1, dst);
2673     movl(Address(rscratch1, 0), src);
2674   }
2675 }
2676 
2677 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2678   if (reachable(src)) {
2679     movl(dst, as_Address(src));
2680   } else {
2681     lea(rscratch1, src);
2682     movl(dst, Address(rscratch1, 0));
2683   }
2684 }
2685 
2686 // C++ bool manipulation
2687 
2688 void MacroAssembler::movbool(Register dst, Address src) {
2689   if(sizeof(bool) == 1)
2690     movb(dst, src);
2691   else if(sizeof(bool) == 2)
2692     movw(dst, src);
2693   else if(sizeof(bool) == 4)
2694     movl(dst, src);
2695   else
2696     // unsupported
2697     ShouldNotReachHere();
2698 }
2699 
2700 void MacroAssembler::movbool(Address dst, bool boolconst) {
2701   if(sizeof(bool) == 1)
2702     movb(dst, (int) boolconst);
2703   else if(sizeof(bool) == 2)
2704     movw(dst, (int) boolconst);
2705   else if(sizeof(bool) == 4)
2706     movl(dst, (int) boolconst);
2707   else
2708     // unsupported
2709     ShouldNotReachHere();
2710 }
2711 
2712 void MacroAssembler::movbool(Address dst, Register src) {
2713   if(sizeof(bool) == 1)
2714     movb(dst, src);
2715   else if(sizeof(bool) == 2)
2716     movw(dst, src);
2717   else if(sizeof(bool) == 4)
2718     movl(dst, src);
2719   else
2720     // unsupported
2721     ShouldNotReachHere();
2722 }
2723 
2724 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2725   movb(as_Address(dst), src);
2726 }
2727 
2728 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
2729   if (reachable(src)) {
2730     movdl(dst, as_Address(src));
2731   } else {
2732     lea(rscratch1, src);
2733     movdl(dst, Address(rscratch1, 0));
2734   }
2735 }
2736 
2737 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
2738   if (reachable(src)) {
2739     movq(dst, as_Address(src));
2740   } else {
2741     lea(rscratch1, src);
2742     movq(dst, Address(rscratch1, 0));
2743   }
2744 }
2745 
2746 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2747   if (reachable(src)) {
2748     if (UseXmmLoadAndClearUpper) {
2749       movsd (dst, as_Address(src));
2750     } else {
2751       movlpd(dst, as_Address(src));
2752     }
2753   } else {
2754     lea(rscratch1, src);
2755     if (UseXmmLoadAndClearUpper) {
2756       movsd (dst, Address(rscratch1, 0));
2757     } else {
2758       movlpd(dst, Address(rscratch1, 0));
2759     }
2760   }
2761 }
2762 
2763 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2764   if (reachable(src)) {
2765     movss(dst, as_Address(src));
2766   } else {
2767     lea(rscratch1, src);
2768     movss(dst, Address(rscratch1, 0));
2769   }
2770 }
2771 
2772 void MacroAssembler::movptr(Register dst, Register src) {
2773   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2774 }
2775 
2776 void MacroAssembler::movptr(Register dst, Address src) {
2777   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2778 }
2779 
2780 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2781 void MacroAssembler::movptr(Register dst, intptr_t src) {
2782   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
2783 }
2784 
2785 void MacroAssembler::movptr(Address dst, Register src) {
2786   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2787 }
2788 
2789 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
2790   if (reachable(src)) {
2791     Assembler::movdqu(dst, as_Address(src));
2792   } else {
2793     lea(rscratch1, src);
2794     Assembler::movdqu(dst, Address(rscratch1, 0));
2795   }
2796 }
2797 
2798 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
2799   if (reachable(src)) {
2800     Assembler::movdqa(dst, as_Address(src));
2801   } else {
2802     lea(rscratch1, src);
2803     Assembler::movdqa(dst, Address(rscratch1, 0));
2804   }
2805 }
2806 
2807 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2808   if (reachable(src)) {
2809     Assembler::movsd(dst, as_Address(src));
2810   } else {
2811     lea(rscratch1, src);
2812     Assembler::movsd(dst, Address(rscratch1, 0));
2813   }
2814 }
2815 
2816 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2817   if (reachable(src)) {
2818     Assembler::movss(dst, as_Address(src));
2819   } else {
2820     lea(rscratch1, src);
2821     Assembler::movss(dst, Address(rscratch1, 0));
2822   }
2823 }
2824 
2825 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
2826   if (reachable(src)) {
2827     Assembler::mulsd(dst, as_Address(src));
2828   } else {
2829     lea(rscratch1, src);
2830     Assembler::mulsd(dst, Address(rscratch1, 0));
2831   }
2832 }
2833 
2834 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
2835   if (reachable(src)) {
2836     Assembler::mulss(dst, as_Address(src));
2837   } else {
2838     lea(rscratch1, src);
2839     Assembler::mulss(dst, Address(rscratch1, 0));
2840   }
2841 }
2842 
2843 void MacroAssembler::null_check(Register reg, int offset) {
2844   if (needs_explicit_null_check(offset)) {
2845     // provoke OS NULL exception if reg = NULL by
2846     // accessing M[reg] w/o changing any (non-CC) registers
2847     // NOTE: cmpl is plenty here to provoke a segv
2848     cmpptr(rax, Address(reg, 0));
2849     // Note: should probably use testl(rax, Address(reg, 0));
2850     //       may be shorter code (however, this version of
2851     //       testl needs to be implemented first)
2852   } else {
2853     // nothing to do, (later) access of M[reg + offset]
2854     // will provoke OS NULL exception if reg = NULL
2855   }
2856 }
2857 
2858 void MacroAssembler::os_breakpoint() {
2859   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2860   // (e.g., MSVC can't call ps() otherwise)
2861   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2862 }
2863 
2864 void MacroAssembler::pop_CPU_state() {
2865   pop_FPU_state();
2866   pop_IU_state();
2867 }
2868 
2869 void MacroAssembler::pop_FPU_state() {
2870   NOT_LP64(frstor(Address(rsp, 0));)
2871   LP64_ONLY(fxrstor(Address(rsp, 0));)
2872   addptr(rsp, FPUStateSizeInWords * wordSize);
2873 }
2874 
2875 void MacroAssembler::pop_IU_state() {
2876   popa();
2877   LP64_ONLY(addq(rsp, 8));
2878   popf();
2879 }
2880 
2881 // Save Integer and Float state
2882 // Warning: Stack must be 16 byte aligned (64bit)
2883 void MacroAssembler::push_CPU_state() {
2884   push_IU_state();
2885   push_FPU_state();
2886 }
2887 
2888 void MacroAssembler::push_FPU_state() {
2889   subptr(rsp, FPUStateSizeInWords * wordSize);
2890 #ifndef _LP64
2891   fnsave(Address(rsp, 0));
2892   fwait();
2893 #else
2894   fxsave(Address(rsp, 0));
2895 #endif // LP64
2896 }
2897 
2898 void MacroAssembler::push_IU_state() {
2899   // Push flags first because pusha kills them
2900   pushf();
2901   // Make sure rsp stays 16-byte aligned
2902   LP64_ONLY(subq(rsp, 8));
2903   pusha();
2904 }
2905 
2906 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
2907   // determine java_thread register
2908   if (!java_thread->is_valid()) {
2909     java_thread = rdi;
2910     get_thread(java_thread);
2911   }
2912   // we must set sp to zero to clear frame
2913   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2914   if (clear_fp) {
2915     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2916   }
2917 
2918   if (clear_pc)
2919     movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2920 
2921 }
2922 
2923 void MacroAssembler::restore_rax(Register tmp) {
2924   if (tmp == noreg) pop(rax);
2925   else if (tmp != rax) mov(rax, tmp);
2926 }
2927 
2928 void MacroAssembler::round_to(Register reg, int modulus) {
2929   addptr(reg, modulus - 1);
2930   andptr(reg, -modulus);
2931 }
2932 
2933 void MacroAssembler::save_rax(Register tmp) {
2934   if (tmp == noreg) push(rax);
2935   else if (tmp != rax) mov(tmp, rax);
2936 }
2937 
2938 // Write serialization page so VM thread can do a pseudo remote membar.
2939 // We use the current thread pointer to calculate a thread specific
2940 // offset to write to within the page. This minimizes bus traffic
2941 // due to cache line collision.
2942 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
2943   movl(tmp, thread);
2944   shrl(tmp, os::get_serialize_page_shift_count());
2945   andl(tmp, (os::vm_page_size() - sizeof(int)));
2946 
2947   Address index(noreg, tmp, Address::times_1);
2948   ExternalAddress page(os::get_memory_serialize_page());
2949 
2950   // Size of store must match masking code above
2951   movl(as_Address(ArrayAddress(page, index)), tmp);
2952 }
2953 
2954 // Calls to C land
2955 //
2956 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2957 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2958 // has to be reset to 0. This is required to allow proper stack traversal.
2959 void MacroAssembler::set_last_Java_frame(Register java_thread,
2960                                          Register last_java_sp,
2961                                          Register last_java_fp,
2962                                          address  last_java_pc) {
2963   // determine java_thread register
2964   if (!java_thread->is_valid()) {
2965     java_thread = rdi;
2966     get_thread(java_thread);
2967   }
2968   // determine last_java_sp register
2969   if (!last_java_sp->is_valid()) {
2970     last_java_sp = rsp;
2971   }
2972 
2973   // last_java_fp is optional
2974 
2975   if (last_java_fp->is_valid()) {
2976     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2977   }
2978 
2979   // last_java_pc is optional
2980 
2981   if (last_java_pc != NULL) {
2982     lea(Address(java_thread,
2983                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
2984         InternalAddress(last_java_pc));
2985 
2986   }
2987   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2988 }
2989 
2990 void MacroAssembler::shlptr(Register dst, int imm8) {
2991   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
2992 }
2993 
2994 void MacroAssembler::shrptr(Register dst, int imm8) {
2995   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
2996 }
2997 
2998 void MacroAssembler::sign_extend_byte(Register reg) {
2999   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3000     movsbl(reg, reg); // movsxb
3001   } else {
3002     shll(reg, 24);
3003     sarl(reg, 24);
3004   }
3005 }
3006 
3007 void MacroAssembler::sign_extend_short(Register reg) {
3008   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3009     movswl(reg, reg); // movsxw
3010   } else {
3011     shll(reg, 16);
3012     sarl(reg, 16);
3013   }
3014 }
3015 
3016 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3017   assert(reachable(src), "Address should be reachable");
3018   testl(dst, as_Address(src));
3019 }
3020 
3021 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3022   if (reachable(src)) {
3023     Assembler::sqrtsd(dst, as_Address(src));
3024   } else {
3025     lea(rscratch1, src);
3026     Assembler::sqrtsd(dst, Address(rscratch1, 0));
3027   }
3028 }
3029 
3030 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3031   if (reachable(src)) {
3032     Assembler::sqrtss(dst, as_Address(src));
3033   } else {
3034     lea(rscratch1, src);
3035     Assembler::sqrtss(dst, Address(rscratch1, 0));
3036   }
3037 }
3038 
3039 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3040   if (reachable(src)) {
3041     Assembler::subsd(dst, as_Address(src));
3042   } else {
3043     lea(rscratch1, src);
3044     Assembler::subsd(dst, Address(rscratch1, 0));
3045   }
3046 }
3047 
3048 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3049   if (reachable(src)) {
3050     Assembler::subss(dst, as_Address(src));
3051   } else {
3052     lea(rscratch1, src);
3053     Assembler::subss(dst, Address(rscratch1, 0));
3054   }
3055 }
3056 
3057 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3058   if (reachable(src)) {
3059     Assembler::ucomisd(dst, as_Address(src));
3060   } else {
3061     lea(rscratch1, src);
3062     Assembler::ucomisd(dst, Address(rscratch1, 0));
3063   }
3064 }
3065 
3066 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3067   if (reachable(src)) {
3068     Assembler::ucomiss(dst, as_Address(src));
3069   } else {
3070     lea(rscratch1, src);
3071     Assembler::ucomiss(dst, Address(rscratch1, 0));
3072   }
3073 }
3074 
3075 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3076   // Used in sign-bit flipping with aligned address.
3077   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3078   if (reachable(src)) {
3079     Assembler::xorpd(dst, as_Address(src));
3080   } else {
3081     lea(rscratch1, src);
3082     Assembler::xorpd(dst, Address(rscratch1, 0));
3083   }
3084 }
3085 
3086 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3087   // Used in sign-bit flipping with aligned address.
3088   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3089   if (reachable(src)) {
3090     Assembler::xorps(dst, as_Address(src));
3091   } else {
3092     lea(rscratch1, src);
3093     Assembler::xorps(dst, Address(rscratch1, 0));
3094   }
3095 }
3096 
3097 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3098   // Used in sign-bit flipping with aligned address.
3099   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3100   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3101   if (reachable(src)) {
3102     Assembler::pshufb(dst, as_Address(src));
3103   } else {
3104     lea(rscratch1, src);
3105     Assembler::pshufb(dst, Address(rscratch1, 0));
3106   }
3107 }
3108 
3109 // AVX 3-operands instructions
3110 
3111 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3112   if (reachable(src)) {
3113     vaddsd(dst, nds, as_Address(src));
3114   } else {
3115     lea(rscratch1, src);
3116     vaddsd(dst, nds, Address(rscratch1, 0));
3117   }
3118 }
3119 
3120 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3121   if (reachable(src)) {
3122     vaddss(dst, nds, as_Address(src));
3123   } else {
3124     lea(rscratch1, src);
3125     vaddss(dst, nds, Address(rscratch1, 0));
3126   }
3127 }
3128 
3129 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
3130   if (reachable(src)) {
3131     vandpd(dst, nds, as_Address(src), vector256);
3132   } else {
3133     lea(rscratch1, src);
3134     vandpd(dst, nds, Address(rscratch1, 0), vector256);
3135   }
3136 }
3137 
3138 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
3139   if (reachable(src)) {
3140     vandps(dst, nds, as_Address(src), vector256);
3141   } else {
3142     lea(rscratch1, src);
3143     vandps(dst, nds, Address(rscratch1, 0), vector256);
3144   }
3145 }
3146 
3147 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3148   if (reachable(src)) {
3149     vdivsd(dst, nds, as_Address(src));
3150   } else {
3151     lea(rscratch1, src);
3152     vdivsd(dst, nds, Address(rscratch1, 0));
3153   }
3154 }
3155 
3156 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3157   if (reachable(src)) {
3158     vdivss(dst, nds, as_Address(src));
3159   } else {
3160     lea(rscratch1, src);
3161     vdivss(dst, nds, Address(rscratch1, 0));
3162   }
3163 }
3164 
3165 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3166   if (reachable(src)) {
3167     vmulsd(dst, nds, as_Address(src));
3168   } else {
3169     lea(rscratch1, src);
3170     vmulsd(dst, nds, Address(rscratch1, 0));
3171   }
3172 }
3173 
3174 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3175   if (reachable(src)) {
3176     vmulss(dst, nds, as_Address(src));
3177   } else {
3178     lea(rscratch1, src);
3179     vmulss(dst, nds, Address(rscratch1, 0));
3180   }
3181 }
3182 
3183 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3184   if (reachable(src)) {
3185     vsubsd(dst, nds, as_Address(src));
3186   } else {
3187     lea(rscratch1, src);
3188     vsubsd(dst, nds, Address(rscratch1, 0));
3189   }
3190 }
3191 
3192 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3193   if (reachable(src)) {
3194     vsubss(dst, nds, as_Address(src));
3195   } else {
3196     lea(rscratch1, src);
3197     vsubss(dst, nds, Address(rscratch1, 0));
3198   }
3199 }
3200 
3201 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
3202   if (reachable(src)) {
3203     vxorpd(dst, nds, as_Address(src), vector256);
3204   } else {
3205     lea(rscratch1, src);
3206     vxorpd(dst, nds, Address(rscratch1, 0), vector256);
3207   }
3208 }
3209 
3210 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
3211   if (reachable(src)) {
3212     vxorps(dst, nds, as_Address(src), vector256);
3213   } else {
3214     lea(rscratch1, src);
3215     vxorps(dst, nds, Address(rscratch1, 0), vector256);
3216   }
3217 }
3218 
3219 
3220 //////////////////////////////////////////////////////////////////////////////////
3221 #if INCLUDE_ALL_GCS
3222 
3223 void MacroAssembler::g1_write_barrier_pre(Register obj,
3224                                           Register pre_val,
3225                                           Register thread,
3226                                           Register tmp,
3227                                           bool tosca_live,
3228                                           bool expand_call) {
3229 
3230   // If expand_call is true then we expand the call_VM_leaf macro
3231   // directly to skip generating the check by
3232   // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
3233 
3234 #ifdef _LP64
3235   assert(thread == r15_thread, "must be");
3236 #endif // _LP64
3237 
3238   Label done;
3239   Label runtime;
3240 
3241   assert(pre_val != noreg, "check this code");
3242 
3243   if (obj != noreg) {
3244     assert_different_registers(obj, pre_val, tmp);
3245     assert(pre_val != rax, "check this code");
3246   }
3247 
3248   Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3249                                        PtrQueue::byte_offset_of_active()));
3250   Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3251                                        PtrQueue::byte_offset_of_index()));
3252   Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
3253                                        PtrQueue::byte_offset_of_buf()));
3254 
3255 
3256   // Is marking active?
3257   if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
3258     cmpl(in_progress, 0);
3259   } else {
3260     assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
3261     cmpb(in_progress, 0);
3262   }
3263   jcc(Assembler::equal, done);
3264 
3265   // Do we need to load the previous value?
3266   if (obj != noreg) {
3267     load_heap_oop(pre_val, Address(obj, 0));
3268   }
3269 
3270   // Is the previous value null?
3271   cmpptr(pre_val, (int32_t) NULL_WORD);
3272   jcc(Assembler::equal, done);
3273 
3274   // Can we store original value in the thread's buffer?
3275   // Is index == 0?
3276   // (The index field is typed as size_t.)
3277 
3278   movptr(tmp, index);                   // tmp := *index_adr
3279   cmpptr(tmp, 0);                       // tmp == 0?
3280   jcc(Assembler::equal, runtime);       // If yes, goto runtime
3281 
3282   subptr(tmp, wordSize);                // tmp := tmp - wordSize
3283   movptr(index, tmp);                   // *index_adr := tmp
3284   addptr(tmp, buffer);                  // tmp := tmp + *buffer_adr
3285 
3286   // Record the previous value
3287   movptr(Address(tmp, 0), pre_val);
3288   jmp(done);
3289 
3290   bind(runtime);
3291   // save the live input values
3292   if(tosca_live) push(rax);
3293 
3294   if (obj != noreg && obj != rax)
3295     push(obj);
3296 
3297   if (pre_val != rax)
3298     push(pre_val);
3299 
3300   // Calling the runtime using the regular call_VM_leaf mechanism generates
3301   // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
3302   // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
3303   //
3304   // If we care generating the pre-barrier without a frame (e.g. in the
3305   // intrinsified Reference.get() routine) then ebp might be pointing to
3306   // the caller frame and so this check will most likely fail at runtime.
3307   //
3308   // Expanding the call directly bypasses the generation of the check.
3309   // So when we do not have have a full interpreter frame on the stack
3310   // expand_call should be passed true.
3311 
3312   NOT_LP64( push(thread); )
3313 
3314   if (expand_call) {
3315     LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
3316     pass_arg1(this, thread);
3317     pass_arg0(this, pre_val);
3318     MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
3319   } else {
3320     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
3321   }
3322 
3323   NOT_LP64( pop(thread); )
3324 
3325   // save the live input values
3326   if (pre_val != rax)
3327     pop(pre_val);
3328 
3329   if (obj != noreg && obj != rax)
3330     pop(obj);
3331 
3332   if(tosca_live) pop(rax);
3333 
3334   bind(done);
3335 }
3336 
3337 void MacroAssembler::g1_write_barrier_post(Register store_addr,
3338                                            Register new_val,
3339                                            Register thread,
3340                                            Register tmp,
3341                                            Register tmp2) {
3342 #ifdef _LP64
3343   assert(thread == r15_thread, "must be");
3344 #endif // _LP64
3345 
3346   Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3347                                        PtrQueue::byte_offset_of_index()));
3348   Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
3349                                        PtrQueue::byte_offset_of_buf()));
3350 
3351   BarrierSet* bs = Universe::heap()->barrier_set();
3352   CardTableModRefBS* ct = (CardTableModRefBS*)bs;
3353   Label done;
3354   Label runtime;
3355 
3356   // Does store cross heap regions?
3357 
3358   movptr(tmp, store_addr);
3359   xorptr(tmp, new_val);
3360   shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
3361   jcc(Assembler::equal, done);
3362 
3363   // crosses regions, storing NULL?
3364 
3365   cmpptr(new_val, (int32_t) NULL_WORD);
3366   jcc(Assembler::equal, done);
3367 
3368   // storing region crossing non-NULL, is card already dirty?
3369 
3370   ExternalAddress cardtable((address) ct->byte_map_base);
3371   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3372 #ifdef _LP64
3373   const Register card_addr = tmp;
3374 
3375   movq(card_addr, store_addr);
3376   shrq(card_addr, CardTableModRefBS::card_shift);
3377 
3378   lea(tmp2, cardtable);
3379 
3380   // get the address of the card
3381   addq(card_addr, tmp2);
3382 #else
3383   const Register card_index = tmp;
3384 
3385   movl(card_index, store_addr);
3386   shrl(card_index, CardTableModRefBS::card_shift);
3387 
3388   Address index(noreg, card_index, Address::times_1);
3389   const Register card_addr = tmp;
3390   lea(card_addr, as_Address(ArrayAddress(cardtable, index)));
3391 #endif
3392   cmpb(Address(card_addr, 0), 0);
3393   jcc(Assembler::equal, done);
3394 
3395   // storing a region crossing, non-NULL oop, card is clean.
3396   // dirty card and log.
3397 
3398   movb(Address(card_addr, 0), 0);
3399 
3400   cmpl(queue_index, 0);
3401   jcc(Assembler::equal, runtime);
3402   subl(queue_index, wordSize);
3403   movptr(tmp2, buffer);
3404 #ifdef _LP64
3405   movslq(rscratch1, queue_index);
3406   addq(tmp2, rscratch1);
3407   movq(Address(tmp2, 0), card_addr);
3408 #else
3409   addl(tmp2, queue_index);
3410   movl(Address(tmp2, 0), card_index);
3411 #endif
3412   jmp(done);
3413 
3414   bind(runtime);
3415   // save the live input values
3416   push(store_addr);
3417   push(new_val);
3418 #ifdef _LP64
3419   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
3420 #else
3421   push(thread);
3422   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
3423   pop(thread);
3424 #endif
3425   pop(new_val);
3426   pop(store_addr);
3427 
3428   bind(done);
3429 }
3430 
3431 #endif // INCLUDE_ALL_GCS
3432 //////////////////////////////////////////////////////////////////////////////////
3433 
3434 
3435 void MacroAssembler::store_check(Register obj) {
3436   // Does a store check for the oop in register obj. The content of
3437   // register obj is destroyed afterwards.
3438   store_check_part_1(obj);
3439   store_check_part_2(obj);
3440 }
3441 
3442 void MacroAssembler::store_check(Register obj, Address dst) {
3443   store_check(obj);
3444 }
3445 
3446 
3447 // split the store check operation so that other instructions can be scheduled inbetween
3448 void MacroAssembler::store_check_part_1(Register obj) {
3449   BarrierSet* bs = Universe::heap()->barrier_set();
3450   assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
3451   shrptr(obj, CardTableModRefBS::card_shift);
3452 }
3453 
3454 void MacroAssembler::store_check_part_2(Register obj) {
3455   BarrierSet* bs = Universe::heap()->barrier_set();
3456   assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
3457   CardTableModRefBS* ct = (CardTableModRefBS*)bs;
3458   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3459 
3460   // The calculation for byte_map_base is as follows:
3461   // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
3462   // So this essentially converts an address to a displacement and
3463   // it will never need to be relocated. On 64bit however the value may be too
3464   // large for a 32bit displacement
3465 
3466   intptr_t disp = (intptr_t) ct->byte_map_base;
3467   if (is_simm32(disp)) {
3468     Address cardtable(noreg, obj, Address::times_1, disp);
3469     movb(cardtable, 0);
3470   } else {
3471     // By doing it as an ExternalAddress disp could be converted to a rip-relative
3472     // displacement and done in a single instruction given favorable mapping and
3473     // a smarter version of as_Address. Worst case it is two instructions which
3474     // is no worse off then loading disp into a register and doing as a simple
3475     // Address() as above.
3476     // We can't do as ExternalAddress as the only style since if disp == 0 we'll
3477     // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
3478     // in some cases we'll get a single instruction version.
3479 
3480     ExternalAddress cardtable((address)disp);
3481     Address index(noreg, obj, Address::times_1);
3482     movb(as_Address(ArrayAddress(cardtable, index)), 0);
3483   }
3484 }
3485 
3486 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3487   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
3488 }
3489 
3490 // Force generation of a 4 byte immediate value even if it fits into 8bit
3491 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3492   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
3493 }
3494 
3495 void MacroAssembler::subptr(Register dst, Register src) {
3496   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
3497 }
3498 
3499 // C++ bool manipulation
3500 void MacroAssembler::testbool(Register dst) {
3501   if(sizeof(bool) == 1)
3502     testb(dst, 0xff);
3503   else if(sizeof(bool) == 2) {
3504     // testw implementation needed for two byte bools
3505     ShouldNotReachHere();
3506   } else if(sizeof(bool) == 4)
3507     testl(dst, dst);
3508   else
3509     // unsupported
3510     ShouldNotReachHere();
3511 }
3512 
3513 void MacroAssembler::testptr(Register dst, Register src) {
3514   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
3515 }
3516 
3517 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3518 void MacroAssembler::tlab_allocate(Register obj,
3519                                    Register var_size_in_bytes,
3520                                    int con_size_in_bytes,
3521                                    Register t1,
3522                                    Register t2,
3523                                    Label& slow_case) {
3524   assert_different_registers(obj, t1, t2);
3525   assert_different_registers(obj, var_size_in_bytes, t1);
3526   Register end = t2;
3527   Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
3528 
3529   verify_tlab();
3530 
3531   NOT_LP64(get_thread(thread));
3532 
3533   movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
3534   if (var_size_in_bytes == noreg) {
3535     lea(end, Address(obj, con_size_in_bytes));
3536   } else {
3537     lea(end, Address(obj, var_size_in_bytes, Address::times_1));
3538   }
3539   cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
3540   jcc(Assembler::above, slow_case);
3541 
3542   // update the tlab top pointer
3543   movptr(Address(thread, JavaThread::tlab_top_offset()), end);
3544 
3545   // recover var_size_in_bytes if necessary
3546   if (var_size_in_bytes == end) {
3547     subptr(var_size_in_bytes, obj);
3548   }
3549   verify_tlab();
3550 }
3551 
3552 // Preserves rbx, and rdx.
3553 Register MacroAssembler::tlab_refill(Label& retry,
3554                                      Label& try_eden,
3555                                      Label& slow_case) {
3556   Register top = rax;
3557   Register t1  = rcx;
3558   Register t2  = rsi;
3559   Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
3560   assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
3561   Label do_refill, discard_tlab;
3562 
3563   if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3564     // No allocation in the shared eden.
3565     jmp(slow_case);
3566   }
3567 
3568   NOT_LP64(get_thread(thread_reg));
3569 
3570   movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
3571   movptr(t1,  Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
3572 
3573   // calculate amount of free space
3574   subptr(t1, top);
3575   shrptr(t1, LogHeapWordSize);
3576 
3577   // Retain tlab and allocate object in shared space if
3578   // the amount free in the tlab is too large to discard.
3579   cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
3580   jcc(Assembler::lessEqual, discard_tlab);
3581 
3582   // Retain
3583   // %%% yuck as movptr...
3584   movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
3585   addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
3586   if (TLABStats) {
3587     // increment number of slow_allocations
3588     addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
3589   }
3590   jmp(try_eden);
3591 
3592   bind(discard_tlab);
3593   if (TLABStats) {
3594     // increment number of refills
3595     addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
3596     // accumulate wastage -- t1 is amount free in tlab
3597     addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
3598   }
3599 
3600   // if tlab is currently allocated (top or end != null) then
3601   // fill [top, end + alignment_reserve) with array object
3602   testptr(top, top);
3603   jcc(Assembler::zero, do_refill);
3604 
3605   // set up the mark word
3606   movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
3607   // set the length to the remaining space
3608   subptr(t1, typeArrayOopDesc::header_size(T_INT));
3609   addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
3610   shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
3611   movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
3612   // set klass to intArrayKlass
3613   // dubious reloc why not an oop reloc?
3614   movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
3615   // store klass last.  concurrent gcs assumes klass length is valid if
3616   // klass field is not null.
3617   store_klass(top, t1);
3618 
3619   movptr(t1, top);
3620   subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
3621   incr_allocated_bytes(thread_reg, t1, 0);
3622 
3623   // refill the tlab with an eden allocation
3624   bind(do_refill);
3625   movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
3626   shlptr(t1, LogHeapWordSize);
3627   // allocate new tlab, address returned in top
3628   eden_allocate(top, t1, 0, t2, slow_case);
3629 
3630   // Check that t1 was preserved in eden_allocate.
3631 #ifdef ASSERT
3632   if (UseTLAB) {
3633     Label ok;
3634     Register tsize = rsi;
3635     assert_different_registers(tsize, thread_reg, t1);
3636     push(tsize);
3637     movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
3638     shlptr(tsize, LogHeapWordSize);
3639     cmpptr(t1, tsize);
3640     jcc(Assembler::equal, ok);
3641     STOP("assert(t1 != tlab size)");
3642     should_not_reach_here();
3643 
3644     bind(ok);
3645     pop(tsize);
3646   }
3647 #endif
3648   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
3649   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
3650   addptr(top, t1);
3651   subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
3652   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
3653   verify_tlab();
3654   jmp(retry);
3655 
3656   return thread_reg; // for use by caller
3657 }
3658 
3659 void MacroAssembler::incr_allocated_bytes(Register thread,
3660                                           Register var_size_in_bytes,
3661                                           int con_size_in_bytes,
3662                                           Register t1) {
3663   if (!thread->is_valid()) {
3664 #ifdef _LP64
3665     thread = r15_thread;
3666 #else
3667     assert(t1->is_valid(), "need temp reg");
3668     thread = t1;
3669     get_thread(thread);
3670 #endif
3671   }
3672 
3673 #ifdef _LP64
3674   if (var_size_in_bytes->is_valid()) {
3675     addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
3676   } else {
3677     addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
3678   }
3679 #else
3680   if (var_size_in_bytes->is_valid()) {
3681     addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
3682   } else {
3683     addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
3684   }
3685   adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
3686 #endif
3687 }
3688 
3689 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
3690   pusha();
3691 
3692   // if we are coming from c1, xmm registers may be live
3693   int off = 0;
3694   if (UseSSE == 1)  {
3695     subptr(rsp, sizeof(jdouble)*8);
3696     movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
3697     movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
3698     movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
3699     movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
3700     movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
3701     movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
3702     movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
3703     movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
3704   } else if (UseSSE >= 2)  {
3705 #ifdef COMPILER2
3706     if (MaxVectorSize > 16) {
3707       assert(UseAVX > 0, "256bit vectors are supported only with AVX");
3708       // Save upper half of YMM registes
3709       subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
3710       vextractf128h(Address(rsp,  0),xmm0);
3711       vextractf128h(Address(rsp, 16),xmm1);
3712       vextractf128h(Address(rsp, 32),xmm2);
3713       vextractf128h(Address(rsp, 48),xmm3);
3714       vextractf128h(Address(rsp, 64),xmm4);
3715       vextractf128h(Address(rsp, 80),xmm5);
3716       vextractf128h(Address(rsp, 96),xmm6);
3717       vextractf128h(Address(rsp,112),xmm7);
3718 #ifdef _LP64
3719       vextractf128h(Address(rsp,128),xmm8);
3720       vextractf128h(Address(rsp,144),xmm9);
3721       vextractf128h(Address(rsp,160),xmm10);
3722       vextractf128h(Address(rsp,176),xmm11);
3723       vextractf128h(Address(rsp,192),xmm12);
3724       vextractf128h(Address(rsp,208),xmm13);
3725       vextractf128h(Address(rsp,224),xmm14);
3726       vextractf128h(Address(rsp,240),xmm15);
3727 #endif
3728     }
3729 #endif
3730     // Save whole 128bit (16 bytes) XMM regiters
3731     subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
3732     movdqu(Address(rsp,off++*16),xmm0);
3733     movdqu(Address(rsp,off++*16),xmm1);
3734     movdqu(Address(rsp,off++*16),xmm2);
3735     movdqu(Address(rsp,off++*16),xmm3);
3736     movdqu(Address(rsp,off++*16),xmm4);
3737     movdqu(Address(rsp,off++*16),xmm5);
3738     movdqu(Address(rsp,off++*16),xmm6);
3739     movdqu(Address(rsp,off++*16),xmm7);
3740 #ifdef _LP64
3741     movdqu(Address(rsp,off++*16),xmm8);
3742     movdqu(Address(rsp,off++*16),xmm9);
3743     movdqu(Address(rsp,off++*16),xmm10);
3744     movdqu(Address(rsp,off++*16),xmm11);
3745     movdqu(Address(rsp,off++*16),xmm12);
3746     movdqu(Address(rsp,off++*16),xmm13);
3747     movdqu(Address(rsp,off++*16),xmm14);
3748     movdqu(Address(rsp,off++*16),xmm15);
3749 #endif
3750   }
3751 
3752   // Preserve registers across runtime call
3753   int incoming_argument_and_return_value_offset = -1;
3754   if (num_fpu_regs_in_use > 1) {
3755     // Must preserve all other FPU regs (could alternatively convert
3756     // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
3757     // FPU state, but can not trust C compiler)
3758     NEEDS_CLEANUP;
3759     // NOTE that in this case we also push the incoming argument(s) to
3760     // the stack and restore it later; we also use this stack slot to
3761     // hold the return value from dsin, dcos etc.
3762     for (int i = 0; i < num_fpu_regs_in_use; i++) {
3763       subptr(rsp, sizeof(jdouble));
3764       fstp_d(Address(rsp, 0));
3765     }
3766     incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
3767     for (int i = nb_args-1; i >= 0; i--) {
3768       fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
3769     }
3770   }
3771 
3772   subptr(rsp, nb_args*sizeof(jdouble));
3773   for (int i = 0; i < nb_args; i++) {
3774     fstp_d(Address(rsp, i*sizeof(jdouble)));
3775   }
3776 
3777 #ifdef _LP64
3778   if (nb_args > 0) {
3779     movdbl(xmm0, Address(rsp, 0));
3780   }
3781   if (nb_args > 1) {
3782     movdbl(xmm1, Address(rsp, sizeof(jdouble)));
3783   }
3784   assert(nb_args <= 2, "unsupported number of args");
3785 #endif // _LP64
3786 
3787   // NOTE: we must not use call_VM_leaf here because that requires a
3788   // complete interpreter frame in debug mode -- same bug as 4387334
3789   // MacroAssembler::call_VM_leaf_base is perfectly safe and will
3790   // do proper 64bit abi
3791 
3792   NEEDS_CLEANUP;
3793   // Need to add stack banging before this runtime call if it needs to
3794   // be taken; however, there is no generic stack banging routine at
3795   // the MacroAssembler level
3796 
3797   MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
3798 
3799 #ifdef _LP64
3800   movsd(Address(rsp, 0), xmm0);
3801   fld_d(Address(rsp, 0));
3802 #endif // _LP64
3803   addptr(rsp, sizeof(jdouble) * nb_args);
3804   if (num_fpu_regs_in_use > 1) {
3805     // Must save return value to stack and then restore entire FPU
3806     // stack except incoming arguments
3807     fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
3808     for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
3809       fld_d(Address(rsp, 0));
3810       addptr(rsp, sizeof(jdouble));
3811     }
3812     fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
3813     addptr(rsp, sizeof(jdouble) * nb_args);
3814   }
3815 
3816   off = 0;
3817   if (UseSSE == 1)  {
3818     movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
3819     movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
3820     movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
3821     movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
3822     movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
3823     movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
3824     movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
3825     movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
3826     addptr(rsp, sizeof(jdouble)*8);
3827   } else if (UseSSE >= 2)  {
3828     // Restore whole 128bit (16 bytes) XMM regiters
3829     movdqu(xmm0, Address(rsp,off++*16));
3830     movdqu(xmm1, Address(rsp,off++*16));
3831     movdqu(xmm2, Address(rsp,off++*16));
3832     movdqu(xmm3, Address(rsp,off++*16));
3833     movdqu(xmm4, Address(rsp,off++*16));
3834     movdqu(xmm5, Address(rsp,off++*16));
3835     movdqu(xmm6, Address(rsp,off++*16));
3836     movdqu(xmm7, Address(rsp,off++*16));
3837 #ifdef _LP64
3838     movdqu(xmm8, Address(rsp,off++*16));
3839     movdqu(xmm9, Address(rsp,off++*16));
3840     movdqu(xmm10, Address(rsp,off++*16));
3841     movdqu(xmm11, Address(rsp,off++*16));
3842     movdqu(xmm12, Address(rsp,off++*16));
3843     movdqu(xmm13, Address(rsp,off++*16));
3844     movdqu(xmm14, Address(rsp,off++*16));
3845     movdqu(xmm15, Address(rsp,off++*16));
3846 #endif
3847     addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
3848 #ifdef COMPILER2
3849     if (MaxVectorSize > 16) {
3850       // Restore upper half of YMM registes.
3851       vinsertf128h(xmm0, Address(rsp,  0));
3852       vinsertf128h(xmm1, Address(rsp, 16));
3853       vinsertf128h(xmm2, Address(rsp, 32));
3854       vinsertf128h(xmm3, Address(rsp, 48));
3855       vinsertf128h(xmm4, Address(rsp, 64));
3856       vinsertf128h(xmm5, Address(rsp, 80));
3857       vinsertf128h(xmm6, Address(rsp, 96));
3858       vinsertf128h(xmm7, Address(rsp,112));
3859 #ifdef _LP64
3860       vinsertf128h(xmm8, Address(rsp,128));
3861       vinsertf128h(xmm9, Address(rsp,144));
3862       vinsertf128h(xmm10, Address(rsp,160));
3863       vinsertf128h(xmm11, Address(rsp,176));
3864       vinsertf128h(xmm12, Address(rsp,192));
3865       vinsertf128h(xmm13, Address(rsp,208));
3866       vinsertf128h(xmm14, Address(rsp,224));
3867       vinsertf128h(xmm15, Address(rsp,240));
3868 #endif
3869       addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
3870     }
3871 #endif
3872   }
3873   popa();
3874 }
3875 
3876 static const double     pi_4 =  0.7853981633974483;
3877 
3878 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
3879   // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
3880   // was attempted in this code; unfortunately it appears that the
3881   // switch to 80-bit precision and back causes this to be
3882   // unprofitable compared with simply performing a runtime call if
3883   // the argument is out of the (-pi/4, pi/4) range.
3884 
3885   Register tmp = noreg;
3886   if (!VM_Version::supports_cmov()) {
3887     // fcmp needs a temporary so preserve rbx,
3888     tmp = rbx;
3889     push(tmp);
3890   }
3891 
3892   Label slow_case, done;
3893 
3894   ExternalAddress pi4_adr = (address)&pi_4;
3895   if (reachable(pi4_adr)) {
3896     // x ?<= pi/4
3897     fld_d(pi4_adr);
3898     fld_s(1);                // Stack:  X  PI/4  X
3899     fabs();                  // Stack: |X| PI/4  X
3900     fcmp(tmp);
3901     jcc(Assembler::above, slow_case);
3902 
3903     // fastest case: -pi/4 <= x <= pi/4
3904     switch(trig) {
3905     case 's':
3906       fsin();
3907       break;
3908     case 'c':
3909       fcos();
3910       break;
3911     case 't':
3912       ftan();
3913       break;
3914     default:
3915       assert(false, "bad intrinsic");
3916       break;
3917     }
3918     jmp(done);
3919   }
3920 
3921   // slow case: runtime call
3922   bind(slow_case);
3923 
3924   switch(trig) {
3925   case 's':
3926     {
3927       fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
3928     }
3929     break;
3930   case 'c':
3931     {
3932       fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
3933     }
3934     break;
3935   case 't':
3936     {
3937       fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
3938     }
3939     break;
3940   default:
3941     assert(false, "bad intrinsic");
3942     break;
3943   }
3944 
3945   // Come here with result in F-TOS
3946   bind(done);
3947 
3948   if (tmp != noreg) {
3949     pop(tmp);
3950   }
3951 }
3952 
3953 
3954 // Look up the method for a megamorphic invokeinterface call.
3955 // The target method is determined by <intf_klass, itable_index>.
3956 // The receiver klass is in recv_klass.
3957 // On success, the result will be in method_result, and execution falls through.
3958 // On failure, execution transfers to the given label.
3959 void MacroAssembler::lookup_interface_method(Register recv_klass,
3960                                              Register intf_klass,
3961                                              RegisterOrConstant itable_index,
3962                                              Register method_result,
3963                                              Register scan_temp,
3964                                              Label& L_no_such_interface) {
3965   assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
3966   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3967          "caller must use same register for non-constant itable index as for method");
3968 
3969   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3970   int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
3971   int itentry_off = itableMethodEntry::method_offset_in_bytes();
3972   int scan_step   = itableOffsetEntry::size() * wordSize;
3973   int vte_size    = vtableEntry::size() * wordSize;
3974   Address::ScaleFactor times_vte_scale = Address::times_ptr;
3975   assert(vte_size == wordSize, "else adjust times_vte_scale");
3976 
3977   movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
3978 
3979   // %%% Could store the aligned, prescaled offset in the klassoop.
3980   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3981   if (HeapWordsPerLong > 1) {
3982     // Round up to align_object_offset boundary
3983     // see code for InstanceKlass::start_of_itable!
3984     round_to(scan_temp, BytesPerLong);
3985   }
3986 
3987   // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3988   assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3989   lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3990 
3991   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
3992   //   if (scan->interface() == intf) {
3993   //     result = (klass + scan->offset() + itable_index);
3994   //   }
3995   // }
3996   Label search, found_method;
3997 
3998   for (int peel = 1; peel >= 0; peel--) {
3999     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4000     cmpptr(intf_klass, method_result);
4001 
4002     if (peel) {
4003       jccb(Assembler::equal, found_method);
4004     } else {
4005       jccb(Assembler::notEqual, search);
4006       // (invert the test to fall through to found_method...)
4007     }
4008 
4009     if (!peel)  break;
4010 
4011     bind(search);
4012 
4013     // Check that the previous entry is non-null.  A null entry means that
4014     // the receiver class doesn't implement the interface, and wasn't the
4015     // same as when the caller was compiled.
4016     testptr(method_result, method_result);
4017     jcc(Assembler::zero, L_no_such_interface);
4018     addptr(scan_temp, scan_step);
4019   }
4020 
4021   bind(found_method);
4022 
4023   // Got a hit.
4024   movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4025   movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4026 }
4027 
4028 
4029 // virtual method calling
4030 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4031                                            RegisterOrConstant vtable_index,
4032                                            Register method_result) {
4033   const int base = InstanceKlass::vtable_start_offset() * wordSize;
4034   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4035   Address vtable_entry_addr(recv_klass,
4036                             vtable_index, Address::times_ptr,
4037                             base + vtableEntry::method_offset_in_bytes());
4038   movptr(method_result, vtable_entry_addr);
4039 }
4040 
4041 
4042 void MacroAssembler::check_klass_subtype(Register sub_klass,
4043                            Register super_klass,
4044                            Register temp_reg,
4045                            Label& L_success) {
4046   Label L_failure;
4047   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
4048   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4049   bind(L_failure);
4050 }
4051 
4052 
4053 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4054                                                    Register super_klass,
4055                                                    Register temp_reg,
4056                                                    Label* L_success,
4057                                                    Label* L_failure,
4058                                                    Label* L_slow_path,
4059                                         RegisterOrConstant super_check_offset) {
4060   assert_different_registers(sub_klass, super_klass, temp_reg);
4061   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4062   if (super_check_offset.is_register()) {
4063     assert_different_registers(sub_klass, super_klass,
4064                                super_check_offset.as_register());
4065   } else if (must_load_sco) {
4066     assert(temp_reg != noreg, "supply either a temp or a register offset");
4067   }
4068 
4069   Label L_fallthrough;
4070   int label_nulls = 0;
4071   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4072   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4073   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4074   assert(label_nulls <= 1, "at most one NULL in the batch");
4075 
4076   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4077   int sco_offset = in_bytes(Klass::super_check_offset_offset());
4078   Address super_check_offset_addr(super_klass, sco_offset);
4079 
4080   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4081   // range of a jccb.  If this routine grows larger, reconsider at
4082   // least some of these.
4083 #define local_jcc(assembler_cond, label)                                \
4084   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
4085   else                             jcc( assembler_cond, label) /*omit semi*/
4086 
4087   // Hacked jmp, which may only be used just before L_fallthrough.
4088 #define final_jmp(label)                                                \
4089   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
4090   else                            jmp(label)                /*omit semi*/
4091 
4092   // If the pointers are equal, we are done (e.g., String[] elements).
4093   // This self-check enables sharing of secondary supertype arrays among
4094   // non-primary types such as array-of-interface.  Otherwise, each such
4095   // type would need its own customized SSA.
4096   // We move this check to the front of the fast path because many
4097   // type checks are in fact trivially successful in this manner,
4098   // so we get a nicely predicted branch right at the start of the check.
4099   cmpptr(sub_klass, super_klass);
4100   local_jcc(Assembler::equal, *L_success);
4101 
4102   // Check the supertype display:
4103   if (must_load_sco) {
4104     // Positive movl does right thing on LP64.
4105     movl(temp_reg, super_check_offset_addr);
4106     super_check_offset = RegisterOrConstant(temp_reg);
4107   }
4108   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4109   cmpptr(super_klass, super_check_addr); // load displayed supertype
4110 
4111   // This check has worked decisively for primary supers.
4112   // Secondary supers are sought in the super_cache ('super_cache_addr').
4113   // (Secondary supers are interfaces and very deeply nested subtypes.)
4114   // This works in the same check above because of a tricky aliasing
4115   // between the super_cache and the primary super display elements.
4116   // (The 'super_check_addr' can address either, as the case requires.)
4117   // Note that the cache is updated below if it does not help us find
4118   // what we need immediately.
4119   // So if it was a primary super, we can just fail immediately.
4120   // Otherwise, it's the slow path for us (no success at this point).
4121 
4122   if (super_check_offset.is_register()) {
4123     local_jcc(Assembler::equal, *L_success);
4124     cmpl(super_check_offset.as_register(), sc_offset);
4125     if (L_failure == &L_fallthrough) {
4126       local_jcc(Assembler::equal, *L_slow_path);
4127     } else {
4128       local_jcc(Assembler::notEqual, *L_failure);
4129       final_jmp(*L_slow_path);
4130     }
4131   } else if (super_check_offset.as_constant() == sc_offset) {
4132     // Need a slow path; fast failure is impossible.
4133     if (L_slow_path == &L_fallthrough) {
4134       local_jcc(Assembler::equal, *L_success);
4135     } else {
4136       local_jcc(Assembler::notEqual, *L_slow_path);
4137       final_jmp(*L_success);
4138     }
4139   } else {
4140     // No slow path; it's a fast decision.
4141     if (L_failure == &L_fallthrough) {
4142       local_jcc(Assembler::equal, *L_success);
4143     } else {
4144       local_jcc(Assembler::notEqual, *L_failure);
4145       final_jmp(*L_success);
4146     }
4147   }
4148 
4149   bind(L_fallthrough);
4150 
4151 #undef local_jcc
4152 #undef final_jmp
4153 }
4154 
4155 
4156 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4157                                                    Register super_klass,
4158                                                    Register temp_reg,
4159                                                    Register temp2_reg,
4160                                                    Label* L_success,
4161                                                    Label* L_failure,
4162                                                    bool set_cond_codes) {
4163   assert_different_registers(sub_klass, super_klass, temp_reg);
4164   if (temp2_reg != noreg)
4165     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4166 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4167 
4168   Label L_fallthrough;
4169   int label_nulls = 0;
4170   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4171   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4172   assert(label_nulls <= 1, "at most one NULL in the batch");
4173 
4174   // a couple of useful fields in sub_klass:
4175   int ss_offset = in_bytes(Klass::secondary_supers_offset());
4176   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4177   Address secondary_supers_addr(sub_klass, ss_offset);
4178   Address super_cache_addr(     sub_klass, sc_offset);
4179 
4180   // Do a linear scan of the secondary super-klass chain.
4181   // This code is rarely used, so simplicity is a virtue here.
4182   // The repne_scan instruction uses fixed registers, which we must spill.
4183   // Don't worry too much about pre-existing connections with the input regs.
4184 
4185   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4186   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4187 
4188   // Get super_klass value into rax (even if it was in rdi or rcx).
4189   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4190   if (super_klass != rax || UseCompressedOops) {
4191     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4192     mov(rax, super_klass);
4193   }
4194   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4195   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4196 
4197 #ifndef PRODUCT
4198   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4199   ExternalAddress pst_counter_addr((address) pst_counter);
4200   NOT_LP64(  incrementl(pst_counter_addr) );
4201   LP64_ONLY( lea(rcx, pst_counter_addr) );
4202   LP64_ONLY( incrementl(Address(rcx, 0)) );
4203 #endif //PRODUCT
4204 
4205   // We will consult the secondary-super array.
4206   movptr(rdi, secondary_supers_addr);
4207   // Load the array length.  (Positive movl does right thing on LP64.)
4208   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4209   // Skip to start of data.
4210   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4211 
4212   // Scan RCX words at [RDI] for an occurrence of RAX.
4213   // Set NZ/Z based on last compare.
4214   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4215   // not change flags (only scas instruction which is repeated sets flags).
4216   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4217 
4218     testptr(rax,rax); // Set Z = 0
4219     repne_scan();
4220 
4221   // Unspill the temp. registers:
4222   if (pushed_rdi)  pop(rdi);
4223   if (pushed_rcx)  pop(rcx);
4224   if (pushed_rax)  pop(rax);
4225 
4226   if (set_cond_codes) {
4227     // Special hack for the AD files:  rdi is guaranteed non-zero.
4228     assert(!pushed_rdi, "rdi must be left non-NULL");
4229     // Also, the condition codes are properly set Z/NZ on succeed/failure.
4230   }
4231 
4232   if (L_failure == &L_fallthrough)
4233         jccb(Assembler::notEqual, *L_failure);
4234   else  jcc(Assembler::notEqual, *L_failure);
4235 
4236   // Success.  Cache the super we found and proceed in triumph.
4237   movptr(super_cache_addr, super_klass);
4238 
4239   if (L_success != &L_fallthrough) {
4240     jmp(*L_success);
4241   }
4242 
4243 #undef IS_A_TEMP
4244 
4245   bind(L_fallthrough);
4246 }
4247 
4248 
4249 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4250   if (VM_Version::supports_cmov()) {
4251     cmovl(cc, dst, src);
4252   } else {
4253     Label L;
4254     jccb(negate_condition(cc), L);
4255     movl(dst, src);
4256     bind(L);
4257   }
4258 }
4259 
4260 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4261   if (VM_Version::supports_cmov()) {
4262     cmovl(cc, dst, src);
4263   } else {
4264     Label L;
4265     jccb(negate_condition(cc), L);
4266     movl(dst, src);
4267     bind(L);
4268   }
4269 }
4270 
4271 void MacroAssembler::verify_oop(Register reg, const char* s) {
4272   if (!VerifyOops) return;
4273 
4274   // Pass register number to verify_oop_subroutine
4275   const char* b = NULL;
4276   {
4277     ResourceMark rm;
4278     stringStream ss;
4279     ss.print("verify_oop: %s: %s", reg->name(), s);
4280     b = code_string(ss.as_string());
4281   }
4282   BLOCK_COMMENT("verify_oop {");
4283 #ifdef _LP64
4284   push(rscratch1);                    // save r10, trashed by movptr()
4285 #endif
4286   push(rax);                          // save rax,
4287   push(reg);                          // pass register argument
4288   ExternalAddress buffer((address) b);
4289   // avoid using pushptr, as it modifies scratch registers
4290   // and our contract is not to modify anything
4291   movptr(rax, buffer.addr());
4292   push(rax);
4293   // call indirectly to solve generation ordering problem
4294   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4295   call(rax);
4296   // Caller pops the arguments (oop, message) and restores rax, r10
4297   BLOCK_COMMENT("} verify_oop");
4298 }
4299 
4300 
4301 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4302                                                       Register tmp,
4303                                                       int offset) {
4304   intptr_t value = *delayed_value_addr;
4305   if (value != 0)
4306     return RegisterOrConstant(value + offset);
4307 
4308   // load indirectly to solve generation ordering problem
4309   movptr(tmp, ExternalAddress((address) delayed_value_addr));
4310 
4311 #ifdef ASSERT
4312   { Label L;
4313     testptr(tmp, tmp);
4314     if (WizardMode) {
4315       const char* buf = NULL;
4316       {
4317         ResourceMark rm;
4318         stringStream ss;
4319         ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
4320         buf = code_string(ss.as_string());
4321       }
4322       jcc(Assembler::notZero, L);
4323       STOP(buf);
4324     } else {
4325       jccb(Assembler::notZero, L);
4326       hlt();
4327     }
4328     bind(L);
4329   }
4330 #endif
4331 
4332   if (offset != 0)
4333     addptr(tmp, offset);
4334 
4335   return RegisterOrConstant(tmp);
4336 }
4337 
4338 
4339 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4340                                          int extra_slot_offset) {
4341   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4342   int stackElementSize = Interpreter::stackElementSize;
4343   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4344 #ifdef ASSERT
4345   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4346   assert(offset1 - offset == stackElementSize, "correct arithmetic");
4347 #endif
4348   Register             scale_reg    = noreg;
4349   Address::ScaleFactor scale_factor = Address::no_scale;
4350   if (arg_slot.is_constant()) {
4351     offset += arg_slot.as_constant() * stackElementSize;
4352   } else {
4353     scale_reg    = arg_slot.as_register();
4354     scale_factor = Address::times(stackElementSize);
4355   }
4356   offset += wordSize;           // return PC is on stack
4357   return Address(rsp, scale_reg, scale_factor, offset);
4358 }
4359 
4360 
4361 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4362   if (!VerifyOops) return;
4363 
4364   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4365   // Pass register number to verify_oop_subroutine
4366   const char* b = NULL;
4367   {
4368     ResourceMark rm;
4369     stringStream ss;
4370     ss.print("verify_oop_addr: %s", s);
4371     b = code_string(ss.as_string());
4372   }
4373 #ifdef _LP64
4374   push(rscratch1);                    // save r10, trashed by movptr()
4375 #endif
4376   push(rax);                          // save rax,
4377   // addr may contain rsp so we will have to adjust it based on the push
4378   // we just did (and on 64 bit we do two pushes)
4379   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4380   // stores rax into addr which is backwards of what was intended.
4381   if (addr.uses(rsp)) {
4382     lea(rax, addr);
4383     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4384   } else {
4385     pushptr(addr);
4386   }
4387 
4388   ExternalAddress buffer((address) b);
4389   // pass msg argument
4390   // avoid using pushptr, as it modifies scratch registers
4391   // and our contract is not to modify anything
4392   movptr(rax, buffer.addr());
4393   push(rax);
4394 
4395   // call indirectly to solve generation ordering problem
4396   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4397   call(rax);
4398   // Caller pops the arguments (addr, message) and restores rax, r10.
4399 }
4400 
4401 void MacroAssembler::verify_tlab() {
4402 #ifdef ASSERT
4403   if (UseTLAB && VerifyOops) {
4404     Label next, ok;
4405     Register t1 = rsi;
4406     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4407 
4408     push(t1);
4409     NOT_LP64(push(thread_reg));
4410     NOT_LP64(get_thread(thread_reg));
4411 
4412     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4413     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4414     jcc(Assembler::aboveEqual, next);
4415     STOP("assert(top >= start)");
4416     should_not_reach_here();
4417 
4418     bind(next);
4419     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4420     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4421     jcc(Assembler::aboveEqual, ok);
4422     STOP("assert(top <= end)");
4423     should_not_reach_here();
4424 
4425     bind(ok);
4426     NOT_LP64(pop(thread_reg));
4427     pop(t1);
4428   }
4429 #endif
4430 }
4431 
4432 class ControlWord {
4433  public:
4434   int32_t _value;
4435 
4436   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
4437   int  precision_control() const       { return  (_value >>  8) & 3      ; }
4438   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4439   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4440   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4441   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4442   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4443   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4444 
4445   void print() const {
4446     // rounding control
4447     const char* rc;
4448     switch (rounding_control()) {
4449       case 0: rc = "round near"; break;
4450       case 1: rc = "round down"; break;
4451       case 2: rc = "round up  "; break;
4452       case 3: rc = "chop      "; break;
4453     };
4454     // precision control
4455     const char* pc;
4456     switch (precision_control()) {
4457       case 0: pc = "24 bits "; break;
4458       case 1: pc = "reserved"; break;
4459       case 2: pc = "53 bits "; break;
4460       case 3: pc = "64 bits "; break;
4461     };
4462     // flags
4463     char f[9];
4464     f[0] = ' ';
4465     f[1] = ' ';
4466     f[2] = (precision   ()) ? 'P' : 'p';
4467     f[3] = (underflow   ()) ? 'U' : 'u';
4468     f[4] = (overflow    ()) ? 'O' : 'o';
4469     f[5] = (zero_divide ()) ? 'Z' : 'z';
4470     f[6] = (denormalized()) ? 'D' : 'd';
4471     f[7] = (invalid     ()) ? 'I' : 'i';
4472     f[8] = '\x0';
4473     // output
4474     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4475   }
4476 
4477 };
4478 
4479 class StatusWord {
4480  public:
4481   int32_t _value;
4482 
4483   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
4484   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
4485   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
4486   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
4487   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
4488   int  top() const                     { return  (_value >> 11) & 7      ; }
4489   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
4490   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
4491   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4492   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4493   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4494   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4495   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4496   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4497 
4498   void print() const {
4499     // condition codes
4500     char c[5];
4501     c[0] = (C3()) ? '3' : '-';
4502     c[1] = (C2()) ? '2' : '-';
4503     c[2] = (C1()) ? '1' : '-';
4504     c[3] = (C0()) ? '0' : '-';
4505     c[4] = '\x0';
4506     // flags
4507     char f[9];
4508     f[0] = (error_status()) ? 'E' : '-';
4509     f[1] = (stack_fault ()) ? 'S' : '-';
4510     f[2] = (precision   ()) ? 'P' : '-';
4511     f[3] = (underflow   ()) ? 'U' : '-';
4512     f[4] = (overflow    ()) ? 'O' : '-';
4513     f[5] = (zero_divide ()) ? 'Z' : '-';
4514     f[6] = (denormalized()) ? 'D' : '-';
4515     f[7] = (invalid     ()) ? 'I' : '-';
4516     f[8] = '\x0';
4517     // output
4518     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
4519   }
4520 
4521 };
4522 
4523 class TagWord {
4524  public:
4525   int32_t _value;
4526 
4527   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
4528 
4529   void print() const {
4530     printf("%04x", _value & 0xFFFF);
4531   }
4532 
4533 };
4534 
4535 class FPU_Register {
4536  public:
4537   int32_t _m0;
4538   int32_t _m1;
4539   int16_t _ex;
4540 
4541   bool is_indefinite() const           {
4542     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4543   }
4544 
4545   void print() const {
4546     char  sign = (_ex < 0) ? '-' : '+';
4547     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
4548     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
4549   };
4550 
4551 };
4552 
4553 class FPU_State {
4554  public:
4555   enum {
4556     register_size       = 10,
4557     number_of_registers =  8,
4558     register_mask       =  7
4559   };
4560 
4561   ControlWord  _control_word;
4562   StatusWord   _status_word;
4563   TagWord      _tag_word;
4564   int32_t      _error_offset;
4565   int32_t      _error_selector;
4566   int32_t      _data_offset;
4567   int32_t      _data_selector;
4568   int8_t       _register[register_size * number_of_registers];
4569 
4570   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4571   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
4572 
4573   const char* tag_as_string(int tag) const {
4574     switch (tag) {
4575       case 0: return "valid";
4576       case 1: return "zero";
4577       case 2: return "special";
4578       case 3: return "empty";
4579     }
4580     ShouldNotReachHere();
4581     return NULL;
4582   }
4583 
4584   void print() const {
4585     // print computation registers
4586     { int t = _status_word.top();
4587       for (int i = 0; i < number_of_registers; i++) {
4588         int j = (i - t) & register_mask;
4589         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4590         st(j)->print();
4591         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4592       }
4593     }
4594     printf("\n");
4595     // print control registers
4596     printf("ctrl = "); _control_word.print(); printf("\n");
4597     printf("stat = "); _status_word .print(); printf("\n");
4598     printf("tags = "); _tag_word    .print(); printf("\n");
4599   }
4600 
4601 };
4602 
4603 class Flag_Register {
4604  public:
4605   int32_t _value;
4606 
4607   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
4608   bool direction() const               { return ((_value >> 10) & 1) != 0; }
4609   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
4610   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
4611   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
4612   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
4613   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
4614 
4615   void print() const {
4616     // flags
4617     char f[8];
4618     f[0] = (overflow       ()) ? 'O' : '-';
4619     f[1] = (direction      ()) ? 'D' : '-';
4620     f[2] = (sign           ()) ? 'S' : '-';
4621     f[3] = (zero           ()) ? 'Z' : '-';
4622     f[4] = (auxiliary_carry()) ? 'A' : '-';
4623     f[5] = (parity         ()) ? 'P' : '-';
4624     f[6] = (carry          ()) ? 'C' : '-';
4625     f[7] = '\x0';
4626     // output
4627     printf("%08x  flags = %s", _value, f);
4628   }
4629 
4630 };
4631 
4632 class IU_Register {
4633  public:
4634   int32_t _value;
4635 
4636   void print() const {
4637     printf("%08x  %11d", _value, _value);
4638   }
4639 
4640 };
4641 
4642 class IU_State {
4643  public:
4644   Flag_Register _eflags;
4645   IU_Register   _rdi;
4646   IU_Register   _rsi;
4647   IU_Register   _rbp;
4648   IU_Register   _rsp;
4649   IU_Register   _rbx;
4650   IU_Register   _rdx;
4651   IU_Register   _rcx;
4652   IU_Register   _rax;
4653 
4654   void print() const {
4655     // computation registers
4656     printf("rax,  = "); _rax.print(); printf("\n");
4657     printf("rbx,  = "); _rbx.print(); printf("\n");
4658     printf("rcx  = "); _rcx.print(); printf("\n");
4659     printf("rdx  = "); _rdx.print(); printf("\n");
4660     printf("rdi  = "); _rdi.print(); printf("\n");
4661     printf("rsi  = "); _rsi.print(); printf("\n");
4662     printf("rbp,  = "); _rbp.print(); printf("\n");
4663     printf("rsp  = "); _rsp.print(); printf("\n");
4664     printf("\n");
4665     // control registers
4666     printf("flgs = "); _eflags.print(); printf("\n");
4667   }
4668 };
4669 
4670 
4671 class CPU_State {
4672  public:
4673   FPU_State _fpu_state;
4674   IU_State  _iu_state;
4675 
4676   void print() const {
4677     printf("--------------------------------------------------\n");
4678     _iu_state .print();
4679     printf("\n");
4680     _fpu_state.print();
4681     printf("--------------------------------------------------\n");
4682   }
4683 
4684 };
4685 
4686 
4687 static void _print_CPU_state(CPU_State* state) {
4688   state->print();
4689 };
4690 
4691 
4692 void MacroAssembler::print_CPU_state() {
4693   push_CPU_state();
4694   push(rsp);                // pass CPU state
4695   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4696   addptr(rsp, wordSize);       // discard argument
4697   pop_CPU_state();
4698 }
4699 
4700 
4701 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4702   static int counter = 0;
4703   FPU_State* fs = &state->_fpu_state;
4704   counter++;
4705   // For leaf calls, only verify that the top few elements remain empty.
4706   // We only need 1 empty at the top for C2 code.
4707   if( stack_depth < 0 ) {
4708     if( fs->tag_for_st(7) != 3 ) {
4709       printf("FPR7 not empty\n");
4710       state->print();
4711       assert(false, "error");
4712       return false;
4713     }
4714     return true;                // All other stack states do not matter
4715   }
4716 
4717   assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
4718          "bad FPU control word");
4719 
4720   // compute stack depth
4721   int i = 0;
4722   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
4723   int d = i;
4724   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4725   // verify findings
4726   if (i != FPU_State::number_of_registers) {
4727     // stack not contiguous
4728     printf("%s: stack not contiguous at ST%d\n", s, i);
4729     state->print();
4730     assert(false, "error");
4731     return false;
4732   }
4733   // check if computed stack depth corresponds to expected stack depth
4734   if (stack_depth < 0) {
4735     // expected stack depth is -stack_depth or less
4736     if (d > -stack_depth) {
4737       // too many elements on the stack
4738       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4739       state->print();
4740       assert(false, "error");
4741       return false;
4742     }
4743   } else {
4744     // expected stack depth is stack_depth
4745     if (d != stack_depth) {
4746       // wrong stack depth
4747       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4748       state->print();
4749       assert(false, "error");
4750       return false;
4751     }
4752   }
4753   // everything is cool
4754   return true;
4755 }
4756 
4757 
4758 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4759   if (!VerifyFPU) return;
4760   push_CPU_state();
4761   push(rsp);                // pass CPU state
4762   ExternalAddress msg((address) s);
4763   // pass message string s
4764   pushptr(msg.addr());
4765   push(stack_depth);        // pass stack depth
4766   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4767   addptr(rsp, 3 * wordSize);   // discard arguments
4768   // check for error
4769   { Label L;
4770     testl(rax, rax);
4771     jcc(Assembler::notZero, L);
4772     int3();                  // break if error condition
4773     bind(L);
4774   }
4775   pop_CPU_state();
4776 }
4777 
4778 void MacroAssembler::restore_cpu_control_state_after_jni() {
4779   // Either restore the MXCSR register after returning from the JNI Call
4780   // or verify that it wasn't changed (with -Xcheck:jni flag).
4781   if (VM_Version::supports_sse()) {
4782     if (RestoreMXCSROnJNICalls) {
4783       ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
4784     } else if (CheckJNICalls) {
4785       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
4786     }
4787   }
4788   if (VM_Version::supports_avx()) {
4789     // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
4790     vzeroupper();
4791   }
4792 
4793 #ifndef _LP64
4794   // Either restore the x87 floating pointer control word after returning
4795   // from the JNI call or verify that it wasn't changed.
4796   if (CheckJNICalls) {
4797     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
4798   }
4799 #endif // _LP64
4800 }
4801 
4802 
4803 void MacroAssembler::load_klass(Register dst, Register src) {
4804 #ifdef _LP64
4805   if (UseCompressedClassPointers) {
4806     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4807     decode_klass_not_null(dst);
4808   } else
4809 #endif
4810     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4811 }
4812 
4813 void MacroAssembler::load_prototype_header(Register dst, Register src) {
4814   load_klass(dst, src);
4815   movptr(dst, Address(dst, Klass::prototype_header_offset()));
4816 }
4817 
4818 void MacroAssembler::store_klass(Register dst, Register src) {
4819 #ifdef _LP64
4820   if (UseCompressedClassPointers) {
4821     encode_klass_not_null(src);
4822     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4823   } else
4824 #endif
4825     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4826 }
4827 
4828 void MacroAssembler::load_heap_oop(Register dst, Address src) {
4829 #ifdef _LP64
4830   // FIXME: Must change all places where we try to load the klass.
4831   if (UseCompressedOops) {
4832     movl(dst, src);
4833     decode_heap_oop(dst);
4834   } else
4835 #endif
4836     movptr(dst, src);
4837 }
4838 
4839 // Doesn't do verfication, generates fixed size code
4840 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
4841 #ifdef _LP64
4842   if (UseCompressedOops) {
4843     movl(dst, src);
4844     decode_heap_oop_not_null(dst);
4845   } else
4846 #endif
4847     movptr(dst, src);
4848 }
4849 
4850 void MacroAssembler::store_heap_oop(Address dst, Register src) {
4851 #ifdef _LP64
4852   if (UseCompressedOops) {
4853     assert(!dst.uses(src), "not enough registers");
4854     encode_heap_oop(src);
4855     movl(dst, src);
4856   } else
4857 #endif
4858     movptr(dst, src);
4859 }
4860 
4861 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
4862   assert_different_registers(src1, tmp);
4863 #ifdef _LP64
4864   if (UseCompressedOops) {
4865     bool did_push = false;
4866     if (tmp == noreg) {
4867       tmp = rax;
4868       push(tmp);
4869       did_push = true;
4870       assert(!src2.uses(rsp), "can't push");
4871     }
4872     load_heap_oop(tmp, src2);
4873     cmpptr(src1, tmp);
4874     if (did_push)  pop(tmp);
4875   } else
4876 #endif
4877     cmpptr(src1, src2);
4878 }
4879 
4880 // Used for storing NULLs.
4881 void MacroAssembler::store_heap_oop_null(Address dst) {
4882 #ifdef _LP64
4883   if (UseCompressedOops) {
4884     movl(dst, (int32_t)NULL_WORD);
4885   } else {
4886     movslq(dst, (int32_t)NULL_WORD);
4887   }
4888 #else
4889   movl(dst, (int32_t)NULL_WORD);
4890 #endif
4891 }
4892 
4893 #ifdef _LP64
4894 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4895   if (UseCompressedClassPointers) {
4896     // Store to klass gap in destination
4897     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
4898   }
4899 }
4900 
4901 #ifdef ASSERT
4902 void MacroAssembler::verify_heapbase(const char* msg) {
4903   assert (UseCompressedOops, "should be compressed");
4904   assert (Universe::heap() != NULL, "java heap should be initialized");
4905   if (CheckCompressedOops) {
4906     Label ok;
4907     push(rscratch1); // cmpptr trashes rscratch1
4908     cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
4909     jcc(Assembler::equal, ok);
4910     STOP(msg);
4911     bind(ok);
4912     pop(rscratch1);
4913   }
4914 }
4915 #endif
4916 
4917 // Algorithm must match oop.inline.hpp encode_heap_oop.
4918 void MacroAssembler::encode_heap_oop(Register r) {
4919 #ifdef ASSERT
4920   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
4921 #endif
4922   verify_oop(r, "broken oop in encode_heap_oop");
4923   if (Universe::narrow_oop_base() == NULL) {
4924     if (Universe::narrow_oop_shift() != 0) {
4925       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4926       shrq(r, LogMinObjAlignmentInBytes);
4927     }
4928     return;
4929   }
4930   testq(r, r);
4931   cmovq(Assembler::equal, r, r12_heapbase);
4932   subq(r, r12_heapbase);
4933   shrq(r, LogMinObjAlignmentInBytes);
4934 }
4935 
4936 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4937 #ifdef ASSERT
4938   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
4939   if (CheckCompressedOops) {
4940     Label ok;
4941     testq(r, r);
4942     jcc(Assembler::notEqual, ok);
4943     STOP("null oop passed to encode_heap_oop_not_null");
4944     bind(ok);
4945   }
4946 #endif
4947   verify_oop(r, "broken oop in encode_heap_oop_not_null");
4948   if (Universe::narrow_oop_base() != NULL) {
4949     subq(r, r12_heapbase);
4950   }
4951   if (Universe::narrow_oop_shift() != 0) {
4952     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4953     shrq(r, LogMinObjAlignmentInBytes);
4954   }
4955 }
4956 
4957 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
4958 #ifdef ASSERT
4959   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
4960   if (CheckCompressedOops) {
4961     Label ok;
4962     testq(src, src);
4963     jcc(Assembler::notEqual, ok);
4964     STOP("null oop passed to encode_heap_oop_not_null2");
4965     bind(ok);
4966   }
4967 #endif
4968   verify_oop(src, "broken oop in encode_heap_oop_not_null2");
4969   if (dst != src) {
4970     movq(dst, src);
4971   }
4972   if (Universe::narrow_oop_base() != NULL) {
4973     subq(dst, r12_heapbase);
4974   }
4975   if (Universe::narrow_oop_shift() != 0) {
4976     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4977     shrq(dst, LogMinObjAlignmentInBytes);
4978   }
4979 }
4980 
4981 void  MacroAssembler::decode_heap_oop(Register r) {
4982 #ifdef ASSERT
4983   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
4984 #endif
4985   if (Universe::narrow_oop_base() == NULL) {
4986     if (Universe::narrow_oop_shift() != 0) {
4987       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4988       shlq(r, LogMinObjAlignmentInBytes);
4989     }
4990   } else {
4991     Label done;
4992     shlq(r, LogMinObjAlignmentInBytes);
4993     jccb(Assembler::equal, done);
4994     addq(r, r12_heapbase);
4995     bind(done);
4996   }
4997   verify_oop(r, "broken oop in decode_heap_oop");
4998 }
4999 
5000 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
5001   // Note: it will change flags
5002   assert (UseCompressedOops, "should only be used for compressed headers");
5003   assert (Universe::heap() != NULL, "java heap should be initialized");
5004   // Cannot assert, unverified entry point counts instructions (see .ad file)
5005   // vtableStubs also counts instructions in pd_code_size_limit.
5006   // Also do not verify_oop as this is called by verify_oop.
5007   if (Universe::narrow_oop_shift() != 0) {
5008     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5009     shlq(r, LogMinObjAlignmentInBytes);
5010     if (Universe::narrow_oop_base() != NULL) {
5011       addq(r, r12_heapbase);
5012     }
5013   } else {
5014     assert (Universe::narrow_oop_base() == NULL, "sanity");
5015   }
5016 }
5017 
5018 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5019   // Note: it will change flags
5020   assert (UseCompressedOops, "should only be used for compressed headers");
5021   assert (Universe::heap() != NULL, "java heap should be initialized");
5022   // Cannot assert, unverified entry point counts instructions (see .ad file)
5023   // vtableStubs also counts instructions in pd_code_size_limit.
5024   // Also do not verify_oop as this is called by verify_oop.
5025   if (Universe::narrow_oop_shift() != 0) {
5026     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5027     if (LogMinObjAlignmentInBytes == Address::times_8) {
5028       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5029     } else {
5030       if (dst != src) {
5031         movq(dst, src);
5032       }
5033       shlq(dst, LogMinObjAlignmentInBytes);
5034       if (Universe::narrow_oop_base() != NULL) {
5035         addq(dst, r12_heapbase);
5036       }
5037     }
5038   } else {
5039     assert (Universe::narrow_oop_base() == NULL, "sanity");
5040     if (dst != src) {
5041       movq(dst, src);
5042     }
5043   }
5044 }
5045 
5046 void MacroAssembler::encode_klass_not_null(Register r) {
5047   assert(Universe::narrow_klass_base() != NULL, "Base should be initialized");
5048   // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5049   assert(r != r12_heapbase, "Encoding a klass in r12");
5050   mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5051   subq(r, r12_heapbase);
5052   if (Universe::narrow_klass_shift() != 0) {
5053     assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5054     shrq(r, LogKlassAlignmentInBytes);
5055   }
5056   reinit_heapbase();
5057 }
5058 
5059 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5060   if (dst == src) {
5061     encode_klass_not_null(src);
5062   } else {
5063     mov64(dst, (int64_t)Universe::narrow_klass_base());
5064     negq(dst);
5065     addq(dst, src);
5066     if (Universe::narrow_klass_shift() != 0) {
5067       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5068       shrq(dst, LogKlassAlignmentInBytes);
5069     }
5070   }
5071 }
5072 
5073 // Function instr_size_for_decode_klass_not_null() counts the instructions
5074 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5075 // when (Universe::heap() != NULL).  Hence, if the instructions they
5076 // generate change, then this method needs to be updated.
5077 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5078   assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5079   // mov64 + addq + shlq? + mov64  (for reinit_heapbase()).
5080   return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5081 }
5082 
5083 // !!! If the instructions that get generated here change then function
5084 // instr_size_for_decode_klass_not_null() needs to get updated.
5085 void  MacroAssembler::decode_klass_not_null(Register r) {
5086   // Note: it will change flags
5087   assert(Universe::narrow_klass_base() != NULL, "Base should be initialized");
5088   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5089   assert(r != r12_heapbase, "Decoding a klass in r12");
5090   // Cannot assert, unverified entry point counts instructions (see .ad file)
5091   // vtableStubs also counts instructions in pd_code_size_limit.
5092   // Also do not verify_oop as this is called by verify_oop.
5093   if (Universe::narrow_klass_shift() != 0) {
5094     assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5095     shlq(r, LogKlassAlignmentInBytes);
5096   }
5097   // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5098   mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5099   addq(r, r12_heapbase);
5100   reinit_heapbase();
5101 }
5102 
5103 void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5104   // Note: it will change flags
5105   assert(Universe::narrow_klass_base() != NULL, "Base should be initialized");
5106   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5107   if (dst == src) {
5108     decode_klass_not_null(dst);
5109   } else {
5110     // Cannot assert, unverified entry point counts instructions (see .ad file)
5111     // vtableStubs also counts instructions in pd_code_size_limit.
5112     // Also do not verify_oop as this is called by verify_oop.
5113 
5114     mov64(dst, (int64_t)Universe::narrow_klass_base());
5115     if (Universe::narrow_klass_shift() != 0) {
5116       assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5117       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5118       leaq(dst, Address(dst, src, Address::times_8, 0));
5119     } else {
5120       addq(dst, src);
5121     }
5122   }
5123 }
5124 
5125 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5126   assert (UseCompressedOops, "should only be used for compressed headers");
5127   assert (Universe::heap() != NULL, "java heap should be initialized");
5128   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5129   int oop_index = oop_recorder()->find_index(obj);
5130   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5131   mov_narrow_oop(dst, oop_index, rspec);
5132 }
5133 
5134 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5135   assert (UseCompressedOops, "should only be used for compressed headers");
5136   assert (Universe::heap() != NULL, "java heap should be initialized");
5137   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5138   int oop_index = oop_recorder()->find_index(obj);
5139   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5140   mov_narrow_oop(dst, oop_index, rspec);
5141 }
5142 
5143 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5144   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5145   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5146   int klass_index = oop_recorder()->find_index(k);
5147   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5148   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5149 }
5150 
5151 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5152   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5153   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5154   int klass_index = oop_recorder()->find_index(k);
5155   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5156   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5157 }
5158 
5159 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5160   assert (UseCompressedOops, "should only be used for compressed headers");
5161   assert (Universe::heap() != NULL, "java heap should be initialized");
5162   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5163   int oop_index = oop_recorder()->find_index(obj);
5164   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5165   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5166 }
5167 
5168 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5169   assert (UseCompressedOops, "should only be used for compressed headers");
5170   assert (Universe::heap() != NULL, "java heap should be initialized");
5171   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5172   int oop_index = oop_recorder()->find_index(obj);
5173   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5174   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5175 }
5176 
5177 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5178   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5179   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5180   int klass_index = oop_recorder()->find_index(k);
5181   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5182   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5183 }
5184 
5185 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5186   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5187   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5188   int klass_index = oop_recorder()->find_index(k);
5189   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5190   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5191 }
5192 
5193 void MacroAssembler::reinit_heapbase() {
5194   if (UseCompressedOops || UseCompressedClassPointers) {
5195     if (Universe::heap() != NULL) {
5196       if (Universe::narrow_oop_base() == NULL) {
5197         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5198       } else {
5199         mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
5200       }
5201     } else {
5202       movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5203     }
5204   }
5205 }
5206 
5207 #endif // _LP64
5208 
5209 
5210 // C2 compiled method's prolog code.
5211 void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) {
5212 
5213   // WARNING: Initial instruction MUST be 5 bytes or longer so that
5214   // NativeJump::patch_verified_entry will be able to patch out the entry
5215   // code safely. The push to verify stack depth is ok at 5 bytes,
5216   // the frame allocation can be either 3 or 6 bytes. So if we don't do
5217   // stack bang then we must use the 6 byte frame allocation even if
5218   // we have no frame. :-(
5219 
5220   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5221   // Remove word for return addr
5222   framesize -= wordSize;
5223 
5224   // Calls to C2R adapters often do not accept exceptional returns.
5225   // We require that their callers must bang for them.  But be careful, because
5226   // some VM calls (such as call site linkage) can use several kilobytes of
5227   // stack.  But the stack safety zone should account for that.
5228   // See bugs 4446381, 4468289, 4497237.
5229   if (stack_bang) {
5230     generate_stack_overflow_check(framesize);
5231 
5232     // We always push rbp, so that on return to interpreter rbp, will be
5233     // restored correctly and we can correct the stack.
5234     push(rbp);
5235     // Remove word for ebp
5236     framesize -= wordSize;
5237 
5238     // Create frame
5239     if (framesize) {
5240       subptr(rsp, framesize);
5241     }
5242   } else {
5243     // Create frame (force generation of a 4 byte immediate value)
5244     subptr_imm32(rsp, framesize);
5245 
5246     // Save RBP register now.
5247     framesize -= wordSize;
5248     movptr(Address(rsp, framesize), rbp);
5249   }
5250 
5251   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5252     framesize -= wordSize;
5253     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5254   }
5255 
5256 #ifndef _LP64
5257   // If method sets FPU control word do it now
5258   if (fp_mode_24b) {
5259     fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5260   }
5261   if (UseSSE >= 2 && VerifyFPU) {
5262     verify_FPU(0, "FPU stack must be clean on entry");
5263   }
5264 #endif
5265 
5266 #ifdef ASSERT
5267   if (VerifyStackAtCalls) {
5268     Label L;
5269     push(rax);
5270     mov(rax, rsp);
5271     andptr(rax, StackAlignmentInBytes-1);
5272     cmpptr(rax, StackAlignmentInBytes-wordSize);
5273     pop(rax);
5274     jcc(Assembler::equal, L);
5275     STOP("Stack is not properly aligned!");
5276     bind(L);
5277   }
5278 #endif
5279 
5280 }
5281 
5282 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
5283   // cnt - number of qwords (8-byte words).
5284   // base - start address, qword aligned.
5285   assert(base==rdi, "base register must be edi for rep stos");
5286   assert(tmp==rax,   "tmp register must be eax for rep stos");
5287   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
5288 
5289   xorptr(tmp, tmp);
5290   if (UseFastStosb) {
5291     shlptr(cnt,3); // convert to number of bytes
5292     rep_stosb();
5293   } else {
5294     NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
5295     rep_stos();
5296   }
5297 }
5298 
5299 // IndexOf for constant substrings with size >= 8 chars
5300 // which don't need to be loaded through stack.
5301 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5302                                       Register cnt1, Register cnt2,
5303                                       int int_cnt2,  Register result,
5304                                       XMMRegister vec, Register tmp) {
5305   ShortBranchVerifier sbv(this);
5306   assert(UseSSE42Intrinsics, "SSE4.2 is required");
5307 
5308   // This method uses pcmpestri inxtruction with bound registers
5309   //   inputs:
5310   //     xmm - substring
5311   //     rax - substring length (elements count)
5312   //     mem - scanned string
5313   //     rdx - string length (elements count)
5314   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5315   //   outputs:
5316   //     rcx - matched index in string
5317   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5318 
5319   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5320         RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5321         MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5322 
5323   // Note, inline_string_indexOf() generates checks:
5324   // if (substr.count > string.count) return -1;
5325   // if (substr.count == 0) return 0;
5326   assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
5327 
5328   // Load substring.
5329   movdqu(vec, Address(str2, 0));
5330   movl(cnt2, int_cnt2);
5331   movptr(result, str1); // string addr
5332 
5333   if (int_cnt2 > 8) {
5334     jmpb(SCAN_TO_SUBSTR);
5335 
5336     // Reload substr for rescan, this code
5337     // is executed only for large substrings (> 8 chars)
5338     bind(RELOAD_SUBSTR);
5339     movdqu(vec, Address(str2, 0));
5340     negptr(cnt2); // Jumped here with negative cnt2, convert to positive
5341 
5342     bind(RELOAD_STR);
5343     // We came here after the beginning of the substring was
5344     // matched but the rest of it was not so we need to search
5345     // again. Start from the next element after the previous match.
5346 
5347     // cnt2 is number of substring reminding elements and
5348     // cnt1 is number of string reminding elements when cmp failed.
5349     // Restored cnt1 = cnt1 - cnt2 + int_cnt2
5350     subl(cnt1, cnt2);
5351     addl(cnt1, int_cnt2);
5352     movl(cnt2, int_cnt2); // Now restore cnt2
5353 
5354     decrementl(cnt1);     // Shift to next element
5355     cmpl(cnt1, cnt2);
5356     jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
5357 
5358     addptr(result, 2);
5359 
5360   } // (int_cnt2 > 8)
5361 
5362   // Scan string for start of substr in 16-byte vectors
5363   bind(SCAN_TO_SUBSTR);
5364   pcmpestri(vec, Address(result, 0), 0x0d);
5365   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
5366   subl(cnt1, 8);
5367   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5368   cmpl(cnt1, cnt2);
5369   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
5370   addptr(result, 16);
5371   jmpb(SCAN_TO_SUBSTR);
5372 
5373   // Found a potential substr
5374   bind(FOUND_CANDIDATE);
5375   // Matched whole vector if first element matched (tmp(rcx) == 0).
5376   if (int_cnt2 == 8) {
5377     jccb(Assembler::overflow, RET_FOUND);    // OF == 1
5378   } else { // int_cnt2 > 8
5379     jccb(Assembler::overflow, FOUND_SUBSTR);
5380   }
5381   // After pcmpestri tmp(rcx) contains matched element index
5382   // Compute start addr of substr
5383   lea(result, Address(result, tmp, Address::times_2));
5384 
5385   // Make sure string is still long enough
5386   subl(cnt1, tmp);
5387   cmpl(cnt1, cnt2);
5388   if (int_cnt2 == 8) {
5389     jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5390   } else { // int_cnt2 > 8
5391     jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
5392   }
5393   // Left less then substring.
5394 
5395   bind(RET_NOT_FOUND);
5396   movl(result, -1);
5397   jmpb(EXIT);
5398 
5399   if (int_cnt2 > 8) {
5400     // This code is optimized for the case when whole substring
5401     // is matched if its head is matched.
5402     bind(MATCH_SUBSTR_HEAD);
5403     pcmpestri(vec, Address(result, 0), 0x0d);
5404     // Reload only string if does not match
5405     jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
5406 
5407     Label CONT_SCAN_SUBSTR;
5408     // Compare the rest of substring (> 8 chars).
5409     bind(FOUND_SUBSTR);
5410     // First 8 chars are already matched.
5411     negptr(cnt2);
5412     addptr(cnt2, 8);
5413 
5414     bind(SCAN_SUBSTR);
5415     subl(cnt1, 8);
5416     cmpl(cnt2, -8); // Do not read beyond substring
5417     jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
5418     // Back-up strings to avoid reading beyond substring:
5419     // cnt1 = cnt1 - cnt2 + 8
5420     addl(cnt1, cnt2); // cnt2 is negative
5421     addl(cnt1, 8);
5422     movl(cnt2, 8); negptr(cnt2);
5423     bind(CONT_SCAN_SUBSTR);
5424     if (int_cnt2 < (int)G) {
5425       movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
5426       pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
5427     } else {
5428       // calculate index in register to avoid integer overflow (int_cnt2*2)
5429       movl(tmp, int_cnt2);
5430       addptr(tmp, cnt2);
5431       movdqu(vec, Address(str2, tmp, Address::times_2, 0));
5432       pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
5433     }
5434     // Need to reload strings pointers if not matched whole vector
5435     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
5436     addptr(cnt2, 8);
5437     jcc(Assembler::negative, SCAN_SUBSTR);
5438     // Fall through if found full substring
5439 
5440   } // (int_cnt2 > 8)
5441 
5442   bind(RET_FOUND);
5443   // Found result if we matched full small substring.
5444   // Compute substr offset
5445   subptr(result, str1);
5446   shrl(result, 1); // index
5447   bind(EXIT);
5448 
5449 } // string_indexofC8
5450 
5451 // Small strings are loaded through stack if they cross page boundary.
5452 void MacroAssembler::string_indexof(Register str1, Register str2,
5453                                     Register cnt1, Register cnt2,
5454                                     int int_cnt2,  Register result,
5455                                     XMMRegister vec, Register tmp) {
5456   ShortBranchVerifier sbv(this);
5457   assert(UseSSE42Intrinsics, "SSE4.2 is required");
5458   //
5459   // int_cnt2 is length of small (< 8 chars) constant substring
5460   // or (-1) for non constant substring in which case its length
5461   // is in cnt2 register.
5462   //
5463   // Note, inline_string_indexOf() generates checks:
5464   // if (substr.count > string.count) return -1;
5465   // if (substr.count == 0) return 0;
5466   //
5467   assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
5468 
5469   // This method uses pcmpestri inxtruction with bound registers
5470   //   inputs:
5471   //     xmm - substring
5472   //     rax - substring length (elements count)
5473   //     mem - scanned string
5474   //     rdx - string length (elements count)
5475   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5476   //   outputs:
5477   //     rcx - matched index in string
5478   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5479 
5480   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
5481         RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
5482         FOUND_CANDIDATE;
5483 
5484   { //========================================================
5485     // We don't know where these strings are located
5486     // and we can't read beyond them. Load them through stack.
5487     Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
5488 
5489     movptr(tmp, rsp); // save old SP
5490 
5491     if (int_cnt2 > 0) {     // small (< 8 chars) constant substring
5492       if (int_cnt2 == 1) {  // One char
5493         load_unsigned_short(result, Address(str2, 0));
5494         movdl(vec, result); // move 32 bits
5495       } else if (int_cnt2 == 2) { // Two chars
5496         movdl(vec, Address(str2, 0)); // move 32 bits
5497       } else if (int_cnt2 == 4) { // Four chars
5498         movq(vec, Address(str2, 0));  // move 64 bits
5499       } else { // cnt2 = { 3, 5, 6, 7 }
5500         // Array header size is 12 bytes in 32-bit VM
5501         // + 6 bytes for 3 chars == 18 bytes,
5502         // enough space to load vec and shift.
5503         assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
5504         movdqu(vec, Address(str2, (int_cnt2*2)-16));
5505         psrldq(vec, 16-(int_cnt2*2));
5506       }
5507     } else { // not constant substring
5508       cmpl(cnt2, 8);
5509       jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
5510 
5511       // We can read beyond string if srt+16 does not cross page boundary
5512       // since heaps are aligned and mapped by pages.
5513       assert(os::vm_page_size() < (int)G, "default page should be small");
5514       movl(result, str2); // We need only low 32 bits
5515       andl(result, (os::vm_page_size()-1));
5516       cmpl(result, (os::vm_page_size()-16));
5517       jccb(Assembler::belowEqual, CHECK_STR);
5518 
5519       // Move small strings to stack to allow load 16 bytes into vec.
5520       subptr(rsp, 16);
5521       int stk_offset = wordSize-2;
5522       push(cnt2);
5523 
5524       bind(COPY_SUBSTR);
5525       load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
5526       movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
5527       decrement(cnt2);
5528       jccb(Assembler::notZero, COPY_SUBSTR);
5529 
5530       pop(cnt2);
5531       movptr(str2, rsp);  // New substring address
5532     } // non constant
5533 
5534     bind(CHECK_STR);
5535     cmpl(cnt1, 8);
5536     jccb(Assembler::aboveEqual, BIG_STRINGS);
5537 
5538     // Check cross page boundary.
5539     movl(result, str1); // We need only low 32 bits
5540     andl(result, (os::vm_page_size()-1));
5541     cmpl(result, (os::vm_page_size()-16));
5542     jccb(Assembler::belowEqual, BIG_STRINGS);
5543 
5544     subptr(rsp, 16);
5545     int stk_offset = -2;
5546     if (int_cnt2 < 0) { // not constant
5547       push(cnt2);
5548       stk_offset += wordSize;
5549     }
5550     movl(cnt2, cnt1);
5551 
5552     bind(COPY_STR);
5553     load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
5554     movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
5555     decrement(cnt2);
5556     jccb(Assembler::notZero, COPY_STR);
5557 
5558     if (int_cnt2 < 0) { // not constant
5559       pop(cnt2);
5560     }
5561     movptr(str1, rsp);  // New string address
5562 
5563     bind(BIG_STRINGS);
5564     // Load substring.
5565     if (int_cnt2 < 0) { // -1
5566       movdqu(vec, Address(str2, 0));
5567       push(cnt2);       // substr count
5568       push(str2);       // substr addr
5569       push(str1);       // string addr
5570     } else {
5571       // Small (< 8 chars) constant substrings are loaded already.
5572       movl(cnt2, int_cnt2);
5573     }
5574     push(tmp);  // original SP
5575 
5576   } // Finished loading
5577 
5578   //========================================================
5579   // Start search
5580   //
5581 
5582   movptr(result, str1); // string addr
5583 
5584   if (int_cnt2  < 0) {  // Only for non constant substring
5585     jmpb(SCAN_TO_SUBSTR);
5586 
5587     // SP saved at sp+0
5588     // String saved at sp+1*wordSize
5589     // Substr saved at sp+2*wordSize
5590     // Substr count saved at sp+3*wordSize
5591 
5592     // Reload substr for rescan, this code
5593     // is executed only for large substrings (> 8 chars)
5594     bind(RELOAD_SUBSTR);
5595     movptr(str2, Address(rsp, 2*wordSize));
5596     movl(cnt2, Address(rsp, 3*wordSize));
5597     movdqu(vec, Address(str2, 0));
5598     // We came here after the beginning of the substring was
5599     // matched but the rest of it was not so we need to search
5600     // again. Start from the next element after the previous match.
5601     subptr(str1, result); // Restore counter
5602     shrl(str1, 1);
5603     addl(cnt1, str1);
5604     decrementl(cnt1);   // Shift to next element
5605     cmpl(cnt1, cnt2);
5606     jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
5607 
5608     addptr(result, 2);
5609   } // non constant
5610 
5611   // Scan string for start of substr in 16-byte vectors
5612   bind(SCAN_TO_SUBSTR);
5613   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5614   pcmpestri(vec, Address(result, 0), 0x0d);
5615   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
5616   subl(cnt1, 8);
5617   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5618   cmpl(cnt1, cnt2);
5619   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
5620   addptr(result, 16);
5621 
5622   bind(ADJUST_STR);
5623   cmpl(cnt1, 8); // Do not read beyond string
5624   jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5625   // Back-up string to avoid reading beyond string.
5626   lea(result, Address(result, cnt1, Address::times_2, -16));
5627   movl(cnt1, 8);
5628   jmpb(SCAN_TO_SUBSTR);
5629 
5630   // Found a potential substr
5631   bind(FOUND_CANDIDATE);
5632   // After pcmpestri tmp(rcx) contains matched element index
5633 
5634   // Make sure string is still long enough
5635   subl(cnt1, tmp);
5636   cmpl(cnt1, cnt2);
5637   jccb(Assembler::greaterEqual, FOUND_SUBSTR);
5638   // Left less then substring.
5639 
5640   bind(RET_NOT_FOUND);
5641   movl(result, -1);
5642   jmpb(CLEANUP);
5643 
5644   bind(FOUND_SUBSTR);
5645   // Compute start addr of substr
5646   lea(result, Address(result, tmp, Address::times_2));
5647 
5648   if (int_cnt2 > 0) { // Constant substring
5649     // Repeat search for small substring (< 8 chars)
5650     // from new point without reloading substring.
5651     // Have to check that we don't read beyond string.
5652     cmpl(tmp, 8-int_cnt2);
5653     jccb(Assembler::greater, ADJUST_STR);
5654     // Fall through if matched whole substring.
5655   } else { // non constant
5656     assert(int_cnt2 == -1, "should be != 0");
5657 
5658     addl(tmp, cnt2);
5659     // Found result if we matched whole substring.
5660     cmpl(tmp, 8);
5661     jccb(Assembler::lessEqual, RET_FOUND);
5662 
5663     // Repeat search for small substring (<= 8 chars)
5664     // from new point 'str1' without reloading substring.
5665     cmpl(cnt2, 8);
5666     // Have to check that we don't read beyond string.
5667     jccb(Assembler::lessEqual, ADJUST_STR);
5668 
5669     Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
5670     // Compare the rest of substring (> 8 chars).
5671     movptr(str1, result);
5672 
5673     cmpl(tmp, cnt2);
5674     // First 8 chars are already matched.
5675     jccb(Assembler::equal, CHECK_NEXT);
5676 
5677     bind(SCAN_SUBSTR);
5678     pcmpestri(vec, Address(str1, 0), 0x0d);
5679     // Need to reload strings pointers if not matched whole vector
5680     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
5681 
5682     bind(CHECK_NEXT);
5683     subl(cnt2, 8);
5684     jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
5685     addptr(str1, 16);
5686     addptr(str2, 16);
5687     subl(cnt1, 8);
5688     cmpl(cnt2, 8); // Do not read beyond substring
5689     jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
5690     // Back-up strings to avoid reading beyond substring.
5691     lea(str2, Address(str2, cnt2, Address::times_2, -16));
5692     lea(str1, Address(str1, cnt2, Address::times_2, -16));
5693     subl(cnt1, cnt2);
5694     movl(cnt2, 8);
5695     addl(cnt1, 8);
5696     bind(CONT_SCAN_SUBSTR);
5697     movdqu(vec, Address(str2, 0));
5698     jmpb(SCAN_SUBSTR);
5699 
5700     bind(RET_FOUND_LONG);
5701     movptr(str1, Address(rsp, wordSize));
5702   } // non constant
5703 
5704   bind(RET_FOUND);
5705   // Compute substr offset
5706   subptr(result, str1);
5707   shrl(result, 1); // index
5708 
5709   bind(CLEANUP);
5710   pop(rsp); // restore SP
5711 
5712 } // string_indexof
5713 
5714 // Compare strings.
5715 void MacroAssembler::string_compare(Register str1, Register str2,
5716                                     Register cnt1, Register cnt2, Register result,
5717                                     XMMRegister vec1) {
5718   ShortBranchVerifier sbv(this);
5719   Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
5720 
5721   // Compute the minimum of the string lengths and the
5722   // difference of the string lengths (stack).
5723   // Do the conditional move stuff
5724   movl(result, cnt1);
5725   subl(cnt1, cnt2);
5726   push(cnt1);
5727   cmov32(Assembler::lessEqual, cnt2, result);
5728 
5729   // Is the minimum length zero?
5730   testl(cnt2, cnt2);
5731   jcc(Assembler::zero, LENGTH_DIFF_LABEL);
5732 
5733   // Compare first characters
5734   load_unsigned_short(result, Address(str1, 0));
5735   load_unsigned_short(cnt1, Address(str2, 0));
5736   subl(result, cnt1);
5737   jcc(Assembler::notZero,  POP_LABEL);
5738   cmpl(cnt2, 1);
5739   jcc(Assembler::equal, LENGTH_DIFF_LABEL);
5740 
5741   // Check if the strings start at the same location.
5742   cmpptr(str1, str2);
5743   jcc(Assembler::equal, LENGTH_DIFF_LABEL);
5744 
5745   Address::ScaleFactor scale = Address::times_2;
5746   int stride = 8;
5747 
5748   if (UseAVX >= 2 && UseSSE42Intrinsics) {
5749     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
5750     Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
5751     Label COMPARE_TAIL_LONG;
5752     int pcmpmask = 0x19;
5753 
5754     // Setup to compare 16-chars (32-bytes) vectors,
5755     // start from first character again because it has aligned address.
5756     int stride2 = 16;
5757     int adr_stride  = stride  << scale;
5758     int adr_stride2 = stride2 << scale;
5759 
5760     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
5761     // rax and rdx are used by pcmpestri as elements counters
5762     movl(result, cnt2);
5763     andl(cnt2, ~(stride2-1));   // cnt2 holds the vector count
5764     jcc(Assembler::zero, COMPARE_TAIL_LONG);
5765 
5766     // fast path : compare first 2 8-char vectors.
5767     bind(COMPARE_16_CHARS);
5768     movdqu(vec1, Address(str1, 0));
5769     pcmpestri(vec1, Address(str2, 0), pcmpmask);
5770     jccb(Assembler::below, COMPARE_INDEX_CHAR);
5771 
5772     movdqu(vec1, Address(str1, adr_stride));
5773     pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
5774     jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
5775     addl(cnt1, stride);
5776 
5777     // Compare the characters at index in cnt1
5778     bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
5779     load_unsigned_short(result, Address(str1, cnt1, scale));
5780     load_unsigned_short(cnt2, Address(str2, cnt1, scale));
5781     subl(result, cnt2);
5782     jmp(POP_LABEL);
5783 
5784     // Setup the registers to start vector comparison loop
5785     bind(COMPARE_WIDE_VECTORS);
5786     lea(str1, Address(str1, result, scale));
5787     lea(str2, Address(str2, result, scale));
5788     subl(result, stride2);
5789     subl(cnt2, stride2);
5790     jccb(Assembler::zero, COMPARE_WIDE_TAIL);
5791     negptr(result);
5792 
5793     //  In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
5794     bind(COMPARE_WIDE_VECTORS_LOOP);
5795     vmovdqu(vec1, Address(str1, result, scale));
5796     vpxor(vec1, Address(str2, result, scale));
5797     vptest(vec1, vec1);
5798     jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
5799     addptr(result, stride2);
5800     subl(cnt2, stride2);
5801     jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
5802     // clean upper bits of YMM registers
5803     vzeroupper();
5804 
5805     // compare wide vectors tail
5806     bind(COMPARE_WIDE_TAIL);
5807     testptr(result, result);
5808     jccb(Assembler::zero, LENGTH_DIFF_LABEL);
5809 
5810     movl(result, stride2);
5811     movl(cnt2, result);
5812     negptr(result);
5813     jmpb(COMPARE_WIDE_VECTORS_LOOP);
5814 
5815     // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
5816     bind(VECTOR_NOT_EQUAL);
5817     // clean upper bits of YMM registers
5818     vzeroupper();
5819     lea(str1, Address(str1, result, scale));
5820     lea(str2, Address(str2, result, scale));
5821     jmp(COMPARE_16_CHARS);
5822 
5823     // Compare tail chars, length between 1 to 15 chars
5824     bind(COMPARE_TAIL_LONG);
5825     movl(cnt2, result);
5826     cmpl(cnt2, stride);
5827     jccb(Assembler::less, COMPARE_SMALL_STR);
5828 
5829     movdqu(vec1, Address(str1, 0));
5830     pcmpestri(vec1, Address(str2, 0), pcmpmask);
5831     jcc(Assembler::below, COMPARE_INDEX_CHAR);
5832     subptr(cnt2, stride);
5833     jccb(Assembler::zero, LENGTH_DIFF_LABEL);
5834     lea(str1, Address(str1, result, scale));
5835     lea(str2, Address(str2, result, scale));
5836     negptr(cnt2);
5837     jmpb(WHILE_HEAD_LABEL);
5838 
5839     bind(COMPARE_SMALL_STR);
5840   } else if (UseSSE42Intrinsics) {
5841     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
5842     int pcmpmask = 0x19;
5843     // Setup to compare 8-char (16-byte) vectors,
5844     // start from first character again because it has aligned address.
5845     movl(result, cnt2);
5846     andl(cnt2, ~(stride - 1));   // cnt2 holds the vector count
5847     jccb(Assembler::zero, COMPARE_TAIL);
5848 
5849     lea(str1, Address(str1, result, scale));
5850     lea(str2, Address(str2, result, scale));
5851     negptr(result);
5852 
5853     // pcmpestri
5854     //   inputs:
5855     //     vec1- substring
5856     //     rax - negative string length (elements count)
5857     //     mem - scaned string
5858     //     rdx - string length (elements count)
5859     //     pcmpmask - cmp mode: 11000 (string compare with negated result)
5860     //               + 00 (unsigned bytes) or  + 01 (unsigned shorts)
5861     //   outputs:
5862     //     rcx - first mismatched element index
5863     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
5864 
5865     bind(COMPARE_WIDE_VECTORS);
5866     movdqu(vec1, Address(str1, result, scale));
5867     pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
5868     // After pcmpestri cnt1(rcx) contains mismatched element index
5869 
5870     jccb(Assembler::below, VECTOR_NOT_EQUAL);  // CF==1
5871     addptr(result, stride);
5872     subptr(cnt2, stride);
5873     jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
5874 
5875     // compare wide vectors tail
5876     testptr(result, result);
5877     jccb(Assembler::zero, LENGTH_DIFF_LABEL);
5878 
5879     movl(cnt2, stride);
5880     movl(result, stride);
5881     negptr(result);
5882     movdqu(vec1, Address(str1, result, scale));
5883     pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
5884     jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
5885 
5886     // Mismatched characters in the vectors
5887     bind(VECTOR_NOT_EQUAL);
5888     addptr(cnt1, result);
5889     load_unsigned_short(result, Address(str1, cnt1, scale));
5890     load_unsigned_short(cnt2, Address(str2, cnt1, scale));
5891     subl(result, cnt2);
5892     jmpb(POP_LABEL);
5893 
5894     bind(COMPARE_TAIL); // limit is zero
5895     movl(cnt2, result);
5896     // Fallthru to tail compare
5897   }
5898   // Shift str2 and str1 to the end of the arrays, negate min
5899   lea(str1, Address(str1, cnt2, scale));
5900   lea(str2, Address(str2, cnt2, scale));
5901   decrementl(cnt2);  // first character was compared already
5902   negptr(cnt2);
5903 
5904   // Compare the rest of the elements
5905   bind(WHILE_HEAD_LABEL);
5906   load_unsigned_short(result, Address(str1, cnt2, scale, 0));
5907   load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
5908   subl(result, cnt1);
5909   jccb(Assembler::notZero, POP_LABEL);
5910   increment(cnt2);
5911   jccb(Assembler::notZero, WHILE_HEAD_LABEL);
5912 
5913   // Strings are equal up to min length.  Return the length difference.
5914   bind(LENGTH_DIFF_LABEL);
5915   pop(result);
5916   jmpb(DONE_LABEL);
5917 
5918   // Discard the stored length difference
5919   bind(POP_LABEL);
5920   pop(cnt1);
5921 
5922   // That's it
5923   bind(DONE_LABEL);
5924 }
5925 
5926 // Compare char[] arrays aligned to 4 bytes or substrings.
5927 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
5928                                         Register limit, Register result, Register chr,
5929                                         XMMRegister vec1, XMMRegister vec2) {
5930   ShortBranchVerifier sbv(this);
5931   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
5932 
5933   int length_offset  = arrayOopDesc::length_offset_in_bytes();
5934   int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);
5935 
5936   // Check the input args
5937   cmpptr(ary1, ary2);
5938   jcc(Assembler::equal, TRUE_LABEL);
5939 
5940   if (is_array_equ) {
5941     // Need additional checks for arrays_equals.
5942     testptr(ary1, ary1);
5943     jcc(Assembler::zero, FALSE_LABEL);
5944     testptr(ary2, ary2);
5945     jcc(Assembler::zero, FALSE_LABEL);
5946 
5947     // Check the lengths
5948     movl(limit, Address(ary1, length_offset));
5949     cmpl(limit, Address(ary2, length_offset));
5950     jcc(Assembler::notEqual, FALSE_LABEL);
5951   }
5952 
5953   // count == 0
5954   testl(limit, limit);
5955   jcc(Assembler::zero, TRUE_LABEL);
5956 
5957   if (is_array_equ) {
5958     // Load array address
5959     lea(ary1, Address(ary1, base_offset));
5960     lea(ary2, Address(ary2, base_offset));
5961   }
5962 
5963   shll(limit, 1);      // byte count != 0
5964   movl(result, limit); // copy
5965 
5966   if (UseAVX >= 2) {
5967     // With AVX2, use 32-byte vector compare
5968     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
5969 
5970     // Compare 32-byte vectors
5971     andl(result, 0x0000001e);  //   tail count (in bytes)
5972     andl(limit, 0xffffffe0);   // vector count (in bytes)
5973     jccb(Assembler::zero, COMPARE_TAIL);
5974 
5975     lea(ary1, Address(ary1, limit, Address::times_1));
5976     lea(ary2, Address(ary2, limit, Address::times_1));
5977     negptr(limit);
5978 
5979     bind(COMPARE_WIDE_VECTORS);
5980     vmovdqu(vec1, Address(ary1, limit, Address::times_1));
5981     vmovdqu(vec2, Address(ary2, limit, Address::times_1));
5982     vpxor(vec1, vec2);
5983 
5984     vptest(vec1, vec1);
5985     jccb(Assembler::notZero, FALSE_LABEL);
5986     addptr(limit, 32);
5987     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
5988 
5989     testl(result, result);
5990     jccb(Assembler::zero, TRUE_LABEL);
5991 
5992     vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
5993     vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
5994     vpxor(vec1, vec2);
5995 
5996     vptest(vec1, vec1);
5997     jccb(Assembler::notZero, FALSE_LABEL);
5998     jmpb(TRUE_LABEL);
5999 
6000     bind(COMPARE_TAIL); // limit is zero
6001     movl(limit, result);
6002     // Fallthru to tail compare
6003   } else if (UseSSE42Intrinsics) {
6004     // With SSE4.2, use double quad vector compare
6005     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6006 
6007     // Compare 16-byte vectors
6008     andl(result, 0x0000000e);  //   tail count (in bytes)
6009     andl(limit, 0xfffffff0);   // vector count (in bytes)
6010     jccb(Assembler::zero, COMPARE_TAIL);
6011 
6012     lea(ary1, Address(ary1, limit, Address::times_1));
6013     lea(ary2, Address(ary2, limit, Address::times_1));
6014     negptr(limit);
6015 
6016     bind(COMPARE_WIDE_VECTORS);
6017     movdqu(vec1, Address(ary1, limit, Address::times_1));
6018     movdqu(vec2, Address(ary2, limit, Address::times_1));
6019     pxor(vec1, vec2);
6020 
6021     ptest(vec1, vec1);
6022     jccb(Assembler::notZero, FALSE_LABEL);
6023     addptr(limit, 16);
6024     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6025 
6026     testl(result, result);
6027     jccb(Assembler::zero, TRUE_LABEL);
6028 
6029     movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6030     movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6031     pxor(vec1, vec2);
6032 
6033     ptest(vec1, vec1);
6034     jccb(Assembler::notZero, FALSE_LABEL);
6035     jmpb(TRUE_LABEL);
6036 
6037     bind(COMPARE_TAIL); // limit is zero
6038     movl(limit, result);
6039     // Fallthru to tail compare
6040   }
6041 
6042   // Compare 4-byte vectors
6043   andl(limit, 0xfffffffc); // vector count (in bytes)
6044   jccb(Assembler::zero, COMPARE_CHAR);
6045 
6046   lea(ary1, Address(ary1, limit, Address::times_1));
6047   lea(ary2, Address(ary2, limit, Address::times_1));
6048   negptr(limit);
6049 
6050   bind(COMPARE_VECTORS);
6051   movl(chr, Address(ary1, limit, Address::times_1));
6052   cmpl(chr, Address(ary2, limit, Address::times_1));
6053   jccb(Assembler::notEqual, FALSE_LABEL);
6054   addptr(limit, 4);
6055   jcc(Assembler::notZero, COMPARE_VECTORS);
6056 
6057   // Compare trailing char (final 2 bytes), if any
6058   bind(COMPARE_CHAR);
6059   testl(result, 0x2);   // tail  char
6060   jccb(Assembler::zero, TRUE_LABEL);
6061   load_unsigned_short(chr, Address(ary1, 0));
6062   load_unsigned_short(limit, Address(ary2, 0));
6063   cmpl(chr, limit);
6064   jccb(Assembler::notEqual, FALSE_LABEL);
6065 
6066   bind(TRUE_LABEL);
6067   movl(result, 1);   // return true
6068   jmpb(DONE);
6069 
6070   bind(FALSE_LABEL);
6071   xorl(result, result); // return false
6072 
6073   // That's it
6074   bind(DONE);
6075   if (UseAVX >= 2) {
6076     // clean upper bits of YMM registers
6077     vzeroupper();
6078   }
6079 }
6080 
6081 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6082                                    Register to, Register value, Register count,
6083                                    Register rtmp, XMMRegister xtmp) {
6084   ShortBranchVerifier sbv(this);
6085   assert_different_registers(to, value, count, rtmp);
6086   Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6087   Label L_fill_2_bytes, L_fill_4_bytes;
6088 
6089   int shift = -1;
6090   switch (t) {
6091     case T_BYTE:
6092       shift = 2;
6093       break;
6094     case T_SHORT:
6095       shift = 1;
6096       break;
6097     case T_INT:
6098       shift = 0;
6099       break;
6100     default: ShouldNotReachHere();
6101   }
6102 
6103   if (t == T_BYTE) {
6104     andl(value, 0xff);
6105     movl(rtmp, value);
6106     shll(rtmp, 8);
6107     orl(value, rtmp);
6108   }
6109   if (t == T_SHORT) {
6110     andl(value, 0xffff);
6111   }
6112   if (t == T_BYTE || t == T_SHORT) {
6113     movl(rtmp, value);
6114     shll(rtmp, 16);
6115     orl(value, rtmp);
6116   }
6117 
6118   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6119   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6120   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6121     // align source address at 4 bytes address boundary
6122     if (t == T_BYTE) {
6123       // One byte misalignment happens only for byte arrays
6124       testptr(to, 1);
6125       jccb(Assembler::zero, L_skip_align1);
6126       movb(Address(to, 0), value);
6127       increment(to);
6128       decrement(count);
6129       BIND(L_skip_align1);
6130     }
6131     // Two bytes misalignment happens only for byte and short (char) arrays
6132     testptr(to, 2);
6133     jccb(Assembler::zero, L_skip_align2);
6134     movw(Address(to, 0), value);
6135     addptr(to, 2);
6136     subl(count, 1<<(shift-1));
6137     BIND(L_skip_align2);
6138   }
6139   if (UseSSE < 2) {
6140     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6141     // Fill 32-byte chunks
6142     subl(count, 8 << shift);
6143     jcc(Assembler::less, L_check_fill_8_bytes);
6144     align(16);
6145 
6146     BIND(L_fill_32_bytes_loop);
6147 
6148     for (int i = 0; i < 32; i += 4) {
6149       movl(Address(to, i), value);
6150     }
6151 
6152     addptr(to, 32);
6153     subl(count, 8 << shift);
6154     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6155     BIND(L_check_fill_8_bytes);
6156     addl(count, 8 << shift);
6157     jccb(Assembler::zero, L_exit);
6158     jmpb(L_fill_8_bytes);
6159 
6160     //
6161     // length is too short, just fill qwords
6162     //
6163     BIND(L_fill_8_bytes_loop);
6164     movl(Address(to, 0), value);
6165     movl(Address(to, 4), value);
6166     addptr(to, 8);
6167     BIND(L_fill_8_bytes);
6168     subl(count, 1 << (shift + 1));
6169     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6170     // fall through to fill 4 bytes
6171   } else {
6172     Label L_fill_32_bytes;
6173     if (!UseUnalignedLoadStores) {
6174       // align to 8 bytes, we know we are 4 byte aligned to start
6175       testptr(to, 4);
6176       jccb(Assembler::zero, L_fill_32_bytes);
6177       movl(Address(to, 0), value);
6178       addptr(to, 4);
6179       subl(count, 1<<shift);
6180     }
6181     BIND(L_fill_32_bytes);
6182     {
6183       assert( UseSSE >= 2, "supported cpu only" );
6184       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6185       movdl(xtmp, value);
6186       if (UseAVX >= 2 && UseUnalignedLoadStores) {
6187         // Fill 64-byte chunks
6188         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
6189         vpbroadcastd(xtmp, xtmp);
6190 
6191         subl(count, 16 << shift);
6192         jcc(Assembler::less, L_check_fill_32_bytes);
6193         align(16);
6194 
6195         BIND(L_fill_64_bytes_loop);
6196         vmovdqu(Address(to, 0), xtmp);
6197         vmovdqu(Address(to, 32), xtmp);
6198         addptr(to, 64);
6199         subl(count, 16 << shift);
6200         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6201 
6202         BIND(L_check_fill_32_bytes);
6203         addl(count, 8 << shift);
6204         jccb(Assembler::less, L_check_fill_8_bytes);
6205         vmovdqu(Address(to, 0), xtmp);
6206         addptr(to, 32);
6207         subl(count, 8 << shift);
6208 
6209         BIND(L_check_fill_8_bytes);
6210         // clean upper bits of YMM registers
6211         vzeroupper();
6212       } else {
6213         // Fill 32-byte chunks
6214         pshufd(xtmp, xtmp, 0);
6215 
6216         subl(count, 8 << shift);
6217         jcc(Assembler::less, L_check_fill_8_bytes);
6218         align(16);
6219 
6220         BIND(L_fill_32_bytes_loop);
6221 
6222         if (UseUnalignedLoadStores) {
6223           movdqu(Address(to, 0), xtmp);
6224           movdqu(Address(to, 16), xtmp);
6225         } else {
6226           movq(Address(to, 0), xtmp);
6227           movq(Address(to, 8), xtmp);
6228           movq(Address(to, 16), xtmp);
6229           movq(Address(to, 24), xtmp);
6230         }
6231 
6232         addptr(to, 32);
6233         subl(count, 8 << shift);
6234         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6235 
6236         BIND(L_check_fill_8_bytes);
6237       }
6238       addl(count, 8 << shift);
6239       jccb(Assembler::zero, L_exit);
6240       jmpb(L_fill_8_bytes);
6241 
6242       //
6243       // length is too short, just fill qwords
6244       //
6245       BIND(L_fill_8_bytes_loop);
6246       movq(Address(to, 0), xtmp);
6247       addptr(to, 8);
6248       BIND(L_fill_8_bytes);
6249       subl(count, 1 << (shift + 1));
6250       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6251     }
6252   }
6253   // fill trailing 4 bytes
6254   BIND(L_fill_4_bytes);
6255   testl(count, 1<<shift);
6256   jccb(Assembler::zero, L_fill_2_bytes);
6257   movl(Address(to, 0), value);
6258   if (t == T_BYTE || t == T_SHORT) {
6259     addptr(to, 4);
6260     BIND(L_fill_2_bytes);
6261     // fill trailing 2 bytes
6262     testl(count, 1<<(shift-1));
6263     jccb(Assembler::zero, L_fill_byte);
6264     movw(Address(to, 0), value);
6265     if (t == T_BYTE) {
6266       addptr(to, 2);
6267       BIND(L_fill_byte);
6268       // fill trailing byte
6269       testl(count, 1);
6270       jccb(Assembler::zero, L_exit);
6271       movb(Address(to, 0), value);
6272     } else {
6273       BIND(L_fill_byte);
6274     }
6275   } else {
6276     BIND(L_fill_2_bytes);
6277   }
6278   BIND(L_exit);
6279 }
6280 
6281 // encode char[] to byte[] in ISO_8859_1
6282 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6283                                       XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6284                                       XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6285                                       Register tmp5, Register result) {
6286   // rsi: src
6287   // rdi: dst
6288   // rdx: len
6289   // rcx: tmp5
6290   // rax: result
6291   ShortBranchVerifier sbv(this);
6292   assert_different_registers(src, dst, len, tmp5, result);
6293   Label L_done, L_copy_1_char, L_copy_1_char_exit;
6294 
6295   // set result
6296   xorl(result, result);
6297   // check for zero length
6298   testl(len, len);
6299   jcc(Assembler::zero, L_done);
6300   movl(result, len);
6301 
6302   // Setup pointers
6303   lea(src, Address(src, len, Address::times_2)); // char[]
6304   lea(dst, Address(dst, len, Address::times_1)); // byte[]
6305   negptr(len);
6306 
6307   if (UseSSE42Intrinsics || UseAVX >= 2) {
6308     Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
6309     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6310 
6311     if (UseAVX >= 2) {
6312       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6313       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
6314       movdl(tmp1Reg, tmp5);
6315       vpbroadcastd(tmp1Reg, tmp1Reg);
6316       jmpb(L_chars_32_check);
6317 
6318       bind(L_copy_32_chars);
6319       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6320       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6321       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
6322       vptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
6323       jccb(Assembler::notZero, L_copy_32_chars_exit);
6324       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
6325       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true);
6326       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6327 
6328       bind(L_chars_32_check);
6329       addptr(len, 32);
6330       jccb(Assembler::lessEqual, L_copy_32_chars);
6331 
6332       bind(L_copy_32_chars_exit);
6333       subptr(len, 16);
6334       jccb(Assembler::greater, L_copy_16_chars_exit);
6335 
6336     } else if (UseSSE42Intrinsics) {
6337       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
6338       movdl(tmp1Reg, tmp5);
6339       pshufd(tmp1Reg, tmp1Reg, 0);
6340       jmpb(L_chars_16_check);
6341     }
6342 
6343     bind(L_copy_16_chars);
6344     if (UseAVX >= 2) {
6345       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6346       vptest(tmp2Reg, tmp1Reg);
6347       jccb(Assembler::notZero, L_copy_16_chars_exit);
6348       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true);
6349       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true);
6350     } else {
6351       if (UseAVX > 0) {
6352         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6353         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6354         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false);
6355       } else {
6356         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6357         por(tmp2Reg, tmp3Reg);
6358         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6359         por(tmp2Reg, tmp4Reg);
6360       }
6361       ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
6362       jccb(Assembler::notZero, L_copy_16_chars_exit);
6363       packuswb(tmp3Reg, tmp4Reg);
6364     }
6365     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6366 
6367     bind(L_chars_16_check);
6368     addptr(len, 16);
6369     jccb(Assembler::lessEqual, L_copy_16_chars);
6370 
6371     bind(L_copy_16_chars_exit);
6372     if (UseAVX >= 2) {
6373       // clean upper bits of YMM registers
6374       vzeroupper();
6375     }
6376     subptr(len, 8);
6377     jccb(Assembler::greater, L_copy_8_chars_exit);
6378 
6379     bind(L_copy_8_chars);
6380     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6381     ptest(tmp3Reg, tmp1Reg);
6382     jccb(Assembler::notZero, L_copy_8_chars_exit);
6383     packuswb(tmp3Reg, tmp1Reg);
6384     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6385     addptr(len, 8);
6386     jccb(Assembler::lessEqual, L_copy_8_chars);
6387 
6388     bind(L_copy_8_chars_exit);
6389     subptr(len, 8);
6390     jccb(Assembler::zero, L_done);
6391   }
6392 
6393   bind(L_copy_1_char);
6394   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6395   testl(tmp5, 0xff00);      // check if Unicode char
6396   jccb(Assembler::notZero, L_copy_1_char_exit);
6397   movb(Address(dst, len, Address::times_1, 0), tmp5);
6398   addptr(len, 1);
6399   jccb(Assembler::less, L_copy_1_char);
6400 
6401   bind(L_copy_1_char_exit);
6402   addptr(result, len); // len is negative count of not processed elements
6403   bind(L_done);
6404 }
6405 
6406 /**
6407  * Emits code to update CRC-32 with a byte value according to constants in table
6408  *
6409  * @param [in,out]crc   Register containing the crc.
6410  * @param [in]val       Register containing the byte to fold into the CRC.
6411  * @param [in]table     Register containing the table of crc constants.
6412  *
6413  * uint32_t crc;
6414  * val = crc_table[(val ^ crc) & 0xFF];
6415  * crc = val ^ (crc >> 8);
6416  *
6417  */
6418 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
6419   xorl(val, crc);
6420   andl(val, 0xFF);
6421   shrl(crc, 8); // unsigned shift
6422   xorl(crc, Address(table, val, Address::times_4, 0));
6423 }
6424 
6425 /**
6426  * Fold 128-bit data chunk
6427  */
6428 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
6429   vpclmulhdq(xtmp, xK, xcrc); // [123:64]
6430   vpclmulldq(xcrc, xK, xcrc); // [63:0]
6431   vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */);
6432   pxor(xcrc, xtmp);
6433 }
6434 
6435 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
6436   vpclmulhdq(xtmp, xK, xcrc);
6437   vpclmulldq(xcrc, xK, xcrc);
6438   pxor(xcrc, xbuf);
6439   pxor(xcrc, xtmp);
6440 }
6441 
6442 /**
6443  * 8-bit folds to compute 32-bit CRC
6444  *
6445  * uint64_t xcrc;
6446  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
6447  */
6448 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
6449   movdl(tmp, xcrc);
6450   andl(tmp, 0xFF);
6451   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
6452   psrldq(xcrc, 1); // unsigned shift one byte
6453   pxor(xcrc, xtmp);
6454 }
6455 
6456 /**
6457  * uint32_t crc;
6458  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
6459  */
6460 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
6461   movl(tmp, crc);
6462   andl(tmp, 0xFF);
6463   shrl(crc, 8);
6464   xorl(crc, Address(table, tmp, Address::times_4, 0));
6465 }
6466 
6467 /**
6468  * @param crc   register containing existing CRC (32-bit)
6469  * @param buf   register pointing to input byte buffer (byte*)
6470  * @param len   register containing number of bytes
6471  * @param table register that will contain address of CRC table
6472  * @param tmp   scratch register
6473  */
6474 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
6475   assert_different_registers(crc, buf, len, table, tmp, rax);
6476 
6477   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
6478   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
6479 
6480   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
6481   notl(crc); // ~crc
6482   cmpl(len, 16);
6483   jcc(Assembler::less, L_tail);
6484 
6485   // Align buffer to 16 bytes
6486   movl(tmp, buf);
6487   andl(tmp, 0xF);
6488   jccb(Assembler::zero, L_aligned);
6489   subl(tmp,  16);
6490   addl(len, tmp);
6491 
6492   align(4);
6493   BIND(L_align_loop);
6494   movsbl(rax, Address(buf, 0)); // load byte with sign extension
6495   update_byte_crc32(crc, rax, table);
6496   increment(buf);
6497   incrementl(tmp);
6498   jccb(Assembler::less, L_align_loop);
6499 
6500   BIND(L_aligned);
6501   movl(tmp, len); // save
6502   shrl(len, 4);
6503   jcc(Assembler::zero, L_tail_restore);
6504 
6505   // Fold crc into first bytes of vector
6506   movdqa(xmm1, Address(buf, 0));
6507   movdl(rax, xmm1);
6508   xorl(crc, rax);
6509   pinsrd(xmm1, crc, 0);
6510   addptr(buf, 16);
6511   subl(len, 4); // len > 0
6512   jcc(Assembler::less, L_fold_tail);
6513 
6514   movdqa(xmm2, Address(buf,  0));
6515   movdqa(xmm3, Address(buf, 16));
6516   movdqa(xmm4, Address(buf, 32));
6517   addptr(buf, 48);
6518   subl(len, 3);
6519   jcc(Assembler::lessEqual, L_fold_512b);
6520 
6521   // Fold total 512 bits of polynomial on each iteration,
6522   // 128 bits per each of 4 parallel streams.
6523   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
6524 
6525   align(32);
6526   BIND(L_fold_512b_loop);
6527   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
6528   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
6529   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
6530   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
6531   addptr(buf, 64);
6532   subl(len, 4);
6533   jcc(Assembler::greater, L_fold_512b_loop);
6534 
6535   // Fold 512 bits to 128 bits.
6536   BIND(L_fold_512b);
6537   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
6538   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
6539   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
6540   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
6541 
6542   // Fold the rest of 128 bits data chunks
6543   BIND(L_fold_tail);
6544   addl(len, 3);
6545   jccb(Assembler::lessEqual, L_fold_128b);
6546   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
6547 
6548   BIND(L_fold_tail_loop);
6549   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
6550   addptr(buf, 16);
6551   decrementl(len);
6552   jccb(Assembler::greater, L_fold_tail_loop);
6553 
6554   // Fold 128 bits in xmm1 down into 32 bits in crc register.
6555   BIND(L_fold_128b);
6556   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
6557   vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
6558   vpand(xmm3, xmm0, xmm2, false /* vector256 */);
6559   vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
6560   psrldq(xmm1, 8);
6561   psrldq(xmm2, 4);
6562   pxor(xmm0, xmm1);
6563   pxor(xmm0, xmm2);
6564 
6565   // 8 8-bit folds to compute 32-bit CRC.
6566   for (int j = 0; j < 4; j++) {
6567     fold_8bit_crc32(xmm0, table, xmm1, rax);
6568   }
6569   movdl(crc, xmm0); // mov 32 bits to general register
6570   for (int j = 0; j < 4; j++) {
6571     fold_8bit_crc32(crc, table, rax);
6572   }
6573 
6574   BIND(L_tail_restore);
6575   movl(len, tmp); // restore
6576   BIND(L_tail);
6577   andl(len, 0xf);
6578   jccb(Assembler::zero, L_exit);
6579 
6580   // Fold the rest of bytes
6581   align(4);
6582   BIND(L_tail_loop);
6583   movsbl(rax, Address(buf, 0)); // load byte with sign extension
6584   update_byte_crc32(crc, rax, table);
6585   increment(buf);
6586   decrementl(len);
6587   jccb(Assembler::greater, L_tail_loop);
6588 
6589   BIND(L_exit);
6590   notl(crc); // ~c
6591 }
6592 
6593 #undef BIND
6594 #undef BLOCK_COMMENT
6595 
6596 
6597 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
6598   switch (cond) {
6599     // Note some conditions are synonyms for others
6600     case Assembler::zero:         return Assembler::notZero;
6601     case Assembler::notZero:      return Assembler::zero;
6602     case Assembler::less:         return Assembler::greaterEqual;
6603     case Assembler::lessEqual:    return Assembler::greater;
6604     case Assembler::greater:      return Assembler::lessEqual;
6605     case Assembler::greaterEqual: return Assembler::less;
6606     case Assembler::below:        return Assembler::aboveEqual;
6607     case Assembler::belowEqual:   return Assembler::above;
6608     case Assembler::above:        return Assembler::belowEqual;
6609     case Assembler::aboveEqual:   return Assembler::below;
6610     case Assembler::overflow:     return Assembler::noOverflow;
6611     case Assembler::noOverflow:   return Assembler::overflow;
6612     case Assembler::negative:     return Assembler::positive;
6613     case Assembler::positive:     return Assembler::negative;
6614     case Assembler::parity:       return Assembler::noParity;
6615     case Assembler::noParity:     return Assembler::parity;
6616   }
6617   ShouldNotReachHere(); return Assembler::overflow;
6618 }
6619 
6620 SkipIfEqual::SkipIfEqual(
6621     MacroAssembler* masm, const bool* flag_addr, bool value) {
6622   _masm = masm;
6623   _masm->cmp8(ExternalAddress((address)flag_addr), value);
6624   _masm->jcc(Assembler::equal, _label);
6625 }
6626 
6627 SkipIfEqual::~SkipIfEqual() {
6628   _masm->bind(_label);
6629 }