1 //
2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2015 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29,*/ // global TOC
451 R30,
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29,*/
488 R30,
489 R31
490 );
491
492 reg_class rscratch1_bits32_reg(R11);
493 reg_class rscratch2_bits32_reg(R12);
494 reg_class rarg1_bits32_reg(R3);
495 reg_class rarg2_bits32_reg(R4);
496 reg_class rarg3_bits32_reg(R5);
497 reg_class rarg4_bits32_reg(R6);
498
499 // ----------------------------
500 // 64 Bit Register Classes
501 // ----------------------------
502 // 64-bit build means 64-bit pointers means hi/lo pairs
503
504 reg_class rscratch1_bits64_reg(R11_H, R11);
505 reg_class rscratch2_bits64_reg(R12_H, R12);
506 reg_class rarg1_bits64_reg(R3_H, R3);
507 reg_class rarg2_bits64_reg(R4_H, R4);
508 reg_class rarg3_bits64_reg(R5_H, R5);
509 reg_class rarg4_bits64_reg(R6_H, R6);
510 // Thread register, 'written' by tlsLoadP, see there.
511 reg_class thread_bits64_reg(R16_H, R16);
512
513 reg_class r19_bits64_reg(R19_H, R19);
514
515 // 64 bit registers that can be read and written i.e. these registers
516 // can be dest (or src) of normal instructions.
517 reg_class bits64_reg_rw(
518 /*R0_H, R0*/ // R0
519 /*R1_H, R1*/ // SP
520 R2_H, R2, // TOC
521 R3_H, R3,
522 R4_H, R4,
523 R5_H, R5,
524 R6_H, R6,
525 R7_H, R7,
526 R8_H, R8,
527 R9_H, R9,
528 R10_H, R10,
529 R11_H, R11,
530 R12_H, R12,
531 /*R13_H, R13*/ // system thread id
532 R14_H, R14,
533 R15_H, R15,
534 /*R16_H, R16*/ // R16_thread
535 R17_H, R17,
536 R18_H, R18,
537 R19_H, R19,
538 R20_H, R20,
539 R21_H, R21,
540 R22_H, R22,
541 R23_H, R23,
542 R24_H, R24,
543 R25_H, R25,
544 R26_H, R26,
545 R27_H, R27,
546 R28_H, R28,
547 /*R29_H, R29,*/
548 R30_H, R30,
549 R31_H, R31
550 );
551
552 // 64 bit registers used excluding r2, r11 and r12
553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
554 // r2, r11 and r12 internally.
555 reg_class bits64_reg_leaf_call(
556 /*R0_H, R0*/ // R0
557 /*R1_H, R1*/ // SP
558 /*R2_H, R2*/ // TOC
559 R3_H, R3,
560 R4_H, R4,
561 R5_H, R5,
562 R6_H, R6,
563 R7_H, R7,
564 R8_H, R8,
565 R9_H, R9,
566 R10_H, R10,
567 /*R11_H, R11*/
568 /*R12_H, R12*/
569 /*R13_H, R13*/ // system thread id
570 R14_H, R14,
571 R15_H, R15,
572 /*R16_H, R16*/ // R16_thread
573 R17_H, R17,
574 R18_H, R18,
575 R19_H, R19,
576 R20_H, R20,
577 R21_H, R21,
578 R22_H, R22,
579 R23_H, R23,
580 R24_H, R24,
581 R25_H, R25,
582 R26_H, R26,
583 R27_H, R27,
584 R28_H, R28,
585 /*R29_H, R29,*/
586 R30_H, R30,
587 R31_H, R31
588 );
589
590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
591 // which uses r19 as inline cache internally and expanded LeafCall which uses
592 // r2, r11 and r12 internally.
593 reg_class bits64_constant_table_base(
594 /*R0_H, R0*/ // R0
595 /*R1_H, R1*/ // SP
596 /*R2_H, R2*/ // TOC
597 R3_H, R3,
598 R4_H, R4,
599 R5_H, R5,
600 R6_H, R6,
601 R7_H, R7,
602 R8_H, R8,
603 R9_H, R9,
604 R10_H, R10,
605 /*R11_H, R11*/
606 /*R12_H, R12*/
607 /*R13_H, R13*/ // system thread id
608 R14_H, R14,
609 R15_H, R15,
610 /*R16_H, R16*/ // R16_thread
611 R17_H, R17,
612 R18_H, R18,
613 /*R19_H, R19*/
614 R20_H, R20,
615 R21_H, R21,
616 R22_H, R22,
617 R23_H, R23,
618 R24_H, R24,
619 R25_H, R25,
620 R26_H, R26,
621 R27_H, R27,
622 R28_H, R28,
623 /*R29_H, R29,*/
624 R30_H, R30,
625 R31_H, R31
626 );
627
628 // 64 bit registers that can only be read i.e. these registers can
629 // only be src of all instructions.
630 reg_class bits64_reg_ro(
631 /*R0_H, R0*/ // R0
632 R1_H, R1,
633 R2_H, R2, // TOC
634 R3_H, R3,
635 R4_H, R4,
636 R5_H, R5,
637 R6_H, R6,
638 R7_H, R7,
639 R8_H, R8,
640 R9_H, R9,
641 R10_H, R10,
642 R11_H, R11,
643 R12_H, R12,
644 /*R13_H, R13*/ // system thread id
645 R14_H, R14,
646 R15_H, R15,
647 R16_H, R16, // R16_thread
648 R17_H, R17,
649 R18_H, R18,
650 R19_H, R19,
651 R20_H, R20,
652 R21_H, R21,
653 R22_H, R22,
654 R23_H, R23,
655 R24_H, R24,
656 R25_H, R25,
657 R26_H, R26,
658 R27_H, R27,
659 R28_H, R28,
660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
661 R30_H, R30,
662 R31_H, R31
663 );
664
665
666 // ----------------------------
667 // Special Class for Condition Code Flags Register
668
669 reg_class int_flags(
670 /*CCR0*/ // scratch
671 /*CCR1*/ // scratch
672 /*CCR2*/ // nv!
673 /*CCR3*/ // nv!
674 /*CCR4*/ // nv!
675 CCR5,
676 CCR6,
677 CCR7
678 );
679
680 reg_class int_flags_ro(
681 CCR0,
682 CCR1,
683 CCR2,
684 CCR3,
685 CCR4,
686 CCR5,
687 CCR6,
688 CCR7
689 );
690
691 reg_class int_flags_CR0(CCR0);
692 reg_class int_flags_CR1(CCR1);
693 reg_class int_flags_CR6(CCR6);
694 reg_class ctr_reg(SR_CTR);
695
696 // ----------------------------
697 // Float Register Classes
698 // ----------------------------
699
700 reg_class flt_reg(
701 /*F0*/ // scratch
702 F1,
703 F2,
704 F3,
705 F4,
706 F5,
707 F6,
708 F7,
709 F8,
710 F9,
711 F10,
712 F11,
713 F12,
714 F13,
715 F14, // nv!
716 F15, // nv!
717 F16, // nv!
718 F17, // nv!
719 F18, // nv!
720 F19, // nv!
721 F20, // nv!
722 F21, // nv!
723 F22, // nv!
724 F23, // nv!
725 F24, // nv!
726 F25, // nv!
727 F26, // nv!
728 F27, // nv!
729 F28, // nv!
730 F29, // nv!
731 F30, // nv!
732 F31 // nv!
733 );
734
735 // Double precision float registers have virtual `high halves' that
736 // are needed by the allocator.
737 reg_class dbl_reg(
738 /*F0, F0_H*/ // scratch
739 F1, F1_H,
740 F2, F2_H,
741 F3, F3_H,
742 F4, F4_H,
743 F5, F5_H,
744 F6, F6_H,
745 F7, F7_H,
746 F8, F8_H,
747 F9, F9_H,
748 F10, F10_H,
749 F11, F11_H,
750 F12, F12_H,
751 F13, F13_H,
752 F14, F14_H, // nv!
753 F15, F15_H, // nv!
754 F16, F16_H, // nv!
755 F17, F17_H, // nv!
756 F18, F18_H, // nv!
757 F19, F19_H, // nv!
758 F20, F20_H, // nv!
759 F21, F21_H, // nv!
760 F22, F22_H, // nv!
761 F23, F23_H, // nv!
762 F24, F24_H, // nv!
763 F25, F25_H, // nv!
764 F26, F26_H, // nv!
765 F27, F27_H, // nv!
766 F28, F28_H, // nv!
767 F29, F29_H, // nv!
768 F30, F30_H, // nv!
769 F31, F31_H // nv!
770 );
771
772 %}
773
774 //----------DEFINITION BLOCK---------------------------------------------------
775 // Define name --> value mappings to inform the ADLC of an integer valued name
776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
777 // Format:
778 // int_def <name> ( <int_value>, <expression>);
779 // Generated Code in ad_<arch>.hpp
780 // #define <name> (<expression>)
781 // // value == <int_value>
782 // Generated code in ad_<arch>.cpp adlc_verification()
783 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
784 //
785 definitions %{
786 // The default cost (of an ALU instruction).
787 int_def DEFAULT_COST_LOW ( 30, 30);
788 int_def DEFAULT_COST ( 100, 100);
789 int_def HUGE_COST (1000000, 1000000);
790
791 // Memory refs
792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
794
795 // Branches are even more expensive.
796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
797 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
798 %}
799
800
801 //----------SOURCE BLOCK-------------------------------------------------------
802 // This is a block of C++ code which provides values, functions, and
803 // definitions necessary in the rest of the architecture description.
804 source_hpp %{
805 // Header information of the source block.
806 // Method declarations/definitions which are used outside
807 // the ad-scope can conveniently be defined here.
808 //
809 // To keep related declarations/definitions/uses close together,
810 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
811
812 // Returns true if Node n is followed by a MemBar node that
813 // will do an acquire. If so, this node must not do the acquire
814 // operation.
815 bool followed_by_acquire(const Node *n);
816 %}
817
818 source %{
819
820 // Optimize load-acquire.
821 //
822 // Check if acquire is unnecessary due to following operation that does
823 // acquire anyways.
824 // Walk the pattern:
825 //
826 // n: Load.acq
827 // |
828 // MemBarAcquire
829 // | |
830 // Proj(ctrl) Proj(mem)
831 // | |
832 // MemBarRelease/Volatile
833 //
834 bool followed_by_acquire(const Node *load) {
835 assert(load->is_Load(), "So far implemented only for loads.");
836
837 // Find MemBarAcquire.
838 const Node *mba = NULL;
839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
840 const Node *out = load->fast_out(i);
841 if (out->Opcode() == Op_MemBarAcquire) {
842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
843 mba = out;
844 break;
845 }
846 }
847 if (!mba) return false;
848
849 // Find following MemBar node.
850 //
851 // The following node must be reachable by control AND memory
852 // edge to assure no other operations are in between the two nodes.
853 //
854 // So first get the Proj node, mem_proj, to use it to iterate forward.
855 Node *mem_proj = NULL;
856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
858 assert(mem_proj->is_Proj(), "only projections here");
859 ProjNode *proj = mem_proj->as_Proj();
860 if (proj->_con == TypeFunc::Memory &&
861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
862 break;
863 }
864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
865
866 // Search MemBar behind Proj. If there are other memory operations
867 // behind the Proj we lost.
868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
869 Node *x = mem_proj->fast_out(j);
870 // Proj might have an edge to a store or load node which precedes the membar.
871 if (x->is_Mem()) return false;
872
873 // On PPC64 release and volatile are implemented by an instruction
874 // that also has acquire semantics. I.e. there is no need for an
875 // acquire before these.
876 int xop = x->Opcode();
877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
878 // Make sure we're not missing Call/Phi/MergeMem by checking
879 // control edges. The control edge must directly lead back
880 // to the MemBarAcquire
881 Node *ctrl_proj = x->in(0);
882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
883 return true;
884 }
885 }
886 }
887
888 return false;
889 }
890
891 #define __ _masm.
892
893 // Tertiary op of a LoadP or StoreP encoding.
894 #define REGP_OP true
895
896 // ****************************************************************************
897
898 // REQUIRED FUNCTIONALITY
899
900 // !!!!! Special hack to get all type of calls to specify the byte offset
901 // from the start of the call to the point where the return address
902 // will point.
903
904 // PPC port: Removed use of lazy constant construct.
905
906 int MachCallStaticJavaNode::ret_addr_offset() {
907 // It's only a single branch-and-link instruction.
908 return 4;
909 }
910
911 int MachCallDynamicJavaNode::ret_addr_offset() {
912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
913 // postalloc expanded calls if we use inline caches and do not update method data.
914 if (UseInlineCaches)
915 return 4;
916
917 int vtable_index = this->_vtable_index;
918 if (vtable_index < 0) {
919 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
921 return 12;
922 } else {
923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
924 return 24;
925 }
926 }
927
928 int MachCallRuntimeNode::ret_addr_offset() {
929 #if defined(ABI_ELFv2)
930 return 28;
931 #else
932 return 40;
933 #endif
934 }
935
936 //=============================================================================
937
938 // condition code conversions
939
940 static int cc_to_boint(int cc) {
941 return Assembler::bcondCRbiIs0 | (cc & 8);
942 }
943
944 static int cc_to_inverse_boint(int cc) {
945 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
946 }
947
948 static int cc_to_biint(int cc, int flags_reg) {
949 return (flags_reg << 2) | (cc & 3);
950 }
951
952 //=============================================================================
953
954 // Compute padding required for nodes which need alignment. The padding
955 // is the number of bytes (not instructions) which will be inserted before
956 // the instruction. The padding must match the size of a NOP instruction.
957
958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
959 return (3*4-current_offset)&31;
960 }
961
962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
963 return (2*4-current_offset)&31;
964 }
965
966 int string_indexOf_immNode::compute_padding(int current_offset) const {
967 return (3*4-current_offset)&31;
968 }
969
970 int string_indexOfNode::compute_padding(int current_offset) const {
971 return (1*4-current_offset)&31;
972 }
973
974 int string_compareNode::compute_padding(int current_offset) const {
975 return (4*4-current_offset)&31;
976 }
977
978 int string_equals_immNode::compute_padding(int current_offset) const {
979 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
980 return (2*4-current_offset)&31;
981 }
982
983 int string_equalsNode::compute_padding(int current_offset) const {
984 return (7*4-current_offset)&31;
985 }
986
987 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
988 return (2*4-current_offset)&31;
989 }
990
991 //=============================================================================
992
993 // Indicate if the safepoint node needs the polling page as an input.
994 bool SafePointNode::needs_polling_address_input() {
995 // The address is loaded from thread by a seperate node.
996 return true;
997 }
998
999 //=============================================================================
1000
1001 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1002 void emit_break(CodeBuffer &cbuf) {
1003 MacroAssembler _masm(&cbuf);
1004 __ illtrap();
1005 }
1006
1007 #ifndef PRODUCT
1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1009 st->print("BREAKPOINT");
1010 }
1011 #endif
1012
1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1014 emit_break(cbuf);
1015 }
1016
1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1018 return MachNode::size(ra_);
1019 }
1020
1021 //=============================================================================
1022
1023 void emit_nop(CodeBuffer &cbuf) {
1024 MacroAssembler _masm(&cbuf);
1025 __ nop();
1026 }
1027
1028 static inline void emit_long(CodeBuffer &cbuf, int value) {
1029 *((int*)(cbuf.insts_end())) = value;
1030 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1031 }
1032
1033 //=============================================================================
1034
1035 %} // interrupt source
1036
1037 source_hpp %{ // Header information of the source block.
1038
1039 //--------------------------------------------------------------
1040 //---< Used for optimization in Compile::Shorten_branches >---
1041 //--------------------------------------------------------------
1042
1043 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1044
1045 class CallStubImpl {
1046
1047 public:
1048
1049 // Emit call stub, compiled java to interpreter.
1050 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1051
1052 // Size of call trampoline stub.
1053 // This doesn't need to be accurate to the byte, but it
1054 // must be larger than or equal to the real size of the stub.
1055 static uint size_call_trampoline() {
1056 return trampoline_stub_size;
1057 }
1058
1059 // number of relocations needed by a call trampoline stub
1060 static uint reloc_call_trampoline() {
1061 return 5;
1062 }
1063
1064 };
1065
1066 %} // end source_hpp
1067
1068 source %{
1069
1070 // Emit a trampoline stub for a call to a target which is too far away.
1071 //
1072 // code sequences:
1073 //
1074 // call-site:
1075 // branch-and-link to <destination> or <trampoline stub>
1076 //
1077 // Related trampoline stub for this call-site in the stub section:
1078 // load the call target from the constant pool
1079 // branch via CTR (LR/link still points to the call-site above)
1080
1081 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1082 // Start the stub.
1083 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1084 if (stub == NULL) {
1085 ciEnv::current()->record_failure("CodeCache is full");
1086 return;
1087 }
1088
1089 // For java_to_interp stubs we use R11_scratch1 as scratch register
1090 // and in call trampoline stubs we use R12_scratch2. This way we
1091 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1092 Register reg_scratch = R12_scratch2;
1093
1094 // Create a trampoline stub relocation which relates this trampoline stub
1095 // with the call instruction at insts_call_instruction_offset in the
1096 // instructions code-section.
1097 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1098 const int stub_start_offset = __ offset();
1099
1100 // Now, create the trampoline stub's code:
1101 // - load the TOC
1102 // - load the call target from the constant pool
1103 // - call
1104 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1105 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1106 __ mtctr(reg_scratch);
1107 __ bctr();
1108
1109 const address stub_start_addr = __ addr_at(stub_start_offset);
1110
1111 // FIXME: Assert that the trampoline stub can be identified and patched.
1112
1113 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1114 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1115 "encoded offset into the constant pool must match");
1116 // Trampoline_stub_size should be good.
1117 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1118 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1119
1120 // End the stub.
1121 __ end_a_stub();
1122 }
1123
1124 //=============================================================================
1125
1126 // Emit an inline branch-and-link call and a related trampoline stub.
1127 //
1128 // code sequences:
1129 //
1130 // call-site:
1131 // branch-and-link to <destination> or <trampoline stub>
1132 //
1133 // Related trampoline stub for this call-site in the stub section:
1134 // load the call target from the constant pool
1135 // branch via CTR (LR/link still points to the call-site above)
1136 //
1137
1138 typedef struct {
1139 int insts_call_instruction_offset;
1140 int ret_addr_offset;
1141 } EmitCallOffsets;
1142
1143 // Emit a branch-and-link instruction that branches to a trampoline.
1144 // - Remember the offset of the branch-and-link instruction.
1145 // - Add a relocation at the branch-and-link instruction.
1146 // - Emit a branch-and-link.
1147 // - Remember the return pc offset.
1148 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1149 EmitCallOffsets offsets = { -1, -1 };
1150 const int start_offset = __ offset();
1151 offsets.insts_call_instruction_offset = __ offset();
1152
1153 // No entry point given, use the current pc.
1154 if (entry_point == NULL) entry_point = __ pc();
1155
1156 if (!Compile::current()->in_scratch_emit_size()) {
1157 // Put the entry point as a constant into the constant pool.
1158 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1159 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1160
1161 // Emit the trampoline stub which will be related to the branch-and-link below.
1162 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1163 if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1164 __ relocate(rtype);
1165 }
1166
1167 // Note: At this point we do not have the address of the trampoline
1168 // stub, and the entry point might be too far away for bl, so __ pc()
1169 // serves as dummy and the bl will be patched later.
1170 __ bl((address) __ pc());
1171
1172 offsets.ret_addr_offset = __ offset() - start_offset;
1173
1174 return offsets;
1175 }
1176
1177 //=============================================================================
1178
1179 // Factory for creating loadConL* nodes for large/small constant pool.
1180
1181 static inline jlong replicate_immF(float con) {
1182 // Replicate float con 2 times and pack into vector.
1183 int val = *((int*)&con);
1184 jlong lval = val;
1185 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1186 return lval;
1187 }
1188
1189 //=============================================================================
1190
1191 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1192 int Compile::ConstantTable::calculate_table_base_offset() const {
1193 return 0; // absolute addressing, no offset
1194 }
1195
1196 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1197 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1198 iRegPdstOper *op_dst = new iRegPdstOper();
1199 MachNode *m1 = new loadToc_hiNode();
1200 MachNode *m2 = new loadToc_loNode();
1201
1202 m1->add_req(NULL);
1203 m2->add_req(NULL, m1);
1204 m1->_opnds[0] = op_dst;
1205 m2->_opnds[0] = op_dst;
1206 m2->_opnds[1] = op_dst;
1207 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1208 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1209 nodes->push(m1);
1210 nodes->push(m2);
1211 }
1212
1213 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1214 // Is postalloc expanded.
1215 ShouldNotReachHere();
1216 }
1217
1218 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1219 return 0;
1220 }
1221
1222 #ifndef PRODUCT
1223 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1224 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1225 }
1226 #endif
1227
1228 //=============================================================================
1229
1230 #ifndef PRODUCT
1231 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1232 Compile* C = ra_->C;
1233 const long framesize = C->frame_slots() << LogBytesPerInt;
1234
1235 st->print("PROLOG\n\t");
1236 if (C->need_stack_bang(framesize)) {
1237 st->print("stack_overflow_check\n\t");
1238 }
1239
1240 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1241 st->print("save return pc\n\t");
1242 st->print("push frame %ld\n\t", -framesize);
1243 }
1244 }
1245 #endif
1246
1247 // Macro used instead of the common __ to emulate the pipes of PPC.
1248 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1249 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1250 // still no scheduling of this code is possible, the micro scheduler is aware of the
1251 // code and can update its internal data. The following mechanism is used to achieve this:
1252 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1253 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1254 #if 0 // TODO: PPC port
1255 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1256 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1257 _masm.
1258 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1259 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1260 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1261 C->hb_scheduling()->_pdScheduling->advance_offset
1262 #else
1263 #define ___(op) if (UsePower6SchedulerPPC64) \
1264 Unimplemented(); \
1265 _masm.
1266 #define ___stop if (UsePower6SchedulerPPC64) \
1267 Unimplemented()
1268 #define ___advance if (UsePower6SchedulerPPC64) \
1269 Unimplemented()
1270 #endif
1271
1272 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1273 Compile* C = ra_->C;
1274 MacroAssembler _masm(&cbuf);
1275
1276 const long framesize = C->frame_size_in_bytes();
1277 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1278
1279 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1280
1281 const Register return_pc = R20; // Must match return_addr() in frame section.
1282 const Register callers_sp = R21;
1283 const Register push_frame_temp = R22;
1284 const Register toc_temp = R23;
1285 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1286
1287 if (method_is_frameless) {
1288 // Add nop at beginning of all frameless methods to prevent any
1289 // oop instructions from getting overwritten by make_not_entrant
1290 // (patching attempt would fail).
1291 ___(nop) nop();
1292 } else {
1293 // Get return pc.
1294 ___(mflr) mflr(return_pc);
1295 }
1296
1297 // Calls to C2R adapters often do not accept exceptional returns.
1298 // We require that their callers must bang for them. But be
1299 // careful, because some VM calls (such as call site linkage) can
1300 // use several kilobytes of stack. But the stack safety zone should
1301 // account for that. See bugs 4446381, 4468289, 4497237.
1302
1303 int bangsize = C->bang_size_in_bytes();
1304 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1305 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1306 // Unfortunately we cannot use the function provided in
1307 // assembler.cpp as we have to emulate the pipes. So I had to
1308 // insert the code of generate_stack_overflow_check(), see
1309 // assembler.cpp for some illuminative comments.
1310 const int page_size = os::vm_page_size();
1311 int bang_end = JavaThread::stack_shadow_zone_size();
1312
1313 // This is how far the previous frame's stack banging extended.
1314 const int bang_end_safe = bang_end;
1315
1316 if (bangsize > page_size) {
1317 bang_end += bangsize;
1318 }
1319
1320 int bang_offset = bang_end_safe;
1321
1322 while (bang_offset <= bang_end) {
1323 // Need at least one stack bang at end of shadow zone.
1324
1325 // Again I had to copy code, this time from assembler_ppc.cpp,
1326 // bang_stack_with_offset - see there for comments.
1327
1328 // Stack grows down, caller passes positive offset.
1329 assert(bang_offset > 0, "must bang with positive offset");
1330
1331 long stdoffset = -bang_offset;
1332
1333 if (Assembler::is_simm(stdoffset, 16)) {
1334 // Signed 16 bit offset, a simple std is ok.
1335 if (UseLoadInstructionsForStackBangingPPC64) {
1336 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1337 } else {
1338 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1339 }
1340 } else if (Assembler::is_simm(stdoffset, 31)) {
1341 // Use largeoffset calculations for addis & ld/std.
1342 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1343 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1344
1345 Register tmp = R11;
1346 ___(addis) addis(tmp, R1_SP, hi);
1347 if (UseLoadInstructionsForStackBangingPPC64) {
1348 ___(ld) ld(R0, lo, tmp);
1349 } else {
1350 ___(std) std(R0, lo, tmp);
1351 }
1352 } else {
1353 ShouldNotReachHere();
1354 }
1355
1356 bang_offset += page_size;
1357 }
1358 // R11 trashed
1359 } // C->need_stack_bang(framesize) && UseStackBanging
1360
1361 unsigned int bytes = (unsigned int)framesize;
1362 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1363 ciMethod *currMethod = C->method();
1364
1365 // Optimized version for most common case.
1366 if (UsePower6SchedulerPPC64 &&
1367 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1368 !(false /* ConstantsALot TODO: PPC port*/)) {
1369 ___(or) mr(callers_sp, R1_SP);
1370 ___(std) std(return_pc, _abi(lr), R1_SP);
1371 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1372 return;
1373 }
1374
1375 if (!method_is_frameless) {
1376 // Get callers sp.
1377 ___(or) mr(callers_sp, R1_SP);
1378
1379 // Push method's frame, modifies SP.
1380 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1381 // The ABI is already accounted for in 'framesize' via the
1382 // 'out_preserve' area.
1383 Register tmp = push_frame_temp;
1384 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1385 if (Assembler::is_simm(-offset, 16)) {
1386 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1387 } else {
1388 long x = -offset;
1389 // Had to insert load_const(tmp, -offset).
1390 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1391 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1392 ___(rldicr) sldi(tmp, tmp, 32);
1393 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1394 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1395
1396 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1397 }
1398 }
1399 #if 0 // TODO: PPC port
1400 // For testing large constant pools, emit a lot of constants to constant pool.
1401 // "Randomize" const_size.
1402 if (ConstantsALot) {
1403 const int num_consts = const_size();
1404 for (int i = 0; i < num_consts; i++) {
1405 __ long_constant(0xB0B5B00BBABE);
1406 }
1407 }
1408 #endif
1409 if (!method_is_frameless) {
1410 // Save return pc.
1411 ___(std) std(return_pc, _abi(lr), callers_sp);
1412 }
1413 }
1414 #undef ___
1415 #undef ___stop
1416 #undef ___advance
1417
1418 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1419 // Variable size. determine dynamically.
1420 return MachNode::size(ra_);
1421 }
1422
1423 int MachPrologNode::reloc() const {
1424 // Return number of relocatable values contained in this instruction.
1425 return 1; // 1 reloc entry for load_const(toc).
1426 }
1427
1428 //=============================================================================
1429
1430 #ifndef PRODUCT
1431 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1432 Compile* C = ra_->C;
1433
1434 st->print("EPILOG\n\t");
1435 st->print("restore return pc\n\t");
1436 st->print("pop frame\n\t");
1437
1438 if (do_polling() && C->is_method_compilation()) {
1439 st->print("touch polling page\n\t");
1440 }
1441 }
1442 #endif
1443
1444 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1445 Compile* C = ra_->C;
1446 MacroAssembler _masm(&cbuf);
1447
1448 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1449 assert(framesize >= 0, "negative frame-size?");
1450
1451 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1452 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1453 const Register return_pc = R11;
1454 const Register polling_page = R12;
1455
1456 if (!method_is_frameless) {
1457 // Restore return pc relative to callers' sp.
1458 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1459 }
1460
1461 if (method_needs_polling) {
1462 if (LoadPollAddressFromThread) {
1463 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1464 Unimplemented();
1465 } else {
1466 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1467 }
1468 }
1469
1470 if (!method_is_frameless) {
1471 // Move return pc to LR.
1472 __ mtlr(return_pc);
1473 // Pop frame (fixed frame-size).
1474 __ addi(R1_SP, R1_SP, (int)framesize);
1475 }
1476
1477 if (method_needs_polling) {
1478 // We need to mark the code position where the load from the safepoint
1479 // polling page was emitted as relocInfo::poll_return_type here.
1480 __ relocate(relocInfo::poll_return_type);
1481 __ load_from_polling_page(polling_page);
1482 }
1483 }
1484
1485 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1486 // Variable size. Determine dynamically.
1487 return MachNode::size(ra_);
1488 }
1489
1490 int MachEpilogNode::reloc() const {
1491 // Return number of relocatable values contained in this instruction.
1492 return 1; // 1 for load_from_polling_page.
1493 }
1494
1495 const Pipeline * MachEpilogNode::pipeline() const {
1496 return MachNode::pipeline_class();
1497 }
1498
1499 // This method seems to be obsolete. It is declared in machnode.hpp
1500 // and defined in all *.ad files, but it is never called. Should we
1501 // get rid of it?
1502 int MachEpilogNode::safepoint_offset() const {
1503 assert(do_polling(), "no return for this epilog node");
1504 return 0;
1505 }
1506
1507 #if 0 // TODO: PPC port
1508 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1509 MacroAssembler _masm(&cbuf);
1510 if (LoadPollAddressFromThread) {
1511 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1512 } else {
1513 _masm.nop();
1514 }
1515 }
1516
1517 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1518 if (LoadPollAddressFromThread) {
1519 return 4;
1520 } else {
1521 return 4;
1522 }
1523 }
1524
1525 #ifndef PRODUCT
1526 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1527 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1528 }
1529 #endif
1530
1531 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1532 return RSCRATCH1_BITS64_REG_mask();
1533 }
1534 #endif // PPC port
1535
1536 // =============================================================================
1537
1538 // Figure out which register class each belongs in: rc_int, rc_float or
1539 // rc_stack.
1540 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1541
1542 static enum RC rc_class(OptoReg::Name reg) {
1543 // Return the register class for the given register. The given register
1544 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1545 // enumeration in adGlobals_ppc.hpp.
1546
1547 if (reg == OptoReg::Bad) return rc_bad;
1548
1549 // We have 64 integer register halves, starting at index 0.
1550 if (reg < 64) return rc_int;
1551
1552 // We have 64 floating-point register halves, starting at index 64.
1553 if (reg < 64+64) return rc_float;
1554
1555 // Between float regs & stack are the flags regs.
1556 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1557
1558 return rc_stack;
1559 }
1560
1561 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1562 bool do_print, Compile* C, outputStream *st) {
1563
1564 assert(opcode == Assembler::LD_OPCODE ||
1565 opcode == Assembler::STD_OPCODE ||
1566 opcode == Assembler::LWZ_OPCODE ||
1567 opcode == Assembler::STW_OPCODE ||
1568 opcode == Assembler::LFD_OPCODE ||
1569 opcode == Assembler::STFD_OPCODE ||
1570 opcode == Assembler::LFS_OPCODE ||
1571 opcode == Assembler::STFS_OPCODE,
1572 "opcode not supported");
1573
1574 if (cbuf) {
1575 int d =
1576 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1577 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1578 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1579 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1580 }
1581 #ifndef PRODUCT
1582 else if (do_print) {
1583 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1584 op_str,
1585 Matcher::regName[reg],
1586 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1587 }
1588 #endif
1589 return 4; // size
1590 }
1591
1592 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1593 Compile* C = ra_->C;
1594
1595 // Get registers to move.
1596 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1597 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1598 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1599 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1600
1601 enum RC src_hi_rc = rc_class(src_hi);
1602 enum RC src_lo_rc = rc_class(src_lo);
1603 enum RC dst_hi_rc = rc_class(dst_hi);
1604 enum RC dst_lo_rc = rc_class(dst_lo);
1605
1606 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1607 if (src_hi != OptoReg::Bad)
1608 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1609 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1610 "expected aligned-adjacent pairs");
1611 // Generate spill code!
1612 int size = 0;
1613
1614 if (src_lo == dst_lo && src_hi == dst_hi)
1615 return size; // Self copy, no move.
1616
1617 // --------------------------------------
1618 // Memory->Memory Spill. Use R0 to hold the value.
1619 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1620 int src_offset = ra_->reg2offset(src_lo);
1621 int dst_offset = ra_->reg2offset(dst_lo);
1622 if (src_hi != OptoReg::Bad) {
1623 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1624 "expected same type of move for high parts");
1625 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1626 if (!cbuf && !do_size) st->print("\n\t");
1627 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1628 } else {
1629 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1630 if (!cbuf && !do_size) st->print("\n\t");
1631 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1632 }
1633 return size;
1634 }
1635
1636 // --------------------------------------
1637 // Check for float->int copy; requires a trip through memory.
1638 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1639 Unimplemented();
1640 }
1641
1642 // --------------------------------------
1643 // Check for integer reg-reg copy.
1644 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1645 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1646 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1647 size = (Rsrc != Rdst) ? 4 : 0;
1648
1649 if (cbuf) {
1650 MacroAssembler _masm(cbuf);
1651 if (size) {
1652 __ mr(Rdst, Rsrc);
1653 }
1654 }
1655 #ifndef PRODUCT
1656 else if (!do_size) {
1657 if (size) {
1658 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1659 } else {
1660 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1661 }
1662 }
1663 #endif
1664 return size;
1665 }
1666
1667 // Check for integer store.
1668 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1669 int dst_offset = ra_->reg2offset(dst_lo);
1670 if (src_hi != OptoReg::Bad) {
1671 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1672 "expected same type of move for high parts");
1673 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1674 } else {
1675 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1676 }
1677 return size;
1678 }
1679
1680 // Check for integer load.
1681 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1682 int src_offset = ra_->reg2offset(src_lo);
1683 if (src_hi != OptoReg::Bad) {
1684 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1685 "expected same type of move for high parts");
1686 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1687 } else {
1688 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1689 }
1690 return size;
1691 }
1692
1693 // Check for float reg-reg copy.
1694 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1695 if (cbuf) {
1696 MacroAssembler _masm(cbuf);
1697 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1698 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1699 __ fmr(Rdst, Rsrc);
1700 }
1701 #ifndef PRODUCT
1702 else if (!do_size) {
1703 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1704 }
1705 #endif
1706 return 4;
1707 }
1708
1709 // Check for float store.
1710 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1711 int dst_offset = ra_->reg2offset(dst_lo);
1712 if (src_hi != OptoReg::Bad) {
1713 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1714 "expected same type of move for high parts");
1715 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1716 } else {
1717 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1718 }
1719 return size;
1720 }
1721
1722 // Check for float load.
1723 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1724 int src_offset = ra_->reg2offset(src_lo);
1725 if (src_hi != OptoReg::Bad) {
1726 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1727 "expected same type of move for high parts");
1728 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1729 } else {
1730 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1731 }
1732 return size;
1733 }
1734
1735 // --------------------------------------------------------------------
1736 // Check for hi bits still needing moving. Only happens for misaligned
1737 // arguments to native calls.
1738 if (src_hi == dst_hi)
1739 return size; // Self copy; no move.
1740
1741 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1742 ShouldNotReachHere(); // Unimplemented
1743 return 0;
1744 }
1745
1746 #ifndef PRODUCT
1747 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748 if (!ra_)
1749 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1750 else
1751 implementation(NULL, ra_, false, st);
1752 }
1753 #endif
1754
1755 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1756 implementation(&cbuf, ra_, false, NULL);
1757 }
1758
1759 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1760 return implementation(NULL, ra_, true, NULL);
1761 }
1762
1763 #if 0 // TODO: PPC port
1764 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1765 #ifndef PRODUCT
1766 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1767 #endif
1768 assert(ra_->node_regs_max_index() != 0, "");
1769
1770 // Get registers to move.
1771 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1772 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1773 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1774 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1775
1776 enum RC src_lo_rc = rc_class(src_lo);
1777 enum RC dst_lo_rc = rc_class(dst_lo);
1778
1779 if (src_lo == dst_lo && src_hi == dst_hi)
1780 return ppc64Opcode_none; // Self copy, no move.
1781
1782 // --------------------------------------
1783 // Memory->Memory Spill. Use R0 to hold the value.
1784 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1785 return ppc64Opcode_compound;
1786 }
1787
1788 // --------------------------------------
1789 // Check for float->int copy; requires a trip through memory.
1790 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1791 Unimplemented();
1792 }
1793
1794 // --------------------------------------
1795 // Check for integer reg-reg copy.
1796 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1797 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1798 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1799 if (Rsrc == Rdst) {
1800 return ppc64Opcode_none;
1801 } else {
1802 return ppc64Opcode_or;
1803 }
1804 }
1805
1806 // Check for integer store.
1807 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1808 if (src_hi != OptoReg::Bad) {
1809 return ppc64Opcode_std;
1810 } else {
1811 return ppc64Opcode_stw;
1812 }
1813 }
1814
1815 // Check for integer load.
1816 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1817 if (src_hi != OptoReg::Bad) {
1818 return ppc64Opcode_ld;
1819 } else {
1820 return ppc64Opcode_lwz;
1821 }
1822 }
1823
1824 // Check for float reg-reg copy.
1825 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1826 return ppc64Opcode_fmr;
1827 }
1828
1829 // Check for float store.
1830 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1831 if (src_hi != OptoReg::Bad) {
1832 return ppc64Opcode_stfd;
1833 } else {
1834 return ppc64Opcode_stfs;
1835 }
1836 }
1837
1838 // Check for float load.
1839 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1840 if (src_hi != OptoReg::Bad) {
1841 return ppc64Opcode_lfd;
1842 } else {
1843 return ppc64Opcode_lfs;
1844 }
1845 }
1846
1847 // --------------------------------------------------------------------
1848 // Check for hi bits still needing moving. Only happens for misaligned
1849 // arguments to native calls.
1850 if (src_hi == dst_hi) {
1851 return ppc64Opcode_none; // Self copy; no move.
1852 }
1853
1854 ShouldNotReachHere();
1855 return ppc64Opcode_undefined;
1856 }
1857 #endif // PPC port
1858
1859 #ifndef PRODUCT
1860 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1861 st->print("NOP \t// %d nops to pad for loops.", _count);
1862 }
1863 #endif
1864
1865 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1866 MacroAssembler _masm(&cbuf);
1867 // _count contains the number of nops needed for padding.
1868 for (int i = 0; i < _count; i++) {
1869 __ nop();
1870 }
1871 }
1872
1873 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1874 return _count * 4;
1875 }
1876
1877 #ifndef PRODUCT
1878 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1879 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1880 char reg_str[128];
1881 ra_->dump_register(this, reg_str);
1882 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1883 }
1884 #endif
1885
1886 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1887 MacroAssembler _masm(&cbuf);
1888
1889 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1890 int reg = ra_->get_encode(this);
1891
1892 if (Assembler::is_simm(offset, 16)) {
1893 __ addi(as_Register(reg), R1, offset);
1894 } else {
1895 ShouldNotReachHere();
1896 }
1897 }
1898
1899 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1900 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1901 return 4;
1902 }
1903
1904 #ifndef PRODUCT
1905 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1906 st->print_cr("---- MachUEPNode ----");
1907 st->print_cr("...");
1908 }
1909 #endif
1910
1911 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1912 // This is the unverified entry point.
1913 MacroAssembler _masm(&cbuf);
1914
1915 // Inline_cache contains a klass.
1916 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1917 Register receiver_klass = R12_scratch2; // tmp
1918
1919 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1920 assert(R11_scratch1 == R11, "need prologue scratch register");
1921
1922 // Check for NULL argument if we don't have implicit null checks.
1923 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1924 if (TrapBasedNullChecks) {
1925 __ trap_null_check(R3_ARG1);
1926 } else {
1927 Label valid;
1928 __ cmpdi(CCR0, R3_ARG1, 0);
1929 __ bne_predict_taken(CCR0, valid);
1930 // We have a null argument, branch to ic_miss_stub.
1931 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1932 relocInfo::runtime_call_type);
1933 __ bind(valid);
1934 }
1935 }
1936 // Assume argument is not NULL, load klass from receiver.
1937 __ load_klass(receiver_klass, R3_ARG1);
1938
1939 if (TrapBasedICMissChecks) {
1940 __ trap_ic_miss_check(receiver_klass, ic_klass);
1941 } else {
1942 Label valid;
1943 __ cmpd(CCR0, receiver_klass, ic_klass);
1944 __ beq_predict_taken(CCR0, valid);
1945 // We have an unexpected klass, branch to ic_miss_stub.
1946 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1947 relocInfo::runtime_call_type);
1948 __ bind(valid);
1949 }
1950
1951 // Argument is valid and klass is as expected, continue.
1952 }
1953
1954 #if 0 // TODO: PPC port
1955 // Optimize UEP code on z (save a load_const() call in main path).
1956 int MachUEPNode::ep_offset() {
1957 return 0;
1958 }
1959 #endif
1960
1961 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1962 // Variable size. Determine dynamically.
1963 return MachNode::size(ra_);
1964 }
1965
1966 //=============================================================================
1967
1968 %} // interrupt source
1969
1970 source_hpp %{ // Header information of the source block.
1971
1972 class HandlerImpl {
1973
1974 public:
1975
1976 static int emit_exception_handler(CodeBuffer &cbuf);
1977 static int emit_deopt_handler(CodeBuffer& cbuf);
1978
1979 static uint size_exception_handler() {
1980 // The exception_handler is a b64_patchable.
1981 return MacroAssembler::b64_patchable_size;
1982 }
1983
1984 static uint size_deopt_handler() {
1985 // The deopt_handler is a bl64_patchable.
1986 return MacroAssembler::bl64_patchable_size;
1987 }
1988
1989 };
1990
1991 %} // end source_hpp
1992
1993 source %{
1994
1995 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1996 MacroAssembler _masm(&cbuf);
1997
1998 address base = __ start_a_stub(size_exception_handler());
1999 if (base == NULL) return 0; // CodeBuffer::expand failed
2000
2001 int offset = __ offset();
2002 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2003 relocInfo::runtime_call_type);
2004 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2005 __ end_a_stub();
2006
2007 return offset;
2008 }
2009
2010 // The deopt_handler is like the exception handler, but it calls to
2011 // the deoptimization blob instead of jumping to the exception blob.
2012 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2013 MacroAssembler _masm(&cbuf);
2014
2015 address base = __ start_a_stub(size_deopt_handler());
2016 if (base == NULL) return 0; // CodeBuffer::expand failed
2017
2018 int offset = __ offset();
2019 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2020 relocInfo::runtime_call_type);
2021 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2022 __ end_a_stub();
2023
2024 return offset;
2025 }
2026
2027 //=============================================================================
2028
2029 // Use a frame slots bias for frameless methods if accessing the stack.
2030 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2031 if (as_Register(reg_enc) == R1_SP) {
2032 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2033 }
2034 return 0;
2035 }
2036
2037 const bool Matcher::match_rule_supported(int opcode) {
2038 if (!has_match_rule(opcode))
2039 return false;
2040
2041 switch (opcode) {
2042 case Op_SqrtD:
2043 return VM_Version::has_fsqrt();
2044 case Op_CountLeadingZerosI:
2045 case Op_CountLeadingZerosL:
2046 case Op_CountTrailingZerosI:
2047 case Op_CountTrailingZerosL:
2048 if (!UseCountLeadingZerosInstructionsPPC64)
2049 return false;
2050 break;
2051
2052 case Op_PopCountI:
2053 case Op_PopCountL:
2054 return (UsePopCountInstruction && VM_Version::has_popcntw());
2055
2056 case Op_StrComp:
2057 return SpecialStringCompareTo && !CompactStrings;
2058 case Op_StrEquals:
2059 return SpecialStringEquals && !CompactStrings;
2060 case Op_StrIndexOf:
2061 return SpecialStringIndexOf && !CompactStrings;
2062 }
2063
2064 return true; // Per default match rules are supported.
2065 }
2066
2067 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2068
2069 // TODO
2070 // identify extra cases that we might want to provide match rules for
2071 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2072 bool ret_value = match_rule_supported(opcode);
2073 // Add rules here.
2074
2075 return ret_value; // Per default match rules are supported.
2076 }
2077
2078 const int Matcher::float_pressure(int default_pressure_threshold) {
2079 return default_pressure_threshold;
2080 }
2081
2082 int Matcher::regnum_to_fpu_offset(int regnum) {
2083 // No user for this method?
2084 Unimplemented();
2085 return 999;
2086 }
2087
2088 const bool Matcher::convL2FSupported(void) {
2089 // fcfids can do the conversion (>= Power7).
2090 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2091 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2092 }
2093
2094 // Vector width in bytes.
2095 const int Matcher::vector_width_in_bytes(BasicType bt) {
2096 assert(MaxVectorSize == 8, "");
2097 return 8;
2098 }
2099
2100 // Vector ideal reg.
2101 const int Matcher::vector_ideal_reg(int size) {
2102 assert(MaxVectorSize == 8 && size == 8, "");
2103 return Op_RegL;
2104 }
2105
2106 const int Matcher::vector_shift_count_ideal_reg(int size) {
2107 fatal("vector shift is not supported");
2108 return Node::NotAMachineReg;
2109 }
2110
2111 // Limits on vector size (number of elements) loaded into vector.
2112 const int Matcher::max_vector_size(const BasicType bt) {
2113 assert(is_java_primitive(bt), "only primitive type vectors");
2114 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2115 }
2116
2117 const int Matcher::min_vector_size(const BasicType bt) {
2118 return max_vector_size(bt); // Same as max.
2119 }
2120
2121 // PPC doesn't support misaligned vectors store/load.
2122 const bool Matcher::misaligned_vectors_ok() {
2123 return false;
2124 }
2125
2126 // PPC AES support not yet implemented
2127 const bool Matcher::pass_original_key_for_aes() {
2128 return false;
2129 }
2130
2131 // RETURNS: whether this branch offset is short enough that a short
2132 // branch can be used.
2133 //
2134 // If the platform does not provide any short branch variants, then
2135 // this method should return `false' for offset 0.
2136 //
2137 // `Compile::Fill_buffer' will decide on basis of this information
2138 // whether to do the pass `Compile::Shorten_branches' at all.
2139 //
2140 // And `Compile::Shorten_branches' will decide on basis of this
2141 // information whether to replace particular branch sites by short
2142 // ones.
2143 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2144 // Is the offset within the range of a ppc64 pc relative branch?
2145 bool b;
2146
2147 const int safety_zone = 3 * BytesPerInstWord;
2148 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2149 29 - 16 + 1 + 2);
2150 return b;
2151 }
2152
2153 const bool Matcher::isSimpleConstant64(jlong value) {
2154 // Probably always true, even if a temp register is required.
2155 return true;
2156 }
2157 /* TODO: PPC port
2158 // Make a new machine dependent decode node (with its operands).
2159 MachTypeNode *Matcher::make_decode_node() {
2160 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2161 "This method is only implemented for unscaled cOops mode so far");
2162 MachTypeNode *decode = new decodeN_unscaledNode();
2163 decode->set_opnd_array(0, new iRegPdstOper());
2164 decode->set_opnd_array(1, new iRegNsrcOper());
2165 return decode;
2166 }
2167 */
2168 // Threshold size for cleararray.
2169 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2170
2171 // false => size gets scaled to BytesPerLong, ok.
2172 const bool Matcher::init_array_count_is_in_bytes = false;
2173
2174 // Use conditional move (CMOVL) on Power7.
2175 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2176
2177 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2178 // fsel doesn't accept a condition register as input, so this would be slightly different.
2179 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2180
2181 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2182 const bool Matcher::require_postalloc_expand = true;
2183
2184 // Should the Matcher clone shifts on addressing modes, expecting them to
2185 // be subsumed into complex addressing expressions or compute them into
2186 // registers? True for Intel but false for most RISCs.
2187 const bool Matcher::clone_shift_expressions = false;
2188
2189 // Do we need to mask the count passed to shift instructions or does
2190 // the cpu only look at the lower 5/6 bits anyway?
2191 // PowerPC requires masked shift counts.
2192 const bool Matcher::need_masked_shift_count = true;
2193
2194 // This affects two different things:
2195 // - how Decode nodes are matched
2196 // - how ImplicitNullCheck opportunities are recognized
2197 // If true, the matcher will try to remove all Decodes and match them
2198 // (as operands) into nodes. NullChecks are not prepared to deal with
2199 // Decodes by final_graph_reshaping().
2200 // If false, final_graph_reshaping() forces the decode behind the Cmp
2201 // for a NullCheck. The matcher matches the Decode node into a register.
2202 // Implicit_null_check optimization moves the Decode along with the
2203 // memory operation back up before the NullCheck.
2204 bool Matcher::narrow_oop_use_complex_address() {
2205 // TODO: PPC port if (MatchDecodeNodes) return true;
2206 return false;
2207 }
2208
2209 bool Matcher::narrow_klass_use_complex_address() {
2210 NOT_LP64(ShouldNotCallThis());
2211 assert(UseCompressedClassPointers, "only for compressed klass code");
2212 // TODO: PPC port if (MatchDecodeNodes) return true;
2213 return false;
2214 }
2215
2216 // Is it better to copy float constants, or load them directly from memory?
2217 // Intel can load a float constant from a direct address, requiring no
2218 // extra registers. Most RISCs will have to materialize an address into a
2219 // register first, so they would do better to copy the constant from stack.
2220 const bool Matcher::rematerialize_float_constants = false;
2221
2222 // If CPU can load and store mis-aligned doubles directly then no fixup is
2223 // needed. Else we split the double into 2 integer pieces and move it
2224 // piece-by-piece. Only happens when passing doubles into C code as the
2225 // Java calling convention forces doubles to be aligned.
2226 const bool Matcher::misaligned_doubles_ok = true;
2227
2228 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2229 Unimplemented();
2230 }
2231
2232 // Advertise here if the CPU requires explicit rounding operations
2233 // to implement the UseStrictFP mode.
2234 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2235
2236 // Do floats take an entire double register or just half?
2237 //
2238 // A float occupies a ppc64 double register. For the allocator, a
2239 // ppc64 double register appears as a pair of float registers.
2240 bool Matcher::float_in_double() { return true; }
2241
2242 // Do ints take an entire long register or just half?
2243 // The relevant question is how the int is callee-saved:
2244 // the whole long is written but de-opt'ing will have to extract
2245 // the relevant 32 bits.
2246 const bool Matcher::int_in_long = true;
2247
2248 // Constants for c2c and c calling conventions.
2249
2250 const MachRegisterNumbers iarg_reg[8] = {
2251 R3_num, R4_num, R5_num, R6_num,
2252 R7_num, R8_num, R9_num, R10_num
2253 };
2254
2255 const MachRegisterNumbers farg_reg[13] = {
2256 F1_num, F2_num, F3_num, F4_num,
2257 F5_num, F6_num, F7_num, F8_num,
2258 F9_num, F10_num, F11_num, F12_num,
2259 F13_num
2260 };
2261
2262 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2263
2264 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2265
2266 // Return whether or not this register is ever used as an argument. This
2267 // function is used on startup to build the trampoline stubs in generateOptoStub.
2268 // Registers not mentioned will be killed by the VM call in the trampoline, and
2269 // arguments in those registers not be available to the callee.
2270 bool Matcher::can_be_java_arg(int reg) {
2271 // We return true for all registers contained in iarg_reg[] and
2272 // farg_reg[] and their virtual halves.
2273 // We must include the virtual halves in order to get STDs and LDs
2274 // instead of STWs and LWs in the trampoline stubs.
2275
2276 if ( reg == R3_num || reg == R3_H_num
2277 || reg == R4_num || reg == R4_H_num
2278 || reg == R5_num || reg == R5_H_num
2279 || reg == R6_num || reg == R6_H_num
2280 || reg == R7_num || reg == R7_H_num
2281 || reg == R8_num || reg == R8_H_num
2282 || reg == R9_num || reg == R9_H_num
2283 || reg == R10_num || reg == R10_H_num)
2284 return true;
2285
2286 if ( reg == F1_num || reg == F1_H_num
2287 || reg == F2_num || reg == F2_H_num
2288 || reg == F3_num || reg == F3_H_num
2289 || reg == F4_num || reg == F4_H_num
2290 || reg == F5_num || reg == F5_H_num
2291 || reg == F6_num || reg == F6_H_num
2292 || reg == F7_num || reg == F7_H_num
2293 || reg == F8_num || reg == F8_H_num
2294 || reg == F9_num || reg == F9_H_num
2295 || reg == F10_num || reg == F10_H_num
2296 || reg == F11_num || reg == F11_H_num
2297 || reg == F12_num || reg == F12_H_num
2298 || reg == F13_num || reg == F13_H_num)
2299 return true;
2300
2301 return false;
2302 }
2303
2304 bool Matcher::is_spillable_arg(int reg) {
2305 return can_be_java_arg(reg);
2306 }
2307
2308 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2309 return false;
2310 }
2311
2312 // Register for DIVI projection of divmodI.
2313 RegMask Matcher::divI_proj_mask() {
2314 ShouldNotReachHere();
2315 return RegMask();
2316 }
2317
2318 // Register for MODI projection of divmodI.
2319 RegMask Matcher::modI_proj_mask() {
2320 ShouldNotReachHere();
2321 return RegMask();
2322 }
2323
2324 // Register for DIVL projection of divmodL.
2325 RegMask Matcher::divL_proj_mask() {
2326 ShouldNotReachHere();
2327 return RegMask();
2328 }
2329
2330 // Register for MODL projection of divmodL.
2331 RegMask Matcher::modL_proj_mask() {
2332 ShouldNotReachHere();
2333 return RegMask();
2334 }
2335
2336 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2337 return RegMask();
2338 }
2339
2340 %}
2341
2342 //----------ENCODING BLOCK-----------------------------------------------------
2343 // This block specifies the encoding classes used by the compiler to output
2344 // byte streams. Encoding classes are parameterized macros used by
2345 // Machine Instruction Nodes in order to generate the bit encoding of the
2346 // instruction. Operands specify their base encoding interface with the
2347 // interface keyword. There are currently supported four interfaces,
2348 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2349 // operand to generate a function which returns its register number when
2350 // queried. CONST_INTER causes an operand to generate a function which
2351 // returns the value of the constant when queried. MEMORY_INTER causes an
2352 // operand to generate four functions which return the Base Register, the
2353 // Index Register, the Scale Value, and the Offset Value of the operand when
2354 // queried. COND_INTER causes an operand to generate six functions which
2355 // return the encoding code (ie - encoding bits for the instruction)
2356 // associated with each basic boolean condition for a conditional instruction.
2357 //
2358 // Instructions specify two basic values for encoding. Again, a function
2359 // is available to check if the constant displacement is an oop. They use the
2360 // ins_encode keyword to specify their encoding classes (which must be
2361 // a sequence of enc_class names, and their parameters, specified in
2362 // the encoding block), and they use the
2363 // opcode keyword to specify, in order, their primary, secondary, and
2364 // tertiary opcode. Only the opcode sections which a particular instruction
2365 // needs for encoding need to be specified.
2366 encode %{
2367 enc_class enc_unimplemented %{
2368 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2369 MacroAssembler _masm(&cbuf);
2370 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2371 %}
2372
2373 enc_class enc_untested %{
2374 #ifdef ASSERT
2375 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2376 MacroAssembler _masm(&cbuf);
2377 __ untested("Untested mach node encoding in AD file.");
2378 #else
2379 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2380 #endif
2381 %}
2382
2383 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2384 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2385 MacroAssembler _masm(&cbuf);
2386 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2387 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2388 %}
2389
2390 // Load acquire.
2391 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2392 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2393 MacroAssembler _masm(&cbuf);
2394 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2395 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2396 __ twi_0($dst$$Register);
2397 __ isync();
2398 %}
2399
2400 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2401 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2402
2403 MacroAssembler _masm(&cbuf);
2404 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2405 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2406 %}
2407
2408 // Load acquire.
2409 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2410 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2411
2412 MacroAssembler _masm(&cbuf);
2413 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2414 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2415 __ twi_0($dst$$Register);
2416 __ isync();
2417 %}
2418
2419 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2420 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2421
2422 MacroAssembler _masm(&cbuf);
2423 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2424 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2425 %}
2426
2427 // Load acquire.
2428 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2429 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2430
2431 MacroAssembler _masm(&cbuf);
2432 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2433 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2434 __ twi_0($dst$$Register);
2435 __ isync();
2436 %}
2437
2438 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2439 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2440 MacroAssembler _masm(&cbuf);
2441 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2442 // Operand 'ds' requires 4-alignment.
2443 assert((Idisp & 0x3) == 0, "unaligned offset");
2444 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2445 %}
2446
2447 // Load acquire.
2448 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2449 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2450 MacroAssembler _masm(&cbuf);
2451 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2452 // Operand 'ds' requires 4-alignment.
2453 assert((Idisp & 0x3) == 0, "unaligned offset");
2454 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2455 __ twi_0($dst$$Register);
2456 __ isync();
2457 %}
2458
2459 enc_class enc_lfd(RegF dst, memory mem) %{
2460 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2461 MacroAssembler _masm(&cbuf);
2462 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2463 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2464 %}
2465
2466 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2467 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2468
2469 MacroAssembler _masm(&cbuf);
2470 int toc_offset = 0;
2471
2472 if (!ra_->C->in_scratch_emit_size()) {
2473 address const_toc_addr;
2474 // Create a non-oop constant, no relocation needed.
2475 // If it is an IC, it has a virtual_call_Relocation.
2476 const_toc_addr = __ long_constant((jlong)$src$$constant);
2477
2478 // Get the constant's TOC offset.
2479 toc_offset = __ offset_to_method_toc(const_toc_addr);
2480
2481 // Keep the current instruction offset in mind.
2482 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2483 }
2484
2485 __ ld($dst$$Register, toc_offset, $toc$$Register);
2486 %}
2487
2488 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2489 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2490
2491 MacroAssembler _masm(&cbuf);
2492
2493 if (!ra_->C->in_scratch_emit_size()) {
2494 address const_toc_addr;
2495 // Create a non-oop constant, no relocation needed.
2496 // If it is an IC, it has a virtual_call_Relocation.
2497 const_toc_addr = __ long_constant((jlong)$src$$constant);
2498
2499 // Get the constant's TOC offset.
2500 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2501 // Store the toc offset of the constant.
2502 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2503
2504 // Also keep the current instruction offset in mind.
2505 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2506 }
2507
2508 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2509 %}
2510
2511 %} // encode
2512
2513 source %{
2514
2515 typedef struct {
2516 loadConL_hiNode *_large_hi;
2517 loadConL_loNode *_large_lo;
2518 loadConLNode *_small;
2519 MachNode *_last;
2520 } loadConLNodesTuple;
2521
2522 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2523 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2524 loadConLNodesTuple nodes;
2525
2526 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2527 if (large_constant_pool) {
2528 // Create new nodes.
2529 loadConL_hiNode *m1 = new loadConL_hiNode();
2530 loadConL_loNode *m2 = new loadConL_loNode();
2531
2532 // inputs for new nodes
2533 m1->add_req(NULL, toc);
2534 m2->add_req(NULL, m1);
2535
2536 // operands for new nodes
2537 m1->_opnds[0] = new iRegLdstOper(); // dst
2538 m1->_opnds[1] = immSrc; // src
2539 m1->_opnds[2] = new iRegPdstOper(); // toc
2540 m2->_opnds[0] = new iRegLdstOper(); // dst
2541 m2->_opnds[1] = immSrc; // src
2542 m2->_opnds[2] = new iRegLdstOper(); // base
2543
2544 // Initialize ins_attrib TOC fields.
2545 m1->_const_toc_offset = -1;
2546 m2->_const_toc_offset_hi_node = m1;
2547
2548 // Initialize ins_attrib instruction offset.
2549 m1->_cbuf_insts_offset = -1;
2550
2551 // register allocation for new nodes
2552 ra_->set_pair(m1->_idx, reg_second, reg_first);
2553 ra_->set_pair(m2->_idx, reg_second, reg_first);
2554
2555 // Create result.
2556 nodes._large_hi = m1;
2557 nodes._large_lo = m2;
2558 nodes._small = NULL;
2559 nodes._last = nodes._large_lo;
2560 assert(m2->bottom_type()->isa_long(), "must be long");
2561 } else {
2562 loadConLNode *m2 = new loadConLNode();
2563
2564 // inputs for new nodes
2565 m2->add_req(NULL, toc);
2566
2567 // operands for new nodes
2568 m2->_opnds[0] = new iRegLdstOper(); // dst
2569 m2->_opnds[1] = immSrc; // src
2570 m2->_opnds[2] = new iRegPdstOper(); // toc
2571
2572 // Initialize ins_attrib instruction offset.
2573 m2->_cbuf_insts_offset = -1;
2574
2575 // register allocation for new nodes
2576 ra_->set_pair(m2->_idx, reg_second, reg_first);
2577
2578 // Create result.
2579 nodes._large_hi = NULL;
2580 nodes._large_lo = NULL;
2581 nodes._small = m2;
2582 nodes._last = nodes._small;
2583 assert(m2->bottom_type()->isa_long(), "must be long");
2584 }
2585
2586 return nodes;
2587 }
2588
2589 %} // source
2590
2591 encode %{
2592 // Postalloc expand emitter for loading a long constant from the method's TOC.
2593 // Enc_class needed as consttanttablebase is not supported by postalloc
2594 // expand.
2595 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2596 // Create new nodes.
2597 loadConLNodesTuple loadConLNodes =
2598 loadConLNodesTuple_create(ra_, n_toc, op_src,
2599 ra_->get_reg_second(this), ra_->get_reg_first(this));
2600
2601 // Push new nodes.
2602 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2603 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2604
2605 // some asserts
2606 assert(nodes->length() >= 1, "must have created at least 1 node");
2607 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2608 %}
2609
2610 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2611 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2612
2613 MacroAssembler _masm(&cbuf);
2614 int toc_offset = 0;
2615
2616 if (!ra_->C->in_scratch_emit_size()) {
2617 intptr_t val = $src$$constant;
2618 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2619 address const_toc_addr;
2620 if (constant_reloc == relocInfo::oop_type) {
2621 // Create an oop constant and a corresponding relocation.
2622 AddressLiteral a = __ allocate_oop_address((jobject)val);
2623 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2624 __ relocate(a.rspec());
2625 } else if (constant_reloc == relocInfo::metadata_type) {
2626 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2627 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2628 __ relocate(a.rspec());
2629 } else {
2630 // Create a non-oop constant, no relocation needed.
2631 const_toc_addr = __ long_constant((jlong)$src$$constant);
2632 }
2633
2634 // Get the constant's TOC offset.
2635 toc_offset = __ offset_to_method_toc(const_toc_addr);
2636 }
2637
2638 __ ld($dst$$Register, toc_offset, $toc$$Register);
2639 %}
2640
2641 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2642 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2643
2644 MacroAssembler _masm(&cbuf);
2645 if (!ra_->C->in_scratch_emit_size()) {
2646 intptr_t val = $src$$constant;
2647 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2648 address const_toc_addr;
2649 if (constant_reloc == relocInfo::oop_type) {
2650 // Create an oop constant and a corresponding relocation.
2651 AddressLiteral a = __ allocate_oop_address((jobject)val);
2652 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2653 __ relocate(a.rspec());
2654 } else if (constant_reloc == relocInfo::metadata_type) {
2655 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2656 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2657 __ relocate(a.rspec());
2658 } else { // non-oop pointers, e.g. card mark base, heap top
2659 // Create a non-oop constant, no relocation needed.
2660 const_toc_addr = __ long_constant((jlong)$src$$constant);
2661 }
2662
2663 // Get the constant's TOC offset.
2664 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2665 // Store the toc offset of the constant.
2666 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2667 }
2668
2669 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2670 %}
2671
2672 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2673 // Enc_class needed as consttanttablebase is not supported by postalloc
2674 // expand.
2675 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2676 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2677 if (large_constant_pool) {
2678 // Create new nodes.
2679 loadConP_hiNode *m1 = new loadConP_hiNode();
2680 loadConP_loNode *m2 = new loadConP_loNode();
2681
2682 // inputs for new nodes
2683 m1->add_req(NULL, n_toc);
2684 m2->add_req(NULL, m1);
2685
2686 // operands for new nodes
2687 m1->_opnds[0] = new iRegPdstOper(); // dst
2688 m1->_opnds[1] = op_src; // src
2689 m1->_opnds[2] = new iRegPdstOper(); // toc
2690 m2->_opnds[0] = new iRegPdstOper(); // dst
2691 m2->_opnds[1] = op_src; // src
2692 m2->_opnds[2] = new iRegLdstOper(); // base
2693
2694 // Initialize ins_attrib TOC fields.
2695 m1->_const_toc_offset = -1;
2696 m2->_const_toc_offset_hi_node = m1;
2697
2698 // Register allocation for new nodes.
2699 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2700 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2701
2702 nodes->push(m1);
2703 nodes->push(m2);
2704 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2705 } else {
2706 loadConPNode *m2 = new loadConPNode();
2707
2708 // inputs for new nodes
2709 m2->add_req(NULL, n_toc);
2710
2711 // operands for new nodes
2712 m2->_opnds[0] = new iRegPdstOper(); // dst
2713 m2->_opnds[1] = op_src; // src
2714 m2->_opnds[2] = new iRegPdstOper(); // toc
2715
2716 // Register allocation for new nodes.
2717 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2718
2719 nodes->push(m2);
2720 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2721 }
2722 %}
2723
2724 // Enc_class needed as consttanttablebase is not supported by postalloc
2725 // expand.
2726 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2727 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2728
2729 MachNode *m2;
2730 if (large_constant_pool) {
2731 m2 = new loadConFCompNode();
2732 } else {
2733 m2 = new loadConFNode();
2734 }
2735 // inputs for new nodes
2736 m2->add_req(NULL, n_toc);
2737
2738 // operands for new nodes
2739 m2->_opnds[0] = op_dst;
2740 m2->_opnds[1] = op_src;
2741 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2742
2743 // register allocation for new nodes
2744 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2745 nodes->push(m2);
2746 %}
2747
2748 // Enc_class needed as consttanttablebase is not supported by postalloc
2749 // expand.
2750 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2751 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2752
2753 MachNode *m2;
2754 if (large_constant_pool) {
2755 m2 = new loadConDCompNode();
2756 } else {
2757 m2 = new loadConDNode();
2758 }
2759 // inputs for new nodes
2760 m2->add_req(NULL, n_toc);
2761
2762 // operands for new nodes
2763 m2->_opnds[0] = op_dst;
2764 m2->_opnds[1] = op_src;
2765 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2766
2767 // register allocation for new nodes
2768 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2769 nodes->push(m2);
2770 %}
2771
2772 enc_class enc_stw(iRegIsrc src, memory mem) %{
2773 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2774 MacroAssembler _masm(&cbuf);
2775 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2776 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2777 %}
2778
2779 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2780 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2781 MacroAssembler _masm(&cbuf);
2782 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2783 // Operand 'ds' requires 4-alignment.
2784 assert((Idisp & 0x3) == 0, "unaligned offset");
2785 __ std($src$$Register, Idisp, $mem$$base$$Register);
2786 %}
2787
2788 enc_class enc_stfs(RegF src, memory mem) %{
2789 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2790 MacroAssembler _masm(&cbuf);
2791 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2792 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2793 %}
2794
2795 enc_class enc_stfd(RegF src, memory mem) %{
2796 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2797 MacroAssembler _masm(&cbuf);
2798 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2799 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2800 %}
2801
2802 // Use release_store for card-marking to ensure that previous
2803 // oop-stores are visible before the card-mark change.
2804 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2805 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2806 // FIXME: Implement this as a cmove and use a fixed condition code
2807 // register which is written on every transition to compiled code,
2808 // e.g. in call-stub and when returning from runtime stubs.
2809 //
2810 // Proposed code sequence for the cmove implementation:
2811 //
2812 // Label skip_release;
2813 // __ beq(CCRfixed, skip_release);
2814 // __ release();
2815 // __ bind(skip_release);
2816 // __ stb(card mark);
2817
2818 MacroAssembler _masm(&cbuf);
2819 Label skip_storestore;
2820
2821 #if 0 // TODO: PPC port
2822 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2823 // StoreStore barrier conditionally.
2824 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2825 __ cmpwi($crx$$CondRegister, R0, 0);
2826 __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2827 #endif
2828 __ li(R0, 0);
2829 __ membar(Assembler::StoreStore);
2830 #if 0 // TODO: PPC port
2831 __ bind(skip_storestore);
2832 #endif
2833
2834 // Do the store.
2835 if ($mem$$index == 0) {
2836 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2837 } else {
2838 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2839 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2840 }
2841 %}
2842
2843 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2844
2845 if (VM_Version::has_isel()) {
2846 // use isel instruction with Power 7
2847 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2848 encodeP_subNode *n_sub_base = new encodeP_subNode();
2849 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2850 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2851
2852 n_compare->add_req(n_region, n_src);
2853 n_compare->_opnds[0] = op_crx;
2854 n_compare->_opnds[1] = op_src;
2855 n_compare->_opnds[2] = new immL16Oper(0);
2856
2857 n_sub_base->add_req(n_region, n_src);
2858 n_sub_base->_opnds[0] = op_dst;
2859 n_sub_base->_opnds[1] = op_src;
2860 n_sub_base->_bottom_type = _bottom_type;
2861
2862 n_shift->add_req(n_region, n_sub_base);
2863 n_shift->_opnds[0] = op_dst;
2864 n_shift->_opnds[1] = op_dst;
2865 n_shift->_bottom_type = _bottom_type;
2866
2867 n_cond_set->add_req(n_region, n_compare, n_shift);
2868 n_cond_set->_opnds[0] = op_dst;
2869 n_cond_set->_opnds[1] = op_crx;
2870 n_cond_set->_opnds[2] = op_dst;
2871 n_cond_set->_bottom_type = _bottom_type;
2872
2873 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2874 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2875 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2876 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2877
2878 nodes->push(n_compare);
2879 nodes->push(n_sub_base);
2880 nodes->push(n_shift);
2881 nodes->push(n_cond_set);
2882
2883 } else {
2884 // before Power 7
2885 moveRegNode *n_move = new moveRegNode();
2886 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2887 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2888 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode();
2889
2890 n_move->add_req(n_region, n_src);
2891 n_move->_opnds[0] = op_dst;
2892 n_move->_opnds[1] = op_src;
2893 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2894
2895 n_compare->add_req(n_region, n_src);
2896 n_compare->add_prec(n_move);
2897
2898 n_compare->_opnds[0] = op_crx;
2899 n_compare->_opnds[1] = op_src;
2900 n_compare->_opnds[2] = new immL16Oper(0);
2901
2902 n_sub_base->add_req(n_region, n_compare, n_src);
2903 n_sub_base->_opnds[0] = op_dst;
2904 n_sub_base->_opnds[1] = op_crx;
2905 n_sub_base->_opnds[2] = op_src;
2906 n_sub_base->_bottom_type = _bottom_type;
2907
2908 n_shift->add_req(n_region, n_sub_base);
2909 n_shift->_opnds[0] = op_dst;
2910 n_shift->_opnds[1] = op_dst;
2911 n_shift->_bottom_type = _bottom_type;
2912
2913 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2914 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2915 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2916 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2917
2918 nodes->push(n_move);
2919 nodes->push(n_compare);
2920 nodes->push(n_sub_base);
2921 nodes->push(n_shift);
2922 }
2923
2924 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2925 %}
2926
2927 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2928
2929 encodeP_subNode *n1 = new encodeP_subNode();
2930 n1->add_req(n_region, n_src);
2931 n1->_opnds[0] = op_dst;
2932 n1->_opnds[1] = op_src;
2933 n1->_bottom_type = _bottom_type;
2934
2935 encodeP_shiftNode *n2 = new encodeP_shiftNode();
2936 n2->add_req(n_region, n1);
2937 n2->_opnds[0] = op_dst;
2938 n2->_opnds[1] = op_dst;
2939 n2->_bottom_type = _bottom_type;
2940 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2941 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2942
2943 nodes->push(n1);
2944 nodes->push(n2);
2945 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2946 %}
2947
2948 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2949 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
2950 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
2951
2952 n_compare->add_req(n_region, n_src);
2953 n_compare->_opnds[0] = op_crx;
2954 n_compare->_opnds[1] = op_src;
2955 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2956
2957 n_shift->add_req(n_region, n_src);
2958 n_shift->_opnds[0] = op_dst;
2959 n_shift->_opnds[1] = op_src;
2960 n_shift->_bottom_type = _bottom_type;
2961
2962 if (VM_Version::has_isel()) {
2963 // use isel instruction with Power 7
2964
2965 decodeN_addNode *n_add_base = new decodeN_addNode();
2966 n_add_base->add_req(n_region, n_shift);
2967 n_add_base->_opnds[0] = op_dst;
2968 n_add_base->_opnds[1] = op_dst;
2969 n_add_base->_bottom_type = _bottom_type;
2970
2971 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2972 n_cond_set->add_req(n_region, n_compare, n_add_base);
2973 n_cond_set->_opnds[0] = op_dst;
2974 n_cond_set->_opnds[1] = op_crx;
2975 n_cond_set->_opnds[2] = op_dst;
2976 n_cond_set->_bottom_type = _bottom_type;
2977
2978 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2979 ra_->set_oop(n_cond_set, true);
2980
2981 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2982 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2983 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2984 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2985
2986 nodes->push(n_compare);
2987 nodes->push(n_shift);
2988 nodes->push(n_add_base);
2989 nodes->push(n_cond_set);
2990
2991 } else {
2992 // before Power 7
2993 cond_add_baseNode *n_add_base = new cond_add_baseNode();
2994
2995 n_add_base->add_req(n_region, n_compare, n_shift);
2996 n_add_base->_opnds[0] = op_dst;
2997 n_add_base->_opnds[1] = op_crx;
2998 n_add_base->_opnds[2] = op_dst;
2999 n_add_base->_bottom_type = _bottom_type;
3000
3001 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3002 ra_->set_oop(n_add_base, true);
3003
3004 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3005 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3006 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3007
3008 nodes->push(n_compare);
3009 nodes->push(n_shift);
3010 nodes->push(n_add_base);
3011 }
3012 %}
3013
3014 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3015 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3016 n1->add_req(n_region, n_src);
3017 n1->_opnds[0] = op_dst;
3018 n1->_opnds[1] = op_src;
3019 n1->_bottom_type = _bottom_type;
3020
3021 decodeN_addNode *n2 = new decodeN_addNode();
3022 n2->add_req(n_region, n1);
3023 n2->_opnds[0] = op_dst;
3024 n2->_opnds[1] = op_dst;
3025 n2->_bottom_type = _bottom_type;
3026 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3027 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3028
3029 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3030 ra_->set_oop(n2, true);
3031
3032 nodes->push(n1);
3033 nodes->push(n2);
3034 %}
3035
3036 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3037 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3038
3039 MacroAssembler _masm(&cbuf);
3040 int cc = $cmp$$cmpcode;
3041 int flags_reg = $crx$$reg;
3042 Label done;
3043 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3044 // Branch if not (cmp crx).
3045 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3046 __ mr($dst$$Register, $src$$Register);
3047 // TODO PPC port __ endgroup_if_needed(_size == 12);
3048 __ bind(done);
3049 %}
3050
3051 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3052 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3053
3054 MacroAssembler _masm(&cbuf);
3055 Label done;
3056 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3057 // Branch if not (cmp crx).
3058 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3059 __ li($dst$$Register, $src$$constant);
3060 // TODO PPC port __ endgroup_if_needed(_size == 12);
3061 __ bind(done);
3062 %}
3063
3064 // New atomics.
3065 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3066 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3067
3068 MacroAssembler _masm(&cbuf);
3069 Register Rtmp = R0;
3070 Register Rres = $res$$Register;
3071 Register Rsrc = $src$$Register;
3072 Register Rptr = $mem_ptr$$Register;
3073 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3074 Register Rold = RegCollision ? Rtmp : Rres;
3075
3076 Label Lretry;
3077 __ bind(Lretry);
3078 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3079 __ add(Rtmp, Rsrc, Rold);
3080 __ stwcx_(Rtmp, Rptr);
3081 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3082 __ bne_predict_not_taken(CCR0, Lretry);
3083 } else {
3084 __ bne( CCR0, Lretry);
3085 }
3086 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3087 __ fence();
3088 %}
3089
3090 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3091 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3092
3093 MacroAssembler _masm(&cbuf);
3094 Register Rtmp = R0;
3095 Register Rres = $res$$Register;
3096 Register Rsrc = $src$$Register;
3097 Register Rptr = $mem_ptr$$Register;
3098 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3099 Register Rold = RegCollision ? Rtmp : Rres;
3100
3101 Label Lretry;
3102 __ bind(Lretry);
3103 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3104 __ add(Rtmp, Rsrc, Rold);
3105 __ stdcx_(Rtmp, Rptr);
3106 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3107 __ bne_predict_not_taken(CCR0, Lretry);
3108 } else {
3109 __ bne( CCR0, Lretry);
3110 }
3111 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3112 __ fence();
3113 %}
3114
3115 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3116 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3117
3118 MacroAssembler _masm(&cbuf);
3119 Register Rtmp = R0;
3120 Register Rres = $res$$Register;
3121 Register Rsrc = $src$$Register;
3122 Register Rptr = $mem_ptr$$Register;
3123 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3124 Register Rold = RegCollision ? Rtmp : Rres;
3125
3126 Label Lretry;
3127 __ bind(Lretry);
3128 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3129 __ stwcx_(Rsrc, Rptr);
3130 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3131 __ bne_predict_not_taken(CCR0, Lretry);
3132 } else {
3133 __ bne( CCR0, Lretry);
3134 }
3135 if (RegCollision) __ mr(Rres, Rtmp);
3136 __ fence();
3137 %}
3138
3139 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3140 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3141
3142 MacroAssembler _masm(&cbuf);
3143 Register Rtmp = R0;
3144 Register Rres = $res$$Register;
3145 Register Rsrc = $src$$Register;
3146 Register Rptr = $mem_ptr$$Register;
3147 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3148 Register Rold = RegCollision ? Rtmp : Rres;
3149
3150 Label Lretry;
3151 __ bind(Lretry);
3152 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3153 __ stdcx_(Rsrc, Rptr);
3154 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3155 __ bne_predict_not_taken(CCR0, Lretry);
3156 } else {
3157 __ bne( CCR0, Lretry);
3158 }
3159 if (RegCollision) __ mr(Rres, Rtmp);
3160 __ fence();
3161 %}
3162
3163 // This enc_class is needed so that scheduler gets proper
3164 // input mapping for latency computation.
3165 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3166 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3167 MacroAssembler _masm(&cbuf);
3168 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3169 %}
3170
3171 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3172 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3173
3174 MacroAssembler _masm(&cbuf);
3175
3176 Label done;
3177 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3178 __ li($dst$$Register, $zero$$constant);
3179 __ beq($crx$$CondRegister, done);
3180 __ li($dst$$Register, $notzero$$constant);
3181 __ bind(done);
3182 %}
3183
3184 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3185 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3186
3187 MacroAssembler _masm(&cbuf);
3188
3189 Label done;
3190 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3191 __ li($dst$$Register, $zero$$constant);
3192 __ beq($crx$$CondRegister, done);
3193 __ li($dst$$Register, $notzero$$constant);
3194 __ bind(done);
3195 %}
3196
3197 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3198 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3199
3200 MacroAssembler _masm(&cbuf);
3201 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3202 Label done;
3203 __ bso($crx$$CondRegister, done);
3204 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3205 // TODO PPC port __ endgroup_if_needed(_size == 12);
3206 __ bind(done);
3207 %}
3208
3209 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3210 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3211
3212 MacroAssembler _masm(&cbuf);
3213 Label d; // dummy
3214 __ bind(d);
3215 Label* p = ($lbl$$label);
3216 // `p' is `NULL' when this encoding class is used only to
3217 // determine the size of the encoded instruction.
3218 Label& l = (NULL == p)? d : *(p);
3219 int cc = $cmp$$cmpcode;
3220 int flags_reg = $crx$$reg;
3221 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3222 int bhint = Assembler::bhintNoHint;
3223
3224 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3225 if (_prob <= PROB_NEVER) {
3226 bhint = Assembler::bhintIsNotTaken;
3227 } else if (_prob >= PROB_ALWAYS) {
3228 bhint = Assembler::bhintIsTaken;
3229 }
3230 }
3231
3232 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3233 cc_to_biint(cc, flags_reg),
3234 l);
3235 %}
3236
3237 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3238 // The scheduler doesn't know about branch shortening, so we set the opcode
3239 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3240 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3241
3242 MacroAssembler _masm(&cbuf);
3243 Label d; // dummy
3244 __ bind(d);
3245 Label* p = ($lbl$$label);
3246 // `p' is `NULL' when this encoding class is used only to
3247 // determine the size of the encoded instruction.
3248 Label& l = (NULL == p)? d : *(p);
3249 int cc = $cmp$$cmpcode;
3250 int flags_reg = $crx$$reg;
3251 int bhint = Assembler::bhintNoHint;
3252
3253 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3254 if (_prob <= PROB_NEVER) {
3255 bhint = Assembler::bhintIsNotTaken;
3256 } else if (_prob >= PROB_ALWAYS) {
3257 bhint = Assembler::bhintIsTaken;
3258 }
3259 }
3260
3261 // Tell the conditional far branch to optimize itself when being relocated.
3262 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3263 cc_to_biint(cc, flags_reg),
3264 l,
3265 MacroAssembler::bc_far_optimize_on_relocate);
3266 %}
3267
3268 // Branch used with Power6 scheduling (can be shortened without changing the node).
3269 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3270 // The scheduler doesn't know about branch shortening, so we set the opcode
3271 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3272 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3273
3274 MacroAssembler _masm(&cbuf);
3275 Label d; // dummy
3276 __ bind(d);
3277 Label* p = ($lbl$$label);
3278 // `p' is `NULL' when this encoding class is used only to
3279 // determine the size of the encoded instruction.
3280 Label& l = (NULL == p)? d : *(p);
3281 int cc = $cmp$$cmpcode;
3282 int flags_reg = $crx$$reg;
3283 int bhint = Assembler::bhintNoHint;
3284
3285 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3286 if (_prob <= PROB_NEVER) {
3287 bhint = Assembler::bhintIsNotTaken;
3288 } else if (_prob >= PROB_ALWAYS) {
3289 bhint = Assembler::bhintIsTaken;
3290 }
3291 }
3292
3293 #if 0 // TODO: PPC port
3294 if (_size == 8) {
3295 // Tell the conditional far branch to optimize itself when being relocated.
3296 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3297 cc_to_biint(cc, flags_reg),
3298 l,
3299 MacroAssembler::bc_far_optimize_on_relocate);
3300 } else {
3301 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3302 cc_to_biint(cc, flags_reg),
3303 l);
3304 }
3305 #endif
3306 Unimplemented();
3307 %}
3308
3309 // Postalloc expand emitter for loading a replicatef float constant from
3310 // the method's TOC.
3311 // Enc_class needed as consttanttablebase is not supported by postalloc
3312 // expand.
3313 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3314 // Create new nodes.
3315
3316 // Make an operand with the bit pattern to load as float.
3317 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3318
3319 loadConLNodesTuple loadConLNodes =
3320 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3321 ra_->get_reg_second(this), ra_->get_reg_first(this));
3322
3323 // Push new nodes.
3324 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3325 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3326
3327 assert(nodes->length() >= 1, "must have created at least 1 node");
3328 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3329 %}
3330
3331 // This enc_class is needed so that scheduler gets proper
3332 // input mapping for latency computation.
3333 enc_class enc_poll(immI dst, iRegLdst poll) %{
3334 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3335 // Fake operand dst needed for PPC scheduler.
3336 assert($dst$$constant == 0x0, "dst must be 0x0");
3337
3338 MacroAssembler _masm(&cbuf);
3339 // Mark the code position where the load from the safepoint
3340 // polling page was emitted as relocInfo::poll_type.
3341 __ relocate(relocInfo::poll_type);
3342 __ load_from_polling_page($poll$$Register);
3343 %}
3344
3345 // A Java static call or a runtime call.
3346 //
3347 // Branch-and-link relative to a trampoline.
3348 // The trampoline loads the target address and does a long branch to there.
3349 // In case we call java, the trampoline branches to a interpreter_stub
3350 // which loads the inline cache and the real call target from the constant pool.
3351 //
3352 // This basically looks like this:
3353 //
3354 // >>>> consts -+ -+
3355 // | |- offset1
3356 // [call target1] | <-+
3357 // [IC cache] |- offset2
3358 // [call target2] <--+
3359 //
3360 // <<<< consts
3361 // >>>> insts
3362 //
3363 // bl offset16 -+ -+ ??? // How many bits available?
3364 // | |
3365 // <<<< insts | |
3366 // >>>> stubs | |
3367 // | |- trampoline_stub_Reloc
3368 // trampoline stub: | <-+
3369 // r2 = toc |
3370 // r2 = [r2 + offset1] | // Load call target1 from const section
3371 // mtctr r2 |
3372 // bctr |- static_stub_Reloc
3373 // comp_to_interp_stub: <---+
3374 // r1 = toc
3375 // ICreg = [r1 + IC_offset] // Load IC from const section
3376 // r1 = [r1 + offset2] // Load call target2 from const section
3377 // mtctr r1
3378 // bctr
3379 //
3380 // <<<< stubs
3381 //
3382 // The call instruction in the code either
3383 // - Branches directly to a compiled method if the offset is encodable in instruction.
3384 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3385 // - Branches to the compiled_to_interp stub if the target is interpreted.
3386 //
3387 // Further there are three relocations from the loads to the constants in
3388 // the constant section.
3389 //
3390 // Usage of r1 and r2 in the stubs allows to distinguish them.
3391 enc_class enc_java_static_call(method meth) %{
3392 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3393
3394 MacroAssembler _masm(&cbuf);
3395 address entry_point = (address)$meth$$method;
3396
3397 if (!_method) {
3398 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3399 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3400 } else {
3401 // Remember the offset not the address.
3402 const int start_offset = __ offset();
3403 // The trampoline stub.
3404 if (!Compile::current()->in_scratch_emit_size()) {
3405 // No entry point given, use the current pc.
3406 // Make sure branch fits into
3407 if (entry_point == 0) entry_point = __ pc();
3408
3409 // Put the entry point as a constant into the constant pool.
3410 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3411 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3412
3413 // Emit the trampoline stub which will be related to the branch-and-link below.
3414 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3415 if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3416 __ relocate(_optimized_virtual ?
3417 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3418 }
3419
3420 // The real call.
3421 // Note: At this point we do not have the address of the trampoline
3422 // stub, and the entry point might be too far away for bl, so __ pc()
3423 // serves as dummy and the bl will be patched later.
3424 cbuf.set_insts_mark();
3425 __ bl(__ pc()); // Emits a relocation.
3426
3427 // The stub for call to interpreter.
3428 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3429 if (stub == NULL) {
3430 ciEnv::current()->record_failure("CodeCache is full");
3431 return;
3432 }
3433 }
3434 %}
3435
3436 // Emit a method handle call.
3437 //
3438 // Method handle calls from compiled to compiled are going thru a
3439 // c2i -> i2c adapter, extending the frame for their arguments. The
3440 // caller however, returns directly to the compiled callee, that has
3441 // to cope with the extended frame. We restore the original frame by
3442 // loading the callers sp and adding the calculated framesize.
3443 enc_class enc_java_handle_call(method meth) %{
3444 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3445
3446 MacroAssembler _masm(&cbuf);
3447 address entry_point = (address)$meth$$method;
3448
3449 // Remember the offset not the address.
3450 const int start_offset = __ offset();
3451 // The trampoline stub.
3452 if (!ra_->C->in_scratch_emit_size()) {
3453 // No entry point given, use the current pc.
3454 // Make sure branch fits into
3455 if (entry_point == 0) entry_point = __ pc();
3456
3457 // Put the entry point as a constant into the constant pool.
3458 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3459 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3460
3461 // Emit the trampoline stub which will be related to the branch-and-link below.
3462 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3463 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3464 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3465 __ relocate(relocInfo::opt_virtual_call_type);
3466 }
3467
3468 // The real call.
3469 // Note: At this point we do not have the address of the trampoline
3470 // stub, and the entry point might be too far away for bl, so __ pc()
3471 // serves as dummy and the bl will be patched later.
3472 cbuf.set_insts_mark();
3473 __ bl(__ pc()); // Emits a relocation.
3474
3475 assert(_method, "execute next statement conditionally");
3476 // The stub for call to interpreter.
3477 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3478 if (stub == NULL) {
3479 ciEnv::current()->record_failure("CodeCache is full");
3480 return;
3481 }
3482
3483 // Restore original sp.
3484 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3485 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3486 unsigned int bytes = (unsigned int)framesize;
3487 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3488 if (Assembler::is_simm(-offset, 16)) {
3489 __ addi(R1_SP, R11_scratch1, -offset);
3490 } else {
3491 __ load_const_optimized(R12_scratch2, -offset);
3492 __ add(R1_SP, R11_scratch1, R12_scratch2);
3493 }
3494 #ifdef ASSERT
3495 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3496 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3497 __ asm_assert_eq("backlink changed", 0x8000);
3498 #endif
3499 // If fails should store backlink before unextending.
3500
3501 if (ra_->C->env()->failing()) {
3502 return;
3503 }
3504 %}
3505
3506 // Second node of expanded dynamic call - the call.
3507 enc_class enc_java_dynamic_call_sched(method meth) %{
3508 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3509
3510 MacroAssembler _masm(&cbuf);
3511
3512 if (!ra_->C->in_scratch_emit_size()) {
3513 // Create a call trampoline stub for the given method.
3514 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3515 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3516 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3517 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3518 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3519
3520 // Build relocation at call site with ic position as data.
3521 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3522 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3523 "must have one, but can't have both");
3524 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3525 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3526 "must contain instruction offset");
3527 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3528 ? _load_ic_hi_node->_cbuf_insts_offset
3529 : _load_ic_node->_cbuf_insts_offset;
3530 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3531 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3532 "should be load from TOC");
3533
3534 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3535 }
3536
3537 // At this point I do not have the address of the trampoline stub,
3538 // and the entry point might be too far away for bl. Pc() serves
3539 // as dummy and bl will be patched later.
3540 __ bl((address) __ pc());
3541 %}
3542
3543 // postalloc expand emitter for virtual calls.
3544 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3545
3546 // Create the nodes for loading the IC from the TOC.
3547 loadConLNodesTuple loadConLNodes_IC =
3548 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3549 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3550
3551 // Create the call node.
3552 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3553 call->_method_handle_invoke = _method_handle_invoke;
3554 call->_vtable_index = _vtable_index;
3555 call->_method = _method;
3556 call->_bci = _bci;
3557 call->_optimized_virtual = _optimized_virtual;
3558 call->_tf = _tf;
3559 call->_entry_point = _entry_point;
3560 call->_cnt = _cnt;
3561 call->_argsize = _argsize;
3562 call->_oop_map = _oop_map;
3563 call->_jvms = _jvms;
3564 call->_jvmadj = _jvmadj;
3565 call->_in_rms = _in_rms;
3566 call->_nesting = _nesting;
3567
3568 // New call needs all inputs of old call.
3569 // Req...
3570 for (uint i = 0; i < req(); ++i) {
3571 // The expanded node does not need toc any more.
3572 // Add the inline cache constant here instead. This expresses the
3573 // register of the inline cache must be live at the call.
3574 // Else we would have to adapt JVMState by -1.
3575 if (i == mach_constant_base_node_input()) {
3576 call->add_req(loadConLNodes_IC._last);
3577 } else {
3578 call->add_req(in(i));
3579 }
3580 }
3581 // ...as well as prec
3582 for (uint i = req(); i < len(); ++i) {
3583 call->add_prec(in(i));
3584 }
3585
3586 // Remember nodes loading the inline cache into r19.
3587 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3588 call->_load_ic_node = loadConLNodes_IC._small;
3589
3590 // Operands for new nodes.
3591 call->_opnds[0] = _opnds[0];
3592 call->_opnds[1] = _opnds[1];
3593
3594 // Only the inline cache is associated with a register.
3595 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3596
3597 // Push new nodes.
3598 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3599 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3600 nodes->push(call);
3601 %}
3602
3603 // Compound version of call dynamic
3604 // Toc is only passed so that it can be used in ins_encode statement.
3605 // In the code we have to use $constanttablebase.
3606 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3607 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3608 MacroAssembler _masm(&cbuf);
3609 int start_offset = __ offset();
3610
3611 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3612 #if 0
3613 int vtable_index = this->_vtable_index;
3614 if (_vtable_index < 0) {
3615 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3616 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3617 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3618
3619 // Virtual call relocation will point to ic load.
3620 address virtual_call_meta_addr = __ pc();
3621 // Load a clear inline cache.
3622 AddressLiteral empty_ic((address) Universe::non_oop_word());
3623 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3624 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3625 // to determine who we intended to call.
3626 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3627 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3628 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3629 "Fix constant in ret_addr_offset()");
3630 } else {
3631 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3632 // Go thru the vtable. Get receiver klass. Receiver already
3633 // checked for non-null. If we'll go thru a C2I adapter, the
3634 // interpreter expects method in R19_method.
3635
3636 __ load_klass(R11_scratch1, R3);
3637
3638 int entry_offset = in_bytes(InstanceKlass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes();
3639 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
3640 __ li(R19_method, v_off);
3641 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3642 // NOTE: for vtable dispatches, the vtable entry will never be
3643 // null. However it may very well end up in handle_wrong_method
3644 // if the method is abstract for the particular class.
3645 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3646 // Call target. Either compiled code or C2I adapter.
3647 __ mtctr(R11_scratch1);
3648 __ bctrl();
3649 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3650 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3651 }
3652 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3653 "Fix constant in ret_addr_offset()");
3654 }
3655 #endif
3656 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3657 %}
3658
3659 // a runtime call
3660 enc_class enc_java_to_runtime_call (method meth) %{
3661 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3662
3663 MacroAssembler _masm(&cbuf);
3664 const address start_pc = __ pc();
3665
3666 #if defined(ABI_ELFv2)
3667 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3668 __ call_c(entry, relocInfo::runtime_call_type);
3669 #else
3670 // The function we're going to call.
3671 FunctionDescriptor fdtemp;
3672 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3673
3674 Register Rtoc = R12_scratch2;
3675 // Calculate the method's TOC.
3676 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3677 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3678 // pool entries; call_c_using_toc will optimize the call.
3679 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3680 #endif
3681
3682 // Check the ret_addr_offset.
3683 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3684 "Fix constant in ret_addr_offset()");
3685 %}
3686
3687 // Move to ctr for leaf call.
3688 // This enc_class is needed so that scheduler gets proper
3689 // input mapping for latency computation.
3690 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3691 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3692 MacroAssembler _masm(&cbuf);
3693 __ mtctr($src$$Register);
3694 %}
3695
3696 // Postalloc expand emitter for runtime leaf calls.
3697 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3698 loadConLNodesTuple loadConLNodes_Entry;
3699 #if defined(ABI_ELFv2)
3700 jlong entry_address = (jlong) this->entry_point();
3701 assert(entry_address, "need address here");
3702 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3703 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3704 #else
3705 // Get the struct that describes the function we are about to call.
3706 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3707 assert(fd, "need fd here");
3708 jlong entry_address = (jlong) fd->entry();
3709 // new nodes
3710 loadConLNodesTuple loadConLNodes_Env;
3711 loadConLNodesTuple loadConLNodes_Toc;
3712
3713 // Create nodes and operands for loading the entry point.
3714 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3715 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3716
3717
3718 // Create nodes and operands for loading the env pointer.
3719 if (fd->env() != NULL) {
3720 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3721 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3722 } else {
3723 loadConLNodes_Env._large_hi = NULL;
3724 loadConLNodes_Env._large_lo = NULL;
3725 loadConLNodes_Env._small = NULL;
3726 loadConLNodes_Env._last = new loadConL16Node();
3727 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3728 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3729 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3730 }
3731
3732 // Create nodes and operands for loading the Toc point.
3733 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3734 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3735 #endif // ABI_ELFv2
3736 // mtctr node
3737 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3738
3739 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3740 mtctr->add_req(0, loadConLNodes_Entry._last);
3741
3742 mtctr->_opnds[0] = new iRegLdstOper();
3743 mtctr->_opnds[1] = new iRegLdstOper();
3744
3745 // call node
3746 MachCallLeafNode *call = new CallLeafDirectNode();
3747
3748 call->_opnds[0] = _opnds[0];
3749 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3750
3751 // Make the new call node look like the old one.
3752 call->_name = _name;
3753 call->_tf = _tf;
3754 call->_entry_point = _entry_point;
3755 call->_cnt = _cnt;
3756 call->_argsize = _argsize;
3757 call->_oop_map = _oop_map;
3758 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3759 call->_jvms = NULL;
3760 call->_jvmadj = _jvmadj;
3761 call->_in_rms = _in_rms;
3762 call->_nesting = _nesting;
3763
3764
3765 // New call needs all inputs of old call.
3766 // Req...
3767 for (uint i = 0; i < req(); ++i) {
3768 if (i != mach_constant_base_node_input()) {
3769 call->add_req(in(i));
3770 }
3771 }
3772
3773 // These must be reqired edges, as the registers are live up to
3774 // the call. Else the constants are handled as kills.
3775 call->add_req(mtctr);
3776 #if !defined(ABI_ELFv2)
3777 call->add_req(loadConLNodes_Env._last);
3778 call->add_req(loadConLNodes_Toc._last);
3779 #endif
3780
3781 // ...as well as prec
3782 for (uint i = req(); i < len(); ++i) {
3783 call->add_prec(in(i));
3784 }
3785
3786 // registers
3787 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3788
3789 // Insert the new nodes.
3790 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3791 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3792 #if !defined(ABI_ELFv2)
3793 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3794 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3795 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3796 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3797 #endif
3798 nodes->push(mtctr);
3799 nodes->push(call);
3800 %}
3801 %}
3802
3803 //----------FRAME--------------------------------------------------------------
3804 // Definition of frame structure and management information.
3805
3806 frame %{
3807 // What direction does stack grow in (assumed to be same for native & Java).
3808 stack_direction(TOWARDS_LOW);
3809
3810 // These two registers define part of the calling convention between
3811 // compiled code and the interpreter.
3812
3813 // Inline Cache Register or method for I2C.
3814 inline_cache_reg(R19); // R19_method
3815
3816 // Method Oop Register when calling interpreter.
3817 interpreter_method_oop_reg(R19); // R19_method
3818
3819 // Optional: name the operand used by cisc-spilling to access
3820 // [stack_pointer + offset].
3821 cisc_spilling_operand_name(indOffset);
3822
3823 // Number of stack slots consumed by a Monitor enter.
3824 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3825
3826 // Compiled code's Frame Pointer.
3827 frame_pointer(R1); // R1_SP
3828
3829 // Interpreter stores its frame pointer in a register which is
3830 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3831 // interpreted java to compiled java.
3832 //
3833 // R14_state holds pointer to caller's cInterpreter.
3834 interpreter_frame_pointer(R14); // R14_state
3835
3836 stack_alignment(frame::alignment_in_bytes);
3837
3838 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3839
3840 // Number of outgoing stack slots killed above the
3841 // out_preserve_stack_slots for calls to C. Supports the var-args
3842 // backing area for register parms.
3843 //
3844 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3845
3846 // The after-PROLOG location of the return address. Location of
3847 // return address specifies a type (REG or STACK) and a number
3848 // representing the register number (i.e. - use a register name) or
3849 // stack slot.
3850 //
3851 // A: Link register is stored in stack slot ...
3852 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3853 // J: Therefore, we make sure that the link register is also in R11_scratch1
3854 // at the end of the prolog.
3855 // B: We use R20, now.
3856 //return_addr(REG R20);
3857
3858 // G: After reading the comments made by all the luminaries on their
3859 // failure to tell the compiler where the return address really is,
3860 // I hardly dare to try myself. However, I'm convinced it's in slot
3861 // 4 what apparently works and saves us some spills.
3862 return_addr(STACK 4);
3863
3864 // This is the body of the function
3865 //
3866 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3867 // uint length, // length of array
3868 // bool is_outgoing)
3869 //
3870 // The `sig' array is to be updated. sig[j] represents the location
3871 // of the j-th argument, either a register or a stack slot.
3872
3873 // Comment taken from i486.ad:
3874 // Body of function which returns an integer array locating
3875 // arguments either in registers or in stack slots. Passed an array
3876 // of ideal registers called "sig" and a "length" count. Stack-slot
3877 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3878 // arguments for a CALLEE. Incoming stack arguments are
3879 // automatically biased by the preserve_stack_slots field above.
3880 calling_convention %{
3881 // No difference between ingoing/outgoing. Just pass false.
3882 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3883 %}
3884
3885 // Comment taken from i486.ad:
3886 // Body of function which returns an integer array locating
3887 // arguments either in registers or in stack slots. Passed an array
3888 // of ideal registers called "sig" and a "length" count. Stack-slot
3889 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3890 // arguments for a CALLEE. Incoming stack arguments are
3891 // automatically biased by the preserve_stack_slots field above.
3892 c_calling_convention %{
3893 // This is obviously always outgoing.
3894 // C argument in register AND stack slot.
3895 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3896 %}
3897
3898 // Location of native (C/C++) and interpreter return values. This
3899 // is specified to be the same as Java. In the 32-bit VM, long
3900 // values are actually returned from native calls in O0:O1 and
3901 // returned to the interpreter in I0:I1. The copying to and from
3902 // the register pairs is done by the appropriate call and epilog
3903 // opcodes. This simplifies the register allocator.
3904 c_return_value %{
3905 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3906 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3907 "only return normal values");
3908 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3909 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3910 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3911 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3912 %}
3913
3914 // Location of compiled Java return values. Same as C
3915 return_value %{
3916 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3917 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3918 "only return normal values");
3919 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3920 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3921 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3922 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3923 %}
3924 %}
3925
3926
3927 //----------ATTRIBUTES---------------------------------------------------------
3928
3929 //----------Operand Attributes-------------------------------------------------
3930 op_attrib op_cost(1); // Required cost attribute.
3931
3932 //----------Instruction Attributes---------------------------------------------
3933
3934 // Cost attribute. required.
3935 ins_attrib ins_cost(DEFAULT_COST);
3936
3937 // Is this instruction a non-matching short branch variant of some
3938 // long branch? Not required.
3939 ins_attrib ins_short_branch(0);
3940
3941 ins_attrib ins_is_TrapBasedCheckNode(true);
3942
3943 // Number of constants.
3944 // This instruction uses the given number of constants
3945 // (optional attribute).
3946 // This is needed to determine in time whether the constant pool will
3947 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3948 // is determined. It's also used to compute the constant pool size
3949 // in Output().
3950 ins_attrib ins_num_consts(0);
3951
3952 // Required alignment attribute (must be a power of 2) specifies the
3953 // alignment that some part of the instruction (not necessarily the
3954 // start) requires. If > 1, a compute_padding() function must be
3955 // provided for the instruction.
3956 ins_attrib ins_alignment(1);
3957
3958 // Enforce/prohibit rematerializations.
3959 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3960 // then rematerialization of that instruction is prohibited and the
3961 // instruction's value will be spilled if necessary.
3962 // Causes that MachNode::rematerialize() returns false.
3963 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3964 // then rematerialization should be enforced and a copy of the instruction
3965 // should be inserted if possible; rematerialization is not guaranteed.
3966 // Note: this may result in rematerializations in front of every use.
3967 // Causes that MachNode::rematerialize() can return true.
3968 // (optional attribute)
3969 ins_attrib ins_cannot_rematerialize(false);
3970 ins_attrib ins_should_rematerialize(false);
3971
3972 // Instruction has variable size depending on alignment.
3973 ins_attrib ins_variable_size_depending_on_alignment(false);
3974
3975 // Instruction is a nop.
3976 ins_attrib ins_is_nop(false);
3977
3978 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3979 ins_attrib ins_use_mach_if_fast_lock_node(false);
3980
3981 // Field for the toc offset of a constant.
3982 //
3983 // This is needed if the toc offset is not encodable as an immediate in
3984 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3985 // added to the toc, and from this a load with immediate is performed.
3986 // With postalloc expand, we get two nodes that require the same offset
3987 // but which don't know about each other. The offset is only known
3988 // when the constant is added to the constant pool during emitting.
3989 // It is generated in the 'hi'-node adding the upper bits, and saved
3990 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3991 // the offset from there when it gets encoded.
3992 ins_attrib ins_field_const_toc_offset(0);
3993 ins_attrib ins_field_const_toc_offset_hi_node(0);
3994
3995 // A field that can hold the instructions offset in the code buffer.
3996 // Set in the nodes emitter.
3997 ins_attrib ins_field_cbuf_insts_offset(-1);
3998
3999 // Fields for referencing a call's load-IC-node.
4000 // If the toc offset can not be encoded as an immediate in a load, we
4001 // use two nodes.
4002 ins_attrib ins_field_load_ic_hi_node(0);
4003 ins_attrib ins_field_load_ic_node(0);
4004
4005 //----------OPERANDS-----------------------------------------------------------
4006 // Operand definitions must precede instruction definitions for correct
4007 // parsing in the ADLC because operands constitute user defined types
4008 // which are used in instruction definitions.
4009 //
4010 // Formats are generated automatically for constants and base registers.
4011
4012 //----------Simple Operands----------------------------------------------------
4013 // Immediate Operands
4014
4015 // Integer Immediate: 32-bit
4016 operand immI() %{
4017 match(ConI);
4018 op_cost(40);
4019 format %{ %}
4020 interface(CONST_INTER);
4021 %}
4022
4023 operand immI8() %{
4024 predicate(Assembler::is_simm(n->get_int(), 8));
4025 op_cost(0);
4026 match(ConI);
4027 format %{ %}
4028 interface(CONST_INTER);
4029 %}
4030
4031 // Integer Immediate: 16-bit
4032 operand immI16() %{
4033 predicate(Assembler::is_simm(n->get_int(), 16));
4034 op_cost(0);
4035 match(ConI);
4036 format %{ %}
4037 interface(CONST_INTER);
4038 %}
4039
4040 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4041 operand immIhi16() %{
4042 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4043 match(ConI);
4044 op_cost(0);
4045 format %{ %}
4046 interface(CONST_INTER);
4047 %}
4048
4049 operand immInegpow2() %{
4050 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4051 match(ConI);
4052 op_cost(0);
4053 format %{ %}
4054 interface(CONST_INTER);
4055 %}
4056
4057 operand immIpow2minus1() %{
4058 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4059 match(ConI);
4060 op_cost(0);
4061 format %{ %}
4062 interface(CONST_INTER);
4063 %}
4064
4065 operand immIpowerOf2() %{
4066 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4067 match(ConI);
4068 op_cost(0);
4069 format %{ %}
4070 interface(CONST_INTER);
4071 %}
4072
4073 // Unsigned Integer Immediate: the values 0-31
4074 operand uimmI5() %{
4075 predicate(Assembler::is_uimm(n->get_int(), 5));
4076 match(ConI);
4077 op_cost(0);
4078 format %{ %}
4079 interface(CONST_INTER);
4080 %}
4081
4082 // Unsigned Integer Immediate: 6-bit
4083 operand uimmI6() %{
4084 predicate(Assembler::is_uimm(n->get_int(), 6));
4085 match(ConI);
4086 op_cost(0);
4087 format %{ %}
4088 interface(CONST_INTER);
4089 %}
4090
4091 // Unsigned Integer Immediate: 6-bit int, greater than 32
4092 operand uimmI6_ge32() %{
4093 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4094 match(ConI);
4095 op_cost(0);
4096 format %{ %}
4097 interface(CONST_INTER);
4098 %}
4099
4100 // Unsigned Integer Immediate: 15-bit
4101 operand uimmI15() %{
4102 predicate(Assembler::is_uimm(n->get_int(), 15));
4103 match(ConI);
4104 op_cost(0);
4105 format %{ %}
4106 interface(CONST_INTER);
4107 %}
4108
4109 // Unsigned Integer Immediate: 16-bit
4110 operand uimmI16() %{
4111 predicate(Assembler::is_uimm(n->get_int(), 16));
4112 match(ConI);
4113 op_cost(0);
4114 format %{ %}
4115 interface(CONST_INTER);
4116 %}
4117
4118 // constant 'int 0'.
4119 operand immI_0() %{
4120 predicate(n->get_int() == 0);
4121 match(ConI);
4122 op_cost(0);
4123 format %{ %}
4124 interface(CONST_INTER);
4125 %}
4126
4127 // constant 'int 1'.
4128 operand immI_1() %{
4129 predicate(n->get_int() == 1);
4130 match(ConI);
4131 op_cost(0);
4132 format %{ %}
4133 interface(CONST_INTER);
4134 %}
4135
4136 // constant 'int -1'.
4137 operand immI_minus1() %{
4138 predicate(n->get_int() == -1);
4139 match(ConI);
4140 op_cost(0);
4141 format %{ %}
4142 interface(CONST_INTER);
4143 %}
4144
4145 // int value 16.
4146 operand immI_16() %{
4147 predicate(n->get_int() == 16);
4148 match(ConI);
4149 op_cost(0);
4150 format %{ %}
4151 interface(CONST_INTER);
4152 %}
4153
4154 // int value 24.
4155 operand immI_24() %{
4156 predicate(n->get_int() == 24);
4157 match(ConI);
4158 op_cost(0);
4159 format %{ %}
4160 interface(CONST_INTER);
4161 %}
4162
4163 // Compressed oops constants
4164 // Pointer Immediate
4165 operand immN() %{
4166 match(ConN);
4167
4168 op_cost(10);
4169 format %{ %}
4170 interface(CONST_INTER);
4171 %}
4172
4173 // NULL Pointer Immediate
4174 operand immN_0() %{
4175 predicate(n->get_narrowcon() == 0);
4176 match(ConN);
4177
4178 op_cost(0);
4179 format %{ %}
4180 interface(CONST_INTER);
4181 %}
4182
4183 // Compressed klass constants
4184 operand immNKlass() %{
4185 match(ConNKlass);
4186
4187 op_cost(0);
4188 format %{ %}
4189 interface(CONST_INTER);
4190 %}
4191
4192 // This operand can be used to avoid matching of an instruct
4193 // with chain rule.
4194 operand immNKlass_NM() %{
4195 match(ConNKlass);
4196 predicate(false);
4197 op_cost(0);
4198 format %{ %}
4199 interface(CONST_INTER);
4200 %}
4201
4202 // Pointer Immediate: 64-bit
4203 operand immP() %{
4204 match(ConP);
4205 op_cost(0);
4206 format %{ %}
4207 interface(CONST_INTER);
4208 %}
4209
4210 // Operand to avoid match of loadConP.
4211 // This operand can be used to avoid matching of an instruct
4212 // with chain rule.
4213 operand immP_NM() %{
4214 match(ConP);
4215 predicate(false);
4216 op_cost(0);
4217 format %{ %}
4218 interface(CONST_INTER);
4219 %}
4220
4221 // costant 'pointer 0'.
4222 operand immP_0() %{
4223 predicate(n->get_ptr() == 0);
4224 match(ConP);
4225 op_cost(0);
4226 format %{ %}
4227 interface(CONST_INTER);
4228 %}
4229
4230 // pointer 0x0 or 0x1
4231 operand immP_0or1() %{
4232 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4233 match(ConP);
4234 op_cost(0);
4235 format %{ %}
4236 interface(CONST_INTER);
4237 %}
4238
4239 operand immL() %{
4240 match(ConL);
4241 op_cost(40);
4242 format %{ %}
4243 interface(CONST_INTER);
4244 %}
4245
4246 // Long Immediate: 16-bit
4247 operand immL16() %{
4248 predicate(Assembler::is_simm(n->get_long(), 16));
4249 match(ConL);
4250 op_cost(0);
4251 format %{ %}
4252 interface(CONST_INTER);
4253 %}
4254
4255 // Long Immediate: 16-bit, 4-aligned
4256 operand immL16Alg4() %{
4257 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4258 match(ConL);
4259 op_cost(0);
4260 format %{ %}
4261 interface(CONST_INTER);
4262 %}
4263
4264 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4265 operand immL32hi16() %{
4266 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4267 match(ConL);
4268 op_cost(0);
4269 format %{ %}
4270 interface(CONST_INTER);
4271 %}
4272
4273 // Long Immediate: 32-bit
4274 operand immL32() %{
4275 predicate(Assembler::is_simm(n->get_long(), 32));
4276 match(ConL);
4277 op_cost(0);
4278 format %{ %}
4279 interface(CONST_INTER);
4280 %}
4281
4282 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4283 operand immLhighest16() %{
4284 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4285 match(ConL);
4286 op_cost(0);
4287 format %{ %}
4288 interface(CONST_INTER);
4289 %}
4290
4291 operand immLnegpow2() %{
4292 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4293 match(ConL);
4294 op_cost(0);
4295 format %{ %}
4296 interface(CONST_INTER);
4297 %}
4298
4299 operand immLpow2minus1() %{
4300 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4301 (n->get_long() != (jlong)0xffffffffffffffffL));
4302 match(ConL);
4303 op_cost(0);
4304 format %{ %}
4305 interface(CONST_INTER);
4306 %}
4307
4308 // constant 'long 0'.
4309 operand immL_0() %{
4310 predicate(n->get_long() == 0L);
4311 match(ConL);
4312 op_cost(0);
4313 format %{ %}
4314 interface(CONST_INTER);
4315 %}
4316
4317 // constat ' long -1'.
4318 operand immL_minus1() %{
4319 predicate(n->get_long() == -1L);
4320 match(ConL);
4321 op_cost(0);
4322 format %{ %}
4323 interface(CONST_INTER);
4324 %}
4325
4326 // Long Immediate: low 32-bit mask
4327 operand immL_32bits() %{
4328 predicate(n->get_long() == 0xFFFFFFFFL);
4329 match(ConL);
4330 op_cost(0);
4331 format %{ %}
4332 interface(CONST_INTER);
4333 %}
4334
4335 // Unsigned Long Immediate: 16-bit
4336 operand uimmL16() %{
4337 predicate(Assembler::is_uimm(n->get_long(), 16));
4338 match(ConL);
4339 op_cost(0);
4340 format %{ %}
4341 interface(CONST_INTER);
4342 %}
4343
4344 // Float Immediate
4345 operand immF() %{
4346 match(ConF);
4347 op_cost(40);
4348 format %{ %}
4349 interface(CONST_INTER);
4350 %}
4351
4352 // Float Immediate: +0.0f.
4353 operand immF_0() %{
4354 predicate(jint_cast(n->getf()) == 0);
4355 match(ConF);
4356
4357 op_cost(0);
4358 format %{ %}
4359 interface(CONST_INTER);
4360 %}
4361
4362 // Double Immediate
4363 operand immD() %{
4364 match(ConD);
4365 op_cost(40);
4366 format %{ %}
4367 interface(CONST_INTER);
4368 %}
4369
4370 // Integer Register Operands
4371 // Integer Destination Register
4372 // See definition of reg_class bits32_reg_rw.
4373 operand iRegIdst() %{
4374 constraint(ALLOC_IN_RC(bits32_reg_rw));
4375 match(RegI);
4376 match(rscratch1RegI);
4377 match(rscratch2RegI);
4378 match(rarg1RegI);
4379 match(rarg2RegI);
4380 match(rarg3RegI);
4381 match(rarg4RegI);
4382 format %{ %}
4383 interface(REG_INTER);
4384 %}
4385
4386 // Integer Source Register
4387 // See definition of reg_class bits32_reg_ro.
4388 operand iRegIsrc() %{
4389 constraint(ALLOC_IN_RC(bits32_reg_ro));
4390 match(RegI);
4391 match(rscratch1RegI);
4392 match(rscratch2RegI);
4393 match(rarg1RegI);
4394 match(rarg2RegI);
4395 match(rarg3RegI);
4396 match(rarg4RegI);
4397 format %{ %}
4398 interface(REG_INTER);
4399 %}
4400
4401 operand rscratch1RegI() %{
4402 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4403 match(iRegIdst);
4404 format %{ %}
4405 interface(REG_INTER);
4406 %}
4407
4408 operand rscratch2RegI() %{
4409 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4410 match(iRegIdst);
4411 format %{ %}
4412 interface(REG_INTER);
4413 %}
4414
4415 operand rarg1RegI() %{
4416 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4417 match(iRegIdst);
4418 format %{ %}
4419 interface(REG_INTER);
4420 %}
4421
4422 operand rarg2RegI() %{
4423 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4424 match(iRegIdst);
4425 format %{ %}
4426 interface(REG_INTER);
4427 %}
4428
4429 operand rarg3RegI() %{
4430 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4431 match(iRegIdst);
4432 format %{ %}
4433 interface(REG_INTER);
4434 %}
4435
4436 operand rarg4RegI() %{
4437 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4438 match(iRegIdst);
4439 format %{ %}
4440 interface(REG_INTER);
4441 %}
4442
4443 operand rarg1RegL() %{
4444 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4445 match(iRegLdst);
4446 format %{ %}
4447 interface(REG_INTER);
4448 %}
4449
4450 operand rarg2RegL() %{
4451 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4452 match(iRegLdst);
4453 format %{ %}
4454 interface(REG_INTER);
4455 %}
4456
4457 operand rarg3RegL() %{
4458 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4459 match(iRegLdst);
4460 format %{ %}
4461 interface(REG_INTER);
4462 %}
4463
4464 operand rarg4RegL() %{
4465 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4466 match(iRegLdst);
4467 format %{ %}
4468 interface(REG_INTER);
4469 %}
4470
4471 // Pointer Destination Register
4472 // See definition of reg_class bits64_reg_rw.
4473 operand iRegPdst() %{
4474 constraint(ALLOC_IN_RC(bits64_reg_rw));
4475 match(RegP);
4476 match(rscratch1RegP);
4477 match(rscratch2RegP);
4478 match(rarg1RegP);
4479 match(rarg2RegP);
4480 match(rarg3RegP);
4481 match(rarg4RegP);
4482 format %{ %}
4483 interface(REG_INTER);
4484 %}
4485
4486 // Pointer Destination Register
4487 // Operand not using r11 and r12 (killed in epilog).
4488 operand iRegPdstNoScratch() %{
4489 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4490 match(RegP);
4491 match(rarg1RegP);
4492 match(rarg2RegP);
4493 match(rarg3RegP);
4494 match(rarg4RegP);
4495 format %{ %}
4496 interface(REG_INTER);
4497 %}
4498
4499 // Pointer Source Register
4500 // See definition of reg_class bits64_reg_ro.
4501 operand iRegPsrc() %{
4502 constraint(ALLOC_IN_RC(bits64_reg_ro));
4503 match(RegP);
4504 match(iRegPdst);
4505 match(rscratch1RegP);
4506 match(rscratch2RegP);
4507 match(rarg1RegP);
4508 match(rarg2RegP);
4509 match(rarg3RegP);
4510 match(rarg4RegP);
4511 match(threadRegP);
4512 format %{ %}
4513 interface(REG_INTER);
4514 %}
4515
4516 // Thread operand.
4517 operand threadRegP() %{
4518 constraint(ALLOC_IN_RC(thread_bits64_reg));
4519 match(iRegPdst);
4520 format %{ "R16" %}
4521 interface(REG_INTER);
4522 %}
4523
4524 operand rscratch1RegP() %{
4525 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4526 match(iRegPdst);
4527 format %{ "R11" %}
4528 interface(REG_INTER);
4529 %}
4530
4531 operand rscratch2RegP() %{
4532 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4533 match(iRegPdst);
4534 format %{ %}
4535 interface(REG_INTER);
4536 %}
4537
4538 operand rarg1RegP() %{
4539 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4540 match(iRegPdst);
4541 format %{ %}
4542 interface(REG_INTER);
4543 %}
4544
4545 operand rarg2RegP() %{
4546 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4547 match(iRegPdst);
4548 format %{ %}
4549 interface(REG_INTER);
4550 %}
4551
4552 operand rarg3RegP() %{
4553 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4554 match(iRegPdst);
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4558
4559 operand rarg4RegP() %{
4560 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4561 match(iRegPdst);
4562 format %{ %}
4563 interface(REG_INTER);
4564 %}
4565
4566 operand iRegNsrc() %{
4567 constraint(ALLOC_IN_RC(bits32_reg_ro));
4568 match(RegN);
4569 match(iRegNdst);
4570
4571 format %{ %}
4572 interface(REG_INTER);
4573 %}
4574
4575 operand iRegNdst() %{
4576 constraint(ALLOC_IN_RC(bits32_reg_rw));
4577 match(RegN);
4578
4579 format %{ %}
4580 interface(REG_INTER);
4581 %}
4582
4583 // Long Destination Register
4584 // See definition of reg_class bits64_reg_rw.
4585 operand iRegLdst() %{
4586 constraint(ALLOC_IN_RC(bits64_reg_rw));
4587 match(RegL);
4588 match(rscratch1RegL);
4589 match(rscratch2RegL);
4590 format %{ %}
4591 interface(REG_INTER);
4592 %}
4593
4594 // Long Source Register
4595 // See definition of reg_class bits64_reg_ro.
4596 operand iRegLsrc() %{
4597 constraint(ALLOC_IN_RC(bits64_reg_ro));
4598 match(RegL);
4599 match(iRegLdst);
4600 match(rscratch1RegL);
4601 match(rscratch2RegL);
4602 format %{ %}
4603 interface(REG_INTER);
4604 %}
4605
4606 // Special operand for ConvL2I.
4607 operand iRegL2Isrc(iRegLsrc reg) %{
4608 constraint(ALLOC_IN_RC(bits64_reg_ro));
4609 match(ConvL2I reg);
4610 format %{ "ConvL2I($reg)" %}
4611 interface(REG_INTER)
4612 %}
4613
4614 operand rscratch1RegL() %{
4615 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4616 match(RegL);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4620
4621 operand rscratch2RegL() %{
4622 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4623 match(RegL);
4624 format %{ %}
4625 interface(REG_INTER);
4626 %}
4627
4628 // Condition Code Flag Registers
4629 operand flagsReg() %{
4630 constraint(ALLOC_IN_RC(int_flags));
4631 match(RegFlags);
4632 format %{ %}
4633 interface(REG_INTER);
4634 %}
4635
4636 operand flagsRegSrc() %{
4637 constraint(ALLOC_IN_RC(int_flags_ro));
4638 match(RegFlags);
4639 match(flagsReg);
4640 match(flagsRegCR0);
4641 format %{ %}
4642 interface(REG_INTER);
4643 %}
4644
4645 // Condition Code Flag Register CR0
4646 operand flagsRegCR0() %{
4647 constraint(ALLOC_IN_RC(int_flags_CR0));
4648 match(RegFlags);
4649 format %{ "CR0" %}
4650 interface(REG_INTER);
4651 %}
4652
4653 operand flagsRegCR1() %{
4654 constraint(ALLOC_IN_RC(int_flags_CR1));
4655 match(RegFlags);
4656 format %{ "CR1" %}
4657 interface(REG_INTER);
4658 %}
4659
4660 operand flagsRegCR6() %{
4661 constraint(ALLOC_IN_RC(int_flags_CR6));
4662 match(RegFlags);
4663 format %{ "CR6" %}
4664 interface(REG_INTER);
4665 %}
4666
4667 operand regCTR() %{
4668 constraint(ALLOC_IN_RC(ctr_reg));
4669 // RegFlags should work. Introducing a RegSpecial type would cause a
4670 // lot of changes.
4671 match(RegFlags);
4672 format %{"SR_CTR" %}
4673 interface(REG_INTER);
4674 %}
4675
4676 operand regD() %{
4677 constraint(ALLOC_IN_RC(dbl_reg));
4678 match(RegD);
4679 format %{ %}
4680 interface(REG_INTER);
4681 %}
4682
4683 operand regF() %{
4684 constraint(ALLOC_IN_RC(flt_reg));
4685 match(RegF);
4686 format %{ %}
4687 interface(REG_INTER);
4688 %}
4689
4690 // Special Registers
4691
4692 // Method Register
4693 operand inline_cache_regP(iRegPdst reg) %{
4694 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4695 match(reg);
4696 format %{ %}
4697 interface(REG_INTER);
4698 %}
4699
4700 operand compiler_method_oop_regP(iRegPdst reg) %{
4701 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4702 match(reg);
4703 format %{ %}
4704 interface(REG_INTER);
4705 %}
4706
4707 operand interpreter_method_oop_regP(iRegPdst reg) %{
4708 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4709 match(reg);
4710 format %{ %}
4711 interface(REG_INTER);
4712 %}
4713
4714 // Operands to remove register moves in unscaled mode.
4715 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4716 operand iRegP2N(iRegPsrc reg) %{
4717 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4718 constraint(ALLOC_IN_RC(bits64_reg_ro));
4719 match(EncodeP reg);
4720 format %{ "$reg" %}
4721 interface(REG_INTER)
4722 %}
4723
4724 operand iRegN2P(iRegNsrc reg) %{
4725 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4726 constraint(ALLOC_IN_RC(bits32_reg_ro));
4727 match(DecodeN reg);
4728 format %{ "$reg" %}
4729 interface(REG_INTER)
4730 %}
4731
4732 operand iRegN2P_klass(iRegNsrc reg) %{
4733 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4734 constraint(ALLOC_IN_RC(bits32_reg_ro));
4735 match(DecodeNKlass reg);
4736 format %{ "$reg" %}
4737 interface(REG_INTER)
4738 %}
4739
4740 //----------Complex Operands---------------------------------------------------
4741 // Indirect Memory Reference
4742 operand indirect(iRegPsrc reg) %{
4743 constraint(ALLOC_IN_RC(bits64_reg_ro));
4744 match(reg);
4745 op_cost(100);
4746 format %{ "[$reg]" %}
4747 interface(MEMORY_INTER) %{
4748 base($reg);
4749 index(0x0);
4750 scale(0x0);
4751 disp(0x0);
4752 %}
4753 %}
4754
4755 // Indirect with Offset
4756 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4757 constraint(ALLOC_IN_RC(bits64_reg_ro));
4758 match(AddP reg offset);
4759 op_cost(100);
4760 format %{ "[$reg + $offset]" %}
4761 interface(MEMORY_INTER) %{
4762 base($reg);
4763 index(0x0);
4764 scale(0x0);
4765 disp($offset);
4766 %}
4767 %}
4768
4769 // Indirect with 4-aligned Offset
4770 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4771 constraint(ALLOC_IN_RC(bits64_reg_ro));
4772 match(AddP reg offset);
4773 op_cost(100);
4774 format %{ "[$reg + $offset]" %}
4775 interface(MEMORY_INTER) %{
4776 base($reg);
4777 index(0x0);
4778 scale(0x0);
4779 disp($offset);
4780 %}
4781 %}
4782
4783 //----------Complex Operands for Compressed OOPs-------------------------------
4784 // Compressed OOPs with narrow_oop_shift == 0.
4785
4786 // Indirect Memory Reference, compressed OOP
4787 operand indirectNarrow(iRegNsrc reg) %{
4788 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4789 constraint(ALLOC_IN_RC(bits64_reg_ro));
4790 match(DecodeN reg);
4791 op_cost(100);
4792 format %{ "[$reg]" %}
4793 interface(MEMORY_INTER) %{
4794 base($reg);
4795 index(0x0);
4796 scale(0x0);
4797 disp(0x0);
4798 %}
4799 %}
4800
4801 operand indirectNarrow_klass(iRegNsrc reg) %{
4802 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4803 constraint(ALLOC_IN_RC(bits64_reg_ro));
4804 match(DecodeNKlass reg);
4805 op_cost(100);
4806 format %{ "[$reg]" %}
4807 interface(MEMORY_INTER) %{
4808 base($reg);
4809 index(0x0);
4810 scale(0x0);
4811 disp(0x0);
4812 %}
4813 %}
4814
4815 // Indirect with Offset, compressed OOP
4816 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4817 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4818 constraint(ALLOC_IN_RC(bits64_reg_ro));
4819 match(AddP (DecodeN reg) offset);
4820 op_cost(100);
4821 format %{ "[$reg + $offset]" %}
4822 interface(MEMORY_INTER) %{
4823 base($reg);
4824 index(0x0);
4825 scale(0x0);
4826 disp($offset);
4827 %}
4828 %}
4829
4830 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4831 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4832 constraint(ALLOC_IN_RC(bits64_reg_ro));
4833 match(AddP (DecodeNKlass reg) offset);
4834 op_cost(100);
4835 format %{ "[$reg + $offset]" %}
4836 interface(MEMORY_INTER) %{
4837 base($reg);
4838 index(0x0);
4839 scale(0x0);
4840 disp($offset);
4841 %}
4842 %}
4843
4844 // Indirect with 4-aligned Offset, compressed OOP
4845 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4846 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4847 constraint(ALLOC_IN_RC(bits64_reg_ro));
4848 match(AddP (DecodeN reg) offset);
4849 op_cost(100);
4850 format %{ "[$reg + $offset]" %}
4851 interface(MEMORY_INTER) %{
4852 base($reg);
4853 index(0x0);
4854 scale(0x0);
4855 disp($offset);
4856 %}
4857 %}
4858
4859 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4860 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4861 constraint(ALLOC_IN_RC(bits64_reg_ro));
4862 match(AddP (DecodeNKlass reg) offset);
4863 op_cost(100);
4864 format %{ "[$reg + $offset]" %}
4865 interface(MEMORY_INTER) %{
4866 base($reg);
4867 index(0x0);
4868 scale(0x0);
4869 disp($offset);
4870 %}
4871 %}
4872
4873 //----------Special Memory Operands--------------------------------------------
4874 // Stack Slot Operand
4875 //
4876 // This operand is used for loading and storing temporary values on
4877 // the stack where a match requires a value to flow through memory.
4878 operand stackSlotI(sRegI reg) %{
4879 constraint(ALLOC_IN_RC(stack_slots));
4880 op_cost(100);
4881 //match(RegI);
4882 format %{ "[sp+$reg]" %}
4883 interface(MEMORY_INTER) %{
4884 base(0x1); // R1_SP
4885 index(0x0);
4886 scale(0x0);
4887 disp($reg); // Stack Offset
4888 %}
4889 %}
4890
4891 operand stackSlotL(sRegL reg) %{
4892 constraint(ALLOC_IN_RC(stack_slots));
4893 op_cost(100);
4894 //match(RegL);
4895 format %{ "[sp+$reg]" %}
4896 interface(MEMORY_INTER) %{
4897 base(0x1); // R1_SP
4898 index(0x0);
4899 scale(0x0);
4900 disp($reg); // Stack Offset
4901 %}
4902 %}
4903
4904 operand stackSlotP(sRegP reg) %{
4905 constraint(ALLOC_IN_RC(stack_slots));
4906 op_cost(100);
4907 //match(RegP);
4908 format %{ "[sp+$reg]" %}
4909 interface(MEMORY_INTER) %{
4910 base(0x1); // R1_SP
4911 index(0x0);
4912 scale(0x0);
4913 disp($reg); // Stack Offset
4914 %}
4915 %}
4916
4917 operand stackSlotF(sRegF reg) %{
4918 constraint(ALLOC_IN_RC(stack_slots));
4919 op_cost(100);
4920 //match(RegF);
4921 format %{ "[sp+$reg]" %}
4922 interface(MEMORY_INTER) %{
4923 base(0x1); // R1_SP
4924 index(0x0);
4925 scale(0x0);
4926 disp($reg); // Stack Offset
4927 %}
4928 %}
4929
4930 operand stackSlotD(sRegD reg) %{
4931 constraint(ALLOC_IN_RC(stack_slots));
4932 op_cost(100);
4933 //match(RegD);
4934 format %{ "[sp+$reg]" %}
4935 interface(MEMORY_INTER) %{
4936 base(0x1); // R1_SP
4937 index(0x0);
4938 scale(0x0);
4939 disp($reg); // Stack Offset
4940 %}
4941 %}
4942
4943 // Operands for expressing Control Flow
4944 // NOTE: Label is a predefined operand which should not be redefined in
4945 // the AD file. It is generically handled within the ADLC.
4946
4947 //----------Conditional Branch Operands----------------------------------------
4948 // Comparison Op
4949 //
4950 // This is the operation of the comparison, and is limited to the
4951 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4952 // (!=).
4953 //
4954 // Other attributes of the comparison, such as unsignedness, are specified
4955 // by the comparison instruction that sets a condition code flags register.
4956 // That result is represented by a flags operand whose subtype is appropriate
4957 // to the unsignedness (etc.) of the comparison.
4958 //
4959 // Later, the instruction which matches both the Comparison Op (a Bool) and
4960 // the flags (produced by the Cmp) specifies the coding of the comparison op
4961 // by matching a specific subtype of Bool operand below.
4962
4963 // When used for floating point comparisons: unordered same as less.
4964 operand cmpOp() %{
4965 match(Bool);
4966 format %{ "" %}
4967 interface(COND_INTER) %{
4968 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4969 // BO & BI
4970 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4971 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4972 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4973 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4974 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4975 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4976 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4977 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4978 %}
4979 %}
4980
4981 //----------OPERAND CLASSES----------------------------------------------------
4982 // Operand Classes are groups of operands that are used to simplify
4983 // instruction definitions by not requiring the AD writer to specify
4984 // seperate instructions for every form of operand when the
4985 // instruction accepts multiple operand types with the same basic
4986 // encoding and format. The classic case of this is memory operands.
4987 // Indirect is not included since its use is limited to Compare & Swap.
4988
4989 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4990 // Memory operand where offsets are 4-aligned. Required for ld, std.
4991 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4992 opclass indirectMemory(indirect, indirectNarrow);
4993
4994 // Special opclass for I and ConvL2I.
4995 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4996
4997 // Operand classes to match encode and decode. iRegN_P2N is only used
4998 // for storeN. I have never seen an encode node elsewhere.
4999 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5000 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
5001
5002 //----------PIPELINE-----------------------------------------------------------
5003
5004 pipeline %{
5005
5006 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5007 // J. Res. & Dev., No. 1, Jan. 2002.
5008
5009 //----------ATTRIBUTES---------------------------------------------------------
5010 attributes %{
5011
5012 // Power4 instructions are of fixed length.
5013 fixed_size_instructions;
5014
5015 // TODO: if `bundle' means number of instructions fetched
5016 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5017 // max instructions issued per cycle, this is 5.
5018 max_instructions_per_bundle = 8;
5019
5020 // A Power4 instruction is 4 bytes long.
5021 instruction_unit_size = 4;
5022
5023 // The Power4 processor fetches 64 bytes...
5024 instruction_fetch_unit_size = 64;
5025
5026 // ...in one line
5027 instruction_fetch_units = 1
5028
5029 // Unused, list one so that array generated by adlc is not empty.
5030 // Aix compiler chokes if _nop_count = 0.
5031 nops(fxNop);
5032 %}
5033
5034 //----------RESOURCES----------------------------------------------------------
5035 // Resources are the functional units available to the machine
5036 resources(
5037 PPC_BR, // branch unit
5038 PPC_CR, // condition unit
5039 PPC_FX1, // integer arithmetic unit 1
5040 PPC_FX2, // integer arithmetic unit 2
5041 PPC_LDST1, // load/store unit 1
5042 PPC_LDST2, // load/store unit 2
5043 PPC_FP1, // float arithmetic unit 1
5044 PPC_FP2, // float arithmetic unit 2
5045 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5046 PPC_FX = PPC_FX1 | PPC_FX2,
5047 PPC_FP = PPC_FP1 | PPC_FP2
5048 );
5049
5050 //----------PIPELINE DESCRIPTION-----------------------------------------------
5051 // Pipeline Description specifies the stages in the machine's pipeline
5052 pipe_desc(
5053 // Power4 longest pipeline path
5054 PPC_IF, // instruction fetch
5055 PPC_IC,
5056 //PPC_BP, // branch prediction
5057 PPC_D0, // decode
5058 PPC_D1, // decode
5059 PPC_D2, // decode
5060 PPC_D3, // decode
5061 PPC_Xfer1,
5062 PPC_GD, // group definition
5063 PPC_MP, // map
5064 PPC_ISS, // issue
5065 PPC_RF, // resource fetch
5066 PPC_EX1, // execute (all units)
5067 PPC_EX2, // execute (FP, LDST)
5068 PPC_EX3, // execute (FP, LDST)
5069 PPC_EX4, // execute (FP)
5070 PPC_EX5, // execute (FP)
5071 PPC_EX6, // execute (FP)
5072 PPC_WB, // write back
5073 PPC_Xfer2,
5074 PPC_CP
5075 );
5076
5077 //----------PIPELINE CLASSES---------------------------------------------------
5078 // Pipeline Classes describe the stages in which input and output are
5079 // referenced by the hardware pipeline.
5080
5081 // Simple pipeline classes.
5082
5083 // Default pipeline class.
5084 pipe_class pipe_class_default() %{
5085 single_instruction;
5086 fixed_latency(2);
5087 %}
5088
5089 // Pipeline class for empty instructions.
5090 pipe_class pipe_class_empty() %{
5091 single_instruction;
5092 fixed_latency(0);
5093 %}
5094
5095 // Pipeline class for compares.
5096 pipe_class pipe_class_compare() %{
5097 single_instruction;
5098 fixed_latency(16);
5099 %}
5100
5101 // Pipeline class for traps.
5102 pipe_class pipe_class_trap() %{
5103 single_instruction;
5104 fixed_latency(100);
5105 %}
5106
5107 // Pipeline class for memory operations.
5108 pipe_class pipe_class_memory() %{
5109 single_instruction;
5110 fixed_latency(16);
5111 %}
5112
5113 // Pipeline class for call.
5114 pipe_class pipe_class_call() %{
5115 single_instruction;
5116 fixed_latency(100);
5117 %}
5118
5119 // Define the class for the Nop node.
5120 define %{
5121 MachNop = pipe_class_default;
5122 %}
5123
5124 %}
5125
5126 //----------INSTRUCTIONS-------------------------------------------------------
5127
5128 // Naming of instructions:
5129 // opA_operB / opA_operB_operC:
5130 // Operation 'op' with one or two source operands 'oper'. Result
5131 // type is A, source operand types are B and C.
5132 // Iff A == B == C, B and C are left out.
5133 //
5134 // The instructions are ordered according to the following scheme:
5135 // - loads
5136 // - load constants
5137 // - prefetch
5138 // - store
5139 // - encode/decode
5140 // - membar
5141 // - conditional moves
5142 // - compare & swap
5143 // - arithmetic and logic operations
5144 // * int: Add, Sub, Mul, Div, Mod
5145 // * int: lShift, arShift, urShift, rot
5146 // * float: Add, Sub, Mul, Div
5147 // * and, or, xor ...
5148 // - register moves: float <-> int, reg <-> stack, repl
5149 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5150 // - conv (low level type cast requiring bit changes (sign extend etc)
5151 // - compares, range & zero checks.
5152 // - branches
5153 // - complex operations, intrinsics, min, max, replicate
5154 // - lock
5155 // - Calls
5156 //
5157 // If there are similar instructions with different types they are sorted:
5158 // int before float
5159 // small before big
5160 // signed before unsigned
5161 // e.g., loadS before loadUS before loadI before loadF.
5162
5163
5164 //----------Load/Store Instructions--------------------------------------------
5165
5166 //----------Load Instructions--------------------------------------------------
5167
5168 // Converts byte to int.
5169 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5170 // reuses the 'amount' operand, but adlc expects that operand specification
5171 // and operands in match rule are equivalent.
5172 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5173 effect(DEF dst, USE src);
5174 format %{ "EXTSB $dst, $src \t// byte->int" %}
5175 size(4);
5176 ins_encode %{
5177 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5178 __ extsb($dst$$Register, $src$$Register);
5179 %}
5180 ins_pipe(pipe_class_default);
5181 %}
5182
5183 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5184 // match-rule, false predicate
5185 match(Set dst (LoadB mem));
5186 predicate(false);
5187
5188 format %{ "LBZ $dst, $mem" %}
5189 size(4);
5190 ins_encode( enc_lbz(dst, mem) );
5191 ins_pipe(pipe_class_memory);
5192 %}
5193
5194 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5195 // match-rule, false predicate
5196 match(Set dst (LoadB mem));
5197 predicate(false);
5198
5199 format %{ "LBZ $dst, $mem\n\t"
5200 "TWI $dst\n\t"
5201 "ISYNC" %}
5202 size(12);
5203 ins_encode( enc_lbz_ac(dst, mem) );
5204 ins_pipe(pipe_class_memory);
5205 %}
5206
5207 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5208 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5209 match(Set dst (LoadB mem));
5210 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5211 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5212 expand %{
5213 iRegIdst tmp;
5214 loadUB_indirect(tmp, mem);
5215 convB2I_reg_2(dst, tmp);
5216 %}
5217 %}
5218
5219 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5220 match(Set dst (LoadB mem));
5221 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5222 expand %{
5223 iRegIdst tmp;
5224 loadUB_indirect_ac(tmp, mem);
5225 convB2I_reg_2(dst, tmp);
5226 %}
5227 %}
5228
5229 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5230 // match-rule, false predicate
5231 match(Set dst (LoadB mem));
5232 predicate(false);
5233
5234 format %{ "LBZ $dst, $mem" %}
5235 size(4);
5236 ins_encode( enc_lbz(dst, mem) );
5237 ins_pipe(pipe_class_memory);
5238 %}
5239
5240 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5241 // match-rule, false predicate
5242 match(Set dst (LoadB mem));
5243 predicate(false);
5244
5245 format %{ "LBZ $dst, $mem\n\t"
5246 "TWI $dst\n\t"
5247 "ISYNC" %}
5248 size(12);
5249 ins_encode( enc_lbz_ac(dst, mem) );
5250 ins_pipe(pipe_class_memory);
5251 %}
5252
5253 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5254 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5255 match(Set dst (LoadB mem));
5256 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5257 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5258
5259 expand %{
5260 iRegIdst tmp;
5261 loadUB_indOffset16(tmp, mem);
5262 convB2I_reg_2(dst, tmp);
5263 %}
5264 %}
5265
5266 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5267 match(Set dst (LoadB mem));
5268 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5269
5270 expand %{
5271 iRegIdst tmp;
5272 loadUB_indOffset16_ac(tmp, mem);
5273 convB2I_reg_2(dst, tmp);
5274 %}
5275 %}
5276
5277 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5278 instruct loadUB(iRegIdst dst, memory mem) %{
5279 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5280 match(Set dst (LoadUB mem));
5281 ins_cost(MEMORY_REF_COST);
5282
5283 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5284 size(4);
5285 ins_encode( enc_lbz(dst, mem) );
5286 ins_pipe(pipe_class_memory);
5287 %}
5288
5289 // Load Unsigned Byte (8bit UNsigned) acquire.
5290 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5291 match(Set dst (LoadUB mem));
5292 ins_cost(3*MEMORY_REF_COST);
5293
5294 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5295 "TWI $dst\n\t"
5296 "ISYNC" %}
5297 size(12);
5298 ins_encode( enc_lbz_ac(dst, mem) );
5299 ins_pipe(pipe_class_memory);
5300 %}
5301
5302 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5303 instruct loadUB2L(iRegLdst dst, memory mem) %{
5304 match(Set dst (ConvI2L (LoadUB mem)));
5305 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5306 ins_cost(MEMORY_REF_COST);
5307
5308 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5309 size(4);
5310 ins_encode( enc_lbz(dst, mem) );
5311 ins_pipe(pipe_class_memory);
5312 %}
5313
5314 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5315 match(Set dst (ConvI2L (LoadUB mem)));
5316 ins_cost(3*MEMORY_REF_COST);
5317
5318 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5319 "TWI $dst\n\t"
5320 "ISYNC" %}
5321 size(12);
5322 ins_encode( enc_lbz_ac(dst, mem) );
5323 ins_pipe(pipe_class_memory);
5324 %}
5325
5326 // Load Short (16bit signed)
5327 instruct loadS(iRegIdst dst, memory mem) %{
5328 match(Set dst (LoadS mem));
5329 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5330 ins_cost(MEMORY_REF_COST);
5331
5332 format %{ "LHA $dst, $mem" %}
5333 size(4);
5334 ins_encode %{
5335 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5336 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5337 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5338 %}
5339 ins_pipe(pipe_class_memory);
5340 %}
5341
5342 // Load Short (16bit signed) acquire.
5343 instruct loadS_ac(iRegIdst dst, memory mem) %{
5344 match(Set dst (LoadS mem));
5345 ins_cost(3*MEMORY_REF_COST);
5346
5347 format %{ "LHA $dst, $mem\t acquire\n\t"
5348 "TWI $dst\n\t"
5349 "ISYNC" %}
5350 size(12);
5351 ins_encode %{
5352 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5353 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5354 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5355 __ twi_0($dst$$Register);
5356 __ isync();
5357 %}
5358 ins_pipe(pipe_class_memory);
5359 %}
5360
5361 // Load Char (16bit unsigned)
5362 instruct loadUS(iRegIdst dst, memory mem) %{
5363 match(Set dst (LoadUS mem));
5364 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5365 ins_cost(MEMORY_REF_COST);
5366
5367 format %{ "LHZ $dst, $mem" %}
5368 size(4);
5369 ins_encode( enc_lhz(dst, mem) );
5370 ins_pipe(pipe_class_memory);
5371 %}
5372
5373 // Load Char (16bit unsigned) acquire.
5374 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5375 match(Set dst (LoadUS mem));
5376 ins_cost(3*MEMORY_REF_COST);
5377
5378 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5379 "TWI $dst\n\t"
5380 "ISYNC" %}
5381 size(12);
5382 ins_encode( enc_lhz_ac(dst, mem) );
5383 ins_pipe(pipe_class_memory);
5384 %}
5385
5386 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5387 instruct loadUS2L(iRegLdst dst, memory mem) %{
5388 match(Set dst (ConvI2L (LoadUS mem)));
5389 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5390 ins_cost(MEMORY_REF_COST);
5391
5392 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5393 size(4);
5394 ins_encode( enc_lhz(dst, mem) );
5395 ins_pipe(pipe_class_memory);
5396 %}
5397
5398 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5399 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5400 match(Set dst (ConvI2L (LoadUS mem)));
5401 ins_cost(3*MEMORY_REF_COST);
5402
5403 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5404 "TWI $dst\n\t"
5405 "ISYNC" %}
5406 size(12);
5407 ins_encode( enc_lhz_ac(dst, mem) );
5408 ins_pipe(pipe_class_memory);
5409 %}
5410
5411 // Load Integer.
5412 instruct loadI(iRegIdst dst, memory mem) %{
5413 match(Set dst (LoadI mem));
5414 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5415 ins_cost(MEMORY_REF_COST);
5416
5417 format %{ "LWZ $dst, $mem" %}
5418 size(4);
5419 ins_encode( enc_lwz(dst, mem) );
5420 ins_pipe(pipe_class_memory);
5421 %}
5422
5423 // Load Integer acquire.
5424 instruct loadI_ac(iRegIdst dst, memory mem) %{
5425 match(Set dst (LoadI mem));
5426 ins_cost(3*MEMORY_REF_COST);
5427
5428 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5429 "TWI $dst\n\t"
5430 "ISYNC" %}
5431 size(12);
5432 ins_encode( enc_lwz_ac(dst, mem) );
5433 ins_pipe(pipe_class_memory);
5434 %}
5435
5436 // Match loading integer and casting it to unsigned int in
5437 // long register.
5438 // LoadI + ConvI2L + AndL 0xffffffff.
5439 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5440 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5441 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5442 ins_cost(MEMORY_REF_COST);
5443
5444 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5445 size(4);
5446 ins_encode( enc_lwz(dst, mem) );
5447 ins_pipe(pipe_class_memory);
5448 %}
5449
5450 // Match loading integer and casting it to long.
5451 instruct loadI2L(iRegLdst dst, memory mem) %{
5452 match(Set dst (ConvI2L (LoadI mem)));
5453 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5454 ins_cost(MEMORY_REF_COST);
5455
5456 format %{ "LWA $dst, $mem \t// loadI2L" %}
5457 size(4);
5458 ins_encode %{
5459 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5460 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5461 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5462 %}
5463 ins_pipe(pipe_class_memory);
5464 %}
5465
5466 // Match loading integer and casting it to long - acquire.
5467 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5468 match(Set dst (ConvI2L (LoadI mem)));
5469 ins_cost(3*MEMORY_REF_COST);
5470
5471 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5472 "TWI $dst\n\t"
5473 "ISYNC" %}
5474 size(12);
5475 ins_encode %{
5476 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5477 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5478 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5479 __ twi_0($dst$$Register);
5480 __ isync();
5481 %}
5482 ins_pipe(pipe_class_memory);
5483 %}
5484
5485 // Load Long - aligned
5486 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5487 match(Set dst (LoadL mem));
5488 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5489 ins_cost(MEMORY_REF_COST);
5490
5491 format %{ "LD $dst, $mem \t// long" %}
5492 size(4);
5493 ins_encode( enc_ld(dst, mem) );
5494 ins_pipe(pipe_class_memory);
5495 %}
5496
5497 // Load Long - aligned acquire.
5498 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5499 match(Set dst (LoadL mem));
5500 ins_cost(3*MEMORY_REF_COST);
5501
5502 format %{ "LD $dst, $mem \t// long acquire\n\t"
5503 "TWI $dst\n\t"
5504 "ISYNC" %}
5505 size(12);
5506 ins_encode( enc_ld_ac(dst, mem) );
5507 ins_pipe(pipe_class_memory);
5508 %}
5509
5510 // Load Long - UNaligned
5511 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5512 match(Set dst (LoadL_unaligned mem));
5513 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5514 ins_cost(MEMORY_REF_COST);
5515
5516 format %{ "LD $dst, $mem \t// unaligned long" %}
5517 size(4);
5518 ins_encode( enc_ld(dst, mem) );
5519 ins_pipe(pipe_class_memory);
5520 %}
5521
5522 // Load nodes for superwords
5523
5524 // Load Aligned Packed Byte
5525 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5526 predicate(n->as_LoadVector()->memory_size() == 8);
5527 match(Set dst (LoadVector mem));
5528 ins_cost(MEMORY_REF_COST);
5529
5530 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5531 size(4);
5532 ins_encode( enc_ld(dst, mem) );
5533 ins_pipe(pipe_class_memory);
5534 %}
5535
5536 // Load Range, range = array length (=jint)
5537 instruct loadRange(iRegIdst dst, memory mem) %{
5538 match(Set dst (LoadRange mem));
5539 ins_cost(MEMORY_REF_COST);
5540
5541 format %{ "LWZ $dst, $mem \t// range" %}
5542 size(4);
5543 ins_encode( enc_lwz(dst, mem) );
5544 ins_pipe(pipe_class_memory);
5545 %}
5546
5547 // Load Compressed Pointer
5548 instruct loadN(iRegNdst dst, memory mem) %{
5549 match(Set dst (LoadN mem));
5550 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5551 ins_cost(MEMORY_REF_COST);
5552
5553 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5554 size(4);
5555 ins_encode( enc_lwz(dst, mem) );
5556 ins_pipe(pipe_class_memory);
5557 %}
5558
5559 // Load Compressed Pointer acquire.
5560 instruct loadN_ac(iRegNdst dst, memory mem) %{
5561 match(Set dst (LoadN mem));
5562 ins_cost(3*MEMORY_REF_COST);
5563
5564 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5565 "TWI $dst\n\t"
5566 "ISYNC" %}
5567 size(12);
5568 ins_encode( enc_lwz_ac(dst, mem) );
5569 ins_pipe(pipe_class_memory);
5570 %}
5571
5572 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5573 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5574 match(Set dst (DecodeN (LoadN mem)));
5575 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5576 ins_cost(MEMORY_REF_COST);
5577
5578 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5579 size(4);
5580 ins_encode( enc_lwz(dst, mem) );
5581 ins_pipe(pipe_class_memory);
5582 %}
5583
5584 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5585 match(Set dst (DecodeNKlass (LoadNKlass mem)));
5586 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5587 _kids[0]->_leaf->as_Load()->is_unordered());
5588 ins_cost(MEMORY_REF_COST);
5589
5590 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5591 size(4);
5592 ins_encode( enc_lwz(dst, mem) );
5593 ins_pipe(pipe_class_memory);
5594 %}
5595
5596 // Load Pointer
5597 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5598 match(Set dst (LoadP mem));
5599 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5600 ins_cost(MEMORY_REF_COST);
5601
5602 format %{ "LD $dst, $mem \t// ptr" %}
5603 size(4);
5604 ins_encode( enc_ld(dst, mem) );
5605 ins_pipe(pipe_class_memory);
5606 %}
5607
5608 // Load Pointer acquire.
5609 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5610 match(Set dst (LoadP mem));
5611 ins_cost(3*MEMORY_REF_COST);
5612
5613 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5614 "TWI $dst\n\t"
5615 "ISYNC" %}
5616 size(12);
5617 ins_encode( enc_ld_ac(dst, mem) );
5618 ins_pipe(pipe_class_memory);
5619 %}
5620
5621 // LoadP + CastP2L
5622 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5623 match(Set dst (CastP2X (LoadP mem)));
5624 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5625 ins_cost(MEMORY_REF_COST);
5626
5627 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5628 size(4);
5629 ins_encode( enc_ld(dst, mem) );
5630 ins_pipe(pipe_class_memory);
5631 %}
5632
5633 // Load compressed klass pointer.
5634 instruct loadNKlass(iRegNdst dst, memory mem) %{
5635 match(Set dst (LoadNKlass mem));
5636 ins_cost(MEMORY_REF_COST);
5637
5638 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5639 size(4);
5640 ins_encode( enc_lwz(dst, mem) );
5641 ins_pipe(pipe_class_memory);
5642 %}
5643
5644 // Load Klass Pointer
5645 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5646 match(Set dst (LoadKlass mem));
5647 ins_cost(MEMORY_REF_COST);
5648
5649 format %{ "LD $dst, $mem \t// klass ptr" %}
5650 size(4);
5651 ins_encode( enc_ld(dst, mem) );
5652 ins_pipe(pipe_class_memory);
5653 %}
5654
5655 // Load Float
5656 instruct loadF(regF dst, memory mem) %{
5657 match(Set dst (LoadF mem));
5658 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5659 ins_cost(MEMORY_REF_COST);
5660
5661 format %{ "LFS $dst, $mem" %}
5662 size(4);
5663 ins_encode %{
5664 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5665 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5666 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5667 %}
5668 ins_pipe(pipe_class_memory);
5669 %}
5670
5671 // Load Float acquire.
5672 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5673 match(Set dst (LoadF mem));
5674 effect(TEMP cr0);
5675 ins_cost(3*MEMORY_REF_COST);
5676
5677 format %{ "LFS $dst, $mem \t// acquire\n\t"
5678 "FCMPU cr0, $dst, $dst\n\t"
5679 "BNE cr0, next\n"
5680 "next:\n\t"
5681 "ISYNC" %}
5682 size(16);
5683 ins_encode %{
5684 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5685 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5686 Label next;
5687 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5688 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5689 __ bne(CCR0, next);
5690 __ bind(next);
5691 __ isync();
5692 %}
5693 ins_pipe(pipe_class_memory);
5694 %}
5695
5696 // Load Double - aligned
5697 instruct loadD(regD dst, memory mem) %{
5698 match(Set dst (LoadD mem));
5699 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5700 ins_cost(MEMORY_REF_COST);
5701
5702 format %{ "LFD $dst, $mem" %}
5703 size(4);
5704 ins_encode( enc_lfd(dst, mem) );
5705 ins_pipe(pipe_class_memory);
5706 %}
5707
5708 // Load Double - aligned acquire.
5709 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5710 match(Set dst (LoadD mem));
5711 effect(TEMP cr0);
5712 ins_cost(3*MEMORY_REF_COST);
5713
5714 format %{ "LFD $dst, $mem \t// acquire\n\t"
5715 "FCMPU cr0, $dst, $dst\n\t"
5716 "BNE cr0, next\n"
5717 "next:\n\t"
5718 "ISYNC" %}
5719 size(16);
5720 ins_encode %{
5721 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5722 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5723 Label next;
5724 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5725 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5726 __ bne(CCR0, next);
5727 __ bind(next);
5728 __ isync();
5729 %}
5730 ins_pipe(pipe_class_memory);
5731 %}
5732
5733 // Load Double - UNaligned
5734 instruct loadD_unaligned(regD dst, memory mem) %{
5735 match(Set dst (LoadD_unaligned mem));
5736 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5737 ins_cost(MEMORY_REF_COST);
5738
5739 format %{ "LFD $dst, $mem" %}
5740 size(4);
5741 ins_encode( enc_lfd(dst, mem) );
5742 ins_pipe(pipe_class_memory);
5743 %}
5744
5745 //----------Constants--------------------------------------------------------
5746
5747 // Load MachConstantTableBase: add hi offset to global toc.
5748 // TODO: Handle hidden register r29 in bundler!
5749 instruct loadToc_hi(iRegLdst dst) %{
5750 effect(DEF dst);
5751 ins_cost(DEFAULT_COST);
5752
5753 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5754 size(4);
5755 ins_encode %{
5756 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5757 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5758 %}
5759 ins_pipe(pipe_class_default);
5760 %}
5761
5762 // Load MachConstantTableBase: add lo offset to global toc.
5763 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5764 effect(DEF dst, USE src);
5765 ins_cost(DEFAULT_COST);
5766
5767 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5768 size(4);
5769 ins_encode %{
5770 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5771 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5772 %}
5773 ins_pipe(pipe_class_default);
5774 %}
5775
5776 // Load 16-bit integer constant 0xssss????
5777 instruct loadConI16(iRegIdst dst, immI16 src) %{
5778 match(Set dst src);
5779
5780 format %{ "LI $dst, $src" %}
5781 size(4);
5782 ins_encode %{
5783 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5784 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5785 %}
5786 ins_pipe(pipe_class_default);
5787 %}
5788
5789 // Load integer constant 0x????0000
5790 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5791 match(Set dst src);
5792 ins_cost(DEFAULT_COST);
5793
5794 format %{ "LIS $dst, $src.hi" %}
5795 size(4);
5796 ins_encode %{
5797 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5798 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5799 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5800 %}
5801 ins_pipe(pipe_class_default);
5802 %}
5803
5804 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5805 // and sign extended), this adds the low 16 bits.
5806 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5807 // no match-rule, false predicate
5808 effect(DEF dst, USE src1, USE src2);
5809 predicate(false);
5810
5811 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5812 size(4);
5813 ins_encode %{
5814 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5815 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5816 %}
5817 ins_pipe(pipe_class_default);
5818 %}
5819
5820 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5821 match(Set dst src);
5822 ins_cost(DEFAULT_COST*2);
5823
5824 expand %{
5825 // Would like to use $src$$constant.
5826 immI16 srcLo %{ _opnds[1]->constant() %}
5827 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5828 immIhi16 srcHi %{ _opnds[1]->constant() %}
5829 iRegIdst tmpI;
5830 loadConIhi16(tmpI, srcHi);
5831 loadConI32_lo16(dst, tmpI, srcLo);
5832 %}
5833 %}
5834
5835 // No constant pool entries required.
5836 instruct loadConL16(iRegLdst dst, immL16 src) %{
5837 match(Set dst src);
5838
5839 format %{ "LI $dst, $src \t// long" %}
5840 size(4);
5841 ins_encode %{
5842 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5843 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5844 %}
5845 ins_pipe(pipe_class_default);
5846 %}
5847
5848 // Load long constant 0xssssssss????0000
5849 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5850 match(Set dst src);
5851 ins_cost(DEFAULT_COST);
5852
5853 format %{ "LIS $dst, $src.hi \t// long" %}
5854 size(4);
5855 ins_encode %{
5856 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5857 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5858 %}
5859 ins_pipe(pipe_class_default);
5860 %}
5861
5862 // To load a 32 bit constant: merge lower 16 bits into already loaded
5863 // high 16 bits.
5864 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5865 // no match-rule, false predicate
5866 effect(DEF dst, USE src1, USE src2);
5867 predicate(false);
5868
5869 format %{ "ORI $dst, $src1, $src2.lo" %}
5870 size(4);
5871 ins_encode %{
5872 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5873 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5874 %}
5875 ins_pipe(pipe_class_default);
5876 %}
5877
5878 // Load 32-bit long constant
5879 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5880 match(Set dst src);
5881 ins_cost(DEFAULT_COST*2);
5882
5883 expand %{
5884 // Would like to use $src$$constant.
5885 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5886 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5887 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5888 iRegLdst tmpL;
5889 loadConL32hi16(tmpL, srcHi);
5890 loadConL32_lo16(dst, tmpL, srcLo);
5891 %}
5892 %}
5893
5894 // Load long constant 0x????000000000000.
5895 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5896 match(Set dst src);
5897 ins_cost(DEFAULT_COST);
5898
5899 expand %{
5900 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5901 immI shift32 %{ 32 %}
5902 iRegLdst tmpL;
5903 loadConL32hi16(tmpL, srcHi);
5904 lshiftL_regL_immI(dst, tmpL, shift32);
5905 %}
5906 %}
5907
5908 // Expand node for constant pool load: small offset.
5909 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5910 effect(DEF dst, USE src, USE toc);
5911 ins_cost(MEMORY_REF_COST);
5912
5913 ins_num_consts(1);
5914 // Needed so that CallDynamicJavaDirect can compute the address of this
5915 // instruction for relocation.
5916 ins_field_cbuf_insts_offset(int);
5917
5918 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5919 size(4);
5920 ins_encode( enc_load_long_constL(dst, src, toc) );
5921 ins_pipe(pipe_class_memory);
5922 %}
5923
5924 // Expand node for constant pool load: large offset.
5925 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5926 effect(DEF dst, USE src, USE toc);
5927 predicate(false);
5928
5929 ins_num_consts(1);
5930 ins_field_const_toc_offset(int);
5931 // Needed so that CallDynamicJavaDirect can compute the address of this
5932 // instruction for relocation.
5933 ins_field_cbuf_insts_offset(int);
5934
5935 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5936 size(4);
5937 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5938 ins_pipe(pipe_class_default);
5939 %}
5940
5941 // Expand node for constant pool load: large offset.
5942 // No constant pool entries required.
5943 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5944 effect(DEF dst, USE src, USE base);
5945 predicate(false);
5946
5947 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5948
5949 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5950 size(4);
5951 ins_encode %{
5952 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5953 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5954 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5955 %}
5956 ins_pipe(pipe_class_memory);
5957 %}
5958
5959 // Load long constant from constant table. Expand in case of
5960 // offset > 16 bit is needed.
5961 // Adlc adds toc node MachConstantTableBase.
5962 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5963 match(Set dst src);
5964 ins_cost(MEMORY_REF_COST);
5965
5966 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5967 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5968 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5969 %}
5970
5971 // Load NULL as compressed oop.
5972 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5973 match(Set dst src);
5974 ins_cost(DEFAULT_COST);
5975
5976 format %{ "LI $dst, $src \t// compressed ptr" %}
5977 size(4);
5978 ins_encode %{
5979 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5980 __ li($dst$$Register, 0);
5981 %}
5982 ins_pipe(pipe_class_default);
5983 %}
5984
5985 // Load hi part of compressed oop constant.
5986 instruct loadConN_hi(iRegNdst dst, immN src) %{
5987 effect(DEF dst, USE src);
5988 ins_cost(DEFAULT_COST);
5989
5990 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5991 size(4);
5992 ins_encode %{
5993 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5994 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5995 %}
5996 ins_pipe(pipe_class_default);
5997 %}
5998
5999 // Add lo part of compressed oop constant to already loaded hi part.
6000 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6001 effect(DEF dst, USE src1, USE src2);
6002 ins_cost(DEFAULT_COST);
6003
6004 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6005 size(4);
6006 ins_encode %{
6007 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6008 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6009 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6010 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6011 __ relocate(rspec, 1);
6012 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6013 %}
6014 ins_pipe(pipe_class_default);
6015 %}
6016
6017 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6018 // leaving the upper 32 bits with sign-extension bits.
6019 // This clears these bits: dst = src & 0xFFFFFFFF.
6020 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6021 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6022 effect(DEF dst, USE src);
6023 predicate(false);
6024
6025 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6026 size(4);
6027 ins_encode %{
6028 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6029 __ clrldi($dst$$Register, $src$$Register, 0x20);
6030 %}
6031 ins_pipe(pipe_class_default);
6032 %}
6033
6034 // Optimize DecodeN for disjoint base.
6035 // Load base of compressed oops into a register
6036 instruct loadBase(iRegLdst dst) %{
6037 effect(DEF dst);
6038
6039 format %{ "LoadConst $dst, heapbase" %}
6040 ins_encode %{
6041 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6042 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
6043 %}
6044 ins_pipe(pipe_class_default);
6045 %}
6046
6047 // Loading ConN must be postalloc expanded so that edges between
6048 // the nodes are safe. They may not interfere with a safepoint.
6049 // GL TODO: This needs three instructions: better put this into the constant pool.
6050 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6051 match(Set dst src);
6052 ins_cost(DEFAULT_COST*2);
6053
6054 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6055 postalloc_expand %{
6056 MachNode *m1 = new loadConN_hiNode();
6057 MachNode *m2 = new loadConN_loNode();
6058 MachNode *m3 = new clearMs32bNode();
6059 m1->add_req(NULL);
6060 m2->add_req(NULL, m1);
6061 m3->add_req(NULL, m2);
6062 m1->_opnds[0] = op_dst;
6063 m1->_opnds[1] = op_src;
6064 m2->_opnds[0] = op_dst;
6065 m2->_opnds[1] = op_dst;
6066 m2->_opnds[2] = op_src;
6067 m3->_opnds[0] = op_dst;
6068 m3->_opnds[1] = op_dst;
6069 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6070 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6071 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6072 nodes->push(m1);
6073 nodes->push(m2);
6074 nodes->push(m3);
6075 %}
6076 %}
6077
6078 // We have seen a safepoint between the hi and lo parts, and this node was handled
6079 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6080 // not a narrow oop.
6081 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6082 match(Set dst src);
6083 effect(DEF dst, USE src);
6084 ins_cost(DEFAULT_COST);
6085
6086 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6087 size(4);
6088 ins_encode %{
6089 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6090 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6091 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6092 %}
6093 ins_pipe(pipe_class_default);
6094 %}
6095
6096 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6097 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6098 match(Set dst src1);
6099 effect(TEMP src2);
6100 ins_cost(DEFAULT_COST);
6101
6102 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6103 size(4);
6104 ins_encode %{
6105 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6106 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6107 %}
6108 ins_pipe(pipe_class_default);
6109 %}
6110
6111 // This needs a match rule so that build_oop_map knows this is
6112 // not a narrow oop.
6113 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6114 match(Set dst src1);
6115 effect(TEMP src2);
6116 ins_cost(DEFAULT_COST);
6117
6118 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6119 size(4);
6120 ins_encode %{
6121 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6122 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6123 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6124 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6125 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6126
6127 __ relocate(rspec, 1);
6128 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6129 %}
6130 ins_pipe(pipe_class_default);
6131 %}
6132
6133 // Loading ConNKlass must be postalloc expanded so that edges between
6134 // the nodes are safe. They may not interfere with a safepoint.
6135 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6136 match(Set dst src);
6137 ins_cost(DEFAULT_COST*2);
6138
6139 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6140 postalloc_expand %{
6141 // Load high bits into register. Sign extended.
6142 MachNode *m1 = new loadConNKlass_hiNode();
6143 m1->add_req(NULL);
6144 m1->_opnds[0] = op_dst;
6145 m1->_opnds[1] = op_src;
6146 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6147 nodes->push(m1);
6148
6149 MachNode *m2 = m1;
6150 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6151 // Value might be 1-extended. Mask out these bits.
6152 m2 = new loadConNKlass_maskNode();
6153 m2->add_req(NULL, m1);
6154 m2->_opnds[0] = op_dst;
6155 m2->_opnds[1] = op_src;
6156 m2->_opnds[2] = op_dst;
6157 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6158 nodes->push(m2);
6159 }
6160
6161 MachNode *m3 = new loadConNKlass_loNode();
6162 m3->add_req(NULL, m2);
6163 m3->_opnds[0] = op_dst;
6164 m3->_opnds[1] = op_src;
6165 m3->_opnds[2] = op_dst;
6166 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6167 nodes->push(m3);
6168 %}
6169 %}
6170
6171 // 0x1 is used in object initialization (initial object header).
6172 // No constant pool entries required.
6173 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6174 match(Set dst src);
6175
6176 format %{ "LI $dst, $src \t// ptr" %}
6177 size(4);
6178 ins_encode %{
6179 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6180 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6181 %}
6182 ins_pipe(pipe_class_default);
6183 %}
6184
6185 // Expand node for constant pool load: small offset.
6186 // The match rule is needed to generate the correct bottom_type(),
6187 // however this node should never match. The use of predicate is not
6188 // possible since ADLC forbids predicates for chain rules. The higher
6189 // costs do not prevent matching in this case. For that reason the
6190 // operand immP_NM with predicate(false) is used.
6191 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6192 match(Set dst src);
6193 effect(TEMP toc);
6194
6195 ins_num_consts(1);
6196
6197 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6198 size(4);
6199 ins_encode( enc_load_long_constP(dst, src, toc) );
6200 ins_pipe(pipe_class_memory);
6201 %}
6202
6203 // Expand node for constant pool load: large offset.
6204 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6205 effect(DEF dst, USE src, USE toc);
6206 predicate(false);
6207
6208 ins_num_consts(1);
6209 ins_field_const_toc_offset(int);
6210
6211 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6212 size(4);
6213 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6214 ins_pipe(pipe_class_default);
6215 %}
6216
6217 // Expand node for constant pool load: large offset.
6218 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6219 match(Set dst src);
6220 effect(TEMP base);
6221
6222 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6223
6224 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6225 size(4);
6226 ins_encode %{
6227 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6228 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6229 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6230 %}
6231 ins_pipe(pipe_class_memory);
6232 %}
6233
6234 // Load pointer constant from constant table. Expand in case an
6235 // offset > 16 bit is needed.
6236 // Adlc adds toc node MachConstantTableBase.
6237 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6238 match(Set dst src);
6239 ins_cost(MEMORY_REF_COST);
6240
6241 // This rule does not use "expand" because then
6242 // the result type is not known to be an Oop. An ADLC
6243 // enhancement will be needed to make that work - not worth it!
6244
6245 // If this instruction rematerializes, it prolongs the live range
6246 // of the toc node, causing illegal graphs.
6247 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6248 ins_cannot_rematerialize(true);
6249
6250 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6251 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6252 %}
6253
6254 // Expand node for constant pool load: small offset.
6255 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6256 effect(DEF dst, USE src, USE toc);
6257 ins_cost(MEMORY_REF_COST);
6258
6259 ins_num_consts(1);
6260
6261 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6262 size(4);
6263 ins_encode %{
6264 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6265 address float_address = __ float_constant($src$$constant);
6266 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6267 %}
6268 ins_pipe(pipe_class_memory);
6269 %}
6270
6271 // Expand node for constant pool load: large offset.
6272 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6273 effect(DEF dst, USE src, USE toc);
6274 ins_cost(MEMORY_REF_COST);
6275
6276 ins_num_consts(1);
6277
6278 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6279 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6280 "ADDIS $toc, $toc, -offset_hi"%}
6281 size(12);
6282 ins_encode %{
6283 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6284 FloatRegister Rdst = $dst$$FloatRegister;
6285 Register Rtoc = $toc$$Register;
6286 address float_address = __ float_constant($src$$constant);
6287 int offset = __ offset_to_method_toc(float_address);
6288 int hi = (offset + (1<<15))>>16;
6289 int lo = offset - hi * (1<<16);
6290
6291 __ addis(Rtoc, Rtoc, hi);
6292 __ lfs(Rdst, lo, Rtoc);
6293 __ addis(Rtoc, Rtoc, -hi);
6294 %}
6295 ins_pipe(pipe_class_memory);
6296 %}
6297
6298 // Adlc adds toc node MachConstantTableBase.
6299 instruct loadConF_Ex(regF dst, immF src) %{
6300 match(Set dst src);
6301 ins_cost(MEMORY_REF_COST);
6302
6303 // See loadConP.
6304 ins_cannot_rematerialize(true);
6305
6306 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6307 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6308 %}
6309
6310 // Expand node for constant pool load: small offset.
6311 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6312 effect(DEF dst, USE src, USE toc);
6313 ins_cost(MEMORY_REF_COST);
6314
6315 ins_num_consts(1);
6316
6317 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6318 size(4);
6319 ins_encode %{
6320 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6321 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6322 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6323 %}
6324 ins_pipe(pipe_class_memory);
6325 %}
6326
6327 // Expand node for constant pool load: large offset.
6328 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6329 effect(DEF dst, USE src, USE toc);
6330 ins_cost(MEMORY_REF_COST);
6331
6332 ins_num_consts(1);
6333
6334 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6335 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6336 "ADDIS $toc, $toc, -offset_hi" %}
6337 size(12);
6338 ins_encode %{
6339 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6340 FloatRegister Rdst = $dst$$FloatRegister;
6341 Register Rtoc = $toc$$Register;
6342 address float_address = __ double_constant($src$$constant);
6343 int offset = __ offset_to_method_toc(float_address);
6344 int hi = (offset + (1<<15))>>16;
6345 int lo = offset - hi * (1<<16);
6346
6347 __ addis(Rtoc, Rtoc, hi);
6348 __ lfd(Rdst, lo, Rtoc);
6349 __ addis(Rtoc, Rtoc, -hi);
6350 %}
6351 ins_pipe(pipe_class_memory);
6352 %}
6353
6354 // Adlc adds toc node MachConstantTableBase.
6355 instruct loadConD_Ex(regD dst, immD src) %{
6356 match(Set dst src);
6357 ins_cost(MEMORY_REF_COST);
6358
6359 // See loadConP.
6360 ins_cannot_rematerialize(true);
6361
6362 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6363 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6364 %}
6365
6366 // Prefetch instructions.
6367 // Must be safe to execute with invalid address (cannot fault).
6368
6369 // Special prefetch versions which use the dcbz instruction.
6370 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6371 match(PrefetchAllocation (AddP mem src));
6372 predicate(AllocatePrefetchStyle == 3);
6373 ins_cost(MEMORY_REF_COST);
6374
6375 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6376 size(4);
6377 ins_encode %{
6378 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6379 __ dcbz($src$$Register, $mem$$base$$Register);
6380 %}
6381 ins_pipe(pipe_class_memory);
6382 %}
6383
6384 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6385 match(PrefetchAllocation mem);
6386 predicate(AllocatePrefetchStyle == 3);
6387 ins_cost(MEMORY_REF_COST);
6388
6389 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6390 size(4);
6391 ins_encode %{
6392 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6393 __ dcbz($mem$$base$$Register);
6394 %}
6395 ins_pipe(pipe_class_memory);
6396 %}
6397
6398 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6399 match(PrefetchAllocation (AddP mem src));
6400 predicate(AllocatePrefetchStyle != 3);
6401 ins_cost(MEMORY_REF_COST);
6402
6403 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6404 size(4);
6405 ins_encode %{
6406 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6407 __ dcbtst($src$$Register, $mem$$base$$Register);
6408 %}
6409 ins_pipe(pipe_class_memory);
6410 %}
6411
6412 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6413 match(PrefetchAllocation mem);
6414 predicate(AllocatePrefetchStyle != 3);
6415 ins_cost(MEMORY_REF_COST);
6416
6417 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6418 size(4);
6419 ins_encode %{
6420 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6421 __ dcbtst($mem$$base$$Register);
6422 %}
6423 ins_pipe(pipe_class_memory);
6424 %}
6425
6426 //----------Store Instructions-------------------------------------------------
6427
6428 // Store Byte
6429 instruct storeB(memory mem, iRegIsrc src) %{
6430 match(Set mem (StoreB mem src));
6431 ins_cost(MEMORY_REF_COST);
6432
6433 format %{ "STB $src, $mem \t// byte" %}
6434 size(4);
6435 ins_encode %{
6436 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6437 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6438 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6439 %}
6440 ins_pipe(pipe_class_memory);
6441 %}
6442
6443 // Store Char/Short
6444 instruct storeC(memory mem, iRegIsrc src) %{
6445 match(Set mem (StoreC mem src));
6446 ins_cost(MEMORY_REF_COST);
6447
6448 format %{ "STH $src, $mem \t// short" %}
6449 size(4);
6450 ins_encode %{
6451 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6452 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6453 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6454 %}
6455 ins_pipe(pipe_class_memory);
6456 %}
6457
6458 // Store Integer
6459 instruct storeI(memory mem, iRegIsrc src) %{
6460 match(Set mem (StoreI mem src));
6461 ins_cost(MEMORY_REF_COST);
6462
6463 format %{ "STW $src, $mem" %}
6464 size(4);
6465 ins_encode( enc_stw(src, mem) );
6466 ins_pipe(pipe_class_memory);
6467 %}
6468
6469 // ConvL2I + StoreI.
6470 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6471 match(Set mem (StoreI mem (ConvL2I src)));
6472 ins_cost(MEMORY_REF_COST);
6473
6474 format %{ "STW l2i($src), $mem" %}
6475 size(4);
6476 ins_encode( enc_stw(src, mem) );
6477 ins_pipe(pipe_class_memory);
6478 %}
6479
6480 // Store Long
6481 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6482 match(Set mem (StoreL mem src));
6483 ins_cost(MEMORY_REF_COST);
6484
6485 format %{ "STD $src, $mem \t// long" %}
6486 size(4);
6487 ins_encode( enc_std(src, mem) );
6488 ins_pipe(pipe_class_memory);
6489 %}
6490
6491 // Store super word nodes.
6492
6493 // Store Aligned Packed Byte long register to memory
6494 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6495 predicate(n->as_StoreVector()->memory_size() == 8);
6496 match(Set mem (StoreVector mem src));
6497 ins_cost(MEMORY_REF_COST);
6498
6499 format %{ "STD $mem, $src \t// packed8B" %}
6500 size(4);
6501 ins_encode( enc_std(src, mem) );
6502 ins_pipe(pipe_class_memory);
6503 %}
6504
6505 // Store Compressed Oop
6506 instruct storeN(memory dst, iRegN_P2N src) %{
6507 match(Set dst (StoreN dst src));
6508 ins_cost(MEMORY_REF_COST);
6509
6510 format %{ "STW $src, $dst \t// compressed oop" %}
6511 size(4);
6512 ins_encode( enc_stw(src, dst) );
6513 ins_pipe(pipe_class_memory);
6514 %}
6515
6516 // Store Compressed KLass
6517 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6518 match(Set dst (StoreNKlass dst src));
6519 ins_cost(MEMORY_REF_COST);
6520
6521 format %{ "STW $src, $dst \t// compressed klass" %}
6522 size(4);
6523 ins_encode( enc_stw(src, dst) );
6524 ins_pipe(pipe_class_memory);
6525 %}
6526
6527 // Store Pointer
6528 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6529 match(Set dst (StoreP dst src));
6530 ins_cost(MEMORY_REF_COST);
6531
6532 format %{ "STD $src, $dst \t// ptr" %}
6533 size(4);
6534 ins_encode( enc_std(src, dst) );
6535 ins_pipe(pipe_class_memory);
6536 %}
6537
6538 // Store Float
6539 instruct storeF(memory mem, regF src) %{
6540 match(Set mem (StoreF mem src));
6541 ins_cost(MEMORY_REF_COST);
6542
6543 format %{ "STFS $src, $mem" %}
6544 size(4);
6545 ins_encode( enc_stfs(src, mem) );
6546 ins_pipe(pipe_class_memory);
6547 %}
6548
6549 // Store Double
6550 instruct storeD(memory mem, regD src) %{
6551 match(Set mem (StoreD mem src));
6552 ins_cost(MEMORY_REF_COST);
6553
6554 format %{ "STFD $src, $mem" %}
6555 size(4);
6556 ins_encode( enc_stfd(src, mem) );
6557 ins_pipe(pipe_class_memory);
6558 %}
6559
6560 //----------Store Instructions With Zeros--------------------------------------
6561
6562 // Card-mark for CMS garbage collection.
6563 // This cardmark does an optimization so that it must not always
6564 // do a releasing store. For this, it gets the address of
6565 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6566 // (Using releaseFieldAddr in the match rule is a hack.)
6567 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6568 match(Set mem (StoreCM mem releaseFieldAddr));
6569 effect(TEMP crx);
6570 predicate(false);
6571 ins_cost(MEMORY_REF_COST);
6572
6573 // See loadConP.
6574 ins_cannot_rematerialize(true);
6575
6576 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6577 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6578 ins_pipe(pipe_class_memory);
6579 %}
6580
6581 // Card-mark for CMS garbage collection.
6582 // This cardmark does an optimization so that it must not always
6583 // do a releasing store. For this, it needs the constant address of
6584 // CMSCollectorCardTableModRefBSExt::_requires_release.
6585 // This constant address is split off here by expand so we can use
6586 // adlc / matcher functionality to load it from the constant section.
6587 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6588 match(Set mem (StoreCM mem zero));
6589 predicate(UseConcMarkSweepGC);
6590
6591 expand %{
6592 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6593 iRegLdst releaseFieldAddress;
6594 flagsReg crx;
6595 loadConL_Ex(releaseFieldAddress, baseImm);
6596 storeCM_CMS(mem, releaseFieldAddress, crx);
6597 %}
6598 %}
6599
6600 instruct storeCM_G1(memory mem, immI_0 zero) %{
6601 match(Set mem (StoreCM mem zero));
6602 predicate(UseG1GC);
6603 ins_cost(MEMORY_REF_COST);
6604
6605 ins_cannot_rematerialize(true);
6606
6607 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6608 size(8);
6609 ins_encode %{
6610 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6611 __ li(R0, 0);
6612 //__ release(); // G1: oops are allowed to get visible after dirty marking
6613 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6614 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6615 %}
6616 ins_pipe(pipe_class_memory);
6617 %}
6618
6619 // Convert oop pointer into compressed form.
6620
6621 // Nodes for postalloc expand.
6622
6623 // Shift node for expand.
6624 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6625 // The match rule is needed to make it a 'MachTypeNode'!
6626 match(Set dst (EncodeP src));
6627 predicate(false);
6628
6629 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6630 size(4);
6631 ins_encode %{
6632 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6633 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6634 %}
6635 ins_pipe(pipe_class_default);
6636 %}
6637
6638 // Add node for expand.
6639 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6640 // The match rule is needed to make it a 'MachTypeNode'!
6641 match(Set dst (EncodeP src));
6642 predicate(false);
6643
6644 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6645 ins_encode %{
6646 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6647 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6648 %}
6649 ins_pipe(pipe_class_default);
6650 %}
6651
6652 // Conditional sub base.
6653 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6654 // The match rule is needed to make it a 'MachTypeNode'!
6655 match(Set dst (EncodeP (Binary crx src1)));
6656 predicate(false);
6657
6658 format %{ "BEQ $crx, done\n\t"
6659 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6660 "done:" %}
6661 ins_encode %{
6662 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6663 Label done;
6664 __ beq($crx$$CondRegister, done);
6665 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6666 __ bind(done);
6667 %}
6668 ins_pipe(pipe_class_default);
6669 %}
6670
6671 // Power 7 can use isel instruction
6672 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6673 // The match rule is needed to make it a 'MachTypeNode'!
6674 match(Set dst (EncodeP (Binary crx src1)));
6675 predicate(false);
6676
6677 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6678 size(4);
6679 ins_encode %{
6680 // This is a Power7 instruction for which no machine description exists.
6681 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6682 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6683 %}
6684 ins_pipe(pipe_class_default);
6685 %}
6686
6687 // Disjoint narrow oop base.
6688 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6689 match(Set dst (EncodeP src));
6690 predicate(Universe::narrow_oop_base_disjoint());
6691
6692 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6693 size(4);
6694 ins_encode %{
6695 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6696 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6697 %}
6698 ins_pipe(pipe_class_default);
6699 %}
6700
6701 // shift != 0, base != 0
6702 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6703 match(Set dst (EncodeP src));
6704 effect(TEMP crx);
6705 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6706 Universe::narrow_oop_shift() != 0 &&
6707 Universe::narrow_oop_base_overlaps());
6708
6709 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6710 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6711 %}
6712
6713 // shift != 0, base != 0
6714 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6715 match(Set dst (EncodeP src));
6716 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6717 Universe::narrow_oop_shift() != 0 &&
6718 Universe::narrow_oop_base_overlaps());
6719
6720 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6721 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6722 %}
6723
6724 // shift != 0, base == 0
6725 // TODO: This is the same as encodeP_shift. Merge!
6726 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6727 match(Set dst (EncodeP src));
6728 predicate(Universe::narrow_oop_shift() != 0 &&
6729 Universe::narrow_oop_base() ==0);
6730
6731 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6732 size(4);
6733 ins_encode %{
6734 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6735 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6736 %}
6737 ins_pipe(pipe_class_default);
6738 %}
6739
6740 // Compressed OOPs with narrow_oop_shift == 0.
6741 // shift == 0, base == 0
6742 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6743 match(Set dst (EncodeP src));
6744 predicate(Universe::narrow_oop_shift() == 0);
6745
6746 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6747 // variable size, 0 or 4.
6748 ins_encode %{
6749 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6750 __ mr_if_needed($dst$$Register, $src$$Register);
6751 %}
6752 ins_pipe(pipe_class_default);
6753 %}
6754
6755 // Decode nodes.
6756
6757 // Shift node for expand.
6758 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6759 // The match rule is needed to make it a 'MachTypeNode'!
6760 match(Set dst (DecodeN src));
6761 predicate(false);
6762
6763 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6764 size(4);
6765 ins_encode %{
6766 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6767 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6768 %}
6769 ins_pipe(pipe_class_default);
6770 %}
6771
6772 // Add node for expand.
6773 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6774 // The match rule is needed to make it a 'MachTypeNode'!
6775 match(Set dst (DecodeN src));
6776 predicate(false);
6777
6778 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %}
6779 ins_encode %{
6780 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6781 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6782 %}
6783 ins_pipe(pipe_class_default);
6784 %}
6785
6786 // conditianal add base for expand
6787 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6788 // The match rule is needed to make it a 'MachTypeNode'!
6789 // NOTICE that the rule is nonsense - we just have to make sure that:
6790 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6791 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6792 match(Set dst (DecodeN (Binary crx src)));
6793 predicate(false);
6794
6795 format %{ "BEQ $crx, done\n\t"
6796 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6797 "done:" %}
6798 ins_encode %{
6799 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6800 Label done;
6801 __ beq($crx$$CondRegister, done);
6802 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6803 __ bind(done);
6804 %}
6805 ins_pipe(pipe_class_default);
6806 %}
6807
6808 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6809 // The match rule is needed to make it a 'MachTypeNode'!
6810 // NOTICE that the rule is nonsense - we just have to make sure that:
6811 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6812 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6813 match(Set dst (DecodeN (Binary crx src1)));
6814 predicate(false);
6815
6816 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6817 size(4);
6818 ins_encode %{
6819 // This is a Power7 instruction for which no machine description exists.
6820 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6821 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6822 %}
6823 ins_pipe(pipe_class_default);
6824 %}
6825
6826 // shift != 0, base != 0
6827 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6828 match(Set dst (DecodeN src));
6829 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6830 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6831 Universe::narrow_oop_shift() != 0 &&
6832 Universe::narrow_oop_base() != 0);
6833 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6834 effect(TEMP crx);
6835
6836 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6837 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6838 %}
6839
6840 // shift != 0, base == 0
6841 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6842 match(Set dst (DecodeN src));
6843 predicate(Universe::narrow_oop_shift() != 0 &&
6844 Universe::narrow_oop_base() == 0);
6845
6846 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6847 size(4);
6848 ins_encode %{
6849 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6850 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6851 %}
6852 ins_pipe(pipe_class_default);
6853 %}
6854
6855 // Optimize DecodeN for disjoint base.
6856 // Shift narrow oop and or it into register that already contains the heap base.
6857 // Base == dst must hold, and is assured by construction in postaloc_expand.
6858 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6859 match(Set dst (DecodeN src));
6860 effect(TEMP base);
6861 predicate(false);
6862
6863 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6864 size(4);
6865 ins_encode %{
6866 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6867 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6868 %}
6869 ins_pipe(pipe_class_default);
6870 %}
6871
6872 // Optimize DecodeN for disjoint base.
6873 // This node requires only one cycle on the critical path.
6874 // We must postalloc_expand as we can not express use_def effects where
6875 // the used register is L and the def'ed register P.
6876 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6877 match(Set dst (DecodeN src));
6878 effect(TEMP_DEF dst);
6879 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6880 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6881 Universe::narrow_oop_base_disjoint());
6882 ins_cost(DEFAULT_COST);
6883
6884 format %{ "MOV $dst, heapbase \t\n"
6885 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6886 postalloc_expand %{
6887 loadBaseNode *n1 = new loadBaseNode();
6888 n1->add_req(NULL);
6889 n1->_opnds[0] = op_dst;
6890
6891 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6892 n2->add_req(n_region, n_src, n1);
6893 n2->_opnds[0] = op_dst;
6894 n2->_opnds[1] = op_src;
6895 n2->_opnds[2] = op_dst;
6896 n2->_bottom_type = _bottom_type;
6897
6898 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6899 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6900
6901 nodes->push(n1);
6902 nodes->push(n2);
6903 %}
6904 %}
6905
6906 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6907 match(Set dst (DecodeN src));
6908 effect(TEMP_DEF dst, TEMP crx);
6909 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6910 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6911 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6912 ins_cost(3 * DEFAULT_COST);
6913
6914 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %}
6915 postalloc_expand %{
6916 loadBaseNode *n1 = new loadBaseNode();
6917 n1->add_req(NULL);
6918 n1->_opnds[0] = op_dst;
6919
6920 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
6921 n_compare->add_req(n_region, n_src);
6922 n_compare->_opnds[0] = op_crx;
6923 n_compare->_opnds[1] = op_src;
6924 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6925
6926 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6927 n2->add_req(n_region, n_src, n1);
6928 n2->_opnds[0] = op_dst;
6929 n2->_opnds[1] = op_src;
6930 n2->_opnds[2] = op_dst;
6931 n2->_bottom_type = _bottom_type;
6932
6933 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6934 n_cond_set->add_req(n_region, n_compare, n2);
6935 n_cond_set->_opnds[0] = op_dst;
6936 n_cond_set->_opnds[1] = op_crx;
6937 n_cond_set->_opnds[2] = op_dst;
6938 n_cond_set->_bottom_type = _bottom_type;
6939
6940 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6941 ra_->set_oop(n_cond_set, true);
6942
6943 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6944 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6945 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6946 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6947
6948 nodes->push(n1);
6949 nodes->push(n_compare);
6950 nodes->push(n2);
6951 nodes->push(n_cond_set);
6952 %}
6953 %}
6954
6955 // src != 0, shift != 0, base != 0
6956 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6957 match(Set dst (DecodeN src));
6958 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6959 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6960 Universe::narrow_oop_shift() != 0 &&
6961 Universe::narrow_oop_base() != 0);
6962 ins_cost(2 * DEFAULT_COST);
6963
6964 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6965 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6966 %}
6967
6968 // Compressed OOPs with narrow_oop_shift == 0.
6969 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6970 match(Set dst (DecodeN src));
6971 predicate(Universe::narrow_oop_shift() == 0);
6972 ins_cost(DEFAULT_COST);
6973
6974 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6975 // variable size, 0 or 4.
6976 ins_encode %{
6977 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6978 __ mr_if_needed($dst$$Register, $src$$Register);
6979 %}
6980 ins_pipe(pipe_class_default);
6981 %}
6982
6983 // Convert compressed oop into int for vectors alignment masking.
6984 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6985 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6986 predicate(Universe::narrow_oop_shift() == 0);
6987 ins_cost(DEFAULT_COST);
6988
6989 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6990 // variable size, 0 or 4.
6991 ins_encode %{
6992 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6993 __ mr_if_needed($dst$$Register, $src$$Register);
6994 %}
6995 ins_pipe(pipe_class_default);
6996 %}
6997
6998 // Convert klass pointer into compressed form.
6999
7000 // Nodes for postalloc expand.
7001
7002 // Shift node for expand.
7003 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
7004 // The match rule is needed to make it a 'MachTypeNode'!
7005 match(Set dst (EncodePKlass src));
7006 predicate(false);
7007
7008 format %{ "SRDI $dst, $src, 3 \t// encode" %}
7009 size(4);
7010 ins_encode %{
7011 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7012 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7013 %}
7014 ins_pipe(pipe_class_default);
7015 %}
7016
7017 // Add node for expand.
7018 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7019 // The match rule is needed to make it a 'MachTypeNode'!
7020 match(Set dst (EncodePKlass (Binary base src)));
7021 predicate(false);
7022
7023 format %{ "SUB $dst, $base, $src \t// encode" %}
7024 size(4);
7025 ins_encode %{
7026 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7027 __ subf($dst$$Register, $base$$Register, $src$$Register);
7028 %}
7029 ins_pipe(pipe_class_default);
7030 %}
7031
7032 // Disjoint narrow oop base.
7033 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7034 match(Set dst (EncodePKlass src));
7035 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7036
7037 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
7038 size(4);
7039 ins_encode %{
7040 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7041 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7042 %}
7043 ins_pipe(pipe_class_default);
7044 %}
7045
7046 // shift != 0, base != 0
7047 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7048 match(Set dst (EncodePKlass (Binary base src)));
7049 predicate(false);
7050
7051 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7052 postalloc_expand %{
7053 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7054 n1->add_req(n_region, n_base, n_src);
7055 n1->_opnds[0] = op_dst;
7056 n1->_opnds[1] = op_base;
7057 n1->_opnds[2] = op_src;
7058 n1->_bottom_type = _bottom_type;
7059
7060 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7061 n2->add_req(n_region, n1);
7062 n2->_opnds[0] = op_dst;
7063 n2->_opnds[1] = op_dst;
7064 n2->_bottom_type = _bottom_type;
7065 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7066 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7067
7068 nodes->push(n1);
7069 nodes->push(n2);
7070 %}
7071 %}
7072
7073 // shift != 0, base != 0
7074 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7075 match(Set dst (EncodePKlass src));
7076 //predicate(Universe::narrow_klass_shift() != 0 &&
7077 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7078
7079 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7080 ins_cost(DEFAULT_COST*2); // Don't count constant.
7081 expand %{
7082 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7083 iRegLdst base;
7084 loadConL_Ex(base, baseImm);
7085 encodePKlass_not_null_Ex(dst, base, src);
7086 %}
7087 %}
7088
7089 // Decode nodes.
7090
7091 // Shift node for expand.
7092 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7093 // The match rule is needed to make it a 'MachTypeNode'!
7094 match(Set dst (DecodeNKlass src));
7095 predicate(false);
7096
7097 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7098 size(4);
7099 ins_encode %{
7100 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7101 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7102 %}
7103 ins_pipe(pipe_class_default);
7104 %}
7105
7106 // Add node for expand.
7107
7108 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7109 // The match rule is needed to make it a 'MachTypeNode'!
7110 match(Set dst (DecodeNKlass (Binary base src)));
7111 predicate(false);
7112
7113 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7114 size(4);
7115 ins_encode %{
7116 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7117 __ add($dst$$Register, $base$$Register, $src$$Register);
7118 %}
7119 ins_pipe(pipe_class_default);
7120 %}
7121
7122 // src != 0, shift != 0, base != 0
7123 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7124 match(Set dst (DecodeNKlass (Binary base src)));
7125 //effect(kill src); // We need a register for the immediate result after shifting.
7126 predicate(false);
7127
7128 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7129 postalloc_expand %{
7130 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7131 n1->add_req(n_region, n_base, n_src);
7132 n1->_opnds[0] = op_dst;
7133 n1->_opnds[1] = op_base;
7134 n1->_opnds[2] = op_src;
7135 n1->_bottom_type = _bottom_type;
7136
7137 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7138 n2->add_req(n_region, n1);
7139 n2->_opnds[0] = op_dst;
7140 n2->_opnds[1] = op_dst;
7141 n2->_bottom_type = _bottom_type;
7142
7143 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7144 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7145
7146 nodes->push(n1);
7147 nodes->push(n2);
7148 %}
7149 %}
7150
7151 // src != 0, shift != 0, base != 0
7152 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7153 match(Set dst (DecodeNKlass src));
7154 // predicate(Universe::narrow_klass_shift() != 0 &&
7155 // Universe::narrow_klass_base() != 0);
7156
7157 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7158
7159 ins_cost(DEFAULT_COST*2); // Don't count constant.
7160 expand %{
7161 // We add first, then we shift. Like this, we can get along with one register less.
7162 // But we have to load the base pre-shifted.
7163 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7164 iRegLdst base;
7165 loadConL_Ex(base, baseImm);
7166 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7167 %}
7168 %}
7169
7170 //----------MemBar Instructions-----------------------------------------------
7171 // Memory barrier flavors
7172
7173 instruct membar_acquire() %{
7174 match(LoadFence);
7175 ins_cost(4*MEMORY_REF_COST);
7176
7177 format %{ "MEMBAR-acquire" %}
7178 size(4);
7179 ins_encode %{
7180 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7181 __ acquire();
7182 %}
7183 ins_pipe(pipe_class_default);
7184 %}
7185
7186 instruct unnecessary_membar_acquire() %{
7187 match(MemBarAcquire);
7188 ins_cost(0);
7189
7190 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7191 size(0);
7192 ins_encode( /*empty*/ );
7193 ins_pipe(pipe_class_default);
7194 %}
7195
7196 instruct membar_acquire_lock() %{
7197 match(MemBarAcquireLock);
7198 ins_cost(0);
7199
7200 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7201 size(0);
7202 ins_encode( /*empty*/ );
7203 ins_pipe(pipe_class_default);
7204 %}
7205
7206 instruct membar_release() %{
7207 match(MemBarRelease);
7208 match(StoreFence);
7209 ins_cost(4*MEMORY_REF_COST);
7210
7211 format %{ "MEMBAR-release" %}
7212 size(4);
7213 ins_encode %{
7214 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7215 __ release();
7216 %}
7217 ins_pipe(pipe_class_default);
7218 %}
7219
7220 instruct membar_storestore() %{
7221 match(MemBarStoreStore);
7222 ins_cost(4*MEMORY_REF_COST);
7223
7224 format %{ "MEMBAR-store-store" %}
7225 size(4);
7226 ins_encode %{
7227 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7228 __ membar(Assembler::StoreStore);
7229 %}
7230 ins_pipe(pipe_class_default);
7231 %}
7232
7233 instruct membar_release_lock() %{
7234 match(MemBarReleaseLock);
7235 ins_cost(0);
7236
7237 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7238 size(0);
7239 ins_encode( /*empty*/ );
7240 ins_pipe(pipe_class_default);
7241 %}
7242
7243 instruct membar_volatile() %{
7244 match(MemBarVolatile);
7245 ins_cost(4*MEMORY_REF_COST);
7246
7247 format %{ "MEMBAR-volatile" %}
7248 size(4);
7249 ins_encode %{
7250 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7251 __ fence();
7252 %}
7253 ins_pipe(pipe_class_default);
7254 %}
7255
7256 // This optimization is wrong on PPC. The following pattern is not supported:
7257 // MemBarVolatile
7258 // ^ ^
7259 // | |
7260 // CtrlProj MemProj
7261 // ^ ^
7262 // | |
7263 // | Load
7264 // |
7265 // MemBarVolatile
7266 //
7267 // The first MemBarVolatile could get optimized out! According to
7268 // Vladimir, this pattern can not occur on Oracle platforms.
7269 // However, it does occur on PPC64 (because of membars in
7270 // inline_unsafe_load_store).
7271 //
7272 // Add this node again if we found a good solution for inline_unsafe_load_store().
7273 // Don't forget to look at the implementation of post_store_load_barrier again,
7274 // we did other fixes in that method.
7275 //instruct unnecessary_membar_volatile() %{
7276 // match(MemBarVolatile);
7277 // predicate(Matcher::post_store_load_barrier(n));
7278 // ins_cost(0);
7279 //
7280 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7281 // size(0);
7282 // ins_encode( /*empty*/ );
7283 // ins_pipe(pipe_class_default);
7284 //%}
7285
7286 instruct membar_CPUOrder() %{
7287 match(MemBarCPUOrder);
7288 ins_cost(0);
7289
7290 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7291 size(0);
7292 ins_encode( /*empty*/ );
7293 ins_pipe(pipe_class_default);
7294 %}
7295
7296 //----------Conditional Move---------------------------------------------------
7297
7298 // Cmove using isel.
7299 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7300 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7301 predicate(VM_Version::has_isel());
7302 ins_cost(DEFAULT_COST);
7303
7304 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7305 size(4);
7306 ins_encode %{
7307 // This is a Power7 instruction for which no machine description
7308 // exists. Anyways, the scheduler should be off on Power7.
7309 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7310 int cc = $cmp$$cmpcode;
7311 __ isel($dst$$Register, $crx$$CondRegister,
7312 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7313 %}
7314 ins_pipe(pipe_class_default);
7315 %}
7316
7317 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7318 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7319 predicate(!VM_Version::has_isel());
7320 ins_cost(DEFAULT_COST+BRANCH_COST);
7321
7322 ins_variable_size_depending_on_alignment(true);
7323
7324 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7325 // Worst case is branch + move + stop, no stop without scheduler
7326 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7327 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7328 ins_pipe(pipe_class_default);
7329 %}
7330
7331 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7332 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7333 ins_cost(DEFAULT_COST+BRANCH_COST);
7334
7335 ins_variable_size_depending_on_alignment(true);
7336
7337 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7338 // Worst case is branch + move + stop, no stop without scheduler
7339 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7340 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7341 ins_pipe(pipe_class_default);
7342 %}
7343
7344 // Cmove using isel.
7345 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7346 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7347 predicate(VM_Version::has_isel());
7348 ins_cost(DEFAULT_COST);
7349
7350 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7351 size(4);
7352 ins_encode %{
7353 // This is a Power7 instruction for which no machine description
7354 // exists. Anyways, the scheduler should be off on Power7.
7355 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7356 int cc = $cmp$$cmpcode;
7357 __ isel($dst$$Register, $crx$$CondRegister,
7358 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7359 %}
7360 ins_pipe(pipe_class_default);
7361 %}
7362
7363 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7364 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7365 predicate(!VM_Version::has_isel());
7366 ins_cost(DEFAULT_COST+BRANCH_COST);
7367
7368 ins_variable_size_depending_on_alignment(true);
7369
7370 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7371 // Worst case is branch + move + stop, no stop without scheduler.
7372 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7373 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7374 ins_pipe(pipe_class_default);
7375 %}
7376
7377 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7378 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7379 ins_cost(DEFAULT_COST+BRANCH_COST);
7380
7381 ins_variable_size_depending_on_alignment(true);
7382
7383 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7384 // Worst case is branch + move + stop, no stop without scheduler.
7385 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7386 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7387 ins_pipe(pipe_class_default);
7388 %}
7389
7390 // Cmove using isel.
7391 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7392 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7393 predicate(VM_Version::has_isel());
7394 ins_cost(DEFAULT_COST);
7395
7396 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7397 size(4);
7398 ins_encode %{
7399 // This is a Power7 instruction for which no machine description
7400 // exists. Anyways, the scheduler should be off on Power7.
7401 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7402 int cc = $cmp$$cmpcode;
7403 __ isel($dst$$Register, $crx$$CondRegister,
7404 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7405 %}
7406 ins_pipe(pipe_class_default);
7407 %}
7408
7409 // Conditional move for RegN. Only cmov(reg, reg).
7410 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7411 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7412 predicate(!VM_Version::has_isel());
7413 ins_cost(DEFAULT_COST+BRANCH_COST);
7414
7415 ins_variable_size_depending_on_alignment(true);
7416
7417 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7418 // Worst case is branch + move + stop, no stop without scheduler.
7419 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7420 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7421 ins_pipe(pipe_class_default);
7422 %}
7423
7424 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7425 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7426 ins_cost(DEFAULT_COST+BRANCH_COST);
7427
7428 ins_variable_size_depending_on_alignment(true);
7429
7430 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7431 // Worst case is branch + move + stop, no stop without scheduler.
7432 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7433 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7434 ins_pipe(pipe_class_default);
7435 %}
7436
7437 // Cmove using isel.
7438 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7439 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7440 predicate(VM_Version::has_isel());
7441 ins_cost(DEFAULT_COST);
7442
7443 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7444 size(4);
7445 ins_encode %{
7446 // This is a Power7 instruction for which no machine description
7447 // exists. Anyways, the scheduler should be off on Power7.
7448 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7449 int cc = $cmp$$cmpcode;
7450 __ isel($dst$$Register, $crx$$CondRegister,
7451 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7452 %}
7453 ins_pipe(pipe_class_default);
7454 %}
7455
7456 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7457 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7458 predicate(!VM_Version::has_isel());
7459 ins_cost(DEFAULT_COST+BRANCH_COST);
7460
7461 ins_variable_size_depending_on_alignment(true);
7462
7463 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7464 // Worst case is branch + move + stop, no stop without scheduler.
7465 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7466 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7467 ins_pipe(pipe_class_default);
7468 %}
7469
7470 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7471 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7472 ins_cost(DEFAULT_COST+BRANCH_COST);
7473
7474 ins_variable_size_depending_on_alignment(true);
7475
7476 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7477 // Worst case is branch + move + stop, no stop without scheduler.
7478 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7479 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7480 ins_pipe(pipe_class_default);
7481 %}
7482
7483 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7484 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7485 ins_cost(DEFAULT_COST+BRANCH_COST);
7486
7487 ins_variable_size_depending_on_alignment(true);
7488
7489 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7490 // Worst case is branch + move + stop, no stop without scheduler.
7491 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7492 ins_encode %{
7493 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7494 Label done;
7495 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7496 // Branch if not (cmp crx).
7497 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7498 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7499 // TODO PPC port __ endgroup_if_needed(_size == 12);
7500 __ bind(done);
7501 %}
7502 ins_pipe(pipe_class_default);
7503 %}
7504
7505 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7506 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7507 ins_cost(DEFAULT_COST+BRANCH_COST);
7508
7509 ins_variable_size_depending_on_alignment(true);
7510
7511 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7512 // Worst case is branch + move + stop, no stop without scheduler.
7513 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7514 ins_encode %{
7515 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7516 Label done;
7517 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7518 // Branch if not (cmp crx).
7519 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7520 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7521 // TODO PPC port __ endgroup_if_needed(_size == 12);
7522 __ bind(done);
7523 %}
7524 ins_pipe(pipe_class_default);
7525 %}
7526
7527 //----------Conditional_store--------------------------------------------------
7528 // Conditional-store of the updated heap-top.
7529 // Used during allocation of the shared heap.
7530 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7531
7532 // As compareAndSwapL, but return flag register instead of boolean value in
7533 // int register.
7534 // Used by sun/misc/AtomicLongCSImpl.java.
7535 // Mem_ptr must be a memory operand, else this node does not get
7536 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7537 // can be rematerialized which leads to errors.
7538 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7539 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7540 effect(TEMP cr0);
7541 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7542 ins_encode %{
7543 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7544 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7545 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7546 noreg, NULL, true);
7547 %}
7548 ins_pipe(pipe_class_default);
7549 %}
7550
7551 // As compareAndSwapP, but return flag register instead of boolean value in
7552 // int register.
7553 // This instruction is matched if UseTLAB is off.
7554 // Mem_ptr must be a memory operand, else this node does not get
7555 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7556 // can be rematerialized which leads to errors.
7557 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7558 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7559 ins_cost(2*MEMORY_REF_COST);
7560
7561 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7562 ins_encode %{
7563 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7564 __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7565 %}
7566 ins_pipe(pipe_class_memory);
7567 %}
7568
7569 // Implement LoadPLocked. Must be ordered against changes of the memory location
7570 // by storePConditional.
7571 // Don't know whether this is ever used.
7572 instruct loadPLocked(iRegPdst dst, memory mem) %{
7573 match(Set dst (LoadPLocked mem));
7574 ins_cost(2*MEMORY_REF_COST);
7575
7576 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %}
7577 size(4);
7578 ins_encode %{
7579 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7580 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7581 %}
7582 ins_pipe(pipe_class_memory);
7583 %}
7584
7585 //----------Compare-And-Swap---------------------------------------------------
7586
7587 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7588 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7589 // matched.
7590
7591 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7592 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7593 effect(TEMP cr0);
7594 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7595 // Variable size: instruction count smaller if regs are disjoint.
7596 ins_encode %{
7597 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7598 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7599 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7600 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7601 $res$$Register, true);
7602 %}
7603 ins_pipe(pipe_class_default);
7604 %}
7605
7606 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7607 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7608 effect(TEMP cr0);
7609 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7610 // Variable size: instruction count smaller if regs are disjoint.
7611 ins_encode %{
7612 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7613 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7614 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7615 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7616 $res$$Register, true);
7617 %}
7618 ins_pipe(pipe_class_default);
7619 %}
7620
7621 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7622 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7623 effect(TEMP cr0);
7624 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7625 // Variable size: instruction count smaller if regs are disjoint.
7626 ins_encode %{
7627 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7628 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7629 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7630 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7631 $res$$Register, NULL, true);
7632 %}
7633 ins_pipe(pipe_class_default);
7634 %}
7635
7636 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7637 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7638 effect(TEMP cr0);
7639 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7640 // Variable size: instruction count smaller if regs are disjoint.
7641 ins_encode %{
7642 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7643 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7644 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7645 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7646 $res$$Register, NULL, true);
7647 %}
7648 ins_pipe(pipe_class_default);
7649 %}
7650
7651 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7652 match(Set res (GetAndAddI mem_ptr src));
7653 effect(TEMP cr0);
7654 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7655 // Variable size: instruction count smaller if regs are disjoint.
7656 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7657 ins_pipe(pipe_class_default);
7658 %}
7659
7660 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7661 match(Set res (GetAndAddL mem_ptr src));
7662 effect(TEMP cr0);
7663 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7664 // Variable size: instruction count smaller if regs are disjoint.
7665 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7666 ins_pipe(pipe_class_default);
7667 %}
7668
7669 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7670 match(Set res (GetAndSetI mem_ptr src));
7671 effect(TEMP cr0);
7672 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7673 // Variable size: instruction count smaller if regs are disjoint.
7674 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7675 ins_pipe(pipe_class_default);
7676 %}
7677
7678 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7679 match(Set res (GetAndSetL mem_ptr src));
7680 effect(TEMP cr0);
7681 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7682 // Variable size: instruction count smaller if regs are disjoint.
7683 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7684 ins_pipe(pipe_class_default);
7685 %}
7686
7687 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7688 match(Set res (GetAndSetP mem_ptr src));
7689 effect(TEMP cr0);
7690 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7691 // Variable size: instruction count smaller if regs are disjoint.
7692 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7693 ins_pipe(pipe_class_default);
7694 %}
7695
7696 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7697 match(Set res (GetAndSetN mem_ptr src));
7698 effect(TEMP cr0);
7699 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7700 // Variable size: instruction count smaller if regs are disjoint.
7701 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7702 ins_pipe(pipe_class_default);
7703 %}
7704
7705 //----------Arithmetic Instructions--------------------------------------------
7706 // Addition Instructions
7707
7708 // Register Addition
7709 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7710 match(Set dst (AddI src1 src2));
7711 format %{ "ADD $dst, $src1, $src2" %}
7712 size(4);
7713 ins_encode %{
7714 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7715 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7716 %}
7717 ins_pipe(pipe_class_default);
7718 %}
7719
7720 // Expand does not work with above instruct. (??)
7721 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7722 // no match-rule
7723 effect(DEF dst, USE src1, USE src2);
7724 format %{ "ADD $dst, $src1, $src2" %}
7725 size(4);
7726 ins_encode %{
7727 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7728 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7729 %}
7730 ins_pipe(pipe_class_default);
7731 %}
7732
7733 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7734 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7735 ins_cost(DEFAULT_COST*3);
7736
7737 expand %{
7738 // FIXME: we should do this in the ideal world.
7739 iRegIdst tmp1;
7740 iRegIdst tmp2;
7741 addI_reg_reg(tmp1, src1, src2);
7742 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7743 addI_reg_reg(dst, tmp1, tmp2);
7744 %}
7745 %}
7746
7747 // Immediate Addition
7748 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7749 match(Set dst (AddI src1 src2));
7750 format %{ "ADDI $dst, $src1, $src2" %}
7751 size(4);
7752 ins_encode %{
7753 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7754 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7755 %}
7756 ins_pipe(pipe_class_default);
7757 %}
7758
7759 // Immediate Addition with 16-bit shifted operand
7760 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7761 match(Set dst (AddI src1 src2));
7762 format %{ "ADDIS $dst, $src1, $src2" %}
7763 size(4);
7764 ins_encode %{
7765 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7766 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7767 %}
7768 ins_pipe(pipe_class_default);
7769 %}
7770
7771 // Long Addition
7772 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7773 match(Set dst (AddL src1 src2));
7774 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7775 size(4);
7776 ins_encode %{
7777 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7778 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7779 %}
7780 ins_pipe(pipe_class_default);
7781 %}
7782
7783 // Expand does not work with above instruct. (??)
7784 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7785 // no match-rule
7786 effect(DEF dst, USE src1, USE src2);
7787 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7788 size(4);
7789 ins_encode %{
7790 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7791 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7792 %}
7793 ins_pipe(pipe_class_default);
7794 %}
7795
7796 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7797 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7798 ins_cost(DEFAULT_COST*3);
7799
7800 expand %{
7801 // FIXME: we should do this in the ideal world.
7802 iRegLdst tmp1;
7803 iRegLdst tmp2;
7804 addL_reg_reg(tmp1, src1, src2);
7805 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7806 addL_reg_reg(dst, tmp1, tmp2);
7807 %}
7808 %}
7809
7810 // AddL + ConvL2I.
7811 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7812 match(Set dst (ConvL2I (AddL src1 src2)));
7813
7814 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7815 size(4);
7816 ins_encode %{
7817 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7818 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7819 %}
7820 ins_pipe(pipe_class_default);
7821 %}
7822
7823 // No constant pool entries required.
7824 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7825 match(Set dst (AddL src1 src2));
7826
7827 format %{ "ADDI $dst, $src1, $src2" %}
7828 size(4);
7829 ins_encode %{
7830 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7831 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7832 %}
7833 ins_pipe(pipe_class_default);
7834 %}
7835
7836 // Long Immediate Addition with 16-bit shifted operand.
7837 // No constant pool entries required.
7838 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7839 match(Set dst (AddL src1 src2));
7840
7841 format %{ "ADDIS $dst, $src1, $src2" %}
7842 size(4);
7843 ins_encode %{
7844 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7845 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7846 %}
7847 ins_pipe(pipe_class_default);
7848 %}
7849
7850 // Pointer Register Addition
7851 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7852 match(Set dst (AddP src1 src2));
7853 format %{ "ADD $dst, $src1, $src2" %}
7854 size(4);
7855 ins_encode %{
7856 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7857 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7858 %}
7859 ins_pipe(pipe_class_default);
7860 %}
7861
7862 // Pointer Immediate Addition
7863 // No constant pool entries required.
7864 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7865 match(Set dst (AddP src1 src2));
7866
7867 format %{ "ADDI $dst, $src1, $src2" %}
7868 size(4);
7869 ins_encode %{
7870 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7871 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7872 %}
7873 ins_pipe(pipe_class_default);
7874 %}
7875
7876 // Pointer Immediate Addition with 16-bit shifted operand.
7877 // No constant pool entries required.
7878 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7879 match(Set dst (AddP src1 src2));
7880
7881 format %{ "ADDIS $dst, $src1, $src2" %}
7882 size(4);
7883 ins_encode %{
7884 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7885 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7886 %}
7887 ins_pipe(pipe_class_default);
7888 %}
7889
7890 //---------------------
7891 // Subtraction Instructions
7892
7893 // Register Subtraction
7894 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7895 match(Set dst (SubI src1 src2));
7896 format %{ "SUBF $dst, $src2, $src1" %}
7897 size(4);
7898 ins_encode %{
7899 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7900 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7901 %}
7902 ins_pipe(pipe_class_default);
7903 %}
7904
7905 // Immediate Subtraction
7906 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7907 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7908
7909 // SubI from constant (using subfic).
7910 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7911 match(Set dst (SubI src1 src2));
7912 format %{ "SUBI $dst, $src1, $src2" %}
7913
7914 size(4);
7915 ins_encode %{
7916 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7917 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7918 %}
7919 ins_pipe(pipe_class_default);
7920 %}
7921
7922 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7923 // positive integers and 0xF...F for negative ones.
7924 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7925 // no match-rule, false predicate
7926 effect(DEF dst, USE src);
7927 predicate(false);
7928
7929 format %{ "SRAWI $dst, $src, #31" %}
7930 size(4);
7931 ins_encode %{
7932 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7933 __ srawi($dst$$Register, $src$$Register, 0x1f);
7934 %}
7935 ins_pipe(pipe_class_default);
7936 %}
7937
7938 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7939 match(Set dst (AbsI src));
7940 ins_cost(DEFAULT_COST*3);
7941
7942 expand %{
7943 iRegIdst tmp1;
7944 iRegIdst tmp2;
7945 signmask32I_regI(tmp1, src);
7946 xorI_reg_reg(tmp2, tmp1, src);
7947 subI_reg_reg(dst, tmp2, tmp1);
7948 %}
7949 %}
7950
7951 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7952 match(Set dst (SubI zero src2));
7953 format %{ "NEG $dst, $src2" %}
7954 size(4);
7955 ins_encode %{
7956 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7957 __ neg($dst$$Register, $src2$$Register);
7958 %}
7959 ins_pipe(pipe_class_default);
7960 %}
7961
7962 // Long subtraction
7963 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7964 match(Set dst (SubL src1 src2));
7965 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7966 size(4);
7967 ins_encode %{
7968 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7969 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7970 %}
7971 ins_pipe(pipe_class_default);
7972 %}
7973
7974 // SubL + convL2I.
7975 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7976 match(Set dst (ConvL2I (SubL src1 src2)));
7977
7978 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7979 size(4);
7980 ins_encode %{
7981 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7982 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7983 %}
7984 ins_pipe(pipe_class_default);
7985 %}
7986
7987 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7988 // positive longs and 0xF...F for negative ones.
7989 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7990 // no match-rule, false predicate
7991 effect(DEF dst, USE src);
7992 predicate(false);
7993
7994 format %{ "SRADI $dst, $src, #63" %}
7995 size(4);
7996 ins_encode %{
7997 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7998 __ sradi($dst$$Register, $src$$Register, 0x3f);
7999 %}
8000 ins_pipe(pipe_class_default);
8001 %}
8002
8003 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8004 // positive longs and 0xF...F for negative ones.
8005 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
8006 // no match-rule, false predicate
8007 effect(DEF dst, USE src);
8008 predicate(false);
8009
8010 format %{ "SRADI $dst, $src, #63" %}
8011 size(4);
8012 ins_encode %{
8013 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8014 __ sradi($dst$$Register, $src$$Register, 0x3f);
8015 %}
8016 ins_pipe(pipe_class_default);
8017 %}
8018
8019 // Long negation
8020 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8021 match(Set dst (SubL zero src2));
8022 format %{ "NEG $dst, $src2 \t// long" %}
8023 size(4);
8024 ins_encode %{
8025 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8026 __ neg($dst$$Register, $src2$$Register);
8027 %}
8028 ins_pipe(pipe_class_default);
8029 %}
8030
8031 // NegL + ConvL2I.
8032 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8033 match(Set dst (ConvL2I (SubL zero src2)));
8034
8035 format %{ "NEG $dst, $src2 \t// long + l2i" %}
8036 size(4);
8037 ins_encode %{
8038 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8039 __ neg($dst$$Register, $src2$$Register);
8040 %}
8041 ins_pipe(pipe_class_default);
8042 %}
8043
8044 // Multiplication Instructions
8045 // Integer Multiplication
8046
8047 // Register Multiplication
8048 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8049 match(Set dst (MulI src1 src2));
8050 ins_cost(DEFAULT_COST);
8051
8052 format %{ "MULLW $dst, $src1, $src2" %}
8053 size(4);
8054 ins_encode %{
8055 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8056 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8057 %}
8058 ins_pipe(pipe_class_default);
8059 %}
8060
8061 // Immediate Multiplication
8062 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8063 match(Set dst (MulI src1 src2));
8064 ins_cost(DEFAULT_COST);
8065
8066 format %{ "MULLI $dst, $src1, $src2" %}
8067 size(4);
8068 ins_encode %{
8069 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8070 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8071 %}
8072 ins_pipe(pipe_class_default);
8073 %}
8074
8075 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8076 match(Set dst (MulL src1 src2));
8077 ins_cost(DEFAULT_COST);
8078
8079 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8080 size(4);
8081 ins_encode %{
8082 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8083 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8084 %}
8085 ins_pipe(pipe_class_default);
8086 %}
8087
8088 // Multiply high for optimized long division by constant.
8089 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8090 match(Set dst (MulHiL src1 src2));
8091 ins_cost(DEFAULT_COST);
8092
8093 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8094 size(4);
8095 ins_encode %{
8096 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8097 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8098 %}
8099 ins_pipe(pipe_class_default);
8100 %}
8101
8102 // Immediate Multiplication
8103 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8104 match(Set dst (MulL src1 src2));
8105 ins_cost(DEFAULT_COST);
8106
8107 format %{ "MULLI $dst, $src1, $src2" %}
8108 size(4);
8109 ins_encode %{
8110 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8111 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8112 %}
8113 ins_pipe(pipe_class_default);
8114 %}
8115
8116 // Integer Division with Immediate -1: Negate.
8117 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8118 match(Set dst (DivI src1 src2));
8119 ins_cost(DEFAULT_COST);
8120
8121 format %{ "NEG $dst, $src1 \t// /-1" %}
8122 size(4);
8123 ins_encode %{
8124 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8125 __ neg($dst$$Register, $src1$$Register);
8126 %}
8127 ins_pipe(pipe_class_default);
8128 %}
8129
8130 // Integer Division with constant, but not -1.
8131 // We should be able to improve this by checking the type of src2.
8132 // It might well be that src2 is known to be positive.
8133 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8134 match(Set dst (DivI src1 src2));
8135 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8136 ins_cost(2*DEFAULT_COST);
8137
8138 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8139 size(4);
8140 ins_encode %{
8141 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8142 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8143 %}
8144 ins_pipe(pipe_class_default);
8145 %}
8146
8147 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8148 effect(USE_DEF dst, USE src1, USE crx);
8149 predicate(false);
8150
8151 ins_variable_size_depending_on_alignment(true);
8152
8153 format %{ "CMOVE $dst, neg($src1), $crx" %}
8154 // Worst case is branch + move + stop, no stop without scheduler.
8155 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8156 ins_encode %{
8157 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8158 Label done;
8159 __ bne($crx$$CondRegister, done);
8160 __ neg($dst$$Register, $src1$$Register);
8161 // TODO PPC port __ endgroup_if_needed(_size == 12);
8162 __ bind(done);
8163 %}
8164 ins_pipe(pipe_class_default);
8165 %}
8166
8167 // Integer Division with Registers not containing constants.
8168 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8169 match(Set dst (DivI src1 src2));
8170 ins_cost(10*DEFAULT_COST);
8171
8172 expand %{
8173 immI16 imm %{ (int)-1 %}
8174 flagsReg tmp1;
8175 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8176 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8177 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8178 %}
8179 %}
8180
8181 // Long Division with Immediate -1: Negate.
8182 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8183 match(Set dst (DivL src1 src2));
8184 ins_cost(DEFAULT_COST);
8185
8186 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8187 size(4);
8188 ins_encode %{
8189 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8190 __ neg($dst$$Register, $src1$$Register);
8191 %}
8192 ins_pipe(pipe_class_default);
8193 %}
8194
8195 // Long Division with constant, but not -1.
8196 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8197 match(Set dst (DivL src1 src2));
8198 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8199 ins_cost(2*DEFAULT_COST);
8200
8201 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8202 size(4);
8203 ins_encode %{
8204 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8205 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8206 %}
8207 ins_pipe(pipe_class_default);
8208 %}
8209
8210 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8211 effect(USE_DEF dst, USE src1, USE crx);
8212 predicate(false);
8213
8214 ins_variable_size_depending_on_alignment(true);
8215
8216 format %{ "CMOVE $dst, neg($src1), $crx" %}
8217 // Worst case is branch + move + stop, no stop without scheduler.
8218 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8219 ins_encode %{
8220 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8221 Label done;
8222 __ bne($crx$$CondRegister, done);
8223 __ neg($dst$$Register, $src1$$Register);
8224 // TODO PPC port __ endgroup_if_needed(_size == 12);
8225 __ bind(done);
8226 %}
8227 ins_pipe(pipe_class_default);
8228 %}
8229
8230 // Long Division with Registers not containing constants.
8231 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8232 match(Set dst (DivL src1 src2));
8233 ins_cost(10*DEFAULT_COST);
8234
8235 expand %{
8236 immL16 imm %{ (int)-1 %}
8237 flagsReg tmp1;
8238 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8239 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8240 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8241 %}
8242 %}
8243
8244 // Integer Remainder with registers.
8245 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8246 match(Set dst (ModI src1 src2));
8247 ins_cost(10*DEFAULT_COST);
8248
8249 expand %{
8250 immI16 imm %{ (int)-1 %}
8251 flagsReg tmp1;
8252 iRegIdst tmp2;
8253 iRegIdst tmp3;
8254 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8255 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8256 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8257 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8258 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8259 %}
8260 %}
8261
8262 // Long Remainder with registers
8263 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8264 match(Set dst (ModL src1 src2));
8265 ins_cost(10*DEFAULT_COST);
8266
8267 expand %{
8268 immL16 imm %{ (int)-1 %}
8269 flagsReg tmp1;
8270 iRegLdst tmp2;
8271 iRegLdst tmp3;
8272 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8273 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8274 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8275 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8276 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8277 %}
8278 %}
8279
8280 // Integer Shift Instructions
8281
8282 // Register Shift Left
8283
8284 // Clear all but the lowest #mask bits.
8285 // Used to normalize shift amounts in registers.
8286 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8287 // no match-rule, false predicate
8288 effect(DEF dst, USE src, USE mask);
8289 predicate(false);
8290
8291 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8292 size(4);
8293 ins_encode %{
8294 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8295 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8296 %}
8297 ins_pipe(pipe_class_default);
8298 %}
8299
8300 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8301 // no match-rule, false predicate
8302 effect(DEF dst, USE src1, USE src2);
8303 predicate(false);
8304
8305 format %{ "SLW $dst, $src1, $src2" %}
8306 size(4);
8307 ins_encode %{
8308 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8309 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8310 %}
8311 ins_pipe(pipe_class_default);
8312 %}
8313
8314 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8315 match(Set dst (LShiftI src1 src2));
8316 ins_cost(DEFAULT_COST*2);
8317 expand %{
8318 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8319 iRegIdst tmpI;
8320 maskI_reg_imm(tmpI, src2, mask);
8321 lShiftI_reg_reg(dst, src1, tmpI);
8322 %}
8323 %}
8324
8325 // Register Shift Left Immediate
8326 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8327 match(Set dst (LShiftI src1 src2));
8328
8329 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8330 size(4);
8331 ins_encode %{
8332 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8333 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8334 %}
8335 ins_pipe(pipe_class_default);
8336 %}
8337
8338 // AndI with negpow2-constant + LShiftI
8339 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8340 match(Set dst (LShiftI (AndI src1 src2) src3));
8341 predicate(UseRotateAndMaskInstructionsPPC64);
8342
8343 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8344 size(4);
8345 ins_encode %{
8346 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8347 long src2 = $src2$$constant;
8348 long src3 = $src3$$constant;
8349 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8350 if (maskbits >= 32) {
8351 __ li($dst$$Register, 0); // addi
8352 } else {
8353 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8354 }
8355 %}
8356 ins_pipe(pipe_class_default);
8357 %}
8358
8359 // RShiftI + AndI with negpow2-constant + LShiftI
8360 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8361 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8362 predicate(UseRotateAndMaskInstructionsPPC64);
8363
8364 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8365 size(4);
8366 ins_encode %{
8367 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8368 long src2 = $src2$$constant;
8369 long src3 = $src3$$constant;
8370 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8371 if (maskbits >= 32) {
8372 __ li($dst$$Register, 0); // addi
8373 } else {
8374 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8375 }
8376 %}
8377 ins_pipe(pipe_class_default);
8378 %}
8379
8380 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8381 // no match-rule, false predicate
8382 effect(DEF dst, USE src1, USE src2);
8383 predicate(false);
8384
8385 format %{ "SLD $dst, $src1, $src2" %}
8386 size(4);
8387 ins_encode %{
8388 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8389 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8390 %}
8391 ins_pipe(pipe_class_default);
8392 %}
8393
8394 // Register Shift Left
8395 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8396 match(Set dst (LShiftL src1 src2));
8397 ins_cost(DEFAULT_COST*2);
8398 expand %{
8399 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8400 iRegIdst tmpI;
8401 maskI_reg_imm(tmpI, src2, mask);
8402 lShiftL_regL_regI(dst, src1, tmpI);
8403 %}
8404 %}
8405
8406 // Register Shift Left Immediate
8407 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8408 match(Set dst (LShiftL src1 src2));
8409 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8410 size(4);
8411 ins_encode %{
8412 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8413 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8414 %}
8415 ins_pipe(pipe_class_default);
8416 %}
8417
8418 // If we shift more than 32 bits, we need not convert I2L.
8419 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8420 match(Set dst (LShiftL (ConvI2L src1) src2));
8421 ins_cost(DEFAULT_COST);
8422
8423 size(4);
8424 format %{ "SLDI $dst, i2l($src1), $src2" %}
8425 ins_encode %{
8426 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8427 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8428 %}
8429 ins_pipe(pipe_class_default);
8430 %}
8431
8432 // Shift a postivie int to the left.
8433 // Clrlsldi clears the upper 32 bits and shifts.
8434 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8435 match(Set dst (LShiftL (ConvI2L src1) src2));
8436 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8437
8438 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8439 size(4);
8440 ins_encode %{
8441 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8442 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8443 %}
8444 ins_pipe(pipe_class_default);
8445 %}
8446
8447 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8448 // no match-rule, false predicate
8449 effect(DEF dst, USE src1, USE src2);
8450 predicate(false);
8451
8452 format %{ "SRAW $dst, $src1, $src2" %}
8453 size(4);
8454 ins_encode %{
8455 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8456 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8457 %}
8458 ins_pipe(pipe_class_default);
8459 %}
8460
8461 // Register Arithmetic Shift Right
8462 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8463 match(Set dst (RShiftI src1 src2));
8464 ins_cost(DEFAULT_COST*2);
8465 expand %{
8466 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8467 iRegIdst tmpI;
8468 maskI_reg_imm(tmpI, src2, mask);
8469 arShiftI_reg_reg(dst, src1, tmpI);
8470 %}
8471 %}
8472
8473 // Register Arithmetic Shift Right Immediate
8474 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8475 match(Set dst (RShiftI src1 src2));
8476
8477 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8478 size(4);
8479 ins_encode %{
8480 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8481 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8482 %}
8483 ins_pipe(pipe_class_default);
8484 %}
8485
8486 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8487 // no match-rule, false predicate
8488 effect(DEF dst, USE src1, USE src2);
8489 predicate(false);
8490
8491 format %{ "SRAD $dst, $src1, $src2" %}
8492 size(4);
8493 ins_encode %{
8494 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8495 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8496 %}
8497 ins_pipe(pipe_class_default);
8498 %}
8499
8500 // Register Shift Right Arithmetic Long
8501 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8502 match(Set dst (RShiftL src1 src2));
8503 ins_cost(DEFAULT_COST*2);
8504
8505 expand %{
8506 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8507 iRegIdst tmpI;
8508 maskI_reg_imm(tmpI, src2, mask);
8509 arShiftL_regL_regI(dst, src1, tmpI);
8510 %}
8511 %}
8512
8513 // Register Shift Right Immediate
8514 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8515 match(Set dst (RShiftL src1 src2));
8516
8517 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8518 size(4);
8519 ins_encode %{
8520 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8521 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8522 %}
8523 ins_pipe(pipe_class_default);
8524 %}
8525
8526 // RShiftL + ConvL2I
8527 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8528 match(Set dst (ConvL2I (RShiftL src1 src2)));
8529
8530 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8531 size(4);
8532 ins_encode %{
8533 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8534 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8535 %}
8536 ins_pipe(pipe_class_default);
8537 %}
8538
8539 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8540 // no match-rule, false predicate
8541 effect(DEF dst, USE src1, USE src2);
8542 predicate(false);
8543
8544 format %{ "SRW $dst, $src1, $src2" %}
8545 size(4);
8546 ins_encode %{
8547 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8548 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8549 %}
8550 ins_pipe(pipe_class_default);
8551 %}
8552
8553 // Register Shift Right
8554 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8555 match(Set dst (URShiftI src1 src2));
8556 ins_cost(DEFAULT_COST*2);
8557
8558 expand %{
8559 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8560 iRegIdst tmpI;
8561 maskI_reg_imm(tmpI, src2, mask);
8562 urShiftI_reg_reg(dst, src1, tmpI);
8563 %}
8564 %}
8565
8566 // Register Shift Right Immediate
8567 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8568 match(Set dst (URShiftI src1 src2));
8569
8570 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8571 size(4);
8572 ins_encode %{
8573 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8574 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8575 %}
8576 ins_pipe(pipe_class_default);
8577 %}
8578
8579 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8580 // no match-rule, false predicate
8581 effect(DEF dst, USE src1, USE src2);
8582 predicate(false);
8583
8584 format %{ "SRD $dst, $src1, $src2" %}
8585 size(4);
8586 ins_encode %{
8587 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8588 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8589 %}
8590 ins_pipe(pipe_class_default);
8591 %}
8592
8593 // Register Shift Right
8594 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8595 match(Set dst (URShiftL src1 src2));
8596 ins_cost(DEFAULT_COST*2);
8597
8598 expand %{
8599 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8600 iRegIdst tmpI;
8601 maskI_reg_imm(tmpI, src2, mask);
8602 urShiftL_regL_regI(dst, src1, tmpI);
8603 %}
8604 %}
8605
8606 // Register Shift Right Immediate
8607 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8608 match(Set dst (URShiftL src1 src2));
8609
8610 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8611 size(4);
8612 ins_encode %{
8613 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8614 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8615 %}
8616 ins_pipe(pipe_class_default);
8617 %}
8618
8619 // URShiftL + ConvL2I.
8620 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8621 match(Set dst (ConvL2I (URShiftL src1 src2)));
8622
8623 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8624 size(4);
8625 ins_encode %{
8626 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8627 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8628 %}
8629 ins_pipe(pipe_class_default);
8630 %}
8631
8632 // Register Shift Right Immediate with a CastP2X
8633 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8634 match(Set dst (URShiftL (CastP2X src1) src2));
8635
8636 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8637 size(4);
8638 ins_encode %{
8639 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8640 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8641 %}
8642 ins_pipe(pipe_class_default);
8643 %}
8644
8645 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8646 match(Set dst (ConvL2I (ConvI2L src)));
8647
8648 format %{ "EXTSW $dst, $src \t// int->int" %}
8649 size(4);
8650 ins_encode %{
8651 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8652 __ extsw($dst$$Register, $src$$Register);
8653 %}
8654 ins_pipe(pipe_class_default);
8655 %}
8656
8657 //----------Rotate Instructions------------------------------------------------
8658
8659 // Rotate Left by 8-bit immediate
8660 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8661 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8662 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8663
8664 format %{ "ROTLWI $dst, $src, $lshift" %}
8665 size(4);
8666 ins_encode %{
8667 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8668 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8669 %}
8670 ins_pipe(pipe_class_default);
8671 %}
8672
8673 // Rotate Right by 8-bit immediate
8674 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8675 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8676 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8677
8678 format %{ "ROTRWI $dst, $rshift" %}
8679 size(4);
8680 ins_encode %{
8681 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8682 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8683 %}
8684 ins_pipe(pipe_class_default);
8685 %}
8686
8687 //----------Floating Point Arithmetic Instructions-----------------------------
8688
8689 // Add float single precision
8690 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8691 match(Set dst (AddF src1 src2));
8692
8693 format %{ "FADDS $dst, $src1, $src2" %}
8694 size(4);
8695 ins_encode %{
8696 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8697 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8698 %}
8699 ins_pipe(pipe_class_default);
8700 %}
8701
8702 // Add float double precision
8703 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8704 match(Set dst (AddD src1 src2));
8705
8706 format %{ "FADD $dst, $src1, $src2" %}
8707 size(4);
8708 ins_encode %{
8709 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8710 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8711 %}
8712 ins_pipe(pipe_class_default);
8713 %}
8714
8715 // Sub float single precision
8716 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8717 match(Set dst (SubF src1 src2));
8718
8719 format %{ "FSUBS $dst, $src1, $src2" %}
8720 size(4);
8721 ins_encode %{
8722 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8723 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8724 %}
8725 ins_pipe(pipe_class_default);
8726 %}
8727
8728 // Sub float double precision
8729 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8730 match(Set dst (SubD src1 src2));
8731 format %{ "FSUB $dst, $src1, $src2" %}
8732 size(4);
8733 ins_encode %{
8734 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8735 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8736 %}
8737 ins_pipe(pipe_class_default);
8738 %}
8739
8740 // Mul float single precision
8741 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8742 match(Set dst (MulF src1 src2));
8743 format %{ "FMULS $dst, $src1, $src2" %}
8744 size(4);
8745 ins_encode %{
8746 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8747 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8748 %}
8749 ins_pipe(pipe_class_default);
8750 %}
8751
8752 // Mul float double precision
8753 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8754 match(Set dst (MulD src1 src2));
8755 format %{ "FMUL $dst, $src1, $src2" %}
8756 size(4);
8757 ins_encode %{
8758 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8759 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8760 %}
8761 ins_pipe(pipe_class_default);
8762 %}
8763
8764 // Div float single precision
8765 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8766 match(Set dst (DivF src1 src2));
8767 format %{ "FDIVS $dst, $src1, $src2" %}
8768 size(4);
8769 ins_encode %{
8770 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8771 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8772 %}
8773 ins_pipe(pipe_class_default);
8774 %}
8775
8776 // Div float double precision
8777 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8778 match(Set dst (DivD src1 src2));
8779 format %{ "FDIV $dst, $src1, $src2" %}
8780 size(4);
8781 ins_encode %{
8782 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8783 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8784 %}
8785 ins_pipe(pipe_class_default);
8786 %}
8787
8788 // Absolute float single precision
8789 instruct absF_reg(regF dst, regF src) %{
8790 match(Set dst (AbsF src));
8791 format %{ "FABS $dst, $src \t// float" %}
8792 size(4);
8793 ins_encode %{
8794 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8795 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8796 %}
8797 ins_pipe(pipe_class_default);
8798 %}
8799
8800 // Absolute float double precision
8801 instruct absD_reg(regD dst, regD src) %{
8802 match(Set dst (AbsD src));
8803 format %{ "FABS $dst, $src \t// double" %}
8804 size(4);
8805 ins_encode %{
8806 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8807 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8808 %}
8809 ins_pipe(pipe_class_default);
8810 %}
8811
8812 instruct negF_reg(regF dst, regF src) %{
8813 match(Set dst (NegF src));
8814 format %{ "FNEG $dst, $src \t// float" %}
8815 size(4);
8816 ins_encode %{
8817 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8818 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8819 %}
8820 ins_pipe(pipe_class_default);
8821 %}
8822
8823 instruct negD_reg(regD dst, regD src) %{
8824 match(Set dst (NegD src));
8825 format %{ "FNEG $dst, $src \t// double" %}
8826 size(4);
8827 ins_encode %{
8828 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8829 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8830 %}
8831 ins_pipe(pipe_class_default);
8832 %}
8833
8834 // AbsF + NegF.
8835 instruct negF_absF_reg(regF dst, regF src) %{
8836 match(Set dst (NegF (AbsF src)));
8837 format %{ "FNABS $dst, $src \t// float" %}
8838 size(4);
8839 ins_encode %{
8840 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8841 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8842 %}
8843 ins_pipe(pipe_class_default);
8844 %}
8845
8846 // AbsD + NegD.
8847 instruct negD_absD_reg(regD dst, regD src) %{
8848 match(Set dst (NegD (AbsD src)));
8849 format %{ "FNABS $dst, $src \t// double" %}
8850 size(4);
8851 ins_encode %{
8852 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8853 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8854 %}
8855 ins_pipe(pipe_class_default);
8856 %}
8857
8858 // VM_Version::has_fsqrt() decides if this node will be used.
8859 // Sqrt float double precision
8860 instruct sqrtD_reg(regD dst, regD src) %{
8861 match(Set dst (SqrtD src));
8862 format %{ "FSQRT $dst, $src" %}
8863 size(4);
8864 ins_encode %{
8865 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8866 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8867 %}
8868 ins_pipe(pipe_class_default);
8869 %}
8870
8871 // Single-precision sqrt.
8872 instruct sqrtF_reg(regF dst, regF src) %{
8873 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8874 predicate(VM_Version::has_fsqrts());
8875 ins_cost(DEFAULT_COST);
8876
8877 format %{ "FSQRTS $dst, $src" %}
8878 size(4);
8879 ins_encode %{
8880 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8881 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8882 %}
8883 ins_pipe(pipe_class_default);
8884 %}
8885
8886 instruct roundDouble_nop(regD dst) %{
8887 match(Set dst (RoundDouble dst));
8888 ins_cost(0);
8889
8890 format %{ " -- \t// RoundDouble not needed - empty" %}
8891 size(0);
8892 // PPC results are already "rounded" (i.e., normal-format IEEE).
8893 ins_encode( /*empty*/ );
8894 ins_pipe(pipe_class_default);
8895 %}
8896
8897 instruct roundFloat_nop(regF dst) %{
8898 match(Set dst (RoundFloat dst));
8899 ins_cost(0);
8900
8901 format %{ " -- \t// RoundFloat not needed - empty" %}
8902 size(0);
8903 // PPC results are already "rounded" (i.e., normal-format IEEE).
8904 ins_encode( /*empty*/ );
8905 ins_pipe(pipe_class_default);
8906 %}
8907
8908 //----------Logical Instructions-----------------------------------------------
8909
8910 // And Instructions
8911
8912 // Register And
8913 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8914 match(Set dst (AndI src1 src2));
8915 format %{ "AND $dst, $src1, $src2" %}
8916 size(4);
8917 ins_encode %{
8918 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8919 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8920 %}
8921 ins_pipe(pipe_class_default);
8922 %}
8923
8924 // Immediate And
8925 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8926 match(Set dst (AndI src1 src2));
8927 effect(KILL cr0);
8928
8929 format %{ "ANDI $dst, $src1, $src2" %}
8930 size(4);
8931 ins_encode %{
8932 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8933 // FIXME: avoid andi_ ?
8934 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8935 %}
8936 ins_pipe(pipe_class_default);
8937 %}
8938
8939 // Immediate And where the immediate is a negative power of 2.
8940 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8941 match(Set dst (AndI src1 src2));
8942 format %{ "ANDWI $dst, $src1, $src2" %}
8943 size(4);
8944 ins_encode %{
8945 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8946 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8947 %}
8948 ins_pipe(pipe_class_default);
8949 %}
8950
8951 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8952 match(Set dst (AndI src1 src2));
8953 format %{ "ANDWI $dst, $src1, $src2" %}
8954 size(4);
8955 ins_encode %{
8956 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8957 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8958 %}
8959 ins_pipe(pipe_class_default);
8960 %}
8961
8962 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8963 match(Set dst (AndI src1 src2));
8964 predicate(UseRotateAndMaskInstructionsPPC64);
8965 format %{ "ANDWI $dst, $src1, $src2" %}
8966 size(4);
8967 ins_encode %{
8968 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8969 __ rlwinm($dst$$Register, $src1$$Register, 0,
8970 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8971 %}
8972 ins_pipe(pipe_class_default);
8973 %}
8974
8975 // Register And Long
8976 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8977 match(Set dst (AndL src1 src2));
8978 ins_cost(DEFAULT_COST);
8979
8980 format %{ "AND $dst, $src1, $src2 \t// long" %}
8981 size(4);
8982 ins_encode %{
8983 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8984 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8985 %}
8986 ins_pipe(pipe_class_default);
8987 %}
8988
8989 // Immediate And long
8990 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8991 match(Set dst (AndL src1 src2));
8992 effect(KILL cr0);
8993
8994 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8995 size(4);
8996 ins_encode %{
8997 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8998 // FIXME: avoid andi_ ?
8999 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9000 %}
9001 ins_pipe(pipe_class_default);
9002 %}
9003
9004 // Immediate And Long where the immediate is a negative power of 2.
9005 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
9006 match(Set dst (AndL src1 src2));
9007 format %{ "ANDDI $dst, $src1, $src2" %}
9008 size(4);
9009 ins_encode %{
9010 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9011 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
9012 %}
9013 ins_pipe(pipe_class_default);
9014 %}
9015
9016 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9017 match(Set dst (AndL src1 src2));
9018 format %{ "ANDDI $dst, $src1, $src2" %}
9019 size(4);
9020 ins_encode %{
9021 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9022 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9023 %}
9024 ins_pipe(pipe_class_default);
9025 %}
9026
9027 // AndL + ConvL2I.
9028 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9029 match(Set dst (ConvL2I (AndL src1 src2)));
9030 ins_cost(DEFAULT_COST);
9031
9032 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
9033 size(4);
9034 ins_encode %{
9035 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9036 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9037 %}
9038 ins_pipe(pipe_class_default);
9039 %}
9040
9041 // Or Instructions
9042
9043 // Register Or
9044 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9045 match(Set dst (OrI src1 src2));
9046 format %{ "OR $dst, $src1, $src2" %}
9047 size(4);
9048 ins_encode %{
9049 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9050 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9051 %}
9052 ins_pipe(pipe_class_default);
9053 %}
9054
9055 // Expand does not work with above instruct. (??)
9056 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9057 // no match-rule
9058 effect(DEF dst, USE src1, USE src2);
9059 format %{ "OR $dst, $src1, $src2" %}
9060 size(4);
9061 ins_encode %{
9062 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9063 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9064 %}
9065 ins_pipe(pipe_class_default);
9066 %}
9067
9068 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9069 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9070 ins_cost(DEFAULT_COST*3);
9071
9072 expand %{
9073 // FIXME: we should do this in the ideal world.
9074 iRegIdst tmp1;
9075 iRegIdst tmp2;
9076 orI_reg_reg(tmp1, src1, src2);
9077 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9078 orI_reg_reg(dst, tmp1, tmp2);
9079 %}
9080 %}
9081
9082 // Immediate Or
9083 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9084 match(Set dst (OrI src1 src2));
9085 format %{ "ORI $dst, $src1, $src2" %}
9086 size(4);
9087 ins_encode %{
9088 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9089 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9090 %}
9091 ins_pipe(pipe_class_default);
9092 %}
9093
9094 // Register Or Long
9095 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9096 match(Set dst (OrL src1 src2));
9097 ins_cost(DEFAULT_COST);
9098
9099 size(4);
9100 format %{ "OR $dst, $src1, $src2 \t// long" %}
9101 ins_encode %{
9102 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9103 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9104 %}
9105 ins_pipe(pipe_class_default);
9106 %}
9107
9108 // OrL + ConvL2I.
9109 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9110 match(Set dst (ConvL2I (OrL src1 src2)));
9111 ins_cost(DEFAULT_COST);
9112
9113 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9114 size(4);
9115 ins_encode %{
9116 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9117 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9118 %}
9119 ins_pipe(pipe_class_default);
9120 %}
9121
9122 // Immediate Or long
9123 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9124 match(Set dst (OrL src1 con));
9125 ins_cost(DEFAULT_COST);
9126
9127 format %{ "ORI $dst, $src1, $con \t// long" %}
9128 size(4);
9129 ins_encode %{
9130 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9131 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9132 %}
9133 ins_pipe(pipe_class_default);
9134 %}
9135
9136 // Xor Instructions
9137
9138 // Register Xor
9139 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9140 match(Set dst (XorI src1 src2));
9141 format %{ "XOR $dst, $src1, $src2" %}
9142 size(4);
9143 ins_encode %{
9144 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9145 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9146 %}
9147 ins_pipe(pipe_class_default);
9148 %}
9149
9150 // Expand does not work with above instruct. (??)
9151 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9152 // no match-rule
9153 effect(DEF dst, USE src1, USE src2);
9154 format %{ "XOR $dst, $src1, $src2" %}
9155 size(4);
9156 ins_encode %{
9157 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9158 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9159 %}
9160 ins_pipe(pipe_class_default);
9161 %}
9162
9163 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9164 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9165 ins_cost(DEFAULT_COST*3);
9166
9167 expand %{
9168 // FIXME: we should do this in the ideal world.
9169 iRegIdst tmp1;
9170 iRegIdst tmp2;
9171 xorI_reg_reg(tmp1, src1, src2);
9172 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9173 xorI_reg_reg(dst, tmp1, tmp2);
9174 %}
9175 %}
9176
9177 // Immediate Xor
9178 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9179 match(Set dst (XorI src1 src2));
9180 format %{ "XORI $dst, $src1, $src2" %}
9181 size(4);
9182 ins_encode %{
9183 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9184 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9185 %}
9186 ins_pipe(pipe_class_default);
9187 %}
9188
9189 // Register Xor Long
9190 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9191 match(Set dst (XorL src1 src2));
9192 ins_cost(DEFAULT_COST);
9193
9194 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9195 size(4);
9196 ins_encode %{
9197 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9198 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9199 %}
9200 ins_pipe(pipe_class_default);
9201 %}
9202
9203 // XorL + ConvL2I.
9204 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9205 match(Set dst (ConvL2I (XorL src1 src2)));
9206 ins_cost(DEFAULT_COST);
9207
9208 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9209 size(4);
9210 ins_encode %{
9211 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9212 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9213 %}
9214 ins_pipe(pipe_class_default);
9215 %}
9216
9217 // Immediate Xor Long
9218 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9219 match(Set dst (XorL src1 src2));
9220 ins_cost(DEFAULT_COST);
9221
9222 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9223 size(4);
9224 ins_encode %{
9225 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9226 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9227 %}
9228 ins_pipe(pipe_class_default);
9229 %}
9230
9231 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9232 match(Set dst (XorI src1 src2));
9233 ins_cost(DEFAULT_COST);
9234
9235 format %{ "NOT $dst, $src1 ($src2)" %}
9236 size(4);
9237 ins_encode %{
9238 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9239 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9240 %}
9241 ins_pipe(pipe_class_default);
9242 %}
9243
9244 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9245 match(Set dst (XorL src1 src2));
9246 ins_cost(DEFAULT_COST);
9247
9248 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9249 size(4);
9250 ins_encode %{
9251 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9252 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9253 %}
9254 ins_pipe(pipe_class_default);
9255 %}
9256
9257 // And-complement
9258 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9259 match(Set dst (AndI (XorI src1 src2) src3));
9260 ins_cost(DEFAULT_COST);
9261
9262 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9263 size(4);
9264 ins_encode( enc_andc(dst, src3, src1) );
9265 ins_pipe(pipe_class_default);
9266 %}
9267
9268 // And-complement
9269 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9270 // no match-rule, false predicate
9271 effect(DEF dst, USE src1, USE src2);
9272 predicate(false);
9273
9274 format %{ "ANDC $dst, $src1, $src2" %}
9275 size(4);
9276 ins_encode %{
9277 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9278 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9279 %}
9280 ins_pipe(pipe_class_default);
9281 %}
9282
9283 //----------Moves between int/long and float/double----------------------------
9284 //
9285 // The following rules move values from int/long registers/stack-locations
9286 // to float/double registers/stack-locations and vice versa, without doing any
9287 // conversions. These rules are used to implement the bit-conversion methods
9288 // of java.lang.Float etc., e.g.
9289 // int floatToIntBits(float value)
9290 // float intBitsToFloat(int bits)
9291 //
9292 // Notes on the implementation on ppc64:
9293 // We only provide rules which move between a register and a stack-location,
9294 // because we always have to go through memory when moving between a float
9295 // register and an integer register.
9296
9297 //---------- Chain stack slots between similar types --------
9298
9299 // These are needed so that the rules below can match.
9300
9301 // Load integer from stack slot
9302 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9303 match(Set dst src);
9304 ins_cost(MEMORY_REF_COST);
9305
9306 format %{ "LWZ $dst, $src" %}
9307 size(4);
9308 ins_encode( enc_lwz(dst, src) );
9309 ins_pipe(pipe_class_memory);
9310 %}
9311
9312 // Store integer to stack slot
9313 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9314 match(Set dst src);
9315 ins_cost(MEMORY_REF_COST);
9316
9317 format %{ "STW $src, $dst \t// stk" %}
9318 size(4);
9319 ins_encode( enc_stw(src, dst) ); // rs=rt
9320 ins_pipe(pipe_class_memory);
9321 %}
9322
9323 // Load long from stack slot
9324 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9325 match(Set dst src);
9326 ins_cost(MEMORY_REF_COST);
9327
9328 format %{ "LD $dst, $src \t// long" %}
9329 size(4);
9330 ins_encode( enc_ld(dst, src) );
9331 ins_pipe(pipe_class_memory);
9332 %}
9333
9334 // Store long to stack slot
9335 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9336 match(Set dst src);
9337 ins_cost(MEMORY_REF_COST);
9338
9339 format %{ "STD $src, $dst \t// long" %}
9340 size(4);
9341 ins_encode( enc_std(src, dst) ); // rs=rt
9342 ins_pipe(pipe_class_memory);
9343 %}
9344
9345 //----------Moves between int and float
9346
9347 // Move float value from float stack-location to integer register.
9348 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9349 match(Set dst (MoveF2I src));
9350 ins_cost(MEMORY_REF_COST);
9351
9352 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9353 size(4);
9354 ins_encode( enc_lwz(dst, src) );
9355 ins_pipe(pipe_class_memory);
9356 %}
9357
9358 // Move float value from float register to integer stack-location.
9359 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9360 match(Set dst (MoveF2I src));
9361 ins_cost(MEMORY_REF_COST);
9362
9363 format %{ "STFS $src, $dst \t// MoveF2I" %}
9364 size(4);
9365 ins_encode( enc_stfs(src, dst) );
9366 ins_pipe(pipe_class_memory);
9367 %}
9368
9369 // Move integer value from integer stack-location to float register.
9370 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9371 match(Set dst (MoveI2F src));
9372 ins_cost(MEMORY_REF_COST);
9373
9374 format %{ "LFS $dst, $src \t// MoveI2F" %}
9375 size(4);
9376 ins_encode %{
9377 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9378 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9379 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9380 %}
9381 ins_pipe(pipe_class_memory);
9382 %}
9383
9384 // Move integer value from integer register to float stack-location.
9385 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9386 match(Set dst (MoveI2F src));
9387 ins_cost(MEMORY_REF_COST);
9388
9389 format %{ "STW $src, $dst \t// MoveI2F" %}
9390 size(4);
9391 ins_encode( enc_stw(src, dst) );
9392 ins_pipe(pipe_class_memory);
9393 %}
9394
9395 //----------Moves between long and float
9396
9397 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9398 // no match-rule, false predicate
9399 effect(DEF dst, USE src);
9400 predicate(false);
9401
9402 format %{ "storeD $src, $dst \t// STACK" %}
9403 size(4);
9404 ins_encode( enc_stfd(src, dst) );
9405 ins_pipe(pipe_class_default);
9406 %}
9407
9408 //----------Moves between long and double
9409
9410 // Move double value from double stack-location to long register.
9411 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9412 match(Set dst (MoveD2L src));
9413 ins_cost(MEMORY_REF_COST);
9414 size(4);
9415 format %{ "LD $dst, $src \t// MoveD2L" %}
9416 ins_encode( enc_ld(dst, src) );
9417 ins_pipe(pipe_class_memory);
9418 %}
9419
9420 // Move double value from double register to long stack-location.
9421 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9422 match(Set dst (MoveD2L src));
9423 effect(DEF dst, USE src);
9424 ins_cost(MEMORY_REF_COST);
9425
9426 format %{ "STFD $src, $dst \t// MoveD2L" %}
9427 size(4);
9428 ins_encode( enc_stfd(src, dst) );
9429 ins_pipe(pipe_class_memory);
9430 %}
9431
9432 // Move long value from long stack-location to double register.
9433 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9434 match(Set dst (MoveL2D src));
9435 ins_cost(MEMORY_REF_COST);
9436
9437 format %{ "LFD $dst, $src \t// MoveL2D" %}
9438 size(4);
9439 ins_encode( enc_lfd(dst, src) );
9440 ins_pipe(pipe_class_memory);
9441 %}
9442
9443 // Move long value from long register to double stack-location.
9444 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9445 match(Set dst (MoveL2D src));
9446 ins_cost(MEMORY_REF_COST);
9447
9448 format %{ "STD $src, $dst \t// MoveL2D" %}
9449 size(4);
9450 ins_encode( enc_std(src, dst) );
9451 ins_pipe(pipe_class_memory);
9452 %}
9453
9454 //----------Register Move Instructions-----------------------------------------
9455
9456 // Replicate for Superword
9457
9458 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9459 predicate(false);
9460 effect(DEF dst, USE src);
9461
9462 format %{ "MR $dst, $src \t// replicate " %}
9463 // variable size, 0 or 4.
9464 ins_encode %{
9465 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9466 __ mr_if_needed($dst$$Register, $src$$Register);
9467 %}
9468 ins_pipe(pipe_class_default);
9469 %}
9470
9471 //----------Cast instructions (Java-level type cast)---------------------------
9472
9473 // Cast Long to Pointer for unsafe natives.
9474 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9475 match(Set dst (CastX2P src));
9476
9477 format %{ "MR $dst, $src \t// Long->Ptr" %}
9478 // variable size, 0 or 4.
9479 ins_encode %{
9480 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9481 __ mr_if_needed($dst$$Register, $src$$Register);
9482 %}
9483 ins_pipe(pipe_class_default);
9484 %}
9485
9486 // Cast Pointer to Long for unsafe natives.
9487 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9488 match(Set dst (CastP2X src));
9489
9490 format %{ "MR $dst, $src \t// Ptr->Long" %}
9491 // variable size, 0 or 4.
9492 ins_encode %{
9493 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9494 __ mr_if_needed($dst$$Register, $src$$Register);
9495 %}
9496 ins_pipe(pipe_class_default);
9497 %}
9498
9499 instruct castPP(iRegPdst dst) %{
9500 match(Set dst (CastPP dst));
9501 format %{ " -- \t// castPP of $dst" %}
9502 size(0);
9503 ins_encode( /*empty*/ );
9504 ins_pipe(pipe_class_default);
9505 %}
9506
9507 instruct castII(iRegIdst dst) %{
9508 match(Set dst (CastII dst));
9509 format %{ " -- \t// castII of $dst" %}
9510 size(0);
9511 ins_encode( /*empty*/ );
9512 ins_pipe(pipe_class_default);
9513 %}
9514
9515 instruct checkCastPP(iRegPdst dst) %{
9516 match(Set dst (CheckCastPP dst));
9517 format %{ " -- \t// checkcastPP of $dst" %}
9518 size(0);
9519 ins_encode( /*empty*/ );
9520 ins_pipe(pipe_class_default);
9521 %}
9522
9523 //----------Convert instructions-----------------------------------------------
9524
9525 // Convert to boolean.
9526
9527 // int_to_bool(src) : { 1 if src != 0
9528 // { 0 else
9529 //
9530 // strategy:
9531 // 1) Count leading zeros of 32 bit-value src,
9532 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9533 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9534 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9535
9536 // convI2Bool
9537 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9538 match(Set dst (Conv2B src));
9539 predicate(UseCountLeadingZerosInstructionsPPC64);
9540 ins_cost(DEFAULT_COST);
9541
9542 expand %{
9543 immI shiftAmount %{ 0x5 %}
9544 uimmI16 mask %{ 0x1 %}
9545 iRegIdst tmp1;
9546 iRegIdst tmp2;
9547 countLeadingZerosI(tmp1, src);
9548 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9549 xorI_reg_uimm16(dst, tmp2, mask);
9550 %}
9551 %}
9552
9553 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9554 match(Set dst (Conv2B src));
9555 effect(TEMP crx);
9556 predicate(!UseCountLeadingZerosInstructionsPPC64);
9557 ins_cost(DEFAULT_COST);
9558
9559 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9560 "LI $dst, #0\n\t"
9561 "BEQ $crx, done\n\t"
9562 "LI $dst, #1\n"
9563 "done:" %}
9564 size(16);
9565 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9566 ins_pipe(pipe_class_compare);
9567 %}
9568
9569 // ConvI2B + XorI
9570 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9571 match(Set dst (XorI (Conv2B src) mask));
9572 predicate(UseCountLeadingZerosInstructionsPPC64);
9573 ins_cost(DEFAULT_COST);
9574
9575 expand %{
9576 immI shiftAmount %{ 0x5 %}
9577 iRegIdst tmp1;
9578 countLeadingZerosI(tmp1, src);
9579 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9580 %}
9581 %}
9582
9583 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9584 match(Set dst (XorI (Conv2B src) mask));
9585 effect(TEMP crx);
9586 predicate(!UseCountLeadingZerosInstructionsPPC64);
9587 ins_cost(DEFAULT_COST);
9588
9589 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9590 "LI $dst, #1\n\t"
9591 "BEQ $crx, done\n\t"
9592 "LI $dst, #0\n"
9593 "done:" %}
9594 size(16);
9595 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9596 ins_pipe(pipe_class_compare);
9597 %}
9598
9599 // AndI 0b0..010..0 + ConvI2B
9600 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9601 match(Set dst (Conv2B (AndI src mask)));
9602 predicate(UseRotateAndMaskInstructionsPPC64);
9603 ins_cost(DEFAULT_COST);
9604
9605 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9606 size(4);
9607 ins_encode %{
9608 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9609 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9610 %}
9611 ins_pipe(pipe_class_default);
9612 %}
9613
9614 // Convert pointer to boolean.
9615 //
9616 // ptr_to_bool(src) : { 1 if src != 0
9617 // { 0 else
9618 //
9619 // strategy:
9620 // 1) Count leading zeros of 64 bit-value src,
9621 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9622 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9623 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9624
9625 // ConvP2B
9626 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9627 match(Set dst (Conv2B src));
9628 predicate(UseCountLeadingZerosInstructionsPPC64);
9629 ins_cost(DEFAULT_COST);
9630
9631 expand %{
9632 immI shiftAmount %{ 0x6 %}
9633 uimmI16 mask %{ 0x1 %}
9634 iRegIdst tmp1;
9635 iRegIdst tmp2;
9636 countLeadingZerosP(tmp1, src);
9637 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9638 xorI_reg_uimm16(dst, tmp2, mask);
9639 %}
9640 %}
9641
9642 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9643 match(Set dst (Conv2B src));
9644 effect(TEMP crx);
9645 predicate(!UseCountLeadingZerosInstructionsPPC64);
9646 ins_cost(DEFAULT_COST);
9647
9648 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9649 "LI $dst, #0\n\t"
9650 "BEQ $crx, done\n\t"
9651 "LI $dst, #1\n"
9652 "done:" %}
9653 size(16);
9654 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9655 ins_pipe(pipe_class_compare);
9656 %}
9657
9658 // ConvP2B + XorI
9659 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9660 match(Set dst (XorI (Conv2B src) mask));
9661 predicate(UseCountLeadingZerosInstructionsPPC64);
9662 ins_cost(DEFAULT_COST);
9663
9664 expand %{
9665 immI shiftAmount %{ 0x6 %}
9666 iRegIdst tmp1;
9667 countLeadingZerosP(tmp1, src);
9668 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9669 %}
9670 %}
9671
9672 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9673 match(Set dst (XorI (Conv2B src) mask));
9674 effect(TEMP crx);
9675 predicate(!UseCountLeadingZerosInstructionsPPC64);
9676 ins_cost(DEFAULT_COST);
9677
9678 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9679 "LI $dst, #1\n\t"
9680 "BEQ $crx, done\n\t"
9681 "LI $dst, #0\n"
9682 "done:" %}
9683 size(16);
9684 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9685 ins_pipe(pipe_class_compare);
9686 %}
9687
9688 // if src1 < src2, return -1 else return 0
9689 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9690 match(Set dst (CmpLTMask src1 src2));
9691 ins_cost(DEFAULT_COST*4);
9692
9693 expand %{
9694 iRegLdst src1s;
9695 iRegLdst src2s;
9696 iRegLdst diff;
9697 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9698 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9699 subL_reg_reg(diff, src1s, src2s);
9700 // Need to consider >=33 bit result, therefore we need signmaskL.
9701 signmask64I_regL(dst, diff);
9702 %}
9703 %}
9704
9705 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9706 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9707 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9708 size(4);
9709 ins_encode %{
9710 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9711 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9712 %}
9713 ins_pipe(pipe_class_default);
9714 %}
9715
9716 //----------Arithmetic Conversion Instructions---------------------------------
9717
9718 // Convert to Byte -- nop
9719 // Convert to Short -- nop
9720
9721 // Convert to Int
9722
9723 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9724 match(Set dst (RShiftI (LShiftI src amount) amount));
9725 format %{ "EXTSB $dst, $src \t// byte->int" %}
9726 size(4);
9727 ins_encode %{
9728 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9729 __ extsb($dst$$Register, $src$$Register);
9730 %}
9731 ins_pipe(pipe_class_default);
9732 %}
9733
9734 // LShiftI 16 + RShiftI 16 converts short to int.
9735 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9736 match(Set dst (RShiftI (LShiftI src amount) amount));
9737 format %{ "EXTSH $dst, $src \t// short->int" %}
9738 size(4);
9739 ins_encode %{
9740 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9741 __ extsh($dst$$Register, $src$$Register);
9742 %}
9743 ins_pipe(pipe_class_default);
9744 %}
9745
9746 // ConvL2I + ConvI2L: Sign extend int in long register.
9747 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9748 match(Set dst (ConvI2L (ConvL2I src)));
9749
9750 format %{ "EXTSW $dst, $src \t// long->long" %}
9751 size(4);
9752 ins_encode %{
9753 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9754 __ extsw($dst$$Register, $src$$Register);
9755 %}
9756 ins_pipe(pipe_class_default);
9757 %}
9758
9759 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9760 match(Set dst (ConvL2I src));
9761 format %{ "MR $dst, $src \t// long->int" %}
9762 // variable size, 0 or 4
9763 ins_encode %{
9764 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9765 __ mr_if_needed($dst$$Register, $src$$Register);
9766 %}
9767 ins_pipe(pipe_class_default);
9768 %}
9769
9770 instruct convD2IRaw_regD(regD dst, regD src) %{
9771 // no match-rule, false predicate
9772 effect(DEF dst, USE src);
9773 predicate(false);
9774
9775 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9776 size(4);
9777 ins_encode %{
9778 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9779 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9780 %}
9781 ins_pipe(pipe_class_default);
9782 %}
9783
9784 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9785 // no match-rule, false predicate
9786 effect(DEF dst, USE crx, USE src);
9787 predicate(false);
9788
9789 ins_variable_size_depending_on_alignment(true);
9790
9791 format %{ "cmovI $crx, $dst, $src" %}
9792 // Worst case is branch + move + stop, no stop without scheduler.
9793 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9794 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9795 ins_pipe(pipe_class_default);
9796 %}
9797
9798 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9799 // no match-rule, false predicate
9800 effect(DEF dst, USE crx, USE mem);
9801 predicate(false);
9802
9803 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9804 postalloc_expand %{
9805 //
9806 // replaces
9807 //
9808 // region dst crx mem
9809 // \ | | /
9810 // dst=cmovI_bso_stackSlotL_conLvalue0
9811 //
9812 // with
9813 //
9814 // region dst
9815 // \ /
9816 // dst=loadConI16(0)
9817 // |
9818 // ^ region dst crx mem
9819 // | \ | | /
9820 // dst=cmovI_bso_stackSlotL
9821 //
9822
9823 // Create new nodes.
9824 MachNode *m1 = new loadConI16Node();
9825 MachNode *m2 = new cmovI_bso_stackSlotLNode();
9826
9827 // inputs for new nodes
9828 m1->add_req(n_region);
9829 m2->add_req(n_region, n_crx, n_mem);
9830
9831 // precedences for new nodes
9832 m2->add_prec(m1);
9833
9834 // operands for new nodes
9835 m1->_opnds[0] = op_dst;
9836 m1->_opnds[1] = new immI16Oper(0);
9837
9838 m2->_opnds[0] = op_dst;
9839 m2->_opnds[1] = op_crx;
9840 m2->_opnds[2] = op_mem;
9841
9842 // registers for new nodes
9843 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9844 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9845
9846 // Insert new nodes.
9847 nodes->push(m1);
9848 nodes->push(m2);
9849 %}
9850 %}
9851
9852 // Double to Int conversion, NaN is mapped to 0.
9853 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9854 match(Set dst (ConvD2I src));
9855 ins_cost(DEFAULT_COST);
9856
9857 expand %{
9858 regD tmpD;
9859 stackSlotL tmpS;
9860 flagsReg crx;
9861 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9862 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9863 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9864 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9865 %}
9866 %}
9867
9868 instruct convF2IRaw_regF(regF dst, regF src) %{
9869 // no match-rule, false predicate
9870 effect(DEF dst, USE src);
9871 predicate(false);
9872
9873 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9874 size(4);
9875 ins_encode %{
9876 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9877 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9878 %}
9879 ins_pipe(pipe_class_default);
9880 %}
9881
9882 // Float to Int conversion, NaN is mapped to 0.
9883 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9884 match(Set dst (ConvF2I src));
9885 ins_cost(DEFAULT_COST);
9886
9887 expand %{
9888 regF tmpF;
9889 stackSlotL tmpS;
9890 flagsReg crx;
9891 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9892 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9893 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9894 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9895 %}
9896 %}
9897
9898 // Convert to Long
9899
9900 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9901 match(Set dst (ConvI2L src));
9902 format %{ "EXTSW $dst, $src \t// int->long" %}
9903 size(4);
9904 ins_encode %{
9905 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9906 __ extsw($dst$$Register, $src$$Register);
9907 %}
9908 ins_pipe(pipe_class_default);
9909 %}
9910
9911 // Zero-extend: convert unsigned int to long (convUI2L).
9912 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9913 match(Set dst (AndL (ConvI2L src) mask));
9914 ins_cost(DEFAULT_COST);
9915
9916 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9917 size(4);
9918 ins_encode %{
9919 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9920 __ clrldi($dst$$Register, $src$$Register, 32);
9921 %}
9922 ins_pipe(pipe_class_default);
9923 %}
9924
9925 // Zero-extend: convert unsigned int to long in long register.
9926 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9927 match(Set dst (AndL src mask));
9928 ins_cost(DEFAULT_COST);
9929
9930 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9931 size(4);
9932 ins_encode %{
9933 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9934 __ clrldi($dst$$Register, $src$$Register, 32);
9935 %}
9936 ins_pipe(pipe_class_default);
9937 %}
9938
9939 instruct convF2LRaw_regF(regF dst, regF src) %{
9940 // no match-rule, false predicate
9941 effect(DEF dst, USE src);
9942 predicate(false);
9943
9944 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9945 size(4);
9946 ins_encode %{
9947 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9948 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9949 %}
9950 ins_pipe(pipe_class_default);
9951 %}
9952
9953 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9954 // no match-rule, false predicate
9955 effect(DEF dst, USE crx, USE src);
9956 predicate(false);
9957
9958 ins_variable_size_depending_on_alignment(true);
9959
9960 format %{ "cmovL $crx, $dst, $src" %}
9961 // Worst case is branch + move + stop, no stop without scheduler.
9962 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9963 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9964 ins_pipe(pipe_class_default);
9965 %}
9966
9967 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9968 // no match-rule, false predicate
9969 effect(DEF dst, USE crx, USE mem);
9970 predicate(false);
9971
9972 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9973 postalloc_expand %{
9974 //
9975 // replaces
9976 //
9977 // region dst crx mem
9978 // \ | | /
9979 // dst=cmovL_bso_stackSlotL_conLvalue0
9980 //
9981 // with
9982 //
9983 // region dst
9984 // \ /
9985 // dst=loadConL16(0)
9986 // |
9987 // ^ region dst crx mem
9988 // | \ | | /
9989 // dst=cmovL_bso_stackSlotL
9990 //
9991
9992 // Create new nodes.
9993 MachNode *m1 = new loadConL16Node();
9994 MachNode *m2 = new cmovL_bso_stackSlotLNode();
9995
9996 // inputs for new nodes
9997 m1->add_req(n_region);
9998 m2->add_req(n_region, n_crx, n_mem);
9999 m2->add_prec(m1);
10000
10001 // operands for new nodes
10002 m1->_opnds[0] = op_dst;
10003 m1->_opnds[1] = new immL16Oper(0);
10004 m2->_opnds[0] = op_dst;
10005 m2->_opnds[1] = op_crx;
10006 m2->_opnds[2] = op_mem;
10007
10008 // registers for new nodes
10009 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10010 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10011
10012 // Insert new nodes.
10013 nodes->push(m1);
10014 nodes->push(m2);
10015 %}
10016 %}
10017
10018 // Float to Long conversion, NaN is mapped to 0.
10019 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
10020 match(Set dst (ConvF2L src));
10021 ins_cost(DEFAULT_COST);
10022
10023 expand %{
10024 regF tmpF;
10025 stackSlotL tmpS;
10026 flagsReg crx;
10027 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10028 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
10029 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
10030 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10031 %}
10032 %}
10033
10034 instruct convD2LRaw_regD(regD dst, regD src) %{
10035 // no match-rule, false predicate
10036 effect(DEF dst, USE src);
10037 predicate(false);
10038
10039 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10040 size(4);
10041 ins_encode %{
10042 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10043 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10044 %}
10045 ins_pipe(pipe_class_default);
10046 %}
10047
10048 // Double to Long conversion, NaN is mapped to 0.
10049 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10050 match(Set dst (ConvD2L src));
10051 ins_cost(DEFAULT_COST);
10052
10053 expand %{
10054 regD tmpD;
10055 stackSlotL tmpS;
10056 flagsReg crx;
10057 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10058 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10059 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10060 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10061 %}
10062 %}
10063
10064 // Convert to Float
10065
10066 // Placed here as needed in expand.
10067 instruct convL2DRaw_regD(regD dst, regD src) %{
10068 // no match-rule, false predicate
10069 effect(DEF dst, USE src);
10070 predicate(false);
10071
10072 format %{ "FCFID $dst, $src \t// convL2D" %}
10073 size(4);
10074 ins_encode %{
10075 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10076 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10077 %}
10078 ins_pipe(pipe_class_default);
10079 %}
10080
10081 // Placed here as needed in expand.
10082 instruct convD2F_reg(regF dst, regD src) %{
10083 match(Set dst (ConvD2F src));
10084 format %{ "FRSP $dst, $src \t// convD2F" %}
10085 size(4);
10086 ins_encode %{
10087 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10088 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10089 %}
10090 ins_pipe(pipe_class_default);
10091 %}
10092
10093 // Integer to Float conversion.
10094 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10095 match(Set dst (ConvI2F src));
10096 predicate(!VM_Version::has_fcfids());
10097 ins_cost(DEFAULT_COST);
10098
10099 expand %{
10100 iRegLdst tmpL;
10101 stackSlotL tmpS;
10102 regD tmpD;
10103 regD tmpD2;
10104 convI2L_reg(tmpL, src); // Sign-extension int to long.
10105 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10106 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10107 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10108 convD2F_reg(dst, tmpD2); // Convert double to float.
10109 %}
10110 %}
10111
10112 instruct convL2FRaw_regF(regF dst, regD src) %{
10113 // no match-rule, false predicate
10114 effect(DEF dst, USE src);
10115 predicate(false);
10116
10117 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10118 size(4);
10119 ins_encode %{
10120 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10121 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10122 %}
10123 ins_pipe(pipe_class_default);
10124 %}
10125
10126 // Integer to Float conversion. Special version for Power7.
10127 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10128 match(Set dst (ConvI2F src));
10129 predicate(VM_Version::has_fcfids());
10130 ins_cost(DEFAULT_COST);
10131
10132 expand %{
10133 iRegLdst tmpL;
10134 stackSlotL tmpS;
10135 regD tmpD;
10136 convI2L_reg(tmpL, src); // Sign-extension int to long.
10137 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10138 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10139 convL2FRaw_regF(dst, tmpD); // Convert to float.
10140 %}
10141 %}
10142
10143 // L2F to avoid runtime call.
10144 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10145 match(Set dst (ConvL2F src));
10146 predicate(VM_Version::has_fcfids());
10147 ins_cost(DEFAULT_COST);
10148
10149 expand %{
10150 stackSlotL tmpS;
10151 regD tmpD;
10152 regL_to_stkL(tmpS, src); // Store long to stack.
10153 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10154 convL2FRaw_regF(dst, tmpD); // Convert to float.
10155 %}
10156 %}
10157
10158 // Moved up as used in expand.
10159 //instruct convD2F_reg(regF dst, regD src) %{%}
10160
10161 // Convert to Double
10162
10163 // Integer to Double conversion.
10164 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10165 match(Set dst (ConvI2D src));
10166 ins_cost(DEFAULT_COST);
10167
10168 expand %{
10169 iRegLdst tmpL;
10170 stackSlotL tmpS;
10171 regD tmpD;
10172 convI2L_reg(tmpL, src); // Sign-extension int to long.
10173 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10174 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10175 convL2DRaw_regD(dst, tmpD); // Convert to double.
10176 %}
10177 %}
10178
10179 // Long to Double conversion
10180 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10181 match(Set dst (ConvL2D src));
10182 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10183
10184 expand %{
10185 regD tmpD;
10186 moveL2D_stack_reg(tmpD, src);
10187 convL2DRaw_regD(dst, tmpD);
10188 %}
10189 %}
10190
10191 instruct convF2D_reg(regD dst, regF src) %{
10192 match(Set dst (ConvF2D src));
10193 format %{ "FMR $dst, $src \t// float->double" %}
10194 // variable size, 0 or 4
10195 ins_encode %{
10196 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10197 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10198 %}
10199 ins_pipe(pipe_class_default);
10200 %}
10201
10202 //----------Control Flow Instructions------------------------------------------
10203 // Compare Instructions
10204
10205 // Compare Integers
10206 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10207 match(Set crx (CmpI src1 src2));
10208 size(4);
10209 format %{ "CMPW $crx, $src1, $src2" %}
10210 ins_encode %{
10211 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10212 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10213 %}
10214 ins_pipe(pipe_class_compare);
10215 %}
10216
10217 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10218 match(Set crx (CmpI src1 src2));
10219 format %{ "CMPWI $crx, $src1, $src2" %}
10220 size(4);
10221 ins_encode %{
10222 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10223 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10224 %}
10225 ins_pipe(pipe_class_compare);
10226 %}
10227
10228 // (src1 & src2) == 0?
10229 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10230 match(Set cr0 (CmpI (AndI src1 src2) zero));
10231 // r0 is killed
10232 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10233 size(4);
10234 ins_encode %{
10235 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10236 __ andi_(R0, $src1$$Register, $src2$$constant);
10237 %}
10238 ins_pipe(pipe_class_compare);
10239 %}
10240
10241 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10242 match(Set crx (CmpL src1 src2));
10243 format %{ "CMPD $crx, $src1, $src2" %}
10244 size(4);
10245 ins_encode %{
10246 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10247 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10248 %}
10249 ins_pipe(pipe_class_compare);
10250 %}
10251
10252 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10253 match(Set crx (CmpL src1 src2));
10254 format %{ "CMPDI $crx, $src1, $src2" %}
10255 size(4);
10256 ins_encode %{
10257 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10258 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10259 %}
10260 ins_pipe(pipe_class_compare);
10261 %}
10262
10263 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10264 match(Set cr0 (CmpL (AndL src1 src2) zero));
10265 // r0 is killed
10266 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10267 size(4);
10268 ins_encode %{
10269 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10270 __ and_(R0, $src1$$Register, $src2$$Register);
10271 %}
10272 ins_pipe(pipe_class_compare);
10273 %}
10274
10275 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10276 match(Set cr0 (CmpL (AndL src1 src2) zero));
10277 // r0 is killed
10278 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10279 size(4);
10280 ins_encode %{
10281 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10282 __ andi_(R0, $src1$$Register, $src2$$constant);
10283 %}
10284 ins_pipe(pipe_class_compare);
10285 %}
10286
10287 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10288 // no match-rule, false predicate
10289 effect(DEF dst, USE crx);
10290 predicate(false);
10291
10292 ins_variable_size_depending_on_alignment(true);
10293
10294 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10295 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10296 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10297 ins_encode %{
10298 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10299 Label done;
10300 // li(Rdst, 0); // equal -> 0
10301 __ beq($crx$$CondRegister, done);
10302 __ li($dst$$Register, 1); // greater -> +1
10303 __ bgt($crx$$CondRegister, done);
10304 __ li($dst$$Register, -1); // unordered or less -> -1
10305 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10306 __ bind(done);
10307 %}
10308 ins_pipe(pipe_class_compare);
10309 %}
10310
10311 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10312 // no match-rule, false predicate
10313 effect(DEF dst, USE crx);
10314 predicate(false);
10315
10316 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10317 postalloc_expand %{
10318 //
10319 // replaces
10320 //
10321 // region crx
10322 // \ |
10323 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10324 //
10325 // with
10326 //
10327 // region
10328 // \
10329 // dst=loadConI16(0)
10330 // |
10331 // ^ region crx
10332 // | \ |
10333 // dst=cmovI_conIvalueMinus1_conIvalue1
10334 //
10335
10336 // Create new nodes.
10337 MachNode *m1 = new loadConI16Node();
10338 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10339
10340 // inputs for new nodes
10341 m1->add_req(n_region);
10342 m2->add_req(n_region, n_crx);
10343 m2->add_prec(m1);
10344
10345 // operands for new nodes
10346 m1->_opnds[0] = op_dst;
10347 m1->_opnds[1] = new immI16Oper(0);
10348 m2->_opnds[0] = op_dst;
10349 m2->_opnds[1] = op_crx;
10350
10351 // registers for new nodes
10352 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10353 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10354
10355 // Insert new nodes.
10356 nodes->push(m1);
10357 nodes->push(m2);
10358 %}
10359 %}
10360
10361 // Manifest a CmpL3 result in an integer register. Very painful.
10362 // This is the test to avoid.
10363 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10364 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10365 match(Set dst (CmpL3 src1 src2));
10366 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10367
10368 expand %{
10369 flagsReg tmp1;
10370 cmpL_reg_reg(tmp1, src1, src2);
10371 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10372 %}
10373 %}
10374
10375 // Implicit range checks.
10376 // A range check in the ideal world has one of the following shapes:
10377 // - (If le (CmpU length index)), (IfTrue throw exception)
10378 // - (If lt (CmpU index length)), (IfFalse throw exception)
10379 //
10380 // Match range check 'If le (CmpU length index)'.
10381 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10382 match(If cmp (CmpU src_length index));
10383 effect(USE labl);
10384 predicate(TrapBasedRangeChecks &&
10385 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10386 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10387 (Matcher::branches_to_uncommon_trap(_leaf)));
10388
10389 ins_is_TrapBasedCheckNode(true);
10390
10391 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10392 size(4);
10393 ins_encode %{
10394 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10395 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10396 __ trap_range_check_le($src_length$$Register, $index$$constant);
10397 } else {
10398 // Both successors are uncommon traps, probability is 0.
10399 // Node got flipped during fixup flow.
10400 assert($cmp$$cmpcode == 0x9, "must be greater");
10401 __ trap_range_check_g($src_length$$Register, $index$$constant);
10402 }
10403 %}
10404 ins_pipe(pipe_class_trap);
10405 %}
10406
10407 // Match range check 'If lt (CmpU index length)'.
10408 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10409 match(If cmp (CmpU src_index src_length));
10410 effect(USE labl);
10411 predicate(TrapBasedRangeChecks &&
10412 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10413 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10414 (Matcher::branches_to_uncommon_trap(_leaf)));
10415
10416 ins_is_TrapBasedCheckNode(true);
10417
10418 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10419 size(4);
10420 ins_encode %{
10421 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10422 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10423 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10424 } else {
10425 // Both successors are uncommon traps, probability is 0.
10426 // Node got flipped during fixup flow.
10427 assert($cmp$$cmpcode == 0x8, "must be less");
10428 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10429 }
10430 %}
10431 ins_pipe(pipe_class_trap);
10432 %}
10433
10434 // Match range check 'If lt (CmpU index length)'.
10435 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10436 match(If cmp (CmpU src_index length));
10437 effect(USE labl);
10438 predicate(TrapBasedRangeChecks &&
10439 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10440 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10441 (Matcher::branches_to_uncommon_trap(_leaf)));
10442
10443 ins_is_TrapBasedCheckNode(true);
10444
10445 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10446 size(4);
10447 ins_encode %{
10448 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10449 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10450 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10451 } else {
10452 // Both successors are uncommon traps, probability is 0.
10453 // Node got flipped during fixup flow.
10454 assert($cmp$$cmpcode == 0x8, "must be less");
10455 __ trap_range_check_l($src_index$$Register, $length$$constant);
10456 }
10457 %}
10458 ins_pipe(pipe_class_trap);
10459 %}
10460
10461 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10462 match(Set crx (CmpU src1 src2));
10463 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10464 size(4);
10465 ins_encode %{
10466 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10467 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10468 %}
10469 ins_pipe(pipe_class_compare);
10470 %}
10471
10472 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10473 match(Set crx (CmpU src1 src2));
10474 size(4);
10475 format %{ "CMPLWI $crx, $src1, $src2" %}
10476 ins_encode %{
10477 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10478 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10479 %}
10480 ins_pipe(pipe_class_compare);
10481 %}
10482
10483 // Implicit zero checks (more implicit null checks).
10484 // No constant pool entries required.
10485 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10486 match(If cmp (CmpN value zero));
10487 effect(USE labl);
10488 predicate(TrapBasedNullChecks &&
10489 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10490 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10491 Matcher::branches_to_uncommon_trap(_leaf));
10492 ins_cost(1);
10493
10494 ins_is_TrapBasedCheckNode(true);
10495
10496 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10497 size(4);
10498 ins_encode %{
10499 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10500 if ($cmp$$cmpcode == 0xA) {
10501 __ trap_null_check($value$$Register);
10502 } else {
10503 // Both successors are uncommon traps, probability is 0.
10504 // Node got flipped during fixup flow.
10505 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10506 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10507 }
10508 %}
10509 ins_pipe(pipe_class_trap);
10510 %}
10511
10512 // Compare narrow oops.
10513 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10514 match(Set crx (CmpN src1 src2));
10515
10516 size(4);
10517 ins_cost(2);
10518 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10519 ins_encode %{
10520 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10521 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10522 %}
10523 ins_pipe(pipe_class_compare);
10524 %}
10525
10526 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10527 match(Set crx (CmpN src1 src2));
10528 // Make this more expensive than zeroCheckN_iReg_imm0.
10529 ins_cost(2);
10530
10531 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10532 size(4);
10533 ins_encode %{
10534 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10535 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10536 %}
10537 ins_pipe(pipe_class_compare);
10538 %}
10539
10540 // Implicit zero checks (more implicit null checks).
10541 // No constant pool entries required.
10542 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10543 match(If cmp (CmpP value zero));
10544 effect(USE labl);
10545 predicate(TrapBasedNullChecks &&
10546 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10547 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10548 Matcher::branches_to_uncommon_trap(_leaf));
10549 ins_cost(1); // Should not be cheaper than zeroCheckN.
10550
10551 ins_is_TrapBasedCheckNode(true);
10552
10553 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10554 size(4);
10555 ins_encode %{
10556 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10557 if ($cmp$$cmpcode == 0xA) {
10558 __ trap_null_check($value$$Register);
10559 } else {
10560 // Both successors are uncommon traps, probability is 0.
10561 // Node got flipped during fixup flow.
10562 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10563 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10564 }
10565 %}
10566 ins_pipe(pipe_class_trap);
10567 %}
10568
10569 // Compare Pointers
10570 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10571 match(Set crx (CmpP src1 src2));
10572 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10573 size(4);
10574 ins_encode %{
10575 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10576 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10577 %}
10578 ins_pipe(pipe_class_compare);
10579 %}
10580
10581 // Used in postalloc expand.
10582 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10583 // This match rule prevents reordering of node before a safepoint.
10584 // This only makes sense if this instructions is used exclusively
10585 // for the expansion of EncodeP!
10586 match(Set crx (CmpP src1 src2));
10587 predicate(false);
10588
10589 format %{ "CMPDI $crx, $src1, $src2" %}
10590 size(4);
10591 ins_encode %{
10592 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10593 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10594 %}
10595 ins_pipe(pipe_class_compare);
10596 %}
10597
10598 //----------Float Compares----------------------------------------------------
10599
10600 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10601 // Needs matchrule, see cmpDUnordered.
10602 match(Set crx (CmpF src1 src2));
10603 // no match-rule, false predicate
10604 predicate(false);
10605
10606 format %{ "cmpFUrd $crx, $src1, $src2" %}
10607 size(4);
10608 ins_encode %{
10609 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10610 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10611 %}
10612 ins_pipe(pipe_class_default);
10613 %}
10614
10615 instruct cmov_bns_less(flagsReg crx) %{
10616 // no match-rule, false predicate
10617 effect(DEF crx);
10618 predicate(false);
10619
10620 ins_variable_size_depending_on_alignment(true);
10621
10622 format %{ "cmov $crx" %}
10623 // Worst case is branch + move + stop, no stop without scheduler.
10624 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10625 ins_encode %{
10626 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10627 Label done;
10628 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10629 __ li(R0, 0);
10630 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10631 // TODO PPC port __ endgroup_if_needed(_size == 16);
10632 __ bind(done);
10633 %}
10634 ins_pipe(pipe_class_default);
10635 %}
10636
10637 // Compare floating, generate condition code.
10638 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10639 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10640 //
10641 // The following code sequence occurs a lot in mpegaudio:
10642 //
10643 // block BXX:
10644 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10645 // cmpFUrd CCR6, F11, F9
10646 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10647 // cmov CCR6
10648 // 8: instruct branchConSched:
10649 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10650 match(Set crx (CmpF src1 src2));
10651 ins_cost(DEFAULT_COST+BRANCH_COST);
10652
10653 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10654 postalloc_expand %{
10655 //
10656 // replaces
10657 //
10658 // region src1 src2
10659 // \ | |
10660 // crx=cmpF_reg_reg
10661 //
10662 // with
10663 //
10664 // region src1 src2
10665 // \ | |
10666 // crx=cmpFUnordered_reg_reg
10667 // |
10668 // ^ region
10669 // | \
10670 // crx=cmov_bns_less
10671 //
10672
10673 // Create new nodes.
10674 MachNode *m1 = new cmpFUnordered_reg_regNode();
10675 MachNode *m2 = new cmov_bns_lessNode();
10676
10677 // inputs for new nodes
10678 m1->add_req(n_region, n_src1, n_src2);
10679 m2->add_req(n_region);
10680 m2->add_prec(m1);
10681
10682 // operands for new nodes
10683 m1->_opnds[0] = op_crx;
10684 m1->_opnds[1] = op_src1;
10685 m1->_opnds[2] = op_src2;
10686 m2->_opnds[0] = op_crx;
10687
10688 // registers for new nodes
10689 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10690 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10691
10692 // Insert new nodes.
10693 nodes->push(m1);
10694 nodes->push(m2);
10695 %}
10696 %}
10697
10698 // Compare float, generate -1,0,1
10699 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10700 match(Set dst (CmpF3 src1 src2));
10701 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10702
10703 expand %{
10704 flagsReg tmp1;
10705 cmpFUnordered_reg_reg(tmp1, src1, src2);
10706 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10707 %}
10708 %}
10709
10710 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10711 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10712 // node right before the conditional move using it.
10713 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10714 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10715 // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10716 // conditional move was supposed to be spilled.
10717 match(Set crx (CmpD src1 src2));
10718 // False predicate, shall not be matched.
10719 predicate(false);
10720
10721 format %{ "cmpFUrd $crx, $src1, $src2" %}
10722 size(4);
10723 ins_encode %{
10724 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10725 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10726 %}
10727 ins_pipe(pipe_class_default);
10728 %}
10729
10730 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10731 match(Set crx (CmpD src1 src2));
10732 ins_cost(DEFAULT_COST+BRANCH_COST);
10733
10734 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10735 postalloc_expand %{
10736 //
10737 // replaces
10738 //
10739 // region src1 src2
10740 // \ | |
10741 // crx=cmpD_reg_reg
10742 //
10743 // with
10744 //
10745 // region src1 src2
10746 // \ | |
10747 // crx=cmpDUnordered_reg_reg
10748 // |
10749 // ^ region
10750 // | \
10751 // crx=cmov_bns_less
10752 //
10753
10754 // create new nodes
10755 MachNode *m1 = new cmpDUnordered_reg_regNode();
10756 MachNode *m2 = new cmov_bns_lessNode();
10757
10758 // inputs for new nodes
10759 m1->add_req(n_region, n_src1, n_src2);
10760 m2->add_req(n_region);
10761 m2->add_prec(m1);
10762
10763 // operands for new nodes
10764 m1->_opnds[0] = op_crx;
10765 m1->_opnds[1] = op_src1;
10766 m1->_opnds[2] = op_src2;
10767 m2->_opnds[0] = op_crx;
10768
10769 // registers for new nodes
10770 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10771 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10772
10773 // Insert new nodes.
10774 nodes->push(m1);
10775 nodes->push(m2);
10776 %}
10777 %}
10778
10779 // Compare double, generate -1,0,1
10780 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10781 match(Set dst (CmpD3 src1 src2));
10782 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10783
10784 expand %{
10785 flagsReg tmp1;
10786 cmpDUnordered_reg_reg(tmp1, src1, src2);
10787 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10788 %}
10789 %}
10790
10791 //----------Branches---------------------------------------------------------
10792 // Jump
10793
10794 // Direct Branch.
10795 instruct branch(label labl) %{
10796 match(Goto);
10797 effect(USE labl);
10798 ins_cost(BRANCH_COST);
10799
10800 format %{ "B $labl" %}
10801 size(4);
10802 ins_encode %{
10803 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10804 Label d; // dummy
10805 __ bind(d);
10806 Label* p = $labl$$label;
10807 // `p' is `NULL' when this encoding class is used only to
10808 // determine the size of the encoded instruction.
10809 Label& l = (NULL == p)? d : *(p);
10810 __ b(l);
10811 %}
10812 ins_pipe(pipe_class_default);
10813 %}
10814
10815 // Conditional Near Branch
10816 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10817 // Same match rule as `branchConFar'.
10818 match(If cmp crx);
10819 effect(USE lbl);
10820 ins_cost(BRANCH_COST);
10821
10822 // If set to 1 this indicates that the current instruction is a
10823 // short variant of a long branch. This avoids using this
10824 // instruction in first-pass matching. It will then only be used in
10825 // the `Shorten_branches' pass.
10826 ins_short_branch(1);
10827
10828 format %{ "B$cmp $crx, $lbl" %}
10829 size(4);
10830 ins_encode( enc_bc(crx, cmp, lbl) );
10831 ins_pipe(pipe_class_default);
10832 %}
10833
10834 // This is for cases when the ppc64 `bc' instruction does not
10835 // reach far enough. So we emit a far branch here, which is more
10836 // expensive.
10837 //
10838 // Conditional Far Branch
10839 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10840 // Same match rule as `branchCon'.
10841 match(If cmp crx);
10842 effect(USE crx, USE lbl);
10843 predicate(!false /* TODO: PPC port HB_Schedule*/);
10844 // Higher cost than `branchCon'.
10845 ins_cost(5*BRANCH_COST);
10846
10847 // This is not a short variant of a branch, but the long variant.
10848 ins_short_branch(0);
10849
10850 format %{ "B_FAR$cmp $crx, $lbl" %}
10851 size(8);
10852 ins_encode( enc_bc_far(crx, cmp, lbl) );
10853 ins_pipe(pipe_class_default);
10854 %}
10855
10856 // Conditional Branch used with Power6 scheduler (can be far or short).
10857 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10858 // Same match rule as `branchCon'.
10859 match(If cmp crx);
10860 effect(USE crx, USE lbl);
10861 predicate(false /* TODO: PPC port HB_Schedule*/);
10862 // Higher cost than `branchCon'.
10863 ins_cost(5*BRANCH_COST);
10864
10865 // Actually size doesn't depend on alignment but on shortening.
10866 ins_variable_size_depending_on_alignment(true);
10867 // long variant.
10868 ins_short_branch(0);
10869
10870 format %{ "B_FAR$cmp $crx, $lbl" %}
10871 size(8); // worst case
10872 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10873 ins_pipe(pipe_class_default);
10874 %}
10875
10876 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10877 match(CountedLoopEnd cmp crx);
10878 effect(USE labl);
10879 ins_cost(BRANCH_COST);
10880
10881 // short variant.
10882 ins_short_branch(1);
10883
10884 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10885 size(4);
10886 ins_encode( enc_bc(crx, cmp, labl) );
10887 ins_pipe(pipe_class_default);
10888 %}
10889
10890 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10891 match(CountedLoopEnd cmp crx);
10892 effect(USE labl);
10893 predicate(!false /* TODO: PPC port HB_Schedule */);
10894 ins_cost(BRANCH_COST);
10895
10896 // Long variant.
10897 ins_short_branch(0);
10898
10899 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10900 size(8);
10901 ins_encode( enc_bc_far(crx, cmp, labl) );
10902 ins_pipe(pipe_class_default);
10903 %}
10904
10905 // Conditional Branch used with Power6 scheduler (can be far or short).
10906 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10907 match(CountedLoopEnd cmp crx);
10908 effect(USE labl);
10909 predicate(false /* TODO: PPC port HB_Schedule */);
10910 // Higher cost than `branchCon'.
10911 ins_cost(5*BRANCH_COST);
10912
10913 // Actually size doesn't depend on alignment but on shortening.
10914 ins_variable_size_depending_on_alignment(true);
10915 // Long variant.
10916 ins_short_branch(0);
10917
10918 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10919 size(8); // worst case
10920 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10921 ins_pipe(pipe_class_default);
10922 %}
10923
10924 // ============================================================================
10925 // Java runtime operations, intrinsics and other complex operations.
10926
10927 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10928 // array for an instance of the superklass. Set a hidden internal cache on a
10929 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10930 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10931 //
10932 // GL TODO: Improve this.
10933 // - result should not be a TEMP
10934 // - Add match rule as on sparc avoiding additional Cmp.
10935 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10936 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10937 match(Set result (PartialSubtypeCheck subklass superklass));
10938 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10939 ins_cost(DEFAULT_COST*10);
10940
10941 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10942 ins_encode %{
10943 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10944 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10945 $tmp_klass$$Register, NULL, $result$$Register);
10946 %}
10947 ins_pipe(pipe_class_default);
10948 %}
10949
10950 // inlined locking and unlocking
10951
10952 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10953 match(Set crx (FastLock oop box));
10954 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10955 predicate(!Compile::current()->use_rtm());
10956
10957 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10958 ins_encode %{
10959 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10960 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10961 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10962 UseBiasedLocking && !UseOptoBiasInlining);
10963 // If locking was successfull, crx should indicate 'EQ'.
10964 // The compiler generates a branch to the runtime call to
10965 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10966 %}
10967 ins_pipe(pipe_class_compare);
10968 %}
10969
10970 // Separate version for TM. Use bound register for box to enable USE_KILL.
10971 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10972 match(Set crx (FastLock oop box));
10973 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10974 predicate(Compile::current()->use_rtm());
10975
10976 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10977 ins_encode %{
10978 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10979 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10980 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10981 /*Biased Locking*/ false,
10982 _rtm_counters, _stack_rtm_counters,
10983 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10984 /*TM*/ true, ra_->C->profile_rtm());
10985 // If locking was successfull, crx should indicate 'EQ'.
10986 // The compiler generates a branch to the runtime call to
10987 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10988 %}
10989 ins_pipe(pipe_class_compare);
10990 %}
10991
10992 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10993 match(Set crx (FastUnlock oop box));
10994 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10995 predicate(!Compile::current()->use_rtm());
10996
10997 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10998 ins_encode %{
10999 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11000 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
11001 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11002 UseBiasedLocking && !UseOptoBiasInlining,
11003 false);
11004 // If unlocking was successfull, crx should indicate 'EQ'.
11005 // The compiler generates a branch to the runtime call to
11006 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11007 %}
11008 ins_pipe(pipe_class_compare);
11009 %}
11010
11011 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
11012 match(Set crx (FastUnlock oop box));
11013 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11014 predicate(Compile::current()->use_rtm());
11015
11016 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %}
11017 ins_encode %{
11018 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11019 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
11020 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11021 /*Biased Locking*/ false, /*TM*/ true);
11022 // If unlocking was successfull, crx should indicate 'EQ'.
11023 // The compiler generates a branch to the runtime call to
11024 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11025 %}
11026 ins_pipe(pipe_class_compare);
11027 %}
11028
11029 // Align address.
11030 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11031 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11032
11033 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
11034 size(4);
11035 ins_encode %{
11036 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11037 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11038 %}
11039 ins_pipe(pipe_class_default);
11040 %}
11041
11042 // Array size computation.
11043 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11044 match(Set dst (SubL (CastP2X end) (CastP2X start)));
11045
11046 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
11047 size(4);
11048 ins_encode %{
11049 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11050 __ subf($dst$$Register, $start$$Register, $end$$Register);
11051 %}
11052 ins_pipe(pipe_class_default);
11053 %}
11054
11055 // Clear-array with dynamic array-size.
11056 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11057 match(Set dummy (ClearArray cnt base));
11058 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11059 ins_cost(MEMORY_REF_COST);
11060
11061 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11062
11063 format %{ "ClearArray $cnt, $base" %}
11064 ins_encode %{
11065 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11066 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11067 %}
11068 ins_pipe(pipe_class_default);
11069 %}
11070
11071 // String_IndexOf for needle of length 1.
11072 //
11073 // Match needle into immediate operands: no loadConP node needed. Saves one
11074 // register and two instructions over string_indexOf_imm1Node.
11075 //
11076 // Assumes register result differs from all input registers.
11077 //
11078 // Preserves registers haystack, haycnt
11079 // Kills registers tmp1, tmp2
11080 // Defines registers result
11081 //
11082 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11083 //
11084 // Unfortunately this does not match too often. In many situations the AddP is used
11085 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11086 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11087 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11088 iRegIdst tmp1, iRegIdst tmp2,
11089 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11090 predicate(SpecialStringIndexOf && !CompactStrings); // type check implicit by parameter type, See Matcher::match_rule_supported
11091 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11092
11093 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11094
11095 ins_cost(150);
11096 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11097 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11098
11099 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11100 ins_encode %{
11101 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11102 immPOper *needleOper = (immPOper *)$needleImm;
11103 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11104 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11105
11106 __ string_indexof_1($result$$Register,
11107 $haystack$$Register, $haycnt$$Register,
11108 R0, needle_values->char_at(0),
11109 $tmp1$$Register, $tmp2$$Register);
11110 %}
11111 ins_pipe(pipe_class_compare);
11112 %}
11113
11114 // String_IndexOf for needle of length 1.
11115 //
11116 // Special case requires less registers and emits less instructions.
11117 //
11118 // Assumes register result differs from all input registers.
11119 //
11120 // Preserves registers haystack, haycnt
11121 // Kills registers tmp1, tmp2, needle
11122 // Defines registers result
11123 //
11124 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11125 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11126 rscratch2RegP needle, immI_1 needlecntImm,
11127 iRegIdst tmp1, iRegIdst tmp2,
11128 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11129 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11130 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11131 TEMP tmp1, TEMP tmp2);
11132 // Required for EA: check if it is still a type_array.
11133 predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11134 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11135 ins_cost(180);
11136
11137 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11138
11139 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11140 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11141 ins_encode %{
11142 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11143 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11144 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11145 guarantee(needle_values, "sanity");
11146 if (needle_values != NULL) {
11147 __ string_indexof_1($result$$Register,
11148 $haystack$$Register, $haycnt$$Register,
11149 R0, needle_values->char_at(0),
11150 $tmp1$$Register, $tmp2$$Register);
11151 } else {
11152 __ string_indexof_1($result$$Register,
11153 $haystack$$Register, $haycnt$$Register,
11154 $needle$$Register, 0,
11155 $tmp1$$Register, $tmp2$$Register);
11156 }
11157 %}
11158 ins_pipe(pipe_class_compare);
11159 %}
11160
11161 // String_IndexOf.
11162 //
11163 // Length of needle as immediate. This saves instruction loading constant needle
11164 // length.
11165 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11166 // completely or do it in vector instruction. This should save registers for
11167 // needlecnt and needle.
11168 //
11169 // Assumes register result differs from all input registers.
11170 // Overwrites haycnt, needlecnt.
11171 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11172 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11173 iRegPsrc needle, uimmI15 needlecntImm,
11174 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11175 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11176 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11177 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11178 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11179 // Required for EA: check if it is still a type_array.
11180 predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11181 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11182 ins_cost(250);
11183
11184 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11185
11186 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11187 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11188 ins_encode %{
11189 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11190 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11191 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11192
11193 __ string_indexof($result$$Register,
11194 $haystack$$Register, $haycnt$$Register,
11195 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11196 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11197 %}
11198 ins_pipe(pipe_class_compare);
11199 %}
11200
11201 // StrIndexOf node.
11202 //
11203 // Assumes register result differs from all input registers.
11204 // Overwrites haycnt, needlecnt.
11205 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11206 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11207 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11208 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11209 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11210 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11211 TEMP_DEF result,
11212 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11213 predicate(SpecialStringIndexOf && !CompactStrings); // See Matcher::match_rule_supported.
11214 ins_cost(300);
11215
11216 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11217
11218 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11219 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11220 ins_encode %{
11221 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11222 __ string_indexof($result$$Register,
11223 $haystack$$Register, $haycnt$$Register,
11224 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11225 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11226 %}
11227 ins_pipe(pipe_class_compare);
11228 %}
11229
11230 // String equals with immediate.
11231 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11232 iRegPdst tmp1, iRegPdst tmp2,
11233 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11234 match(Set result (StrEquals (Binary str1 str2) cntImm));
11235 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11236 KILL cr0, KILL cr6, KILL ctr);
11237 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported.
11238 ins_cost(250);
11239
11240 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11241
11242 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11243 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11244 ins_encode %{
11245 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11246 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11247 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11248 %}
11249 ins_pipe(pipe_class_compare);
11250 %}
11251
11252 // String equals.
11253 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11254 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11255 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11256 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11257 match(Set result (StrEquals (Binary str1 str2) cnt));
11258 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11259 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11260 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported.
11261 ins_cost(300);
11262
11263 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11264
11265 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11266 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11267 ins_encode %{
11268 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11269 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11270 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11271 %}
11272 ins_pipe(pipe_class_compare);
11273 %}
11274
11275 // String compare.
11276 // Char[] pointers are passed in.
11277 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11278 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11279 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11280 predicate(!CompactStrings);
11281 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11282 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11283 ins_cost(300);
11284
11285 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11286
11287 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11288 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11289 ins_encode %{
11290 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11291 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11292 $result$$Register, $tmp$$Register);
11293 %}
11294 ins_pipe(pipe_class_compare);
11295 %}
11296
11297 //---------- Min/Max Instructions ---------------------------------------------
11298
11299 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11300 match(Set dst (MinI src1 src2));
11301 ins_cost(DEFAULT_COST*6);
11302
11303 expand %{
11304 iRegLdst src1s;
11305 iRegLdst src2s;
11306 iRegLdst diff;
11307 iRegLdst sm;
11308 iRegLdst doz; // difference or zero
11309 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11310 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11311 subL_reg_reg(diff, src2s, src1s);
11312 // Need to consider >=33 bit result, therefore we need signmaskL.
11313 signmask64L_regL(sm, diff);
11314 andL_reg_reg(doz, diff, sm); // <=0
11315 addI_regL_regL(dst, doz, src1s);
11316 %}
11317 %}
11318
11319 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11320 match(Set dst (MaxI src1 src2));
11321 ins_cost(DEFAULT_COST*6);
11322
11323 expand %{
11324 iRegLdst src1s;
11325 iRegLdst src2s;
11326 iRegLdst diff;
11327 iRegLdst sm;
11328 iRegLdst doz; // difference or zero
11329 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11330 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11331 subL_reg_reg(diff, src2s, src1s);
11332 // Need to consider >=33 bit result, therefore we need signmaskL.
11333 signmask64L_regL(sm, diff);
11334 andcL_reg_reg(doz, diff, sm); // >=0
11335 addI_regL_regL(dst, doz, src1s);
11336 %}
11337 %}
11338
11339 //---------- Population Count Instructions ------------------------------------
11340
11341 // Popcnt for Power7.
11342 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11343 match(Set dst (PopCountI src));
11344 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11345 ins_cost(DEFAULT_COST);
11346
11347 format %{ "POPCNTW $dst, $src" %}
11348 size(4);
11349 ins_encode %{
11350 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11351 __ popcntw($dst$$Register, $src$$Register);
11352 %}
11353 ins_pipe(pipe_class_default);
11354 %}
11355
11356 // Popcnt for Power7.
11357 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11358 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11359 match(Set dst (PopCountL src));
11360 ins_cost(DEFAULT_COST);
11361
11362 format %{ "POPCNTD $dst, $src" %}
11363 size(4);
11364 ins_encode %{
11365 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11366 __ popcntd($dst$$Register, $src$$Register);
11367 %}
11368 ins_pipe(pipe_class_default);
11369 %}
11370
11371 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11372 match(Set dst (CountLeadingZerosI src));
11373 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11374 ins_cost(DEFAULT_COST);
11375
11376 format %{ "CNTLZW $dst, $src" %}
11377 size(4);
11378 ins_encode %{
11379 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11380 __ cntlzw($dst$$Register, $src$$Register);
11381 %}
11382 ins_pipe(pipe_class_default);
11383 %}
11384
11385 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11386 match(Set dst (CountLeadingZerosL src));
11387 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11388 ins_cost(DEFAULT_COST);
11389
11390 format %{ "CNTLZD $dst, $src" %}
11391 size(4);
11392 ins_encode %{
11393 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11394 __ cntlzd($dst$$Register, $src$$Register);
11395 %}
11396 ins_pipe(pipe_class_default);
11397 %}
11398
11399 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11400 // no match-rule, false predicate
11401 effect(DEF dst, USE src);
11402 predicate(false);
11403
11404 format %{ "CNTLZD $dst, $src" %}
11405 size(4);
11406 ins_encode %{
11407 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11408 __ cntlzd($dst$$Register, $src$$Register);
11409 %}
11410 ins_pipe(pipe_class_default);
11411 %}
11412
11413 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11414 match(Set dst (CountTrailingZerosI src));
11415 predicate(UseCountLeadingZerosInstructionsPPC64);
11416 ins_cost(DEFAULT_COST);
11417
11418 expand %{
11419 immI16 imm1 %{ (int)-1 %}
11420 immI16 imm2 %{ (int)32 %}
11421 immI_minus1 m1 %{ -1 %}
11422 iRegIdst tmpI1;
11423 iRegIdst tmpI2;
11424 iRegIdst tmpI3;
11425 addI_reg_imm16(tmpI1, src, imm1);
11426 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11427 countLeadingZerosI(tmpI3, tmpI2);
11428 subI_imm16_reg(dst, imm2, tmpI3);
11429 %}
11430 %}
11431
11432 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11433 match(Set dst (CountTrailingZerosL src));
11434 predicate(UseCountLeadingZerosInstructionsPPC64);
11435 ins_cost(DEFAULT_COST);
11436
11437 expand %{
11438 immL16 imm1 %{ (long)-1 %}
11439 immI16 imm2 %{ (int)64 %}
11440 iRegLdst tmpL1;
11441 iRegLdst tmpL2;
11442 iRegIdst tmpL3;
11443 addL_reg_imm16(tmpL1, src, imm1);
11444 andcL_reg_reg(tmpL2, tmpL1, src);
11445 countLeadingZerosL(tmpL3, tmpL2);
11446 subI_imm16_reg(dst, imm2, tmpL3);
11447 %}
11448 %}
11449
11450 // Expand nodes for byte_reverse_int.
11451 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11452 effect(DEF dst, USE src, USE pos, USE shift);
11453 predicate(false);
11454
11455 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11456 size(4);
11457 ins_encode %{
11458 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11459 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11460 %}
11461 ins_pipe(pipe_class_default);
11462 %}
11463
11464 // As insrwi_a, but with USE_DEF.
11465 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11466 effect(USE_DEF dst, USE src, USE pos, USE shift);
11467 predicate(false);
11468
11469 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11470 size(4);
11471 ins_encode %{
11472 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11473 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11474 %}
11475 ins_pipe(pipe_class_default);
11476 %}
11477
11478 // Just slightly faster than java implementation.
11479 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11480 match(Set dst (ReverseBytesI src));
11481 predicate(UseCountLeadingZerosInstructionsPPC64);
11482 ins_cost(DEFAULT_COST);
11483
11484 expand %{
11485 immI16 imm24 %{ (int) 24 %}
11486 immI16 imm16 %{ (int) 16 %}
11487 immI16 imm8 %{ (int) 8 %}
11488 immI16 imm4 %{ (int) 4 %}
11489 immI16 imm0 %{ (int) 0 %}
11490 iRegLdst tmpI1;
11491 iRegLdst tmpI2;
11492 iRegLdst tmpI3;
11493
11494 urShiftI_reg_imm(tmpI1, src, imm24);
11495 insrwi_a(dst, tmpI1, imm24, imm8);
11496 urShiftI_reg_imm(tmpI2, src, imm16);
11497 insrwi(dst, tmpI2, imm8, imm16);
11498 urShiftI_reg_imm(tmpI3, src, imm8);
11499 insrwi(dst, tmpI3, imm8, imm8);
11500 insrwi(dst, src, imm0, imm8);
11501 %}
11502 %}
11503
11504 //---------- Replicate Vector Instructions ------------------------------------
11505
11506 // Insrdi does replicate if src == dst.
11507 instruct repl32(iRegLdst dst) %{
11508 predicate(false);
11509 effect(USE_DEF dst);
11510
11511 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11512 size(4);
11513 ins_encode %{
11514 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11515 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11516 %}
11517 ins_pipe(pipe_class_default);
11518 %}
11519
11520 // Insrdi does replicate if src == dst.
11521 instruct repl48(iRegLdst dst) %{
11522 predicate(false);
11523 effect(USE_DEF dst);
11524
11525 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11526 size(4);
11527 ins_encode %{
11528 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11529 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11530 %}
11531 ins_pipe(pipe_class_default);
11532 %}
11533
11534 // Insrdi does replicate if src == dst.
11535 instruct repl56(iRegLdst dst) %{
11536 predicate(false);
11537 effect(USE_DEF dst);
11538
11539 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11540 size(4);
11541 ins_encode %{
11542 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11543 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11544 %}
11545 ins_pipe(pipe_class_default);
11546 %}
11547
11548 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11549 match(Set dst (ReplicateB src));
11550 predicate(n->as_Vector()->length() == 8);
11551 expand %{
11552 moveReg(dst, src);
11553 repl56(dst);
11554 repl48(dst);
11555 repl32(dst);
11556 %}
11557 %}
11558
11559 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11560 match(Set dst (ReplicateB zero));
11561 predicate(n->as_Vector()->length() == 8);
11562 format %{ "LI $dst, #0 \t// replicate8B" %}
11563 size(4);
11564 ins_encode %{
11565 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11566 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11567 %}
11568 ins_pipe(pipe_class_default);
11569 %}
11570
11571 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11572 match(Set dst (ReplicateB src));
11573 predicate(n->as_Vector()->length() == 8);
11574 format %{ "LI $dst, #-1 \t// replicate8B" %}
11575 size(4);
11576 ins_encode %{
11577 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11578 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11579 %}
11580 ins_pipe(pipe_class_default);
11581 %}
11582
11583 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11584 match(Set dst (ReplicateS src));
11585 predicate(n->as_Vector()->length() == 4);
11586 expand %{
11587 moveReg(dst, src);
11588 repl48(dst);
11589 repl32(dst);
11590 %}
11591 %}
11592
11593 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11594 match(Set dst (ReplicateS zero));
11595 predicate(n->as_Vector()->length() == 4);
11596 format %{ "LI $dst, #0 \t// replicate4C" %}
11597 size(4);
11598 ins_encode %{
11599 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11600 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11601 %}
11602 ins_pipe(pipe_class_default);
11603 %}
11604
11605 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11606 match(Set dst (ReplicateS src));
11607 predicate(n->as_Vector()->length() == 4);
11608 format %{ "LI $dst, -1 \t// replicate4C" %}
11609 size(4);
11610 ins_encode %{
11611 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11612 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11613 %}
11614 ins_pipe(pipe_class_default);
11615 %}
11616
11617 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11618 match(Set dst (ReplicateI src));
11619 predicate(n->as_Vector()->length() == 2);
11620 ins_cost(2 * DEFAULT_COST);
11621 expand %{
11622 moveReg(dst, src);
11623 repl32(dst);
11624 %}
11625 %}
11626
11627 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11628 match(Set dst (ReplicateI zero));
11629 predicate(n->as_Vector()->length() == 2);
11630 format %{ "LI $dst, #0 \t// replicate4C" %}
11631 size(4);
11632 ins_encode %{
11633 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11634 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11635 %}
11636 ins_pipe(pipe_class_default);
11637 %}
11638
11639 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11640 match(Set dst (ReplicateI src));
11641 predicate(n->as_Vector()->length() == 2);
11642 format %{ "LI $dst, -1 \t// replicate4C" %}
11643 size(4);
11644 ins_encode %{
11645 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11646 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11647 %}
11648 ins_pipe(pipe_class_default);
11649 %}
11650
11651 // Move float to int register via stack, replicate.
11652 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11653 match(Set dst (ReplicateF src));
11654 predicate(n->as_Vector()->length() == 2);
11655 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11656 expand %{
11657 stackSlotL tmpS;
11658 iRegIdst tmpI;
11659 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11660 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11661 moveReg(dst, tmpI); // Move int to long reg.
11662 repl32(dst); // Replicate bitpattern.
11663 %}
11664 %}
11665
11666 // Replicate scalar constant to packed float values in Double register
11667 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11668 match(Set dst (ReplicateF src));
11669 predicate(n->as_Vector()->length() == 2);
11670 ins_cost(5 * DEFAULT_COST);
11671
11672 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11673 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11674 %}
11675
11676 // Replicate scalar zero constant to packed float values in Double register
11677 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11678 match(Set dst (ReplicateF zero));
11679 predicate(n->as_Vector()->length() == 2);
11680
11681 format %{ "LI $dst, #0 \t// replicate2F" %}
11682 ins_encode %{
11683 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11684 __ li($dst$$Register, 0x0);
11685 %}
11686 ins_pipe(pipe_class_default);
11687 %}
11688
11689
11690 //----------Overflow Math Instructions-----------------------------------------
11691
11692 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
11693 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
11694 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
11695
11696 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11697 match(Set cr0 (OverflowAddL op1 op2));
11698
11699 format %{ "add_ $op1, $op2\t# overflow check long" %}
11700 ins_encode %{
11701 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11702 __ li(R0, 0);
11703 __ mtxer(R0); // clear XER.SO
11704 __ addo_(R0, $op1$$Register, $op2$$Register);
11705 %}
11706 ins_pipe(pipe_class_default);
11707 %}
11708
11709 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11710 match(Set cr0 (OverflowSubL op1 op2));
11711
11712 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %}
11713 ins_encode %{
11714 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11715 __ li(R0, 0);
11716 __ mtxer(R0); // clear XER.SO
11717 __ subfo_(R0, $op2$$Register, $op1$$Register);
11718 %}
11719 ins_pipe(pipe_class_default);
11720 %}
11721
11722 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
11723 match(Set cr0 (OverflowSubL zero op2));
11724
11725 format %{ "nego_ R0, $op2\t# overflow check long" %}
11726 ins_encode %{
11727 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11728 __ li(R0, 0);
11729 __ mtxer(R0); // clear XER.SO
11730 __ nego_(R0, $op2$$Register);
11731 %}
11732 ins_pipe(pipe_class_default);
11733 %}
11734
11735 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11736 match(Set cr0 (OverflowMulL op1 op2));
11737
11738 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
11739 ins_encode %{
11740 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11741 __ li(R0, 0);
11742 __ mtxer(R0); // clear XER.SO
11743 __ mulldo_(R0, $op1$$Register, $op2$$Register);
11744 %}
11745 ins_pipe(pipe_class_default);
11746 %}
11747
11748
11749 // ============================================================================
11750 // Safepoint Instruction
11751
11752 instruct safePoint_poll(iRegPdst poll) %{
11753 match(SafePoint poll);
11754 predicate(LoadPollAddressFromThread);
11755
11756 // It caused problems to add the effect that r0 is killed, but this
11757 // effect no longer needs to be mentioned, since r0 is not contained
11758 // in a reg_class.
11759
11760 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11761 size(4);
11762 ins_encode( enc_poll(0x0, poll) );
11763 ins_pipe(pipe_class_default);
11764 %}
11765
11766 // Safepoint without per-thread support. Load address of page to poll
11767 // as constant.
11768 // Rscratch2RegP is R12.
11769 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11770 // a seperate node so that the oop map is at the right location.
11771 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11772 match(SafePoint poll);
11773 predicate(!LoadPollAddressFromThread);
11774
11775 // It caused problems to add the effect that r0 is killed, but this
11776 // effect no longer needs to be mentioned, since r0 is not contained
11777 // in a reg_class.
11778
11779 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11780 ins_encode( enc_poll(0x0, poll) );
11781 ins_pipe(pipe_class_default);
11782 %}
11783
11784 // ============================================================================
11785 // Call Instructions
11786
11787 // Call Java Static Instruction
11788
11789 // Schedulable version of call static node.
11790 instruct CallStaticJavaDirect(method meth) %{
11791 match(CallStaticJava);
11792 effect(USE meth);
11793 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11794 ins_cost(CALL_COST);
11795
11796 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11797
11798 format %{ "CALL,static $meth \t// ==> " %}
11799 size(4);
11800 ins_encode( enc_java_static_call(meth) );
11801 ins_pipe(pipe_class_call);
11802 %}
11803
11804 // Schedulable version of call static node.
11805 instruct CallStaticJavaDirectHandle(method meth) %{
11806 match(CallStaticJava);
11807 effect(USE meth);
11808 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11809 ins_cost(CALL_COST);
11810
11811 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11812
11813 format %{ "CALL,static $meth \t// ==> " %}
11814 ins_encode( enc_java_handle_call(meth) );
11815 ins_pipe(pipe_class_call);
11816 %}
11817
11818 // Call Java Dynamic Instruction
11819
11820 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11821 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11822 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11823 // The call destination must still be placed in the constant pool.
11824 instruct CallDynamicJavaDirectSched(method meth) %{
11825 match(CallDynamicJava); // To get all the data fields we need ...
11826 effect(USE meth);
11827 predicate(false); // ... but never match.
11828
11829 ins_field_load_ic_hi_node(loadConL_hiNode*);
11830 ins_field_load_ic_node(loadConLNode*);
11831 ins_num_consts(1 /* 1 patchable constant: call destination */);
11832
11833 format %{ "BL \t// dynamic $meth ==> " %}
11834 size(4);
11835 ins_encode( enc_java_dynamic_call_sched(meth) );
11836 ins_pipe(pipe_class_call);
11837 %}
11838
11839 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11840 // We use postalloc expanded calls if we use inline caches
11841 // and do not update method data.
11842 //
11843 // This instruction has two constants: inline cache (IC) and call destination.
11844 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11845 // one constant.
11846 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11847 match(CallDynamicJava);
11848 effect(USE meth);
11849 predicate(UseInlineCaches);
11850 ins_cost(CALL_COST);
11851
11852 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11853
11854 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11855 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11856 %}
11857
11858 // Compound version of call dynamic java
11859 // We use postalloc expanded calls if we use inline caches
11860 // and do not update method data.
11861 instruct CallDynamicJavaDirect(method meth) %{
11862 match(CallDynamicJava);
11863 effect(USE meth);
11864 predicate(!UseInlineCaches);
11865 ins_cost(CALL_COST);
11866
11867 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11868 ins_num_consts(4);
11869
11870 format %{ "CALL,dynamic $meth \t// ==> " %}
11871 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11872 ins_pipe(pipe_class_call);
11873 %}
11874
11875 // Call Runtime Instruction
11876
11877 instruct CallRuntimeDirect(method meth) %{
11878 match(CallRuntime);
11879 effect(USE meth);
11880 ins_cost(CALL_COST);
11881
11882 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11883 // env for callee, C-toc.
11884 ins_num_consts(3);
11885
11886 format %{ "CALL,runtime" %}
11887 ins_encode( enc_java_to_runtime_call(meth) );
11888 ins_pipe(pipe_class_call);
11889 %}
11890
11891 // Call Leaf
11892
11893 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11894 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11895 effect(DEF dst, USE src);
11896
11897 ins_num_consts(1);
11898
11899 format %{ "MTCTR $src" %}
11900 size(4);
11901 ins_encode( enc_leaf_call_mtctr(src) );
11902 ins_pipe(pipe_class_default);
11903 %}
11904
11905 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11906 instruct CallLeafDirect(method meth) %{
11907 match(CallLeaf); // To get the data all the data fields we need ...
11908 effect(USE meth);
11909 predicate(false); // but never match.
11910
11911 format %{ "BCTRL \t// leaf call $meth ==> " %}
11912 size(4);
11913 ins_encode %{
11914 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11915 __ bctrl();
11916 %}
11917 ins_pipe(pipe_class_call);
11918 %}
11919
11920 // postalloc expand of CallLeafDirect.
11921 // Load adress to call from TOC, then bl to it.
11922 instruct CallLeafDirect_Ex(method meth) %{
11923 match(CallLeaf);
11924 effect(USE meth);
11925 ins_cost(CALL_COST);
11926
11927 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11928 // env for callee, C-toc.
11929 ins_num_consts(3);
11930
11931 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11932 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11933 %}
11934
11935 // Call runtime without safepoint - same as CallLeaf.
11936 // postalloc expand of CallLeafNoFPDirect.
11937 // Load adress to call from TOC, then bl to it.
11938 instruct CallLeafNoFPDirect_Ex(method meth) %{
11939 match(CallLeafNoFP);
11940 effect(USE meth);
11941 ins_cost(CALL_COST);
11942
11943 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11944 // env for callee, C-toc.
11945 ins_num_consts(3);
11946
11947 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11948 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11949 %}
11950
11951 // Tail Call; Jump from runtime stub to Java code.
11952 // Also known as an 'interprocedural jump'.
11953 // Target of jump will eventually return to caller.
11954 // TailJump below removes the return address.
11955 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11956 match(TailCall jump_target method_oop);
11957 ins_cost(CALL_COST);
11958
11959 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11960 "BCTR \t// tail call" %}
11961 size(8);
11962 ins_encode %{
11963 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11964 __ mtctr($jump_target$$Register);
11965 __ bctr();
11966 %}
11967 ins_pipe(pipe_class_call);
11968 %}
11969
11970 // Return Instruction
11971 instruct Ret() %{
11972 match(Return);
11973 format %{ "BLR \t// branch to link register" %}
11974 size(4);
11975 ins_encode %{
11976 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11977 // LR is restored in MachEpilogNode. Just do the RET here.
11978 __ blr();
11979 %}
11980 ins_pipe(pipe_class_default);
11981 %}
11982
11983 // Tail Jump; remove the return address; jump to target.
11984 // TailCall above leaves the return address around.
11985 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11986 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11987 // "restore" before this instruction (in Epilogue), we need to materialize it
11988 // in %i0.
11989 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11990 match(TailJump jump_target ex_oop);
11991 ins_cost(CALL_COST);
11992
11993 format %{ "LD R4_ARG2 = LR\n\t"
11994 "MTCTR $jump_target\n\t"
11995 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11996 size(12);
11997 ins_encode %{
11998 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11999 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
12000 __ mtctr($jump_target$$Register);
12001 __ bctr();
12002 %}
12003 ins_pipe(pipe_class_call);
12004 %}
12005
12006 // Create exception oop: created by stack-crawling runtime code.
12007 // Created exception is now available to this handler, and is setup
12008 // just prior to jumping to this handler. No code emitted.
12009 instruct CreateException(rarg1RegP ex_oop) %{
12010 match(Set ex_oop (CreateEx));
12011 ins_cost(0);
12012
12013 format %{ " -- \t// exception oop; no code emitted" %}
12014 size(0);
12015 ins_encode( /*empty*/ );
12016 ins_pipe(pipe_class_default);
12017 %}
12018
12019 // Rethrow exception: The exception oop will come in the first
12020 // argument position. Then JUMP (not call) to the rethrow stub code.
12021 instruct RethrowException() %{
12022 match(Rethrow);
12023 ins_cost(CALL_COST);
12024
12025 format %{ "Jmp rethrow_stub" %}
12026 ins_encode %{
12027 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12028 cbuf.set_insts_mark();
12029 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12030 %}
12031 ins_pipe(pipe_class_call);
12032 %}
12033
12034 // Die now.
12035 instruct ShouldNotReachHere() %{
12036 match(Halt);
12037 ins_cost(CALL_COST);
12038
12039 format %{ "ShouldNotReachHere" %}
12040 size(4);
12041 ins_encode %{
12042 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12043 __ trap_should_not_reach_here();
12044 %}
12045 ins_pipe(pipe_class_default);
12046 %}
12047
12048 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
12049 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12050 // Get a DEF on threadRegP, no costs, no encoding, use
12051 // 'ins_should_rematerialize(true)' to avoid spilling.
12052 instruct tlsLoadP(threadRegP dst) %{
12053 match(Set dst (ThreadLocal));
12054 ins_cost(0);
12055
12056 ins_should_rematerialize(true);
12057
12058 format %{ " -- \t// $dst=Thread::current(), empty" %}
12059 size(0);
12060 ins_encode( /*empty*/ );
12061 ins_pipe(pipe_class_empty);
12062 %}
12063
12064 //---Some PPC specific nodes---------------------------------------------------
12065
12066 // Stop a group.
12067 instruct endGroup() %{
12068 ins_cost(0);
12069
12070 ins_is_nop(true);
12071
12072 format %{ "End Bundle (ori r1, r1, 0)" %}
12073 size(4);
12074 ins_encode %{
12075 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12076 __ endgroup();
12077 %}
12078 ins_pipe(pipe_class_default);
12079 %}
12080
12081 // Nop instructions
12082
12083 instruct fxNop() %{
12084 ins_cost(0);
12085
12086 ins_is_nop(true);
12087
12088 format %{ "fxNop" %}
12089 size(4);
12090 ins_encode %{
12091 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12092 __ nop();
12093 %}
12094 ins_pipe(pipe_class_default);
12095 %}
12096
12097 instruct fpNop0() %{
12098 ins_cost(0);
12099
12100 ins_is_nop(true);
12101
12102 format %{ "fpNop0" %}
12103 size(4);
12104 ins_encode %{
12105 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12106 __ fpnop0();
12107 %}
12108 ins_pipe(pipe_class_default);
12109 %}
12110
12111 instruct fpNop1() %{
12112 ins_cost(0);
12113
12114 ins_is_nop(true);
12115
12116 format %{ "fpNop1" %}
12117 size(4);
12118 ins_encode %{
12119 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12120 __ fpnop1();
12121 %}
12122 ins_pipe(pipe_class_default);
12123 %}
12124
12125 instruct brNop0() %{
12126 ins_cost(0);
12127 size(4);
12128 format %{ "brNop0" %}
12129 ins_encode %{
12130 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12131 __ brnop0();
12132 %}
12133 ins_is_nop(true);
12134 ins_pipe(pipe_class_default);
12135 %}
12136
12137 instruct brNop1() %{
12138 ins_cost(0);
12139
12140 ins_is_nop(true);
12141
12142 format %{ "brNop1" %}
12143 size(4);
12144 ins_encode %{
12145 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12146 __ brnop1();
12147 %}
12148 ins_pipe(pipe_class_default);
12149 %}
12150
12151 instruct brNop2() %{
12152 ins_cost(0);
12153
12154 ins_is_nop(true);
12155
12156 format %{ "brNop2" %}
12157 size(4);
12158 ins_encode %{
12159 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12160 __ brnop2();
12161 %}
12162 ins_pipe(pipe_class_default);
12163 %}
12164
12165 //----------PEEPHOLE RULES-----------------------------------------------------
12166 // These must follow all instruction definitions as they use the names
12167 // defined in the instructions definitions.
12168 //
12169 // peepmatch ( root_instr_name [preceeding_instruction]* );
12170 //
12171 // peepconstraint %{
12172 // (instruction_number.operand_name relational_op instruction_number.operand_name
12173 // [, ...] );
12174 // // instruction numbers are zero-based using left to right order in peepmatch
12175 //
12176 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12177 // // provide an instruction_number.operand_name for each operand that appears
12178 // // in the replacement instruction's match rule
12179 //
12180 // ---------VM FLAGS---------------------------------------------------------
12181 //
12182 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12183 //
12184 // Each peephole rule is given an identifying number starting with zero and
12185 // increasing by one in the order seen by the parser. An individual peephole
12186 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12187 // on the command-line.
12188 //
12189 // ---------CURRENT LIMITATIONS----------------------------------------------
12190 //
12191 // Only match adjacent instructions in same basic block
12192 // Only equality constraints
12193 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12194 // Only one replacement instruction
12195 //
12196 // ---------EXAMPLE----------------------------------------------------------
12197 //
12198 // // pertinent parts of existing instructions in architecture description
12199 // instruct movI(eRegI dst, eRegI src) %{
12200 // match(Set dst (CopyI src));
12201 // %}
12202 //
12203 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12204 // match(Set dst (AddI dst src));
12205 // effect(KILL cr);
12206 // %}
12207 //
12208 // // Change (inc mov) to lea
12209 // peephole %{
12210 // // increment preceeded by register-register move
12211 // peepmatch ( incI_eReg movI );
12212 // // require that the destination register of the increment
12213 // // match the destination register of the move
12214 // peepconstraint ( 0.dst == 1.dst );
12215 // // construct a replacement instruction that sets
12216 // // the destination to ( move's source register + one )
12217 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12218 // %}
12219 //
12220 // Implementation no longer uses movX instructions since
12221 // machine-independent system no longer uses CopyX nodes.
12222 //
12223 // peephole %{
12224 // peepmatch ( incI_eReg movI );
12225 // peepconstraint ( 0.dst == 1.dst );
12226 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12227 // %}
12228 //
12229 // peephole %{
12230 // peepmatch ( decI_eReg movI );
12231 // peepconstraint ( 0.dst == 1.dst );
12232 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12233 // %}
12234 //
12235 // peephole %{
12236 // peepmatch ( addI_eReg_imm movI );
12237 // peepconstraint ( 0.dst == 1.dst );
12238 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12239 // %}
12240 //
12241 // peephole %{
12242 // peepmatch ( addP_eReg_imm movP );
12243 // peepconstraint ( 0.dst == 1.dst );
12244 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12245 // %}
12246
12247 // // Change load of spilled value to only a spill
12248 // instruct storeI(memory mem, eRegI src) %{
12249 // match(Set mem (StoreI mem src));
12250 // %}
12251 //
12252 // instruct loadI(eRegI dst, memory mem) %{
12253 // match(Set dst (LoadI mem));
12254 // %}
12255 //
12256 peephole %{
12257 peepmatch ( loadI storeI );
12258 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12259 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12260 %}
12261
12262 peephole %{
12263 peepmatch ( loadL storeL );
12264 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12265 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12266 %}
12267
12268 peephole %{
12269 peepmatch ( loadP storeP );
12270 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12271 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12272 %}
12273
12274 //----------SMARTSPILL RULES---------------------------------------------------
12275 // These must follow all instruction definitions as they use the names
12276 // defined in the instructions definitions.