1 // 2 // Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved. 3 // Copyright 2012, 2015 SAP AG. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 // 25 26 // 27 // PPC64 Architecture Description File 28 // 29 30 //----------REGISTER DEFINITION BLOCK------------------------------------------ 31 // This information is used by the matcher and the register allocator to 32 // describe individual registers and classes of registers within the target 33 // architecture. 34 register %{ 35 //----------Architecture Description Register Definitions---------------------- 36 // General Registers 37 // "reg_def" name (register save type, C convention save type, 38 // ideal register type, encoding); 39 // 40 // Register Save Types: 41 // 42 // NS = No-Save: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, & 44 // that they do not need to be saved at call sites. 45 // 46 // SOC = Save-On-Call: The register allocator assumes that these registers 47 // can be used without saving upon entry to the method, 48 // but that they must be saved at call sites. 49 // These are called "volatiles" on ppc. 50 // 51 // SOE = Save-On-Entry: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, but they do not need to be saved at call 54 // sites. 55 // These are called "nonvolatiles" on ppc. 56 // 57 // AS = Always-Save: The register allocator assumes that these registers 58 // must be saved before using them upon entry to the 59 // method, & that they must be saved at call sites. 60 // 61 // Ideal Register Type is used to determine how to save & restore a 62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 64 // 65 // The encoding number is the actual bit-pattern placed into the opcodes. 66 // 67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI 68 // Supplement Version 1.7 as of 2003-10-29. 69 // 70 // For each 64-bit register we must define two registers: the register 71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', 72 // e.g. R3_H, which is needed by the allocator, but is not used 73 // for stores, loads, etc. 74 75 // ---------------------------- 76 // Integer/Long Registers 77 // ---------------------------- 78 79 // PPC64 has 32 64-bit integer registers. 80 81 // types: v = volatile, nv = non-volatile, s = system 82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs 83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); 84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP 85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); 86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC 87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); 88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret 89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); 90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); 92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); 94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); 96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); 98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); 100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); 102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); 104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch 105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); 106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch 107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); 108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id 109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); 110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv 111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); 112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv 113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); 114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv 115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); 116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv 117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); 118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv 119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); 120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv 121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); 122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv 123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); 124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv 125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); 126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv 127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); 128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv 129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); 130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv 131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); 132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv 133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); 134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv 135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); 136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv 137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); 138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv 139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); 140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv 141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); 142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv 143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); 144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv 145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); 146 147 148 // ---------------------------- 149 // Float/Double Registers 150 // ---------------------------- 151 152 // Double Registers 153 // The rules of ADL require that double registers be defined in pairs. 154 // Each pair must be two 32-bit values, but not necessarily a pair of 155 // single float registers. In each pair, ADLC-assigned register numbers 156 // must be adjacent, with the lower number even. Finally, when the 157 // CPU stores such a register pair to memory, the word associated with 158 // the lower ADLC-assigned number must be stored to the lower address. 159 160 // PPC64 has 32 64-bit floating-point registers. Each can store a single 161 // or double precision floating-point value. 162 163 // types: v = volatile, nv = non-volatile, s = system 164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch 165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); 166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret 167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); 168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); 170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); 172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); 174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); 176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); 178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); 180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); 182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); 184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); 186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); 188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); 190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); 192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv 193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); 194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv 195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); 196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv 197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); 198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv 199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); 200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv 201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); 202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv 203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); 204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv 205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); 206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv 207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); 208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv 209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); 210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv 211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); 212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv 213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); 214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv 215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); 216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv 217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); 218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv 219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); 220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv 221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); 222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv 223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); 224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv 225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); 226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv 227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); 228 229 // ---------------------------- 230 // Special Registers 231 // ---------------------------- 232 233 // Condition Codes Flag Registers 234 235 // PPC64 has 8 condition code "registers" which are all contained 236 // in the CR register. 237 238 // types: v = volatile, nv = non-volatile, s = system 239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v 240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v 241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv 242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv 243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv 244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v 245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v 246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v 247 248 // Special registers of PPC64 249 250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v 251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v 252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v 253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v 254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v 255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v 256 257 258 // ---------------------------- 259 // Specify priority of register selection within phases of register 260 // allocation. Highest priority is first. A useful heuristic is to 261 // give registers a low priority when they are required by machine 262 // instructions, like EAX and EDX on I486, and choose no-save registers 263 // before save-on-call, & save-on-call before save-on-entry. Registers 264 // which participate in fixed calling sequences should come last. 265 // Registers which are used as pairs must fall on an even boundary. 266 267 // It's worth about 1% on SPEC geomean to get this right. 268 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g. 271 // R3_num. Therefore, R3_num may not be (and in reality is not) 272 // the same as R3->encoding()! Furthermore, we cannot make any 273 // assumptions on ordering, e.g. R3_num may be less than R2_num. 274 // Additionally, the function 275 // static enum RC rc_class(OptoReg::Name reg ) 276 // maps a given <register>_num value to its chunk type (except for flags) 277 // and its current implementation relies on chunk0 and chunk1 having a 278 // size of 64 each. 279 280 // If you change this allocation class, please have a look at the 281 // default values for the parameters RoundRobinIntegerRegIntervalStart 282 // and RoundRobinFloatRegIntervalStart 283 284 alloc_class chunk0 ( 285 // Chunk0 contains *all* 64 integer registers halves. 286 287 // "non-volatile" registers 288 R14, R14_H, 289 R15, R15_H, 290 R17, R17_H, 291 R18, R18_H, 292 R19, R19_H, 293 R20, R20_H, 294 R21, R21_H, 295 R22, R22_H, 296 R23, R23_H, 297 R24, R24_H, 298 R25, R25_H, 299 R26, R26_H, 300 R27, R27_H, 301 R28, R28_H, 302 R29, R29_H, 303 R30, R30_H, 304 R31, R31_H, 305 306 // scratch/special registers 307 R11, R11_H, 308 R12, R12_H, 309 310 // argument registers 311 R10, R10_H, 312 R9, R9_H, 313 R8, R8_H, 314 R7, R7_H, 315 R6, R6_H, 316 R5, R5_H, 317 R4, R4_H, 318 R3, R3_H, 319 320 // special registers, not available for allocation 321 R16, R16_H, // R16_thread 322 R13, R13_H, // system thread id 323 R2, R2_H, // may be used for TOC 324 R1, R1_H, // SP 325 R0, R0_H // R0 (scratch) 326 ); 327 328 // If you change this allocation class, please have a look at the 329 // default values for the parameters RoundRobinIntegerRegIntervalStart 330 // and RoundRobinFloatRegIntervalStart 331 332 alloc_class chunk1 ( 333 // Chunk1 contains *all* 64 floating-point registers halves. 334 335 // scratch register 336 F0, F0_H, 337 338 // argument registers 339 F13, F13_H, 340 F12, F12_H, 341 F11, F11_H, 342 F10, F10_H, 343 F9, F9_H, 344 F8, F8_H, 345 F7, F7_H, 346 F6, F6_H, 347 F5, F5_H, 348 F4, F4_H, 349 F3, F3_H, 350 F2, F2_H, 351 F1, F1_H, 352 353 // non-volatile registers 354 F14, F14_H, 355 F15, F15_H, 356 F16, F16_H, 357 F17, F17_H, 358 F18, F18_H, 359 F19, F19_H, 360 F20, F20_H, 361 F21, F21_H, 362 F22, F22_H, 363 F23, F23_H, 364 F24, F24_H, 365 F25, F25_H, 366 F26, F26_H, 367 F27, F27_H, 368 F28, F28_H, 369 F29, F29_H, 370 F30, F30_H, 371 F31, F31_H 372 ); 373 374 alloc_class chunk2 ( 375 // Chunk2 contains *all* 8 condition code registers. 376 377 CCR0, 378 CCR1, 379 CCR2, 380 CCR3, 381 CCR4, 382 CCR5, 383 CCR6, 384 CCR7 385 ); 386 387 alloc_class chunk3 ( 388 // special registers 389 // These registers are not allocated, but used for nodes generated by postalloc expand. 390 SR_XER, 391 SR_LR, 392 SR_CTR, 393 SR_VRSAVE, 394 SR_SPEFSCR, 395 SR_PPR 396 ); 397 398 //-------Architecture Description Register Classes----------------------- 399 400 // Several register classes are automatically defined based upon 401 // information in this architecture description. 402 403 // 1) reg_class inline_cache_reg ( as defined in frame section ) 404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section ) 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 407 // 408 409 // ---------------------------- 410 // 32 Bit Register Classes 411 // ---------------------------- 412 413 // We specify registers twice, once as read/write, and once read-only. 414 // We use the read-only registers for source operands. With this, we 415 // can include preset read only registers in this class, as a hard-coded 416 // '0'-register. (We used to simulate this on ppc.) 417 418 // 32 bit registers that can be read and written i.e. these registers 419 // can be dest (or src) of normal instructions. 420 reg_class bits32_reg_rw( 421 /*R0*/ // R0 422 /*R1*/ // SP 423 R2, // TOC 424 R3, 425 R4, 426 R5, 427 R6, 428 R7, 429 R8, 430 R9, 431 R10, 432 R11, 433 R12, 434 /*R13*/ // system thread id 435 R14, 436 R15, 437 /*R16*/ // R16_thread 438 R17, 439 R18, 440 R19, 441 R20, 442 R21, 443 R22, 444 R23, 445 R24, 446 R25, 447 R26, 448 R27, 449 R28, 450 /*R29,*/ // global TOC 451 R30, 452 R31 453 ); 454 455 // 32 bit registers that can only be read i.e. these registers can 456 // only be src of all instructions. 457 reg_class bits32_reg_ro( 458 /*R0*/ // R0 459 /*R1*/ // SP 460 R2 // TOC 461 R3, 462 R4, 463 R5, 464 R6, 465 R7, 466 R8, 467 R9, 468 R10, 469 R11, 470 R12, 471 /*R13*/ // system thread id 472 R14, 473 R15, 474 /*R16*/ // R16_thread 475 R17, 476 R18, 477 R19, 478 R20, 479 R21, 480 R22, 481 R23, 482 R24, 483 R25, 484 R26, 485 R27, 486 R28, 487 /*R29,*/ 488 R30, 489 R31 490 ); 491 492 reg_class rscratch1_bits32_reg(R11); 493 reg_class rscratch2_bits32_reg(R12); 494 reg_class rarg1_bits32_reg(R3); 495 reg_class rarg2_bits32_reg(R4); 496 reg_class rarg3_bits32_reg(R5); 497 reg_class rarg4_bits32_reg(R6); 498 499 // ---------------------------- 500 // 64 Bit Register Classes 501 // ---------------------------- 502 // 64-bit build means 64-bit pointers means hi/lo pairs 503 504 reg_class rscratch1_bits64_reg(R11_H, R11); 505 reg_class rscratch2_bits64_reg(R12_H, R12); 506 reg_class rarg1_bits64_reg(R3_H, R3); 507 reg_class rarg2_bits64_reg(R4_H, R4); 508 reg_class rarg3_bits64_reg(R5_H, R5); 509 reg_class rarg4_bits64_reg(R6_H, R6); 510 // Thread register, 'written' by tlsLoadP, see there. 511 reg_class thread_bits64_reg(R16_H, R16); 512 513 reg_class r19_bits64_reg(R19_H, R19); 514 515 // 64 bit registers that can be read and written i.e. these registers 516 // can be dest (or src) of normal instructions. 517 reg_class bits64_reg_rw( 518 /*R0_H, R0*/ // R0 519 /*R1_H, R1*/ // SP 520 R2_H, R2, // TOC 521 R3_H, R3, 522 R4_H, R4, 523 R5_H, R5, 524 R6_H, R6, 525 R7_H, R7, 526 R8_H, R8, 527 R9_H, R9, 528 R10_H, R10, 529 R11_H, R11, 530 R12_H, R12, 531 /*R13_H, R13*/ // system thread id 532 R14_H, R14, 533 R15_H, R15, 534 /*R16_H, R16*/ // R16_thread 535 R17_H, R17, 536 R18_H, R18, 537 R19_H, R19, 538 R20_H, R20, 539 R21_H, R21, 540 R22_H, R22, 541 R23_H, R23, 542 R24_H, R24, 543 R25_H, R25, 544 R26_H, R26, 545 R27_H, R27, 546 R28_H, R28, 547 /*R29_H, R29,*/ 548 R30_H, R30, 549 R31_H, R31 550 ); 551 552 // 64 bit registers used excluding r2, r11 and r12 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses 554 // r2, r11 and r12 internally. 555 reg_class bits64_reg_leaf_call( 556 /*R0_H, R0*/ // R0 557 /*R1_H, R1*/ // SP 558 /*R2_H, R2*/ // TOC 559 R3_H, R3, 560 R4_H, R4, 561 R5_H, R5, 562 R6_H, R6, 563 R7_H, R7, 564 R8_H, R8, 565 R9_H, R9, 566 R10_H, R10, 567 /*R11_H, R11*/ 568 /*R12_H, R12*/ 569 /*R13_H, R13*/ // system thread id 570 R14_H, R14, 571 R15_H, R15, 572 /*R16_H, R16*/ // R16_thread 573 R17_H, R17, 574 R18_H, R18, 575 R19_H, R19, 576 R20_H, R20, 577 R21_H, R21, 578 R22_H, R22, 579 R23_H, R23, 580 R24_H, R24, 581 R25_H, R25, 582 R26_H, R26, 583 R27_H, R27, 584 R28_H, R28, 585 /*R29_H, R29,*/ 586 R30_H, R30, 587 R31_H, R31 588 ); 589 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall 591 // which uses r19 as inline cache internally and expanded LeafCall which uses 592 // r2, r11 and r12 internally. 593 reg_class bits64_constant_table_base( 594 /*R0_H, R0*/ // R0 595 /*R1_H, R1*/ // SP 596 /*R2_H, R2*/ // TOC 597 R3_H, R3, 598 R4_H, R4, 599 R5_H, R5, 600 R6_H, R6, 601 R7_H, R7, 602 R8_H, R8, 603 R9_H, R9, 604 R10_H, R10, 605 /*R11_H, R11*/ 606 /*R12_H, R12*/ 607 /*R13_H, R13*/ // system thread id 608 R14_H, R14, 609 R15_H, R15, 610 /*R16_H, R16*/ // R16_thread 611 R17_H, R17, 612 R18_H, R18, 613 /*R19_H, R19*/ 614 R20_H, R20, 615 R21_H, R21, 616 R22_H, R22, 617 R23_H, R23, 618 R24_H, R24, 619 R25_H, R25, 620 R26_H, R26, 621 R27_H, R27, 622 R28_H, R28, 623 /*R29_H, R29,*/ 624 R30_H, R30, 625 R31_H, R31 626 ); 627 628 // 64 bit registers that can only be read i.e. these registers can 629 // only be src of all instructions. 630 reg_class bits64_reg_ro( 631 /*R0_H, R0*/ // R0 632 R1_H, R1, 633 R2_H, R2, // TOC 634 R3_H, R3, 635 R4_H, R4, 636 R5_H, R5, 637 R6_H, R6, 638 R7_H, R7, 639 R8_H, R8, 640 R9_H, R9, 641 R10_H, R10, 642 R11_H, R11, 643 R12_H, R12, 644 /*R13_H, R13*/ // system thread id 645 R14_H, R14, 646 R15_H, R15, 647 R16_H, R16, // R16_thread 648 R17_H, R17, 649 R18_H, R18, 650 R19_H, R19, 651 R20_H, R20, 652 R21_H, R21, 653 R22_H, R22, 654 R23_H, R23, 655 R24_H, R24, 656 R25_H, R25, 657 R26_H, R26, 658 R27_H, R27, 659 R28_H, R28, 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!! 661 R30_H, R30, 662 R31_H, R31 663 ); 664 665 666 // ---------------------------- 667 // Special Class for Condition Code Flags Register 668 669 reg_class int_flags( 670 /*CCR0*/ // scratch 671 /*CCR1*/ // scratch 672 /*CCR2*/ // nv! 673 /*CCR3*/ // nv! 674 /*CCR4*/ // nv! 675 CCR5, 676 CCR6, 677 CCR7 678 ); 679 680 reg_class int_flags_ro( 681 CCR0, 682 CCR1, 683 CCR2, 684 CCR3, 685 CCR4, 686 CCR5, 687 CCR6, 688 CCR7 689 ); 690 691 reg_class int_flags_CR0(CCR0); 692 reg_class int_flags_CR1(CCR1); 693 reg_class int_flags_CR6(CCR6); 694 reg_class ctr_reg(SR_CTR); 695 696 // ---------------------------- 697 // Float Register Classes 698 // ---------------------------- 699 700 reg_class flt_reg( 701 F0, 702 F1, 703 F2, 704 F3, 705 F4, 706 F5, 707 F6, 708 F7, 709 F8, 710 F9, 711 F10, 712 F11, 713 F12, 714 F13, 715 F14, // nv! 716 F15, // nv! 717 F16, // nv! 718 F17, // nv! 719 F18, // nv! 720 F19, // nv! 721 F20, // nv! 722 F21, // nv! 723 F22, // nv! 724 F23, // nv! 725 F24, // nv! 726 F25, // nv! 727 F26, // nv! 728 F27, // nv! 729 F28, // nv! 730 F29, // nv! 731 F30, // nv! 732 F31 // nv! 733 ); 734 735 // Double precision float registers have virtual `high halves' that 736 // are needed by the allocator. 737 reg_class dbl_reg( 738 F0, F0_H, 739 F1, F1_H, 740 F2, F2_H, 741 F3, F3_H, 742 F4, F4_H, 743 F5, F5_H, 744 F6, F6_H, 745 F7, F7_H, 746 F8, F8_H, 747 F9, F9_H, 748 F10, F10_H, 749 F11, F11_H, 750 F12, F12_H, 751 F13, F13_H, 752 F14, F14_H, // nv! 753 F15, F15_H, // nv! 754 F16, F16_H, // nv! 755 F17, F17_H, // nv! 756 F18, F18_H, // nv! 757 F19, F19_H, // nv! 758 F20, F20_H, // nv! 759 F21, F21_H, // nv! 760 F22, F22_H, // nv! 761 F23, F23_H, // nv! 762 F24, F24_H, // nv! 763 F25, F25_H, // nv! 764 F26, F26_H, // nv! 765 F27, F27_H, // nv! 766 F28, F28_H, // nv! 767 F29, F29_H, // nv! 768 F30, F30_H, // nv! 769 F31, F31_H // nv! 770 ); 771 772 %} 773 774 //----------DEFINITION BLOCK--------------------------------------------------- 775 // Define name --> value mappings to inform the ADLC of an integer valued name 776 // Current support includes integer values in the range [0, 0x7FFFFFFF] 777 // Format: 778 // int_def <name> ( <int_value>, <expression>); 779 // Generated Code in ad_<arch>.hpp 780 // #define <name> (<expression>) 781 // // value == <int_value> 782 // Generated code in ad_<arch>.cpp adlc_verification() 783 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 784 // 785 definitions %{ 786 // The default cost (of an ALU instruction). 787 int_def DEFAULT_COST_LOW ( 30, 30); 788 int_def DEFAULT_COST ( 100, 100); 789 int_def HUGE_COST (1000000, 1000000); 790 791 // Memory refs 792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); 793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); 794 795 // Branches are even more expensive. 796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); 797 int_def CALL_COST ( 1300, DEFAULT_COST * 13); 798 %} 799 800 801 //----------SOURCE BLOCK------------------------------------------------------- 802 // This is a block of C++ code which provides values, functions, and 803 // definitions necessary in the rest of the architecture description. 804 source_hpp %{ 805 // Header information of the source block. 806 // Method declarations/definitions which are used outside 807 // the ad-scope can conveniently be defined here. 808 // 809 // To keep related declarations/definitions/uses close together, 810 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 811 812 // Returns true if Node n is followed by a MemBar node that 813 // will do an acquire. If so, this node must not do the acquire 814 // operation. 815 bool followed_by_acquire(const Node *n); 816 %} 817 818 source %{ 819 820 // Optimize load-acquire. 821 // 822 // Check if acquire is unnecessary due to following operation that does 823 // acquire anyways. 824 // Walk the pattern: 825 // 826 // n: Load.acq 827 // | 828 // MemBarAcquire 829 // | | 830 // Proj(ctrl) Proj(mem) 831 // | | 832 // MemBarRelease/Volatile 833 // 834 bool followed_by_acquire(const Node *load) { 835 assert(load->is_Load(), "So far implemented only for loads."); 836 837 // Find MemBarAcquire. 838 const Node *mba = NULL; 839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { 840 const Node *out = load->fast_out(i); 841 if (out->Opcode() == Op_MemBarAcquire) { 842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. 843 mba = out; 844 break; 845 } 846 } 847 if (!mba) return false; 848 849 // Find following MemBar node. 850 // 851 // The following node must be reachable by control AND memory 852 // edge to assure no other operations are in between the two nodes. 853 // 854 // So first get the Proj node, mem_proj, to use it to iterate forward. 855 Node *mem_proj = NULL; 856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { 857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found 858 assert(mem_proj->is_Proj(), "only projections here"); 859 ProjNode *proj = mem_proj->as_Proj(); 860 if (proj->_con == TypeFunc::Memory && 861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only 862 break; 863 } 864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); 865 866 // Search MemBar behind Proj. If there are other memory operations 867 // behind the Proj we lost. 868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { 869 Node *x = mem_proj->fast_out(j); 870 // Proj might have an edge to a store or load node which precedes the membar. 871 if (x->is_Mem()) return false; 872 873 // On PPC64 release and volatile are implemented by an instruction 874 // that also has acquire semantics. I.e. there is no need for an 875 // acquire before these. 876 int xop = x->Opcode(); 877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { 878 // Make sure we're not missing Call/Phi/MergeMem by checking 879 // control edges. The control edge must directly lead back 880 // to the MemBarAcquire 881 Node *ctrl_proj = x->in(0); 882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { 883 return true; 884 } 885 } 886 } 887 888 return false; 889 } 890 891 #define __ _masm. 892 893 // Tertiary op of a LoadP or StoreP encoding. 894 #define REGP_OP true 895 896 // **************************************************************************** 897 898 // REQUIRED FUNCTIONALITY 899 900 // !!!!! Special hack to get all type of calls to specify the byte offset 901 // from the start of the call to the point where the return address 902 // will point. 903 904 // PPC port: Removed use of lazy constant construct. 905 906 int MachCallStaticJavaNode::ret_addr_offset() { 907 // It's only a single branch-and-link instruction. 908 return 4; 909 } 910 911 int MachCallDynamicJavaNode::ret_addr_offset() { 912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use 913 // postalloc expanded calls if we use inline caches and do not update method data. 914 if (UseInlineCaches) 915 return 4; 916 917 int vtable_index = this->_vtable_index; 918 if (vtable_index < 0) { 919 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 921 return 12; 922 } else { 923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 924 return 24; 925 } 926 } 927 928 int MachCallRuntimeNode::ret_addr_offset() { 929 #if defined(ABI_ELFv2) 930 return 28; 931 #else 932 return 40; 933 #endif 934 } 935 936 //============================================================================= 937 938 // condition code conversions 939 940 static int cc_to_boint(int cc) { 941 return Assembler::bcondCRbiIs0 | (cc & 8); 942 } 943 944 static int cc_to_inverse_boint(int cc) { 945 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); 946 } 947 948 static int cc_to_biint(int cc, int flags_reg) { 949 return (flags_reg << 2) | (cc & 3); 950 } 951 952 //============================================================================= 953 954 // Compute padding required for nodes which need alignment. The padding 955 // is the number of bytes (not instructions) which will be inserted before 956 // the instruction. The padding must match the size of a NOP instruction. 957 958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { 959 return (3*4-current_offset)&31; 960 } 961 962 int string_indexOf_imm1Node::compute_padding(int current_offset) const { 963 return (2*4-current_offset)&31; 964 } 965 966 int string_indexOf_immNode::compute_padding(int current_offset) const { 967 return (3*4-current_offset)&31; 968 } 969 970 int string_indexOfNode::compute_padding(int current_offset) const { 971 return (1*4-current_offset)&31; 972 } 973 974 int string_compareNode::compute_padding(int current_offset) const { 975 return (4*4-current_offset)&31; 976 } 977 978 int string_equals_immNode::compute_padding(int current_offset) const { 979 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled). 980 return (2*4-current_offset)&31; 981 } 982 983 int string_equalsNode::compute_padding(int current_offset) const { 984 return (7*4-current_offset)&31; 985 } 986 987 int inlineCallClearArrayNode::compute_padding(int current_offset) const { 988 return (2*4-current_offset)&31; 989 } 990 991 //============================================================================= 992 993 // Indicate if the safepoint node needs the polling page as an input. 994 bool SafePointNode::needs_polling_address_input() { 995 // The address is loaded from thread by a seperate node. 996 return true; 997 } 998 999 //============================================================================= 1000 1001 // Emit an interrupt that is caught by the debugger (for debugging compiler). 1002 void emit_break(CodeBuffer &cbuf) { 1003 MacroAssembler _masm(&cbuf); 1004 __ illtrap(); 1005 } 1006 1007 #ifndef PRODUCT 1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1009 st->print("BREAKPOINT"); 1010 } 1011 #endif 1012 1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1014 emit_break(cbuf); 1015 } 1016 1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 1018 return MachNode::size(ra_); 1019 } 1020 1021 //============================================================================= 1022 1023 void emit_nop(CodeBuffer &cbuf) { 1024 MacroAssembler _masm(&cbuf); 1025 __ nop(); 1026 } 1027 1028 static inline void emit_long(CodeBuffer &cbuf, int value) { 1029 *((int*)(cbuf.insts_end())) = value; 1030 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); 1031 } 1032 1033 //============================================================================= 1034 1035 %} // interrupt source 1036 1037 source_hpp %{ // Header information of the source block. 1038 1039 //-------------------------------------------------------------- 1040 //---< Used for optimization in Compile::Shorten_branches >--- 1041 //-------------------------------------------------------------- 1042 1043 class CallStubImpl { 1044 1045 public: 1046 1047 // Emit call stub, compiled java to interpreter. 1048 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset); 1049 1050 // Size of call trampoline stub. 1051 // This doesn't need to be accurate to the byte, but it 1052 // must be larger than or equal to the real size of the stub. 1053 static uint size_call_trampoline() { 1054 return MacroAssembler::trampoline_stub_size; 1055 } 1056 1057 // number of relocations needed by a call trampoline stub 1058 static uint reloc_call_trampoline() { 1059 return 5; 1060 } 1061 1062 }; 1063 1064 %} // end source_hpp 1065 1066 source %{ 1067 1068 // Emit a trampoline stub for a call to a target which is too far away. 1069 // 1070 // code sequences: 1071 // 1072 // call-site: 1073 // branch-and-link to <destination> or <trampoline stub> 1074 // 1075 // Related trampoline stub for this call-site in the stub section: 1076 // load the call target from the constant pool 1077 // branch via CTR (LR/link still points to the call-site above) 1078 1079 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { 1080 address stub = __ emit_trampoline_stub(destination_toc_offset, insts_call_instruction_offset); 1081 if (stub == NULL) { 1082 ciEnv::current()->record_out_of_memory_failure(); 1083 } 1084 } 1085 1086 //============================================================================= 1087 1088 // Emit an inline branch-and-link call and a related trampoline stub. 1089 // 1090 // code sequences: 1091 // 1092 // call-site: 1093 // branch-and-link to <destination> or <trampoline stub> 1094 // 1095 // Related trampoline stub for this call-site in the stub section: 1096 // load the call target from the constant pool 1097 // branch via CTR (LR/link still points to the call-site above) 1098 // 1099 1100 typedef struct { 1101 int insts_call_instruction_offset; 1102 int ret_addr_offset; 1103 } EmitCallOffsets; 1104 1105 // Emit a branch-and-link instruction that branches to a trampoline. 1106 // - Remember the offset of the branch-and-link instruction. 1107 // - Add a relocation at the branch-and-link instruction. 1108 // - Emit a branch-and-link. 1109 // - Remember the return pc offset. 1110 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { 1111 EmitCallOffsets offsets = { -1, -1 }; 1112 const int start_offset = __ offset(); 1113 offsets.insts_call_instruction_offset = __ offset(); 1114 1115 // No entry point given, use the current pc. 1116 if (entry_point == NULL) entry_point = __ pc(); 1117 1118 if (!Compile::current()->in_scratch_emit_size()) { 1119 // Put the entry point as a constant into the constant pool. 1120 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 1121 if (entry_point_toc_addr == NULL) { 1122 ciEnv::current()->record_out_of_memory_failure(); 1123 return offsets; 1124 } 1125 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 1126 1127 // Emit the trampoline stub which will be related to the branch-and-link below. 1128 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); 1129 if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full. 1130 __ relocate(rtype); 1131 } 1132 1133 // Note: At this point we do not have the address of the trampoline 1134 // stub, and the entry point might be too far away for bl, so __ pc() 1135 // serves as dummy and the bl will be patched later. 1136 __ bl((address) __ pc()); 1137 1138 offsets.ret_addr_offset = __ offset() - start_offset; 1139 1140 return offsets; 1141 } 1142 1143 //============================================================================= 1144 1145 // Factory for creating loadConL* nodes for large/small constant pool. 1146 1147 static inline jlong replicate_immF(float con) { 1148 // Replicate float con 2 times and pack into vector. 1149 int val = *((int*)&con); 1150 jlong lval = val; 1151 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 1152 return lval; 1153 } 1154 1155 //============================================================================= 1156 1157 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); 1158 int Compile::ConstantTable::calculate_table_base_offset() const { 1159 return 0; // absolute addressing, no offset 1160 } 1161 1162 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } 1163 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1164 iRegPdstOper *op_dst = new iRegPdstOper(); 1165 MachNode *m1 = new loadToc_hiNode(); 1166 MachNode *m2 = new loadToc_loNode(); 1167 1168 m1->add_req(NULL); 1169 m2->add_req(NULL, m1); 1170 m1->_opnds[0] = op_dst; 1171 m2->_opnds[0] = op_dst; 1172 m2->_opnds[1] = op_dst; 1173 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1174 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1175 nodes->push(m1); 1176 nodes->push(m2); 1177 } 1178 1179 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1180 // Is postalloc expanded. 1181 ShouldNotReachHere(); 1182 } 1183 1184 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 1185 return 0; 1186 } 1187 1188 #ifndef PRODUCT 1189 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1190 st->print("-- \t// MachConstantBaseNode (empty encoding)"); 1191 } 1192 #endif 1193 1194 //============================================================================= 1195 1196 #ifndef PRODUCT 1197 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1198 Compile* C = ra_->C; 1199 const long framesize = C->frame_slots() << LogBytesPerInt; 1200 1201 st->print("PROLOG\n\t"); 1202 if (C->need_stack_bang(framesize)) { 1203 st->print("stack_overflow_check\n\t"); 1204 } 1205 1206 if (!false /* TODO: PPC port C->is_frameless_method()*/) { 1207 st->print("save return pc\n\t"); 1208 st->print("push frame %ld\n\t", -framesize); 1209 } 1210 } 1211 #endif 1212 1213 // Macro used instead of the common __ to emulate the pipes of PPC. 1214 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the 1215 // micro scheduler to cope with "hand written" assembler like in the prolog. Though 1216 // still no scheduling of this code is possible, the micro scheduler is aware of the 1217 // code and can update its internal data. The following mechanism is used to achieve this: 1218 // The micro scheduler calls size() of each compound node during scheduling. size() does a 1219 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. 1220 #if 0 // TODO: PPC port 1221 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1222 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ 1223 _masm. 1224 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1225 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) 1226 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1227 C->hb_scheduling()->_pdScheduling->advance_offset 1228 #else 1229 #define ___(op) if (UsePower6SchedulerPPC64) \ 1230 Unimplemented(); \ 1231 _masm. 1232 #define ___stop if (UsePower6SchedulerPPC64) \ 1233 Unimplemented() 1234 #define ___advance if (UsePower6SchedulerPPC64) \ 1235 Unimplemented() 1236 #endif 1237 1238 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1239 Compile* C = ra_->C; 1240 MacroAssembler _masm(&cbuf); 1241 1242 const long framesize = C->frame_size_in_bytes(); 1243 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment"); 1244 1245 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1246 1247 const Register return_pc = R20; // Must match return_addr() in frame section. 1248 const Register callers_sp = R21; 1249 const Register push_frame_temp = R22; 1250 const Register toc_temp = R23; 1251 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); 1252 1253 if (method_is_frameless) { 1254 // Add nop at beginning of all frameless methods to prevent any 1255 // oop instructions from getting overwritten by make_not_entrant 1256 // (patching attempt would fail). 1257 ___(nop) nop(); 1258 } else { 1259 // Get return pc. 1260 ___(mflr) mflr(return_pc); 1261 } 1262 1263 // Calls to C2R adapters often do not accept exceptional returns. 1264 // We require that their callers must bang for them. But be 1265 // careful, because some VM calls (such as call site linkage) can 1266 // use several kilobytes of stack. But the stack safety zone should 1267 // account for that. See bugs 4446381, 4468289, 4497237. 1268 1269 int bangsize = C->bang_size_in_bytes(); 1270 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect"); 1271 if (C->need_stack_bang(bangsize) && UseStackBanging) { 1272 // Unfortunately we cannot use the function provided in 1273 // assembler.cpp as we have to emulate the pipes. So I had to 1274 // insert the code of generate_stack_overflow_check(), see 1275 // assembler.cpp for some illuminative comments. 1276 const int page_size = os::vm_page_size(); 1277 int bang_end = JavaThread::stack_shadow_zone_size(); 1278 1279 // This is how far the previous frame's stack banging extended. 1280 const int bang_end_safe = bang_end; 1281 1282 if (bangsize > page_size) { 1283 bang_end += bangsize; 1284 } 1285 1286 int bang_offset = bang_end_safe; 1287 1288 while (bang_offset <= bang_end) { 1289 // Need at least one stack bang at end of shadow zone. 1290 1291 // Again I had to copy code, this time from assembler_ppc.cpp, 1292 // bang_stack_with_offset - see there for comments. 1293 1294 // Stack grows down, caller passes positive offset. 1295 assert(bang_offset > 0, "must bang with positive offset"); 1296 1297 long stdoffset = -bang_offset; 1298 1299 if (Assembler::is_simm(stdoffset, 16)) { 1300 // Signed 16 bit offset, a simple std is ok. 1301 if (UseLoadInstructionsForStackBangingPPC64) { 1302 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); 1303 } else { 1304 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); 1305 } 1306 } else if (Assembler::is_simm(stdoffset, 31)) { 1307 // Use largeoffset calculations for addis & ld/std. 1308 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); 1309 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); 1310 1311 Register tmp = R11; 1312 ___(addis) addis(tmp, R1_SP, hi); 1313 if (UseLoadInstructionsForStackBangingPPC64) { 1314 ___(ld) ld(R0, lo, tmp); 1315 } else { 1316 ___(std) std(R0, lo, tmp); 1317 } 1318 } else { 1319 ShouldNotReachHere(); 1320 } 1321 1322 bang_offset += page_size; 1323 } 1324 // R11 trashed 1325 } // C->need_stack_bang(framesize) && UseStackBanging 1326 1327 unsigned int bytes = (unsigned int)framesize; 1328 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 1329 ciMethod *currMethod = C->method(); 1330 1331 // Optimized version for most common case. 1332 if (UsePower6SchedulerPPC64 && 1333 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) && 1334 !(false /* ConstantsALot TODO: PPC port*/)) { 1335 ___(or) mr(callers_sp, R1_SP); 1336 ___(std) std(return_pc, _abi(lr), R1_SP); 1337 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1338 return; 1339 } 1340 1341 if (!method_is_frameless) { 1342 // Get callers sp. 1343 ___(or) mr(callers_sp, R1_SP); 1344 1345 // Push method's frame, modifies SP. 1346 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); 1347 // The ABI is already accounted for in 'framesize' via the 1348 // 'out_preserve' area. 1349 Register tmp = push_frame_temp; 1350 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). 1351 if (Assembler::is_simm(-offset, 16)) { 1352 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1353 } else { 1354 long x = -offset; 1355 // Had to insert load_const(tmp, -offset). 1356 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); 1357 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); 1358 ___(rldicr) sldi(tmp, tmp, 32); 1359 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); 1360 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); 1361 1362 ___(stdux) stdux(R1_SP, R1_SP, tmp); 1363 } 1364 } 1365 #if 0 // TODO: PPC port 1366 // For testing large constant pools, emit a lot of constants to constant pool. 1367 // "Randomize" const_size. 1368 if (ConstantsALot) { 1369 const int num_consts = const_size(); 1370 for (int i = 0; i < num_consts; i++) { 1371 __ long_constant(0xB0B5B00BBABE); 1372 } 1373 } 1374 #endif 1375 if (!method_is_frameless) { 1376 // Save return pc. 1377 ___(std) std(return_pc, _abi(lr), callers_sp); 1378 } 1379 } 1380 #undef ___ 1381 #undef ___stop 1382 #undef ___advance 1383 1384 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1385 // Variable size. determine dynamically. 1386 return MachNode::size(ra_); 1387 } 1388 1389 int MachPrologNode::reloc() const { 1390 // Return number of relocatable values contained in this instruction. 1391 return 1; // 1 reloc entry for load_const(toc). 1392 } 1393 1394 //============================================================================= 1395 1396 #ifndef PRODUCT 1397 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1398 Compile* C = ra_->C; 1399 1400 st->print("EPILOG\n\t"); 1401 st->print("restore return pc\n\t"); 1402 st->print("pop frame\n\t"); 1403 1404 if (do_polling() && C->is_method_compilation()) { 1405 st->print("touch polling page\n\t"); 1406 } 1407 } 1408 #endif 1409 1410 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1411 Compile* C = ra_->C; 1412 MacroAssembler _masm(&cbuf); 1413 1414 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; 1415 assert(framesize >= 0, "negative frame-size?"); 1416 1417 const bool method_needs_polling = do_polling() && C->is_method_compilation(); 1418 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1419 const Register return_pc = R11; 1420 const Register polling_page = R12; 1421 1422 if (!method_is_frameless) { 1423 // Restore return pc relative to callers' sp. 1424 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); 1425 } 1426 1427 if (method_needs_polling) { 1428 if (LoadPollAddressFromThread) { 1429 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1430 Unimplemented(); 1431 } else { 1432 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() 1433 } 1434 } 1435 1436 if (!method_is_frameless) { 1437 // Move return pc to LR. 1438 __ mtlr(return_pc); 1439 // Pop frame (fixed frame-size). 1440 __ addi(R1_SP, R1_SP, (int)framesize); 1441 } 1442 1443 if (method_needs_polling) { 1444 // We need to mark the code position where the load from the safepoint 1445 // polling page was emitted as relocInfo::poll_return_type here. 1446 __ relocate(relocInfo::poll_return_type); 1447 __ load_from_polling_page(polling_page); 1448 } 1449 } 1450 1451 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1452 // Variable size. Determine dynamically. 1453 return MachNode::size(ra_); 1454 } 1455 1456 int MachEpilogNode::reloc() const { 1457 // Return number of relocatable values contained in this instruction. 1458 return 1; // 1 for load_from_polling_page. 1459 } 1460 1461 const Pipeline * MachEpilogNode::pipeline() const { 1462 return MachNode::pipeline_class(); 1463 } 1464 1465 // This method seems to be obsolete. It is declared in machnode.hpp 1466 // and defined in all *.ad files, but it is never called. Should we 1467 // get rid of it? 1468 int MachEpilogNode::safepoint_offset() const { 1469 assert(do_polling(), "no return for this epilog node"); 1470 return 0; 1471 } 1472 1473 #if 0 // TODO: PPC port 1474 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1475 MacroAssembler _masm(&cbuf); 1476 if (LoadPollAddressFromThread) { 1477 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1478 } else { 1479 _masm.nop(); 1480 } 1481 } 1482 1483 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { 1484 if (LoadPollAddressFromThread) { 1485 return 4; 1486 } else { 1487 return 4; 1488 } 1489 } 1490 1491 #ifndef PRODUCT 1492 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1493 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); 1494 } 1495 #endif 1496 1497 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { 1498 return RSCRATCH1_BITS64_REG_mask(); 1499 } 1500 #endif // PPC port 1501 1502 // ============================================================================= 1503 1504 // Figure out which register class each belongs in: rc_int, rc_float or 1505 // rc_stack. 1506 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1507 1508 static enum RC rc_class(OptoReg::Name reg) { 1509 // Return the register class for the given register. The given register 1510 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 1511 // enumeration in adGlobals_ppc.hpp. 1512 1513 if (reg == OptoReg::Bad) return rc_bad; 1514 1515 // We have 64 integer register halves, starting at index 0. 1516 if (reg < 64) return rc_int; 1517 1518 // We have 64 floating-point register halves, starting at index 64. 1519 if (reg < 64+64) return rc_float; 1520 1521 // Between float regs & stack are the flags regs. 1522 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); 1523 1524 return rc_stack; 1525 } 1526 1527 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, 1528 bool do_print, Compile* C, outputStream *st) { 1529 1530 assert(opcode == Assembler::LD_OPCODE || 1531 opcode == Assembler::STD_OPCODE || 1532 opcode == Assembler::LWZ_OPCODE || 1533 opcode == Assembler::STW_OPCODE || 1534 opcode == Assembler::LFD_OPCODE || 1535 opcode == Assembler::STFD_OPCODE || 1536 opcode == Assembler::LFS_OPCODE || 1537 opcode == Assembler::STFS_OPCODE, 1538 "opcode not supported"); 1539 1540 if (cbuf) { 1541 int d = 1542 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? 1543 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) 1544 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. 1545 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); 1546 } 1547 #ifndef PRODUCT 1548 else if (do_print) { 1549 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", 1550 op_str, 1551 Matcher::regName[reg], 1552 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); 1553 } 1554 #endif 1555 return 4; // size 1556 } 1557 1558 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { 1559 Compile* C = ra_->C; 1560 1561 // Get registers to move. 1562 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1563 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1564 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1565 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1566 1567 enum RC src_hi_rc = rc_class(src_hi); 1568 enum RC src_lo_rc = rc_class(src_lo); 1569 enum RC dst_hi_rc = rc_class(dst_hi); 1570 enum RC dst_lo_rc = rc_class(dst_lo); 1571 1572 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1573 if (src_hi != OptoReg::Bad) 1574 assert((src_lo&1)==0 && src_lo+1==src_hi && 1575 (dst_lo&1)==0 && dst_lo+1==dst_hi, 1576 "expected aligned-adjacent pairs"); 1577 // Generate spill code! 1578 int size = 0; 1579 1580 if (src_lo == dst_lo && src_hi == dst_hi) 1581 return size; // Self copy, no move. 1582 1583 // -------------------------------------- 1584 // Memory->Memory Spill. Use R0 to hold the value. 1585 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1586 int src_offset = ra_->reg2offset(src_lo); 1587 int dst_offset = ra_->reg2offset(dst_lo); 1588 if (src_hi != OptoReg::Bad) { 1589 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, 1590 "expected same type of move for high parts"); 1591 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); 1592 if (!cbuf && !do_size) st->print("\n\t"); 1593 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); 1594 } else { 1595 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); 1596 if (!cbuf && !do_size) st->print("\n\t"); 1597 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); 1598 } 1599 return size; 1600 } 1601 1602 // -------------------------------------- 1603 // Check for float->int copy; requires a trip through memory. 1604 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1605 Unimplemented(); 1606 } 1607 1608 // -------------------------------------- 1609 // Check for integer reg-reg copy. 1610 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1611 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1612 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1613 size = (Rsrc != Rdst) ? 4 : 0; 1614 1615 if (cbuf) { 1616 MacroAssembler _masm(cbuf); 1617 if (size) { 1618 __ mr(Rdst, Rsrc); 1619 } 1620 } 1621 #ifndef PRODUCT 1622 else if (!do_size) { 1623 if (size) { 1624 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1625 } else { 1626 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1627 } 1628 } 1629 #endif 1630 return size; 1631 } 1632 1633 // Check for integer store. 1634 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1635 int dst_offset = ra_->reg2offset(dst_lo); 1636 if (src_hi != OptoReg::Bad) { 1637 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, 1638 "expected same type of move for high parts"); 1639 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1640 } else { 1641 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); 1642 } 1643 return size; 1644 } 1645 1646 // Check for integer load. 1647 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1648 int src_offset = ra_->reg2offset(src_lo); 1649 if (src_hi != OptoReg::Bad) { 1650 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, 1651 "expected same type of move for high parts"); 1652 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1653 } else { 1654 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); 1655 } 1656 return size; 1657 } 1658 1659 // Check for float reg-reg copy. 1660 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1661 if (cbuf) { 1662 MacroAssembler _masm(cbuf); 1663 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1664 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1665 __ fmr(Rdst, Rsrc); 1666 } 1667 #ifndef PRODUCT 1668 else if (!do_size) { 1669 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1670 } 1671 #endif 1672 return 4; 1673 } 1674 1675 // Check for float store. 1676 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1677 int dst_offset = ra_->reg2offset(dst_lo); 1678 if (src_hi != OptoReg::Bad) { 1679 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, 1680 "expected same type of move for high parts"); 1681 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1682 } else { 1683 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); 1684 } 1685 return size; 1686 } 1687 1688 // Check for float load. 1689 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1690 int src_offset = ra_->reg2offset(src_lo); 1691 if (src_hi != OptoReg::Bad) { 1692 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, 1693 "expected same type of move for high parts"); 1694 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1695 } else { 1696 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); 1697 } 1698 return size; 1699 } 1700 1701 // -------------------------------------------------------------------- 1702 // Check for hi bits still needing moving. Only happens for misaligned 1703 // arguments to native calls. 1704 if (src_hi == dst_hi) 1705 return size; // Self copy; no move. 1706 1707 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1708 ShouldNotReachHere(); // Unimplemented 1709 return 0; 1710 } 1711 1712 #ifndef PRODUCT 1713 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1714 if (!ra_) 1715 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); 1716 else 1717 implementation(NULL, ra_, false, st); 1718 } 1719 #endif 1720 1721 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1722 implementation(&cbuf, ra_, false, NULL); 1723 } 1724 1725 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1726 return implementation(NULL, ra_, true, NULL); 1727 } 1728 1729 #if 0 // TODO: PPC port 1730 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { 1731 #ifndef PRODUCT 1732 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; 1733 #endif 1734 assert(ra_->node_regs_max_index() != 0, ""); 1735 1736 // Get registers to move. 1737 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); 1738 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); 1739 OptoReg::Name dst_hi = ra_->get_reg_second(n); 1740 OptoReg::Name dst_lo = ra_->get_reg_first(n); 1741 1742 enum RC src_lo_rc = rc_class(src_lo); 1743 enum RC dst_lo_rc = rc_class(dst_lo); 1744 1745 if (src_lo == dst_lo && src_hi == dst_hi) 1746 return ppc64Opcode_none; // Self copy, no move. 1747 1748 // -------------------------------------- 1749 // Memory->Memory Spill. Use R0 to hold the value. 1750 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1751 return ppc64Opcode_compound; 1752 } 1753 1754 // -------------------------------------- 1755 // Check for float->int copy; requires a trip through memory. 1756 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1757 Unimplemented(); 1758 } 1759 1760 // -------------------------------------- 1761 // Check for integer reg-reg copy. 1762 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1763 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1764 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1765 if (Rsrc == Rdst) { 1766 return ppc64Opcode_none; 1767 } else { 1768 return ppc64Opcode_or; 1769 } 1770 } 1771 1772 // Check for integer store. 1773 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1774 if (src_hi != OptoReg::Bad) { 1775 return ppc64Opcode_std; 1776 } else { 1777 return ppc64Opcode_stw; 1778 } 1779 } 1780 1781 // Check for integer load. 1782 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1783 if (src_hi != OptoReg::Bad) { 1784 return ppc64Opcode_ld; 1785 } else { 1786 return ppc64Opcode_lwz; 1787 } 1788 } 1789 1790 // Check for float reg-reg copy. 1791 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1792 return ppc64Opcode_fmr; 1793 } 1794 1795 // Check for float store. 1796 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1797 if (src_hi != OptoReg::Bad) { 1798 return ppc64Opcode_stfd; 1799 } else { 1800 return ppc64Opcode_stfs; 1801 } 1802 } 1803 1804 // Check for float load. 1805 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1806 if (src_hi != OptoReg::Bad) { 1807 return ppc64Opcode_lfd; 1808 } else { 1809 return ppc64Opcode_lfs; 1810 } 1811 } 1812 1813 // -------------------------------------------------------------------- 1814 // Check for hi bits still needing moving. Only happens for misaligned 1815 // arguments to native calls. 1816 if (src_hi == dst_hi) { 1817 return ppc64Opcode_none; // Self copy; no move. 1818 } 1819 1820 ShouldNotReachHere(); 1821 return ppc64Opcode_undefined; 1822 } 1823 #endif // PPC port 1824 1825 #ifndef PRODUCT 1826 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1827 st->print("NOP \t// %d nops to pad for loops.", _count); 1828 } 1829 #endif 1830 1831 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1832 MacroAssembler _masm(&cbuf); 1833 // _count contains the number of nops needed for padding. 1834 for (int i = 0; i < _count; i++) { 1835 __ nop(); 1836 } 1837 } 1838 1839 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1840 return _count * 4; 1841 } 1842 1843 #ifndef PRODUCT 1844 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1845 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1846 char reg_str[128]; 1847 ra_->dump_register(this, reg_str); 1848 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset); 1849 } 1850 #endif 1851 1852 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1853 MacroAssembler _masm(&cbuf); 1854 1855 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1856 int reg = ra_->get_encode(this); 1857 1858 if (Assembler::is_simm(offset, 16)) { 1859 __ addi(as_Register(reg), R1, offset); 1860 } else { 1861 ShouldNotReachHere(); 1862 } 1863 } 1864 1865 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1866 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). 1867 return 4; 1868 } 1869 1870 #ifndef PRODUCT 1871 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1872 st->print_cr("---- MachUEPNode ----"); 1873 st->print_cr("..."); 1874 } 1875 #endif 1876 1877 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1878 // This is the unverified entry point. 1879 MacroAssembler _masm(&cbuf); 1880 1881 // Inline_cache contains a klass. 1882 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 1883 Register receiver_klass = R12_scratch2; // tmp 1884 1885 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); 1886 assert(R11_scratch1 == R11, "need prologue scratch register"); 1887 1888 // Check for NULL argument if we don't have implicit null checks. 1889 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { 1890 if (TrapBasedNullChecks) { 1891 __ trap_null_check(R3_ARG1); 1892 } else { 1893 Label valid; 1894 __ cmpdi(CCR0, R3_ARG1, 0); 1895 __ bne_predict_taken(CCR0, valid); 1896 // We have a null argument, branch to ic_miss_stub. 1897 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 1898 relocInfo::runtime_call_type); 1899 __ bind(valid); 1900 } 1901 } 1902 // Assume argument is not NULL, load klass from receiver. 1903 __ load_klass(receiver_klass, R3_ARG1); 1904 1905 if (TrapBasedICMissChecks) { 1906 __ trap_ic_miss_check(receiver_klass, ic_klass); 1907 } else { 1908 Label valid; 1909 __ cmpd(CCR0, receiver_klass, ic_klass); 1910 __ beq_predict_taken(CCR0, valid); 1911 // We have an unexpected klass, branch to ic_miss_stub. 1912 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 1913 relocInfo::runtime_call_type); 1914 __ bind(valid); 1915 } 1916 1917 // Argument is valid and klass is as expected, continue. 1918 } 1919 1920 #if 0 // TODO: PPC port 1921 // Optimize UEP code on z (save a load_const() call in main path). 1922 int MachUEPNode::ep_offset() { 1923 return 0; 1924 } 1925 #endif 1926 1927 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1928 // Variable size. Determine dynamically. 1929 return MachNode::size(ra_); 1930 } 1931 1932 //============================================================================= 1933 1934 %} // interrupt source 1935 1936 source_hpp %{ // Header information of the source block. 1937 1938 class HandlerImpl { 1939 1940 public: 1941 1942 static int emit_exception_handler(CodeBuffer &cbuf); 1943 static int emit_deopt_handler(CodeBuffer& cbuf); 1944 1945 static uint size_exception_handler() { 1946 // The exception_handler is a b64_patchable. 1947 return MacroAssembler::b64_patchable_size; 1948 } 1949 1950 static uint size_deopt_handler() { 1951 // The deopt_handler is a bl64_patchable. 1952 return MacroAssembler::bl64_patchable_size; 1953 } 1954 1955 }; 1956 1957 %} // end source_hpp 1958 1959 source %{ 1960 1961 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 1962 MacroAssembler _masm(&cbuf); 1963 1964 address base = __ start_a_stub(size_exception_handler()); 1965 if (base == NULL) return 0; // CodeBuffer::expand failed 1966 1967 int offset = __ offset(); 1968 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), 1969 relocInfo::runtime_call_type); 1970 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); 1971 __ end_a_stub(); 1972 1973 return offset; 1974 } 1975 1976 // The deopt_handler is like the exception handler, but it calls to 1977 // the deoptimization blob instead of jumping to the exception blob. 1978 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1979 MacroAssembler _masm(&cbuf); 1980 1981 address base = __ start_a_stub(size_deopt_handler()); 1982 if (base == NULL) return 0; // CodeBuffer::expand failed 1983 1984 int offset = __ offset(); 1985 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), 1986 relocInfo::runtime_call_type); 1987 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 1988 __ end_a_stub(); 1989 1990 return offset; 1991 } 1992 1993 //============================================================================= 1994 1995 // Use a frame slots bias for frameless methods if accessing the stack. 1996 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { 1997 if (as_Register(reg_enc) == R1_SP) { 1998 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); 1999 } 2000 return 0; 2001 } 2002 2003 const bool Matcher::match_rule_supported(int opcode) { 2004 if (!has_match_rule(opcode)) 2005 return false; 2006 2007 switch (opcode) { 2008 case Op_SqrtD: 2009 return VM_Version::has_fsqrt(); 2010 case Op_CountLeadingZerosI: 2011 case Op_CountLeadingZerosL: 2012 case Op_CountTrailingZerosI: 2013 case Op_CountTrailingZerosL: 2014 if (!UseCountLeadingZerosInstructionsPPC64) 2015 return false; 2016 break; 2017 2018 case Op_PopCountI: 2019 case Op_PopCountL: 2020 return (UsePopCountInstruction && VM_Version::has_popcntw()); 2021 2022 case Op_StrComp: 2023 return SpecialStringCompareTo && !CompactStrings; 2024 case Op_StrEquals: 2025 return SpecialStringEquals && !CompactStrings; 2026 case Op_StrIndexOf: 2027 return SpecialStringIndexOf && !CompactStrings; 2028 } 2029 2030 return true; // Per default match rules are supported. 2031 } 2032 2033 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 2034 2035 // TODO 2036 // identify extra cases that we might want to provide match rules for 2037 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 2038 bool ret_value = match_rule_supported(opcode); 2039 // Add rules here. 2040 2041 return ret_value; // Per default match rules are supported. 2042 } 2043 2044 const int Matcher::float_pressure(int default_pressure_threshold) { 2045 return default_pressure_threshold; 2046 } 2047 2048 int Matcher::regnum_to_fpu_offset(int regnum) { 2049 // No user for this method? 2050 Unimplemented(); 2051 return 999; 2052 } 2053 2054 const bool Matcher::convL2FSupported(void) { 2055 // fcfids can do the conversion (>= Power7). 2056 // fcfid + frsp showed rounding problem when result should be 0x3f800001. 2057 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. 2058 } 2059 2060 // Vector width in bytes. 2061 const int Matcher::vector_width_in_bytes(BasicType bt) { 2062 assert(MaxVectorSize == 8, ""); 2063 return 8; 2064 } 2065 2066 // Vector ideal reg. 2067 const int Matcher::vector_ideal_reg(int size) { 2068 assert(MaxVectorSize == 8 && size == 8, ""); 2069 return Op_RegL; 2070 } 2071 2072 const int Matcher::vector_shift_count_ideal_reg(int size) { 2073 fatal("vector shift is not supported"); 2074 return Node::NotAMachineReg; 2075 } 2076 2077 // Limits on vector size (number of elements) loaded into vector. 2078 const int Matcher::max_vector_size(const BasicType bt) { 2079 assert(is_java_primitive(bt), "only primitive type vectors"); 2080 return vector_width_in_bytes(bt)/type2aelembytes(bt); 2081 } 2082 2083 const int Matcher::min_vector_size(const BasicType bt) { 2084 return max_vector_size(bt); // Same as max. 2085 } 2086 2087 // PPC doesn't support misaligned vectors store/load. 2088 const bool Matcher::misaligned_vectors_ok() { 2089 return false; 2090 } 2091 2092 // PPC AES support not yet implemented 2093 const bool Matcher::pass_original_key_for_aes() { 2094 return false; 2095 } 2096 2097 // RETURNS: whether this branch offset is short enough that a short 2098 // branch can be used. 2099 // 2100 // If the platform does not provide any short branch variants, then 2101 // this method should return `false' for offset 0. 2102 // 2103 // `Compile::Fill_buffer' will decide on basis of this information 2104 // whether to do the pass `Compile::Shorten_branches' at all. 2105 // 2106 // And `Compile::Shorten_branches' will decide on basis of this 2107 // information whether to replace particular branch sites by short 2108 // ones. 2109 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 2110 // Is the offset within the range of a ppc64 pc relative branch? 2111 bool b; 2112 2113 const int safety_zone = 3 * BytesPerInstWord; 2114 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), 2115 29 - 16 + 1 + 2); 2116 return b; 2117 } 2118 2119 const bool Matcher::isSimpleConstant64(jlong value) { 2120 // Probably always true, even if a temp register is required. 2121 return true; 2122 } 2123 /* TODO: PPC port 2124 // Make a new machine dependent decode node (with its operands). 2125 MachTypeNode *Matcher::make_decode_node() { 2126 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, 2127 "This method is only implemented for unscaled cOops mode so far"); 2128 MachTypeNode *decode = new decodeN_unscaledNode(); 2129 decode->set_opnd_array(0, new iRegPdstOper()); 2130 decode->set_opnd_array(1, new iRegNsrcOper()); 2131 return decode; 2132 } 2133 */ 2134 // Threshold size for cleararray. 2135 const int Matcher::init_array_short_size = 8 * BytesPerLong; 2136 2137 // false => size gets scaled to BytesPerLong, ok. 2138 const bool Matcher::init_array_count_is_in_bytes = false; 2139 2140 // Use conditional move (CMOVL) on Power7. 2141 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves 2142 2143 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. 2144 // fsel doesn't accept a condition register as input, so this would be slightly different. 2145 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 2146 2147 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand). 2148 const bool Matcher::require_postalloc_expand = true; 2149 2150 // Should the Matcher clone shifts on addressing modes, expecting them to 2151 // be subsumed into complex addressing expressions or compute them into 2152 // registers? True for Intel but false for most RISCs. 2153 const bool Matcher::clone_shift_expressions = false; 2154 2155 // Do we need to mask the count passed to shift instructions or does 2156 // the cpu only look at the lower 5/6 bits anyway? 2157 // PowerPC requires masked shift counts. 2158 const bool Matcher::need_masked_shift_count = true; 2159 2160 // This affects two different things: 2161 // - how Decode nodes are matched 2162 // - how ImplicitNullCheck opportunities are recognized 2163 // If true, the matcher will try to remove all Decodes and match them 2164 // (as operands) into nodes. NullChecks are not prepared to deal with 2165 // Decodes by final_graph_reshaping(). 2166 // If false, final_graph_reshaping() forces the decode behind the Cmp 2167 // for a NullCheck. The matcher matches the Decode node into a register. 2168 // Implicit_null_check optimization moves the Decode along with the 2169 // memory operation back up before the NullCheck. 2170 bool Matcher::narrow_oop_use_complex_address() { 2171 // TODO: PPC port if (MatchDecodeNodes) return true; 2172 return false; 2173 } 2174 2175 bool Matcher::narrow_klass_use_complex_address() { 2176 NOT_LP64(ShouldNotCallThis()); 2177 assert(UseCompressedClassPointers, "only for compressed klass code"); 2178 // TODO: PPC port if (MatchDecodeNodes) return true; 2179 return false; 2180 } 2181 2182 // Is it better to copy float constants, or load them directly from memory? 2183 // Intel can load a float constant from a direct address, requiring no 2184 // extra registers. Most RISCs will have to materialize an address into a 2185 // register first, so they would do better to copy the constant from stack. 2186 const bool Matcher::rematerialize_float_constants = false; 2187 2188 // If CPU can load and store mis-aligned doubles directly then no fixup is 2189 // needed. Else we split the double into 2 integer pieces and move it 2190 // piece-by-piece. Only happens when passing doubles into C code as the 2191 // Java calling convention forces doubles to be aligned. 2192 const bool Matcher::misaligned_doubles_ok = true; 2193 2194 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 2195 Unimplemented(); 2196 } 2197 2198 // Advertise here if the CPU requires explicit rounding operations 2199 // to implement the UseStrictFP mode. 2200 const bool Matcher::strict_fp_requires_explicit_rounding = false; 2201 2202 // Do floats take an entire double register or just half? 2203 // 2204 // A float occupies a ppc64 double register. For the allocator, a 2205 // ppc64 double register appears as a pair of float registers. 2206 bool Matcher::float_in_double() { return true; } 2207 2208 // Do ints take an entire long register or just half? 2209 // The relevant question is how the int is callee-saved: 2210 // the whole long is written but de-opt'ing will have to extract 2211 // the relevant 32 bits. 2212 const bool Matcher::int_in_long = true; 2213 2214 // Constants for c2c and c calling conventions. 2215 2216 const MachRegisterNumbers iarg_reg[8] = { 2217 R3_num, R4_num, R5_num, R6_num, 2218 R7_num, R8_num, R9_num, R10_num 2219 }; 2220 2221 const MachRegisterNumbers farg_reg[13] = { 2222 F1_num, F2_num, F3_num, F4_num, 2223 F5_num, F6_num, F7_num, F8_num, 2224 F9_num, F10_num, F11_num, F12_num, 2225 F13_num 2226 }; 2227 2228 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); 2229 2230 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); 2231 2232 // Return whether or not this register is ever used as an argument. This 2233 // function is used on startup to build the trampoline stubs in generateOptoStub. 2234 // Registers not mentioned will be killed by the VM call in the trampoline, and 2235 // arguments in those registers not be available to the callee. 2236 bool Matcher::can_be_java_arg(int reg) { 2237 // We return true for all registers contained in iarg_reg[] and 2238 // farg_reg[] and their virtual halves. 2239 // We must include the virtual halves in order to get STDs and LDs 2240 // instead of STWs and LWs in the trampoline stubs. 2241 2242 if ( reg == R3_num || reg == R3_H_num 2243 || reg == R4_num || reg == R4_H_num 2244 || reg == R5_num || reg == R5_H_num 2245 || reg == R6_num || reg == R6_H_num 2246 || reg == R7_num || reg == R7_H_num 2247 || reg == R8_num || reg == R8_H_num 2248 || reg == R9_num || reg == R9_H_num 2249 || reg == R10_num || reg == R10_H_num) 2250 return true; 2251 2252 if ( reg == F1_num || reg == F1_H_num 2253 || reg == F2_num || reg == F2_H_num 2254 || reg == F3_num || reg == F3_H_num 2255 || reg == F4_num || reg == F4_H_num 2256 || reg == F5_num || reg == F5_H_num 2257 || reg == F6_num || reg == F6_H_num 2258 || reg == F7_num || reg == F7_H_num 2259 || reg == F8_num || reg == F8_H_num 2260 || reg == F9_num || reg == F9_H_num 2261 || reg == F10_num || reg == F10_H_num 2262 || reg == F11_num || reg == F11_H_num 2263 || reg == F12_num || reg == F12_H_num 2264 || reg == F13_num || reg == F13_H_num) 2265 return true; 2266 2267 return false; 2268 } 2269 2270 bool Matcher::is_spillable_arg(int reg) { 2271 return can_be_java_arg(reg); 2272 } 2273 2274 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 2275 return false; 2276 } 2277 2278 // Register for DIVI projection of divmodI. 2279 RegMask Matcher::divI_proj_mask() { 2280 ShouldNotReachHere(); 2281 return RegMask(); 2282 } 2283 2284 // Register for MODI projection of divmodI. 2285 RegMask Matcher::modI_proj_mask() { 2286 ShouldNotReachHere(); 2287 return RegMask(); 2288 } 2289 2290 // Register for DIVL projection of divmodL. 2291 RegMask Matcher::divL_proj_mask() { 2292 ShouldNotReachHere(); 2293 return RegMask(); 2294 } 2295 2296 // Register for MODL projection of divmodL. 2297 RegMask Matcher::modL_proj_mask() { 2298 ShouldNotReachHere(); 2299 return RegMask(); 2300 } 2301 2302 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2303 return RegMask(); 2304 } 2305 2306 %} 2307 2308 //----------ENCODING BLOCK----------------------------------------------------- 2309 // This block specifies the encoding classes used by the compiler to output 2310 // byte streams. Encoding classes are parameterized macros used by 2311 // Machine Instruction Nodes in order to generate the bit encoding of the 2312 // instruction. Operands specify their base encoding interface with the 2313 // interface keyword. There are currently supported four interfaces, 2314 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2315 // operand to generate a function which returns its register number when 2316 // queried. CONST_INTER causes an operand to generate a function which 2317 // returns the value of the constant when queried. MEMORY_INTER causes an 2318 // operand to generate four functions which return the Base Register, the 2319 // Index Register, the Scale Value, and the Offset Value of the operand when 2320 // queried. COND_INTER causes an operand to generate six functions which 2321 // return the encoding code (ie - encoding bits for the instruction) 2322 // associated with each basic boolean condition for a conditional instruction. 2323 // 2324 // Instructions specify two basic values for encoding. Again, a function 2325 // is available to check if the constant displacement is an oop. They use the 2326 // ins_encode keyword to specify their encoding classes (which must be 2327 // a sequence of enc_class names, and their parameters, specified in 2328 // the encoding block), and they use the 2329 // opcode keyword to specify, in order, their primary, secondary, and 2330 // tertiary opcode. Only the opcode sections which a particular instruction 2331 // needs for encoding need to be specified. 2332 encode %{ 2333 enc_class enc_unimplemented %{ 2334 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2335 MacroAssembler _masm(&cbuf); 2336 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 2337 %} 2338 2339 enc_class enc_untested %{ 2340 #ifdef ASSERT 2341 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2342 MacroAssembler _masm(&cbuf); 2343 __ untested("Untested mach node encoding in AD file."); 2344 #else 2345 // TODO: PPC port $archOpcode(ppc64Opcode_none); 2346 #endif 2347 %} 2348 2349 enc_class enc_lbz(iRegIdst dst, memory mem) %{ 2350 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); 2351 MacroAssembler _masm(&cbuf); 2352 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2353 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2354 %} 2355 2356 // Load acquire. 2357 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ 2358 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2359 MacroAssembler _masm(&cbuf); 2360 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2361 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2362 __ twi_0($dst$$Register); 2363 __ isync(); 2364 %} 2365 2366 enc_class enc_lhz(iRegIdst dst, memory mem) %{ 2367 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); 2368 2369 MacroAssembler _masm(&cbuf); 2370 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2371 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2372 %} 2373 2374 // Load acquire. 2375 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ 2376 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2377 2378 MacroAssembler _masm(&cbuf); 2379 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2380 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2381 __ twi_0($dst$$Register); 2382 __ isync(); 2383 %} 2384 2385 enc_class enc_lwz(iRegIdst dst, memory mem) %{ 2386 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); 2387 2388 MacroAssembler _masm(&cbuf); 2389 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2390 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2391 %} 2392 2393 // Load acquire. 2394 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ 2395 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2396 2397 MacroAssembler _masm(&cbuf); 2398 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2399 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2400 __ twi_0($dst$$Register); 2401 __ isync(); 2402 %} 2403 2404 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ 2405 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2406 MacroAssembler _masm(&cbuf); 2407 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2408 // Operand 'ds' requires 4-alignment. 2409 assert((Idisp & 0x3) == 0, "unaligned offset"); 2410 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2411 %} 2412 2413 // Load acquire. 2414 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ 2415 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2416 MacroAssembler _masm(&cbuf); 2417 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2418 // Operand 'ds' requires 4-alignment. 2419 assert((Idisp & 0x3) == 0, "unaligned offset"); 2420 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2421 __ twi_0($dst$$Register); 2422 __ isync(); 2423 %} 2424 2425 enc_class enc_lfd(RegF dst, memory mem) %{ 2426 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 2427 MacroAssembler _masm(&cbuf); 2428 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2429 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 2430 %} 2431 2432 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ 2433 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2434 2435 MacroAssembler _masm(&cbuf); 2436 int toc_offset = 0; 2437 2438 if (!ra_->C->in_scratch_emit_size()) { 2439 address const_toc_addr; 2440 // Create a non-oop constant, no relocation needed. 2441 // If it is an IC, it has a virtual_call_Relocation. 2442 const_toc_addr = __ long_constant((jlong)$src$$constant); 2443 if (const_toc_addr == NULL) { 2444 ciEnv::current()->record_out_of_memory_failure(); 2445 return; 2446 } 2447 2448 // Get the constant's TOC offset. 2449 toc_offset = __ offset_to_method_toc(const_toc_addr); 2450 2451 // Keep the current instruction offset in mind. 2452 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); 2453 } 2454 2455 __ ld($dst$$Register, toc_offset, $toc$$Register); 2456 %} 2457 2458 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ 2459 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2460 2461 MacroAssembler _masm(&cbuf); 2462 2463 if (!ra_->C->in_scratch_emit_size()) { 2464 address const_toc_addr; 2465 // Create a non-oop constant, no relocation needed. 2466 // If it is an IC, it has a virtual_call_Relocation. 2467 const_toc_addr = __ long_constant((jlong)$src$$constant); 2468 if (const_toc_addr == NULL) { 2469 ciEnv::current()->record_out_of_memory_failure(); 2470 return; 2471 } 2472 2473 // Get the constant's TOC offset. 2474 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2475 // Store the toc offset of the constant. 2476 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; 2477 2478 // Also keep the current instruction offset in mind. 2479 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); 2480 } 2481 2482 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2483 %} 2484 2485 %} // encode 2486 2487 source %{ 2488 2489 typedef struct { 2490 loadConL_hiNode *_large_hi; 2491 loadConL_loNode *_large_lo; 2492 loadConLNode *_small; 2493 MachNode *_last; 2494 } loadConLNodesTuple; 2495 2496 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, 2497 OptoReg::Name reg_second, OptoReg::Name reg_first) { 2498 loadConLNodesTuple nodes; 2499 2500 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2501 if (large_constant_pool) { 2502 // Create new nodes. 2503 loadConL_hiNode *m1 = new loadConL_hiNode(); 2504 loadConL_loNode *m2 = new loadConL_loNode(); 2505 2506 // inputs for new nodes 2507 m1->add_req(NULL, toc); 2508 m2->add_req(NULL, m1); 2509 2510 // operands for new nodes 2511 m1->_opnds[0] = new iRegLdstOper(); // dst 2512 m1->_opnds[1] = immSrc; // src 2513 m1->_opnds[2] = new iRegPdstOper(); // toc 2514 m2->_opnds[0] = new iRegLdstOper(); // dst 2515 m2->_opnds[1] = immSrc; // src 2516 m2->_opnds[2] = new iRegLdstOper(); // base 2517 2518 // Initialize ins_attrib TOC fields. 2519 m1->_const_toc_offset = -1; 2520 m2->_const_toc_offset_hi_node = m1; 2521 2522 // Initialize ins_attrib instruction offset. 2523 m1->_cbuf_insts_offset = -1; 2524 2525 // register allocation for new nodes 2526 ra_->set_pair(m1->_idx, reg_second, reg_first); 2527 ra_->set_pair(m2->_idx, reg_second, reg_first); 2528 2529 // Create result. 2530 nodes._large_hi = m1; 2531 nodes._large_lo = m2; 2532 nodes._small = NULL; 2533 nodes._last = nodes._large_lo; 2534 assert(m2->bottom_type()->isa_long(), "must be long"); 2535 } else { 2536 loadConLNode *m2 = new loadConLNode(); 2537 2538 // inputs for new nodes 2539 m2->add_req(NULL, toc); 2540 2541 // operands for new nodes 2542 m2->_opnds[0] = new iRegLdstOper(); // dst 2543 m2->_opnds[1] = immSrc; // src 2544 m2->_opnds[2] = new iRegPdstOper(); // toc 2545 2546 // Initialize ins_attrib instruction offset. 2547 m2->_cbuf_insts_offset = -1; 2548 2549 // register allocation for new nodes 2550 ra_->set_pair(m2->_idx, reg_second, reg_first); 2551 2552 // Create result. 2553 nodes._large_hi = NULL; 2554 nodes._large_lo = NULL; 2555 nodes._small = m2; 2556 nodes._last = nodes._small; 2557 assert(m2->bottom_type()->isa_long(), "must be long"); 2558 } 2559 2560 return nodes; 2561 } 2562 2563 %} // source 2564 2565 encode %{ 2566 // Postalloc expand emitter for loading a long constant from the method's TOC. 2567 // Enc_class needed as consttanttablebase is not supported by postalloc 2568 // expand. 2569 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ 2570 // Create new nodes. 2571 loadConLNodesTuple loadConLNodes = 2572 loadConLNodesTuple_create(ra_, n_toc, op_src, 2573 ra_->get_reg_second(this), ra_->get_reg_first(this)); 2574 2575 // Push new nodes. 2576 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 2577 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 2578 2579 // some asserts 2580 assert(nodes->length() >= 1, "must have created at least 1 node"); 2581 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 2582 %} 2583 2584 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ 2585 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2586 2587 MacroAssembler _masm(&cbuf); 2588 int toc_offset = 0; 2589 2590 if (!ra_->C->in_scratch_emit_size()) { 2591 intptr_t val = $src$$constant; 2592 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2593 address const_toc_addr; 2594 if (constant_reloc == relocInfo::oop_type) { 2595 // Create an oop constant and a corresponding relocation. 2596 AddressLiteral a = __ allocate_oop_address((jobject)val); 2597 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2598 __ relocate(a.rspec()); 2599 } else if (constant_reloc == relocInfo::metadata_type) { 2600 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2601 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2602 __ relocate(a.rspec()); 2603 } else { 2604 // Create a non-oop constant, no relocation needed. 2605 const_toc_addr = __ long_constant((jlong)$src$$constant); 2606 } 2607 2608 if (const_toc_addr == NULL) { 2609 ciEnv::current()->record_out_of_memory_failure(); 2610 return; 2611 } 2612 // Get the constant's TOC offset. 2613 toc_offset = __ offset_to_method_toc(const_toc_addr); 2614 } 2615 2616 __ ld($dst$$Register, toc_offset, $toc$$Register); 2617 %} 2618 2619 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ 2620 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2621 2622 MacroAssembler _masm(&cbuf); 2623 if (!ra_->C->in_scratch_emit_size()) { 2624 intptr_t val = $src$$constant; 2625 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2626 address const_toc_addr; 2627 if (constant_reloc == relocInfo::oop_type) { 2628 // Create an oop constant and a corresponding relocation. 2629 AddressLiteral a = __ allocate_oop_address((jobject)val); 2630 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2631 __ relocate(a.rspec()); 2632 } else if (constant_reloc == relocInfo::metadata_type) { 2633 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2634 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2635 __ relocate(a.rspec()); 2636 } else { // non-oop pointers, e.g. card mark base, heap top 2637 // Create a non-oop constant, no relocation needed. 2638 const_toc_addr = __ long_constant((jlong)$src$$constant); 2639 } 2640 2641 if (const_toc_addr == NULL) { 2642 ciEnv::current()->record_out_of_memory_failure(); 2643 return; 2644 } 2645 // Get the constant's TOC offset. 2646 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2647 // Store the toc offset of the constant. 2648 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; 2649 } 2650 2651 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2652 %} 2653 2654 // Postalloc expand emitter for loading a ptr constant from the method's TOC. 2655 // Enc_class needed as consttanttablebase is not supported by postalloc 2656 // expand. 2657 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ 2658 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2659 if (large_constant_pool) { 2660 // Create new nodes. 2661 loadConP_hiNode *m1 = new loadConP_hiNode(); 2662 loadConP_loNode *m2 = new loadConP_loNode(); 2663 2664 // inputs for new nodes 2665 m1->add_req(NULL, n_toc); 2666 m2->add_req(NULL, m1); 2667 2668 // operands for new nodes 2669 m1->_opnds[0] = new iRegPdstOper(); // dst 2670 m1->_opnds[1] = op_src; // src 2671 m1->_opnds[2] = new iRegPdstOper(); // toc 2672 m2->_opnds[0] = new iRegPdstOper(); // dst 2673 m2->_opnds[1] = op_src; // src 2674 m2->_opnds[2] = new iRegLdstOper(); // base 2675 2676 // Initialize ins_attrib TOC fields. 2677 m1->_const_toc_offset = -1; 2678 m2->_const_toc_offset_hi_node = m1; 2679 2680 // Register allocation for new nodes. 2681 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2682 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2683 2684 nodes->push(m1); 2685 nodes->push(m2); 2686 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2687 } else { 2688 loadConPNode *m2 = new loadConPNode(); 2689 2690 // inputs for new nodes 2691 m2->add_req(NULL, n_toc); 2692 2693 // operands for new nodes 2694 m2->_opnds[0] = new iRegPdstOper(); // dst 2695 m2->_opnds[1] = op_src; // src 2696 m2->_opnds[2] = new iRegPdstOper(); // toc 2697 2698 // Register allocation for new nodes. 2699 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2700 2701 nodes->push(m2); 2702 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2703 } 2704 %} 2705 2706 // Enc_class needed as consttanttablebase is not supported by postalloc 2707 // expand. 2708 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ 2709 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2710 2711 MachNode *m2; 2712 if (large_constant_pool) { 2713 m2 = new loadConFCompNode(); 2714 } else { 2715 m2 = new loadConFNode(); 2716 } 2717 // inputs for new nodes 2718 m2->add_req(NULL, n_toc); 2719 2720 // operands for new nodes 2721 m2->_opnds[0] = op_dst; 2722 m2->_opnds[1] = op_src; 2723 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2724 2725 // register allocation for new nodes 2726 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2727 nodes->push(m2); 2728 %} 2729 2730 // Enc_class needed as consttanttablebase is not supported by postalloc 2731 // expand. 2732 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ 2733 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2734 2735 MachNode *m2; 2736 if (large_constant_pool) { 2737 m2 = new loadConDCompNode(); 2738 } else { 2739 m2 = new loadConDNode(); 2740 } 2741 // inputs for new nodes 2742 m2->add_req(NULL, n_toc); 2743 2744 // operands for new nodes 2745 m2->_opnds[0] = op_dst; 2746 m2->_opnds[1] = op_src; 2747 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2748 2749 // register allocation for new nodes 2750 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2751 nodes->push(m2); 2752 %} 2753 2754 enc_class enc_stw(iRegIsrc src, memory mem) %{ 2755 // TODO: PPC port $archOpcode(ppc64Opcode_stw); 2756 MacroAssembler _masm(&cbuf); 2757 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2758 __ stw($src$$Register, Idisp, $mem$$base$$Register); 2759 %} 2760 2761 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ 2762 // TODO: PPC port $archOpcode(ppc64Opcode_std); 2763 MacroAssembler _masm(&cbuf); 2764 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2765 // Operand 'ds' requires 4-alignment. 2766 assert((Idisp & 0x3) == 0, "unaligned offset"); 2767 __ std($src$$Register, Idisp, $mem$$base$$Register); 2768 %} 2769 2770 enc_class enc_stfs(RegF src, memory mem) %{ 2771 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); 2772 MacroAssembler _masm(&cbuf); 2773 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2774 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); 2775 %} 2776 2777 enc_class enc_stfd(RegF src, memory mem) %{ 2778 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); 2779 MacroAssembler _masm(&cbuf); 2780 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2781 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); 2782 %} 2783 2784 // Use release_store for card-marking to ensure that previous 2785 // oop-stores are visible before the card-mark change. 2786 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{ 2787 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2788 // FIXME: Implement this as a cmove and use a fixed condition code 2789 // register which is written on every transition to compiled code, 2790 // e.g. in call-stub and when returning from runtime stubs. 2791 // 2792 // Proposed code sequence for the cmove implementation: 2793 // 2794 // Label skip_release; 2795 // __ beq(CCRfixed, skip_release); 2796 // __ release(); 2797 // __ bind(skip_release); 2798 // __ stb(card mark); 2799 2800 MacroAssembler _masm(&cbuf); 2801 Label skip_storestore; 2802 2803 #if 0 // TODO: PPC port 2804 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the 2805 // StoreStore barrier conditionally. 2806 __ lwz(R0, 0, $releaseFieldAddr$$Register); 2807 __ cmpwi($crx$$CondRegister, R0, 0); 2808 __ beq_predict_taken($crx$$CondRegister, skip_storestore); 2809 #endif 2810 __ li(R0, 0); 2811 __ membar(Assembler::StoreStore); 2812 #if 0 // TODO: PPC port 2813 __ bind(skip_storestore); 2814 #endif 2815 2816 // Do the store. 2817 if ($mem$$index == 0) { 2818 __ stb(R0, $mem$$disp, $mem$$base$$Register); 2819 } else { 2820 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); 2821 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); 2822 } 2823 %} 2824 2825 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ 2826 2827 if (VM_Version::has_isel()) { 2828 // use isel instruction with Power 7 2829 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2830 encodeP_subNode *n_sub_base = new encodeP_subNode(); 2831 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2832 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode(); 2833 2834 n_compare->add_req(n_region, n_src); 2835 n_compare->_opnds[0] = op_crx; 2836 n_compare->_opnds[1] = op_src; 2837 n_compare->_opnds[2] = new immL16Oper(0); 2838 2839 n_sub_base->add_req(n_region, n_src); 2840 n_sub_base->_opnds[0] = op_dst; 2841 n_sub_base->_opnds[1] = op_src; 2842 n_sub_base->_bottom_type = _bottom_type; 2843 2844 n_shift->add_req(n_region, n_sub_base); 2845 n_shift->_opnds[0] = op_dst; 2846 n_shift->_opnds[1] = op_dst; 2847 n_shift->_bottom_type = _bottom_type; 2848 2849 n_cond_set->add_req(n_region, n_compare, n_shift); 2850 n_cond_set->_opnds[0] = op_dst; 2851 n_cond_set->_opnds[1] = op_crx; 2852 n_cond_set->_opnds[2] = op_dst; 2853 n_cond_set->_bottom_type = _bottom_type; 2854 2855 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2856 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2857 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2858 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2859 2860 nodes->push(n_compare); 2861 nodes->push(n_sub_base); 2862 nodes->push(n_shift); 2863 nodes->push(n_cond_set); 2864 2865 } else { 2866 // before Power 7 2867 moveRegNode *n_move = new moveRegNode(); 2868 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2869 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2870 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode(); 2871 2872 n_move->add_req(n_region, n_src); 2873 n_move->_opnds[0] = op_dst; 2874 n_move->_opnds[1] = op_src; 2875 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. 2876 2877 n_compare->add_req(n_region, n_src); 2878 n_compare->add_prec(n_move); 2879 2880 n_compare->_opnds[0] = op_crx; 2881 n_compare->_opnds[1] = op_src; 2882 n_compare->_opnds[2] = new immL16Oper(0); 2883 2884 n_sub_base->add_req(n_region, n_compare, n_src); 2885 n_sub_base->_opnds[0] = op_dst; 2886 n_sub_base->_opnds[1] = op_crx; 2887 n_sub_base->_opnds[2] = op_src; 2888 n_sub_base->_bottom_type = _bottom_type; 2889 2890 n_shift->add_req(n_region, n_sub_base); 2891 n_shift->_opnds[0] = op_dst; 2892 n_shift->_opnds[1] = op_dst; 2893 n_shift->_bottom_type = _bottom_type; 2894 2895 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2896 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2897 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2898 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2899 2900 nodes->push(n_move); 2901 nodes->push(n_compare); 2902 nodes->push(n_sub_base); 2903 nodes->push(n_shift); 2904 } 2905 2906 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2907 %} 2908 2909 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ 2910 2911 encodeP_subNode *n1 = new encodeP_subNode(); 2912 n1->add_req(n_region, n_src); 2913 n1->_opnds[0] = op_dst; 2914 n1->_opnds[1] = op_src; 2915 n1->_bottom_type = _bottom_type; 2916 2917 encodeP_shiftNode *n2 = new encodeP_shiftNode(); 2918 n2->add_req(n_region, n1); 2919 n2->_opnds[0] = op_dst; 2920 n2->_opnds[1] = op_dst; 2921 n2->_bottom_type = _bottom_type; 2922 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2923 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2924 2925 nodes->push(n1); 2926 nodes->push(n2); 2927 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2928 %} 2929 2930 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 2931 decodeN_shiftNode *n_shift = new decodeN_shiftNode(); 2932 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 2933 2934 n_compare->add_req(n_region, n_src); 2935 n_compare->_opnds[0] = op_crx; 2936 n_compare->_opnds[1] = op_src; 2937 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 2938 2939 n_shift->add_req(n_region, n_src); 2940 n_shift->_opnds[0] = op_dst; 2941 n_shift->_opnds[1] = op_src; 2942 n_shift->_bottom_type = _bottom_type; 2943 2944 if (VM_Version::has_isel()) { 2945 // use isel instruction with Power 7 2946 2947 decodeN_addNode *n_add_base = new decodeN_addNode(); 2948 n_add_base->add_req(n_region, n_shift); 2949 n_add_base->_opnds[0] = op_dst; 2950 n_add_base->_opnds[1] = op_dst; 2951 n_add_base->_bottom_type = _bottom_type; 2952 2953 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 2954 n_cond_set->add_req(n_region, n_compare, n_add_base); 2955 n_cond_set->_opnds[0] = op_dst; 2956 n_cond_set->_opnds[1] = op_crx; 2957 n_cond_set->_opnds[2] = op_dst; 2958 n_cond_set->_bottom_type = _bottom_type; 2959 2960 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 2961 ra_->set_oop(n_cond_set, true); 2962 2963 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2964 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2965 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2966 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2967 2968 nodes->push(n_compare); 2969 nodes->push(n_shift); 2970 nodes->push(n_add_base); 2971 nodes->push(n_cond_set); 2972 2973 } else { 2974 // before Power 7 2975 cond_add_baseNode *n_add_base = new cond_add_baseNode(); 2976 2977 n_add_base->add_req(n_region, n_compare, n_shift); 2978 n_add_base->_opnds[0] = op_dst; 2979 n_add_base->_opnds[1] = op_crx; 2980 n_add_base->_opnds[2] = op_dst; 2981 n_add_base->_bottom_type = _bottom_type; 2982 2983 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 2984 ra_->set_oop(n_add_base, true); 2985 2986 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2987 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2988 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2989 2990 nodes->push(n_compare); 2991 nodes->push(n_shift); 2992 nodes->push(n_add_base); 2993 } 2994 %} 2995 2996 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ 2997 decodeN_shiftNode *n1 = new decodeN_shiftNode(); 2998 n1->add_req(n_region, n_src); 2999 n1->_opnds[0] = op_dst; 3000 n1->_opnds[1] = op_src; 3001 n1->_bottom_type = _bottom_type; 3002 3003 decodeN_addNode *n2 = new decodeN_addNode(); 3004 n2->add_req(n_region, n1); 3005 n2->_opnds[0] = op_dst; 3006 n2->_opnds[1] = op_dst; 3007 n2->_bottom_type = _bottom_type; 3008 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3009 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3010 3011 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3012 ra_->set_oop(n2, true); 3013 3014 nodes->push(n1); 3015 nodes->push(n2); 3016 %} 3017 3018 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{ 3019 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3020 3021 MacroAssembler _masm(&cbuf); 3022 int cc = $cmp$$cmpcode; 3023 int flags_reg = $crx$$reg; 3024 Label done; 3025 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3026 // Branch if not (cmp crx). 3027 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); 3028 __ mr($dst$$Register, $src$$Register); 3029 // TODO PPC port __ endgroup_if_needed(_size == 12); 3030 __ bind(done); 3031 %} 3032 3033 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{ 3034 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3035 3036 MacroAssembler _masm(&cbuf); 3037 Label done; 3038 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3039 // Branch if not (cmp crx). 3040 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 3041 __ li($dst$$Register, $src$$constant); 3042 // TODO PPC port __ endgroup_if_needed(_size == 12); 3043 __ bind(done); 3044 %} 3045 3046 // New atomics. 3047 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3048 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3049 3050 MacroAssembler _masm(&cbuf); 3051 Register Rtmp = R0; 3052 Register Rres = $res$$Register; 3053 Register Rsrc = $src$$Register; 3054 Register Rptr = $mem_ptr$$Register; 3055 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3056 Register Rold = RegCollision ? Rtmp : Rres; 3057 3058 Label Lretry; 3059 __ bind(Lretry); 3060 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3061 __ add(Rtmp, Rsrc, Rold); 3062 __ stwcx_(Rtmp, Rptr); 3063 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3064 __ bne_predict_not_taken(CCR0, Lretry); 3065 } else { 3066 __ bne( CCR0, Lretry); 3067 } 3068 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3069 __ fence(); 3070 %} 3071 3072 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3073 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3074 3075 MacroAssembler _masm(&cbuf); 3076 Register Rtmp = R0; 3077 Register Rres = $res$$Register; 3078 Register Rsrc = $src$$Register; 3079 Register Rptr = $mem_ptr$$Register; 3080 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3081 Register Rold = RegCollision ? Rtmp : Rres; 3082 3083 Label Lretry; 3084 __ bind(Lretry); 3085 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3086 __ add(Rtmp, Rsrc, Rold); 3087 __ stdcx_(Rtmp, Rptr); 3088 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3089 __ bne_predict_not_taken(CCR0, Lretry); 3090 } else { 3091 __ bne( CCR0, Lretry); 3092 } 3093 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3094 __ fence(); 3095 %} 3096 3097 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3098 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3099 3100 MacroAssembler _masm(&cbuf); 3101 Register Rtmp = R0; 3102 Register Rres = $res$$Register; 3103 Register Rsrc = $src$$Register; 3104 Register Rptr = $mem_ptr$$Register; 3105 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3106 Register Rold = RegCollision ? Rtmp : Rres; 3107 3108 Label Lretry; 3109 __ bind(Lretry); 3110 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3111 __ stwcx_(Rsrc, Rptr); 3112 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3113 __ bne_predict_not_taken(CCR0, Lretry); 3114 } else { 3115 __ bne( CCR0, Lretry); 3116 } 3117 if (RegCollision) __ mr(Rres, Rtmp); 3118 __ fence(); 3119 %} 3120 3121 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3122 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3123 3124 MacroAssembler _masm(&cbuf); 3125 Register Rtmp = R0; 3126 Register Rres = $res$$Register; 3127 Register Rsrc = $src$$Register; 3128 Register Rptr = $mem_ptr$$Register; 3129 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3130 Register Rold = RegCollision ? Rtmp : Rres; 3131 3132 Label Lretry; 3133 __ bind(Lretry); 3134 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3135 __ stdcx_(Rsrc, Rptr); 3136 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3137 __ bne_predict_not_taken(CCR0, Lretry); 3138 } else { 3139 __ bne( CCR0, Lretry); 3140 } 3141 if (RegCollision) __ mr(Rres, Rtmp); 3142 __ fence(); 3143 %} 3144 3145 // This enc_class is needed so that scheduler gets proper 3146 // input mapping for latency computation. 3147 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 3148 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 3149 MacroAssembler _masm(&cbuf); 3150 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 3151 %} 3152 3153 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3154 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3155 3156 MacroAssembler _masm(&cbuf); 3157 3158 Label done; 3159 __ cmpwi($crx$$CondRegister, $src$$Register, 0); 3160 __ li($dst$$Register, $zero$$constant); 3161 __ beq($crx$$CondRegister, done); 3162 __ li($dst$$Register, $notzero$$constant); 3163 __ bind(done); 3164 %} 3165 3166 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3167 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3168 3169 MacroAssembler _masm(&cbuf); 3170 3171 Label done; 3172 __ cmpdi($crx$$CondRegister, $src$$Register, 0); 3173 __ li($dst$$Register, $zero$$constant); 3174 __ beq($crx$$CondRegister, done); 3175 __ li($dst$$Register, $notzero$$constant); 3176 __ bind(done); 3177 %} 3178 3179 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{ 3180 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3181 3182 MacroAssembler _masm(&cbuf); 3183 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 3184 Label done; 3185 __ bso($crx$$CondRegister, done); 3186 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 3187 // TODO PPC port __ endgroup_if_needed(_size == 12); 3188 __ bind(done); 3189 %} 3190 3191 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3192 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3193 3194 MacroAssembler _masm(&cbuf); 3195 Label d; // dummy 3196 __ bind(d); 3197 Label* p = ($lbl$$label); 3198 // `p' is `NULL' when this encoding class is used only to 3199 // determine the size of the encoded instruction. 3200 Label& l = (NULL == p)? d : *(p); 3201 int cc = $cmp$$cmpcode; 3202 int flags_reg = $crx$$reg; 3203 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3204 int bhint = Assembler::bhintNoHint; 3205 3206 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3207 if (_prob <= PROB_NEVER) { 3208 bhint = Assembler::bhintIsNotTaken; 3209 } else if (_prob >= PROB_ALWAYS) { 3210 bhint = Assembler::bhintIsTaken; 3211 } 3212 } 3213 3214 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3215 cc_to_biint(cc, flags_reg), 3216 l); 3217 %} 3218 3219 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3220 // The scheduler doesn't know about branch shortening, so we set the opcode 3221 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3222 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3223 3224 MacroAssembler _masm(&cbuf); 3225 Label d; // dummy 3226 __ bind(d); 3227 Label* p = ($lbl$$label); 3228 // `p' is `NULL' when this encoding class is used only to 3229 // determine the size of the encoded instruction. 3230 Label& l = (NULL == p)? d : *(p); 3231 int cc = $cmp$$cmpcode; 3232 int flags_reg = $crx$$reg; 3233 int bhint = Assembler::bhintNoHint; 3234 3235 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3236 if (_prob <= PROB_NEVER) { 3237 bhint = Assembler::bhintIsNotTaken; 3238 } else if (_prob >= PROB_ALWAYS) { 3239 bhint = Assembler::bhintIsTaken; 3240 } 3241 } 3242 3243 // Tell the conditional far branch to optimize itself when being relocated. 3244 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3245 cc_to_biint(cc, flags_reg), 3246 l, 3247 MacroAssembler::bc_far_optimize_on_relocate); 3248 %} 3249 3250 // Branch used with Power6 scheduling (can be shortened without changing the node). 3251 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3252 // The scheduler doesn't know about branch shortening, so we set the opcode 3253 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3254 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3255 3256 MacroAssembler _masm(&cbuf); 3257 Label d; // dummy 3258 __ bind(d); 3259 Label* p = ($lbl$$label); 3260 // `p' is `NULL' when this encoding class is used only to 3261 // determine the size of the encoded instruction. 3262 Label& l = (NULL == p)? d : *(p); 3263 int cc = $cmp$$cmpcode; 3264 int flags_reg = $crx$$reg; 3265 int bhint = Assembler::bhintNoHint; 3266 3267 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3268 if (_prob <= PROB_NEVER) { 3269 bhint = Assembler::bhintIsNotTaken; 3270 } else if (_prob >= PROB_ALWAYS) { 3271 bhint = Assembler::bhintIsTaken; 3272 } 3273 } 3274 3275 #if 0 // TODO: PPC port 3276 if (_size == 8) { 3277 // Tell the conditional far branch to optimize itself when being relocated. 3278 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3279 cc_to_biint(cc, flags_reg), 3280 l, 3281 MacroAssembler::bc_far_optimize_on_relocate); 3282 } else { 3283 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3284 cc_to_biint(cc, flags_reg), 3285 l); 3286 } 3287 #endif 3288 Unimplemented(); 3289 %} 3290 3291 // Postalloc expand emitter for loading a replicatef float constant from 3292 // the method's TOC. 3293 // Enc_class needed as consttanttablebase is not supported by postalloc 3294 // expand. 3295 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ 3296 // Create new nodes. 3297 3298 // Make an operand with the bit pattern to load as float. 3299 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF())); 3300 3301 loadConLNodesTuple loadConLNodes = 3302 loadConLNodesTuple_create(ra_, n_toc, op_repl, 3303 ra_->get_reg_second(this), ra_->get_reg_first(this)); 3304 3305 // Push new nodes. 3306 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 3307 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 3308 3309 assert(nodes->length() >= 1, "must have created at least 1 node"); 3310 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 3311 %} 3312 3313 // This enc_class is needed so that scheduler gets proper 3314 // input mapping for latency computation. 3315 enc_class enc_poll(immI dst, iRegLdst poll) %{ 3316 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 3317 // Fake operand dst needed for PPC scheduler. 3318 assert($dst$$constant == 0x0, "dst must be 0x0"); 3319 3320 MacroAssembler _masm(&cbuf); 3321 // Mark the code position where the load from the safepoint 3322 // polling page was emitted as relocInfo::poll_type. 3323 __ relocate(relocInfo::poll_type); 3324 __ load_from_polling_page($poll$$Register); 3325 %} 3326 3327 // A Java static call or a runtime call. 3328 // 3329 // Branch-and-link relative to a trampoline. 3330 // The trampoline loads the target address and does a long branch to there. 3331 // In case we call java, the trampoline branches to a interpreter_stub 3332 // which loads the inline cache and the real call target from the constant pool. 3333 // 3334 // This basically looks like this: 3335 // 3336 // >>>> consts -+ -+ 3337 // | |- offset1 3338 // [call target1] | <-+ 3339 // [IC cache] |- offset2 3340 // [call target2] <--+ 3341 // 3342 // <<<< consts 3343 // >>>> insts 3344 // 3345 // bl offset16 -+ -+ ??? // How many bits available? 3346 // | | 3347 // <<<< insts | | 3348 // >>>> stubs | | 3349 // | |- trampoline_stub_Reloc 3350 // trampoline stub: | <-+ 3351 // r2 = toc | 3352 // r2 = [r2 + offset1] | // Load call target1 from const section 3353 // mtctr r2 | 3354 // bctr |- static_stub_Reloc 3355 // comp_to_interp_stub: <---+ 3356 // r1 = toc 3357 // ICreg = [r1 + IC_offset] // Load IC from const section 3358 // r1 = [r1 + offset2] // Load call target2 from const section 3359 // mtctr r1 3360 // bctr 3361 // 3362 // <<<< stubs 3363 // 3364 // The call instruction in the code either 3365 // - Branches directly to a compiled method if the offset is encodable in instruction. 3366 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. 3367 // - Branches to the compiled_to_interp stub if the target is interpreted. 3368 // 3369 // Further there are three relocations from the loads to the constants in 3370 // the constant section. 3371 // 3372 // Usage of r1 and r2 in the stubs allows to distinguish them. 3373 enc_class enc_java_static_call(method meth) %{ 3374 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3375 3376 MacroAssembler _masm(&cbuf); 3377 address entry_point = (address)$meth$$method; 3378 3379 if (!_method) { 3380 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. 3381 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); 3382 } else { 3383 // Remember the offset not the address. 3384 const int start_offset = __ offset(); 3385 // The trampoline stub. 3386 if (!Compile::current()->in_scratch_emit_size()) { 3387 // No entry point given, use the current pc. 3388 // Make sure branch fits into 3389 if (entry_point == 0) entry_point = __ pc(); 3390 3391 // Put the entry point as a constant into the constant pool. 3392 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3393 if (entry_point_toc_addr == NULL) { 3394 ciEnv::current()->record_out_of_memory_failure(); 3395 return; 3396 } 3397 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3398 3399 3400 // Emit the trampoline stub which will be related to the branch-and-link below. 3401 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3402 if (ciEnv::current()->failing()) { return; } // Code cache may be full. 3403 int method_index = resolved_method_index(cbuf); 3404 __ relocate(_optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 3405 : static_call_Relocation::spec(method_index)); 3406 } 3407 3408 // The real call. 3409 // Note: At this point we do not have the address of the trampoline 3410 // stub, and the entry point might be too far away for bl, so __ pc() 3411 // serves as dummy and the bl will be patched later. 3412 cbuf.set_insts_mark(); 3413 __ bl(__ pc()); // Emits a relocation. 3414 3415 // The stub for call to interpreter. 3416 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 3417 if (stub == NULL) { 3418 ciEnv::current()->record_failure("CodeCache is full"); 3419 return; 3420 } 3421 } 3422 %} 3423 3424 // Second node of expanded dynamic call - the call. 3425 enc_class enc_java_dynamic_call_sched(method meth) %{ 3426 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3427 3428 MacroAssembler _masm(&cbuf); 3429 3430 if (!ra_->C->in_scratch_emit_size()) { 3431 // Create a call trampoline stub for the given method. 3432 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; 3433 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); 3434 if (entry_point_const == NULL) { 3435 ciEnv::current()->record_out_of_memory_failure(); 3436 return; 3437 } 3438 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); 3439 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); 3440 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3441 3442 // Build relocation at call site with ic position as data. 3443 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || 3444 (_load_ic_hi_node == NULL && _load_ic_node != NULL), 3445 "must have one, but can't have both"); 3446 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || 3447 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), 3448 "must contain instruction offset"); 3449 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL 3450 ? _load_ic_hi_node->_cbuf_insts_offset 3451 : _load_ic_node->_cbuf_insts_offset; 3452 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); 3453 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), 3454 "should be load from TOC"); 3455 int method_index = resolved_method_index(cbuf); 3456 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index)); 3457 } 3458 3459 // At this point I do not have the address of the trampoline stub, 3460 // and the entry point might be too far away for bl. Pc() serves 3461 // as dummy and bl will be patched later. 3462 __ bl((address) __ pc()); 3463 %} 3464 3465 // postalloc expand emitter for virtual calls. 3466 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ 3467 3468 // Create the nodes for loading the IC from the TOC. 3469 loadConLNodesTuple loadConLNodes_IC = 3470 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()), 3471 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); 3472 3473 // Create the call node. 3474 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode(); 3475 call->_method_handle_invoke = _method_handle_invoke; 3476 call->_vtable_index = _vtable_index; 3477 call->_method = _method; 3478 call->_bci = _bci; 3479 call->_optimized_virtual = _optimized_virtual; 3480 call->_tf = _tf; 3481 call->_entry_point = _entry_point; 3482 call->_cnt = _cnt; 3483 call->_argsize = _argsize; 3484 call->_oop_map = _oop_map; 3485 call->_jvms = _jvms; 3486 call->_jvmadj = _jvmadj; 3487 call->_in_rms = _in_rms; 3488 call->_nesting = _nesting; 3489 call->_override_symbolic_info = _override_symbolic_info; 3490 3491 // New call needs all inputs of old call. 3492 // Req... 3493 for (uint i = 0; i < req(); ++i) { 3494 // The expanded node does not need toc any more. 3495 // Add the inline cache constant here instead. This expresses the 3496 // register of the inline cache must be live at the call. 3497 // Else we would have to adapt JVMState by -1. 3498 if (i == mach_constant_base_node_input()) { 3499 call->add_req(loadConLNodes_IC._last); 3500 } else { 3501 call->add_req(in(i)); 3502 } 3503 } 3504 // ...as well as prec 3505 for (uint i = req(); i < len(); ++i) { 3506 call->add_prec(in(i)); 3507 } 3508 3509 // Remember nodes loading the inline cache into r19. 3510 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; 3511 call->_load_ic_node = loadConLNodes_IC._small; 3512 3513 // Operands for new nodes. 3514 call->_opnds[0] = _opnds[0]; 3515 call->_opnds[1] = _opnds[1]; 3516 3517 // Only the inline cache is associated with a register. 3518 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); 3519 3520 // Push new nodes. 3521 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); 3522 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); 3523 nodes->push(call); 3524 %} 3525 3526 // Compound version of call dynamic 3527 // Toc is only passed so that it can be used in ins_encode statement. 3528 // In the code we have to use $constanttablebase. 3529 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ 3530 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3531 MacroAssembler _masm(&cbuf); 3532 int start_offset = __ offset(); 3533 3534 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; 3535 #if 0 3536 int vtable_index = this->_vtable_index; 3537 if (_vtable_index < 0) { 3538 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 3539 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 3540 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); 3541 3542 // Virtual call relocation will point to ic load. 3543 address virtual_call_meta_addr = __ pc(); 3544 // Load a clear inline cache. 3545 AddressLiteral empty_ic((address) Universe::non_oop_word()); 3546 bool success = __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc, /*fixed_size*/ true); 3547 if (!success) { 3548 ciEnv::current()->record_out_of_memory_failure(); 3549 return; 3550 } 3551 // CALL to fixup routine. Fixup routine uses ScopeDesc info 3552 // to determine who we intended to call. 3553 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 3554 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); 3555 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3556 "Fix constant in ret_addr_offset()"); 3557 } else { 3558 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 3559 // Go thru the vtable. Get receiver klass. Receiver already 3560 // checked for non-null. If we'll go thru a C2I adapter, the 3561 // interpreter expects method in R19_method. 3562 3563 __ load_klass(R11_scratch1, R3); 3564 3565 int entry_offset = in_bytes(Klass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes(); 3566 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 3567 __ li(R19_method, v_off); 3568 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); 3569 // NOTE: for vtable dispatches, the vtable entry will never be 3570 // null. However it may very well end up in handle_wrong_method 3571 // if the method is abstract for the particular class. 3572 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); 3573 // Call target. Either compiled code or C2I adapter. 3574 __ mtctr(R11_scratch1); 3575 __ bctrl(); 3576 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { 3577 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); 3578 } 3579 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3580 "Fix constant in ret_addr_offset()"); 3581 } 3582 #endif 3583 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). 3584 %} 3585 3586 // a runtime call 3587 enc_class enc_java_to_runtime_call (method meth) %{ 3588 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3589 3590 MacroAssembler _masm(&cbuf); 3591 const address start_pc = __ pc(); 3592 3593 #if defined(ABI_ELFv2) 3594 address entry= !($meth$$method) ? NULL : (address)$meth$$method; 3595 __ call_c(entry, relocInfo::runtime_call_type); 3596 #else 3597 // The function we're going to call. 3598 FunctionDescriptor fdtemp; 3599 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; 3600 3601 Register Rtoc = R12_scratch2; 3602 // Calculate the method's TOC. 3603 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); 3604 // Put entry, env, toc into the constant pool, this needs up to 3 constant 3605 // pool entries; call_c_using_toc will optimize the call. 3606 bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); 3607 if (!success) { 3608 ciEnv::current()->record_out_of_memory_failure(); 3609 return; 3610 } 3611 #endif 3612 3613 // Check the ret_addr_offset. 3614 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, 3615 "Fix constant in ret_addr_offset()"); 3616 %} 3617 3618 // Move to ctr for leaf call. 3619 // This enc_class is needed so that scheduler gets proper 3620 // input mapping for latency computation. 3621 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ 3622 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); 3623 MacroAssembler _masm(&cbuf); 3624 __ mtctr($src$$Register); 3625 %} 3626 3627 // Postalloc expand emitter for runtime leaf calls. 3628 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ 3629 loadConLNodesTuple loadConLNodes_Entry; 3630 #if defined(ABI_ELFv2) 3631 jlong entry_address = (jlong) this->entry_point(); 3632 assert(entry_address, "need address here"); 3633 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3634 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3635 #else 3636 // Get the struct that describes the function we are about to call. 3637 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); 3638 assert(fd, "need fd here"); 3639 jlong entry_address = (jlong) fd->entry(); 3640 // new nodes 3641 loadConLNodesTuple loadConLNodes_Env; 3642 loadConLNodesTuple loadConLNodes_Toc; 3643 3644 // Create nodes and operands for loading the entry point. 3645 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3646 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3647 3648 3649 // Create nodes and operands for loading the env pointer. 3650 if (fd->env() != NULL) { 3651 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()), 3652 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3653 } else { 3654 loadConLNodes_Env._large_hi = NULL; 3655 loadConLNodes_Env._large_lo = NULL; 3656 loadConLNodes_Env._small = NULL; 3657 loadConLNodes_Env._last = new loadConL16Node(); 3658 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper(); 3659 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0); 3660 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3661 } 3662 3663 // Create nodes and operands for loading the Toc point. 3664 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()), 3665 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); 3666 #endif // ABI_ELFv2 3667 // mtctr node 3668 MachNode *mtctr = new CallLeafDirect_mtctrNode(); 3669 3670 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); 3671 mtctr->add_req(0, loadConLNodes_Entry._last); 3672 3673 mtctr->_opnds[0] = new iRegLdstOper(); 3674 mtctr->_opnds[1] = new iRegLdstOper(); 3675 3676 // call node 3677 MachCallLeafNode *call = new CallLeafDirectNode(); 3678 3679 call->_opnds[0] = _opnds[0]; 3680 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later. 3681 3682 // Make the new call node look like the old one. 3683 call->_name = _name; 3684 call->_tf = _tf; 3685 call->_entry_point = _entry_point; 3686 call->_cnt = _cnt; 3687 call->_argsize = _argsize; 3688 call->_oop_map = _oop_map; 3689 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); 3690 call->_jvms = NULL; 3691 call->_jvmadj = _jvmadj; 3692 call->_in_rms = _in_rms; 3693 call->_nesting = _nesting; 3694 3695 3696 // New call needs all inputs of old call. 3697 // Req... 3698 for (uint i = 0; i < req(); ++i) { 3699 if (i != mach_constant_base_node_input()) { 3700 call->add_req(in(i)); 3701 } 3702 } 3703 3704 // These must be reqired edges, as the registers are live up to 3705 // the call. Else the constants are handled as kills. 3706 call->add_req(mtctr); 3707 #if !defined(ABI_ELFv2) 3708 call->add_req(loadConLNodes_Env._last); 3709 call->add_req(loadConLNodes_Toc._last); 3710 #endif 3711 3712 // ...as well as prec 3713 for (uint i = req(); i < len(); ++i) { 3714 call->add_prec(in(i)); 3715 } 3716 3717 // registers 3718 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); 3719 3720 // Insert the new nodes. 3721 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); 3722 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); 3723 #if !defined(ABI_ELFv2) 3724 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); 3725 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); 3726 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); 3727 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); 3728 #endif 3729 nodes->push(mtctr); 3730 nodes->push(call); 3731 %} 3732 %} 3733 3734 //----------FRAME-------------------------------------------------------------- 3735 // Definition of frame structure and management information. 3736 3737 frame %{ 3738 // What direction does stack grow in (assumed to be same for native & Java). 3739 stack_direction(TOWARDS_LOW); 3740 3741 // These two registers define part of the calling convention between 3742 // compiled code and the interpreter. 3743 3744 // Inline Cache Register or method for I2C. 3745 inline_cache_reg(R19); // R19_method 3746 3747 // Method Oop Register when calling interpreter. 3748 interpreter_method_oop_reg(R19); // R19_method 3749 3750 // Optional: name the operand used by cisc-spilling to access 3751 // [stack_pointer + offset]. 3752 cisc_spilling_operand_name(indOffset); 3753 3754 // Number of stack slots consumed by a Monitor enter. 3755 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); 3756 3757 // Compiled code's Frame Pointer. 3758 frame_pointer(R1); // R1_SP 3759 3760 // Interpreter stores its frame pointer in a register which is 3761 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 3762 // interpreted java to compiled java. 3763 // 3764 // R14_state holds pointer to caller's cInterpreter. 3765 interpreter_frame_pointer(R14); // R14_state 3766 3767 stack_alignment(frame::alignment_in_bytes); 3768 3769 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); 3770 3771 // Number of outgoing stack slots killed above the 3772 // out_preserve_stack_slots for calls to C. Supports the var-args 3773 // backing area for register parms. 3774 // 3775 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 3776 3777 // The after-PROLOG location of the return address. Location of 3778 // return address specifies a type (REG or STACK) and a number 3779 // representing the register number (i.e. - use a register name) or 3780 // stack slot. 3781 // 3782 // A: Link register is stored in stack slot ... 3783 // M: ... but it's in the caller's frame according to PPC-64 ABI. 3784 // J: Therefore, we make sure that the link register is also in R11_scratch1 3785 // at the end of the prolog. 3786 // B: We use R20, now. 3787 //return_addr(REG R20); 3788 3789 // G: After reading the comments made by all the luminaries on their 3790 // failure to tell the compiler where the return address really is, 3791 // I hardly dare to try myself. However, I'm convinced it's in slot 3792 // 4 what apparently works and saves us some spills. 3793 return_addr(STACK 4); 3794 3795 // This is the body of the function 3796 // 3797 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs 3798 // uint length, // length of array 3799 // bool is_outgoing) 3800 // 3801 // The `sig' array is to be updated. sig[j] represents the location 3802 // of the j-th argument, either a register or a stack slot. 3803 3804 // Comment taken from i486.ad: 3805 // Body of function which returns an integer array locating 3806 // arguments either in registers or in stack slots. Passed an array 3807 // of ideal registers called "sig" and a "length" count. Stack-slot 3808 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3809 // arguments for a CALLEE. Incoming stack arguments are 3810 // automatically biased by the preserve_stack_slots field above. 3811 calling_convention %{ 3812 // No difference between ingoing/outgoing. Just pass false. 3813 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3814 %} 3815 3816 // Comment taken from i486.ad: 3817 // Body of function which returns an integer array locating 3818 // arguments either in registers or in stack slots. Passed an array 3819 // of ideal registers called "sig" and a "length" count. Stack-slot 3820 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3821 // arguments for a CALLEE. Incoming stack arguments are 3822 // automatically biased by the preserve_stack_slots field above. 3823 c_calling_convention %{ 3824 // This is obviously always outgoing. 3825 // C argument in register AND stack slot. 3826 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3827 %} 3828 3829 // Location of native (C/C++) and interpreter return values. This 3830 // is specified to be the same as Java. In the 32-bit VM, long 3831 // values are actually returned from native calls in O0:O1 and 3832 // returned to the interpreter in I0:I1. The copying to and from 3833 // the register pairs is done by the appropriate call and epilog 3834 // opcodes. This simplifies the register allocator. 3835 c_return_value %{ 3836 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3837 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3838 "only return normal values"); 3839 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3840 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3841 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3842 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3843 %} 3844 3845 // Location of compiled Java return values. Same as C 3846 return_value %{ 3847 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3848 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3849 "only return normal values"); 3850 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3851 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3852 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3853 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3854 %} 3855 %} 3856 3857 3858 //----------ATTRIBUTES--------------------------------------------------------- 3859 3860 //----------Operand Attributes------------------------------------------------- 3861 op_attrib op_cost(1); // Required cost attribute. 3862 3863 //----------Instruction Attributes--------------------------------------------- 3864 3865 // Cost attribute. required. 3866 ins_attrib ins_cost(DEFAULT_COST); 3867 3868 // Is this instruction a non-matching short branch variant of some 3869 // long branch? Not required. 3870 ins_attrib ins_short_branch(0); 3871 3872 ins_attrib ins_is_TrapBasedCheckNode(true); 3873 3874 // Number of constants. 3875 // This instruction uses the given number of constants 3876 // (optional attribute). 3877 // This is needed to determine in time whether the constant pool will 3878 // exceed 4000 entries. Before postalloc_expand the overall number of constants 3879 // is determined. It's also used to compute the constant pool size 3880 // in Output(). 3881 ins_attrib ins_num_consts(0); 3882 3883 // Required alignment attribute (must be a power of 2) specifies the 3884 // alignment that some part of the instruction (not necessarily the 3885 // start) requires. If > 1, a compute_padding() function must be 3886 // provided for the instruction. 3887 ins_attrib ins_alignment(1); 3888 3889 // Enforce/prohibit rematerializations. 3890 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 3891 // then rematerialization of that instruction is prohibited and the 3892 // instruction's value will be spilled if necessary. 3893 // Causes that MachNode::rematerialize() returns false. 3894 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 3895 // then rematerialization should be enforced and a copy of the instruction 3896 // should be inserted if possible; rematerialization is not guaranteed. 3897 // Note: this may result in rematerializations in front of every use. 3898 // Causes that MachNode::rematerialize() can return true. 3899 // (optional attribute) 3900 ins_attrib ins_cannot_rematerialize(false); 3901 ins_attrib ins_should_rematerialize(false); 3902 3903 // Instruction has variable size depending on alignment. 3904 ins_attrib ins_variable_size_depending_on_alignment(false); 3905 3906 // Instruction is a nop. 3907 ins_attrib ins_is_nop(false); 3908 3909 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). 3910 ins_attrib ins_use_mach_if_fast_lock_node(false); 3911 3912 // Field for the toc offset of a constant. 3913 // 3914 // This is needed if the toc offset is not encodable as an immediate in 3915 // the PPC load instruction. If so, the upper (hi) bits of the offset are 3916 // added to the toc, and from this a load with immediate is performed. 3917 // With postalloc expand, we get two nodes that require the same offset 3918 // but which don't know about each other. The offset is only known 3919 // when the constant is added to the constant pool during emitting. 3920 // It is generated in the 'hi'-node adding the upper bits, and saved 3921 // in this node. The 'lo'-node has a link to the 'hi'-node and reads 3922 // the offset from there when it gets encoded. 3923 ins_attrib ins_field_const_toc_offset(0); 3924 ins_attrib ins_field_const_toc_offset_hi_node(0); 3925 3926 // A field that can hold the instructions offset in the code buffer. 3927 // Set in the nodes emitter. 3928 ins_attrib ins_field_cbuf_insts_offset(-1); 3929 3930 // Fields for referencing a call's load-IC-node. 3931 // If the toc offset can not be encoded as an immediate in a load, we 3932 // use two nodes. 3933 ins_attrib ins_field_load_ic_hi_node(0); 3934 ins_attrib ins_field_load_ic_node(0); 3935 3936 //----------OPERANDS----------------------------------------------------------- 3937 // Operand definitions must precede instruction definitions for correct 3938 // parsing in the ADLC because operands constitute user defined types 3939 // which are used in instruction definitions. 3940 // 3941 // Formats are generated automatically for constants and base registers. 3942 3943 //----------Simple Operands---------------------------------------------------- 3944 // Immediate Operands 3945 3946 // Integer Immediate: 32-bit 3947 operand immI() %{ 3948 match(ConI); 3949 op_cost(40); 3950 format %{ %} 3951 interface(CONST_INTER); 3952 %} 3953 3954 operand immI8() %{ 3955 predicate(Assembler::is_simm(n->get_int(), 8)); 3956 op_cost(0); 3957 match(ConI); 3958 format %{ %} 3959 interface(CONST_INTER); 3960 %} 3961 3962 // Integer Immediate: 16-bit 3963 operand immI16() %{ 3964 predicate(Assembler::is_simm(n->get_int(), 16)); 3965 op_cost(0); 3966 match(ConI); 3967 format %{ %} 3968 interface(CONST_INTER); 3969 %} 3970 3971 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. 3972 operand immIhi16() %{ 3973 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); 3974 match(ConI); 3975 op_cost(0); 3976 format %{ %} 3977 interface(CONST_INTER); 3978 %} 3979 3980 operand immInegpow2() %{ 3981 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); 3982 match(ConI); 3983 op_cost(0); 3984 format %{ %} 3985 interface(CONST_INTER); 3986 %} 3987 3988 operand immIpow2minus1() %{ 3989 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); 3990 match(ConI); 3991 op_cost(0); 3992 format %{ %} 3993 interface(CONST_INTER); 3994 %} 3995 3996 operand immIpowerOf2() %{ 3997 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); 3998 match(ConI); 3999 op_cost(0); 4000 format %{ %} 4001 interface(CONST_INTER); 4002 %} 4003 4004 // Unsigned Integer Immediate: the values 0-31 4005 operand uimmI5() %{ 4006 predicate(Assembler::is_uimm(n->get_int(), 5)); 4007 match(ConI); 4008 op_cost(0); 4009 format %{ %} 4010 interface(CONST_INTER); 4011 %} 4012 4013 // Unsigned Integer Immediate: 6-bit 4014 operand uimmI6() %{ 4015 predicate(Assembler::is_uimm(n->get_int(), 6)); 4016 match(ConI); 4017 op_cost(0); 4018 format %{ %} 4019 interface(CONST_INTER); 4020 %} 4021 4022 // Unsigned Integer Immediate: 6-bit int, greater than 32 4023 operand uimmI6_ge32() %{ 4024 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); 4025 match(ConI); 4026 op_cost(0); 4027 format %{ %} 4028 interface(CONST_INTER); 4029 %} 4030 4031 // Unsigned Integer Immediate: 15-bit 4032 operand uimmI15() %{ 4033 predicate(Assembler::is_uimm(n->get_int(), 15)); 4034 match(ConI); 4035 op_cost(0); 4036 format %{ %} 4037 interface(CONST_INTER); 4038 %} 4039 4040 // Unsigned Integer Immediate: 16-bit 4041 operand uimmI16() %{ 4042 predicate(Assembler::is_uimm(n->get_int(), 16)); 4043 match(ConI); 4044 op_cost(0); 4045 format %{ %} 4046 interface(CONST_INTER); 4047 %} 4048 4049 // constant 'int 0'. 4050 operand immI_0() %{ 4051 predicate(n->get_int() == 0); 4052 match(ConI); 4053 op_cost(0); 4054 format %{ %} 4055 interface(CONST_INTER); 4056 %} 4057 4058 // constant 'int 1'. 4059 operand immI_1() %{ 4060 predicate(n->get_int() == 1); 4061 match(ConI); 4062 op_cost(0); 4063 format %{ %} 4064 interface(CONST_INTER); 4065 %} 4066 4067 // constant 'int -1'. 4068 operand immI_minus1() %{ 4069 predicate(n->get_int() == -1); 4070 match(ConI); 4071 op_cost(0); 4072 format %{ %} 4073 interface(CONST_INTER); 4074 %} 4075 4076 // int value 16. 4077 operand immI_16() %{ 4078 predicate(n->get_int() == 16); 4079 match(ConI); 4080 op_cost(0); 4081 format %{ %} 4082 interface(CONST_INTER); 4083 %} 4084 4085 // int value 24. 4086 operand immI_24() %{ 4087 predicate(n->get_int() == 24); 4088 match(ConI); 4089 op_cost(0); 4090 format %{ %} 4091 interface(CONST_INTER); 4092 %} 4093 4094 // Compressed oops constants 4095 // Pointer Immediate 4096 operand immN() %{ 4097 match(ConN); 4098 4099 op_cost(10); 4100 format %{ %} 4101 interface(CONST_INTER); 4102 %} 4103 4104 // NULL Pointer Immediate 4105 operand immN_0() %{ 4106 predicate(n->get_narrowcon() == 0); 4107 match(ConN); 4108 4109 op_cost(0); 4110 format %{ %} 4111 interface(CONST_INTER); 4112 %} 4113 4114 // Compressed klass constants 4115 operand immNKlass() %{ 4116 match(ConNKlass); 4117 4118 op_cost(0); 4119 format %{ %} 4120 interface(CONST_INTER); 4121 %} 4122 4123 // This operand can be used to avoid matching of an instruct 4124 // with chain rule. 4125 operand immNKlass_NM() %{ 4126 match(ConNKlass); 4127 predicate(false); 4128 op_cost(0); 4129 format %{ %} 4130 interface(CONST_INTER); 4131 %} 4132 4133 // Pointer Immediate: 64-bit 4134 operand immP() %{ 4135 match(ConP); 4136 op_cost(0); 4137 format %{ %} 4138 interface(CONST_INTER); 4139 %} 4140 4141 // Operand to avoid match of loadConP. 4142 // This operand can be used to avoid matching of an instruct 4143 // with chain rule. 4144 operand immP_NM() %{ 4145 match(ConP); 4146 predicate(false); 4147 op_cost(0); 4148 format %{ %} 4149 interface(CONST_INTER); 4150 %} 4151 4152 // costant 'pointer 0'. 4153 operand immP_0() %{ 4154 predicate(n->get_ptr() == 0); 4155 match(ConP); 4156 op_cost(0); 4157 format %{ %} 4158 interface(CONST_INTER); 4159 %} 4160 4161 // pointer 0x0 or 0x1 4162 operand immP_0or1() %{ 4163 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); 4164 match(ConP); 4165 op_cost(0); 4166 format %{ %} 4167 interface(CONST_INTER); 4168 %} 4169 4170 operand immL() %{ 4171 match(ConL); 4172 op_cost(40); 4173 format %{ %} 4174 interface(CONST_INTER); 4175 %} 4176 4177 // Long Immediate: 16-bit 4178 operand immL16() %{ 4179 predicate(Assembler::is_simm(n->get_long(), 16)); 4180 match(ConL); 4181 op_cost(0); 4182 format %{ %} 4183 interface(CONST_INTER); 4184 %} 4185 4186 // Long Immediate: 16-bit, 4-aligned 4187 operand immL16Alg4() %{ 4188 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); 4189 match(ConL); 4190 op_cost(0); 4191 format %{ %} 4192 interface(CONST_INTER); 4193 %} 4194 4195 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000. 4196 operand immL32hi16() %{ 4197 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); 4198 match(ConL); 4199 op_cost(0); 4200 format %{ %} 4201 interface(CONST_INTER); 4202 %} 4203 4204 // Long Immediate: 32-bit 4205 operand immL32() %{ 4206 predicate(Assembler::is_simm(n->get_long(), 32)); 4207 match(ConL); 4208 op_cost(0); 4209 format %{ %} 4210 interface(CONST_INTER); 4211 %} 4212 4213 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000. 4214 operand immLhighest16() %{ 4215 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); 4216 match(ConL); 4217 op_cost(0); 4218 format %{ %} 4219 interface(CONST_INTER); 4220 %} 4221 4222 operand immLnegpow2() %{ 4223 predicate(is_power_of_2_long((jlong)-(n->get_long()))); 4224 match(ConL); 4225 op_cost(0); 4226 format %{ %} 4227 interface(CONST_INTER); 4228 %} 4229 4230 operand immLpow2minus1() %{ 4231 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && 4232 (n->get_long() != (jlong)0xffffffffffffffffL)); 4233 match(ConL); 4234 op_cost(0); 4235 format %{ %} 4236 interface(CONST_INTER); 4237 %} 4238 4239 // constant 'long 0'. 4240 operand immL_0() %{ 4241 predicate(n->get_long() == 0L); 4242 match(ConL); 4243 op_cost(0); 4244 format %{ %} 4245 interface(CONST_INTER); 4246 %} 4247 4248 // constat ' long -1'. 4249 operand immL_minus1() %{ 4250 predicate(n->get_long() == -1L); 4251 match(ConL); 4252 op_cost(0); 4253 format %{ %} 4254 interface(CONST_INTER); 4255 %} 4256 4257 // Long Immediate: low 32-bit mask 4258 operand immL_32bits() %{ 4259 predicate(n->get_long() == 0xFFFFFFFFL); 4260 match(ConL); 4261 op_cost(0); 4262 format %{ %} 4263 interface(CONST_INTER); 4264 %} 4265 4266 // Unsigned Long Immediate: 16-bit 4267 operand uimmL16() %{ 4268 predicate(Assembler::is_uimm(n->get_long(), 16)); 4269 match(ConL); 4270 op_cost(0); 4271 format %{ %} 4272 interface(CONST_INTER); 4273 %} 4274 4275 // Float Immediate 4276 operand immF() %{ 4277 match(ConF); 4278 op_cost(40); 4279 format %{ %} 4280 interface(CONST_INTER); 4281 %} 4282 4283 // Float Immediate: +0.0f. 4284 operand immF_0() %{ 4285 predicate(jint_cast(n->getf()) == 0); 4286 match(ConF); 4287 4288 op_cost(0); 4289 format %{ %} 4290 interface(CONST_INTER); 4291 %} 4292 4293 // Double Immediate 4294 operand immD() %{ 4295 match(ConD); 4296 op_cost(40); 4297 format %{ %} 4298 interface(CONST_INTER); 4299 %} 4300 4301 // Integer Register Operands 4302 // Integer Destination Register 4303 // See definition of reg_class bits32_reg_rw. 4304 operand iRegIdst() %{ 4305 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4306 match(RegI); 4307 match(rscratch1RegI); 4308 match(rscratch2RegI); 4309 match(rarg1RegI); 4310 match(rarg2RegI); 4311 match(rarg3RegI); 4312 match(rarg4RegI); 4313 format %{ %} 4314 interface(REG_INTER); 4315 %} 4316 4317 // Integer Source Register 4318 // See definition of reg_class bits32_reg_ro. 4319 operand iRegIsrc() %{ 4320 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4321 match(RegI); 4322 match(rscratch1RegI); 4323 match(rscratch2RegI); 4324 match(rarg1RegI); 4325 match(rarg2RegI); 4326 match(rarg3RegI); 4327 match(rarg4RegI); 4328 format %{ %} 4329 interface(REG_INTER); 4330 %} 4331 4332 operand rscratch1RegI() %{ 4333 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); 4334 match(iRegIdst); 4335 format %{ %} 4336 interface(REG_INTER); 4337 %} 4338 4339 operand rscratch2RegI() %{ 4340 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); 4341 match(iRegIdst); 4342 format %{ %} 4343 interface(REG_INTER); 4344 %} 4345 4346 operand rarg1RegI() %{ 4347 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); 4348 match(iRegIdst); 4349 format %{ %} 4350 interface(REG_INTER); 4351 %} 4352 4353 operand rarg2RegI() %{ 4354 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); 4355 match(iRegIdst); 4356 format %{ %} 4357 interface(REG_INTER); 4358 %} 4359 4360 operand rarg3RegI() %{ 4361 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); 4362 match(iRegIdst); 4363 format %{ %} 4364 interface(REG_INTER); 4365 %} 4366 4367 operand rarg4RegI() %{ 4368 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); 4369 match(iRegIdst); 4370 format %{ %} 4371 interface(REG_INTER); 4372 %} 4373 4374 operand rarg1RegL() %{ 4375 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4376 match(iRegLdst); 4377 format %{ %} 4378 interface(REG_INTER); 4379 %} 4380 4381 operand rarg2RegL() %{ 4382 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4383 match(iRegLdst); 4384 format %{ %} 4385 interface(REG_INTER); 4386 %} 4387 4388 operand rarg3RegL() %{ 4389 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4390 match(iRegLdst); 4391 format %{ %} 4392 interface(REG_INTER); 4393 %} 4394 4395 operand rarg4RegL() %{ 4396 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4397 match(iRegLdst); 4398 format %{ %} 4399 interface(REG_INTER); 4400 %} 4401 4402 // Pointer Destination Register 4403 // See definition of reg_class bits64_reg_rw. 4404 operand iRegPdst() %{ 4405 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4406 match(RegP); 4407 match(rscratch1RegP); 4408 match(rscratch2RegP); 4409 match(rarg1RegP); 4410 match(rarg2RegP); 4411 match(rarg3RegP); 4412 match(rarg4RegP); 4413 format %{ %} 4414 interface(REG_INTER); 4415 %} 4416 4417 // Pointer Destination Register 4418 // Operand not using r11 and r12 (killed in epilog). 4419 operand iRegPdstNoScratch() %{ 4420 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); 4421 match(RegP); 4422 match(rarg1RegP); 4423 match(rarg2RegP); 4424 match(rarg3RegP); 4425 match(rarg4RegP); 4426 format %{ %} 4427 interface(REG_INTER); 4428 %} 4429 4430 // Pointer Source Register 4431 // See definition of reg_class bits64_reg_ro. 4432 operand iRegPsrc() %{ 4433 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4434 match(RegP); 4435 match(iRegPdst); 4436 match(rscratch1RegP); 4437 match(rscratch2RegP); 4438 match(rarg1RegP); 4439 match(rarg2RegP); 4440 match(rarg3RegP); 4441 match(rarg4RegP); 4442 match(threadRegP); 4443 format %{ %} 4444 interface(REG_INTER); 4445 %} 4446 4447 // Thread operand. 4448 operand threadRegP() %{ 4449 constraint(ALLOC_IN_RC(thread_bits64_reg)); 4450 match(iRegPdst); 4451 format %{ "R16" %} 4452 interface(REG_INTER); 4453 %} 4454 4455 operand rscratch1RegP() %{ 4456 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4457 match(iRegPdst); 4458 format %{ "R11" %} 4459 interface(REG_INTER); 4460 %} 4461 4462 operand rscratch2RegP() %{ 4463 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4464 match(iRegPdst); 4465 format %{ %} 4466 interface(REG_INTER); 4467 %} 4468 4469 operand rarg1RegP() %{ 4470 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4471 match(iRegPdst); 4472 format %{ %} 4473 interface(REG_INTER); 4474 %} 4475 4476 operand rarg2RegP() %{ 4477 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4478 match(iRegPdst); 4479 format %{ %} 4480 interface(REG_INTER); 4481 %} 4482 4483 operand rarg3RegP() %{ 4484 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4485 match(iRegPdst); 4486 format %{ %} 4487 interface(REG_INTER); 4488 %} 4489 4490 operand rarg4RegP() %{ 4491 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4492 match(iRegPdst); 4493 format %{ %} 4494 interface(REG_INTER); 4495 %} 4496 4497 operand iRegNsrc() %{ 4498 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4499 match(RegN); 4500 match(iRegNdst); 4501 4502 format %{ %} 4503 interface(REG_INTER); 4504 %} 4505 4506 operand iRegNdst() %{ 4507 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4508 match(RegN); 4509 4510 format %{ %} 4511 interface(REG_INTER); 4512 %} 4513 4514 // Long Destination Register 4515 // See definition of reg_class bits64_reg_rw. 4516 operand iRegLdst() %{ 4517 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4518 match(RegL); 4519 match(rscratch1RegL); 4520 match(rscratch2RegL); 4521 format %{ %} 4522 interface(REG_INTER); 4523 %} 4524 4525 // Long Source Register 4526 // See definition of reg_class bits64_reg_ro. 4527 operand iRegLsrc() %{ 4528 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4529 match(RegL); 4530 match(iRegLdst); 4531 match(rscratch1RegL); 4532 match(rscratch2RegL); 4533 format %{ %} 4534 interface(REG_INTER); 4535 %} 4536 4537 // Special operand for ConvL2I. 4538 operand iRegL2Isrc(iRegLsrc reg) %{ 4539 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4540 match(ConvL2I reg); 4541 format %{ "ConvL2I($reg)" %} 4542 interface(REG_INTER) 4543 %} 4544 4545 operand rscratch1RegL() %{ 4546 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4547 match(RegL); 4548 format %{ %} 4549 interface(REG_INTER); 4550 %} 4551 4552 operand rscratch2RegL() %{ 4553 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4554 match(RegL); 4555 format %{ %} 4556 interface(REG_INTER); 4557 %} 4558 4559 // Condition Code Flag Registers 4560 operand flagsReg() %{ 4561 constraint(ALLOC_IN_RC(int_flags)); 4562 match(RegFlags); 4563 format %{ %} 4564 interface(REG_INTER); 4565 %} 4566 4567 operand flagsRegSrc() %{ 4568 constraint(ALLOC_IN_RC(int_flags_ro)); 4569 match(RegFlags); 4570 match(flagsReg); 4571 match(flagsRegCR0); 4572 format %{ %} 4573 interface(REG_INTER); 4574 %} 4575 4576 // Condition Code Flag Register CR0 4577 operand flagsRegCR0() %{ 4578 constraint(ALLOC_IN_RC(int_flags_CR0)); 4579 match(RegFlags); 4580 format %{ "CR0" %} 4581 interface(REG_INTER); 4582 %} 4583 4584 operand flagsRegCR1() %{ 4585 constraint(ALLOC_IN_RC(int_flags_CR1)); 4586 match(RegFlags); 4587 format %{ "CR1" %} 4588 interface(REG_INTER); 4589 %} 4590 4591 operand flagsRegCR6() %{ 4592 constraint(ALLOC_IN_RC(int_flags_CR6)); 4593 match(RegFlags); 4594 format %{ "CR6" %} 4595 interface(REG_INTER); 4596 %} 4597 4598 operand regCTR() %{ 4599 constraint(ALLOC_IN_RC(ctr_reg)); 4600 // RegFlags should work. Introducing a RegSpecial type would cause a 4601 // lot of changes. 4602 match(RegFlags); 4603 format %{"SR_CTR" %} 4604 interface(REG_INTER); 4605 %} 4606 4607 operand regD() %{ 4608 constraint(ALLOC_IN_RC(dbl_reg)); 4609 match(RegD); 4610 format %{ %} 4611 interface(REG_INTER); 4612 %} 4613 4614 operand regF() %{ 4615 constraint(ALLOC_IN_RC(flt_reg)); 4616 match(RegF); 4617 format %{ %} 4618 interface(REG_INTER); 4619 %} 4620 4621 // Special Registers 4622 4623 // Method Register 4624 operand inline_cache_regP(iRegPdst reg) %{ 4625 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg 4626 match(reg); 4627 format %{ %} 4628 interface(REG_INTER); 4629 %} 4630 4631 operand compiler_method_oop_regP(iRegPdst reg) %{ 4632 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg 4633 match(reg); 4634 format %{ %} 4635 interface(REG_INTER); 4636 %} 4637 4638 operand interpreter_method_oop_regP(iRegPdst reg) %{ 4639 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg 4640 match(reg); 4641 format %{ %} 4642 interface(REG_INTER); 4643 %} 4644 4645 // Operands to remove register moves in unscaled mode. 4646 // Match read/write registers with an EncodeP node if neither shift nor add are required. 4647 operand iRegP2N(iRegPsrc reg) %{ 4648 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); 4649 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4650 match(EncodeP reg); 4651 format %{ "$reg" %} 4652 interface(REG_INTER) 4653 %} 4654 4655 operand iRegN2P(iRegNsrc reg) %{ 4656 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4657 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4658 match(DecodeN reg); 4659 format %{ "$reg" %} 4660 interface(REG_INTER) 4661 %} 4662 4663 operand iRegN2P_klass(iRegNsrc reg) %{ 4664 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4665 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4666 match(DecodeNKlass reg); 4667 format %{ "$reg" %} 4668 interface(REG_INTER) 4669 %} 4670 4671 //----------Complex Operands--------------------------------------------------- 4672 // Indirect Memory Reference 4673 operand indirect(iRegPsrc reg) %{ 4674 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4675 match(reg); 4676 op_cost(100); 4677 format %{ "[$reg]" %} 4678 interface(MEMORY_INTER) %{ 4679 base($reg); 4680 index(0x0); 4681 scale(0x0); 4682 disp(0x0); 4683 %} 4684 %} 4685 4686 // Indirect with Offset 4687 operand indOffset16(iRegPsrc reg, immL16 offset) %{ 4688 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4689 match(AddP reg offset); 4690 op_cost(100); 4691 format %{ "[$reg + $offset]" %} 4692 interface(MEMORY_INTER) %{ 4693 base($reg); 4694 index(0x0); 4695 scale(0x0); 4696 disp($offset); 4697 %} 4698 %} 4699 4700 // Indirect with 4-aligned Offset 4701 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ 4702 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4703 match(AddP reg offset); 4704 op_cost(100); 4705 format %{ "[$reg + $offset]" %} 4706 interface(MEMORY_INTER) %{ 4707 base($reg); 4708 index(0x0); 4709 scale(0x0); 4710 disp($offset); 4711 %} 4712 %} 4713 4714 //----------Complex Operands for Compressed OOPs------------------------------- 4715 // Compressed OOPs with narrow_oop_shift == 0. 4716 4717 // Indirect Memory Reference, compressed OOP 4718 operand indirectNarrow(iRegNsrc reg) %{ 4719 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4720 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4721 match(DecodeN reg); 4722 op_cost(100); 4723 format %{ "[$reg]" %} 4724 interface(MEMORY_INTER) %{ 4725 base($reg); 4726 index(0x0); 4727 scale(0x0); 4728 disp(0x0); 4729 %} 4730 %} 4731 4732 operand indirectNarrow_klass(iRegNsrc reg) %{ 4733 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4734 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4735 match(DecodeNKlass reg); 4736 op_cost(100); 4737 format %{ "[$reg]" %} 4738 interface(MEMORY_INTER) %{ 4739 base($reg); 4740 index(0x0); 4741 scale(0x0); 4742 disp(0x0); 4743 %} 4744 %} 4745 4746 // Indirect with Offset, compressed OOP 4747 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ 4748 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4749 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4750 match(AddP (DecodeN reg) offset); 4751 op_cost(100); 4752 format %{ "[$reg + $offset]" %} 4753 interface(MEMORY_INTER) %{ 4754 base($reg); 4755 index(0x0); 4756 scale(0x0); 4757 disp($offset); 4758 %} 4759 %} 4760 4761 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{ 4762 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4763 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4764 match(AddP (DecodeNKlass reg) offset); 4765 op_cost(100); 4766 format %{ "[$reg + $offset]" %} 4767 interface(MEMORY_INTER) %{ 4768 base($reg); 4769 index(0x0); 4770 scale(0x0); 4771 disp($offset); 4772 %} 4773 %} 4774 4775 // Indirect with 4-aligned Offset, compressed OOP 4776 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ 4777 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4778 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4779 match(AddP (DecodeN reg) offset); 4780 op_cost(100); 4781 format %{ "[$reg + $offset]" %} 4782 interface(MEMORY_INTER) %{ 4783 base($reg); 4784 index(0x0); 4785 scale(0x0); 4786 disp($offset); 4787 %} 4788 %} 4789 4790 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{ 4791 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4792 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4793 match(AddP (DecodeNKlass reg) offset); 4794 op_cost(100); 4795 format %{ "[$reg + $offset]" %} 4796 interface(MEMORY_INTER) %{ 4797 base($reg); 4798 index(0x0); 4799 scale(0x0); 4800 disp($offset); 4801 %} 4802 %} 4803 4804 //----------Special Memory Operands-------------------------------------------- 4805 // Stack Slot Operand 4806 // 4807 // This operand is used for loading and storing temporary values on 4808 // the stack where a match requires a value to flow through memory. 4809 operand stackSlotI(sRegI reg) %{ 4810 constraint(ALLOC_IN_RC(stack_slots)); 4811 op_cost(100); 4812 //match(RegI); 4813 format %{ "[sp+$reg]" %} 4814 interface(MEMORY_INTER) %{ 4815 base(0x1); // R1_SP 4816 index(0x0); 4817 scale(0x0); 4818 disp($reg); // Stack Offset 4819 %} 4820 %} 4821 4822 operand stackSlotL(sRegL reg) %{ 4823 constraint(ALLOC_IN_RC(stack_slots)); 4824 op_cost(100); 4825 //match(RegL); 4826 format %{ "[sp+$reg]" %} 4827 interface(MEMORY_INTER) %{ 4828 base(0x1); // R1_SP 4829 index(0x0); 4830 scale(0x0); 4831 disp($reg); // Stack Offset 4832 %} 4833 %} 4834 4835 operand stackSlotP(sRegP reg) %{ 4836 constraint(ALLOC_IN_RC(stack_slots)); 4837 op_cost(100); 4838 //match(RegP); 4839 format %{ "[sp+$reg]" %} 4840 interface(MEMORY_INTER) %{ 4841 base(0x1); // R1_SP 4842 index(0x0); 4843 scale(0x0); 4844 disp($reg); // Stack Offset 4845 %} 4846 %} 4847 4848 operand stackSlotF(sRegF reg) %{ 4849 constraint(ALLOC_IN_RC(stack_slots)); 4850 op_cost(100); 4851 //match(RegF); 4852 format %{ "[sp+$reg]" %} 4853 interface(MEMORY_INTER) %{ 4854 base(0x1); // R1_SP 4855 index(0x0); 4856 scale(0x0); 4857 disp($reg); // Stack Offset 4858 %} 4859 %} 4860 4861 operand stackSlotD(sRegD reg) %{ 4862 constraint(ALLOC_IN_RC(stack_slots)); 4863 op_cost(100); 4864 //match(RegD); 4865 format %{ "[sp+$reg]" %} 4866 interface(MEMORY_INTER) %{ 4867 base(0x1); // R1_SP 4868 index(0x0); 4869 scale(0x0); 4870 disp($reg); // Stack Offset 4871 %} 4872 %} 4873 4874 // Operands for expressing Control Flow 4875 // NOTE: Label is a predefined operand which should not be redefined in 4876 // the AD file. It is generically handled within the ADLC. 4877 4878 //----------Conditional Branch Operands---------------------------------------- 4879 // Comparison Op 4880 // 4881 // This is the operation of the comparison, and is limited to the 4882 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE 4883 // (!=). 4884 // 4885 // Other attributes of the comparison, such as unsignedness, are specified 4886 // by the comparison instruction that sets a condition code flags register. 4887 // That result is represented by a flags operand whose subtype is appropriate 4888 // to the unsignedness (etc.) of the comparison. 4889 // 4890 // Later, the instruction which matches both the Comparison Op (a Bool) and 4891 // the flags (produced by the Cmp) specifies the coding of the comparison op 4892 // by matching a specific subtype of Bool operand below. 4893 4894 // When used for floating point comparisons: unordered same as less. 4895 operand cmpOp() %{ 4896 match(Bool); 4897 format %{ "" %} 4898 interface(COND_INTER) %{ 4899 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. 4900 // BO & BI 4901 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal 4902 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal 4903 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less 4904 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less 4905 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater 4906 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater 4907 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow 4908 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow 4909 %} 4910 %} 4911 4912 //----------OPERAND CLASSES---------------------------------------------------- 4913 // Operand Classes are groups of operands that are used to simplify 4914 // instruction definitions by not requiring the AD writer to specify 4915 // seperate instructions for every form of operand when the 4916 // instruction accepts multiple operand types with the same basic 4917 // encoding and format. The classic case of this is memory operands. 4918 // Indirect is not included since its use is limited to Compare & Swap. 4919 4920 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass); 4921 // Memory operand where offsets are 4-aligned. Required for ld, std. 4922 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass); 4923 opclass indirectMemory(indirect, indirectNarrow); 4924 4925 // Special opclass for I and ConvL2I. 4926 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); 4927 4928 // Operand classes to match encode and decode. iRegN_P2N is only used 4929 // for storeN. I have never seen an encode node elsewhere. 4930 opclass iRegN_P2N(iRegNsrc, iRegP2N); 4931 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass); 4932 4933 //----------PIPELINE----------------------------------------------------------- 4934 4935 pipeline %{ 4936 4937 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM 4938 // J. Res. & Dev., No. 1, Jan. 2002. 4939 4940 //----------ATTRIBUTES--------------------------------------------------------- 4941 attributes %{ 4942 4943 // Power4 instructions are of fixed length. 4944 fixed_size_instructions; 4945 4946 // TODO: if `bundle' means number of instructions fetched 4947 // per cycle, this is 8. If `bundle' means Power4 `group', that is 4948 // max instructions issued per cycle, this is 5. 4949 max_instructions_per_bundle = 8; 4950 4951 // A Power4 instruction is 4 bytes long. 4952 instruction_unit_size = 4; 4953 4954 // The Power4 processor fetches 64 bytes... 4955 instruction_fetch_unit_size = 64; 4956 4957 // ...in one line 4958 instruction_fetch_units = 1 4959 4960 // Unused, list one so that array generated by adlc is not empty. 4961 // Aix compiler chokes if _nop_count = 0. 4962 nops(fxNop); 4963 %} 4964 4965 //----------RESOURCES---------------------------------------------------------- 4966 // Resources are the functional units available to the machine 4967 resources( 4968 PPC_BR, // branch unit 4969 PPC_CR, // condition unit 4970 PPC_FX1, // integer arithmetic unit 1 4971 PPC_FX2, // integer arithmetic unit 2 4972 PPC_LDST1, // load/store unit 1 4973 PPC_LDST2, // load/store unit 2 4974 PPC_FP1, // float arithmetic unit 1 4975 PPC_FP2, // float arithmetic unit 2 4976 PPC_LDST = PPC_LDST1 | PPC_LDST2, 4977 PPC_FX = PPC_FX1 | PPC_FX2, 4978 PPC_FP = PPC_FP1 | PPC_FP2 4979 ); 4980 4981 //----------PIPELINE DESCRIPTION----------------------------------------------- 4982 // Pipeline Description specifies the stages in the machine's pipeline 4983 pipe_desc( 4984 // Power4 longest pipeline path 4985 PPC_IF, // instruction fetch 4986 PPC_IC, 4987 //PPC_BP, // branch prediction 4988 PPC_D0, // decode 4989 PPC_D1, // decode 4990 PPC_D2, // decode 4991 PPC_D3, // decode 4992 PPC_Xfer1, 4993 PPC_GD, // group definition 4994 PPC_MP, // map 4995 PPC_ISS, // issue 4996 PPC_RF, // resource fetch 4997 PPC_EX1, // execute (all units) 4998 PPC_EX2, // execute (FP, LDST) 4999 PPC_EX3, // execute (FP, LDST) 5000 PPC_EX4, // execute (FP) 5001 PPC_EX5, // execute (FP) 5002 PPC_EX6, // execute (FP) 5003 PPC_WB, // write back 5004 PPC_Xfer2, 5005 PPC_CP 5006 ); 5007 5008 //----------PIPELINE CLASSES--------------------------------------------------- 5009 // Pipeline Classes describe the stages in which input and output are 5010 // referenced by the hardware pipeline. 5011 5012 // Simple pipeline classes. 5013 5014 // Default pipeline class. 5015 pipe_class pipe_class_default() %{ 5016 single_instruction; 5017 fixed_latency(2); 5018 %} 5019 5020 // Pipeline class for empty instructions. 5021 pipe_class pipe_class_empty() %{ 5022 single_instruction; 5023 fixed_latency(0); 5024 %} 5025 5026 // Pipeline class for compares. 5027 pipe_class pipe_class_compare() %{ 5028 single_instruction; 5029 fixed_latency(16); 5030 %} 5031 5032 // Pipeline class for traps. 5033 pipe_class pipe_class_trap() %{ 5034 single_instruction; 5035 fixed_latency(100); 5036 %} 5037 5038 // Pipeline class for memory operations. 5039 pipe_class pipe_class_memory() %{ 5040 single_instruction; 5041 fixed_latency(16); 5042 %} 5043 5044 // Pipeline class for call. 5045 pipe_class pipe_class_call() %{ 5046 single_instruction; 5047 fixed_latency(100); 5048 %} 5049 5050 // Define the class for the Nop node. 5051 define %{ 5052 MachNop = pipe_class_default; 5053 %} 5054 5055 %} 5056 5057 //----------INSTRUCTIONS------------------------------------------------------- 5058 5059 // Naming of instructions: 5060 // opA_operB / opA_operB_operC: 5061 // Operation 'op' with one or two source operands 'oper'. Result 5062 // type is A, source operand types are B and C. 5063 // Iff A == B == C, B and C are left out. 5064 // 5065 // The instructions are ordered according to the following scheme: 5066 // - loads 5067 // - load constants 5068 // - prefetch 5069 // - store 5070 // - encode/decode 5071 // - membar 5072 // - conditional moves 5073 // - compare & swap 5074 // - arithmetic and logic operations 5075 // * int: Add, Sub, Mul, Div, Mod 5076 // * int: lShift, arShift, urShift, rot 5077 // * float: Add, Sub, Mul, Div 5078 // * and, or, xor ... 5079 // - register moves: float <-> int, reg <-> stack, repl 5080 // - cast (high level type cast, XtoP, castPP, castII, not_null etc. 5081 // - conv (low level type cast requiring bit changes (sign extend etc) 5082 // - compares, range & zero checks. 5083 // - branches 5084 // - complex operations, intrinsics, min, max, replicate 5085 // - lock 5086 // - Calls 5087 // 5088 // If there are similar instructions with different types they are sorted: 5089 // int before float 5090 // small before big 5091 // signed before unsigned 5092 // e.g., loadS before loadUS before loadI before loadF. 5093 5094 5095 //----------Load/Store Instructions-------------------------------------------- 5096 5097 //----------Load Instructions-------------------------------------------------- 5098 5099 // Converts byte to int. 5100 // As convB2I_reg, but without match rule. The match rule of convB2I_reg 5101 // reuses the 'amount' operand, but adlc expects that operand specification 5102 // and operands in match rule are equivalent. 5103 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ 5104 effect(DEF dst, USE src); 5105 format %{ "EXTSB $dst, $src \t// byte->int" %} 5106 size(4); 5107 ins_encode %{ 5108 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 5109 __ extsb($dst$$Register, $src$$Register); 5110 %} 5111 ins_pipe(pipe_class_default); 5112 %} 5113 5114 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ 5115 // match-rule, false predicate 5116 match(Set dst (LoadB mem)); 5117 predicate(false); 5118 5119 format %{ "LBZ $dst, $mem" %} 5120 size(4); 5121 ins_encode( enc_lbz(dst, mem) ); 5122 ins_pipe(pipe_class_memory); 5123 %} 5124 5125 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ 5126 // match-rule, false predicate 5127 match(Set dst (LoadB mem)); 5128 predicate(false); 5129 5130 format %{ "LBZ $dst, $mem\n\t" 5131 "TWI $dst\n\t" 5132 "ISYNC" %} 5133 size(12); 5134 ins_encode( enc_lbz_ac(dst, mem) ); 5135 ins_pipe(pipe_class_memory); 5136 %} 5137 5138 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5139 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ 5140 match(Set dst (LoadB mem)); 5141 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5142 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5143 expand %{ 5144 iRegIdst tmp; 5145 loadUB_indirect(tmp, mem); 5146 convB2I_reg_2(dst, tmp); 5147 %} 5148 %} 5149 5150 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ 5151 match(Set dst (LoadB mem)); 5152 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5153 expand %{ 5154 iRegIdst tmp; 5155 loadUB_indirect_ac(tmp, mem); 5156 convB2I_reg_2(dst, tmp); 5157 %} 5158 %} 5159 5160 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ 5161 // match-rule, false predicate 5162 match(Set dst (LoadB mem)); 5163 predicate(false); 5164 5165 format %{ "LBZ $dst, $mem" %} 5166 size(4); 5167 ins_encode( enc_lbz(dst, mem) ); 5168 ins_pipe(pipe_class_memory); 5169 %} 5170 5171 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ 5172 // match-rule, false predicate 5173 match(Set dst (LoadB mem)); 5174 predicate(false); 5175 5176 format %{ "LBZ $dst, $mem\n\t" 5177 "TWI $dst\n\t" 5178 "ISYNC" %} 5179 size(12); 5180 ins_encode( enc_lbz_ac(dst, mem) ); 5181 ins_pipe(pipe_class_memory); 5182 %} 5183 5184 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5185 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ 5186 match(Set dst (LoadB mem)); 5187 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5188 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5189 5190 expand %{ 5191 iRegIdst tmp; 5192 loadUB_indOffset16(tmp, mem); 5193 convB2I_reg_2(dst, tmp); 5194 %} 5195 %} 5196 5197 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ 5198 match(Set dst (LoadB mem)); 5199 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5200 5201 expand %{ 5202 iRegIdst tmp; 5203 loadUB_indOffset16_ac(tmp, mem); 5204 convB2I_reg_2(dst, tmp); 5205 %} 5206 %} 5207 5208 // Load Unsigned Byte (8bit UNsigned) into an int reg. 5209 instruct loadUB(iRegIdst dst, memory mem) %{ 5210 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5211 match(Set dst (LoadUB mem)); 5212 ins_cost(MEMORY_REF_COST); 5213 5214 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} 5215 size(4); 5216 ins_encode( enc_lbz(dst, mem) ); 5217 ins_pipe(pipe_class_memory); 5218 %} 5219 5220 // Load Unsigned Byte (8bit UNsigned) acquire. 5221 instruct loadUB_ac(iRegIdst dst, memory mem) %{ 5222 match(Set dst (LoadUB mem)); 5223 ins_cost(3*MEMORY_REF_COST); 5224 5225 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" 5226 "TWI $dst\n\t" 5227 "ISYNC" %} 5228 size(12); 5229 ins_encode( enc_lbz_ac(dst, mem) ); 5230 ins_pipe(pipe_class_memory); 5231 %} 5232 5233 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 5234 instruct loadUB2L(iRegLdst dst, memory mem) %{ 5235 match(Set dst (ConvI2L (LoadUB mem))); 5236 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5237 ins_cost(MEMORY_REF_COST); 5238 5239 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} 5240 size(4); 5241 ins_encode( enc_lbz(dst, mem) ); 5242 ins_pipe(pipe_class_memory); 5243 %} 5244 5245 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ 5246 match(Set dst (ConvI2L (LoadUB mem))); 5247 ins_cost(3*MEMORY_REF_COST); 5248 5249 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" 5250 "TWI $dst\n\t" 5251 "ISYNC" %} 5252 size(12); 5253 ins_encode( enc_lbz_ac(dst, mem) ); 5254 ins_pipe(pipe_class_memory); 5255 %} 5256 5257 // Load Short (16bit signed) 5258 instruct loadS(iRegIdst dst, memory mem) %{ 5259 match(Set dst (LoadS mem)); 5260 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5261 ins_cost(MEMORY_REF_COST); 5262 5263 format %{ "LHA $dst, $mem" %} 5264 size(4); 5265 ins_encode %{ 5266 // TODO: PPC port $archOpcode(ppc64Opcode_lha); 5267 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5268 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5269 %} 5270 ins_pipe(pipe_class_memory); 5271 %} 5272 5273 // Load Short (16bit signed) acquire. 5274 instruct loadS_ac(iRegIdst dst, memory mem) %{ 5275 match(Set dst (LoadS mem)); 5276 ins_cost(3*MEMORY_REF_COST); 5277 5278 format %{ "LHA $dst, $mem\t acquire\n\t" 5279 "TWI $dst\n\t" 5280 "ISYNC" %} 5281 size(12); 5282 ins_encode %{ 5283 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5284 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5285 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5286 __ twi_0($dst$$Register); 5287 __ isync(); 5288 %} 5289 ins_pipe(pipe_class_memory); 5290 %} 5291 5292 // Load Char (16bit unsigned) 5293 instruct loadUS(iRegIdst dst, memory mem) %{ 5294 match(Set dst (LoadUS mem)); 5295 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5296 ins_cost(MEMORY_REF_COST); 5297 5298 format %{ "LHZ $dst, $mem" %} 5299 size(4); 5300 ins_encode( enc_lhz(dst, mem) ); 5301 ins_pipe(pipe_class_memory); 5302 %} 5303 5304 // Load Char (16bit unsigned) acquire. 5305 instruct loadUS_ac(iRegIdst dst, memory mem) %{ 5306 match(Set dst (LoadUS mem)); 5307 ins_cost(3*MEMORY_REF_COST); 5308 5309 format %{ "LHZ $dst, $mem \t// acquire\n\t" 5310 "TWI $dst\n\t" 5311 "ISYNC" %} 5312 size(12); 5313 ins_encode( enc_lhz_ac(dst, mem) ); 5314 ins_pipe(pipe_class_memory); 5315 %} 5316 5317 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 5318 instruct loadUS2L(iRegLdst dst, memory mem) %{ 5319 match(Set dst (ConvI2L (LoadUS mem))); 5320 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5321 ins_cost(MEMORY_REF_COST); 5322 5323 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} 5324 size(4); 5325 ins_encode( enc_lhz(dst, mem) ); 5326 ins_pipe(pipe_class_memory); 5327 %} 5328 5329 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. 5330 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ 5331 match(Set dst (ConvI2L (LoadUS mem))); 5332 ins_cost(3*MEMORY_REF_COST); 5333 5334 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" 5335 "TWI $dst\n\t" 5336 "ISYNC" %} 5337 size(12); 5338 ins_encode( enc_lhz_ac(dst, mem) ); 5339 ins_pipe(pipe_class_memory); 5340 %} 5341 5342 // Load Integer. 5343 instruct loadI(iRegIdst dst, memory mem) %{ 5344 match(Set dst (LoadI mem)); 5345 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5346 ins_cost(MEMORY_REF_COST); 5347 5348 format %{ "LWZ $dst, $mem" %} 5349 size(4); 5350 ins_encode( enc_lwz(dst, mem) ); 5351 ins_pipe(pipe_class_memory); 5352 %} 5353 5354 // Load Integer acquire. 5355 instruct loadI_ac(iRegIdst dst, memory mem) %{ 5356 match(Set dst (LoadI mem)); 5357 ins_cost(3*MEMORY_REF_COST); 5358 5359 format %{ "LWZ $dst, $mem \t// load acquire\n\t" 5360 "TWI $dst\n\t" 5361 "ISYNC" %} 5362 size(12); 5363 ins_encode( enc_lwz_ac(dst, mem) ); 5364 ins_pipe(pipe_class_memory); 5365 %} 5366 5367 // Match loading integer and casting it to unsigned int in 5368 // long register. 5369 // LoadI + ConvI2L + AndL 0xffffffff. 5370 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ 5371 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5372 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); 5373 ins_cost(MEMORY_REF_COST); 5374 5375 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} 5376 size(4); 5377 ins_encode( enc_lwz(dst, mem) ); 5378 ins_pipe(pipe_class_memory); 5379 %} 5380 5381 // Match loading integer and casting it to long. 5382 instruct loadI2L(iRegLdst dst, memory mem) %{ 5383 match(Set dst (ConvI2L (LoadI mem))); 5384 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5385 ins_cost(MEMORY_REF_COST); 5386 5387 format %{ "LWA $dst, $mem \t// loadI2L" %} 5388 size(4); 5389 ins_encode %{ 5390 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5391 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5392 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5393 %} 5394 ins_pipe(pipe_class_memory); 5395 %} 5396 5397 // Match loading integer and casting it to long - acquire. 5398 instruct loadI2L_ac(iRegLdst dst, memory mem) %{ 5399 match(Set dst (ConvI2L (LoadI mem))); 5400 ins_cost(3*MEMORY_REF_COST); 5401 5402 format %{ "LWA $dst, $mem \t// loadI2L acquire" 5403 "TWI $dst\n\t" 5404 "ISYNC" %} 5405 size(12); 5406 ins_encode %{ 5407 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5408 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5409 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5410 __ twi_0($dst$$Register); 5411 __ isync(); 5412 %} 5413 ins_pipe(pipe_class_memory); 5414 %} 5415 5416 // Load Long - aligned 5417 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ 5418 match(Set dst (LoadL mem)); 5419 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5420 ins_cost(MEMORY_REF_COST); 5421 5422 format %{ "LD $dst, $mem \t// long" %} 5423 size(4); 5424 ins_encode( enc_ld(dst, mem) ); 5425 ins_pipe(pipe_class_memory); 5426 %} 5427 5428 // Load Long - aligned acquire. 5429 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ 5430 match(Set dst (LoadL mem)); 5431 ins_cost(3*MEMORY_REF_COST); 5432 5433 format %{ "LD $dst, $mem \t// long acquire\n\t" 5434 "TWI $dst\n\t" 5435 "ISYNC" %} 5436 size(12); 5437 ins_encode( enc_ld_ac(dst, mem) ); 5438 ins_pipe(pipe_class_memory); 5439 %} 5440 5441 // Load Long - UNaligned 5442 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ 5443 match(Set dst (LoadL_unaligned mem)); 5444 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5445 ins_cost(MEMORY_REF_COST); 5446 5447 format %{ "LD $dst, $mem \t// unaligned long" %} 5448 size(4); 5449 ins_encode( enc_ld(dst, mem) ); 5450 ins_pipe(pipe_class_memory); 5451 %} 5452 5453 // Load nodes for superwords 5454 5455 // Load Aligned Packed Byte 5456 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ 5457 predicate(n->as_LoadVector()->memory_size() == 8); 5458 match(Set dst (LoadVector mem)); 5459 ins_cost(MEMORY_REF_COST); 5460 5461 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} 5462 size(4); 5463 ins_encode( enc_ld(dst, mem) ); 5464 ins_pipe(pipe_class_memory); 5465 %} 5466 5467 // Load Range, range = array length (=jint) 5468 instruct loadRange(iRegIdst dst, memory mem) %{ 5469 match(Set dst (LoadRange mem)); 5470 ins_cost(MEMORY_REF_COST); 5471 5472 format %{ "LWZ $dst, $mem \t// range" %} 5473 size(4); 5474 ins_encode( enc_lwz(dst, mem) ); 5475 ins_pipe(pipe_class_memory); 5476 %} 5477 5478 // Load Compressed Pointer 5479 instruct loadN(iRegNdst dst, memory mem) %{ 5480 match(Set dst (LoadN mem)); 5481 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5482 ins_cost(MEMORY_REF_COST); 5483 5484 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} 5485 size(4); 5486 ins_encode( enc_lwz(dst, mem) ); 5487 ins_pipe(pipe_class_memory); 5488 %} 5489 5490 // Load Compressed Pointer acquire. 5491 instruct loadN_ac(iRegNdst dst, memory mem) %{ 5492 match(Set dst (LoadN mem)); 5493 ins_cost(3*MEMORY_REF_COST); 5494 5495 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" 5496 "TWI $dst\n\t" 5497 "ISYNC" %} 5498 size(12); 5499 ins_encode( enc_lwz_ac(dst, mem) ); 5500 ins_pipe(pipe_class_memory); 5501 %} 5502 5503 // Load Compressed Pointer and decode it if narrow_oop_shift == 0. 5504 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ 5505 match(Set dst (DecodeN (LoadN mem))); 5506 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); 5507 ins_cost(MEMORY_REF_COST); 5508 5509 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5510 size(4); 5511 ins_encode( enc_lwz(dst, mem) ); 5512 ins_pipe(pipe_class_memory); 5513 %} 5514 5515 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{ 5516 match(Set dst (DecodeNKlass (LoadNKlass mem))); 5517 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 && 5518 _kids[0]->_leaf->as_Load()->is_unordered()); 5519 ins_cost(MEMORY_REF_COST); 5520 5521 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5522 size(4); 5523 ins_encode( enc_lwz(dst, mem) ); 5524 ins_pipe(pipe_class_memory); 5525 %} 5526 5527 // Load Pointer 5528 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ 5529 match(Set dst (LoadP mem)); 5530 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5531 ins_cost(MEMORY_REF_COST); 5532 5533 format %{ "LD $dst, $mem \t// ptr" %} 5534 size(4); 5535 ins_encode( enc_ld(dst, mem) ); 5536 ins_pipe(pipe_class_memory); 5537 %} 5538 5539 // Load Pointer acquire. 5540 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ 5541 match(Set dst (LoadP mem)); 5542 ins_cost(3*MEMORY_REF_COST); 5543 5544 format %{ "LD $dst, $mem \t// ptr acquire\n\t" 5545 "TWI $dst\n\t" 5546 "ISYNC" %} 5547 size(12); 5548 ins_encode( enc_ld_ac(dst, mem) ); 5549 ins_pipe(pipe_class_memory); 5550 %} 5551 5552 // LoadP + CastP2L 5553 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ 5554 match(Set dst (CastP2X (LoadP mem))); 5555 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5556 ins_cost(MEMORY_REF_COST); 5557 5558 format %{ "LD $dst, $mem \t// ptr + p2x" %} 5559 size(4); 5560 ins_encode( enc_ld(dst, mem) ); 5561 ins_pipe(pipe_class_memory); 5562 %} 5563 5564 // Load compressed klass pointer. 5565 instruct loadNKlass(iRegNdst dst, memory mem) %{ 5566 match(Set dst (LoadNKlass mem)); 5567 ins_cost(MEMORY_REF_COST); 5568 5569 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} 5570 size(4); 5571 ins_encode( enc_lwz(dst, mem) ); 5572 ins_pipe(pipe_class_memory); 5573 %} 5574 5575 // Load Klass Pointer 5576 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ 5577 match(Set dst (LoadKlass mem)); 5578 ins_cost(MEMORY_REF_COST); 5579 5580 format %{ "LD $dst, $mem \t// klass ptr" %} 5581 size(4); 5582 ins_encode( enc_ld(dst, mem) ); 5583 ins_pipe(pipe_class_memory); 5584 %} 5585 5586 // Load Float 5587 instruct loadF(regF dst, memory mem) %{ 5588 match(Set dst (LoadF mem)); 5589 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5590 ins_cost(MEMORY_REF_COST); 5591 5592 format %{ "LFS $dst, $mem" %} 5593 size(4); 5594 ins_encode %{ 5595 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 5596 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5597 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5598 %} 5599 ins_pipe(pipe_class_memory); 5600 %} 5601 5602 // Load Float acquire. 5603 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{ 5604 match(Set dst (LoadF mem)); 5605 effect(TEMP cr0); 5606 ins_cost(3*MEMORY_REF_COST); 5607 5608 format %{ "LFS $dst, $mem \t// acquire\n\t" 5609 "FCMPU cr0, $dst, $dst\n\t" 5610 "BNE cr0, next\n" 5611 "next:\n\t" 5612 "ISYNC" %} 5613 size(16); 5614 ins_encode %{ 5615 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5616 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5617 Label next; 5618 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5619 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5620 __ bne(CCR0, next); 5621 __ bind(next); 5622 __ isync(); 5623 %} 5624 ins_pipe(pipe_class_memory); 5625 %} 5626 5627 // Load Double - aligned 5628 instruct loadD(regD dst, memory mem) %{ 5629 match(Set dst (LoadD mem)); 5630 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5631 ins_cost(MEMORY_REF_COST); 5632 5633 format %{ "LFD $dst, $mem" %} 5634 size(4); 5635 ins_encode( enc_lfd(dst, mem) ); 5636 ins_pipe(pipe_class_memory); 5637 %} 5638 5639 // Load Double - aligned acquire. 5640 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{ 5641 match(Set dst (LoadD mem)); 5642 effect(TEMP cr0); 5643 ins_cost(3*MEMORY_REF_COST); 5644 5645 format %{ "LFD $dst, $mem \t// acquire\n\t" 5646 "FCMPU cr0, $dst, $dst\n\t" 5647 "BNE cr0, next\n" 5648 "next:\n\t" 5649 "ISYNC" %} 5650 size(16); 5651 ins_encode %{ 5652 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5653 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5654 Label next; 5655 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5656 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5657 __ bne(CCR0, next); 5658 __ bind(next); 5659 __ isync(); 5660 %} 5661 ins_pipe(pipe_class_memory); 5662 %} 5663 5664 // Load Double - UNaligned 5665 instruct loadD_unaligned(regD dst, memory mem) %{ 5666 match(Set dst (LoadD_unaligned mem)); 5667 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5668 ins_cost(MEMORY_REF_COST); 5669 5670 format %{ "LFD $dst, $mem" %} 5671 size(4); 5672 ins_encode( enc_lfd(dst, mem) ); 5673 ins_pipe(pipe_class_memory); 5674 %} 5675 5676 //----------Constants-------------------------------------------------------- 5677 5678 // Load MachConstantTableBase: add hi offset to global toc. 5679 // TODO: Handle hidden register r29 in bundler! 5680 instruct loadToc_hi(iRegLdst dst) %{ 5681 effect(DEF dst); 5682 ins_cost(DEFAULT_COST); 5683 5684 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} 5685 size(4); 5686 ins_encode %{ 5687 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5688 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); 5689 %} 5690 ins_pipe(pipe_class_default); 5691 %} 5692 5693 // Load MachConstantTableBase: add lo offset to global toc. 5694 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ 5695 effect(DEF dst, USE src); 5696 ins_cost(DEFAULT_COST); 5697 5698 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} 5699 size(4); 5700 ins_encode %{ 5701 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5702 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); 5703 %} 5704 ins_pipe(pipe_class_default); 5705 %} 5706 5707 // Load 16-bit integer constant 0xssss???? 5708 instruct loadConI16(iRegIdst dst, immI16 src) %{ 5709 match(Set dst src); 5710 5711 format %{ "LI $dst, $src" %} 5712 size(4); 5713 ins_encode %{ 5714 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5715 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 5716 %} 5717 ins_pipe(pipe_class_default); 5718 %} 5719 5720 // Load integer constant 0x????0000 5721 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ 5722 match(Set dst src); 5723 ins_cost(DEFAULT_COST); 5724 5725 format %{ "LIS $dst, $src.hi" %} 5726 size(4); 5727 ins_encode %{ 5728 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5729 // Lis sign extends 16-bit src then shifts it 16 bit to the left. 5730 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5731 %} 5732 ins_pipe(pipe_class_default); 5733 %} 5734 5735 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted 5736 // and sign extended), this adds the low 16 bits. 5737 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 5738 // no match-rule, false predicate 5739 effect(DEF dst, USE src1, USE src2); 5740 predicate(false); 5741 5742 format %{ "ORI $dst, $src1.hi, $src2.lo" %} 5743 size(4); 5744 ins_encode %{ 5745 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5746 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5747 %} 5748 ins_pipe(pipe_class_default); 5749 %} 5750 5751 instruct loadConI_Ex(iRegIdst dst, immI src) %{ 5752 match(Set dst src); 5753 ins_cost(DEFAULT_COST*2); 5754 5755 expand %{ 5756 // Would like to use $src$$constant. 5757 immI16 srcLo %{ _opnds[1]->constant() %} 5758 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5759 immIhi16 srcHi %{ _opnds[1]->constant() %} 5760 iRegIdst tmpI; 5761 loadConIhi16(tmpI, srcHi); 5762 loadConI32_lo16(dst, tmpI, srcLo); 5763 %} 5764 %} 5765 5766 // No constant pool entries required. 5767 instruct loadConL16(iRegLdst dst, immL16 src) %{ 5768 match(Set dst src); 5769 5770 format %{ "LI $dst, $src \t// long" %} 5771 size(4); 5772 ins_encode %{ 5773 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5774 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); 5775 %} 5776 ins_pipe(pipe_class_default); 5777 %} 5778 5779 // Load long constant 0xssssssss????0000 5780 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ 5781 match(Set dst src); 5782 ins_cost(DEFAULT_COST); 5783 5784 format %{ "LIS $dst, $src.hi \t// long" %} 5785 size(4); 5786 ins_encode %{ 5787 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5788 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5789 %} 5790 ins_pipe(pipe_class_default); 5791 %} 5792 5793 // To load a 32 bit constant: merge lower 16 bits into already loaded 5794 // high 16 bits. 5795 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 5796 // no match-rule, false predicate 5797 effect(DEF dst, USE src1, USE src2); 5798 predicate(false); 5799 5800 format %{ "ORI $dst, $src1, $src2.lo" %} 5801 size(4); 5802 ins_encode %{ 5803 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5804 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5805 %} 5806 ins_pipe(pipe_class_default); 5807 %} 5808 5809 // Load 32-bit long constant 5810 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ 5811 match(Set dst src); 5812 ins_cost(DEFAULT_COST*2); 5813 5814 expand %{ 5815 // Would like to use $src$$constant. 5816 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} 5817 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5818 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} 5819 iRegLdst tmpL; 5820 loadConL32hi16(tmpL, srcHi); 5821 loadConL32_lo16(dst, tmpL, srcLo); 5822 %} 5823 %} 5824 5825 // Load long constant 0x????000000000000. 5826 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ 5827 match(Set dst src); 5828 ins_cost(DEFAULT_COST); 5829 5830 expand %{ 5831 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} 5832 immI shift32 %{ 32 %} 5833 iRegLdst tmpL; 5834 loadConL32hi16(tmpL, srcHi); 5835 lshiftL_regL_immI(dst, tmpL, shift32); 5836 %} 5837 %} 5838 5839 // Expand node for constant pool load: small offset. 5840 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ 5841 effect(DEF dst, USE src, USE toc); 5842 ins_cost(MEMORY_REF_COST); 5843 5844 ins_num_consts(1); 5845 // Needed so that CallDynamicJavaDirect can compute the address of this 5846 // instruction for relocation. 5847 ins_field_cbuf_insts_offset(int); 5848 5849 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} 5850 size(4); 5851 ins_encode( enc_load_long_constL(dst, src, toc) ); 5852 ins_pipe(pipe_class_memory); 5853 %} 5854 5855 // Expand node for constant pool load: large offset. 5856 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ 5857 effect(DEF dst, USE src, USE toc); 5858 predicate(false); 5859 5860 ins_num_consts(1); 5861 ins_field_const_toc_offset(int); 5862 // Needed so that CallDynamicJavaDirect can compute the address of this 5863 // instruction for relocation. 5864 ins_field_cbuf_insts_offset(int); 5865 5866 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} 5867 size(4); 5868 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); 5869 ins_pipe(pipe_class_default); 5870 %} 5871 5872 // Expand node for constant pool load: large offset. 5873 // No constant pool entries required. 5874 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ 5875 effect(DEF dst, USE src, USE base); 5876 predicate(false); 5877 5878 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); 5879 5880 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} 5881 size(4); 5882 ins_encode %{ 5883 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 5884 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 5885 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 5886 %} 5887 ins_pipe(pipe_class_memory); 5888 %} 5889 5890 // Load long constant from constant table. Expand in case of 5891 // offset > 16 bit is needed. 5892 // Adlc adds toc node MachConstantTableBase. 5893 instruct loadConL_Ex(iRegLdst dst, immL src) %{ 5894 match(Set dst src); 5895 ins_cost(MEMORY_REF_COST); 5896 5897 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} 5898 // We can not inline the enc_class for the expand as that does not support constanttablebase. 5899 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); 5900 %} 5901 5902 // Load NULL as compressed oop. 5903 instruct loadConN0(iRegNdst dst, immN_0 src) %{ 5904 match(Set dst src); 5905 ins_cost(DEFAULT_COST); 5906 5907 format %{ "LI $dst, $src \t// compressed ptr" %} 5908 size(4); 5909 ins_encode %{ 5910 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5911 __ li($dst$$Register, 0); 5912 %} 5913 ins_pipe(pipe_class_default); 5914 %} 5915 5916 // Load hi part of compressed oop constant. 5917 instruct loadConN_hi(iRegNdst dst, immN src) %{ 5918 effect(DEF dst, USE src); 5919 ins_cost(DEFAULT_COST); 5920 5921 format %{ "LIS $dst, $src \t// narrow oop hi" %} 5922 size(4); 5923 ins_encode %{ 5924 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5925 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); 5926 %} 5927 ins_pipe(pipe_class_default); 5928 %} 5929 5930 // Add lo part of compressed oop constant to already loaded hi part. 5931 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ 5932 effect(DEF dst, USE src1, USE src2); 5933 ins_cost(DEFAULT_COST); 5934 5935 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} 5936 size(4); 5937 ins_encode %{ 5938 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5939 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5940 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); 5941 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5942 __ relocate(rspec, 1); 5943 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); 5944 %} 5945 ins_pipe(pipe_class_default); 5946 %} 5947 5948 // Needed to postalloc expand loadConN: ConN is loaded as ConI 5949 // leaving the upper 32 bits with sign-extension bits. 5950 // This clears these bits: dst = src & 0xFFFFFFFF. 5951 // TODO: Eventually call this maskN_regN_FFFFFFFF. 5952 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ 5953 effect(DEF dst, USE src); 5954 predicate(false); 5955 5956 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask 5957 size(4); 5958 ins_encode %{ 5959 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 5960 __ clrldi($dst$$Register, $src$$Register, 0x20); 5961 %} 5962 ins_pipe(pipe_class_default); 5963 %} 5964 5965 // Optimize DecodeN for disjoint base. 5966 // Load base of compressed oops into a register 5967 instruct loadBase(iRegLdst dst) %{ 5968 effect(DEF dst); 5969 5970 format %{ "LoadConst $dst, heapbase" %} 5971 ins_encode %{ 5972 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5973 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0); 5974 %} 5975 ins_pipe(pipe_class_default); 5976 %} 5977 5978 // Loading ConN must be postalloc expanded so that edges between 5979 // the nodes are safe. They may not interfere with a safepoint. 5980 // GL TODO: This needs three instructions: better put this into the constant pool. 5981 instruct loadConN_Ex(iRegNdst dst, immN src) %{ 5982 match(Set dst src); 5983 ins_cost(DEFAULT_COST*2); 5984 5985 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 5986 postalloc_expand %{ 5987 MachNode *m1 = new loadConN_hiNode(); 5988 MachNode *m2 = new loadConN_loNode(); 5989 MachNode *m3 = new clearMs32bNode(); 5990 m1->add_req(NULL); 5991 m2->add_req(NULL, m1); 5992 m3->add_req(NULL, m2); 5993 m1->_opnds[0] = op_dst; 5994 m1->_opnds[1] = op_src; 5995 m2->_opnds[0] = op_dst; 5996 m2->_opnds[1] = op_dst; 5997 m2->_opnds[2] = op_src; 5998 m3->_opnds[0] = op_dst; 5999 m3->_opnds[1] = op_dst; 6000 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6001 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6002 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6003 nodes->push(m1); 6004 nodes->push(m2); 6005 nodes->push(m3); 6006 %} 6007 %} 6008 6009 // We have seen a safepoint between the hi and lo parts, and this node was handled 6010 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is 6011 // not a narrow oop. 6012 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{ 6013 match(Set dst src); 6014 effect(DEF dst, USE src); 6015 ins_cost(DEFAULT_COST); 6016 6017 format %{ "LIS $dst, $src \t// narrow klass hi" %} 6018 size(4); 6019 ins_encode %{ 6020 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 6021 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); 6022 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); 6023 %} 6024 ins_pipe(pipe_class_default); 6025 %} 6026 6027 // As loadConNKlass_hi this must be recognized as narrow klass, not oop! 6028 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6029 match(Set dst src1); 6030 effect(TEMP src2); 6031 ins_cost(DEFAULT_COST); 6032 6033 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask 6034 size(4); 6035 ins_encode %{ 6036 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6037 __ clrldi($dst$$Register, $src2$$Register, 0x20); 6038 %} 6039 ins_pipe(pipe_class_default); 6040 %} 6041 6042 // This needs a match rule so that build_oop_map knows this is 6043 // not a narrow oop. 6044 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6045 match(Set dst src1); 6046 effect(TEMP src2); 6047 ins_cost(DEFAULT_COST); 6048 6049 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %} 6050 size(4); 6051 ins_encode %{ 6052 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 6053 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); 6054 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6055 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); 6056 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6057 6058 __ relocate(rspec, 1); 6059 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); 6060 %} 6061 ins_pipe(pipe_class_default); 6062 %} 6063 6064 // Loading ConNKlass must be postalloc expanded so that edges between 6065 // the nodes are safe. They may not interfere with a safepoint. 6066 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ 6067 match(Set dst src); 6068 ins_cost(DEFAULT_COST*2); 6069 6070 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6071 postalloc_expand %{ 6072 // Load high bits into register. Sign extended. 6073 MachNode *m1 = new loadConNKlass_hiNode(); 6074 m1->add_req(NULL); 6075 m1->_opnds[0] = op_dst; 6076 m1->_opnds[1] = op_src; 6077 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6078 nodes->push(m1); 6079 6080 MachNode *m2 = m1; 6081 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { 6082 // Value might be 1-extended. Mask out these bits. 6083 m2 = new loadConNKlass_maskNode(); 6084 m2->add_req(NULL, m1); 6085 m2->_opnds[0] = op_dst; 6086 m2->_opnds[1] = op_src; 6087 m2->_opnds[2] = op_dst; 6088 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6089 nodes->push(m2); 6090 } 6091 6092 MachNode *m3 = new loadConNKlass_loNode(); 6093 m3->add_req(NULL, m2); 6094 m3->_opnds[0] = op_dst; 6095 m3->_opnds[1] = op_src; 6096 m3->_opnds[2] = op_dst; 6097 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6098 nodes->push(m3); 6099 %} 6100 %} 6101 6102 // 0x1 is used in object initialization (initial object header). 6103 // No constant pool entries required. 6104 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ 6105 match(Set dst src); 6106 6107 format %{ "LI $dst, $src \t// ptr" %} 6108 size(4); 6109 ins_encode %{ 6110 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6111 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 6112 %} 6113 ins_pipe(pipe_class_default); 6114 %} 6115 6116 // Expand node for constant pool load: small offset. 6117 // The match rule is needed to generate the correct bottom_type(), 6118 // however this node should never match. The use of predicate is not 6119 // possible since ADLC forbids predicates for chain rules. The higher 6120 // costs do not prevent matching in this case. For that reason the 6121 // operand immP_NM with predicate(false) is used. 6122 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6123 match(Set dst src); 6124 effect(TEMP toc); 6125 6126 ins_num_consts(1); 6127 6128 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} 6129 size(4); 6130 ins_encode( enc_load_long_constP(dst, src, toc) ); 6131 ins_pipe(pipe_class_memory); 6132 %} 6133 6134 // Expand node for constant pool load: large offset. 6135 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6136 effect(DEF dst, USE src, USE toc); 6137 predicate(false); 6138 6139 ins_num_consts(1); 6140 ins_field_const_toc_offset(int); 6141 6142 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} 6143 size(4); 6144 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); 6145 ins_pipe(pipe_class_default); 6146 %} 6147 6148 // Expand node for constant pool load: large offset. 6149 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ 6150 match(Set dst src); 6151 effect(TEMP base); 6152 6153 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); 6154 6155 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} 6156 size(4); 6157 ins_encode %{ 6158 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 6159 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 6160 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 6161 %} 6162 ins_pipe(pipe_class_memory); 6163 %} 6164 6165 // Load pointer constant from constant table. Expand in case an 6166 // offset > 16 bit is needed. 6167 // Adlc adds toc node MachConstantTableBase. 6168 instruct loadConP_Ex(iRegPdst dst, immP src) %{ 6169 match(Set dst src); 6170 ins_cost(MEMORY_REF_COST); 6171 6172 // This rule does not use "expand" because then 6173 // the result type is not known to be an Oop. An ADLC 6174 // enhancement will be needed to make that work - not worth it! 6175 6176 // If this instruction rematerializes, it prolongs the live range 6177 // of the toc node, causing illegal graphs. 6178 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). 6179 ins_cannot_rematerialize(true); 6180 6181 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} 6182 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); 6183 %} 6184 6185 // Expand node for constant pool load: small offset. 6186 instruct loadConF(regF dst, immF src, iRegLdst toc) %{ 6187 effect(DEF dst, USE src, USE toc); 6188 ins_cost(MEMORY_REF_COST); 6189 6190 ins_num_consts(1); 6191 6192 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} 6193 size(4); 6194 ins_encode %{ 6195 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 6196 address float_address = __ float_constant($src$$constant); 6197 if (float_address == NULL) { 6198 ciEnv::current()->record_out_of_memory_failure(); 6199 return; 6200 } 6201 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); 6202 %} 6203 ins_pipe(pipe_class_memory); 6204 %} 6205 6206 // Expand node for constant pool load: large offset. 6207 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ 6208 effect(DEF dst, USE src, USE toc); 6209 ins_cost(MEMORY_REF_COST); 6210 6211 ins_num_consts(1); 6212 6213 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6214 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" 6215 "ADDIS $toc, $toc, -offset_hi"%} 6216 size(12); 6217 ins_encode %{ 6218 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6219 FloatRegister Rdst = $dst$$FloatRegister; 6220 Register Rtoc = $toc$$Register; 6221 address float_address = __ float_constant($src$$constant); 6222 if (float_address == NULL) { 6223 ciEnv::current()->record_out_of_memory_failure(); 6224 return; 6225 } 6226 int offset = __ offset_to_method_toc(float_address); 6227 int hi = (offset + (1<<15))>>16; 6228 int lo = offset - hi * (1<<16); 6229 6230 __ addis(Rtoc, Rtoc, hi); 6231 __ lfs(Rdst, lo, Rtoc); 6232 __ addis(Rtoc, Rtoc, -hi); 6233 %} 6234 ins_pipe(pipe_class_memory); 6235 %} 6236 6237 // Adlc adds toc node MachConstantTableBase. 6238 instruct loadConF_Ex(regF dst, immF src) %{ 6239 match(Set dst src); 6240 ins_cost(MEMORY_REF_COST); 6241 6242 // See loadConP. 6243 ins_cannot_rematerialize(true); 6244 6245 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6246 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); 6247 %} 6248 6249 // Expand node for constant pool load: small offset. 6250 instruct loadConD(regD dst, immD src, iRegLdst toc) %{ 6251 effect(DEF dst, USE src, USE toc); 6252 ins_cost(MEMORY_REF_COST); 6253 6254 ins_num_consts(1); 6255 6256 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} 6257 size(4); 6258 ins_encode %{ 6259 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 6260 address float_address = __ double_constant($src$$constant); 6261 if (float_address == NULL) { 6262 ciEnv::current()->record_out_of_memory_failure(); 6263 return; 6264 } 6265 int offset = __ offset_to_method_toc(float_address); 6266 __ lfd($dst$$FloatRegister, offset, $toc$$Register); 6267 %} 6268 ins_pipe(pipe_class_memory); 6269 %} 6270 6271 // Expand node for constant pool load: large offset. 6272 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ 6273 effect(DEF dst, USE src, USE toc); 6274 ins_cost(MEMORY_REF_COST); 6275 6276 ins_num_consts(1); 6277 6278 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6279 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" 6280 "ADDIS $toc, $toc, -offset_hi" %} 6281 size(12); 6282 ins_encode %{ 6283 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6284 FloatRegister Rdst = $dst$$FloatRegister; 6285 Register Rtoc = $toc$$Register; 6286 address float_address = __ double_constant($src$$constant); 6287 if (float_address == NULL) { 6288 ciEnv::current()->record_out_of_memory_failure(); 6289 return; 6290 } 6291 int offset = __ offset_to_method_toc(float_address); 6292 int hi = (offset + (1<<15))>>16; 6293 int lo = offset - hi * (1<<16); 6294 6295 __ addis(Rtoc, Rtoc, hi); 6296 __ lfd(Rdst, lo, Rtoc); 6297 __ addis(Rtoc, Rtoc, -hi); 6298 %} 6299 ins_pipe(pipe_class_memory); 6300 %} 6301 6302 // Adlc adds toc node MachConstantTableBase. 6303 instruct loadConD_Ex(regD dst, immD src) %{ 6304 match(Set dst src); 6305 ins_cost(MEMORY_REF_COST); 6306 6307 // See loadConP. 6308 ins_cannot_rematerialize(true); 6309 6310 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6311 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); 6312 %} 6313 6314 // Prefetch instructions. 6315 // Must be safe to execute with invalid address (cannot fault). 6316 6317 // Special prefetch versions which use the dcbz instruction. 6318 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ 6319 match(PrefetchAllocation (AddP mem src)); 6320 predicate(AllocatePrefetchStyle == 3); 6321 ins_cost(MEMORY_REF_COST); 6322 6323 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} 6324 size(4); 6325 ins_encode %{ 6326 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6327 __ dcbz($src$$Register, $mem$$base$$Register); 6328 %} 6329 ins_pipe(pipe_class_memory); 6330 %} 6331 6332 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ 6333 match(PrefetchAllocation mem); 6334 predicate(AllocatePrefetchStyle == 3); 6335 ins_cost(MEMORY_REF_COST); 6336 6337 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} 6338 size(4); 6339 ins_encode %{ 6340 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6341 __ dcbz($mem$$base$$Register); 6342 %} 6343 ins_pipe(pipe_class_memory); 6344 %} 6345 6346 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ 6347 match(PrefetchAllocation (AddP mem src)); 6348 predicate(AllocatePrefetchStyle != 3); 6349 ins_cost(MEMORY_REF_COST); 6350 6351 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} 6352 size(4); 6353 ins_encode %{ 6354 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6355 __ dcbtst($src$$Register, $mem$$base$$Register); 6356 %} 6357 ins_pipe(pipe_class_memory); 6358 %} 6359 6360 instruct prefetch_alloc_no_offset(indirectMemory mem) %{ 6361 match(PrefetchAllocation mem); 6362 predicate(AllocatePrefetchStyle != 3); 6363 ins_cost(MEMORY_REF_COST); 6364 6365 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} 6366 size(4); 6367 ins_encode %{ 6368 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6369 __ dcbtst($mem$$base$$Register); 6370 %} 6371 ins_pipe(pipe_class_memory); 6372 %} 6373 6374 //----------Store Instructions------------------------------------------------- 6375 6376 // Store Byte 6377 instruct storeB(memory mem, iRegIsrc src) %{ 6378 match(Set mem (StoreB mem src)); 6379 ins_cost(MEMORY_REF_COST); 6380 6381 format %{ "STB $src, $mem \t// byte" %} 6382 size(4); 6383 ins_encode %{ 6384 // TODO: PPC port $archOpcode(ppc64Opcode_stb); 6385 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6386 __ stb($src$$Register, Idisp, $mem$$base$$Register); 6387 %} 6388 ins_pipe(pipe_class_memory); 6389 %} 6390 6391 // Store Char/Short 6392 instruct storeC(memory mem, iRegIsrc src) %{ 6393 match(Set mem (StoreC mem src)); 6394 ins_cost(MEMORY_REF_COST); 6395 6396 format %{ "STH $src, $mem \t// short" %} 6397 size(4); 6398 ins_encode %{ 6399 // TODO: PPC port $archOpcode(ppc64Opcode_sth); 6400 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6401 __ sth($src$$Register, Idisp, $mem$$base$$Register); 6402 %} 6403 ins_pipe(pipe_class_memory); 6404 %} 6405 6406 // Store Integer 6407 instruct storeI(memory mem, iRegIsrc src) %{ 6408 match(Set mem (StoreI mem src)); 6409 ins_cost(MEMORY_REF_COST); 6410 6411 format %{ "STW $src, $mem" %} 6412 size(4); 6413 ins_encode( enc_stw(src, mem) ); 6414 ins_pipe(pipe_class_memory); 6415 %} 6416 6417 // ConvL2I + StoreI. 6418 instruct storeI_convL2I(memory mem, iRegLsrc src) %{ 6419 match(Set mem (StoreI mem (ConvL2I src))); 6420 ins_cost(MEMORY_REF_COST); 6421 6422 format %{ "STW l2i($src), $mem" %} 6423 size(4); 6424 ins_encode( enc_stw(src, mem) ); 6425 ins_pipe(pipe_class_memory); 6426 %} 6427 6428 // Store Long 6429 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ 6430 match(Set mem (StoreL mem src)); 6431 ins_cost(MEMORY_REF_COST); 6432 6433 format %{ "STD $src, $mem \t// long" %} 6434 size(4); 6435 ins_encode( enc_std(src, mem) ); 6436 ins_pipe(pipe_class_memory); 6437 %} 6438 6439 // Store super word nodes. 6440 6441 // Store Aligned Packed Byte long register to memory 6442 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ 6443 predicate(n->as_StoreVector()->memory_size() == 8); 6444 match(Set mem (StoreVector mem src)); 6445 ins_cost(MEMORY_REF_COST); 6446 6447 format %{ "STD $mem, $src \t// packed8B" %} 6448 size(4); 6449 ins_encode( enc_std(src, mem) ); 6450 ins_pipe(pipe_class_memory); 6451 %} 6452 6453 // Store Compressed Oop 6454 instruct storeN(memory dst, iRegN_P2N src) %{ 6455 match(Set dst (StoreN dst src)); 6456 ins_cost(MEMORY_REF_COST); 6457 6458 format %{ "STW $src, $dst \t// compressed oop" %} 6459 size(4); 6460 ins_encode( enc_stw(src, dst) ); 6461 ins_pipe(pipe_class_memory); 6462 %} 6463 6464 // Store Compressed KLass 6465 instruct storeNKlass(memory dst, iRegN_P2N src) %{ 6466 match(Set dst (StoreNKlass dst src)); 6467 ins_cost(MEMORY_REF_COST); 6468 6469 format %{ "STW $src, $dst \t// compressed klass" %} 6470 size(4); 6471 ins_encode( enc_stw(src, dst) ); 6472 ins_pipe(pipe_class_memory); 6473 %} 6474 6475 // Store Pointer 6476 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ 6477 match(Set dst (StoreP dst src)); 6478 ins_cost(MEMORY_REF_COST); 6479 6480 format %{ "STD $src, $dst \t// ptr" %} 6481 size(4); 6482 ins_encode( enc_std(src, dst) ); 6483 ins_pipe(pipe_class_memory); 6484 %} 6485 6486 // Store Float 6487 instruct storeF(memory mem, regF src) %{ 6488 match(Set mem (StoreF mem src)); 6489 ins_cost(MEMORY_REF_COST); 6490 6491 format %{ "STFS $src, $mem" %} 6492 size(4); 6493 ins_encode( enc_stfs(src, mem) ); 6494 ins_pipe(pipe_class_memory); 6495 %} 6496 6497 // Store Double 6498 instruct storeD(memory mem, regD src) %{ 6499 match(Set mem (StoreD mem src)); 6500 ins_cost(MEMORY_REF_COST); 6501 6502 format %{ "STFD $src, $mem" %} 6503 size(4); 6504 ins_encode( enc_stfd(src, mem) ); 6505 ins_pipe(pipe_class_memory); 6506 %} 6507 6508 //----------Store Instructions With Zeros-------------------------------------- 6509 6510 // Card-mark for CMS garbage collection. 6511 // This cardmark does an optimization so that it must not always 6512 // do a releasing store. For this, it gets the address of 6513 // CMSCollectorCardTableModRefBSExt::_requires_release as input. 6514 // (Using releaseFieldAddr in the match rule is a hack.) 6515 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{ 6516 match(Set mem (StoreCM mem releaseFieldAddr)); 6517 effect(TEMP crx); 6518 predicate(false); 6519 ins_cost(MEMORY_REF_COST); 6520 6521 // See loadConP. 6522 ins_cannot_rematerialize(true); 6523 6524 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} 6525 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) ); 6526 ins_pipe(pipe_class_memory); 6527 %} 6528 6529 // Card-mark for CMS garbage collection. 6530 // This cardmark does an optimization so that it must not always 6531 // do a releasing store. For this, it needs the constant address of 6532 // CMSCollectorCardTableModRefBSExt::_requires_release. 6533 // This constant address is split off here by expand so we can use 6534 // adlc / matcher functionality to load it from the constant section. 6535 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ 6536 match(Set mem (StoreCM mem zero)); 6537 predicate(UseConcMarkSweepGC); 6538 6539 expand %{ 6540 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} 6541 iRegLdst releaseFieldAddress; 6542 flagsReg crx; 6543 loadConL_Ex(releaseFieldAddress, baseImm); 6544 storeCM_CMS(mem, releaseFieldAddress, crx); 6545 %} 6546 %} 6547 6548 instruct storeCM_G1(memory mem, immI_0 zero) %{ 6549 match(Set mem (StoreCM mem zero)); 6550 predicate(UseG1GC); 6551 ins_cost(MEMORY_REF_COST); 6552 6553 ins_cannot_rematerialize(true); 6554 6555 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} 6556 size(8); 6557 ins_encode %{ 6558 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6559 __ li(R0, 0); 6560 //__ release(); // G1: oops are allowed to get visible after dirty marking 6561 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); 6562 __ stb(R0, $mem$$disp, $mem$$base$$Register); 6563 %} 6564 ins_pipe(pipe_class_memory); 6565 %} 6566 6567 // Convert oop pointer into compressed form. 6568 6569 // Nodes for postalloc expand. 6570 6571 // Shift node for expand. 6572 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ 6573 // The match rule is needed to make it a 'MachTypeNode'! 6574 match(Set dst (EncodeP src)); 6575 predicate(false); 6576 6577 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6578 size(4); 6579 ins_encode %{ 6580 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6581 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6582 %} 6583 ins_pipe(pipe_class_default); 6584 %} 6585 6586 // Add node for expand. 6587 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ 6588 // The match rule is needed to make it a 'MachTypeNode'! 6589 match(Set dst (EncodeP src)); 6590 predicate(false); 6591 6592 format %{ "SUB $dst, $src, oop_base \t// encode" %} 6593 ins_encode %{ 6594 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6595 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6596 %} 6597 ins_pipe(pipe_class_default); 6598 %} 6599 6600 // Conditional sub base. 6601 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6602 // The match rule is needed to make it a 'MachTypeNode'! 6603 match(Set dst (EncodeP (Binary crx src1))); 6604 predicate(false); 6605 6606 format %{ "BEQ $crx, done\n\t" 6607 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n" 6608 "done:" %} 6609 ins_encode %{ 6610 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6611 Label done; 6612 __ beq($crx$$CondRegister, done); 6613 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0); 6614 __ bind(done); 6615 %} 6616 ins_pipe(pipe_class_default); 6617 %} 6618 6619 // Power 7 can use isel instruction 6620 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6621 // The match rule is needed to make it a 'MachTypeNode'! 6622 match(Set dst (EncodeP (Binary crx src1))); 6623 predicate(false); 6624 6625 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} 6626 size(4); 6627 ins_encode %{ 6628 // This is a Power7 instruction for which no machine description exists. 6629 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6630 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6631 %} 6632 ins_pipe(pipe_class_default); 6633 %} 6634 6635 // Disjoint narrow oop base. 6636 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{ 6637 match(Set dst (EncodeP src)); 6638 predicate(Universe::narrow_oop_base_disjoint()); 6639 6640 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 6641 size(4); 6642 ins_encode %{ 6643 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6644 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 6645 %} 6646 ins_pipe(pipe_class_default); 6647 %} 6648 6649 // shift != 0, base != 0 6650 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ 6651 match(Set dst (EncodeP src)); 6652 effect(TEMP crx); 6653 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && 6654 Universe::narrow_oop_shift() != 0 && 6655 Universe::narrow_oop_base_overlaps()); 6656 6657 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} 6658 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); 6659 %} 6660 6661 // shift != 0, base != 0 6662 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ 6663 match(Set dst (EncodeP src)); 6664 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && 6665 Universe::narrow_oop_shift() != 0 && 6666 Universe::narrow_oop_base_overlaps()); 6667 6668 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} 6669 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); 6670 %} 6671 6672 // shift != 0, base == 0 6673 // TODO: This is the same as encodeP_shift. Merge! 6674 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ 6675 match(Set dst (EncodeP src)); 6676 predicate(Universe::narrow_oop_shift() != 0 && 6677 Universe::narrow_oop_base() ==0); 6678 6679 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} 6680 size(4); 6681 ins_encode %{ 6682 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6683 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6684 %} 6685 ins_pipe(pipe_class_default); 6686 %} 6687 6688 // Compressed OOPs with narrow_oop_shift == 0. 6689 // shift == 0, base == 0 6690 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ 6691 match(Set dst (EncodeP src)); 6692 predicate(Universe::narrow_oop_shift() == 0); 6693 6694 format %{ "MR $dst, $src \t// Ptr->Narrow" %} 6695 // variable size, 0 or 4. 6696 ins_encode %{ 6697 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6698 __ mr_if_needed($dst$$Register, $src$$Register); 6699 %} 6700 ins_pipe(pipe_class_default); 6701 %} 6702 6703 // Decode nodes. 6704 6705 // Shift node for expand. 6706 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ 6707 // The match rule is needed to make it a 'MachTypeNode'! 6708 match(Set dst (DecodeN src)); 6709 predicate(false); 6710 6711 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} 6712 size(4); 6713 ins_encode %{ 6714 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6715 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6716 %} 6717 ins_pipe(pipe_class_default); 6718 %} 6719 6720 // Add node for expand. 6721 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ 6722 // The match rule is needed to make it a 'MachTypeNode'! 6723 match(Set dst (DecodeN src)); 6724 predicate(false); 6725 6726 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %} 6727 ins_encode %{ 6728 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6729 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6730 %} 6731 ins_pipe(pipe_class_default); 6732 %} 6733 6734 // conditianal add base for expand 6735 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{ 6736 // The match rule is needed to make it a 'MachTypeNode'! 6737 // NOTICE that the rule is nonsense - we just have to make sure that: 6738 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6739 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6740 match(Set dst (DecodeN (Binary crx src))); 6741 predicate(false); 6742 6743 format %{ "BEQ $crx, done\n\t" 6744 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n" 6745 "done:" %} 6746 ins_encode %{ 6747 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6748 Label done; 6749 __ beq($crx$$CondRegister, done); 6750 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6751 __ bind(done); 6752 %} 6753 ins_pipe(pipe_class_default); 6754 %} 6755 6756 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6757 // The match rule is needed to make it a 'MachTypeNode'! 6758 // NOTICE that the rule is nonsense - we just have to make sure that: 6759 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6760 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6761 match(Set dst (DecodeN (Binary crx src1))); 6762 predicate(false); 6763 6764 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} 6765 size(4); 6766 ins_encode %{ 6767 // This is a Power7 instruction for which no machine description exists. 6768 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6769 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6770 %} 6771 ins_pipe(pipe_class_default); 6772 %} 6773 6774 // shift != 0, base != 0 6775 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6776 match(Set dst (DecodeN src)); 6777 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6778 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6779 Universe::narrow_oop_shift() != 0 && 6780 Universe::narrow_oop_base() != 0); 6781 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex. 6782 effect(TEMP crx); 6783 6784 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} 6785 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); 6786 %} 6787 6788 // shift != 0, base == 0 6789 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ 6790 match(Set dst (DecodeN src)); 6791 predicate(Universe::narrow_oop_shift() != 0 && 6792 Universe::narrow_oop_base() == 0); 6793 6794 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} 6795 size(4); 6796 ins_encode %{ 6797 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6798 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6799 %} 6800 ins_pipe(pipe_class_default); 6801 %} 6802 6803 // Optimize DecodeN for disjoint base. 6804 // Shift narrow oop and or it into register that already contains the heap base. 6805 // Base == dst must hold, and is assured by construction in postaloc_expand. 6806 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{ 6807 match(Set dst (DecodeN src)); 6808 effect(TEMP base); 6809 predicate(false); 6810 6811 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %} 6812 size(4); 6813 ins_encode %{ 6814 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 6815 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift()); 6816 %} 6817 ins_pipe(pipe_class_default); 6818 %} 6819 6820 // Optimize DecodeN for disjoint base. 6821 // This node requires only one cycle on the critical path. 6822 // We must postalloc_expand as we can not express use_def effects where 6823 // the used register is L and the def'ed register P. 6824 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{ 6825 match(Set dst (DecodeN src)); 6826 effect(TEMP_DEF dst); 6827 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6828 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6829 Universe::narrow_oop_base_disjoint()); 6830 ins_cost(DEFAULT_COST); 6831 6832 format %{ "MOV $dst, heapbase \t\n" 6833 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %} 6834 postalloc_expand %{ 6835 loadBaseNode *n1 = new loadBaseNode(); 6836 n1->add_req(NULL); 6837 n1->_opnds[0] = op_dst; 6838 6839 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6840 n2->add_req(n_region, n_src, n1); 6841 n2->_opnds[0] = op_dst; 6842 n2->_opnds[1] = op_src; 6843 n2->_opnds[2] = op_dst; 6844 n2->_bottom_type = _bottom_type; 6845 6846 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6847 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6848 6849 nodes->push(n1); 6850 nodes->push(n2); 6851 %} 6852 %} 6853 6854 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6855 match(Set dst (DecodeN src)); 6856 effect(TEMP_DEF dst, TEMP crx); 6857 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6858 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6859 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel()); 6860 ins_cost(3 * DEFAULT_COST); 6861 6862 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %} 6863 postalloc_expand %{ 6864 loadBaseNode *n1 = new loadBaseNode(); 6865 n1->add_req(NULL); 6866 n1->_opnds[0] = op_dst; 6867 6868 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 6869 n_compare->add_req(n_region, n_src); 6870 n_compare->_opnds[0] = op_crx; 6871 n_compare->_opnds[1] = op_src; 6872 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 6873 6874 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6875 n2->add_req(n_region, n_src, n1); 6876 n2->_opnds[0] = op_dst; 6877 n2->_opnds[1] = op_src; 6878 n2->_opnds[2] = op_dst; 6879 n2->_bottom_type = _bottom_type; 6880 6881 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 6882 n_cond_set->add_req(n_region, n_compare, n2); 6883 n_cond_set->_opnds[0] = op_dst; 6884 n_cond_set->_opnds[1] = op_crx; 6885 n_cond_set->_opnds[2] = op_dst; 6886 n_cond_set->_bottom_type = _bottom_type; 6887 6888 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 6889 ra_->set_oop(n_cond_set, true); 6890 6891 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6892 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 6893 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6894 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6895 6896 nodes->push(n1); 6897 nodes->push(n_compare); 6898 nodes->push(n2); 6899 nodes->push(n_cond_set); 6900 %} 6901 %} 6902 6903 // src != 0, shift != 0, base != 0 6904 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ 6905 match(Set dst (DecodeN src)); 6906 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6907 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6908 Universe::narrow_oop_shift() != 0 && 6909 Universe::narrow_oop_base() != 0); 6910 ins_cost(2 * DEFAULT_COST); 6911 6912 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} 6913 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); 6914 %} 6915 6916 // Compressed OOPs with narrow_oop_shift == 0. 6917 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ 6918 match(Set dst (DecodeN src)); 6919 predicate(Universe::narrow_oop_shift() == 0); 6920 ins_cost(DEFAULT_COST); 6921 6922 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} 6923 // variable size, 0 or 4. 6924 ins_encode %{ 6925 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6926 __ mr_if_needed($dst$$Register, $src$$Register); 6927 %} 6928 ins_pipe(pipe_class_default); 6929 %} 6930 6931 // Convert compressed oop into int for vectors alignment masking. 6932 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ 6933 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); 6934 predicate(Universe::narrow_oop_shift() == 0); 6935 ins_cost(DEFAULT_COST); 6936 6937 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} 6938 // variable size, 0 or 4. 6939 ins_encode %{ 6940 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6941 __ mr_if_needed($dst$$Register, $src$$Register); 6942 %} 6943 ins_pipe(pipe_class_default); 6944 %} 6945 6946 // Convert klass pointer into compressed form. 6947 6948 // Nodes for postalloc expand. 6949 6950 // Shift node for expand. 6951 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ 6952 // The match rule is needed to make it a 'MachTypeNode'! 6953 match(Set dst (EncodePKlass src)); 6954 predicate(false); 6955 6956 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6957 size(4); 6958 ins_encode %{ 6959 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6960 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 6961 %} 6962 ins_pipe(pipe_class_default); 6963 %} 6964 6965 // Add node for expand. 6966 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 6967 // The match rule is needed to make it a 'MachTypeNode'! 6968 match(Set dst (EncodePKlass (Binary base src))); 6969 predicate(false); 6970 6971 format %{ "SUB $dst, $base, $src \t// encode" %} 6972 size(4); 6973 ins_encode %{ 6974 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 6975 __ subf($dst$$Register, $base$$Register, $src$$Register); 6976 %} 6977 ins_pipe(pipe_class_default); 6978 %} 6979 6980 // Disjoint narrow oop base. 6981 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{ 6982 match(Set dst (EncodePKlass src)); 6983 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); 6984 6985 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 6986 size(4); 6987 ins_encode %{ 6988 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6989 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32); 6990 %} 6991 ins_pipe(pipe_class_default); 6992 %} 6993 6994 // shift != 0, base != 0 6995 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ 6996 match(Set dst (EncodePKlass (Binary base src))); 6997 predicate(false); 6998 6999 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7000 postalloc_expand %{ 7001 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode(); 7002 n1->add_req(n_region, n_base, n_src); 7003 n1->_opnds[0] = op_dst; 7004 n1->_opnds[1] = op_base; 7005 n1->_opnds[2] = op_src; 7006 n1->_bottom_type = _bottom_type; 7007 7008 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode(); 7009 n2->add_req(n_region, n1); 7010 n2->_opnds[0] = op_dst; 7011 n2->_opnds[1] = op_dst; 7012 n2->_bottom_type = _bottom_type; 7013 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7014 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7015 7016 nodes->push(n1); 7017 nodes->push(n2); 7018 %} 7019 %} 7020 7021 // shift != 0, base != 0 7022 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ 7023 match(Set dst (EncodePKlass src)); 7024 //predicate(Universe::narrow_klass_shift() != 0 && 7025 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); 7026 7027 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7028 ins_cost(DEFAULT_COST*2); // Don't count constant. 7029 expand %{ 7030 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} 7031 iRegLdst base; 7032 loadConL_Ex(base, baseImm); 7033 encodePKlass_not_null_Ex(dst, base, src); 7034 %} 7035 %} 7036 7037 // Decode nodes. 7038 7039 // Shift node for expand. 7040 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ 7041 // The match rule is needed to make it a 'MachTypeNode'! 7042 match(Set dst (DecodeNKlass src)); 7043 predicate(false); 7044 7045 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} 7046 size(4); 7047 ins_encode %{ 7048 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 7049 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7050 %} 7051 ins_pipe(pipe_class_default); 7052 %} 7053 7054 // Add node for expand. 7055 7056 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7057 // The match rule is needed to make it a 'MachTypeNode'! 7058 match(Set dst (DecodeNKlass (Binary base src))); 7059 predicate(false); 7060 7061 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} 7062 size(4); 7063 ins_encode %{ 7064 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7065 __ add($dst$$Register, $base$$Register, $src$$Register); 7066 %} 7067 ins_pipe(pipe_class_default); 7068 %} 7069 7070 // src != 0, shift != 0, base != 0 7071 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ 7072 match(Set dst (DecodeNKlass (Binary base src))); 7073 //effect(kill src); // We need a register for the immediate result after shifting. 7074 predicate(false); 7075 7076 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} 7077 postalloc_expand %{ 7078 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode(); 7079 n1->add_req(n_region, n_base, n_src); 7080 n1->_opnds[0] = op_dst; 7081 n1->_opnds[1] = op_base; 7082 n1->_opnds[2] = op_src; 7083 n1->_bottom_type = _bottom_type; 7084 7085 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode(); 7086 n2->add_req(n_region, n1); 7087 n2->_opnds[0] = op_dst; 7088 n2->_opnds[1] = op_dst; 7089 n2->_bottom_type = _bottom_type; 7090 7091 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7092 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7093 7094 nodes->push(n1); 7095 nodes->push(n2); 7096 %} 7097 %} 7098 7099 // src != 0, shift != 0, base != 0 7100 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ 7101 match(Set dst (DecodeNKlass src)); 7102 // predicate(Universe::narrow_klass_shift() != 0 && 7103 // Universe::narrow_klass_base() != 0); 7104 7105 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} 7106 7107 ins_cost(DEFAULT_COST*2); // Don't count constant. 7108 expand %{ 7109 // We add first, then we shift. Like this, we can get along with one register less. 7110 // But we have to load the base pre-shifted. 7111 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} 7112 iRegLdst base; 7113 loadConL_Ex(base, baseImm); 7114 decodeNKlass_notNull_addBase_Ex(dst, base, src); 7115 %} 7116 %} 7117 7118 //----------MemBar Instructions----------------------------------------------- 7119 // Memory barrier flavors 7120 7121 instruct membar_acquire() %{ 7122 match(LoadFence); 7123 ins_cost(4*MEMORY_REF_COST); 7124 7125 format %{ "MEMBAR-acquire" %} 7126 size(4); 7127 ins_encode %{ 7128 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7129 __ acquire(); 7130 %} 7131 ins_pipe(pipe_class_default); 7132 %} 7133 7134 instruct unnecessary_membar_acquire() %{ 7135 match(MemBarAcquire); 7136 ins_cost(0); 7137 7138 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} 7139 size(0); 7140 ins_encode( /*empty*/ ); 7141 ins_pipe(pipe_class_default); 7142 %} 7143 7144 instruct membar_acquire_lock() %{ 7145 match(MemBarAcquireLock); 7146 ins_cost(0); 7147 7148 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} 7149 size(0); 7150 ins_encode( /*empty*/ ); 7151 ins_pipe(pipe_class_default); 7152 %} 7153 7154 instruct membar_release() %{ 7155 match(MemBarRelease); 7156 match(StoreFence); 7157 ins_cost(4*MEMORY_REF_COST); 7158 7159 format %{ "MEMBAR-release" %} 7160 size(4); 7161 ins_encode %{ 7162 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7163 __ release(); 7164 %} 7165 ins_pipe(pipe_class_default); 7166 %} 7167 7168 instruct membar_storestore() %{ 7169 match(MemBarStoreStore); 7170 ins_cost(4*MEMORY_REF_COST); 7171 7172 format %{ "MEMBAR-store-store" %} 7173 size(4); 7174 ins_encode %{ 7175 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7176 __ membar(Assembler::StoreStore); 7177 %} 7178 ins_pipe(pipe_class_default); 7179 %} 7180 7181 instruct membar_release_lock() %{ 7182 match(MemBarReleaseLock); 7183 ins_cost(0); 7184 7185 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} 7186 size(0); 7187 ins_encode( /*empty*/ ); 7188 ins_pipe(pipe_class_default); 7189 %} 7190 7191 instruct membar_volatile() %{ 7192 match(MemBarVolatile); 7193 ins_cost(4*MEMORY_REF_COST); 7194 7195 format %{ "MEMBAR-volatile" %} 7196 size(4); 7197 ins_encode %{ 7198 // TODO: PPC port $archOpcode(ppc64Opcode_sync); 7199 __ fence(); 7200 %} 7201 ins_pipe(pipe_class_default); 7202 %} 7203 7204 // This optimization is wrong on PPC. The following pattern is not supported: 7205 // MemBarVolatile 7206 // ^ ^ 7207 // | | 7208 // CtrlProj MemProj 7209 // ^ ^ 7210 // | | 7211 // | Load 7212 // | 7213 // MemBarVolatile 7214 // 7215 // The first MemBarVolatile could get optimized out! According to 7216 // Vladimir, this pattern can not occur on Oracle platforms. 7217 // However, it does occur on PPC64 (because of membars in 7218 // inline_unsafe_load_store). 7219 // 7220 // Add this node again if we found a good solution for inline_unsafe_load_store(). 7221 // Don't forget to look at the implementation of post_store_load_barrier again, 7222 // we did other fixes in that method. 7223 //instruct unnecessary_membar_volatile() %{ 7224 // match(MemBarVolatile); 7225 // predicate(Matcher::post_store_load_barrier(n)); 7226 // ins_cost(0); 7227 // 7228 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %} 7229 // size(0); 7230 // ins_encode( /*empty*/ ); 7231 // ins_pipe(pipe_class_default); 7232 //%} 7233 7234 instruct membar_CPUOrder() %{ 7235 match(MemBarCPUOrder); 7236 ins_cost(0); 7237 7238 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} 7239 size(0); 7240 ins_encode( /*empty*/ ); 7241 ins_pipe(pipe_class_default); 7242 %} 7243 7244 //----------Conditional Move--------------------------------------------------- 7245 7246 // Cmove using isel. 7247 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{ 7248 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7249 predicate(VM_Version::has_isel()); 7250 ins_cost(DEFAULT_COST); 7251 7252 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7253 size(4); 7254 ins_encode %{ 7255 // This is a Power7 instruction for which no machine description 7256 // exists. Anyways, the scheduler should be off on Power7. 7257 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7258 int cc = $cmp$$cmpcode; 7259 __ isel($dst$$Register, $crx$$CondRegister, 7260 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7261 %} 7262 ins_pipe(pipe_class_default); 7263 %} 7264 7265 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{ 7266 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7267 predicate(!VM_Version::has_isel()); 7268 ins_cost(DEFAULT_COST+BRANCH_COST); 7269 7270 ins_variable_size_depending_on_alignment(true); 7271 7272 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7273 // Worst case is branch + move + stop, no stop without scheduler 7274 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7275 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7276 ins_pipe(pipe_class_default); 7277 %} 7278 7279 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{ 7280 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7281 ins_cost(DEFAULT_COST+BRANCH_COST); 7282 7283 ins_variable_size_depending_on_alignment(true); 7284 7285 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7286 // Worst case is branch + move + stop, no stop without scheduler 7287 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7288 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7289 ins_pipe(pipe_class_default); 7290 %} 7291 7292 // Cmove using isel. 7293 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{ 7294 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7295 predicate(VM_Version::has_isel()); 7296 ins_cost(DEFAULT_COST); 7297 7298 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7299 size(4); 7300 ins_encode %{ 7301 // This is a Power7 instruction for which no machine description 7302 // exists. Anyways, the scheduler should be off on Power7. 7303 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7304 int cc = $cmp$$cmpcode; 7305 __ isel($dst$$Register, $crx$$CondRegister, 7306 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7307 %} 7308 ins_pipe(pipe_class_default); 7309 %} 7310 7311 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{ 7312 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7313 predicate(!VM_Version::has_isel()); 7314 ins_cost(DEFAULT_COST+BRANCH_COST); 7315 7316 ins_variable_size_depending_on_alignment(true); 7317 7318 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7319 // Worst case is branch + move + stop, no stop without scheduler. 7320 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7321 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7322 ins_pipe(pipe_class_default); 7323 %} 7324 7325 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{ 7326 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7327 ins_cost(DEFAULT_COST+BRANCH_COST); 7328 7329 ins_variable_size_depending_on_alignment(true); 7330 7331 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7332 // Worst case is branch + move + stop, no stop without scheduler. 7333 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7334 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7335 ins_pipe(pipe_class_default); 7336 %} 7337 7338 // Cmove using isel. 7339 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{ 7340 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7341 predicate(VM_Version::has_isel()); 7342 ins_cost(DEFAULT_COST); 7343 7344 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7345 size(4); 7346 ins_encode %{ 7347 // This is a Power7 instruction for which no machine description 7348 // exists. Anyways, the scheduler should be off on Power7. 7349 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7350 int cc = $cmp$$cmpcode; 7351 __ isel($dst$$Register, $crx$$CondRegister, 7352 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7353 %} 7354 ins_pipe(pipe_class_default); 7355 %} 7356 7357 // Conditional move for RegN. Only cmov(reg, reg). 7358 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{ 7359 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7360 predicate(!VM_Version::has_isel()); 7361 ins_cost(DEFAULT_COST+BRANCH_COST); 7362 7363 ins_variable_size_depending_on_alignment(true); 7364 7365 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7366 // Worst case is branch + move + stop, no stop without scheduler. 7367 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7368 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7369 ins_pipe(pipe_class_default); 7370 %} 7371 7372 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{ 7373 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7374 ins_cost(DEFAULT_COST+BRANCH_COST); 7375 7376 ins_variable_size_depending_on_alignment(true); 7377 7378 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7379 // Worst case is branch + move + stop, no stop without scheduler. 7380 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7381 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7382 ins_pipe(pipe_class_default); 7383 %} 7384 7385 // Cmove using isel. 7386 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{ 7387 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7388 predicate(VM_Version::has_isel()); 7389 ins_cost(DEFAULT_COST); 7390 7391 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7392 size(4); 7393 ins_encode %{ 7394 // This is a Power7 instruction for which no machine description 7395 // exists. Anyways, the scheduler should be off on Power7. 7396 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7397 int cc = $cmp$$cmpcode; 7398 __ isel($dst$$Register, $crx$$CondRegister, 7399 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7400 %} 7401 ins_pipe(pipe_class_default); 7402 %} 7403 7404 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{ 7405 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7406 predicate(!VM_Version::has_isel()); 7407 ins_cost(DEFAULT_COST+BRANCH_COST); 7408 7409 ins_variable_size_depending_on_alignment(true); 7410 7411 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7412 // Worst case is branch + move + stop, no stop without scheduler. 7413 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7414 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7415 ins_pipe(pipe_class_default); 7416 %} 7417 7418 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{ 7419 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7420 ins_cost(DEFAULT_COST+BRANCH_COST); 7421 7422 ins_variable_size_depending_on_alignment(true); 7423 7424 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7425 // Worst case is branch + move + stop, no stop without scheduler. 7426 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7427 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7428 ins_pipe(pipe_class_default); 7429 %} 7430 7431 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{ 7432 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); 7433 ins_cost(DEFAULT_COST+BRANCH_COST); 7434 7435 ins_variable_size_depending_on_alignment(true); 7436 7437 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7438 // Worst case is branch + move + stop, no stop without scheduler. 7439 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7440 ins_encode %{ 7441 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7442 Label done; 7443 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7444 // Branch if not (cmp crx). 7445 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7446 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7447 // TODO PPC port __ endgroup_if_needed(_size == 12); 7448 __ bind(done); 7449 %} 7450 ins_pipe(pipe_class_default); 7451 %} 7452 7453 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{ 7454 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); 7455 ins_cost(DEFAULT_COST+BRANCH_COST); 7456 7457 ins_variable_size_depending_on_alignment(true); 7458 7459 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7460 // Worst case is branch + move + stop, no stop without scheduler. 7461 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7462 ins_encode %{ 7463 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7464 Label done; 7465 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7466 // Branch if not (cmp crx). 7467 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7468 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7469 // TODO PPC port __ endgroup_if_needed(_size == 12); 7470 __ bind(done); 7471 %} 7472 ins_pipe(pipe_class_default); 7473 %} 7474 7475 //----------Conditional_store-------------------------------------------------- 7476 // Conditional-store of the updated heap-top. 7477 // Used during allocation of the shared heap. 7478 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7479 7480 // As compareAndSwapL, but return flag register instead of boolean value in 7481 // int register. 7482 // Used by sun/misc/AtomicLongCSImpl.java. 7483 // Mem_ptr must be a memory operand, else this node does not get 7484 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7485 // can be rematerialized which leads to errors. 7486 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{ 7487 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); 7488 effect(TEMP cr0); 7489 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7490 ins_encode %{ 7491 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7492 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7493 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(), 7494 noreg, NULL, true); 7495 %} 7496 ins_pipe(pipe_class_default); 7497 %} 7498 7499 // As compareAndSwapP, but return flag register instead of boolean value in 7500 // int register. 7501 // This instruction is matched if UseTLAB is off. 7502 // Mem_ptr must be a memory operand, else this node does not get 7503 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7504 // can be rematerialized which leads to errors. 7505 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ 7506 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal))); 7507 ins_cost(2*MEMORY_REF_COST); 7508 7509 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7510 ins_encode %{ 7511 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_); 7512 __ stdcx_($newVal$$Register, $mem_ptr$$Register); 7513 %} 7514 ins_pipe(pipe_class_memory); 7515 %} 7516 7517 // Implement LoadPLocked. Must be ordered against changes of the memory location 7518 // by storePConditional. 7519 // Don't know whether this is ever used. 7520 instruct loadPLocked(iRegPdst dst, memory mem) %{ 7521 match(Set dst (LoadPLocked mem)); 7522 ins_cost(2*MEMORY_REF_COST); 7523 7524 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %} 7525 size(4); 7526 ins_encode %{ 7527 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx); 7528 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update()); 7529 %} 7530 ins_pipe(pipe_class_memory); 7531 %} 7532 7533 //----------Compare-And-Swap--------------------------------------------------- 7534 7535 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI 7536 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be 7537 // matched. 7538 7539 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{ 7540 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); 7541 effect(TEMP cr0); 7542 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7543 // Variable size: instruction count smaller if regs are disjoint. 7544 ins_encode %{ 7545 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7546 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7547 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7548 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7549 $res$$Register, true); 7550 %} 7551 ins_pipe(pipe_class_default); 7552 %} 7553 7554 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{ 7555 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); 7556 effect(TEMP cr0); 7557 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7558 // Variable size: instruction count smaller if regs are disjoint. 7559 ins_encode %{ 7560 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7561 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7562 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7563 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7564 $res$$Register, true); 7565 %} 7566 ins_pipe(pipe_class_default); 7567 %} 7568 7569 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ 7570 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); 7571 effect(TEMP cr0); 7572 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} 7573 // Variable size: instruction count smaller if regs are disjoint. 7574 ins_encode %{ 7575 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7576 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7577 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7578 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7579 $res$$Register, NULL, true); 7580 %} 7581 ins_pipe(pipe_class_default); 7582 %} 7583 7584 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{ 7585 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); 7586 effect(TEMP cr0); 7587 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} 7588 // Variable size: instruction count smaller if regs are disjoint. 7589 ins_encode %{ 7590 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7591 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7592 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7593 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7594 $res$$Register, NULL, true); 7595 %} 7596 ins_pipe(pipe_class_default); 7597 %} 7598 7599 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{ 7600 match(Set res (GetAndAddI mem_ptr src)); 7601 effect(TEMP cr0); 7602 format %{ "GetAndAddI $res, $mem_ptr, $src" %} 7603 // Variable size: instruction count smaller if regs are disjoint. 7604 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); 7605 ins_pipe(pipe_class_default); 7606 %} 7607 7608 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{ 7609 match(Set res (GetAndAddL mem_ptr src)); 7610 effect(TEMP cr0); 7611 format %{ "GetAndAddL $res, $mem_ptr, $src" %} 7612 // Variable size: instruction count smaller if regs are disjoint. 7613 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); 7614 ins_pipe(pipe_class_default); 7615 %} 7616 7617 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{ 7618 match(Set res (GetAndSetI mem_ptr src)); 7619 effect(TEMP cr0); 7620 format %{ "GetAndSetI $res, $mem_ptr, $src" %} 7621 // Variable size: instruction count smaller if regs are disjoint. 7622 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7623 ins_pipe(pipe_class_default); 7624 %} 7625 7626 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{ 7627 match(Set res (GetAndSetL mem_ptr src)); 7628 effect(TEMP cr0); 7629 format %{ "GetAndSetL $res, $mem_ptr, $src" %} 7630 // Variable size: instruction count smaller if regs are disjoint. 7631 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7632 ins_pipe(pipe_class_default); 7633 %} 7634 7635 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{ 7636 match(Set res (GetAndSetP mem_ptr src)); 7637 effect(TEMP cr0); 7638 format %{ "GetAndSetP $res, $mem_ptr, $src" %} 7639 // Variable size: instruction count smaller if regs are disjoint. 7640 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7641 ins_pipe(pipe_class_default); 7642 %} 7643 7644 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{ 7645 match(Set res (GetAndSetN mem_ptr src)); 7646 effect(TEMP cr0); 7647 format %{ "GetAndSetN $res, $mem_ptr, $src" %} 7648 // Variable size: instruction count smaller if regs are disjoint. 7649 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7650 ins_pipe(pipe_class_default); 7651 %} 7652 7653 //----------Arithmetic Instructions-------------------------------------------- 7654 // Addition Instructions 7655 7656 // Register Addition 7657 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ 7658 match(Set dst (AddI src1 src2)); 7659 format %{ "ADD $dst, $src1, $src2" %} 7660 size(4); 7661 ins_encode %{ 7662 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7663 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7664 %} 7665 ins_pipe(pipe_class_default); 7666 %} 7667 7668 // Expand does not work with above instruct. (??) 7669 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7670 // no match-rule 7671 effect(DEF dst, USE src1, USE src2); 7672 format %{ "ADD $dst, $src1, $src2" %} 7673 size(4); 7674 ins_encode %{ 7675 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7676 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7677 %} 7678 ins_pipe(pipe_class_default); 7679 %} 7680 7681 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 7682 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); 7683 ins_cost(DEFAULT_COST*3); 7684 7685 expand %{ 7686 // FIXME: we should do this in the ideal world. 7687 iRegIdst tmp1; 7688 iRegIdst tmp2; 7689 addI_reg_reg(tmp1, src1, src2); 7690 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. 7691 addI_reg_reg(dst, tmp1, tmp2); 7692 %} 7693 %} 7694 7695 // Immediate Addition 7696 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7697 match(Set dst (AddI src1 src2)); 7698 format %{ "ADDI $dst, $src1, $src2" %} 7699 size(4); 7700 ins_encode %{ 7701 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7702 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7703 %} 7704 ins_pipe(pipe_class_default); 7705 %} 7706 7707 // Immediate Addition with 16-bit shifted operand 7708 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ 7709 match(Set dst (AddI src1 src2)); 7710 format %{ "ADDIS $dst, $src1, $src2" %} 7711 size(4); 7712 ins_encode %{ 7713 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7714 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7715 %} 7716 ins_pipe(pipe_class_default); 7717 %} 7718 7719 // Long Addition 7720 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7721 match(Set dst (AddL src1 src2)); 7722 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7723 size(4); 7724 ins_encode %{ 7725 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7726 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7727 %} 7728 ins_pipe(pipe_class_default); 7729 %} 7730 7731 // Expand does not work with above instruct. (??) 7732 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7733 // no match-rule 7734 effect(DEF dst, USE src1, USE src2); 7735 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7736 size(4); 7737 ins_encode %{ 7738 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7739 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7740 %} 7741 ins_pipe(pipe_class_default); 7742 %} 7743 7744 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ 7745 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); 7746 ins_cost(DEFAULT_COST*3); 7747 7748 expand %{ 7749 // FIXME: we should do this in the ideal world. 7750 iRegLdst tmp1; 7751 iRegLdst tmp2; 7752 addL_reg_reg(tmp1, src1, src2); 7753 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 7754 addL_reg_reg(dst, tmp1, tmp2); 7755 %} 7756 %} 7757 7758 // AddL + ConvL2I. 7759 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7760 match(Set dst (ConvL2I (AddL src1 src2))); 7761 7762 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} 7763 size(4); 7764 ins_encode %{ 7765 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7766 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7767 %} 7768 ins_pipe(pipe_class_default); 7769 %} 7770 7771 // No constant pool entries required. 7772 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7773 match(Set dst (AddL src1 src2)); 7774 7775 format %{ "ADDI $dst, $src1, $src2" %} 7776 size(4); 7777 ins_encode %{ 7778 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7779 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7780 %} 7781 ins_pipe(pipe_class_default); 7782 %} 7783 7784 // Long Immediate Addition with 16-bit shifted operand. 7785 // No constant pool entries required. 7786 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ 7787 match(Set dst (AddL src1 src2)); 7788 7789 format %{ "ADDIS $dst, $src1, $src2" %} 7790 size(4); 7791 ins_encode %{ 7792 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7793 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7794 %} 7795 ins_pipe(pipe_class_default); 7796 %} 7797 7798 // Pointer Register Addition 7799 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ 7800 match(Set dst (AddP src1 src2)); 7801 format %{ "ADD $dst, $src1, $src2" %} 7802 size(4); 7803 ins_encode %{ 7804 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7805 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7806 %} 7807 ins_pipe(pipe_class_default); 7808 %} 7809 7810 // Pointer Immediate Addition 7811 // No constant pool entries required. 7812 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ 7813 match(Set dst (AddP src1 src2)); 7814 7815 format %{ "ADDI $dst, $src1, $src2" %} 7816 size(4); 7817 ins_encode %{ 7818 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7819 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7820 %} 7821 ins_pipe(pipe_class_default); 7822 %} 7823 7824 // Pointer Immediate Addition with 16-bit shifted operand. 7825 // No constant pool entries required. 7826 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ 7827 match(Set dst (AddP src1 src2)); 7828 7829 format %{ "ADDIS $dst, $src1, $src2" %} 7830 size(4); 7831 ins_encode %{ 7832 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7833 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7834 %} 7835 ins_pipe(pipe_class_default); 7836 %} 7837 7838 //--------------------- 7839 // Subtraction Instructions 7840 7841 // Register Subtraction 7842 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7843 match(Set dst (SubI src1 src2)); 7844 format %{ "SUBF $dst, $src2, $src1" %} 7845 size(4); 7846 ins_encode %{ 7847 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7848 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7849 %} 7850 ins_pipe(pipe_class_default); 7851 %} 7852 7853 // Immediate Subtraction 7854 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), 7855 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16. 7856 7857 // SubI from constant (using subfic). 7858 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ 7859 match(Set dst (SubI src1 src2)); 7860 format %{ "SUBI $dst, $src1, $src2" %} 7861 7862 size(4); 7863 ins_encode %{ 7864 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); 7865 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); 7866 %} 7867 ins_pipe(pipe_class_default); 7868 %} 7869 7870 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for 7871 // positive integers and 0xF...F for negative ones. 7872 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ 7873 // no match-rule, false predicate 7874 effect(DEF dst, USE src); 7875 predicate(false); 7876 7877 format %{ "SRAWI $dst, $src, #31" %} 7878 size(4); 7879 ins_encode %{ 7880 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 7881 __ srawi($dst$$Register, $src$$Register, 0x1f); 7882 %} 7883 ins_pipe(pipe_class_default); 7884 %} 7885 7886 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ 7887 match(Set dst (AbsI src)); 7888 ins_cost(DEFAULT_COST*3); 7889 7890 expand %{ 7891 iRegIdst tmp1; 7892 iRegIdst tmp2; 7893 signmask32I_regI(tmp1, src); 7894 xorI_reg_reg(tmp2, tmp1, src); 7895 subI_reg_reg(dst, tmp2, tmp1); 7896 %} 7897 %} 7898 7899 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ 7900 match(Set dst (SubI zero src2)); 7901 format %{ "NEG $dst, $src2" %} 7902 size(4); 7903 ins_encode %{ 7904 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7905 __ neg($dst$$Register, $src2$$Register); 7906 %} 7907 ins_pipe(pipe_class_default); 7908 %} 7909 7910 // Long subtraction 7911 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7912 match(Set dst (SubL src1 src2)); 7913 format %{ "SUBF $dst, $src2, $src1 \t// long" %} 7914 size(4); 7915 ins_encode %{ 7916 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7917 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7918 %} 7919 ins_pipe(pipe_class_default); 7920 %} 7921 7922 // SubL + convL2I. 7923 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7924 match(Set dst (ConvL2I (SubL src1 src2))); 7925 7926 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} 7927 size(4); 7928 ins_encode %{ 7929 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7930 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7931 %} 7932 ins_pipe(pipe_class_default); 7933 %} 7934 7935 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7936 // positive longs and 0xF...F for negative ones. 7937 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{ 7938 // no match-rule, false predicate 7939 effect(DEF dst, USE src); 7940 predicate(false); 7941 7942 format %{ "SRADI $dst, $src, #63" %} 7943 size(4); 7944 ins_encode %{ 7945 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7946 __ sradi($dst$$Register, $src$$Register, 0x3f); 7947 %} 7948 ins_pipe(pipe_class_default); 7949 %} 7950 7951 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7952 // positive longs and 0xF...F for negative ones. 7953 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{ 7954 // no match-rule, false predicate 7955 effect(DEF dst, USE src); 7956 predicate(false); 7957 7958 format %{ "SRADI $dst, $src, #63" %} 7959 size(4); 7960 ins_encode %{ 7961 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7962 __ sradi($dst$$Register, $src$$Register, 0x3f); 7963 %} 7964 ins_pipe(pipe_class_default); 7965 %} 7966 7967 // Long negation 7968 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ 7969 match(Set dst (SubL zero src2)); 7970 format %{ "NEG $dst, $src2 \t// long" %} 7971 size(4); 7972 ins_encode %{ 7973 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7974 __ neg($dst$$Register, $src2$$Register); 7975 %} 7976 ins_pipe(pipe_class_default); 7977 %} 7978 7979 // NegL + ConvL2I. 7980 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ 7981 match(Set dst (ConvL2I (SubL zero src2))); 7982 7983 format %{ "NEG $dst, $src2 \t// long + l2i" %} 7984 size(4); 7985 ins_encode %{ 7986 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7987 __ neg($dst$$Register, $src2$$Register); 7988 %} 7989 ins_pipe(pipe_class_default); 7990 %} 7991 7992 // Multiplication Instructions 7993 // Integer Multiplication 7994 7995 // Register Multiplication 7996 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7997 match(Set dst (MulI src1 src2)); 7998 ins_cost(DEFAULT_COST); 7999 8000 format %{ "MULLW $dst, $src1, $src2" %} 8001 size(4); 8002 ins_encode %{ 8003 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); 8004 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); 8005 %} 8006 ins_pipe(pipe_class_default); 8007 %} 8008 8009 // Immediate Multiplication 8010 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 8011 match(Set dst (MulI src1 src2)); 8012 ins_cost(DEFAULT_COST); 8013 8014 format %{ "MULLI $dst, $src1, $src2" %} 8015 size(4); 8016 ins_encode %{ 8017 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8018 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8019 %} 8020 ins_pipe(pipe_class_default); 8021 %} 8022 8023 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8024 match(Set dst (MulL src1 src2)); 8025 ins_cost(DEFAULT_COST); 8026 8027 format %{ "MULLD $dst $src1, $src2 \t// long" %} 8028 size(4); 8029 ins_encode %{ 8030 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); 8031 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); 8032 %} 8033 ins_pipe(pipe_class_default); 8034 %} 8035 8036 // Multiply high for optimized long division by constant. 8037 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8038 match(Set dst (MulHiL src1 src2)); 8039 ins_cost(DEFAULT_COST); 8040 8041 format %{ "MULHD $dst $src1, $src2 \t// long" %} 8042 size(4); 8043 ins_encode %{ 8044 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); 8045 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); 8046 %} 8047 ins_pipe(pipe_class_default); 8048 %} 8049 8050 // Immediate Multiplication 8051 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 8052 match(Set dst (MulL src1 src2)); 8053 ins_cost(DEFAULT_COST); 8054 8055 format %{ "MULLI $dst, $src1, $src2" %} 8056 size(4); 8057 ins_encode %{ 8058 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8059 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8060 %} 8061 ins_pipe(pipe_class_default); 8062 %} 8063 8064 // Integer Division with Immediate -1: Negate. 8065 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 8066 match(Set dst (DivI src1 src2)); 8067 ins_cost(DEFAULT_COST); 8068 8069 format %{ "NEG $dst, $src1 \t// /-1" %} 8070 size(4); 8071 ins_encode %{ 8072 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8073 __ neg($dst$$Register, $src1$$Register); 8074 %} 8075 ins_pipe(pipe_class_default); 8076 %} 8077 8078 // Integer Division with constant, but not -1. 8079 // We should be able to improve this by checking the type of src2. 8080 // It might well be that src2 is known to be positive. 8081 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8082 match(Set dst (DivI src1 src2)); 8083 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 8084 ins_cost(2*DEFAULT_COST); 8085 8086 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} 8087 size(4); 8088 ins_encode %{ 8089 // TODO: PPC port $archOpcode(ppc64Opcode_divw); 8090 __ divw($dst$$Register, $src1$$Register, $src2$$Register); 8091 %} 8092 ins_pipe(pipe_class_default); 8093 %} 8094 8095 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{ 8096 effect(USE_DEF dst, USE src1, USE crx); 8097 predicate(false); 8098 8099 ins_variable_size_depending_on_alignment(true); 8100 8101 format %{ "CMOVE $dst, neg($src1), $crx" %} 8102 // Worst case is branch + move + stop, no stop without scheduler. 8103 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8104 ins_encode %{ 8105 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8106 Label done; 8107 __ bne($crx$$CondRegister, done); 8108 __ neg($dst$$Register, $src1$$Register); 8109 // TODO PPC port __ endgroup_if_needed(_size == 12); 8110 __ bind(done); 8111 %} 8112 ins_pipe(pipe_class_default); 8113 %} 8114 8115 // Integer Division with Registers not containing constants. 8116 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8117 match(Set dst (DivI src1 src2)); 8118 ins_cost(10*DEFAULT_COST); 8119 8120 expand %{ 8121 immI16 imm %{ (int)-1 %} 8122 flagsReg tmp1; 8123 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8124 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8125 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8126 %} 8127 %} 8128 8129 // Long Division with Immediate -1: Negate. 8130 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 8131 match(Set dst (DivL src1 src2)); 8132 ins_cost(DEFAULT_COST); 8133 8134 format %{ "NEG $dst, $src1 \t// /-1, long" %} 8135 size(4); 8136 ins_encode %{ 8137 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8138 __ neg($dst$$Register, $src1$$Register); 8139 %} 8140 ins_pipe(pipe_class_default); 8141 %} 8142 8143 // Long Division with constant, but not -1. 8144 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8145 match(Set dst (DivL src1 src2)); 8146 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. 8147 ins_cost(2*DEFAULT_COST); 8148 8149 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} 8150 size(4); 8151 ins_encode %{ 8152 // TODO: PPC port $archOpcode(ppc64Opcode_divd); 8153 __ divd($dst$$Register, $src1$$Register, $src2$$Register); 8154 %} 8155 ins_pipe(pipe_class_default); 8156 %} 8157 8158 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{ 8159 effect(USE_DEF dst, USE src1, USE crx); 8160 predicate(false); 8161 8162 ins_variable_size_depending_on_alignment(true); 8163 8164 format %{ "CMOVE $dst, neg($src1), $crx" %} 8165 // Worst case is branch + move + stop, no stop without scheduler. 8166 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8167 ins_encode %{ 8168 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8169 Label done; 8170 __ bne($crx$$CondRegister, done); 8171 __ neg($dst$$Register, $src1$$Register); 8172 // TODO PPC port __ endgroup_if_needed(_size == 12); 8173 __ bind(done); 8174 %} 8175 ins_pipe(pipe_class_default); 8176 %} 8177 8178 // Long Division with Registers not containing constants. 8179 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8180 match(Set dst (DivL src1 src2)); 8181 ins_cost(10*DEFAULT_COST); 8182 8183 expand %{ 8184 immL16 imm %{ (int)-1 %} 8185 flagsReg tmp1; 8186 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8187 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8188 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8189 %} 8190 %} 8191 8192 // Integer Remainder with registers. 8193 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8194 match(Set dst (ModI src1 src2)); 8195 ins_cost(10*DEFAULT_COST); 8196 8197 expand %{ 8198 immI16 imm %{ (int)-1 %} 8199 flagsReg tmp1; 8200 iRegIdst tmp2; 8201 iRegIdst tmp3; 8202 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8203 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8204 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8205 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8206 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8207 %} 8208 %} 8209 8210 // Long Remainder with registers 8211 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8212 match(Set dst (ModL src1 src2)); 8213 ins_cost(10*DEFAULT_COST); 8214 8215 expand %{ 8216 immL16 imm %{ (int)-1 %} 8217 flagsReg tmp1; 8218 iRegLdst tmp2; 8219 iRegLdst tmp3; 8220 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8221 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8222 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8223 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8224 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8225 %} 8226 %} 8227 8228 // Integer Shift Instructions 8229 8230 // Register Shift Left 8231 8232 // Clear all but the lowest #mask bits. 8233 // Used to normalize shift amounts in registers. 8234 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ 8235 // no match-rule, false predicate 8236 effect(DEF dst, USE src, USE mask); 8237 predicate(false); 8238 8239 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} 8240 size(4); 8241 ins_encode %{ 8242 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8243 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); 8244 %} 8245 ins_pipe(pipe_class_default); 8246 %} 8247 8248 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8249 // no match-rule, false predicate 8250 effect(DEF dst, USE src1, USE src2); 8251 predicate(false); 8252 8253 format %{ "SLW $dst, $src1, $src2" %} 8254 size(4); 8255 ins_encode %{ 8256 // TODO: PPC port $archOpcode(ppc64Opcode_slw); 8257 __ slw($dst$$Register, $src1$$Register, $src2$$Register); 8258 %} 8259 ins_pipe(pipe_class_default); 8260 %} 8261 8262 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8263 match(Set dst (LShiftI src1 src2)); 8264 ins_cost(DEFAULT_COST*2); 8265 expand %{ 8266 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8267 iRegIdst tmpI; 8268 maskI_reg_imm(tmpI, src2, mask); 8269 lShiftI_reg_reg(dst, src1, tmpI); 8270 %} 8271 %} 8272 8273 // Register Shift Left Immediate 8274 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8275 match(Set dst (LShiftI src1 src2)); 8276 8277 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} 8278 size(4); 8279 ins_encode %{ 8280 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8281 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8282 %} 8283 ins_pipe(pipe_class_default); 8284 %} 8285 8286 // AndI with negpow2-constant + LShiftI 8287 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8288 match(Set dst (LShiftI (AndI src1 src2) src3)); 8289 predicate(UseRotateAndMaskInstructionsPPC64); 8290 8291 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} 8292 size(4); 8293 ins_encode %{ 8294 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8295 long src2 = $src2$$constant; 8296 long src3 = $src3$$constant; 8297 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8298 if (maskbits >= 32) { 8299 __ li($dst$$Register, 0); // addi 8300 } else { 8301 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); 8302 } 8303 %} 8304 ins_pipe(pipe_class_default); 8305 %} 8306 8307 // RShiftI + AndI with negpow2-constant + LShiftI 8308 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8309 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); 8310 predicate(UseRotateAndMaskInstructionsPPC64); 8311 8312 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} 8313 size(4); 8314 ins_encode %{ 8315 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8316 long src2 = $src2$$constant; 8317 long src3 = $src3$$constant; 8318 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8319 if (maskbits >= 32) { 8320 __ li($dst$$Register, 0); // addi 8321 } else { 8322 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); 8323 } 8324 %} 8325 ins_pipe(pipe_class_default); 8326 %} 8327 8328 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8329 // no match-rule, false predicate 8330 effect(DEF dst, USE src1, USE src2); 8331 predicate(false); 8332 8333 format %{ "SLD $dst, $src1, $src2" %} 8334 size(4); 8335 ins_encode %{ 8336 // TODO: PPC port $archOpcode(ppc64Opcode_sld); 8337 __ sld($dst$$Register, $src1$$Register, $src2$$Register); 8338 %} 8339 ins_pipe(pipe_class_default); 8340 %} 8341 8342 // Register Shift Left 8343 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8344 match(Set dst (LShiftL src1 src2)); 8345 ins_cost(DEFAULT_COST*2); 8346 expand %{ 8347 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8348 iRegIdst tmpI; 8349 maskI_reg_imm(tmpI, src2, mask); 8350 lShiftL_regL_regI(dst, src1, tmpI); 8351 %} 8352 %} 8353 8354 // Register Shift Left Immediate 8355 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8356 match(Set dst (LShiftL src1 src2)); 8357 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} 8358 size(4); 8359 ins_encode %{ 8360 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8361 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8362 %} 8363 ins_pipe(pipe_class_default); 8364 %} 8365 8366 // If we shift more than 32 bits, we need not convert I2L. 8367 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ 8368 match(Set dst (LShiftL (ConvI2L src1) src2)); 8369 ins_cost(DEFAULT_COST); 8370 8371 size(4); 8372 format %{ "SLDI $dst, i2l($src1), $src2" %} 8373 ins_encode %{ 8374 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8375 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8376 %} 8377 ins_pipe(pipe_class_default); 8378 %} 8379 8380 // Shift a postivie int to the left. 8381 // Clrlsldi clears the upper 32 bits and shifts. 8382 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ 8383 match(Set dst (LShiftL (ConvI2L src1) src2)); 8384 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); 8385 8386 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} 8387 size(4); 8388 ins_encode %{ 8389 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); 8390 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); 8391 %} 8392 ins_pipe(pipe_class_default); 8393 %} 8394 8395 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8396 // no match-rule, false predicate 8397 effect(DEF dst, USE src1, USE src2); 8398 predicate(false); 8399 8400 format %{ "SRAW $dst, $src1, $src2" %} 8401 size(4); 8402 ins_encode %{ 8403 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); 8404 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); 8405 %} 8406 ins_pipe(pipe_class_default); 8407 %} 8408 8409 // Register Arithmetic Shift Right 8410 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8411 match(Set dst (RShiftI src1 src2)); 8412 ins_cost(DEFAULT_COST*2); 8413 expand %{ 8414 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8415 iRegIdst tmpI; 8416 maskI_reg_imm(tmpI, src2, mask); 8417 arShiftI_reg_reg(dst, src1, tmpI); 8418 %} 8419 %} 8420 8421 // Register Arithmetic Shift Right Immediate 8422 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8423 match(Set dst (RShiftI src1 src2)); 8424 8425 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} 8426 size(4); 8427 ins_encode %{ 8428 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 8429 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8430 %} 8431 ins_pipe(pipe_class_default); 8432 %} 8433 8434 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8435 // no match-rule, false predicate 8436 effect(DEF dst, USE src1, USE src2); 8437 predicate(false); 8438 8439 format %{ "SRAD $dst, $src1, $src2" %} 8440 size(4); 8441 ins_encode %{ 8442 // TODO: PPC port $archOpcode(ppc64Opcode_srad); 8443 __ srad($dst$$Register, $src1$$Register, $src2$$Register); 8444 %} 8445 ins_pipe(pipe_class_default); 8446 %} 8447 8448 // Register Shift Right Arithmetic Long 8449 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8450 match(Set dst (RShiftL src1 src2)); 8451 ins_cost(DEFAULT_COST*2); 8452 8453 expand %{ 8454 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8455 iRegIdst tmpI; 8456 maskI_reg_imm(tmpI, src2, mask); 8457 arShiftL_regL_regI(dst, src1, tmpI); 8458 %} 8459 %} 8460 8461 // Register Shift Right Immediate 8462 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8463 match(Set dst (RShiftL src1 src2)); 8464 8465 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} 8466 size(4); 8467 ins_encode %{ 8468 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8469 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8470 %} 8471 ins_pipe(pipe_class_default); 8472 %} 8473 8474 // RShiftL + ConvL2I 8475 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8476 match(Set dst (ConvL2I (RShiftL src1 src2))); 8477 8478 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8479 size(4); 8480 ins_encode %{ 8481 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8482 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8483 %} 8484 ins_pipe(pipe_class_default); 8485 %} 8486 8487 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8488 // no match-rule, false predicate 8489 effect(DEF dst, USE src1, USE src2); 8490 predicate(false); 8491 8492 format %{ "SRW $dst, $src1, $src2" %} 8493 size(4); 8494 ins_encode %{ 8495 // TODO: PPC port $archOpcode(ppc64Opcode_srw); 8496 __ srw($dst$$Register, $src1$$Register, $src2$$Register); 8497 %} 8498 ins_pipe(pipe_class_default); 8499 %} 8500 8501 // Register Shift Right 8502 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8503 match(Set dst (URShiftI src1 src2)); 8504 ins_cost(DEFAULT_COST*2); 8505 8506 expand %{ 8507 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8508 iRegIdst tmpI; 8509 maskI_reg_imm(tmpI, src2, mask); 8510 urShiftI_reg_reg(dst, src1, tmpI); 8511 %} 8512 %} 8513 8514 // Register Shift Right Immediate 8515 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8516 match(Set dst (URShiftI src1 src2)); 8517 8518 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} 8519 size(4); 8520 ins_encode %{ 8521 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8522 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8523 %} 8524 ins_pipe(pipe_class_default); 8525 %} 8526 8527 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8528 // no match-rule, false predicate 8529 effect(DEF dst, USE src1, USE src2); 8530 predicate(false); 8531 8532 format %{ "SRD $dst, $src1, $src2" %} 8533 size(4); 8534 ins_encode %{ 8535 // TODO: PPC port $archOpcode(ppc64Opcode_srd); 8536 __ srd($dst$$Register, $src1$$Register, $src2$$Register); 8537 %} 8538 ins_pipe(pipe_class_default); 8539 %} 8540 8541 // Register Shift Right 8542 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8543 match(Set dst (URShiftL src1 src2)); 8544 ins_cost(DEFAULT_COST*2); 8545 8546 expand %{ 8547 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8548 iRegIdst tmpI; 8549 maskI_reg_imm(tmpI, src2, mask); 8550 urShiftL_regL_regI(dst, src1, tmpI); 8551 %} 8552 %} 8553 8554 // Register Shift Right Immediate 8555 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8556 match(Set dst (URShiftL src1 src2)); 8557 8558 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} 8559 size(4); 8560 ins_encode %{ 8561 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8562 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8563 %} 8564 ins_pipe(pipe_class_default); 8565 %} 8566 8567 // URShiftL + ConvL2I. 8568 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8569 match(Set dst (ConvL2I (URShiftL src1 src2))); 8570 8571 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8572 size(4); 8573 ins_encode %{ 8574 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8575 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8576 %} 8577 ins_pipe(pipe_class_default); 8578 %} 8579 8580 // Register Shift Right Immediate with a CastP2X 8581 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ 8582 match(Set dst (URShiftL (CastP2X src1) src2)); 8583 8584 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} 8585 size(4); 8586 ins_encode %{ 8587 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8588 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8589 %} 8590 ins_pipe(pipe_class_default); 8591 %} 8592 8593 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ 8594 match(Set dst (ConvL2I (ConvI2L src))); 8595 8596 format %{ "EXTSW $dst, $src \t// int->int" %} 8597 size(4); 8598 ins_encode %{ 8599 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 8600 __ extsw($dst$$Register, $src$$Register); 8601 %} 8602 ins_pipe(pipe_class_default); 8603 %} 8604 8605 //----------Rotate Instructions------------------------------------------------ 8606 8607 // Rotate Left by 8-bit immediate 8608 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ 8609 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 8610 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8611 8612 format %{ "ROTLWI $dst, $src, $lshift" %} 8613 size(4); 8614 ins_encode %{ 8615 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8616 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); 8617 %} 8618 ins_pipe(pipe_class_default); 8619 %} 8620 8621 // Rotate Right by 8-bit immediate 8622 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ 8623 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 8624 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8625 8626 format %{ "ROTRWI $dst, $rshift" %} 8627 size(4); 8628 ins_encode %{ 8629 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8630 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); 8631 %} 8632 ins_pipe(pipe_class_default); 8633 %} 8634 8635 //----------Floating Point Arithmetic Instructions----------------------------- 8636 8637 // Add float single precision 8638 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 8639 match(Set dst (AddF src1 src2)); 8640 8641 format %{ "FADDS $dst, $src1, $src2" %} 8642 size(4); 8643 ins_encode %{ 8644 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); 8645 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8646 %} 8647 ins_pipe(pipe_class_default); 8648 %} 8649 8650 // Add float double precision 8651 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 8652 match(Set dst (AddD src1 src2)); 8653 8654 format %{ "FADD $dst, $src1, $src2" %} 8655 size(4); 8656 ins_encode %{ 8657 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); 8658 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8659 %} 8660 ins_pipe(pipe_class_default); 8661 %} 8662 8663 // Sub float single precision 8664 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 8665 match(Set dst (SubF src1 src2)); 8666 8667 format %{ "FSUBS $dst, $src1, $src2" %} 8668 size(4); 8669 ins_encode %{ 8670 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); 8671 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8672 %} 8673 ins_pipe(pipe_class_default); 8674 %} 8675 8676 // Sub float double precision 8677 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 8678 match(Set dst (SubD src1 src2)); 8679 format %{ "FSUB $dst, $src1, $src2" %} 8680 size(4); 8681 ins_encode %{ 8682 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); 8683 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8684 %} 8685 ins_pipe(pipe_class_default); 8686 %} 8687 8688 // Mul float single precision 8689 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 8690 match(Set dst (MulF src1 src2)); 8691 format %{ "FMULS $dst, $src1, $src2" %} 8692 size(4); 8693 ins_encode %{ 8694 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); 8695 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8696 %} 8697 ins_pipe(pipe_class_default); 8698 %} 8699 8700 // Mul float double precision 8701 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 8702 match(Set dst (MulD src1 src2)); 8703 format %{ "FMUL $dst, $src1, $src2" %} 8704 size(4); 8705 ins_encode %{ 8706 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); 8707 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8708 %} 8709 ins_pipe(pipe_class_default); 8710 %} 8711 8712 // Div float single precision 8713 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 8714 match(Set dst (DivF src1 src2)); 8715 format %{ "FDIVS $dst, $src1, $src2" %} 8716 size(4); 8717 ins_encode %{ 8718 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); 8719 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8720 %} 8721 ins_pipe(pipe_class_default); 8722 %} 8723 8724 // Div float double precision 8725 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 8726 match(Set dst (DivD src1 src2)); 8727 format %{ "FDIV $dst, $src1, $src2" %} 8728 size(4); 8729 ins_encode %{ 8730 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); 8731 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8732 %} 8733 ins_pipe(pipe_class_default); 8734 %} 8735 8736 // Absolute float single precision 8737 instruct absF_reg(regF dst, regF src) %{ 8738 match(Set dst (AbsF src)); 8739 format %{ "FABS $dst, $src \t// float" %} 8740 size(4); 8741 ins_encode %{ 8742 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8743 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8744 %} 8745 ins_pipe(pipe_class_default); 8746 %} 8747 8748 // Absolute float double precision 8749 instruct absD_reg(regD dst, regD src) %{ 8750 match(Set dst (AbsD src)); 8751 format %{ "FABS $dst, $src \t// double" %} 8752 size(4); 8753 ins_encode %{ 8754 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8755 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8756 %} 8757 ins_pipe(pipe_class_default); 8758 %} 8759 8760 instruct negF_reg(regF dst, regF src) %{ 8761 match(Set dst (NegF src)); 8762 format %{ "FNEG $dst, $src \t// float" %} 8763 size(4); 8764 ins_encode %{ 8765 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8766 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8767 %} 8768 ins_pipe(pipe_class_default); 8769 %} 8770 8771 instruct negD_reg(regD dst, regD src) %{ 8772 match(Set dst (NegD src)); 8773 format %{ "FNEG $dst, $src \t// double" %} 8774 size(4); 8775 ins_encode %{ 8776 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8777 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8778 %} 8779 ins_pipe(pipe_class_default); 8780 %} 8781 8782 // AbsF + NegF. 8783 instruct negF_absF_reg(regF dst, regF src) %{ 8784 match(Set dst (NegF (AbsF src))); 8785 format %{ "FNABS $dst, $src \t// float" %} 8786 size(4); 8787 ins_encode %{ 8788 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8789 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8790 %} 8791 ins_pipe(pipe_class_default); 8792 %} 8793 8794 // AbsD + NegD. 8795 instruct negD_absD_reg(regD dst, regD src) %{ 8796 match(Set dst (NegD (AbsD src))); 8797 format %{ "FNABS $dst, $src \t// double" %} 8798 size(4); 8799 ins_encode %{ 8800 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8801 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8802 %} 8803 ins_pipe(pipe_class_default); 8804 %} 8805 8806 // VM_Version::has_fsqrt() decides if this node will be used. 8807 // Sqrt float double precision 8808 instruct sqrtD_reg(regD dst, regD src) %{ 8809 match(Set dst (SqrtD src)); 8810 format %{ "FSQRT $dst, $src" %} 8811 size(4); 8812 ins_encode %{ 8813 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); 8814 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); 8815 %} 8816 ins_pipe(pipe_class_default); 8817 %} 8818 8819 // Single-precision sqrt. 8820 instruct sqrtF_reg(regF dst, regF src) %{ 8821 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8822 predicate(VM_Version::has_fsqrts()); 8823 ins_cost(DEFAULT_COST); 8824 8825 format %{ "FSQRTS $dst, $src" %} 8826 size(4); 8827 ins_encode %{ 8828 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); 8829 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); 8830 %} 8831 ins_pipe(pipe_class_default); 8832 %} 8833 8834 instruct roundDouble_nop(regD dst) %{ 8835 match(Set dst (RoundDouble dst)); 8836 ins_cost(0); 8837 8838 format %{ " -- \t// RoundDouble not needed - empty" %} 8839 size(0); 8840 // PPC results are already "rounded" (i.e., normal-format IEEE). 8841 ins_encode( /*empty*/ ); 8842 ins_pipe(pipe_class_default); 8843 %} 8844 8845 instruct roundFloat_nop(regF dst) %{ 8846 match(Set dst (RoundFloat dst)); 8847 ins_cost(0); 8848 8849 format %{ " -- \t// RoundFloat not needed - empty" %} 8850 size(0); 8851 // PPC results are already "rounded" (i.e., normal-format IEEE). 8852 ins_encode( /*empty*/ ); 8853 ins_pipe(pipe_class_default); 8854 %} 8855 8856 //----------Logical Instructions----------------------------------------------- 8857 8858 // And Instructions 8859 8860 // Register And 8861 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8862 match(Set dst (AndI src1 src2)); 8863 format %{ "AND $dst, $src1, $src2" %} 8864 size(4); 8865 ins_encode %{ 8866 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8867 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8868 %} 8869 ins_pipe(pipe_class_default); 8870 %} 8871 8872 // Immediate And 8873 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ 8874 match(Set dst (AndI src1 src2)); 8875 effect(KILL cr0); 8876 8877 format %{ "ANDI $dst, $src1, $src2" %} 8878 size(4); 8879 ins_encode %{ 8880 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8881 // FIXME: avoid andi_ ? 8882 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8883 %} 8884 ins_pipe(pipe_class_default); 8885 %} 8886 8887 // Immediate And where the immediate is a negative power of 2. 8888 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ 8889 match(Set dst (AndI src1 src2)); 8890 format %{ "ANDWI $dst, $src1, $src2" %} 8891 size(4); 8892 ins_encode %{ 8893 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8894 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); 8895 %} 8896 ins_pipe(pipe_class_default); 8897 %} 8898 8899 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ 8900 match(Set dst (AndI src1 src2)); 8901 format %{ "ANDWI $dst, $src1, $src2" %} 8902 size(4); 8903 ins_encode %{ 8904 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8905 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8906 %} 8907 ins_pipe(pipe_class_default); 8908 %} 8909 8910 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ 8911 match(Set dst (AndI src1 src2)); 8912 predicate(UseRotateAndMaskInstructionsPPC64); 8913 format %{ "ANDWI $dst, $src1, $src2" %} 8914 size(4); 8915 ins_encode %{ 8916 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8917 __ rlwinm($dst$$Register, $src1$$Register, 0, 8918 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); 8919 %} 8920 ins_pipe(pipe_class_default); 8921 %} 8922 8923 // Register And Long 8924 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8925 match(Set dst (AndL src1 src2)); 8926 ins_cost(DEFAULT_COST); 8927 8928 format %{ "AND $dst, $src1, $src2 \t// long" %} 8929 size(4); 8930 ins_encode %{ 8931 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8932 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8933 %} 8934 ins_pipe(pipe_class_default); 8935 %} 8936 8937 // Immediate And long 8938 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ 8939 match(Set dst (AndL src1 src2)); 8940 effect(KILL cr0); 8941 8942 format %{ "ANDI $dst, $src1, $src2 \t// long" %} 8943 size(4); 8944 ins_encode %{ 8945 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8946 // FIXME: avoid andi_ ? 8947 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8948 %} 8949 ins_pipe(pipe_class_default); 8950 %} 8951 8952 // Immediate And Long where the immediate is a negative power of 2. 8953 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ 8954 match(Set dst (AndL src1 src2)); 8955 format %{ "ANDDI $dst, $src1, $src2" %} 8956 size(4); 8957 ins_encode %{ 8958 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8959 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); 8960 %} 8961 ins_pipe(pipe_class_default); 8962 %} 8963 8964 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8965 match(Set dst (AndL src1 src2)); 8966 format %{ "ANDDI $dst, $src1, $src2" %} 8967 size(4); 8968 ins_encode %{ 8969 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8970 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8971 %} 8972 ins_pipe(pipe_class_default); 8973 %} 8974 8975 // AndL + ConvL2I. 8976 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8977 match(Set dst (ConvL2I (AndL src1 src2))); 8978 ins_cost(DEFAULT_COST); 8979 8980 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} 8981 size(4); 8982 ins_encode %{ 8983 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8984 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8985 %} 8986 ins_pipe(pipe_class_default); 8987 %} 8988 8989 // Or Instructions 8990 8991 // Register Or 8992 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8993 match(Set dst (OrI src1 src2)); 8994 format %{ "OR $dst, $src1, $src2" %} 8995 size(4); 8996 ins_encode %{ 8997 // TODO: PPC port $archOpcode(ppc64Opcode_or); 8998 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 8999 %} 9000 ins_pipe(pipe_class_default); 9001 %} 9002 9003 // Expand does not work with above instruct. (??) 9004 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9005 // no match-rule 9006 effect(DEF dst, USE src1, USE src2); 9007 format %{ "OR $dst, $src1, $src2" %} 9008 size(4); 9009 ins_encode %{ 9010 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9011 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9012 %} 9013 ins_pipe(pipe_class_default); 9014 %} 9015 9016 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9017 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); 9018 ins_cost(DEFAULT_COST*3); 9019 9020 expand %{ 9021 // FIXME: we should do this in the ideal world. 9022 iRegIdst tmp1; 9023 iRegIdst tmp2; 9024 orI_reg_reg(tmp1, src1, src2); 9025 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 9026 orI_reg_reg(dst, tmp1, tmp2); 9027 %} 9028 %} 9029 9030 // Immediate Or 9031 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9032 match(Set dst (OrI src1 src2)); 9033 format %{ "ORI $dst, $src1, $src2" %} 9034 size(4); 9035 ins_encode %{ 9036 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9037 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 9038 %} 9039 ins_pipe(pipe_class_default); 9040 %} 9041 9042 // Register Or Long 9043 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9044 match(Set dst (OrL src1 src2)); 9045 ins_cost(DEFAULT_COST); 9046 9047 size(4); 9048 format %{ "OR $dst, $src1, $src2 \t// long" %} 9049 ins_encode %{ 9050 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9051 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9052 %} 9053 ins_pipe(pipe_class_default); 9054 %} 9055 9056 // OrL + ConvL2I. 9057 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9058 match(Set dst (ConvL2I (OrL src1 src2))); 9059 ins_cost(DEFAULT_COST); 9060 9061 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} 9062 size(4); 9063 ins_encode %{ 9064 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9065 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9066 %} 9067 ins_pipe(pipe_class_default); 9068 %} 9069 9070 // Immediate Or long 9071 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ 9072 match(Set dst (OrL src1 con)); 9073 ins_cost(DEFAULT_COST); 9074 9075 format %{ "ORI $dst, $src1, $con \t// long" %} 9076 size(4); 9077 ins_encode %{ 9078 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9079 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); 9080 %} 9081 ins_pipe(pipe_class_default); 9082 %} 9083 9084 // Xor Instructions 9085 9086 // Register Xor 9087 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9088 match(Set dst (XorI src1 src2)); 9089 format %{ "XOR $dst, $src1, $src2" %} 9090 size(4); 9091 ins_encode %{ 9092 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9093 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9094 %} 9095 ins_pipe(pipe_class_default); 9096 %} 9097 9098 // Expand does not work with above instruct. (??) 9099 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9100 // no match-rule 9101 effect(DEF dst, USE src1, USE src2); 9102 format %{ "XOR $dst, $src1, $src2" %} 9103 size(4); 9104 ins_encode %{ 9105 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9106 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9107 %} 9108 ins_pipe(pipe_class_default); 9109 %} 9110 9111 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9112 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); 9113 ins_cost(DEFAULT_COST*3); 9114 9115 expand %{ 9116 // FIXME: we should do this in the ideal world. 9117 iRegIdst tmp1; 9118 iRegIdst tmp2; 9119 xorI_reg_reg(tmp1, src1, src2); 9120 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. 9121 xorI_reg_reg(dst, tmp1, tmp2); 9122 %} 9123 %} 9124 9125 // Immediate Xor 9126 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9127 match(Set dst (XorI src1 src2)); 9128 format %{ "XORI $dst, $src1, $src2" %} 9129 size(4); 9130 ins_encode %{ 9131 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9132 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9133 %} 9134 ins_pipe(pipe_class_default); 9135 %} 9136 9137 // Register Xor Long 9138 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9139 match(Set dst (XorL src1 src2)); 9140 ins_cost(DEFAULT_COST); 9141 9142 format %{ "XOR $dst, $src1, $src2 \t// long" %} 9143 size(4); 9144 ins_encode %{ 9145 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9146 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9147 %} 9148 ins_pipe(pipe_class_default); 9149 %} 9150 9151 // XorL + ConvL2I. 9152 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9153 match(Set dst (ConvL2I (XorL src1 src2))); 9154 ins_cost(DEFAULT_COST); 9155 9156 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} 9157 size(4); 9158 ins_encode %{ 9159 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9160 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9161 %} 9162 ins_pipe(pipe_class_default); 9163 %} 9164 9165 // Immediate Xor Long 9166 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ 9167 match(Set dst (XorL src1 src2)); 9168 ins_cost(DEFAULT_COST); 9169 9170 format %{ "XORI $dst, $src1, $src2 \t// long" %} 9171 size(4); 9172 ins_encode %{ 9173 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9174 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9175 %} 9176 ins_pipe(pipe_class_default); 9177 %} 9178 9179 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 9180 match(Set dst (XorI src1 src2)); 9181 ins_cost(DEFAULT_COST); 9182 9183 format %{ "NOT $dst, $src1 ($src2)" %} 9184 size(4); 9185 ins_encode %{ 9186 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9187 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9188 %} 9189 ins_pipe(pipe_class_default); 9190 %} 9191 9192 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 9193 match(Set dst (XorL src1 src2)); 9194 ins_cost(DEFAULT_COST); 9195 9196 format %{ "NOT $dst, $src1 ($src2) \t// long" %} 9197 size(4); 9198 ins_encode %{ 9199 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9200 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9201 %} 9202 ins_pipe(pipe_class_default); 9203 %} 9204 9205 // And-complement 9206 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ 9207 match(Set dst (AndI (XorI src1 src2) src3)); 9208 ins_cost(DEFAULT_COST); 9209 9210 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} 9211 size(4); 9212 ins_encode( enc_andc(dst, src3, src1) ); 9213 ins_pipe(pipe_class_default); 9214 %} 9215 9216 // And-complement 9217 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9218 // no match-rule, false predicate 9219 effect(DEF dst, USE src1, USE src2); 9220 predicate(false); 9221 9222 format %{ "ANDC $dst, $src1, $src2" %} 9223 size(4); 9224 ins_encode %{ 9225 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 9226 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 9227 %} 9228 ins_pipe(pipe_class_default); 9229 %} 9230 9231 //----------Moves between int/long and float/double---------------------------- 9232 // 9233 // The following rules move values from int/long registers/stack-locations 9234 // to float/double registers/stack-locations and vice versa, without doing any 9235 // conversions. These rules are used to implement the bit-conversion methods 9236 // of java.lang.Float etc., e.g. 9237 // int floatToIntBits(float value) 9238 // float intBitsToFloat(int bits) 9239 // 9240 // Notes on the implementation on ppc64: 9241 // We only provide rules which move between a register and a stack-location, 9242 // because we always have to go through memory when moving between a float 9243 // register and an integer register. 9244 9245 //---------- Chain stack slots between similar types -------- 9246 9247 // These are needed so that the rules below can match. 9248 9249 // Load integer from stack slot 9250 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ 9251 match(Set dst src); 9252 ins_cost(MEMORY_REF_COST); 9253 9254 format %{ "LWZ $dst, $src" %} 9255 size(4); 9256 ins_encode( enc_lwz(dst, src) ); 9257 ins_pipe(pipe_class_memory); 9258 %} 9259 9260 // Store integer to stack slot 9261 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ 9262 match(Set dst src); 9263 ins_cost(MEMORY_REF_COST); 9264 9265 format %{ "STW $src, $dst \t// stk" %} 9266 size(4); 9267 ins_encode( enc_stw(src, dst) ); // rs=rt 9268 ins_pipe(pipe_class_memory); 9269 %} 9270 9271 // Load long from stack slot 9272 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ 9273 match(Set dst src); 9274 ins_cost(MEMORY_REF_COST); 9275 9276 format %{ "LD $dst, $src \t// long" %} 9277 size(4); 9278 ins_encode( enc_ld(dst, src) ); 9279 ins_pipe(pipe_class_memory); 9280 %} 9281 9282 // Store long to stack slot 9283 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ 9284 match(Set dst src); 9285 ins_cost(MEMORY_REF_COST); 9286 9287 format %{ "STD $src, $dst \t// long" %} 9288 size(4); 9289 ins_encode( enc_std(src, dst) ); // rs=rt 9290 ins_pipe(pipe_class_memory); 9291 %} 9292 9293 //----------Moves between int and float 9294 9295 // Move float value from float stack-location to integer register. 9296 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ 9297 match(Set dst (MoveF2I src)); 9298 ins_cost(MEMORY_REF_COST); 9299 9300 format %{ "LWZ $dst, $src \t// MoveF2I" %} 9301 size(4); 9302 ins_encode( enc_lwz(dst, src) ); 9303 ins_pipe(pipe_class_memory); 9304 %} 9305 9306 // Move float value from float register to integer stack-location. 9307 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ 9308 match(Set dst (MoveF2I src)); 9309 ins_cost(MEMORY_REF_COST); 9310 9311 format %{ "STFS $src, $dst \t// MoveF2I" %} 9312 size(4); 9313 ins_encode( enc_stfs(src, dst) ); 9314 ins_pipe(pipe_class_memory); 9315 %} 9316 9317 // Move integer value from integer stack-location to float register. 9318 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ 9319 match(Set dst (MoveI2F src)); 9320 ins_cost(MEMORY_REF_COST); 9321 9322 format %{ "LFS $dst, $src \t// MoveI2F" %} 9323 size(4); 9324 ins_encode %{ 9325 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 9326 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); 9327 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); 9328 %} 9329 ins_pipe(pipe_class_memory); 9330 %} 9331 9332 // Move integer value from integer register to float stack-location. 9333 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ 9334 match(Set dst (MoveI2F src)); 9335 ins_cost(MEMORY_REF_COST); 9336 9337 format %{ "STW $src, $dst \t// MoveI2F" %} 9338 size(4); 9339 ins_encode( enc_stw(src, dst) ); 9340 ins_pipe(pipe_class_memory); 9341 %} 9342 9343 //----------Moves between long and float 9344 9345 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ 9346 // no match-rule, false predicate 9347 effect(DEF dst, USE src); 9348 predicate(false); 9349 9350 format %{ "storeD $src, $dst \t// STACK" %} 9351 size(4); 9352 ins_encode( enc_stfd(src, dst) ); 9353 ins_pipe(pipe_class_default); 9354 %} 9355 9356 //----------Moves between long and double 9357 9358 // Move double value from double stack-location to long register. 9359 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ 9360 match(Set dst (MoveD2L src)); 9361 ins_cost(MEMORY_REF_COST); 9362 size(4); 9363 format %{ "LD $dst, $src \t// MoveD2L" %} 9364 ins_encode( enc_ld(dst, src) ); 9365 ins_pipe(pipe_class_memory); 9366 %} 9367 9368 // Move double value from double register to long stack-location. 9369 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ 9370 match(Set dst (MoveD2L src)); 9371 effect(DEF dst, USE src); 9372 ins_cost(MEMORY_REF_COST); 9373 9374 format %{ "STFD $src, $dst \t// MoveD2L" %} 9375 size(4); 9376 ins_encode( enc_stfd(src, dst) ); 9377 ins_pipe(pipe_class_memory); 9378 %} 9379 9380 // Move long value from long stack-location to double register. 9381 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ 9382 match(Set dst (MoveL2D src)); 9383 ins_cost(MEMORY_REF_COST); 9384 9385 format %{ "LFD $dst, $src \t// MoveL2D" %} 9386 size(4); 9387 ins_encode( enc_lfd(dst, src) ); 9388 ins_pipe(pipe_class_memory); 9389 %} 9390 9391 // Move long value from long register to double stack-location. 9392 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ 9393 match(Set dst (MoveL2D src)); 9394 ins_cost(MEMORY_REF_COST); 9395 9396 format %{ "STD $src, $dst \t// MoveL2D" %} 9397 size(4); 9398 ins_encode( enc_std(src, dst) ); 9399 ins_pipe(pipe_class_memory); 9400 %} 9401 9402 //----------Register Move Instructions----------------------------------------- 9403 9404 // Replicate for Superword 9405 9406 instruct moveReg(iRegLdst dst, iRegIsrc src) %{ 9407 predicate(false); 9408 effect(DEF dst, USE src); 9409 9410 format %{ "MR $dst, $src \t// replicate " %} 9411 // variable size, 0 or 4. 9412 ins_encode %{ 9413 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9414 __ mr_if_needed($dst$$Register, $src$$Register); 9415 %} 9416 ins_pipe(pipe_class_default); 9417 %} 9418 9419 //----------Cast instructions (Java-level type cast)--------------------------- 9420 9421 // Cast Long to Pointer for unsafe natives. 9422 instruct castX2P(iRegPdst dst, iRegLsrc src) %{ 9423 match(Set dst (CastX2P src)); 9424 9425 format %{ "MR $dst, $src \t// Long->Ptr" %} 9426 // variable size, 0 or 4. 9427 ins_encode %{ 9428 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9429 __ mr_if_needed($dst$$Register, $src$$Register); 9430 %} 9431 ins_pipe(pipe_class_default); 9432 %} 9433 9434 // Cast Pointer to Long for unsafe natives. 9435 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ 9436 match(Set dst (CastP2X src)); 9437 9438 format %{ "MR $dst, $src \t// Ptr->Long" %} 9439 // variable size, 0 or 4. 9440 ins_encode %{ 9441 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9442 __ mr_if_needed($dst$$Register, $src$$Register); 9443 %} 9444 ins_pipe(pipe_class_default); 9445 %} 9446 9447 instruct castPP(iRegPdst dst) %{ 9448 match(Set dst (CastPP dst)); 9449 format %{ " -- \t// castPP of $dst" %} 9450 size(0); 9451 ins_encode( /*empty*/ ); 9452 ins_pipe(pipe_class_default); 9453 %} 9454 9455 instruct castII(iRegIdst dst) %{ 9456 match(Set dst (CastII dst)); 9457 format %{ " -- \t// castII of $dst" %} 9458 size(0); 9459 ins_encode( /*empty*/ ); 9460 ins_pipe(pipe_class_default); 9461 %} 9462 9463 instruct checkCastPP(iRegPdst dst) %{ 9464 match(Set dst (CheckCastPP dst)); 9465 format %{ " -- \t// checkcastPP of $dst" %} 9466 size(0); 9467 ins_encode( /*empty*/ ); 9468 ins_pipe(pipe_class_default); 9469 %} 9470 9471 //----------Convert instructions----------------------------------------------- 9472 9473 // Convert to boolean. 9474 9475 // int_to_bool(src) : { 1 if src != 0 9476 // { 0 else 9477 // 9478 // strategy: 9479 // 1) Count leading zeros of 32 bit-value src, 9480 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. 9481 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9482 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9483 9484 // convI2Bool 9485 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ 9486 match(Set dst (Conv2B src)); 9487 predicate(UseCountLeadingZerosInstructionsPPC64); 9488 ins_cost(DEFAULT_COST); 9489 9490 expand %{ 9491 immI shiftAmount %{ 0x5 %} 9492 uimmI16 mask %{ 0x1 %} 9493 iRegIdst tmp1; 9494 iRegIdst tmp2; 9495 countLeadingZerosI(tmp1, src); 9496 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9497 xorI_reg_uimm16(dst, tmp2, mask); 9498 %} 9499 %} 9500 9501 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ 9502 match(Set dst (Conv2B src)); 9503 effect(TEMP crx); 9504 predicate(!UseCountLeadingZerosInstructionsPPC64); 9505 ins_cost(DEFAULT_COST); 9506 9507 format %{ "CMPWI $crx, $src, #0 \t// convI2B" 9508 "LI $dst, #0\n\t" 9509 "BEQ $crx, done\n\t" 9510 "LI $dst, #1\n" 9511 "done:" %} 9512 size(16); 9513 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); 9514 ins_pipe(pipe_class_compare); 9515 %} 9516 9517 // ConvI2B + XorI 9518 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ 9519 match(Set dst (XorI (Conv2B src) mask)); 9520 predicate(UseCountLeadingZerosInstructionsPPC64); 9521 ins_cost(DEFAULT_COST); 9522 9523 expand %{ 9524 immI shiftAmount %{ 0x5 %} 9525 iRegIdst tmp1; 9526 countLeadingZerosI(tmp1, src); 9527 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9528 %} 9529 %} 9530 9531 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ 9532 match(Set dst (XorI (Conv2B src) mask)); 9533 effect(TEMP crx); 9534 predicate(!UseCountLeadingZerosInstructionsPPC64); 9535 ins_cost(DEFAULT_COST); 9536 9537 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" 9538 "LI $dst, #1\n\t" 9539 "BEQ $crx, done\n\t" 9540 "LI $dst, #0\n" 9541 "done:" %} 9542 size(16); 9543 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); 9544 ins_pipe(pipe_class_compare); 9545 %} 9546 9547 // AndI 0b0..010..0 + ConvI2B 9548 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ 9549 match(Set dst (Conv2B (AndI src mask))); 9550 predicate(UseRotateAndMaskInstructionsPPC64); 9551 ins_cost(DEFAULT_COST); 9552 9553 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} 9554 size(4); 9555 ins_encode %{ 9556 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 9557 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); 9558 %} 9559 ins_pipe(pipe_class_default); 9560 %} 9561 9562 // Convert pointer to boolean. 9563 // 9564 // ptr_to_bool(src) : { 1 if src != 0 9565 // { 0 else 9566 // 9567 // strategy: 9568 // 1) Count leading zeros of 64 bit-value src, 9569 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. 9570 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9571 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9572 9573 // ConvP2B 9574 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ 9575 match(Set dst (Conv2B src)); 9576 predicate(UseCountLeadingZerosInstructionsPPC64); 9577 ins_cost(DEFAULT_COST); 9578 9579 expand %{ 9580 immI shiftAmount %{ 0x6 %} 9581 uimmI16 mask %{ 0x1 %} 9582 iRegIdst tmp1; 9583 iRegIdst tmp2; 9584 countLeadingZerosP(tmp1, src); 9585 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9586 xorI_reg_uimm16(dst, tmp2, mask); 9587 %} 9588 %} 9589 9590 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ 9591 match(Set dst (Conv2B src)); 9592 effect(TEMP crx); 9593 predicate(!UseCountLeadingZerosInstructionsPPC64); 9594 ins_cost(DEFAULT_COST); 9595 9596 format %{ "CMPDI $crx, $src, #0 \t// convP2B" 9597 "LI $dst, #0\n\t" 9598 "BEQ $crx, done\n\t" 9599 "LI $dst, #1\n" 9600 "done:" %} 9601 size(16); 9602 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); 9603 ins_pipe(pipe_class_compare); 9604 %} 9605 9606 // ConvP2B + XorI 9607 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ 9608 match(Set dst (XorI (Conv2B src) mask)); 9609 predicate(UseCountLeadingZerosInstructionsPPC64); 9610 ins_cost(DEFAULT_COST); 9611 9612 expand %{ 9613 immI shiftAmount %{ 0x6 %} 9614 iRegIdst tmp1; 9615 countLeadingZerosP(tmp1, src); 9616 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9617 %} 9618 %} 9619 9620 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ 9621 match(Set dst (XorI (Conv2B src) mask)); 9622 effect(TEMP crx); 9623 predicate(!UseCountLeadingZerosInstructionsPPC64); 9624 ins_cost(DEFAULT_COST); 9625 9626 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" 9627 "LI $dst, #1\n\t" 9628 "BEQ $crx, done\n\t" 9629 "LI $dst, #0\n" 9630 "done:" %} 9631 size(16); 9632 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); 9633 ins_pipe(pipe_class_compare); 9634 %} 9635 9636 // if src1 < src2, return -1 else return 0 9637 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9638 match(Set dst (CmpLTMask src1 src2)); 9639 ins_cost(DEFAULT_COST*4); 9640 9641 expand %{ 9642 iRegLdst src1s; 9643 iRegLdst src2s; 9644 iRegLdst diff; 9645 convI2L_reg(src1s, src1); // Ensure proper sign extension. 9646 convI2L_reg(src2s, src2); // Ensure proper sign extension. 9647 subL_reg_reg(diff, src1s, src2s); 9648 // Need to consider >=33 bit result, therefore we need signmaskL. 9649 signmask64I_regL(dst, diff); 9650 %} 9651 %} 9652 9653 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ 9654 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 9655 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} 9656 size(4); 9657 ins_encode %{ 9658 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 9659 __ srawi($dst$$Register, $src1$$Register, 0x1f); 9660 %} 9661 ins_pipe(pipe_class_default); 9662 %} 9663 9664 //----------Arithmetic Conversion Instructions--------------------------------- 9665 9666 // Convert to Byte -- nop 9667 // Convert to Short -- nop 9668 9669 // Convert to Int 9670 9671 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ 9672 match(Set dst (RShiftI (LShiftI src amount) amount)); 9673 format %{ "EXTSB $dst, $src \t// byte->int" %} 9674 size(4); 9675 ins_encode %{ 9676 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 9677 __ extsb($dst$$Register, $src$$Register); 9678 %} 9679 ins_pipe(pipe_class_default); 9680 %} 9681 9682 // LShiftI 16 + RShiftI 16 converts short to int. 9683 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ 9684 match(Set dst (RShiftI (LShiftI src amount) amount)); 9685 format %{ "EXTSH $dst, $src \t// short->int" %} 9686 size(4); 9687 ins_encode %{ 9688 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); 9689 __ extsh($dst$$Register, $src$$Register); 9690 %} 9691 ins_pipe(pipe_class_default); 9692 %} 9693 9694 // ConvL2I + ConvI2L: Sign extend int in long register. 9695 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ 9696 match(Set dst (ConvI2L (ConvL2I src))); 9697 9698 format %{ "EXTSW $dst, $src \t// long->long" %} 9699 size(4); 9700 ins_encode %{ 9701 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9702 __ extsw($dst$$Register, $src$$Register); 9703 %} 9704 ins_pipe(pipe_class_default); 9705 %} 9706 9707 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ 9708 match(Set dst (ConvL2I src)); 9709 format %{ "MR $dst, $src \t// long->int" %} 9710 // variable size, 0 or 4 9711 ins_encode %{ 9712 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9713 __ mr_if_needed($dst$$Register, $src$$Register); 9714 %} 9715 ins_pipe(pipe_class_default); 9716 %} 9717 9718 instruct convD2IRaw_regD(regD dst, regD src) %{ 9719 // no match-rule, false predicate 9720 effect(DEF dst, USE src); 9721 predicate(false); 9722 9723 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} 9724 size(4); 9725 ins_encode %{ 9726 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; 9727 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9728 %} 9729 ins_pipe(pipe_class_default); 9730 %} 9731 9732 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{ 9733 // no match-rule, false predicate 9734 effect(DEF dst, USE crx, USE src); 9735 predicate(false); 9736 9737 ins_variable_size_depending_on_alignment(true); 9738 9739 format %{ "cmovI $crx, $dst, $src" %} 9740 // Worst case is branch + move + stop, no stop without scheduler. 9741 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 9742 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9743 ins_pipe(pipe_class_default); 9744 %} 9745 9746 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{ 9747 // no match-rule, false predicate 9748 effect(DEF dst, USE crx, USE mem); 9749 predicate(false); 9750 9751 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} 9752 postalloc_expand %{ 9753 // 9754 // replaces 9755 // 9756 // region dst crx mem 9757 // \ | | / 9758 // dst=cmovI_bso_stackSlotL_conLvalue0 9759 // 9760 // with 9761 // 9762 // region dst 9763 // \ / 9764 // dst=loadConI16(0) 9765 // | 9766 // ^ region dst crx mem 9767 // | \ | | / 9768 // dst=cmovI_bso_stackSlotL 9769 // 9770 9771 // Create new nodes. 9772 MachNode *m1 = new loadConI16Node(); 9773 MachNode *m2 = new cmovI_bso_stackSlotLNode(); 9774 9775 // inputs for new nodes 9776 m1->add_req(n_region); 9777 m2->add_req(n_region, n_crx, n_mem); 9778 9779 // precedences for new nodes 9780 m2->add_prec(m1); 9781 9782 // operands for new nodes 9783 m1->_opnds[0] = op_dst; 9784 m1->_opnds[1] = new immI16Oper(0); 9785 9786 m2->_opnds[0] = op_dst; 9787 m2->_opnds[1] = op_crx; 9788 m2->_opnds[2] = op_mem; 9789 9790 // registers for new nodes 9791 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9792 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9793 9794 // Insert new nodes. 9795 nodes->push(m1); 9796 nodes->push(m2); 9797 %} 9798 %} 9799 9800 // Double to Int conversion, NaN is mapped to 0. 9801 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ 9802 match(Set dst (ConvD2I src)); 9803 ins_cost(DEFAULT_COST); 9804 9805 expand %{ 9806 regD tmpD; 9807 stackSlotL tmpS; 9808 flagsReg crx; 9809 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9810 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). 9811 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 9812 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9813 %} 9814 %} 9815 9816 instruct convF2IRaw_regF(regF dst, regF src) %{ 9817 // no match-rule, false predicate 9818 effect(DEF dst, USE src); 9819 predicate(false); 9820 9821 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} 9822 size(4); 9823 ins_encode %{ 9824 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9825 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9826 %} 9827 ins_pipe(pipe_class_default); 9828 %} 9829 9830 // Float to Int conversion, NaN is mapped to 0. 9831 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ 9832 match(Set dst (ConvF2I src)); 9833 ins_cost(DEFAULT_COST); 9834 9835 expand %{ 9836 regF tmpF; 9837 stackSlotL tmpS; 9838 flagsReg crx; 9839 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9840 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). 9841 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9842 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9843 %} 9844 %} 9845 9846 // Convert to Long 9847 9848 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ 9849 match(Set dst (ConvI2L src)); 9850 format %{ "EXTSW $dst, $src \t// int->long" %} 9851 size(4); 9852 ins_encode %{ 9853 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9854 __ extsw($dst$$Register, $src$$Register); 9855 %} 9856 ins_pipe(pipe_class_default); 9857 %} 9858 9859 // Zero-extend: convert unsigned int to long (convUI2L). 9860 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ 9861 match(Set dst (AndL (ConvI2L src) mask)); 9862 ins_cost(DEFAULT_COST); 9863 9864 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9865 size(4); 9866 ins_encode %{ 9867 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9868 __ clrldi($dst$$Register, $src$$Register, 32); 9869 %} 9870 ins_pipe(pipe_class_default); 9871 %} 9872 9873 // Zero-extend: convert unsigned int to long in long register. 9874 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ 9875 match(Set dst (AndL src mask)); 9876 ins_cost(DEFAULT_COST); 9877 9878 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9879 size(4); 9880 ins_encode %{ 9881 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9882 __ clrldi($dst$$Register, $src$$Register, 32); 9883 %} 9884 ins_pipe(pipe_class_default); 9885 %} 9886 9887 instruct convF2LRaw_regF(regF dst, regF src) %{ 9888 // no match-rule, false predicate 9889 effect(DEF dst, USE src); 9890 predicate(false); 9891 9892 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} 9893 size(4); 9894 ins_encode %{ 9895 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9896 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9897 %} 9898 ins_pipe(pipe_class_default); 9899 %} 9900 9901 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{ 9902 // no match-rule, false predicate 9903 effect(DEF dst, USE crx, USE src); 9904 predicate(false); 9905 9906 ins_variable_size_depending_on_alignment(true); 9907 9908 format %{ "cmovL $crx, $dst, $src" %} 9909 // Worst case is branch + move + stop, no stop without scheduler. 9910 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 9911 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9912 ins_pipe(pipe_class_default); 9913 %} 9914 9915 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{ 9916 // no match-rule, false predicate 9917 effect(DEF dst, USE crx, USE mem); 9918 predicate(false); 9919 9920 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} 9921 postalloc_expand %{ 9922 // 9923 // replaces 9924 // 9925 // region dst crx mem 9926 // \ | | / 9927 // dst=cmovL_bso_stackSlotL_conLvalue0 9928 // 9929 // with 9930 // 9931 // region dst 9932 // \ / 9933 // dst=loadConL16(0) 9934 // | 9935 // ^ region dst crx mem 9936 // | \ | | / 9937 // dst=cmovL_bso_stackSlotL 9938 // 9939 9940 // Create new nodes. 9941 MachNode *m1 = new loadConL16Node(); 9942 MachNode *m2 = new cmovL_bso_stackSlotLNode(); 9943 9944 // inputs for new nodes 9945 m1->add_req(n_region); 9946 m2->add_req(n_region, n_crx, n_mem); 9947 m2->add_prec(m1); 9948 9949 // operands for new nodes 9950 m1->_opnds[0] = op_dst; 9951 m1->_opnds[1] = new immL16Oper(0); 9952 m2->_opnds[0] = op_dst; 9953 m2->_opnds[1] = op_crx; 9954 m2->_opnds[2] = op_mem; 9955 9956 // registers for new nodes 9957 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9958 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9959 9960 // Insert new nodes. 9961 nodes->push(m1); 9962 nodes->push(m2); 9963 %} 9964 %} 9965 9966 // Float to Long conversion, NaN is mapped to 0. 9967 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ 9968 match(Set dst (ConvF2L src)); 9969 ins_cost(DEFAULT_COST); 9970 9971 expand %{ 9972 regF tmpF; 9973 stackSlotL tmpS; 9974 flagsReg crx; 9975 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9976 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). 9977 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9978 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9979 %} 9980 %} 9981 9982 instruct convD2LRaw_regD(regD dst, regD src) %{ 9983 // no match-rule, false predicate 9984 effect(DEF dst, USE src); 9985 predicate(false); 9986 9987 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} 9988 size(4); 9989 ins_encode %{ 9990 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9991 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9992 %} 9993 ins_pipe(pipe_class_default); 9994 %} 9995 9996 // Double to Long conversion, NaN is mapped to 0. 9997 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ 9998 match(Set dst (ConvD2L src)); 9999 ins_cost(DEFAULT_COST); 10000 10001 expand %{ 10002 regD tmpD; 10003 stackSlotL tmpS; 10004 flagsReg crx; 10005 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10006 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). 10007 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 10008 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10009 %} 10010 %} 10011 10012 // Convert to Float 10013 10014 // Placed here as needed in expand. 10015 instruct convL2DRaw_regD(regD dst, regD src) %{ 10016 // no match-rule, false predicate 10017 effect(DEF dst, USE src); 10018 predicate(false); 10019 10020 format %{ "FCFID $dst, $src \t// convL2D" %} 10021 size(4); 10022 ins_encode %{ 10023 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10024 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); 10025 %} 10026 ins_pipe(pipe_class_default); 10027 %} 10028 10029 // Placed here as needed in expand. 10030 instruct convD2F_reg(regF dst, regD src) %{ 10031 match(Set dst (ConvD2F src)); 10032 format %{ "FRSP $dst, $src \t// convD2F" %} 10033 size(4); 10034 ins_encode %{ 10035 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); 10036 __ frsp($dst$$FloatRegister, $src$$FloatRegister); 10037 %} 10038 ins_pipe(pipe_class_default); 10039 %} 10040 10041 // Integer to Float conversion. 10042 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ 10043 match(Set dst (ConvI2F src)); 10044 predicate(!VM_Version::has_fcfids()); 10045 ins_cost(DEFAULT_COST); 10046 10047 expand %{ 10048 iRegLdst tmpL; 10049 stackSlotL tmpS; 10050 regD tmpD; 10051 regD tmpD2; 10052 convI2L_reg(tmpL, src); // Sign-extension int to long. 10053 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10054 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10055 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. 10056 convD2F_reg(dst, tmpD2); // Convert double to float. 10057 %} 10058 %} 10059 10060 instruct convL2FRaw_regF(regF dst, regD src) %{ 10061 // no match-rule, false predicate 10062 effect(DEF dst, USE src); 10063 predicate(false); 10064 10065 format %{ "FCFIDS $dst, $src \t// convL2F" %} 10066 size(4); 10067 ins_encode %{ 10068 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10069 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); 10070 %} 10071 ins_pipe(pipe_class_default); 10072 %} 10073 10074 // Integer to Float conversion. Special version for Power7. 10075 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ 10076 match(Set dst (ConvI2F src)); 10077 predicate(VM_Version::has_fcfids()); 10078 ins_cost(DEFAULT_COST); 10079 10080 expand %{ 10081 iRegLdst tmpL; 10082 stackSlotL tmpS; 10083 regD tmpD; 10084 convI2L_reg(tmpL, src); // Sign-extension int to long. 10085 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10086 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10087 convL2FRaw_regF(dst, tmpD); // Convert to float. 10088 %} 10089 %} 10090 10091 // L2F to avoid runtime call. 10092 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ 10093 match(Set dst (ConvL2F src)); 10094 predicate(VM_Version::has_fcfids()); 10095 ins_cost(DEFAULT_COST); 10096 10097 expand %{ 10098 stackSlotL tmpS; 10099 regD tmpD; 10100 regL_to_stkL(tmpS, src); // Store long to stack. 10101 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10102 convL2FRaw_regF(dst, tmpD); // Convert to float. 10103 %} 10104 %} 10105 10106 // Moved up as used in expand. 10107 //instruct convD2F_reg(regF dst, regD src) %{%} 10108 10109 // Convert to Double 10110 10111 // Integer to Double conversion. 10112 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ 10113 match(Set dst (ConvI2D src)); 10114 ins_cost(DEFAULT_COST); 10115 10116 expand %{ 10117 iRegLdst tmpL; 10118 stackSlotL tmpS; 10119 regD tmpD; 10120 convI2L_reg(tmpL, src); // Sign-extension int to long. 10121 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10122 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10123 convL2DRaw_regD(dst, tmpD); // Convert to double. 10124 %} 10125 %} 10126 10127 // Long to Double conversion 10128 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ 10129 match(Set dst (ConvL2D src)); 10130 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10131 10132 expand %{ 10133 regD tmpD; 10134 moveL2D_stack_reg(tmpD, src); 10135 convL2DRaw_regD(dst, tmpD); 10136 %} 10137 %} 10138 10139 instruct convF2D_reg(regD dst, regF src) %{ 10140 match(Set dst (ConvF2D src)); 10141 format %{ "FMR $dst, $src \t// float->double" %} 10142 // variable size, 0 or 4 10143 ins_encode %{ 10144 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 10145 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); 10146 %} 10147 ins_pipe(pipe_class_default); 10148 %} 10149 10150 //----------Control Flow Instructions------------------------------------------ 10151 // Compare Instructions 10152 10153 // Compare Integers 10154 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10155 match(Set crx (CmpI src1 src2)); 10156 size(4); 10157 format %{ "CMPW $crx, $src1, $src2" %} 10158 ins_encode %{ 10159 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10160 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10161 %} 10162 ins_pipe(pipe_class_compare); 10163 %} 10164 10165 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ 10166 match(Set crx (CmpI src1 src2)); 10167 format %{ "CMPWI $crx, $src1, $src2" %} 10168 size(4); 10169 ins_encode %{ 10170 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10171 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10172 %} 10173 ins_pipe(pipe_class_compare); 10174 %} 10175 10176 // (src1 & src2) == 0? 10177 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ 10178 match(Set cr0 (CmpI (AndI src1 src2) zero)); 10179 // r0 is killed 10180 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} 10181 size(4); 10182 ins_encode %{ 10183 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10184 __ andi_(R0, $src1$$Register, $src2$$constant); 10185 %} 10186 ins_pipe(pipe_class_compare); 10187 %} 10188 10189 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ 10190 match(Set crx (CmpL src1 src2)); 10191 format %{ "CMPD $crx, $src1, $src2" %} 10192 size(4); 10193 ins_encode %{ 10194 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10195 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); 10196 %} 10197 ins_pipe(pipe_class_compare); 10198 %} 10199 10200 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ 10201 match(Set crx (CmpL src1 src2)); 10202 format %{ "CMPDI $crx, $src1, $src2" %} 10203 size(4); 10204 ins_encode %{ 10205 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10206 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10207 %} 10208 ins_pipe(pipe_class_compare); 10209 %} 10210 10211 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ 10212 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10213 // r0 is killed 10214 format %{ "AND R0, $src1, $src2 \t// BTST long" %} 10215 size(4); 10216 ins_encode %{ 10217 // TODO: PPC port $archOpcode(ppc64Opcode_and_); 10218 __ and_(R0, $src1$$Register, $src2$$Register); 10219 %} 10220 ins_pipe(pipe_class_compare); 10221 %} 10222 10223 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ 10224 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10225 // r0 is killed 10226 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} 10227 size(4); 10228 ins_encode %{ 10229 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10230 __ andi_(R0, $src1$$Register, $src2$$constant); 10231 %} 10232 ins_pipe(pipe_class_compare); 10233 %} 10234 10235 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{ 10236 // no match-rule, false predicate 10237 effect(DEF dst, USE crx); 10238 predicate(false); 10239 10240 ins_variable_size_depending_on_alignment(true); 10241 10242 format %{ "cmovI $crx, $dst, -1, 0, +1" %} 10243 // Worst case is branch + move + branch + move + stop, no stop without scheduler. 10244 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); 10245 ins_encode %{ 10246 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 10247 Label done; 10248 // li(Rdst, 0); // equal -> 0 10249 __ beq($crx$$CondRegister, done); 10250 __ li($dst$$Register, 1); // greater -> +1 10251 __ bgt($crx$$CondRegister, done); 10252 __ li($dst$$Register, -1); // unordered or less -> -1 10253 // TODO: PPC port__ endgroup_if_needed(_size == 20); 10254 __ bind(done); 10255 %} 10256 ins_pipe(pipe_class_compare); 10257 %} 10258 10259 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{ 10260 // no match-rule, false predicate 10261 effect(DEF dst, USE crx); 10262 predicate(false); 10263 10264 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} 10265 postalloc_expand %{ 10266 // 10267 // replaces 10268 // 10269 // region crx 10270 // \ | 10271 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 10272 // 10273 // with 10274 // 10275 // region 10276 // \ 10277 // dst=loadConI16(0) 10278 // | 10279 // ^ region crx 10280 // | \ | 10281 // dst=cmovI_conIvalueMinus1_conIvalue1 10282 // 10283 10284 // Create new nodes. 10285 MachNode *m1 = new loadConI16Node(); 10286 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node(); 10287 10288 // inputs for new nodes 10289 m1->add_req(n_region); 10290 m2->add_req(n_region, n_crx); 10291 m2->add_prec(m1); 10292 10293 // operands for new nodes 10294 m1->_opnds[0] = op_dst; 10295 m1->_opnds[1] = new immI16Oper(0); 10296 m2->_opnds[0] = op_dst; 10297 m2->_opnds[1] = op_crx; 10298 10299 // registers for new nodes 10300 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10301 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10302 10303 // Insert new nodes. 10304 nodes->push(m1); 10305 nodes->push(m2); 10306 %} 10307 %} 10308 10309 // Manifest a CmpL3 result in an integer register. Very painful. 10310 // This is the test to avoid. 10311 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) 10312 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 10313 match(Set dst (CmpL3 src1 src2)); 10314 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10315 10316 expand %{ 10317 flagsReg tmp1; 10318 cmpL_reg_reg(tmp1, src1, src2); 10319 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10320 %} 10321 %} 10322 10323 // Implicit range checks. 10324 // A range check in the ideal world has one of the following shapes: 10325 // - (If le (CmpU length index)), (IfTrue throw exception) 10326 // - (If lt (CmpU index length)), (IfFalse throw exception) 10327 // 10328 // Match range check 'If le (CmpU length index)'. 10329 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ 10330 match(If cmp (CmpU src_length index)); 10331 effect(USE labl); 10332 predicate(TrapBasedRangeChecks && 10333 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 10334 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && 10335 (Matcher::branches_to_uncommon_trap(_leaf))); 10336 10337 ins_is_TrapBasedCheckNode(true); 10338 10339 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} 10340 size(4); 10341 ins_encode %{ 10342 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10343 if ($cmp$$cmpcode == 0x1 /* less_equal */) { 10344 __ trap_range_check_le($src_length$$Register, $index$$constant); 10345 } else { 10346 // Both successors are uncommon traps, probability is 0. 10347 // Node got flipped during fixup flow. 10348 assert($cmp$$cmpcode == 0x9, "must be greater"); 10349 __ trap_range_check_g($src_length$$Register, $index$$constant); 10350 } 10351 %} 10352 ins_pipe(pipe_class_trap); 10353 %} 10354 10355 // Match range check 'If lt (CmpU index length)'. 10356 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ 10357 match(If cmp (CmpU src_index src_length)); 10358 effect(USE labl); 10359 predicate(TrapBasedRangeChecks && 10360 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10361 _leaf->as_If()->_prob >= PROB_ALWAYS && 10362 (Matcher::branches_to_uncommon_trap(_leaf))); 10363 10364 ins_is_TrapBasedCheckNode(true); 10365 10366 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} 10367 size(4); 10368 ins_encode %{ 10369 // TODO: PPC port $archOpcode(ppc64Opcode_tw); 10370 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10371 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); 10372 } else { 10373 // Both successors are uncommon traps, probability is 0. 10374 // Node got flipped during fixup flow. 10375 assert($cmp$$cmpcode == 0x8, "must be less"); 10376 __ trap_range_check_l($src_index$$Register, $src_length$$Register); 10377 } 10378 %} 10379 ins_pipe(pipe_class_trap); 10380 %} 10381 10382 // Match range check 'If lt (CmpU index length)'. 10383 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ 10384 match(If cmp (CmpU src_index length)); 10385 effect(USE labl); 10386 predicate(TrapBasedRangeChecks && 10387 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10388 _leaf->as_If()->_prob >= PROB_ALWAYS && 10389 (Matcher::branches_to_uncommon_trap(_leaf))); 10390 10391 ins_is_TrapBasedCheckNode(true); 10392 10393 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} 10394 size(4); 10395 ins_encode %{ 10396 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10397 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10398 __ trap_range_check_ge($src_index$$Register, $length$$constant); 10399 } else { 10400 // Both successors are uncommon traps, probability is 0. 10401 // Node got flipped during fixup flow. 10402 assert($cmp$$cmpcode == 0x8, "must be less"); 10403 __ trap_range_check_l($src_index$$Register, $length$$constant); 10404 } 10405 %} 10406 ins_pipe(pipe_class_trap); 10407 %} 10408 10409 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10410 match(Set crx (CmpU src1 src2)); 10411 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} 10412 size(4); 10413 ins_encode %{ 10414 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10415 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10416 %} 10417 ins_pipe(pipe_class_compare); 10418 %} 10419 10420 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ 10421 match(Set crx (CmpU src1 src2)); 10422 size(4); 10423 format %{ "CMPLWI $crx, $src1, $src2" %} 10424 ins_encode %{ 10425 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10426 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10427 %} 10428 ins_pipe(pipe_class_compare); 10429 %} 10430 10431 // Implicit zero checks (more implicit null checks). 10432 // No constant pool entries required. 10433 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ 10434 match(If cmp (CmpN value zero)); 10435 effect(USE labl); 10436 predicate(TrapBasedNullChecks && 10437 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10438 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10439 Matcher::branches_to_uncommon_trap(_leaf)); 10440 ins_cost(1); 10441 10442 ins_is_TrapBasedCheckNode(true); 10443 10444 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} 10445 size(4); 10446 ins_encode %{ 10447 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10448 if ($cmp$$cmpcode == 0xA) { 10449 __ trap_null_check($value$$Register); 10450 } else { 10451 // Both successors are uncommon traps, probability is 0. 10452 // Node got flipped during fixup flow. 10453 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10454 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10455 } 10456 %} 10457 ins_pipe(pipe_class_trap); 10458 %} 10459 10460 // Compare narrow oops. 10461 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ 10462 match(Set crx (CmpN src1 src2)); 10463 10464 size(4); 10465 ins_cost(2); 10466 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} 10467 ins_encode %{ 10468 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10469 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10470 %} 10471 ins_pipe(pipe_class_compare); 10472 %} 10473 10474 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ 10475 match(Set crx (CmpN src1 src2)); 10476 // Make this more expensive than zeroCheckN_iReg_imm0. 10477 ins_cost(2); 10478 10479 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} 10480 size(4); 10481 ins_encode %{ 10482 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10483 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10484 %} 10485 ins_pipe(pipe_class_compare); 10486 %} 10487 10488 // Implicit zero checks (more implicit null checks). 10489 // No constant pool entries required. 10490 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ 10491 match(If cmp (CmpP value zero)); 10492 effect(USE labl); 10493 predicate(TrapBasedNullChecks && 10494 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10495 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10496 Matcher::branches_to_uncommon_trap(_leaf)); 10497 ins_cost(1); // Should not be cheaper than zeroCheckN. 10498 10499 ins_is_TrapBasedCheckNode(true); 10500 10501 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} 10502 size(4); 10503 ins_encode %{ 10504 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10505 if ($cmp$$cmpcode == 0xA) { 10506 __ trap_null_check($value$$Register); 10507 } else { 10508 // Both successors are uncommon traps, probability is 0. 10509 // Node got flipped during fixup flow. 10510 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10511 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10512 } 10513 %} 10514 ins_pipe(pipe_class_trap); 10515 %} 10516 10517 // Compare Pointers 10518 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ 10519 match(Set crx (CmpP src1 src2)); 10520 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} 10521 size(4); 10522 ins_encode %{ 10523 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10524 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); 10525 %} 10526 ins_pipe(pipe_class_compare); 10527 %} 10528 10529 // Used in postalloc expand. 10530 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ 10531 // This match rule prevents reordering of node before a safepoint. 10532 // This only makes sense if this instructions is used exclusively 10533 // for the expansion of EncodeP! 10534 match(Set crx (CmpP src1 src2)); 10535 predicate(false); 10536 10537 format %{ "CMPDI $crx, $src1, $src2" %} 10538 size(4); 10539 ins_encode %{ 10540 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10541 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10542 %} 10543 ins_pipe(pipe_class_compare); 10544 %} 10545 10546 //----------Float Compares---------------------------------------------------- 10547 10548 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ 10549 // Needs matchrule, see cmpDUnordered. 10550 match(Set crx (CmpF src1 src2)); 10551 // no match-rule, false predicate 10552 predicate(false); 10553 10554 format %{ "cmpFUrd $crx, $src1, $src2" %} 10555 size(4); 10556 ins_encode %{ 10557 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10558 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10559 %} 10560 ins_pipe(pipe_class_default); 10561 %} 10562 10563 instruct cmov_bns_less(flagsReg crx) %{ 10564 // no match-rule, false predicate 10565 effect(DEF crx); 10566 predicate(false); 10567 10568 ins_variable_size_depending_on_alignment(true); 10569 10570 format %{ "cmov $crx" %} 10571 // Worst case is branch + move + stop, no stop without scheduler. 10572 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); 10573 ins_encode %{ 10574 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); 10575 Label done; 10576 __ bns($crx$$CondRegister, done); // not unordered -> keep crx 10577 __ li(R0, 0); 10578 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' 10579 // TODO PPC port __ endgroup_if_needed(_size == 16); 10580 __ bind(done); 10581 %} 10582 ins_pipe(pipe_class_default); 10583 %} 10584 10585 // Compare floating, generate condition code. 10586 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ 10587 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? 10588 // 10589 // The following code sequence occurs a lot in mpegaudio: 10590 // 10591 // block BXX: 10592 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): 10593 // cmpFUrd CCR6, F11, F9 10594 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): 10595 // cmov CCR6 10596 // 8: instruct branchConSched: 10597 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 10598 match(Set crx (CmpF src1 src2)); 10599 ins_cost(DEFAULT_COST+BRANCH_COST); 10600 10601 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} 10602 postalloc_expand %{ 10603 // 10604 // replaces 10605 // 10606 // region src1 src2 10607 // \ | | 10608 // crx=cmpF_reg_reg 10609 // 10610 // with 10611 // 10612 // region src1 src2 10613 // \ | | 10614 // crx=cmpFUnordered_reg_reg 10615 // | 10616 // ^ region 10617 // | \ 10618 // crx=cmov_bns_less 10619 // 10620 10621 // Create new nodes. 10622 MachNode *m1 = new cmpFUnordered_reg_regNode(); 10623 MachNode *m2 = new cmov_bns_lessNode(); 10624 10625 // inputs for new nodes 10626 m1->add_req(n_region, n_src1, n_src2); 10627 m2->add_req(n_region); 10628 m2->add_prec(m1); 10629 10630 // operands for new nodes 10631 m1->_opnds[0] = op_crx; 10632 m1->_opnds[1] = op_src1; 10633 m1->_opnds[2] = op_src2; 10634 m2->_opnds[0] = op_crx; 10635 10636 // registers for new nodes 10637 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10638 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10639 10640 // Insert new nodes. 10641 nodes->push(m1); 10642 nodes->push(m2); 10643 %} 10644 %} 10645 10646 // Compare float, generate -1,0,1 10647 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ 10648 match(Set dst (CmpF3 src1 src2)); 10649 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10650 10651 expand %{ 10652 flagsReg tmp1; 10653 cmpFUnordered_reg_reg(tmp1, src1, src2); 10654 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10655 %} 10656 %} 10657 10658 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ 10659 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the 10660 // node right before the conditional move using it. 10661 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7, 10662 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle 10663 // crashed in register allocation where the flags Reg between cmpDUnoredered and a 10664 // conditional move was supposed to be spilled. 10665 match(Set crx (CmpD src1 src2)); 10666 // False predicate, shall not be matched. 10667 predicate(false); 10668 10669 format %{ "cmpFUrd $crx, $src1, $src2" %} 10670 size(4); 10671 ins_encode %{ 10672 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10673 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10674 %} 10675 ins_pipe(pipe_class_default); 10676 %} 10677 10678 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ 10679 match(Set crx (CmpD src1 src2)); 10680 ins_cost(DEFAULT_COST+BRANCH_COST); 10681 10682 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} 10683 postalloc_expand %{ 10684 // 10685 // replaces 10686 // 10687 // region src1 src2 10688 // \ | | 10689 // crx=cmpD_reg_reg 10690 // 10691 // with 10692 // 10693 // region src1 src2 10694 // \ | | 10695 // crx=cmpDUnordered_reg_reg 10696 // | 10697 // ^ region 10698 // | \ 10699 // crx=cmov_bns_less 10700 // 10701 10702 // create new nodes 10703 MachNode *m1 = new cmpDUnordered_reg_regNode(); 10704 MachNode *m2 = new cmov_bns_lessNode(); 10705 10706 // inputs for new nodes 10707 m1->add_req(n_region, n_src1, n_src2); 10708 m2->add_req(n_region); 10709 m2->add_prec(m1); 10710 10711 // operands for new nodes 10712 m1->_opnds[0] = op_crx; 10713 m1->_opnds[1] = op_src1; 10714 m1->_opnds[2] = op_src2; 10715 m2->_opnds[0] = op_crx; 10716 10717 // registers for new nodes 10718 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10719 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10720 10721 // Insert new nodes. 10722 nodes->push(m1); 10723 nodes->push(m2); 10724 %} 10725 %} 10726 10727 // Compare double, generate -1,0,1 10728 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ 10729 match(Set dst (CmpD3 src1 src2)); 10730 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10731 10732 expand %{ 10733 flagsReg tmp1; 10734 cmpDUnordered_reg_reg(tmp1, src1, src2); 10735 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10736 %} 10737 %} 10738 10739 //----------Branches--------------------------------------------------------- 10740 // Jump 10741 10742 // Direct Branch. 10743 instruct branch(label labl) %{ 10744 match(Goto); 10745 effect(USE labl); 10746 ins_cost(BRANCH_COST); 10747 10748 format %{ "B $labl" %} 10749 size(4); 10750 ins_encode %{ 10751 // TODO: PPC port $archOpcode(ppc64Opcode_b); 10752 Label d; // dummy 10753 __ bind(d); 10754 Label* p = $labl$$label; 10755 // `p' is `NULL' when this encoding class is used only to 10756 // determine the size of the encoded instruction. 10757 Label& l = (NULL == p)? d : *(p); 10758 __ b(l); 10759 %} 10760 ins_pipe(pipe_class_default); 10761 %} 10762 10763 // Conditional Near Branch 10764 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10765 // Same match rule as `branchConFar'. 10766 match(If cmp crx); 10767 effect(USE lbl); 10768 ins_cost(BRANCH_COST); 10769 10770 // If set to 1 this indicates that the current instruction is a 10771 // short variant of a long branch. This avoids using this 10772 // instruction in first-pass matching. It will then only be used in 10773 // the `Shorten_branches' pass. 10774 ins_short_branch(1); 10775 10776 format %{ "B$cmp $crx, $lbl" %} 10777 size(4); 10778 ins_encode( enc_bc(crx, cmp, lbl) ); 10779 ins_pipe(pipe_class_default); 10780 %} 10781 10782 // This is for cases when the ppc64 `bc' instruction does not 10783 // reach far enough. So we emit a far branch here, which is more 10784 // expensive. 10785 // 10786 // Conditional Far Branch 10787 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10788 // Same match rule as `branchCon'. 10789 match(If cmp crx); 10790 effect(USE crx, USE lbl); 10791 predicate(!false /* TODO: PPC port HB_Schedule*/); 10792 // Higher cost than `branchCon'. 10793 ins_cost(5*BRANCH_COST); 10794 10795 // This is not a short variant of a branch, but the long variant. 10796 ins_short_branch(0); 10797 10798 format %{ "B_FAR$cmp $crx, $lbl" %} 10799 size(8); 10800 ins_encode( enc_bc_far(crx, cmp, lbl) ); 10801 ins_pipe(pipe_class_default); 10802 %} 10803 10804 // Conditional Branch used with Power6 scheduler (can be far or short). 10805 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10806 // Same match rule as `branchCon'. 10807 match(If cmp crx); 10808 effect(USE crx, USE lbl); 10809 predicate(false /* TODO: PPC port HB_Schedule*/); 10810 // Higher cost than `branchCon'. 10811 ins_cost(5*BRANCH_COST); 10812 10813 // Actually size doesn't depend on alignment but on shortening. 10814 ins_variable_size_depending_on_alignment(true); 10815 // long variant. 10816 ins_short_branch(0); 10817 10818 format %{ "B_FAR$cmp $crx, $lbl" %} 10819 size(8); // worst case 10820 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); 10821 ins_pipe(pipe_class_default); 10822 %} 10823 10824 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10825 match(CountedLoopEnd cmp crx); 10826 effect(USE labl); 10827 ins_cost(BRANCH_COST); 10828 10829 // short variant. 10830 ins_short_branch(1); 10831 10832 format %{ "B$cmp $crx, $labl \t// counted loop end" %} 10833 size(4); 10834 ins_encode( enc_bc(crx, cmp, labl) ); 10835 ins_pipe(pipe_class_default); 10836 %} 10837 10838 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10839 match(CountedLoopEnd cmp crx); 10840 effect(USE labl); 10841 predicate(!false /* TODO: PPC port HB_Schedule */); 10842 ins_cost(BRANCH_COST); 10843 10844 // Long variant. 10845 ins_short_branch(0); 10846 10847 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10848 size(8); 10849 ins_encode( enc_bc_far(crx, cmp, labl) ); 10850 ins_pipe(pipe_class_default); 10851 %} 10852 10853 // Conditional Branch used with Power6 scheduler (can be far or short). 10854 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10855 match(CountedLoopEnd cmp crx); 10856 effect(USE labl); 10857 predicate(false /* TODO: PPC port HB_Schedule */); 10858 // Higher cost than `branchCon'. 10859 ins_cost(5*BRANCH_COST); 10860 10861 // Actually size doesn't depend on alignment but on shortening. 10862 ins_variable_size_depending_on_alignment(true); 10863 // Long variant. 10864 ins_short_branch(0); 10865 10866 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10867 size(8); // worst case 10868 ins_encode( enc_bc_short_far(crx, cmp, labl) ); 10869 ins_pipe(pipe_class_default); 10870 %} 10871 10872 // ============================================================================ 10873 // Java runtime operations, intrinsics and other complex operations. 10874 10875 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10876 // array for an instance of the superklass. Set a hidden internal cache on a 10877 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10878 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10879 // 10880 // GL TODO: Improve this. 10881 // - result should not be a TEMP 10882 // - Add match rule as on sparc avoiding additional Cmp. 10883 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, 10884 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ 10885 match(Set result (PartialSubtypeCheck subklass superklass)); 10886 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr); 10887 ins_cost(DEFAULT_COST*10); 10888 10889 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} 10890 ins_encode %{ 10891 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10892 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 10893 $tmp_klass$$Register, NULL, $result$$Register); 10894 %} 10895 ins_pipe(pipe_class_default); 10896 %} 10897 10898 // inlined locking and unlocking 10899 10900 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{ 10901 match(Set crx (FastLock oop box)); 10902 effect(TEMP tmp1, TEMP tmp2); 10903 predicate(!Compile::current()->use_rtm()); 10904 10905 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2" %} 10906 ins_encode %{ 10907 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10908 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10909 $tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0, 10910 UseBiasedLocking && !UseOptoBiasInlining); 10911 // If locking was successfull, crx should indicate 'EQ'. 10912 // The compiler generates a branch to the runtime call to 10913 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10914 %} 10915 ins_pipe(pipe_class_compare); 10916 %} 10917 10918 // Separate version for TM. Use bound register for box to enable USE_KILL. 10919 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10920 match(Set crx (FastLock oop box)); 10921 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box); 10922 predicate(Compile::current()->use_rtm()); 10923 10924 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %} 10925 ins_encode %{ 10926 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10927 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10928 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10929 /*Biased Locking*/ false, 10930 _rtm_counters, _stack_rtm_counters, 10931 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), 10932 /*TM*/ true, ra_->C->profile_rtm()); 10933 // If locking was successfull, crx should indicate 'EQ'. 10934 // The compiler generates a branch to the runtime call to 10935 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10936 %} 10937 ins_pipe(pipe_class_compare); 10938 %} 10939 10940 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10941 match(Set crx (FastUnlock oop box)); 10942 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10943 predicate(!Compile::current()->use_rtm()); 10944 10945 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} 10946 ins_encode %{ 10947 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10948 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10949 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10950 UseBiasedLocking && !UseOptoBiasInlining, 10951 false); 10952 // If unlocking was successfull, crx should indicate 'EQ'. 10953 // The compiler generates a branch to the runtime call to 10954 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10955 %} 10956 ins_pipe(pipe_class_compare); 10957 %} 10958 10959 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10960 match(Set crx (FastUnlock oop box)); 10961 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10962 predicate(Compile::current()->use_rtm()); 10963 10964 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %} 10965 ins_encode %{ 10966 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10967 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10968 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10969 /*Biased Locking*/ false, /*TM*/ true); 10970 // If unlocking was successfull, crx should indicate 'EQ'. 10971 // The compiler generates a branch to the runtime call to 10972 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10973 %} 10974 ins_pipe(pipe_class_compare); 10975 %} 10976 10977 // Align address. 10978 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ 10979 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 10980 10981 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} 10982 size(4); 10983 ins_encode %{ 10984 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 10985 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); 10986 %} 10987 ins_pipe(pipe_class_default); 10988 %} 10989 10990 // Array size computation. 10991 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ 10992 match(Set dst (SubL (CastP2X end) (CastP2X start))); 10993 10994 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} 10995 size(4); 10996 ins_encode %{ 10997 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 10998 __ subf($dst$$Register, $start$$Register, $end$$Register); 10999 %} 11000 ins_pipe(pipe_class_default); 11001 %} 11002 11003 // Clear-array with dynamic array-size. 11004 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ 11005 match(Set dummy (ClearArray cnt base)); 11006 effect(USE_KILL cnt, USE_KILL base, KILL ctr); 11007 ins_cost(MEMORY_REF_COST); 11008 11009 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11010 11011 format %{ "ClearArray $cnt, $base" %} 11012 ins_encode %{ 11013 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11014 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 11015 %} 11016 ins_pipe(pipe_class_default); 11017 %} 11018 11019 // String_IndexOf for needle of length 1. 11020 // 11021 // Match needle into immediate operands: no loadConP node needed. Saves one 11022 // register and two instructions over string_indexOf_imm1Node. 11023 // 11024 // Assumes register result differs from all input registers. 11025 // 11026 // Preserves registers haystack, haycnt 11027 // Kills registers tmp1, tmp2 11028 // Defines registers result 11029 // 11030 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11031 // 11032 // Unfortunately this does not match too often. In many situations the AddP is used 11033 // by several nodes, even several StrIndexOf nodes, breaking the match tree. 11034 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11035 immP needleImm, immL offsetImm, immI_1 needlecntImm, 11036 iRegIdst tmp1, iRegIdst tmp2, 11037 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11038 predicate(SpecialStringIndexOf && !CompactStrings); // type check implicit by parameter type, See Matcher::match_rule_supported 11039 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11040 11041 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1); 11042 11043 ins_cost(150); 11044 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11045 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11046 11047 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted 11048 ins_encode %{ 11049 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11050 immPOper *needleOper = (immPOper *)$needleImm; 11051 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11052 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11053 11054 __ string_indexof_1($result$$Register, 11055 $haystack$$Register, $haycnt$$Register, 11056 R0, needle_values->char_at(0), 11057 $tmp1$$Register, $tmp2$$Register); 11058 %} 11059 ins_pipe(pipe_class_compare); 11060 %} 11061 11062 // String_IndexOf for needle of length 1. 11063 // 11064 // Special case requires less registers and emits less instructions. 11065 // 11066 // Assumes register result differs from all input registers. 11067 // 11068 // Preserves registers haystack, haycnt 11069 // Kills registers tmp1, tmp2, needle 11070 // Defines registers result 11071 // 11072 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11073 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11074 rscratch2RegP needle, immI_1 needlecntImm, 11075 iRegIdst tmp1, iRegIdst tmp2, 11076 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11077 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11078 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result, 11079 TEMP tmp1, TEMP tmp2); 11080 // Required for EA: check if it is still a type_array. 11081 predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11082 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11083 ins_cost(180); 11084 11085 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11086 11087 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11088 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11089 ins_encode %{ 11090 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11091 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11092 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11093 guarantee(needle_values, "sanity"); 11094 if (needle_values != NULL) { 11095 __ string_indexof_1($result$$Register, 11096 $haystack$$Register, $haycnt$$Register, 11097 R0, needle_values->char_at(0), 11098 $tmp1$$Register, $tmp2$$Register); 11099 } else { 11100 __ string_indexof_1($result$$Register, 11101 $haystack$$Register, $haycnt$$Register, 11102 $needle$$Register, 0, 11103 $tmp1$$Register, $tmp2$$Register); 11104 } 11105 %} 11106 ins_pipe(pipe_class_compare); 11107 %} 11108 11109 // String_IndexOf. 11110 // 11111 // Length of needle as immediate. This saves instruction loading constant needle 11112 // length. 11113 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle 11114 // completely or do it in vector instruction. This should save registers for 11115 // needlecnt and needle. 11116 // 11117 // Assumes register result differs from all input registers. 11118 // Overwrites haycnt, needlecnt. 11119 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11120 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11121 iRegPsrc needle, uimmI15 needlecntImm, 11122 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11123 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11124 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11125 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result, 11126 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6); 11127 // Required for EA: check if it is still a type_array. 11128 predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11129 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11130 ins_cost(250); 11131 11132 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11133 11134 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11135 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11136 ins_encode %{ 11137 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11138 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11139 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11140 11141 __ string_indexof($result$$Register, 11142 $haystack$$Register, $haycnt$$Register, 11143 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11144 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11145 %} 11146 ins_pipe(pipe_class_compare); 11147 %} 11148 11149 // StrIndexOf node. 11150 // 11151 // Assumes register result differs from all input registers. 11152 // Overwrites haycnt, needlecnt. 11153 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11154 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11155 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11156 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11157 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11158 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11159 TEMP_DEF result, 11160 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6); 11161 predicate(SpecialStringIndexOf && !CompactStrings); // See Matcher::match_rule_supported. 11162 ins_cost(300); 11163 11164 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11165 11166 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11167 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11168 ins_encode %{ 11169 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11170 __ string_indexof($result$$Register, 11171 $haystack$$Register, $haycnt$$Register, 11172 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11173 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11174 %} 11175 ins_pipe(pipe_class_compare); 11176 %} 11177 11178 // String equals with immediate. 11179 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, 11180 iRegPdst tmp1, iRegPdst tmp2, 11181 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ 11182 match(Set result (StrEquals (Binary str1 str2) cntImm)); 11183 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, 11184 KILL cr0, KILL cr6, KILL ctr); 11185 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported. 11186 ins_cost(250); 11187 11188 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11189 11190 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" 11191 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} 11192 ins_encode %{ 11193 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11194 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, 11195 $result$$Register, $tmp1$$Register, $tmp2$$Register); 11196 %} 11197 ins_pipe(pipe_class_compare); 11198 %} 11199 11200 // String equals. 11201 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11202 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, 11203 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, 11204 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11205 match(Set result (StrEquals (Binary str1 str2) cnt)); 11206 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11207 KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11208 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported. 11209 ins_cost(300); 11210 11211 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11212 11213 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" 11214 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11215 ins_encode %{ 11216 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11217 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, 11218 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); 11219 %} 11220 ins_pipe(pipe_class_compare); 11221 %} 11222 11223 // String compare. 11224 // Char[] pointers are passed in. 11225 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11226 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11227 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ 11228 predicate(!CompactStrings); 11229 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11230 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr); 11231 ins_cost(300); 11232 11233 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11234 11235 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" 11236 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} 11237 ins_encode %{ 11238 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11239 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, 11240 $result$$Register, $tmp$$Register); 11241 %} 11242 ins_pipe(pipe_class_compare); 11243 %} 11244 11245 //---------- Min/Max Instructions --------------------------------------------- 11246 11247 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11248 match(Set dst (MinI src1 src2)); 11249 ins_cost(DEFAULT_COST*6); 11250 11251 expand %{ 11252 iRegLdst src1s; 11253 iRegLdst src2s; 11254 iRegLdst diff; 11255 iRegLdst sm; 11256 iRegLdst doz; // difference or zero 11257 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11258 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11259 subL_reg_reg(diff, src2s, src1s); 11260 // Need to consider >=33 bit result, therefore we need signmaskL. 11261 signmask64L_regL(sm, diff); 11262 andL_reg_reg(doz, diff, sm); // <=0 11263 addI_regL_regL(dst, doz, src1s); 11264 %} 11265 %} 11266 11267 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11268 match(Set dst (MaxI src1 src2)); 11269 ins_cost(DEFAULT_COST*6); 11270 11271 expand %{ 11272 iRegLdst src1s; 11273 iRegLdst src2s; 11274 iRegLdst diff; 11275 iRegLdst sm; 11276 iRegLdst doz; // difference or zero 11277 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11278 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11279 subL_reg_reg(diff, src2s, src1s); 11280 // Need to consider >=33 bit result, therefore we need signmaskL. 11281 signmask64L_regL(sm, diff); 11282 andcL_reg_reg(doz, diff, sm); // >=0 11283 addI_regL_regL(dst, doz, src1s); 11284 %} 11285 %} 11286 11287 //---------- Population Count Instructions ------------------------------------ 11288 11289 // Popcnt for Power7. 11290 instruct popCountI(iRegIdst dst, iRegIsrc src) %{ 11291 match(Set dst (PopCountI src)); 11292 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11293 ins_cost(DEFAULT_COST); 11294 11295 format %{ "POPCNTW $dst, $src" %} 11296 size(4); 11297 ins_encode %{ 11298 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11299 __ popcntw($dst$$Register, $src$$Register); 11300 %} 11301 ins_pipe(pipe_class_default); 11302 %} 11303 11304 // Popcnt for Power7. 11305 instruct popCountL(iRegIdst dst, iRegLsrc src) %{ 11306 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11307 match(Set dst (PopCountL src)); 11308 ins_cost(DEFAULT_COST); 11309 11310 format %{ "POPCNTD $dst, $src" %} 11311 size(4); 11312 ins_encode %{ 11313 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11314 __ popcntd($dst$$Register, $src$$Register); 11315 %} 11316 ins_pipe(pipe_class_default); 11317 %} 11318 11319 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ 11320 match(Set dst (CountLeadingZerosI src)); 11321 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11322 ins_cost(DEFAULT_COST); 11323 11324 format %{ "CNTLZW $dst, $src" %} 11325 size(4); 11326 ins_encode %{ 11327 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); 11328 __ cntlzw($dst$$Register, $src$$Register); 11329 %} 11330 ins_pipe(pipe_class_default); 11331 %} 11332 11333 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ 11334 match(Set dst (CountLeadingZerosL src)); 11335 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11336 ins_cost(DEFAULT_COST); 11337 11338 format %{ "CNTLZD $dst, $src" %} 11339 size(4); 11340 ins_encode %{ 11341 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11342 __ cntlzd($dst$$Register, $src$$Register); 11343 %} 11344 ins_pipe(pipe_class_default); 11345 %} 11346 11347 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ 11348 // no match-rule, false predicate 11349 effect(DEF dst, USE src); 11350 predicate(false); 11351 11352 format %{ "CNTLZD $dst, $src" %} 11353 size(4); 11354 ins_encode %{ 11355 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11356 __ cntlzd($dst$$Register, $src$$Register); 11357 %} 11358 ins_pipe(pipe_class_default); 11359 %} 11360 11361 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ 11362 match(Set dst (CountTrailingZerosI src)); 11363 predicate(UseCountLeadingZerosInstructionsPPC64); 11364 ins_cost(DEFAULT_COST); 11365 11366 expand %{ 11367 immI16 imm1 %{ (int)-1 %} 11368 immI16 imm2 %{ (int)32 %} 11369 immI_minus1 m1 %{ -1 %} 11370 iRegIdst tmpI1; 11371 iRegIdst tmpI2; 11372 iRegIdst tmpI3; 11373 addI_reg_imm16(tmpI1, src, imm1); 11374 andcI_reg_reg(tmpI2, src, m1, tmpI1); 11375 countLeadingZerosI(tmpI3, tmpI2); 11376 subI_imm16_reg(dst, imm2, tmpI3); 11377 %} 11378 %} 11379 11380 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ 11381 match(Set dst (CountTrailingZerosL src)); 11382 predicate(UseCountLeadingZerosInstructionsPPC64); 11383 ins_cost(DEFAULT_COST); 11384 11385 expand %{ 11386 immL16 imm1 %{ (long)-1 %} 11387 immI16 imm2 %{ (int)64 %} 11388 iRegLdst tmpL1; 11389 iRegLdst tmpL2; 11390 iRegIdst tmpL3; 11391 addL_reg_imm16(tmpL1, src, imm1); 11392 andcL_reg_reg(tmpL2, tmpL1, src); 11393 countLeadingZerosL(tmpL3, tmpL2); 11394 subI_imm16_reg(dst, imm2, tmpL3); 11395 %} 11396 %} 11397 11398 // Expand nodes for byte_reverse_int. 11399 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11400 effect(DEF dst, USE src, USE pos, USE shift); 11401 predicate(false); 11402 11403 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11404 size(4); 11405 ins_encode %{ 11406 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11407 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11408 %} 11409 ins_pipe(pipe_class_default); 11410 %} 11411 11412 // As insrwi_a, but with USE_DEF. 11413 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11414 effect(USE_DEF dst, USE src, USE pos, USE shift); 11415 predicate(false); 11416 11417 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11418 size(4); 11419 ins_encode %{ 11420 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11421 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11422 %} 11423 ins_pipe(pipe_class_default); 11424 %} 11425 11426 // Just slightly faster than java implementation. 11427 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ 11428 match(Set dst (ReverseBytesI src)); 11429 predicate(UseCountLeadingZerosInstructionsPPC64); 11430 ins_cost(DEFAULT_COST); 11431 11432 expand %{ 11433 immI16 imm24 %{ (int) 24 %} 11434 immI16 imm16 %{ (int) 16 %} 11435 immI16 imm8 %{ (int) 8 %} 11436 immI16 imm4 %{ (int) 4 %} 11437 immI16 imm0 %{ (int) 0 %} 11438 iRegLdst tmpI1; 11439 iRegLdst tmpI2; 11440 iRegLdst tmpI3; 11441 11442 urShiftI_reg_imm(tmpI1, src, imm24); 11443 insrwi_a(dst, tmpI1, imm24, imm8); 11444 urShiftI_reg_imm(tmpI2, src, imm16); 11445 insrwi(dst, tmpI2, imm8, imm16); 11446 urShiftI_reg_imm(tmpI3, src, imm8); 11447 insrwi(dst, tmpI3, imm8, imm8); 11448 insrwi(dst, src, imm0, imm8); 11449 %} 11450 %} 11451 11452 //---------- Replicate Vector Instructions ------------------------------------ 11453 11454 // Insrdi does replicate if src == dst. 11455 instruct repl32(iRegLdst dst) %{ 11456 predicate(false); 11457 effect(USE_DEF dst); 11458 11459 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} 11460 size(4); 11461 ins_encode %{ 11462 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11463 __ insrdi($dst$$Register, $dst$$Register, 32, 0); 11464 %} 11465 ins_pipe(pipe_class_default); 11466 %} 11467 11468 // Insrdi does replicate if src == dst. 11469 instruct repl48(iRegLdst dst) %{ 11470 predicate(false); 11471 effect(USE_DEF dst); 11472 11473 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} 11474 size(4); 11475 ins_encode %{ 11476 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11477 __ insrdi($dst$$Register, $dst$$Register, 48, 0); 11478 %} 11479 ins_pipe(pipe_class_default); 11480 %} 11481 11482 // Insrdi does replicate if src == dst. 11483 instruct repl56(iRegLdst dst) %{ 11484 predicate(false); 11485 effect(USE_DEF dst); 11486 11487 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} 11488 size(4); 11489 ins_encode %{ 11490 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11491 __ insrdi($dst$$Register, $dst$$Register, 56, 0); 11492 %} 11493 ins_pipe(pipe_class_default); 11494 %} 11495 11496 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11497 match(Set dst (ReplicateB src)); 11498 predicate(n->as_Vector()->length() == 8); 11499 expand %{ 11500 moveReg(dst, src); 11501 repl56(dst); 11502 repl48(dst); 11503 repl32(dst); 11504 %} 11505 %} 11506 11507 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ 11508 match(Set dst (ReplicateB zero)); 11509 predicate(n->as_Vector()->length() == 8); 11510 format %{ "LI $dst, #0 \t// replicate8B" %} 11511 size(4); 11512 ins_encode %{ 11513 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11514 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11515 %} 11516 ins_pipe(pipe_class_default); 11517 %} 11518 11519 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11520 match(Set dst (ReplicateB src)); 11521 predicate(n->as_Vector()->length() == 8); 11522 format %{ "LI $dst, #-1 \t// replicate8B" %} 11523 size(4); 11524 ins_encode %{ 11525 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11526 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11527 %} 11528 ins_pipe(pipe_class_default); 11529 %} 11530 11531 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11532 match(Set dst (ReplicateS src)); 11533 predicate(n->as_Vector()->length() == 4); 11534 expand %{ 11535 moveReg(dst, src); 11536 repl48(dst); 11537 repl32(dst); 11538 %} 11539 %} 11540 11541 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ 11542 match(Set dst (ReplicateS zero)); 11543 predicate(n->as_Vector()->length() == 4); 11544 format %{ "LI $dst, #0 \t// replicate4C" %} 11545 size(4); 11546 ins_encode %{ 11547 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11548 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11549 %} 11550 ins_pipe(pipe_class_default); 11551 %} 11552 11553 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11554 match(Set dst (ReplicateS src)); 11555 predicate(n->as_Vector()->length() == 4); 11556 format %{ "LI $dst, -1 \t// replicate4C" %} 11557 size(4); 11558 ins_encode %{ 11559 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11560 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11561 %} 11562 ins_pipe(pipe_class_default); 11563 %} 11564 11565 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11566 match(Set dst (ReplicateI src)); 11567 predicate(n->as_Vector()->length() == 2); 11568 ins_cost(2 * DEFAULT_COST); 11569 expand %{ 11570 moveReg(dst, src); 11571 repl32(dst); 11572 %} 11573 %} 11574 11575 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ 11576 match(Set dst (ReplicateI zero)); 11577 predicate(n->as_Vector()->length() == 2); 11578 format %{ "LI $dst, #0 \t// replicate4C" %} 11579 size(4); 11580 ins_encode %{ 11581 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11582 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11583 %} 11584 ins_pipe(pipe_class_default); 11585 %} 11586 11587 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11588 match(Set dst (ReplicateI src)); 11589 predicate(n->as_Vector()->length() == 2); 11590 format %{ "LI $dst, -1 \t// replicate4C" %} 11591 size(4); 11592 ins_encode %{ 11593 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11594 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11595 %} 11596 ins_pipe(pipe_class_default); 11597 %} 11598 11599 // Move float to int register via stack, replicate. 11600 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ 11601 match(Set dst (ReplicateF src)); 11602 predicate(n->as_Vector()->length() == 2); 11603 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); 11604 expand %{ 11605 stackSlotL tmpS; 11606 iRegIdst tmpI; 11607 moveF2I_reg_stack(tmpS, src); // Move float to stack. 11608 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. 11609 moveReg(dst, tmpI); // Move int to long reg. 11610 repl32(dst); // Replicate bitpattern. 11611 %} 11612 %} 11613 11614 // Replicate scalar constant to packed float values in Double register 11615 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ 11616 match(Set dst (ReplicateF src)); 11617 predicate(n->as_Vector()->length() == 2); 11618 ins_cost(5 * DEFAULT_COST); 11619 11620 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} 11621 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); 11622 %} 11623 11624 // Replicate scalar zero constant to packed float values in Double register 11625 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ 11626 match(Set dst (ReplicateF zero)); 11627 predicate(n->as_Vector()->length() == 2); 11628 11629 format %{ "LI $dst, #0 \t// replicate2F" %} 11630 ins_encode %{ 11631 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11632 __ li($dst$$Register, 0x0); 11633 %} 11634 ins_pipe(pipe_class_default); 11635 %} 11636 11637 11638 //----------Overflow Math Instructions----------------------------------------- 11639 11640 // Note that we have to make sure that XER.SO is reset before using overflow instructions. 11641 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc). 11642 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.) 11643 11644 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11645 match(Set cr0 (OverflowAddL op1 op2)); 11646 11647 format %{ "add_ $op1, $op2\t# overflow check long" %} 11648 ins_encode %{ 11649 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11650 __ li(R0, 0); 11651 __ mtxer(R0); // clear XER.SO 11652 __ addo_(R0, $op1$$Register, $op2$$Register); 11653 %} 11654 ins_pipe(pipe_class_default); 11655 %} 11656 11657 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11658 match(Set cr0 (OverflowSubL op1 op2)); 11659 11660 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %} 11661 ins_encode %{ 11662 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11663 __ li(R0, 0); 11664 __ mtxer(R0); // clear XER.SO 11665 __ subfo_(R0, $op2$$Register, $op1$$Register); 11666 %} 11667 ins_pipe(pipe_class_default); 11668 %} 11669 11670 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{ 11671 match(Set cr0 (OverflowSubL zero op2)); 11672 11673 format %{ "nego_ R0, $op2\t# overflow check long" %} 11674 ins_encode %{ 11675 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11676 __ li(R0, 0); 11677 __ mtxer(R0); // clear XER.SO 11678 __ nego_(R0, $op2$$Register); 11679 %} 11680 ins_pipe(pipe_class_default); 11681 %} 11682 11683 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11684 match(Set cr0 (OverflowMulL op1 op2)); 11685 11686 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %} 11687 ins_encode %{ 11688 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11689 __ li(R0, 0); 11690 __ mtxer(R0); // clear XER.SO 11691 __ mulldo_(R0, $op1$$Register, $op2$$Register); 11692 %} 11693 ins_pipe(pipe_class_default); 11694 %} 11695 11696 11697 // ============================================================================ 11698 // Safepoint Instruction 11699 11700 instruct safePoint_poll(iRegPdst poll) %{ 11701 match(SafePoint poll); 11702 predicate(LoadPollAddressFromThread); 11703 11704 // It caused problems to add the effect that r0 is killed, but this 11705 // effect no longer needs to be mentioned, since r0 is not contained 11706 // in a reg_class. 11707 11708 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} 11709 size(4); 11710 ins_encode( enc_poll(0x0, poll) ); 11711 ins_pipe(pipe_class_default); 11712 %} 11713 11714 // Safepoint without per-thread support. Load address of page to poll 11715 // as constant. 11716 // Rscratch2RegP is R12. 11717 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be 11718 // a seperate node so that the oop map is at the right location. 11719 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ 11720 match(SafePoint poll); 11721 predicate(!LoadPollAddressFromThread); 11722 11723 // It caused problems to add the effect that r0 is killed, but this 11724 // effect no longer needs to be mentioned, since r0 is not contained 11725 // in a reg_class. 11726 11727 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %} 11728 ins_encode( enc_poll(0x0, poll) ); 11729 ins_pipe(pipe_class_default); 11730 %} 11731 11732 // ============================================================================ 11733 // Call Instructions 11734 11735 // Call Java Static Instruction 11736 11737 // Schedulable version of call static node. 11738 instruct CallStaticJavaDirect(method meth) %{ 11739 match(CallStaticJava); 11740 effect(USE meth); 11741 ins_cost(CALL_COST); 11742 11743 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11744 11745 format %{ "CALL,static $meth \t// ==> " %} 11746 size(4); 11747 ins_encode( enc_java_static_call(meth) ); 11748 ins_pipe(pipe_class_call); 11749 %} 11750 11751 // Call Java Dynamic Instruction 11752 11753 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). 11754 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable 11755 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. 11756 // The call destination must still be placed in the constant pool. 11757 instruct CallDynamicJavaDirectSched(method meth) %{ 11758 match(CallDynamicJava); // To get all the data fields we need ... 11759 effect(USE meth); 11760 predicate(false); // ... but never match. 11761 11762 ins_field_load_ic_hi_node(loadConL_hiNode*); 11763 ins_field_load_ic_node(loadConLNode*); 11764 ins_num_consts(1 /* 1 patchable constant: call destination */); 11765 11766 format %{ "BL \t// dynamic $meth ==> " %} 11767 size(4); 11768 ins_encode( enc_java_dynamic_call_sched(meth) ); 11769 ins_pipe(pipe_class_call); 11770 %} 11771 11772 // Schedulable (i.e. postalloc expanded) version of call dynamic java. 11773 // We use postalloc expanded calls if we use inline caches 11774 // and do not update method data. 11775 // 11776 // This instruction has two constants: inline cache (IC) and call destination. 11777 // Loading the inline cache will be postalloc expanded, thus leaving a call with 11778 // one constant. 11779 instruct CallDynamicJavaDirectSched_Ex(method meth) %{ 11780 match(CallDynamicJava); 11781 effect(USE meth); 11782 predicate(UseInlineCaches); 11783 ins_cost(CALL_COST); 11784 11785 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); 11786 11787 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} 11788 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); 11789 %} 11790 11791 // Compound version of call dynamic java 11792 // We use postalloc expanded calls if we use inline caches 11793 // and do not update method data. 11794 instruct CallDynamicJavaDirect(method meth) %{ 11795 match(CallDynamicJava); 11796 effect(USE meth); 11797 predicate(!UseInlineCaches); 11798 ins_cost(CALL_COST); 11799 11800 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). 11801 ins_num_consts(4); 11802 11803 format %{ "CALL,dynamic $meth \t// ==> " %} 11804 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); 11805 ins_pipe(pipe_class_call); 11806 %} 11807 11808 // Call Runtime Instruction 11809 11810 instruct CallRuntimeDirect(method meth) %{ 11811 match(CallRuntime); 11812 effect(USE meth); 11813 ins_cost(CALL_COST); 11814 11815 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11816 // env for callee, C-toc. 11817 ins_num_consts(3); 11818 11819 format %{ "CALL,runtime" %} 11820 ins_encode( enc_java_to_runtime_call(meth) ); 11821 ins_pipe(pipe_class_call); 11822 %} 11823 11824 // Call Leaf 11825 11826 // Used by postalloc expand of CallLeafDirect_Ex (mtctr). 11827 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ 11828 effect(DEF dst, USE src); 11829 11830 ins_num_consts(1); 11831 11832 format %{ "MTCTR $src" %} 11833 size(4); 11834 ins_encode( enc_leaf_call_mtctr(src) ); 11835 ins_pipe(pipe_class_default); 11836 %} 11837 11838 // Used by postalloc expand of CallLeafDirect_Ex (actual call). 11839 instruct CallLeafDirect(method meth) %{ 11840 match(CallLeaf); // To get the data all the data fields we need ... 11841 effect(USE meth); 11842 predicate(false); // but never match. 11843 11844 format %{ "BCTRL \t// leaf call $meth ==> " %} 11845 size(4); 11846 ins_encode %{ 11847 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); 11848 __ bctrl(); 11849 %} 11850 ins_pipe(pipe_class_call); 11851 %} 11852 11853 // postalloc expand of CallLeafDirect. 11854 // Load adress to call from TOC, then bl to it. 11855 instruct CallLeafDirect_Ex(method meth) %{ 11856 match(CallLeaf); 11857 effect(USE meth); 11858 ins_cost(CALL_COST); 11859 11860 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, 11861 // env for callee, C-toc. 11862 ins_num_consts(3); 11863 11864 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} 11865 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11866 %} 11867 11868 // Call runtime without safepoint - same as CallLeaf. 11869 // postalloc expand of CallLeafNoFPDirect. 11870 // Load adress to call from TOC, then bl to it. 11871 instruct CallLeafNoFPDirect_Ex(method meth) %{ 11872 match(CallLeafNoFP); 11873 effect(USE meth); 11874 ins_cost(CALL_COST); 11875 11876 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11877 // env for callee, C-toc. 11878 ins_num_consts(3); 11879 11880 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} 11881 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11882 %} 11883 11884 // Tail Call; Jump from runtime stub to Java code. 11885 // Also known as an 'interprocedural jump'. 11886 // Target of jump will eventually return to caller. 11887 // TailJump below removes the return address. 11888 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ 11889 match(TailCall jump_target method_oop); 11890 ins_cost(CALL_COST); 11891 11892 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" 11893 "BCTR \t// tail call" %} 11894 size(8); 11895 ins_encode %{ 11896 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11897 __ mtctr($jump_target$$Register); 11898 __ bctr(); 11899 %} 11900 ins_pipe(pipe_class_call); 11901 %} 11902 11903 // Return Instruction 11904 instruct Ret() %{ 11905 match(Return); 11906 format %{ "BLR \t// branch to link register" %} 11907 size(4); 11908 ins_encode %{ 11909 // TODO: PPC port $archOpcode(ppc64Opcode_blr); 11910 // LR is restored in MachEpilogNode. Just do the RET here. 11911 __ blr(); 11912 %} 11913 ins_pipe(pipe_class_default); 11914 %} 11915 11916 // Tail Jump; remove the return address; jump to target. 11917 // TailCall above leaves the return address around. 11918 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 11919 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 11920 // "restore" before this instruction (in Epilogue), we need to materialize it 11921 // in %i0. 11922 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ 11923 match(TailJump jump_target ex_oop); 11924 ins_cost(CALL_COST); 11925 11926 format %{ "LD R4_ARG2 = LR\n\t" 11927 "MTCTR $jump_target\n\t" 11928 "BCTR \t// TailJump, exception oop: $ex_oop" %} 11929 size(12); 11930 ins_encode %{ 11931 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11932 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); 11933 __ mtctr($jump_target$$Register); 11934 __ bctr(); 11935 %} 11936 ins_pipe(pipe_class_call); 11937 %} 11938 11939 // Create exception oop: created by stack-crawling runtime code. 11940 // Created exception is now available to this handler, and is setup 11941 // just prior to jumping to this handler. No code emitted. 11942 instruct CreateException(rarg1RegP ex_oop) %{ 11943 match(Set ex_oop (CreateEx)); 11944 ins_cost(0); 11945 11946 format %{ " -- \t// exception oop; no code emitted" %} 11947 size(0); 11948 ins_encode( /*empty*/ ); 11949 ins_pipe(pipe_class_default); 11950 %} 11951 11952 // Rethrow exception: The exception oop will come in the first 11953 // argument position. Then JUMP (not call) to the rethrow stub code. 11954 instruct RethrowException() %{ 11955 match(Rethrow); 11956 ins_cost(CALL_COST); 11957 11958 format %{ "Jmp rethrow_stub" %} 11959 ins_encode %{ 11960 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11961 cbuf.set_insts_mark(); 11962 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); 11963 %} 11964 ins_pipe(pipe_class_call); 11965 %} 11966 11967 // Die now. 11968 instruct ShouldNotReachHere() %{ 11969 match(Halt); 11970 ins_cost(CALL_COST); 11971 11972 format %{ "ShouldNotReachHere" %} 11973 size(4); 11974 ins_encode %{ 11975 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 11976 __ trap_should_not_reach_here(); 11977 %} 11978 ins_pipe(pipe_class_default); 11979 %} 11980 11981 // This name is KNOWN by the ADLC and cannot be changed. The ADLC 11982 // forces a 'TypeRawPtr::BOTTOM' output type for this guy. 11983 // Get a DEF on threadRegP, no costs, no encoding, use 11984 // 'ins_should_rematerialize(true)' to avoid spilling. 11985 instruct tlsLoadP(threadRegP dst) %{ 11986 match(Set dst (ThreadLocal)); 11987 ins_cost(0); 11988 11989 ins_should_rematerialize(true); 11990 11991 format %{ " -- \t// $dst=Thread::current(), empty" %} 11992 size(0); 11993 ins_encode( /*empty*/ ); 11994 ins_pipe(pipe_class_empty); 11995 %} 11996 11997 //---Some PPC specific nodes--------------------------------------------------- 11998 11999 // Stop a group. 12000 instruct endGroup() %{ 12001 ins_cost(0); 12002 12003 ins_is_nop(true); 12004 12005 format %{ "End Bundle (ori r1, r1, 0)" %} 12006 size(4); 12007 ins_encode %{ 12008 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); 12009 __ endgroup(); 12010 %} 12011 ins_pipe(pipe_class_default); 12012 %} 12013 12014 // Nop instructions 12015 12016 instruct fxNop() %{ 12017 ins_cost(0); 12018 12019 ins_is_nop(true); 12020 12021 format %{ "fxNop" %} 12022 size(4); 12023 ins_encode %{ 12024 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12025 __ nop(); 12026 %} 12027 ins_pipe(pipe_class_default); 12028 %} 12029 12030 instruct fpNop0() %{ 12031 ins_cost(0); 12032 12033 ins_is_nop(true); 12034 12035 format %{ "fpNop0" %} 12036 size(4); 12037 ins_encode %{ 12038 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12039 __ fpnop0(); 12040 %} 12041 ins_pipe(pipe_class_default); 12042 %} 12043 12044 instruct fpNop1() %{ 12045 ins_cost(0); 12046 12047 ins_is_nop(true); 12048 12049 format %{ "fpNop1" %} 12050 size(4); 12051 ins_encode %{ 12052 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12053 __ fpnop1(); 12054 %} 12055 ins_pipe(pipe_class_default); 12056 %} 12057 12058 instruct brNop0() %{ 12059 ins_cost(0); 12060 size(4); 12061 format %{ "brNop0" %} 12062 ins_encode %{ 12063 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12064 __ brnop0(); 12065 %} 12066 ins_is_nop(true); 12067 ins_pipe(pipe_class_default); 12068 %} 12069 12070 instruct brNop1() %{ 12071 ins_cost(0); 12072 12073 ins_is_nop(true); 12074 12075 format %{ "brNop1" %} 12076 size(4); 12077 ins_encode %{ 12078 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12079 __ brnop1(); 12080 %} 12081 ins_pipe(pipe_class_default); 12082 %} 12083 12084 instruct brNop2() %{ 12085 ins_cost(0); 12086 12087 ins_is_nop(true); 12088 12089 format %{ "brNop2" %} 12090 size(4); 12091 ins_encode %{ 12092 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12093 __ brnop2(); 12094 %} 12095 ins_pipe(pipe_class_default); 12096 %} 12097 12098 //----------PEEPHOLE RULES----------------------------------------------------- 12099 // These must follow all instruction definitions as they use the names 12100 // defined in the instructions definitions. 12101 // 12102 // peepmatch ( root_instr_name [preceeding_instruction]* ); 12103 // 12104 // peepconstraint %{ 12105 // (instruction_number.operand_name relational_op instruction_number.operand_name 12106 // [, ...] ); 12107 // // instruction numbers are zero-based using left to right order in peepmatch 12108 // 12109 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12110 // // provide an instruction_number.operand_name for each operand that appears 12111 // // in the replacement instruction's match rule 12112 // 12113 // ---------VM FLAGS--------------------------------------------------------- 12114 // 12115 // All peephole optimizations can be turned off using -XX:-OptoPeephole 12116 // 12117 // Each peephole rule is given an identifying number starting with zero and 12118 // increasing by one in the order seen by the parser. An individual peephole 12119 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12120 // on the command-line. 12121 // 12122 // ---------CURRENT LIMITATIONS---------------------------------------------- 12123 // 12124 // Only match adjacent instructions in same basic block 12125 // Only equality constraints 12126 // Only constraints between operands, not (0.dest_reg == EAX_enc) 12127 // Only one replacement instruction 12128 // 12129 // ---------EXAMPLE---------------------------------------------------------- 12130 // 12131 // // pertinent parts of existing instructions in architecture description 12132 // instruct movI(eRegI dst, eRegI src) %{ 12133 // match(Set dst (CopyI src)); 12134 // %} 12135 // 12136 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12137 // match(Set dst (AddI dst src)); 12138 // effect(KILL cr); 12139 // %} 12140 // 12141 // // Change (inc mov) to lea 12142 // peephole %{ 12143 // // increment preceeded by register-register move 12144 // peepmatch ( incI_eReg movI ); 12145 // // require that the destination register of the increment 12146 // // match the destination register of the move 12147 // peepconstraint ( 0.dst == 1.dst ); 12148 // // construct a replacement instruction that sets 12149 // // the destination to ( move's source register + one ) 12150 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12151 // %} 12152 // 12153 // Implementation no longer uses movX instructions since 12154 // machine-independent system no longer uses CopyX nodes. 12155 // 12156 // peephole %{ 12157 // peepmatch ( incI_eReg movI ); 12158 // peepconstraint ( 0.dst == 1.dst ); 12159 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12160 // %} 12161 // 12162 // peephole %{ 12163 // peepmatch ( decI_eReg movI ); 12164 // peepconstraint ( 0.dst == 1.dst ); 12165 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12166 // %} 12167 // 12168 // peephole %{ 12169 // peepmatch ( addI_eReg_imm movI ); 12170 // peepconstraint ( 0.dst == 1.dst ); 12171 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12172 // %} 12173 // 12174 // peephole %{ 12175 // peepmatch ( addP_eReg_imm movP ); 12176 // peepconstraint ( 0.dst == 1.dst ); 12177 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12178 // %} 12179 12180 // // Change load of spilled value to only a spill 12181 // instruct storeI(memory mem, eRegI src) %{ 12182 // match(Set mem (StoreI mem src)); 12183 // %} 12184 // 12185 // instruct loadI(eRegI dst, memory mem) %{ 12186 // match(Set dst (LoadI mem)); 12187 // %} 12188 // 12189 peephole %{ 12190 peepmatch ( loadI storeI ); 12191 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12192 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12193 %} 12194 12195 peephole %{ 12196 peepmatch ( loadL storeL ); 12197 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12198 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); 12199 %} 12200 12201 peephole %{ 12202 peepmatch ( loadP storeP ); 12203 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); 12204 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); 12205 %} 12206 12207 //----------SMARTSPILL RULES--------------------------------------------------- 12208 // These must follow all instruction definitions as they use the names 12209 // defined in the instructions definitions.