1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "runtime/thread.hpp" 43 #include "utilities/macros.hpp" 44 #if INCLUDE_ALL_GCS 45 #include "gc/g1/g1CollectedHeap.inline.hpp" 46 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 47 #include "gc/g1/heapRegion.hpp" 48 #endif // INCLUDE_ALL_GCS 49 #include "crc32c.h" 50 #ifdef COMPILER2 51 #include "opto/intrinsicnode.hpp" 52 #endif 53 54 #ifdef PRODUCT 55 #define BLOCK_COMMENT(str) /* nothing */ 56 #define STOP(error) stop(error) 57 #else 58 #define BLOCK_COMMENT(str) block_comment(str) 59 #define STOP(error) block_comment(error); stop(error) 60 #endif 61 62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 63 64 #ifdef ASSERT 65 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 66 #endif 67 68 static Assembler::Condition reverse[] = { 69 Assembler::noOverflow /* overflow = 0x0 */ , 70 Assembler::overflow /* noOverflow = 0x1 */ , 71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 75 Assembler::above /* belowEqual = 0x6 */ , 76 Assembler::belowEqual /* above = 0x7 */ , 77 Assembler::positive /* negative = 0x8 */ , 78 Assembler::negative /* positive = 0x9 */ , 79 Assembler::noParity /* parity = 0xa */ , 80 Assembler::parity /* noParity = 0xb */ , 81 Assembler::greaterEqual /* less = 0xc */ , 82 Assembler::less /* greaterEqual = 0xd */ , 83 Assembler::greater /* lessEqual = 0xe */ , 84 Assembler::lessEqual /* greater = 0xf, */ 85 86 }; 87 88 89 // Implementation of MacroAssembler 90 91 // First all the versions that have distinct versions depending on 32/64 bit 92 // Unless the difference is trivial (1 line or so). 93 94 #ifndef _LP64 95 96 // 32bit versions 97 98 Address MacroAssembler::as_Address(AddressLiteral adr) { 99 return Address(adr.target(), adr.rspec()); 100 } 101 102 Address MacroAssembler::as_Address(ArrayAddress adr) { 103 return Address::make_array(adr); 104 } 105 106 void MacroAssembler::call_VM_leaf_base(address entry_point, 107 int number_of_arguments) { 108 call(RuntimeAddress(entry_point)); 109 increment(rsp, number_of_arguments * wordSize); 110 } 111 112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 114 } 115 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 118 } 119 120 void MacroAssembler::cmpoop(Address src1, jobject obj) { 121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 122 } 123 124 void MacroAssembler::cmpoop(Register src1, jobject obj) { 125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 126 } 127 128 void MacroAssembler::extend_sign(Register hi, Register lo) { 129 // According to Intel Doc. AP-526, "Integer Divide", p.18. 130 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 131 cdql(); 132 } else { 133 movl(hi, lo); 134 sarl(hi, 31); 135 } 136 } 137 138 void MacroAssembler::jC2(Register tmp, Label& L) { 139 // set parity bit if FPU flag C2 is set (via rax) 140 save_rax(tmp); 141 fwait(); fnstsw_ax(); 142 sahf(); 143 restore_rax(tmp); 144 // branch 145 jcc(Assembler::parity, L); 146 } 147 148 void MacroAssembler::jnC2(Register tmp, Label& L) { 149 // set parity bit if FPU flag C2 is set (via rax) 150 save_rax(tmp); 151 fwait(); fnstsw_ax(); 152 sahf(); 153 restore_rax(tmp); 154 // branch 155 jcc(Assembler::noParity, L); 156 } 157 158 // 32bit can do a case table jump in one instruction but we no longer allow the base 159 // to be installed in the Address class 160 void MacroAssembler::jump(ArrayAddress entry) { 161 jmp(as_Address(entry)); 162 } 163 164 // Note: y_lo will be destroyed 165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 166 // Long compare for Java (semantics as described in JVM spec.) 167 Label high, low, done; 168 169 cmpl(x_hi, y_hi); 170 jcc(Assembler::less, low); 171 jcc(Assembler::greater, high); 172 // x_hi is the return register 173 xorl(x_hi, x_hi); 174 cmpl(x_lo, y_lo); 175 jcc(Assembler::below, low); 176 jcc(Assembler::equal, done); 177 178 bind(high); 179 xorl(x_hi, x_hi); 180 increment(x_hi); 181 jmp(done); 182 183 bind(low); 184 xorl(x_hi, x_hi); 185 decrementl(x_hi); 186 187 bind(done); 188 } 189 190 void MacroAssembler::lea(Register dst, AddressLiteral src) { 191 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 192 } 193 194 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 195 // leal(dst, as_Address(adr)); 196 // see note in movl as to why we must use a move 197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 198 } 199 200 void MacroAssembler::leave() { 201 mov(rsp, rbp); 202 pop(rbp); 203 } 204 205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 206 // Multiplication of two Java long values stored on the stack 207 // as illustrated below. Result is in rdx:rax. 208 // 209 // rsp ---> [ ?? ] \ \ 210 // .... | y_rsp_offset | 211 // [ y_lo ] / (in bytes) | x_rsp_offset 212 // [ y_hi ] | (in bytes) 213 // .... | 214 // [ x_lo ] / 215 // [ x_hi ] 216 // .... 217 // 218 // Basic idea: lo(result) = lo(x_lo * y_lo) 219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 222 Label quick; 223 // load x_hi, y_hi and check if quick 224 // multiplication is possible 225 movl(rbx, x_hi); 226 movl(rcx, y_hi); 227 movl(rax, rbx); 228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 230 // do full multiplication 231 // 1st step 232 mull(y_lo); // x_hi * y_lo 233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 234 // 2nd step 235 movl(rax, x_lo); 236 mull(rcx); // x_lo * y_hi 237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 238 // 3rd step 239 bind(quick); // note: rbx, = 0 if quick multiply! 240 movl(rax, x_lo); 241 mull(y_lo); // x_lo * y_lo 242 addl(rdx, rbx); // correct hi(x_lo * y_lo) 243 } 244 245 void MacroAssembler::lneg(Register hi, Register lo) { 246 negl(lo); 247 adcl(hi, 0); 248 negl(hi); 249 } 250 251 void MacroAssembler::lshl(Register hi, Register lo) { 252 // Java shift left long support (semantics as described in JVM spec., p.305) 253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 254 // shift value is in rcx ! 255 assert(hi != rcx, "must not use rcx"); 256 assert(lo != rcx, "must not use rcx"); 257 const Register s = rcx; // shift count 258 const int n = BitsPerWord; 259 Label L; 260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 261 cmpl(s, n); // if (s < n) 262 jcc(Assembler::less, L); // else (s >= n) 263 movl(hi, lo); // x := x << n 264 xorl(lo, lo); 265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 266 bind(L); // s (mod n) < n 267 shldl(hi, lo); // x := x << s 268 shll(lo); 269 } 270 271 272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 275 assert(hi != rcx, "must not use rcx"); 276 assert(lo != rcx, "must not use rcx"); 277 const Register s = rcx; // shift count 278 const int n = BitsPerWord; 279 Label L; 280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 281 cmpl(s, n); // if (s < n) 282 jcc(Assembler::less, L); // else (s >= n) 283 movl(lo, hi); // x := x >> n 284 if (sign_extension) sarl(hi, 31); 285 else xorl(hi, hi); 286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 287 bind(L); // s (mod n) < n 288 shrdl(lo, hi); // x := x >> s 289 if (sign_extension) sarl(hi); 290 else shrl(hi); 291 } 292 293 void MacroAssembler::movoop(Register dst, jobject obj) { 294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 295 } 296 297 void MacroAssembler::movoop(Address dst, jobject obj) { 298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 299 } 300 301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 303 } 304 305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 307 } 308 309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 310 // scratch register is not used, 311 // it is defined to match parameters of 64-bit version of this method. 312 if (src.is_lval()) { 313 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 314 } else { 315 movl(dst, as_Address(src)); 316 } 317 } 318 319 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 320 movl(as_Address(dst), src); 321 } 322 323 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 324 movl(dst, as_Address(src)); 325 } 326 327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 328 void MacroAssembler::movptr(Address dst, intptr_t src) { 329 movl(dst, src); 330 } 331 332 333 void MacroAssembler::pop_callee_saved_registers() { 334 pop(rcx); 335 pop(rdx); 336 pop(rdi); 337 pop(rsi); 338 } 339 340 void MacroAssembler::pop_fTOS() { 341 fld_d(Address(rsp, 0)); 342 addl(rsp, 2 * wordSize); 343 } 344 345 void MacroAssembler::push_callee_saved_registers() { 346 push(rsi); 347 push(rdi); 348 push(rdx); 349 push(rcx); 350 } 351 352 void MacroAssembler::push_fTOS() { 353 subl(rsp, 2 * wordSize); 354 fstp_d(Address(rsp, 0)); 355 } 356 357 358 void MacroAssembler::pushoop(jobject obj) { 359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 360 } 361 362 void MacroAssembler::pushklass(Metadata* obj) { 363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 364 } 365 366 void MacroAssembler::pushptr(AddressLiteral src) { 367 if (src.is_lval()) { 368 push_literal32((int32_t)src.target(), src.rspec()); 369 } else { 370 pushl(as_Address(src)); 371 } 372 } 373 374 void MacroAssembler::set_word_if_not_zero(Register dst) { 375 xorl(dst, dst); 376 set_byte_if_not_zero(dst); 377 } 378 379 static void pass_arg0(MacroAssembler* masm, Register arg) { 380 masm->push(arg); 381 } 382 383 static void pass_arg1(MacroAssembler* masm, Register arg) { 384 masm->push(arg); 385 } 386 387 static void pass_arg2(MacroAssembler* masm, Register arg) { 388 masm->push(arg); 389 } 390 391 static void pass_arg3(MacroAssembler* masm, Register arg) { 392 masm->push(arg); 393 } 394 395 #ifndef PRODUCT 396 extern "C" void findpc(intptr_t x); 397 #endif 398 399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 400 // In order to get locks to work, we need to fake a in_VM state 401 JavaThread* thread = JavaThread::current(); 402 JavaThreadState saved_state = thread->thread_state(); 403 thread->set_thread_state(_thread_in_vm); 404 if (ShowMessageBoxOnError) { 405 JavaThread* thread = JavaThread::current(); 406 JavaThreadState saved_state = thread->thread_state(); 407 thread->set_thread_state(_thread_in_vm); 408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 409 ttyLocker ttyl; 410 BytecodeCounter::print(); 411 } 412 // To see where a verify_oop failed, get $ebx+40/X for this frame. 413 // This is the value of eip which points to where verify_oop will return. 414 if (os::message_box(msg, "Execution stopped, print registers?")) { 415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 416 BREAKPOINT; 417 } 418 } else { 419 ttyLocker ttyl; 420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 421 } 422 // Don't assert holding the ttyLock 423 assert(false, "DEBUG MESSAGE: %s", msg); 424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 425 } 426 427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 428 ttyLocker ttyl; 429 FlagSetting fs(Debugging, true); 430 tty->print_cr("eip = 0x%08x", eip); 431 #ifndef PRODUCT 432 if ((WizardMode || Verbose) && PrintMiscellaneous) { 433 tty->cr(); 434 findpc(eip); 435 tty->cr(); 436 } 437 #endif 438 #define PRINT_REG(rax) \ 439 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 440 PRINT_REG(rax); 441 PRINT_REG(rbx); 442 PRINT_REG(rcx); 443 PRINT_REG(rdx); 444 PRINT_REG(rdi); 445 PRINT_REG(rsi); 446 PRINT_REG(rbp); 447 PRINT_REG(rsp); 448 #undef PRINT_REG 449 // Print some words near top of staack. 450 int* dump_sp = (int*) rsp; 451 for (int col1 = 0; col1 < 8; col1++) { 452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 453 os::print_location(tty, *dump_sp++); 454 } 455 for (int row = 0; row < 16; row++) { 456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 457 for (int col = 0; col < 8; col++) { 458 tty->print(" 0x%08x", *dump_sp++); 459 } 460 tty->cr(); 461 } 462 // Print some instructions around pc: 463 Disassembler::decode((address)eip-64, (address)eip); 464 tty->print_cr("--------"); 465 Disassembler::decode((address)eip, (address)eip+32); 466 } 467 468 void MacroAssembler::stop(const char* msg) { 469 ExternalAddress message((address)msg); 470 // push address of message 471 pushptr(message.addr()); 472 { Label L; call(L, relocInfo::none); bind(L); } // push eip 473 pusha(); // push registers 474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 475 hlt(); 476 } 477 478 void MacroAssembler::warn(const char* msg) { 479 push_CPU_state(); 480 481 ExternalAddress message((address) msg); 482 // push address of message 483 pushptr(message.addr()); 484 485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 486 addl(rsp, wordSize); // discard argument 487 pop_CPU_state(); 488 } 489 490 void MacroAssembler::print_state() { 491 { Label L; call(L, relocInfo::none); bind(L); } // push eip 492 pusha(); // push registers 493 494 push_CPU_state(); 495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 496 pop_CPU_state(); 497 498 popa(); 499 addl(rsp, wordSize); 500 } 501 502 #else // _LP64 503 504 // 64 bit versions 505 506 Address MacroAssembler::as_Address(AddressLiteral adr) { 507 // amd64 always does this as a pc-rel 508 // we can be absolute or disp based on the instruction type 509 // jmp/call are displacements others are absolute 510 assert(!adr.is_lval(), "must be rval"); 511 assert(reachable(adr), "must be"); 512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 513 514 } 515 516 Address MacroAssembler::as_Address(ArrayAddress adr) { 517 AddressLiteral base = adr.base(); 518 lea(rscratch1, base); 519 Address index = adr.index(); 520 assert(index._disp == 0, "must not have disp"); // maybe it can? 521 Address array(rscratch1, index._index, index._scale, index._disp); 522 return array; 523 } 524 525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 526 Label L, E; 527 528 #ifdef _WIN64 529 // Windows always allocates space for it's register args 530 assert(num_args <= 4, "only register arguments supported"); 531 subq(rsp, frame::arg_reg_save_area_bytes); 532 #endif 533 534 // Align stack if necessary 535 testl(rsp, 15); 536 jcc(Assembler::zero, L); 537 538 subq(rsp, 8); 539 { 540 call(RuntimeAddress(entry_point)); 541 } 542 addq(rsp, 8); 543 jmp(E); 544 545 bind(L); 546 { 547 call(RuntimeAddress(entry_point)); 548 } 549 550 bind(E); 551 552 #ifdef _WIN64 553 // restore stack pointer 554 addq(rsp, frame::arg_reg_save_area_bytes); 555 #endif 556 557 } 558 559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 560 assert(!src2.is_lval(), "should use cmpptr"); 561 562 if (reachable(src2)) { 563 cmpq(src1, as_Address(src2)); 564 } else { 565 lea(rscratch1, src2); 566 Assembler::cmpq(src1, Address(rscratch1, 0)); 567 } 568 } 569 570 int MacroAssembler::corrected_idivq(Register reg) { 571 // Full implementation of Java ldiv and lrem; checks for special 572 // case as described in JVM spec., p.243 & p.271. The function 573 // returns the (pc) offset of the idivl instruction - may be needed 574 // for implicit exceptions. 575 // 576 // normal case special case 577 // 578 // input : rax: dividend min_long 579 // reg: divisor (may not be eax/edx) -1 580 // 581 // output: rax: quotient (= rax idiv reg) min_long 582 // rdx: remainder (= rax irem reg) 0 583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 584 static const int64_t min_long = 0x8000000000000000; 585 Label normal_case, special_case; 586 587 // check for special case 588 cmp64(rax, ExternalAddress((address) &min_long)); 589 jcc(Assembler::notEqual, normal_case); 590 xorl(rdx, rdx); // prepare rdx for possible special case (where 591 // remainder = 0) 592 cmpq(reg, -1); 593 jcc(Assembler::equal, special_case); 594 595 // handle normal case 596 bind(normal_case); 597 cdqq(); 598 int idivq_offset = offset(); 599 idivq(reg); 600 601 // normal and special case exit 602 bind(special_case); 603 604 return idivq_offset; 605 } 606 607 void MacroAssembler::decrementq(Register reg, int value) { 608 if (value == min_jint) { subq(reg, value); return; } 609 if (value < 0) { incrementq(reg, -value); return; } 610 if (value == 0) { ; return; } 611 if (value == 1 && UseIncDec) { decq(reg) ; return; } 612 /* else */ { subq(reg, value) ; return; } 613 } 614 615 void MacroAssembler::decrementq(Address dst, int value) { 616 if (value == min_jint) { subq(dst, value); return; } 617 if (value < 0) { incrementq(dst, -value); return; } 618 if (value == 0) { ; return; } 619 if (value == 1 && UseIncDec) { decq(dst) ; return; } 620 /* else */ { subq(dst, value) ; return; } 621 } 622 623 void MacroAssembler::incrementq(AddressLiteral dst) { 624 if (reachable(dst)) { 625 incrementq(as_Address(dst)); 626 } else { 627 lea(rscratch1, dst); 628 incrementq(Address(rscratch1, 0)); 629 } 630 } 631 632 void MacroAssembler::incrementq(Register reg, int value) { 633 if (value == min_jint) { addq(reg, value); return; } 634 if (value < 0) { decrementq(reg, -value); return; } 635 if (value == 0) { ; return; } 636 if (value == 1 && UseIncDec) { incq(reg) ; return; } 637 /* else */ { addq(reg, value) ; return; } 638 } 639 640 void MacroAssembler::incrementq(Address dst, int value) { 641 if (value == min_jint) { addq(dst, value); return; } 642 if (value < 0) { decrementq(dst, -value); return; } 643 if (value == 0) { ; return; } 644 if (value == 1 && UseIncDec) { incq(dst) ; return; } 645 /* else */ { addq(dst, value) ; return; } 646 } 647 648 // 32bit can do a case table jump in one instruction but we no longer allow the base 649 // to be installed in the Address class 650 void MacroAssembler::jump(ArrayAddress entry) { 651 lea(rscratch1, entry.base()); 652 Address dispatch = entry.index(); 653 assert(dispatch._base == noreg, "must be"); 654 dispatch._base = rscratch1; 655 jmp(dispatch); 656 } 657 658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 659 ShouldNotReachHere(); // 64bit doesn't use two regs 660 cmpq(x_lo, y_lo); 661 } 662 663 void MacroAssembler::lea(Register dst, AddressLiteral src) { 664 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 665 } 666 667 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 669 movptr(dst, rscratch1); 670 } 671 672 void MacroAssembler::leave() { 673 // %%% is this really better? Why not on 32bit too? 674 emit_int8((unsigned char)0xC9); // LEAVE 675 } 676 677 void MacroAssembler::lneg(Register hi, Register lo) { 678 ShouldNotReachHere(); // 64bit doesn't use two regs 679 negq(lo); 680 } 681 682 void MacroAssembler::movoop(Register dst, jobject obj) { 683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 684 } 685 686 void MacroAssembler::movoop(Address dst, jobject obj) { 687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 688 movq(dst, rscratch1); 689 } 690 691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 693 } 694 695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 697 movq(dst, rscratch1); 698 } 699 700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 701 if (src.is_lval()) { 702 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 703 } else { 704 if (reachable(src)) { 705 movq(dst, as_Address(src)); 706 } else { 707 lea(scratch, src); 708 movq(dst, Address(scratch, 0)); 709 } 710 } 711 } 712 713 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 714 movq(as_Address(dst), src); 715 } 716 717 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 718 movq(dst, as_Address(src)); 719 } 720 721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 722 void MacroAssembler::movptr(Address dst, intptr_t src) { 723 mov64(rscratch1, src); 724 movq(dst, rscratch1); 725 } 726 727 // These are mostly for initializing NULL 728 void MacroAssembler::movptr(Address dst, int32_t src) { 729 movslq(dst, src); 730 } 731 732 void MacroAssembler::movptr(Register dst, int32_t src) { 733 mov64(dst, (intptr_t)src); 734 } 735 736 void MacroAssembler::pushoop(jobject obj) { 737 movoop(rscratch1, obj); 738 push(rscratch1); 739 } 740 741 void MacroAssembler::pushklass(Metadata* obj) { 742 mov_metadata(rscratch1, obj); 743 push(rscratch1); 744 } 745 746 void MacroAssembler::pushptr(AddressLiteral src) { 747 lea(rscratch1, src); 748 if (src.is_lval()) { 749 push(rscratch1); 750 } else { 751 pushq(Address(rscratch1, 0)); 752 } 753 } 754 755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 756 // we must set sp to zero to clear frame 757 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 758 // must clear fp, so that compiled frames are not confused; it is 759 // possible that we need it only for debugging 760 if (clear_fp) { 761 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 762 } 763 764 // Always clear the pc because it could have been set by make_walkable() 765 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 766 } 767 768 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 769 Register last_java_fp, 770 address last_java_pc) { 771 // determine last_java_sp register 772 if (!last_java_sp->is_valid()) { 773 last_java_sp = rsp; 774 } 775 776 // last_java_fp is optional 777 if (last_java_fp->is_valid()) { 778 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 779 last_java_fp); 780 } 781 782 // last_java_pc is optional 783 if (last_java_pc != NULL) { 784 Address java_pc(r15_thread, 785 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 786 lea(rscratch1, InternalAddress(last_java_pc)); 787 movptr(java_pc, rscratch1); 788 } 789 790 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 791 } 792 793 static void pass_arg0(MacroAssembler* masm, Register arg) { 794 if (c_rarg0 != arg ) { 795 masm->mov(c_rarg0, arg); 796 } 797 } 798 799 static void pass_arg1(MacroAssembler* masm, Register arg) { 800 if (c_rarg1 != arg ) { 801 masm->mov(c_rarg1, arg); 802 } 803 } 804 805 static void pass_arg2(MacroAssembler* masm, Register arg) { 806 if (c_rarg2 != arg ) { 807 masm->mov(c_rarg2, arg); 808 } 809 } 810 811 static void pass_arg3(MacroAssembler* masm, Register arg) { 812 if (c_rarg3 != arg ) { 813 masm->mov(c_rarg3, arg); 814 } 815 } 816 817 void MacroAssembler::stop(const char* msg) { 818 address rip = pc(); 819 pusha(); // get regs on stack 820 lea(c_rarg0, ExternalAddress((address) msg)); 821 lea(c_rarg1, InternalAddress(rip)); 822 movq(c_rarg2, rsp); // pass pointer to regs array 823 andq(rsp, -16); // align stack as required by ABI 824 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 825 hlt(); 826 } 827 828 void MacroAssembler::warn(const char* msg) { 829 push(rbp); 830 movq(rbp, rsp); 831 andq(rsp, -16); // align stack as required by push_CPU_state and call 832 push_CPU_state(); // keeps alignment at 16 bytes 833 lea(c_rarg0, ExternalAddress((address) msg)); 834 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 835 pop_CPU_state(); 836 mov(rsp, rbp); 837 pop(rbp); 838 } 839 840 void MacroAssembler::print_state() { 841 address rip = pc(); 842 pusha(); // get regs on stack 843 push(rbp); 844 movq(rbp, rsp); 845 andq(rsp, -16); // align stack as required by push_CPU_state and call 846 push_CPU_state(); // keeps alignment at 16 bytes 847 848 lea(c_rarg0, InternalAddress(rip)); 849 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 850 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 851 852 pop_CPU_state(); 853 mov(rsp, rbp); 854 pop(rbp); 855 popa(); 856 } 857 858 #ifndef PRODUCT 859 extern "C" void findpc(intptr_t x); 860 #endif 861 862 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 863 // In order to get locks to work, we need to fake a in_VM state 864 if (ShowMessageBoxOnError) { 865 JavaThread* thread = JavaThread::current(); 866 JavaThreadState saved_state = thread->thread_state(); 867 thread->set_thread_state(_thread_in_vm); 868 #ifndef PRODUCT 869 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 870 ttyLocker ttyl; 871 BytecodeCounter::print(); 872 } 873 #endif 874 // To see where a verify_oop failed, get $ebx+40/X for this frame. 875 // XXX correct this offset for amd64 876 // This is the value of eip which points to where verify_oop will return. 877 if (os::message_box(msg, "Execution stopped, print registers?")) { 878 print_state64(pc, regs); 879 BREAKPOINT; 880 assert(false, "start up GDB"); 881 } 882 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 883 } else { 884 ttyLocker ttyl; 885 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 886 msg); 887 assert(false, "DEBUG MESSAGE: %s", msg); 888 } 889 } 890 891 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 892 ttyLocker ttyl; 893 FlagSetting fs(Debugging, true); 894 tty->print_cr("rip = 0x%016lx", pc); 895 #ifndef PRODUCT 896 tty->cr(); 897 findpc(pc); 898 tty->cr(); 899 #endif 900 #define PRINT_REG(rax, value) \ 901 { tty->print("%s = ", #rax); os::print_location(tty, value); } 902 PRINT_REG(rax, regs[15]); 903 PRINT_REG(rbx, regs[12]); 904 PRINT_REG(rcx, regs[14]); 905 PRINT_REG(rdx, regs[13]); 906 PRINT_REG(rdi, regs[8]); 907 PRINT_REG(rsi, regs[9]); 908 PRINT_REG(rbp, regs[10]); 909 PRINT_REG(rsp, regs[11]); 910 PRINT_REG(r8 , regs[7]); 911 PRINT_REG(r9 , regs[6]); 912 PRINT_REG(r10, regs[5]); 913 PRINT_REG(r11, regs[4]); 914 PRINT_REG(r12, regs[3]); 915 PRINT_REG(r13, regs[2]); 916 PRINT_REG(r14, regs[1]); 917 PRINT_REG(r15, regs[0]); 918 #undef PRINT_REG 919 // Print some words near top of staack. 920 int64_t* rsp = (int64_t*) regs[11]; 921 int64_t* dump_sp = rsp; 922 for (int col1 = 0; col1 < 8; col1++) { 923 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 924 os::print_location(tty, *dump_sp++); 925 } 926 for (int row = 0; row < 25; row++) { 927 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 928 for (int col = 0; col < 4; col++) { 929 tty->print(" 0x%016lx", *dump_sp++); 930 } 931 tty->cr(); 932 } 933 // Print some instructions around pc: 934 Disassembler::decode((address)pc-64, (address)pc); 935 tty->print_cr("--------"); 936 Disassembler::decode((address)pc, (address)pc+32); 937 } 938 939 #endif // _LP64 940 941 // Now versions that are common to 32/64 bit 942 943 void MacroAssembler::addptr(Register dst, int32_t imm32) { 944 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 945 } 946 947 void MacroAssembler::addptr(Register dst, Register src) { 948 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 949 } 950 951 void MacroAssembler::addptr(Address dst, Register src) { 952 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 953 } 954 955 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 956 if (reachable(src)) { 957 Assembler::addsd(dst, as_Address(src)); 958 } else { 959 lea(rscratch1, src); 960 Assembler::addsd(dst, Address(rscratch1, 0)); 961 } 962 } 963 964 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 965 if (reachable(src)) { 966 addss(dst, as_Address(src)); 967 } else { 968 lea(rscratch1, src); 969 addss(dst, Address(rscratch1, 0)); 970 } 971 } 972 973 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 974 if (reachable(src)) { 975 Assembler::addpd(dst, as_Address(src)); 976 } else { 977 lea(rscratch1, src); 978 Assembler::addpd(dst, Address(rscratch1, 0)); 979 } 980 } 981 982 void MacroAssembler::align(int modulus) { 983 align(modulus, offset()); 984 } 985 986 void MacroAssembler::align(int modulus, int target) { 987 if (target % modulus != 0) { 988 nop(modulus - (target % modulus)); 989 } 990 } 991 992 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 993 // Used in sign-masking with aligned address. 994 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 995 if (reachable(src)) { 996 Assembler::andpd(dst, as_Address(src)); 997 } else { 998 lea(rscratch1, src); 999 Assembler::andpd(dst, Address(rscratch1, 0)); 1000 } 1001 } 1002 1003 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 1004 // Used in sign-masking with aligned address. 1005 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1006 if (reachable(src)) { 1007 Assembler::andps(dst, as_Address(src)); 1008 } else { 1009 lea(rscratch1, src); 1010 Assembler::andps(dst, Address(rscratch1, 0)); 1011 } 1012 } 1013 1014 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1015 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1016 } 1017 1018 void MacroAssembler::atomic_incl(Address counter_addr) { 1019 if (os::is_MP()) 1020 lock(); 1021 incrementl(counter_addr); 1022 } 1023 1024 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1025 if (reachable(counter_addr)) { 1026 atomic_incl(as_Address(counter_addr)); 1027 } else { 1028 lea(scr, counter_addr); 1029 atomic_incl(Address(scr, 0)); 1030 } 1031 } 1032 1033 #ifdef _LP64 1034 void MacroAssembler::atomic_incq(Address counter_addr) { 1035 if (os::is_MP()) 1036 lock(); 1037 incrementq(counter_addr); 1038 } 1039 1040 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1041 if (reachable(counter_addr)) { 1042 atomic_incq(as_Address(counter_addr)); 1043 } else { 1044 lea(scr, counter_addr); 1045 atomic_incq(Address(scr, 0)); 1046 } 1047 } 1048 #endif 1049 1050 // Writes to stack successive pages until offset reached to check for 1051 // stack overflow + shadow pages. This clobbers tmp. 1052 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1053 movptr(tmp, rsp); 1054 // Bang stack for total size given plus shadow page size. 1055 // Bang one page at a time because large size can bang beyond yellow and 1056 // red zones. 1057 Label loop; 1058 bind(loop); 1059 movl(Address(tmp, (-os::vm_page_size())), size ); 1060 subptr(tmp, os::vm_page_size()); 1061 subl(size, os::vm_page_size()); 1062 jcc(Assembler::greater, loop); 1063 1064 // Bang down shadow pages too. 1065 // At this point, (tmp-0) is the last address touched, so don't 1066 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1067 // was post-decremented.) Skip this address by starting at i=1, and 1068 // touch a few more pages below. N.B. It is important to touch all 1069 // the way down including all pages in the shadow zone. 1070 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1071 // this could be any sized move but this is can be a debugging crumb 1072 // so the bigger the better. 1073 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1074 } 1075 } 1076 1077 void MacroAssembler::reserved_stack_check() { 1078 // testing if reserved zone needs to be enabled 1079 Label no_reserved_zone_enabling; 1080 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1081 NOT_LP64(get_thread(rsi);) 1082 1083 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1084 jcc(Assembler::below, no_reserved_zone_enabling); 1085 1086 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1087 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1088 should_not_reach_here(); 1089 1090 bind(no_reserved_zone_enabling); 1091 } 1092 1093 int MacroAssembler::biased_locking_enter(Register lock_reg, 1094 Register obj_reg, 1095 Register swap_reg, 1096 Register tmp_reg, 1097 bool swap_reg_contains_mark, 1098 Label& done, 1099 Label* slow_case, 1100 BiasedLockingCounters* counters) { 1101 assert(UseBiasedLocking, "why call this otherwise?"); 1102 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1103 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1104 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1105 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1106 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1107 NOT_LP64( Address saved_mark_addr(lock_reg, 0); ) 1108 1109 if (PrintBiasedLockingStatistics && counters == NULL) { 1110 counters = BiasedLocking::counters(); 1111 } 1112 // Biased locking 1113 // See whether the lock is currently biased toward our thread and 1114 // whether the epoch is still valid 1115 // Note that the runtime guarantees sufficient alignment of JavaThread 1116 // pointers to allow age to be placed into low bits 1117 // First check to see whether biasing is even enabled for this object 1118 Label cas_label; 1119 int null_check_offset = -1; 1120 if (!swap_reg_contains_mark) { 1121 null_check_offset = offset(); 1122 movptr(swap_reg, mark_addr); 1123 } 1124 movptr(tmp_reg, swap_reg); 1125 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1126 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1127 jcc(Assembler::notEqual, cas_label); 1128 // The bias pattern is present in the object's header. Need to check 1129 // whether the bias owner and the epoch are both still current. 1130 #ifndef _LP64 1131 // Note that because there is no current thread register on x86_32 we 1132 // need to store off the mark word we read out of the object to 1133 // avoid reloading it and needing to recheck invariants below. This 1134 // store is unfortunate but it makes the overall code shorter and 1135 // simpler. 1136 movptr(saved_mark_addr, swap_reg); 1137 #endif 1138 if (swap_reg_contains_mark) { 1139 null_check_offset = offset(); 1140 } 1141 load_prototype_header(tmp_reg, obj_reg); 1142 #ifdef _LP64 1143 orptr(tmp_reg, r15_thread); 1144 xorptr(tmp_reg, swap_reg); 1145 Register header_reg = tmp_reg; 1146 #else 1147 xorptr(tmp_reg, swap_reg); 1148 get_thread(swap_reg); 1149 xorptr(swap_reg, tmp_reg); 1150 Register header_reg = swap_reg; 1151 #endif 1152 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1153 if (counters != NULL) { 1154 cond_inc32(Assembler::zero, 1155 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1156 } 1157 jcc(Assembler::equal, done); 1158 1159 Label try_revoke_bias; 1160 Label try_rebias; 1161 1162 // At this point we know that the header has the bias pattern and 1163 // that we are not the bias owner in the current epoch. We need to 1164 // figure out more details about the state of the header in order to 1165 // know what operations can be legally performed on the object's 1166 // header. 1167 1168 // If the low three bits in the xor result aren't clear, that means 1169 // the prototype header is no longer biased and we have to revoke 1170 // the bias on this object. 1171 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1172 jccb(Assembler::notZero, try_revoke_bias); 1173 1174 // Biasing is still enabled for this data type. See whether the 1175 // epoch of the current bias is still valid, meaning that the epoch 1176 // bits of the mark word are equal to the epoch bits of the 1177 // prototype header. (Note that the prototype header's epoch bits 1178 // only change at a safepoint.) If not, attempt to rebias the object 1179 // toward the current thread. Note that we must be absolutely sure 1180 // that the current epoch is invalid in order to do this because 1181 // otherwise the manipulations it performs on the mark word are 1182 // illegal. 1183 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1184 jccb(Assembler::notZero, try_rebias); 1185 1186 // The epoch of the current bias is still valid but we know nothing 1187 // about the owner; it might be set or it might be clear. Try to 1188 // acquire the bias of the object using an atomic operation. If this 1189 // fails we will go in to the runtime to revoke the object's bias. 1190 // Note that we first construct the presumed unbiased header so we 1191 // don't accidentally blow away another thread's valid bias. 1192 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1193 andptr(swap_reg, 1194 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1195 #ifdef _LP64 1196 movptr(tmp_reg, swap_reg); 1197 orptr(tmp_reg, r15_thread); 1198 #else 1199 get_thread(tmp_reg); 1200 orptr(tmp_reg, swap_reg); 1201 #endif 1202 if (os::is_MP()) { 1203 lock(); 1204 } 1205 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1206 // If the biasing toward our thread failed, this means that 1207 // another thread succeeded in biasing it toward itself and we 1208 // need to revoke that bias. The revocation will occur in the 1209 // interpreter runtime in the slow case. 1210 if (counters != NULL) { 1211 cond_inc32(Assembler::zero, 1212 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1213 } 1214 if (slow_case != NULL) { 1215 jcc(Assembler::notZero, *slow_case); 1216 } 1217 jmp(done); 1218 1219 bind(try_rebias); 1220 // At this point we know the epoch has expired, meaning that the 1221 // current "bias owner", if any, is actually invalid. Under these 1222 // circumstances _only_, we are allowed to use the current header's 1223 // value as the comparison value when doing the cas to acquire the 1224 // bias in the current epoch. In other words, we allow transfer of 1225 // the bias from one thread to another directly in this situation. 1226 // 1227 // FIXME: due to a lack of registers we currently blow away the age 1228 // bits in this situation. Should attempt to preserve them. 1229 load_prototype_header(tmp_reg, obj_reg); 1230 #ifdef _LP64 1231 orptr(tmp_reg, r15_thread); 1232 #else 1233 get_thread(swap_reg); 1234 orptr(tmp_reg, swap_reg); 1235 movptr(swap_reg, saved_mark_addr); 1236 #endif 1237 if (os::is_MP()) { 1238 lock(); 1239 } 1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1241 // If the biasing toward our thread failed, then another thread 1242 // succeeded in biasing it toward itself and we need to revoke that 1243 // bias. The revocation will occur in the runtime in the slow case. 1244 if (counters != NULL) { 1245 cond_inc32(Assembler::zero, 1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1247 } 1248 if (slow_case != NULL) { 1249 jcc(Assembler::notZero, *slow_case); 1250 } 1251 jmp(done); 1252 1253 bind(try_revoke_bias); 1254 // The prototype mark in the klass doesn't have the bias bit set any 1255 // more, indicating that objects of this data type are not supposed 1256 // to be biased any more. We are going to try to reset the mark of 1257 // this object to the prototype value and fall through to the 1258 // CAS-based locking scheme. Note that if our CAS fails, it means 1259 // that another thread raced us for the privilege of revoking the 1260 // bias of this particular object, so it's okay to continue in the 1261 // normal locking code. 1262 // 1263 // FIXME: due to a lack of registers we currently blow away the age 1264 // bits in this situation. Should attempt to preserve them. 1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1266 load_prototype_header(tmp_reg, obj_reg); 1267 if (os::is_MP()) { 1268 lock(); 1269 } 1270 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1271 // Fall through to the normal CAS-based lock, because no matter what 1272 // the result of the above CAS, some thread must have succeeded in 1273 // removing the bias bit from the object's header. 1274 if (counters != NULL) { 1275 cond_inc32(Assembler::zero, 1276 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1277 } 1278 1279 bind(cas_label); 1280 1281 return null_check_offset; 1282 } 1283 1284 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1285 assert(UseBiasedLocking, "why call this otherwise?"); 1286 1287 // Check for biased locking unlock case, which is a no-op 1288 // Note: we do not have to check the thread ID for two reasons. 1289 // First, the interpreter checks for IllegalMonitorStateException at 1290 // a higher level. Second, if the bias was revoked while we held the 1291 // lock, the object could not be rebiased toward another thread, so 1292 // the bias bit would be clear. 1293 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1294 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1295 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1296 jcc(Assembler::equal, done); 1297 } 1298 1299 #ifdef COMPILER2 1300 1301 #if INCLUDE_RTM_OPT 1302 1303 // Update rtm_counters based on abort status 1304 // input: abort_status 1305 // rtm_counters (RTMLockingCounters*) 1306 // flags are killed 1307 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1308 1309 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1310 if (PrintPreciseRTMLockingStatistics) { 1311 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1312 Label check_abort; 1313 testl(abort_status, (1<<i)); 1314 jccb(Assembler::equal, check_abort); 1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1316 bind(check_abort); 1317 } 1318 } 1319 } 1320 1321 // Branch if (random & (count-1) != 0), count is 2^n 1322 // tmp, scr and flags are killed 1323 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1324 assert(tmp == rax, ""); 1325 assert(scr == rdx, ""); 1326 rdtsc(); // modifies EDX:EAX 1327 andptr(tmp, count-1); 1328 jccb(Assembler::notZero, brLabel); 1329 } 1330 1331 // Perform abort ratio calculation, set no_rtm bit if high ratio 1332 // input: rtm_counters_Reg (RTMLockingCounters* address) 1333 // tmpReg, rtm_counters_Reg and flags are killed 1334 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1335 Register rtm_counters_Reg, 1336 RTMLockingCounters* rtm_counters, 1337 Metadata* method_data) { 1338 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1339 1340 if (RTMLockingCalculationDelay > 0) { 1341 // Delay calculation 1342 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1343 testptr(tmpReg, tmpReg); 1344 jccb(Assembler::equal, L_done); 1345 } 1346 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1347 // Aborted transactions = abort_count * 100 1348 // All transactions = total_count * RTMTotalCountIncrRate 1349 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1350 1351 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1352 cmpptr(tmpReg, RTMAbortThreshold); 1353 jccb(Assembler::below, L_check_always_rtm2); 1354 imulptr(tmpReg, tmpReg, 100); 1355 1356 Register scrReg = rtm_counters_Reg; 1357 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1358 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1359 imulptr(scrReg, scrReg, RTMAbortRatio); 1360 cmpptr(tmpReg, scrReg); 1361 jccb(Assembler::below, L_check_always_rtm1); 1362 if (method_data != NULL) { 1363 // set rtm_state to "no rtm" in MDO 1364 mov_metadata(tmpReg, method_data); 1365 if (os::is_MP()) { 1366 lock(); 1367 } 1368 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1369 } 1370 jmpb(L_done); 1371 bind(L_check_always_rtm1); 1372 // Reload RTMLockingCounters* address 1373 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1374 bind(L_check_always_rtm2); 1375 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1376 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1377 jccb(Assembler::below, L_done); 1378 if (method_data != NULL) { 1379 // set rtm_state to "always rtm" in MDO 1380 mov_metadata(tmpReg, method_data); 1381 if (os::is_MP()) { 1382 lock(); 1383 } 1384 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1385 } 1386 bind(L_done); 1387 } 1388 1389 // Update counters and perform abort ratio calculation 1390 // input: abort_status_Reg 1391 // rtm_counters_Reg, flags are killed 1392 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1393 Register rtm_counters_Reg, 1394 RTMLockingCounters* rtm_counters, 1395 Metadata* method_data, 1396 bool profile_rtm) { 1397 1398 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1399 // update rtm counters based on rax value at abort 1400 // reads abort_status_Reg, updates flags 1401 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1402 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1403 if (profile_rtm) { 1404 // Save abort status because abort_status_Reg is used by following code. 1405 if (RTMRetryCount > 0) { 1406 push(abort_status_Reg); 1407 } 1408 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1409 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1410 // restore abort status 1411 if (RTMRetryCount > 0) { 1412 pop(abort_status_Reg); 1413 } 1414 } 1415 } 1416 1417 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1418 // inputs: retry_count_Reg 1419 // : abort_status_Reg 1420 // output: retry_count_Reg decremented by 1 1421 // flags are killed 1422 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1423 Label doneRetry; 1424 assert(abort_status_Reg == rax, ""); 1425 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1426 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1427 // if reason is in 0x6 and retry count != 0 then retry 1428 andptr(abort_status_Reg, 0x6); 1429 jccb(Assembler::zero, doneRetry); 1430 testl(retry_count_Reg, retry_count_Reg); 1431 jccb(Assembler::zero, doneRetry); 1432 pause(); 1433 decrementl(retry_count_Reg); 1434 jmp(retryLabel); 1435 bind(doneRetry); 1436 } 1437 1438 // Spin and retry if lock is busy, 1439 // inputs: box_Reg (monitor address) 1440 // : retry_count_Reg 1441 // output: retry_count_Reg decremented by 1 1442 // : clear z flag if retry count exceeded 1443 // tmp_Reg, scr_Reg, flags are killed 1444 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1445 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1446 Label SpinLoop, SpinExit, doneRetry; 1447 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1448 1449 testl(retry_count_Reg, retry_count_Reg); 1450 jccb(Assembler::zero, doneRetry); 1451 decrementl(retry_count_Reg); 1452 movptr(scr_Reg, RTMSpinLoopCount); 1453 1454 bind(SpinLoop); 1455 pause(); 1456 decrementl(scr_Reg); 1457 jccb(Assembler::lessEqual, SpinExit); 1458 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1459 testptr(tmp_Reg, tmp_Reg); 1460 jccb(Assembler::notZero, SpinLoop); 1461 1462 bind(SpinExit); 1463 jmp(retryLabel); 1464 bind(doneRetry); 1465 incrementl(retry_count_Reg); // clear z flag 1466 } 1467 1468 // Use RTM for normal stack locks 1469 // Input: objReg (object to lock) 1470 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1471 Register retry_on_abort_count_Reg, 1472 RTMLockingCounters* stack_rtm_counters, 1473 Metadata* method_data, bool profile_rtm, 1474 Label& DONE_LABEL, Label& IsInflated) { 1475 assert(UseRTMForStackLocks, "why call this otherwise?"); 1476 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1477 assert(tmpReg == rax, ""); 1478 assert(scrReg == rdx, ""); 1479 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1480 1481 if (RTMRetryCount > 0) { 1482 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1483 bind(L_rtm_retry); 1484 } 1485 movptr(tmpReg, Address(objReg, 0)); 1486 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1487 jcc(Assembler::notZero, IsInflated); 1488 1489 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1490 Label L_noincrement; 1491 if (RTMTotalCountIncrRate > 1) { 1492 // tmpReg, scrReg and flags are killed 1493 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1494 } 1495 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1496 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1497 bind(L_noincrement); 1498 } 1499 xbegin(L_on_abort); 1500 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1501 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1502 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1503 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1504 1505 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1506 if (UseRTMXendForLockBusy) { 1507 xend(); 1508 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1509 jmp(L_decrement_retry); 1510 } 1511 else { 1512 xabort(0); 1513 } 1514 bind(L_on_abort); 1515 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1516 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1517 } 1518 bind(L_decrement_retry); 1519 if (RTMRetryCount > 0) { 1520 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1521 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1522 } 1523 } 1524 1525 // Use RTM for inflating locks 1526 // inputs: objReg (object to lock) 1527 // boxReg (on-stack box address (displaced header location) - KILLED) 1528 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1529 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1530 Register scrReg, Register retry_on_busy_count_Reg, 1531 Register retry_on_abort_count_Reg, 1532 RTMLockingCounters* rtm_counters, 1533 Metadata* method_data, bool profile_rtm, 1534 Label& DONE_LABEL) { 1535 assert(UseRTMLocking, "why call this otherwise?"); 1536 assert(tmpReg == rax, ""); 1537 assert(scrReg == rdx, ""); 1538 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1539 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1540 1541 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1542 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1543 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1544 1545 if (RTMRetryCount > 0) { 1546 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1547 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1548 bind(L_rtm_retry); 1549 } 1550 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1551 Label L_noincrement; 1552 if (RTMTotalCountIncrRate > 1) { 1553 // tmpReg, scrReg and flags are killed 1554 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1555 } 1556 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1557 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1558 bind(L_noincrement); 1559 } 1560 xbegin(L_on_abort); 1561 movptr(tmpReg, Address(objReg, 0)); 1562 movptr(tmpReg, Address(tmpReg, owner_offset)); 1563 testptr(tmpReg, tmpReg); 1564 jcc(Assembler::zero, DONE_LABEL); 1565 if (UseRTMXendForLockBusy) { 1566 xend(); 1567 jmp(L_decrement_retry); 1568 } 1569 else { 1570 xabort(0); 1571 } 1572 bind(L_on_abort); 1573 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1574 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1575 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1576 } 1577 if (RTMRetryCount > 0) { 1578 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1579 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1580 } 1581 1582 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1583 testptr(tmpReg, tmpReg) ; 1584 jccb(Assembler::notZero, L_decrement_retry) ; 1585 1586 // Appears unlocked - try to swing _owner from null to non-null. 1587 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1588 #ifdef _LP64 1589 Register threadReg = r15_thread; 1590 #else 1591 get_thread(scrReg); 1592 Register threadReg = scrReg; 1593 #endif 1594 if (os::is_MP()) { 1595 lock(); 1596 } 1597 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1598 1599 if (RTMRetryCount > 0) { 1600 // success done else retry 1601 jccb(Assembler::equal, DONE_LABEL) ; 1602 bind(L_decrement_retry); 1603 // Spin and retry if lock is busy. 1604 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1605 } 1606 else { 1607 bind(L_decrement_retry); 1608 } 1609 } 1610 1611 #endif // INCLUDE_RTM_OPT 1612 1613 // Fast_Lock and Fast_Unlock used by C2 1614 1615 // Because the transitions from emitted code to the runtime 1616 // monitorenter/exit helper stubs are so slow it's critical that 1617 // we inline both the stack-locking fast-path and the inflated fast path. 1618 // 1619 // See also: cmpFastLock and cmpFastUnlock. 1620 // 1621 // What follows is a specialized inline transliteration of the code 1622 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1623 // another option would be to emit TrySlowEnter and TrySlowExit methods 1624 // at startup-time. These methods would accept arguments as 1625 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1626 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1627 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1628 // In practice, however, the # of lock sites is bounded and is usually small. 1629 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1630 // if the processor uses simple bimodal branch predictors keyed by EIP 1631 // Since the helper routines would be called from multiple synchronization 1632 // sites. 1633 // 1634 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1635 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1636 // to those specialized methods. That'd give us a mostly platform-independent 1637 // implementation that the JITs could optimize and inline at their pleasure. 1638 // Done correctly, the only time we'd need to cross to native could would be 1639 // to park() or unpark() threads. We'd also need a few more unsafe operators 1640 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1641 // (b) explicit barriers or fence operations. 1642 // 1643 // TODO: 1644 // 1645 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1646 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1647 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1648 // the lock operators would typically be faster than reifying Self. 1649 // 1650 // * Ideally I'd define the primitives as: 1651 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1652 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1653 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1654 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1655 // Furthermore the register assignments are overconstrained, possibly resulting in 1656 // sub-optimal code near the synchronization site. 1657 // 1658 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1659 // Alternately, use a better sp-proximity test. 1660 // 1661 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1662 // Either one is sufficient to uniquely identify a thread. 1663 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1664 // 1665 // * Intrinsify notify() and notifyAll() for the common cases where the 1666 // object is locked by the calling thread but the waitlist is empty. 1667 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1668 // 1669 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1670 // But beware of excessive branch density on AMD Opterons. 1671 // 1672 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1673 // or failure of the fast-path. If the fast-path fails then we pass 1674 // control to the slow-path, typically in C. In Fast_Lock and 1675 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1676 // will emit a conditional branch immediately after the node. 1677 // So we have branches to branches and lots of ICC.ZF games. 1678 // Instead, it might be better to have C2 pass a "FailureLabel" 1679 // into Fast_Lock and Fast_Unlock. In the case of success, control 1680 // will drop through the node. ICC.ZF is undefined at exit. 1681 // In the case of failure, the node will branch directly to the 1682 // FailureLabel 1683 1684 1685 // obj: object to lock 1686 // box: on-stack box address (displaced header location) - KILLED 1687 // rax,: tmp -- KILLED 1688 // scr: tmp -- KILLED 1689 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1690 Register scrReg, Register cx1Reg, Register cx2Reg, 1691 BiasedLockingCounters* counters, 1692 RTMLockingCounters* rtm_counters, 1693 RTMLockingCounters* stack_rtm_counters, 1694 Metadata* method_data, 1695 bool use_rtm, bool profile_rtm) { 1696 // Ensure the register assignments are disjoint 1697 assert(tmpReg == rax, ""); 1698 1699 if (use_rtm) { 1700 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1701 } else { 1702 assert(cx1Reg == noreg, ""); 1703 assert(cx2Reg == noreg, ""); 1704 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1705 } 1706 1707 if (counters != NULL) { 1708 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1709 } 1710 if (EmitSync & 1) { 1711 // set box->dhw = markOopDesc::unused_mark() 1712 // Force all sync thru slow-path: slow_enter() and slow_exit() 1713 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1714 cmpptr (rsp, (int32_t)NULL_WORD); 1715 } else { 1716 // Possible cases that we'll encounter in fast_lock 1717 // ------------------------------------------------ 1718 // * Inflated 1719 // -- unlocked 1720 // -- Locked 1721 // = by self 1722 // = by other 1723 // * biased 1724 // -- by Self 1725 // -- by other 1726 // * neutral 1727 // * stack-locked 1728 // -- by self 1729 // = sp-proximity test hits 1730 // = sp-proximity test generates false-negative 1731 // -- by other 1732 // 1733 1734 Label IsInflated, DONE_LABEL; 1735 1736 // it's stack-locked, biased or neutral 1737 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1738 // order to reduce the number of conditional branches in the most common cases. 1739 // Beware -- there's a subtle invariant that fetch of the markword 1740 // at [FETCH], below, will never observe a biased encoding (*101b). 1741 // If this invariant is not held we risk exclusion (safety) failure. 1742 if (UseBiasedLocking && !UseOptoBiasInlining) { 1743 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1744 } 1745 1746 #if INCLUDE_RTM_OPT 1747 if (UseRTMForStackLocks && use_rtm) { 1748 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1749 stack_rtm_counters, method_data, profile_rtm, 1750 DONE_LABEL, IsInflated); 1751 } 1752 #endif // INCLUDE_RTM_OPT 1753 1754 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1755 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1756 jccb(Assembler::notZero, IsInflated); 1757 1758 // Attempt stack-locking ... 1759 orptr (tmpReg, markOopDesc::unlocked_value); 1760 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1761 if (os::is_MP()) { 1762 lock(); 1763 } 1764 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1765 if (counters != NULL) { 1766 cond_inc32(Assembler::equal, 1767 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1768 } 1769 jcc(Assembler::equal, DONE_LABEL); // Success 1770 1771 // Recursive locking. 1772 // The object is stack-locked: markword contains stack pointer to BasicLock. 1773 // Locked by current thread if difference with current SP is less than one page. 1774 subptr(tmpReg, rsp); 1775 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1776 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1777 movptr(Address(boxReg, 0), tmpReg); 1778 if (counters != NULL) { 1779 cond_inc32(Assembler::equal, 1780 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1781 } 1782 jmp(DONE_LABEL); 1783 1784 bind(IsInflated); 1785 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1786 1787 #if INCLUDE_RTM_OPT 1788 // Use the same RTM locking code in 32- and 64-bit VM. 1789 if (use_rtm) { 1790 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1791 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1792 } else { 1793 #endif // INCLUDE_RTM_OPT 1794 1795 #ifndef _LP64 1796 // The object is inflated. 1797 1798 // boxReg refers to the on-stack BasicLock in the current frame. 1799 // We'd like to write: 1800 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1801 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1802 // additional latency as we have another ST in the store buffer that must drain. 1803 1804 if (EmitSync & 8192) { 1805 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1806 get_thread (scrReg); 1807 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1808 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1809 if (os::is_MP()) { 1810 lock(); 1811 } 1812 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1813 } else 1814 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1815 // register juggle because we need tmpReg for cmpxchgptr below 1816 movptr(scrReg, boxReg); 1817 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1818 1819 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1820 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1821 // prefetchw [eax + Offset(_owner)-2] 1822 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1823 } 1824 1825 if ((EmitSync & 64) == 0) { 1826 // Optimistic form: consider XORL tmpReg,tmpReg 1827 movptr(tmpReg, NULL_WORD); 1828 } else { 1829 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1830 // Test-And-CAS instead of CAS 1831 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1832 testptr(tmpReg, tmpReg); // Locked ? 1833 jccb (Assembler::notZero, DONE_LABEL); 1834 } 1835 1836 // Appears unlocked - try to swing _owner from null to non-null. 1837 // Ideally, I'd manifest "Self" with get_thread and then attempt 1838 // to CAS the register containing Self into m->Owner. 1839 // But we don't have enough registers, so instead we can either try to CAS 1840 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1841 // we later store "Self" into m->Owner. Transiently storing a stack address 1842 // (rsp or the address of the box) into m->owner is harmless. 1843 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1844 if (os::is_MP()) { 1845 lock(); 1846 } 1847 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1848 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1849 // If we weren't able to swing _owner from NULL to the BasicLock 1850 // then take the slow path. 1851 jccb (Assembler::notZero, DONE_LABEL); 1852 // update _owner from BasicLock to thread 1853 get_thread (scrReg); // beware: clobbers ICCs 1854 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1855 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1856 1857 // If the CAS fails we can either retry or pass control to the slow-path. 1858 // We use the latter tactic. 1859 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1860 // If the CAS was successful ... 1861 // Self has acquired the lock 1862 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1863 // Intentional fall-through into DONE_LABEL ... 1864 } else { 1865 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1866 movptr(boxReg, tmpReg); 1867 1868 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1869 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1870 // prefetchw [eax + Offset(_owner)-2] 1871 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1872 } 1873 1874 if ((EmitSync & 64) == 0) { 1875 // Optimistic form 1876 xorptr (tmpReg, tmpReg); 1877 } else { 1878 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1879 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1880 testptr(tmpReg, tmpReg); // Locked ? 1881 jccb (Assembler::notZero, DONE_LABEL); 1882 } 1883 1884 // Appears unlocked - try to swing _owner from null to non-null. 1885 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1886 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1887 get_thread (scrReg); 1888 if (os::is_MP()) { 1889 lock(); 1890 } 1891 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1892 1893 // If the CAS fails we can either retry or pass control to the slow-path. 1894 // We use the latter tactic. 1895 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1896 // If the CAS was successful ... 1897 // Self has acquired the lock 1898 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1899 // Intentional fall-through into DONE_LABEL ... 1900 } 1901 #else // _LP64 1902 // It's inflated 1903 movq(scrReg, tmpReg); 1904 xorq(tmpReg, tmpReg); 1905 1906 if (os::is_MP()) { 1907 lock(); 1908 } 1909 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1910 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1911 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1912 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1913 // Intentional fall-through into DONE_LABEL ... 1914 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1915 #endif // _LP64 1916 #if INCLUDE_RTM_OPT 1917 } // use_rtm() 1918 #endif 1919 // DONE_LABEL is a hot target - we'd really like to place it at the 1920 // start of cache line by padding with NOPs. 1921 // See the AMD and Intel software optimization manuals for the 1922 // most efficient "long" NOP encodings. 1923 // Unfortunately none of our alignment mechanisms suffice. 1924 bind(DONE_LABEL); 1925 1926 // At DONE_LABEL the icc ZFlag is set as follows ... 1927 // Fast_Unlock uses the same protocol. 1928 // ZFlag == 1 -> Success 1929 // ZFlag == 0 -> Failure - force control through the slow-path 1930 } 1931 } 1932 1933 // obj: object to unlock 1934 // box: box address (displaced header location), killed. Must be EAX. 1935 // tmp: killed, cannot be obj nor box. 1936 // 1937 // Some commentary on balanced locking: 1938 // 1939 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1940 // Methods that don't have provably balanced locking are forced to run in the 1941 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1942 // The interpreter provides two properties: 1943 // I1: At return-time the interpreter automatically and quietly unlocks any 1944 // objects acquired the current activation (frame). Recall that the 1945 // interpreter maintains an on-stack list of locks currently held by 1946 // a frame. 1947 // I2: If a method attempts to unlock an object that is not held by the 1948 // the frame the interpreter throws IMSX. 1949 // 1950 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1951 // B() doesn't have provably balanced locking so it runs in the interpreter. 1952 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1953 // is still locked by A(). 1954 // 1955 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1956 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1957 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1958 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1959 // Arguably given that the spec legislates the JNI case as undefined our implementation 1960 // could reasonably *avoid* checking owner in Fast_Unlock(). 1961 // In the interest of performance we elide m->Owner==Self check in unlock. 1962 // A perfectly viable alternative is to elide the owner check except when 1963 // Xcheck:jni is enabled. 1964 1965 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1966 assert(boxReg == rax, ""); 1967 assert_different_registers(objReg, boxReg, tmpReg); 1968 1969 if (EmitSync & 4) { 1970 // Disable - inhibit all inlining. Force control through the slow-path 1971 cmpptr (rsp, 0); 1972 } else { 1973 Label DONE_LABEL, Stacked, CheckSucc; 1974 1975 // Critically, the biased locking test must have precedence over 1976 // and appear before the (box->dhw == 0) recursive stack-lock test. 1977 if (UseBiasedLocking && !UseOptoBiasInlining) { 1978 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1979 } 1980 1981 #if INCLUDE_RTM_OPT 1982 if (UseRTMForStackLocks && use_rtm) { 1983 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1984 Label L_regular_unlock; 1985 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1986 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1987 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1988 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1989 xend(); // otherwise end... 1990 jmp(DONE_LABEL); // ... and we're done 1991 bind(L_regular_unlock); 1992 } 1993 #endif 1994 1995 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1996 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1997 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 1998 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 1999 jccb (Assembler::zero, Stacked); 2000 2001 // It's inflated. 2002 #if INCLUDE_RTM_OPT 2003 if (use_rtm) { 2004 Label L_regular_inflated_unlock; 2005 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 2006 movptr(boxReg, Address(tmpReg, owner_offset)); 2007 testptr(boxReg, boxReg); 2008 jccb(Assembler::notZero, L_regular_inflated_unlock); 2009 xend(); 2010 jmpb(DONE_LABEL); 2011 bind(L_regular_inflated_unlock); 2012 } 2013 #endif 2014 2015 // Despite our balanced locking property we still check that m->_owner == Self 2016 // as java routines or native JNI code called by this thread might 2017 // have released the lock. 2018 // Refer to the comments in synchronizer.cpp for how we might encode extra 2019 // state in _succ so we can avoid fetching EntryList|cxq. 2020 // 2021 // I'd like to add more cases in fast_lock() and fast_unlock() -- 2022 // such as recursive enter and exit -- but we have to be wary of 2023 // I$ bloat, T$ effects and BP$ effects. 2024 // 2025 // If there's no contention try a 1-0 exit. That is, exit without 2026 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2027 // we detect and recover from the race that the 1-0 exit admits. 2028 // 2029 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2030 // before it STs null into _owner, releasing the lock. Updates 2031 // to data protected by the critical section must be visible before 2032 // we drop the lock (and thus before any other thread could acquire 2033 // the lock and observe the fields protected by the lock). 2034 // IA32's memory-model is SPO, so STs are ordered with respect to 2035 // each other and there's no need for an explicit barrier (fence). 2036 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2037 #ifndef _LP64 2038 get_thread (boxReg); 2039 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2040 // prefetchw [ebx + Offset(_owner)-2] 2041 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2042 } 2043 2044 // Note that we could employ various encoding schemes to reduce 2045 // the number of loads below (currently 4) to just 2 or 3. 2046 // Refer to the comments in synchronizer.cpp. 2047 // In practice the chain of fetches doesn't seem to impact performance, however. 2048 xorptr(boxReg, boxReg); 2049 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2050 // Attempt to reduce branch density - AMD's branch predictor. 2051 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2052 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2054 jccb (Assembler::notZero, DONE_LABEL); 2055 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2056 jmpb (DONE_LABEL); 2057 } else { 2058 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2059 jccb (Assembler::notZero, DONE_LABEL); 2060 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2061 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2062 jccb (Assembler::notZero, CheckSucc); 2063 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2064 jmpb (DONE_LABEL); 2065 } 2066 2067 // The Following code fragment (EmitSync & 65536) improves the performance of 2068 // contended applications and contended synchronization microbenchmarks. 2069 // Unfortunately the emission of the code - even though not executed - causes regressions 2070 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2071 // with an equal number of never-executed NOPs results in the same regression. 2072 // We leave it off by default. 2073 2074 if ((EmitSync & 65536) != 0) { 2075 Label LSuccess, LGoSlowPath ; 2076 2077 bind (CheckSucc); 2078 2079 // Optional pre-test ... it's safe to elide this 2080 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2081 jccb(Assembler::zero, LGoSlowPath); 2082 2083 // We have a classic Dekker-style idiom: 2084 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2085 // There are a number of ways to implement the barrier: 2086 // (1) lock:andl &m->_owner, 0 2087 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2088 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2089 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2090 // (2) If supported, an explicit MFENCE is appealing. 2091 // In older IA32 processors MFENCE is slower than lock:add or xchg 2092 // particularly if the write-buffer is full as might be the case if 2093 // if stores closely precede the fence or fence-equivalent instruction. 2094 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2095 // as the situation has changed with Nehalem and Shanghai. 2096 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2097 // The $lines underlying the top-of-stack should be in M-state. 2098 // The locked add instruction is serializing, of course. 2099 // (4) Use xchg, which is serializing 2100 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2101 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2102 // The integer condition codes will tell us if succ was 0. 2103 // Since _succ and _owner should reside in the same $line and 2104 // we just stored into _owner, it's likely that the $line 2105 // remains in M-state for the lock:orl. 2106 // 2107 // We currently use (3), although it's likely that switching to (2) 2108 // is correct for the future. 2109 2110 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2111 if (os::is_MP()) { 2112 lock(); addptr(Address(rsp, 0), 0); 2113 } 2114 // Ratify _succ remains non-null 2115 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2116 jccb (Assembler::notZero, LSuccess); 2117 2118 xorptr(boxReg, boxReg); // box is really EAX 2119 if (os::is_MP()) { lock(); } 2120 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2121 // There's no successor so we tried to regrab the lock with the 2122 // placeholder value. If that didn't work, then another thread 2123 // grabbed the lock so we're done (and exit was a success). 2124 jccb (Assembler::notEqual, LSuccess); 2125 // Since we're low on registers we installed rsp as a placeholding in _owner. 2126 // Now install Self over rsp. This is safe as we're transitioning from 2127 // non-null to non=null 2128 get_thread (boxReg); 2129 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2130 // Intentional fall-through into LGoSlowPath ... 2131 2132 bind (LGoSlowPath); 2133 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2134 jmpb (DONE_LABEL); 2135 2136 bind (LSuccess); 2137 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2138 jmpb (DONE_LABEL); 2139 } 2140 2141 bind (Stacked); 2142 // It's not inflated and it's not recursively stack-locked and it's not biased. 2143 // It must be stack-locked. 2144 // Try to reset the header to displaced header. 2145 // The "box" value on the stack is stable, so we can reload 2146 // and be assured we observe the same value as above. 2147 movptr(tmpReg, Address(boxReg, 0)); 2148 if (os::is_MP()) { 2149 lock(); 2150 } 2151 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2152 // Intention fall-thru into DONE_LABEL 2153 2154 // DONE_LABEL is a hot target - we'd really like to place it at the 2155 // start of cache line by padding with NOPs. 2156 // See the AMD and Intel software optimization manuals for the 2157 // most efficient "long" NOP encodings. 2158 // Unfortunately none of our alignment mechanisms suffice. 2159 if ((EmitSync & 65536) == 0) { 2160 bind (CheckSucc); 2161 } 2162 #else // _LP64 2163 // It's inflated 2164 if (EmitSync & 1024) { 2165 // Emit code to check that _owner == Self 2166 // We could fold the _owner test into subsequent code more efficiently 2167 // than using a stand-alone check, but since _owner checking is off by 2168 // default we don't bother. We also might consider predicating the 2169 // _owner==Self check on Xcheck:jni or running on a debug build. 2170 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2171 xorptr(boxReg, r15_thread); 2172 } else { 2173 xorptr(boxReg, boxReg); 2174 } 2175 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2176 jccb (Assembler::notZero, DONE_LABEL); 2177 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2178 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2179 jccb (Assembler::notZero, CheckSucc); 2180 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2181 jmpb (DONE_LABEL); 2182 2183 if ((EmitSync & 65536) == 0) { 2184 // Try to avoid passing control into the slow_path ... 2185 Label LSuccess, LGoSlowPath ; 2186 bind (CheckSucc); 2187 2188 // The following optional optimization can be elided if necessary 2189 // Effectively: if (succ == null) goto SlowPath 2190 // The code reduces the window for a race, however, 2191 // and thus benefits performance. 2192 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2193 jccb (Assembler::zero, LGoSlowPath); 2194 2195 xorptr(boxReg, boxReg); 2196 if ((EmitSync & 16) && os::is_MP()) { 2197 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2198 } else { 2199 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2200 if (os::is_MP()) { 2201 // Memory barrier/fence 2202 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2203 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2204 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2205 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2206 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2207 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2208 lock(); addl(Address(rsp, 0), 0); 2209 } 2210 } 2211 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2212 jccb (Assembler::notZero, LSuccess); 2213 2214 // Rare inopportune interleaving - race. 2215 // The successor vanished in the small window above. 2216 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2217 // We need to ensure progress and succession. 2218 // Try to reacquire the lock. 2219 // If that fails then the new owner is responsible for succession and this 2220 // thread needs to take no further action and can exit via the fast path (success). 2221 // If the re-acquire succeeds then pass control into the slow path. 2222 // As implemented, this latter mode is horrible because we generated more 2223 // coherence traffic on the lock *and* artifically extended the critical section 2224 // length while by virtue of passing control into the slow path. 2225 2226 // box is really RAX -- the following CMPXCHG depends on that binding 2227 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2228 if (os::is_MP()) { lock(); } 2229 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2230 // There's no successor so we tried to regrab the lock. 2231 // If that didn't work, then another thread grabbed the 2232 // lock so we're done (and exit was a success). 2233 jccb (Assembler::notEqual, LSuccess); 2234 // Intentional fall-through into slow-path 2235 2236 bind (LGoSlowPath); 2237 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2238 jmpb (DONE_LABEL); 2239 2240 bind (LSuccess); 2241 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2242 jmpb (DONE_LABEL); 2243 } 2244 2245 bind (Stacked); 2246 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2247 if (os::is_MP()) { lock(); } 2248 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2249 2250 if (EmitSync & 65536) { 2251 bind (CheckSucc); 2252 } 2253 #endif 2254 bind(DONE_LABEL); 2255 } 2256 } 2257 #endif // COMPILER2 2258 2259 void MacroAssembler::c2bool(Register x) { 2260 // implements x == 0 ? 0 : 1 2261 // note: must only look at least-significant byte of x 2262 // since C-style booleans are stored in one byte 2263 // only! (was bug) 2264 andl(x, 0xFF); 2265 setb(Assembler::notZero, x); 2266 } 2267 2268 // Wouldn't need if AddressLiteral version had new name 2269 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2270 Assembler::call(L, rtype); 2271 } 2272 2273 void MacroAssembler::call(Register entry) { 2274 Assembler::call(entry); 2275 } 2276 2277 void MacroAssembler::call(AddressLiteral entry) { 2278 if (reachable(entry)) { 2279 Assembler::call_literal(entry.target(), entry.rspec()); 2280 } else { 2281 lea(rscratch1, entry); 2282 Assembler::call(rscratch1); 2283 } 2284 } 2285 2286 void MacroAssembler::ic_call(address entry, jint method_index) { 2287 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 2288 movptr(rax, (intptr_t)Universe::non_oop_word()); 2289 call(AddressLiteral(entry, rh)); 2290 } 2291 2292 // Implementation of call_VM versions 2293 2294 void MacroAssembler::call_VM(Register oop_result, 2295 address entry_point, 2296 bool check_exceptions) { 2297 Label C, E; 2298 call(C, relocInfo::none); 2299 jmp(E); 2300 2301 bind(C); 2302 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2303 ret(0); 2304 2305 bind(E); 2306 } 2307 2308 void MacroAssembler::call_VM(Register oop_result, 2309 address entry_point, 2310 Register arg_1, 2311 bool check_exceptions) { 2312 Label C, E; 2313 call(C, relocInfo::none); 2314 jmp(E); 2315 2316 bind(C); 2317 pass_arg1(this, arg_1); 2318 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2319 ret(0); 2320 2321 bind(E); 2322 } 2323 2324 void MacroAssembler::call_VM(Register oop_result, 2325 address entry_point, 2326 Register arg_1, 2327 Register arg_2, 2328 bool check_exceptions) { 2329 Label C, E; 2330 call(C, relocInfo::none); 2331 jmp(E); 2332 2333 bind(C); 2334 2335 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2336 2337 pass_arg2(this, arg_2); 2338 pass_arg1(this, arg_1); 2339 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2340 ret(0); 2341 2342 bind(E); 2343 } 2344 2345 void MacroAssembler::call_VM(Register oop_result, 2346 address entry_point, 2347 Register arg_1, 2348 Register arg_2, 2349 Register arg_3, 2350 bool check_exceptions) { 2351 Label C, E; 2352 call(C, relocInfo::none); 2353 jmp(E); 2354 2355 bind(C); 2356 2357 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2358 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2359 pass_arg3(this, arg_3); 2360 2361 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2362 pass_arg2(this, arg_2); 2363 2364 pass_arg1(this, arg_1); 2365 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2366 ret(0); 2367 2368 bind(E); 2369 } 2370 2371 void MacroAssembler::call_VM(Register oop_result, 2372 Register last_java_sp, 2373 address entry_point, 2374 int number_of_arguments, 2375 bool check_exceptions) { 2376 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2377 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2378 } 2379 2380 void MacroAssembler::call_VM(Register oop_result, 2381 Register last_java_sp, 2382 address entry_point, 2383 Register arg_1, 2384 bool check_exceptions) { 2385 pass_arg1(this, arg_1); 2386 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2387 } 2388 2389 void MacroAssembler::call_VM(Register oop_result, 2390 Register last_java_sp, 2391 address entry_point, 2392 Register arg_1, 2393 Register arg_2, 2394 bool check_exceptions) { 2395 2396 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2397 pass_arg2(this, arg_2); 2398 pass_arg1(this, arg_1); 2399 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2400 } 2401 2402 void MacroAssembler::call_VM(Register oop_result, 2403 Register last_java_sp, 2404 address entry_point, 2405 Register arg_1, 2406 Register arg_2, 2407 Register arg_3, 2408 bool check_exceptions) { 2409 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2410 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2411 pass_arg3(this, arg_3); 2412 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2413 pass_arg2(this, arg_2); 2414 pass_arg1(this, arg_1); 2415 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2416 } 2417 2418 void MacroAssembler::super_call_VM(Register oop_result, 2419 Register last_java_sp, 2420 address entry_point, 2421 int number_of_arguments, 2422 bool check_exceptions) { 2423 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2424 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2425 } 2426 2427 void MacroAssembler::super_call_VM(Register oop_result, 2428 Register last_java_sp, 2429 address entry_point, 2430 Register arg_1, 2431 bool check_exceptions) { 2432 pass_arg1(this, arg_1); 2433 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2434 } 2435 2436 void MacroAssembler::super_call_VM(Register oop_result, 2437 Register last_java_sp, 2438 address entry_point, 2439 Register arg_1, 2440 Register arg_2, 2441 bool check_exceptions) { 2442 2443 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2444 pass_arg2(this, arg_2); 2445 pass_arg1(this, arg_1); 2446 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2447 } 2448 2449 void MacroAssembler::super_call_VM(Register oop_result, 2450 Register last_java_sp, 2451 address entry_point, 2452 Register arg_1, 2453 Register arg_2, 2454 Register arg_3, 2455 bool check_exceptions) { 2456 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2457 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2458 pass_arg3(this, arg_3); 2459 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2460 pass_arg2(this, arg_2); 2461 pass_arg1(this, arg_1); 2462 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2463 } 2464 2465 void MacroAssembler::call_VM_base(Register oop_result, 2466 Register java_thread, 2467 Register last_java_sp, 2468 address entry_point, 2469 int number_of_arguments, 2470 bool check_exceptions) { 2471 // determine java_thread register 2472 if (!java_thread->is_valid()) { 2473 #ifdef _LP64 2474 java_thread = r15_thread; 2475 #else 2476 java_thread = rdi; 2477 get_thread(java_thread); 2478 #endif // LP64 2479 } 2480 // determine last_java_sp register 2481 if (!last_java_sp->is_valid()) { 2482 last_java_sp = rsp; 2483 } 2484 // debugging support 2485 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2486 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2487 #ifdef ASSERT 2488 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2489 // r12 is the heapbase. 2490 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2491 #endif // ASSERT 2492 2493 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2494 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2495 2496 // push java thread (becomes first argument of C function) 2497 2498 NOT_LP64(push(java_thread); number_of_arguments++); 2499 LP64_ONLY(mov(c_rarg0, r15_thread)); 2500 2501 // set last Java frame before call 2502 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2503 2504 // Only interpreter should have to set fp 2505 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2506 2507 // do the call, remove parameters 2508 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2509 2510 // restore the thread (cannot use the pushed argument since arguments 2511 // may be overwritten by C code generated by an optimizing compiler); 2512 // however can use the register value directly if it is callee saved. 2513 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2514 // rdi & rsi (also r15) are callee saved -> nothing to do 2515 #ifdef ASSERT 2516 guarantee(java_thread != rax, "change this code"); 2517 push(rax); 2518 { Label L; 2519 get_thread(rax); 2520 cmpptr(java_thread, rax); 2521 jcc(Assembler::equal, L); 2522 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2523 bind(L); 2524 } 2525 pop(rax); 2526 #endif 2527 } else { 2528 get_thread(java_thread); 2529 } 2530 // reset last Java frame 2531 // Only interpreter should have to clear fp 2532 reset_last_Java_frame(java_thread, true); 2533 2534 // C++ interp handles this in the interpreter 2535 check_and_handle_popframe(java_thread); 2536 check_and_handle_earlyret(java_thread); 2537 2538 if (check_exceptions) { 2539 // check for pending exceptions (java_thread is set upon return) 2540 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2541 #ifndef _LP64 2542 jump_cc(Assembler::notEqual, 2543 RuntimeAddress(StubRoutines::forward_exception_entry())); 2544 #else 2545 // This used to conditionally jump to forward_exception however it is 2546 // possible if we relocate that the branch will not reach. So we must jump 2547 // around so we can always reach 2548 2549 Label ok; 2550 jcc(Assembler::equal, ok); 2551 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2552 bind(ok); 2553 #endif // LP64 2554 } 2555 2556 // get oop result if there is one and reset the value in the thread 2557 if (oop_result->is_valid()) { 2558 get_vm_result(oop_result, java_thread); 2559 } 2560 } 2561 2562 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2563 2564 // Calculate the value for last_Java_sp 2565 // somewhat subtle. call_VM does an intermediate call 2566 // which places a return address on the stack just under the 2567 // stack pointer as the user finsihed with it. This allows 2568 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2569 // On 32bit we then have to push additional args on the stack to accomplish 2570 // the actual requested call. On 64bit call_VM only can use register args 2571 // so the only extra space is the return address that call_VM created. 2572 // This hopefully explains the calculations here. 2573 2574 #ifdef _LP64 2575 // We've pushed one address, correct last_Java_sp 2576 lea(rax, Address(rsp, wordSize)); 2577 #else 2578 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2579 #endif // LP64 2580 2581 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2582 2583 } 2584 2585 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 2586 void MacroAssembler::call_VM_leaf0(address entry_point) { 2587 MacroAssembler::call_VM_leaf_base(entry_point, 0); 2588 } 2589 2590 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2591 call_VM_leaf_base(entry_point, number_of_arguments); 2592 } 2593 2594 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2595 pass_arg0(this, arg_0); 2596 call_VM_leaf(entry_point, 1); 2597 } 2598 2599 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2600 2601 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2602 pass_arg1(this, arg_1); 2603 pass_arg0(this, arg_0); 2604 call_VM_leaf(entry_point, 2); 2605 } 2606 2607 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2608 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2609 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2610 pass_arg2(this, arg_2); 2611 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2612 pass_arg1(this, arg_1); 2613 pass_arg0(this, arg_0); 2614 call_VM_leaf(entry_point, 3); 2615 } 2616 2617 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2618 pass_arg0(this, arg_0); 2619 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2620 } 2621 2622 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2623 2624 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2625 pass_arg1(this, arg_1); 2626 pass_arg0(this, arg_0); 2627 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2628 } 2629 2630 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2631 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2632 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2633 pass_arg2(this, arg_2); 2634 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2635 pass_arg1(this, arg_1); 2636 pass_arg0(this, arg_0); 2637 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2638 } 2639 2640 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2641 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2642 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2643 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2644 pass_arg3(this, arg_3); 2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2647 pass_arg2(this, arg_2); 2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2649 pass_arg1(this, arg_1); 2650 pass_arg0(this, arg_0); 2651 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2652 } 2653 2654 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2655 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2656 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2657 verify_oop(oop_result, "broken oop in call_VM_base"); 2658 } 2659 2660 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2661 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2662 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2663 } 2664 2665 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2666 } 2667 2668 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2669 } 2670 2671 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2672 if (reachable(src1)) { 2673 cmpl(as_Address(src1), imm); 2674 } else { 2675 lea(rscratch1, src1); 2676 cmpl(Address(rscratch1, 0), imm); 2677 } 2678 } 2679 2680 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2681 assert(!src2.is_lval(), "use cmpptr"); 2682 if (reachable(src2)) { 2683 cmpl(src1, as_Address(src2)); 2684 } else { 2685 lea(rscratch1, src2); 2686 cmpl(src1, Address(rscratch1, 0)); 2687 } 2688 } 2689 2690 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2691 Assembler::cmpl(src1, imm); 2692 } 2693 2694 void MacroAssembler::cmp32(Register src1, Address src2) { 2695 Assembler::cmpl(src1, src2); 2696 } 2697 2698 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2699 ucomisd(opr1, opr2); 2700 2701 Label L; 2702 if (unordered_is_less) { 2703 movl(dst, -1); 2704 jcc(Assembler::parity, L); 2705 jcc(Assembler::below , L); 2706 movl(dst, 0); 2707 jcc(Assembler::equal , L); 2708 increment(dst); 2709 } else { // unordered is greater 2710 movl(dst, 1); 2711 jcc(Assembler::parity, L); 2712 jcc(Assembler::above , L); 2713 movl(dst, 0); 2714 jcc(Assembler::equal , L); 2715 decrementl(dst); 2716 } 2717 bind(L); 2718 } 2719 2720 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2721 ucomiss(opr1, opr2); 2722 2723 Label L; 2724 if (unordered_is_less) { 2725 movl(dst, -1); 2726 jcc(Assembler::parity, L); 2727 jcc(Assembler::below , L); 2728 movl(dst, 0); 2729 jcc(Assembler::equal , L); 2730 increment(dst); 2731 } else { // unordered is greater 2732 movl(dst, 1); 2733 jcc(Assembler::parity, L); 2734 jcc(Assembler::above , L); 2735 movl(dst, 0); 2736 jcc(Assembler::equal , L); 2737 decrementl(dst); 2738 } 2739 bind(L); 2740 } 2741 2742 2743 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2744 if (reachable(src1)) { 2745 cmpb(as_Address(src1), imm); 2746 } else { 2747 lea(rscratch1, src1); 2748 cmpb(Address(rscratch1, 0), imm); 2749 } 2750 } 2751 2752 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2753 #ifdef _LP64 2754 if (src2.is_lval()) { 2755 movptr(rscratch1, src2); 2756 Assembler::cmpq(src1, rscratch1); 2757 } else if (reachable(src2)) { 2758 cmpq(src1, as_Address(src2)); 2759 } else { 2760 lea(rscratch1, src2); 2761 Assembler::cmpq(src1, Address(rscratch1, 0)); 2762 } 2763 #else 2764 if (src2.is_lval()) { 2765 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2766 } else { 2767 cmpl(src1, as_Address(src2)); 2768 } 2769 #endif // _LP64 2770 } 2771 2772 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2773 assert(src2.is_lval(), "not a mem-mem compare"); 2774 #ifdef _LP64 2775 // moves src2's literal address 2776 movptr(rscratch1, src2); 2777 Assembler::cmpq(src1, rscratch1); 2778 #else 2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2780 #endif // _LP64 2781 } 2782 2783 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2784 if (reachable(adr)) { 2785 if (os::is_MP()) 2786 lock(); 2787 cmpxchgptr(reg, as_Address(adr)); 2788 } else { 2789 lea(rscratch1, adr); 2790 if (os::is_MP()) 2791 lock(); 2792 cmpxchgptr(reg, Address(rscratch1, 0)); 2793 } 2794 } 2795 2796 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2797 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2798 } 2799 2800 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2801 if (reachable(src)) { 2802 Assembler::comisd(dst, as_Address(src)); 2803 } else { 2804 lea(rscratch1, src); 2805 Assembler::comisd(dst, Address(rscratch1, 0)); 2806 } 2807 } 2808 2809 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2810 if (reachable(src)) { 2811 Assembler::comiss(dst, as_Address(src)); 2812 } else { 2813 lea(rscratch1, src); 2814 Assembler::comiss(dst, Address(rscratch1, 0)); 2815 } 2816 } 2817 2818 2819 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2820 Condition negated_cond = negate_condition(cond); 2821 Label L; 2822 jcc(negated_cond, L); 2823 pushf(); // Preserve flags 2824 atomic_incl(counter_addr); 2825 popf(); 2826 bind(L); 2827 } 2828 2829 int MacroAssembler::corrected_idivl(Register reg) { 2830 // Full implementation of Java idiv and irem; checks for 2831 // special case as described in JVM spec., p.243 & p.271. 2832 // The function returns the (pc) offset of the idivl 2833 // instruction - may be needed for implicit exceptions. 2834 // 2835 // normal case special case 2836 // 2837 // input : rax,: dividend min_int 2838 // reg: divisor (may not be rax,/rdx) -1 2839 // 2840 // output: rax,: quotient (= rax, idiv reg) min_int 2841 // rdx: remainder (= rax, irem reg) 0 2842 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2843 const int min_int = 0x80000000; 2844 Label normal_case, special_case; 2845 2846 // check for special case 2847 cmpl(rax, min_int); 2848 jcc(Assembler::notEqual, normal_case); 2849 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2850 cmpl(reg, -1); 2851 jcc(Assembler::equal, special_case); 2852 2853 // handle normal case 2854 bind(normal_case); 2855 cdql(); 2856 int idivl_offset = offset(); 2857 idivl(reg); 2858 2859 // normal and special case exit 2860 bind(special_case); 2861 2862 return idivl_offset; 2863 } 2864 2865 2866 2867 void MacroAssembler::decrementl(Register reg, int value) { 2868 if (value == min_jint) {subl(reg, value) ; return; } 2869 if (value < 0) { incrementl(reg, -value); return; } 2870 if (value == 0) { ; return; } 2871 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2872 /* else */ { subl(reg, value) ; return; } 2873 } 2874 2875 void MacroAssembler::decrementl(Address dst, int value) { 2876 if (value == min_jint) {subl(dst, value) ; return; } 2877 if (value < 0) { incrementl(dst, -value); return; } 2878 if (value == 0) { ; return; } 2879 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2880 /* else */ { subl(dst, value) ; return; } 2881 } 2882 2883 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2884 assert (shift_value > 0, "illegal shift value"); 2885 Label _is_positive; 2886 testl (reg, reg); 2887 jcc (Assembler::positive, _is_positive); 2888 int offset = (1 << shift_value) - 1 ; 2889 2890 if (offset == 1) { 2891 incrementl(reg); 2892 } else { 2893 addl(reg, offset); 2894 } 2895 2896 bind (_is_positive); 2897 sarl(reg, shift_value); 2898 } 2899 2900 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2901 if (reachable(src)) { 2902 Assembler::divsd(dst, as_Address(src)); 2903 } else { 2904 lea(rscratch1, src); 2905 Assembler::divsd(dst, Address(rscratch1, 0)); 2906 } 2907 } 2908 2909 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2910 if (reachable(src)) { 2911 Assembler::divss(dst, as_Address(src)); 2912 } else { 2913 lea(rscratch1, src); 2914 Assembler::divss(dst, Address(rscratch1, 0)); 2915 } 2916 } 2917 2918 // !defined(COMPILER2) is because of stupid core builds 2919 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2920 void MacroAssembler::empty_FPU_stack() { 2921 if (VM_Version::supports_mmx()) { 2922 emms(); 2923 } else { 2924 for (int i = 8; i-- > 0; ) ffree(i); 2925 } 2926 } 2927 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2928 2929 2930 // Defines obj, preserves var_size_in_bytes 2931 void MacroAssembler::eden_allocate(Register obj, 2932 Register var_size_in_bytes, 2933 int con_size_in_bytes, 2934 Register t1, 2935 Label& slow_case) { 2936 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2937 assert_different_registers(obj, var_size_in_bytes, t1); 2938 if (!Universe::heap()->supports_inline_contig_alloc()) { 2939 jmp(slow_case); 2940 } else { 2941 Register end = t1; 2942 Label retry; 2943 bind(retry); 2944 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2945 movptr(obj, heap_top); 2946 if (var_size_in_bytes == noreg) { 2947 lea(end, Address(obj, con_size_in_bytes)); 2948 } else { 2949 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2950 } 2951 // if end < obj then we wrapped around => object too long => slow case 2952 cmpptr(end, obj); 2953 jcc(Assembler::below, slow_case); 2954 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2955 jcc(Assembler::above, slow_case); 2956 // Compare obj with the top addr, and if still equal, store the new top addr in 2957 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2958 // it otherwise. Use lock prefix for atomicity on MPs. 2959 locked_cmpxchgptr(end, heap_top); 2960 jcc(Assembler::notEqual, retry); 2961 } 2962 } 2963 2964 void MacroAssembler::enter() { 2965 push(rbp); 2966 mov(rbp, rsp); 2967 } 2968 2969 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2970 void MacroAssembler::fat_nop() { 2971 if (UseAddressNop) { 2972 addr_nop_5(); 2973 } else { 2974 emit_int8(0x26); // es: 2975 emit_int8(0x2e); // cs: 2976 emit_int8(0x64); // fs: 2977 emit_int8(0x65); // gs: 2978 emit_int8((unsigned char)0x90); 2979 } 2980 } 2981 2982 void MacroAssembler::fcmp(Register tmp) { 2983 fcmp(tmp, 1, true, true); 2984 } 2985 2986 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2987 assert(!pop_right || pop_left, "usage error"); 2988 if (VM_Version::supports_cmov()) { 2989 assert(tmp == noreg, "unneeded temp"); 2990 if (pop_left) { 2991 fucomip(index); 2992 } else { 2993 fucomi(index); 2994 } 2995 if (pop_right) { 2996 fpop(); 2997 } 2998 } else { 2999 assert(tmp != noreg, "need temp"); 3000 if (pop_left) { 3001 if (pop_right) { 3002 fcompp(); 3003 } else { 3004 fcomp(index); 3005 } 3006 } else { 3007 fcom(index); 3008 } 3009 // convert FPU condition into eflags condition via rax, 3010 save_rax(tmp); 3011 fwait(); fnstsw_ax(); 3012 sahf(); 3013 restore_rax(tmp); 3014 } 3015 // condition codes set as follows: 3016 // 3017 // CF (corresponds to C0) if x < y 3018 // PF (corresponds to C2) if unordered 3019 // ZF (corresponds to C3) if x = y 3020 } 3021 3022 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 3023 fcmp2int(dst, unordered_is_less, 1, true, true); 3024 } 3025 3026 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3027 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3028 Label L; 3029 if (unordered_is_less) { 3030 movl(dst, -1); 3031 jcc(Assembler::parity, L); 3032 jcc(Assembler::below , L); 3033 movl(dst, 0); 3034 jcc(Assembler::equal , L); 3035 increment(dst); 3036 } else { // unordered is greater 3037 movl(dst, 1); 3038 jcc(Assembler::parity, L); 3039 jcc(Assembler::above , L); 3040 movl(dst, 0); 3041 jcc(Assembler::equal , L); 3042 decrementl(dst); 3043 } 3044 bind(L); 3045 } 3046 3047 void MacroAssembler::fld_d(AddressLiteral src) { 3048 fld_d(as_Address(src)); 3049 } 3050 3051 void MacroAssembler::fld_s(AddressLiteral src) { 3052 fld_s(as_Address(src)); 3053 } 3054 3055 void MacroAssembler::fld_x(AddressLiteral src) { 3056 Assembler::fld_x(as_Address(src)); 3057 } 3058 3059 void MacroAssembler::fldcw(AddressLiteral src) { 3060 Assembler::fldcw(as_Address(src)); 3061 } 3062 3063 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3064 if (reachable(src)) { 3065 Assembler::mulpd(dst, as_Address(src)); 3066 } else { 3067 lea(rscratch1, src); 3068 Assembler::mulpd(dst, Address(rscratch1, 0)); 3069 } 3070 } 3071 3072 void MacroAssembler::increase_precision() { 3073 subptr(rsp, BytesPerWord); 3074 fnstcw(Address(rsp, 0)); 3075 movl(rax, Address(rsp, 0)); 3076 orl(rax, 0x300); 3077 push(rax); 3078 fldcw(Address(rsp, 0)); 3079 pop(rax); 3080 } 3081 3082 void MacroAssembler::restore_precision() { 3083 fldcw(Address(rsp, 0)); 3084 addptr(rsp, BytesPerWord); 3085 } 3086 3087 void MacroAssembler::fpop() { 3088 ffree(); 3089 fincstp(); 3090 } 3091 3092 void MacroAssembler::load_float(Address src) { 3093 if (UseSSE >= 1) { 3094 movflt(xmm0, src); 3095 } else { 3096 LP64_ONLY(ShouldNotReachHere()); 3097 NOT_LP64(fld_s(src)); 3098 } 3099 } 3100 3101 void MacroAssembler::store_float(Address dst) { 3102 if (UseSSE >= 1) { 3103 movflt(dst, xmm0); 3104 } else { 3105 LP64_ONLY(ShouldNotReachHere()); 3106 NOT_LP64(fstp_s(dst)); 3107 } 3108 } 3109 3110 void MacroAssembler::load_double(Address src) { 3111 if (UseSSE >= 2) { 3112 movdbl(xmm0, src); 3113 } else { 3114 LP64_ONLY(ShouldNotReachHere()); 3115 NOT_LP64(fld_d(src)); 3116 } 3117 } 3118 3119 void MacroAssembler::store_double(Address dst) { 3120 if (UseSSE >= 2) { 3121 movdbl(dst, xmm0); 3122 } else { 3123 LP64_ONLY(ShouldNotReachHere()); 3124 NOT_LP64(fstp_d(dst)); 3125 } 3126 } 3127 3128 void MacroAssembler::fremr(Register tmp) { 3129 save_rax(tmp); 3130 { Label L; 3131 bind(L); 3132 fprem(); 3133 fwait(); fnstsw_ax(); 3134 #ifdef _LP64 3135 testl(rax, 0x400); 3136 jcc(Assembler::notEqual, L); 3137 #else 3138 sahf(); 3139 jcc(Assembler::parity, L); 3140 #endif // _LP64 3141 } 3142 restore_rax(tmp); 3143 // Result is in ST0. 3144 // Note: fxch & fpop to get rid of ST1 3145 // (otherwise FPU stack could overflow eventually) 3146 fxch(1); 3147 fpop(); 3148 } 3149 3150 // dst = c = a * b + c 3151 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3152 Assembler::vfmadd231sd(c, a, b); 3153 if (dst != c) { 3154 movdbl(dst, c); 3155 } 3156 } 3157 3158 // dst = c = a * b + c 3159 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 3160 Assembler::vfmadd231ss(c, a, b); 3161 if (dst != c) { 3162 movflt(dst, c); 3163 } 3164 } 3165 3166 3167 3168 3169 void MacroAssembler::incrementl(AddressLiteral dst) { 3170 if (reachable(dst)) { 3171 incrementl(as_Address(dst)); 3172 } else { 3173 lea(rscratch1, dst); 3174 incrementl(Address(rscratch1, 0)); 3175 } 3176 } 3177 3178 void MacroAssembler::incrementl(ArrayAddress dst) { 3179 incrementl(as_Address(dst)); 3180 } 3181 3182 void MacroAssembler::incrementl(Register reg, int value) { 3183 if (value == min_jint) {addl(reg, value) ; return; } 3184 if (value < 0) { decrementl(reg, -value); return; } 3185 if (value == 0) { ; return; } 3186 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3187 /* else */ { addl(reg, value) ; return; } 3188 } 3189 3190 void MacroAssembler::incrementl(Address dst, int value) { 3191 if (value == min_jint) {addl(dst, value) ; return; } 3192 if (value < 0) { decrementl(dst, -value); return; } 3193 if (value == 0) { ; return; } 3194 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3195 /* else */ { addl(dst, value) ; return; } 3196 } 3197 3198 void MacroAssembler::jump(AddressLiteral dst) { 3199 if (reachable(dst)) { 3200 jmp_literal(dst.target(), dst.rspec()); 3201 } else { 3202 lea(rscratch1, dst); 3203 jmp(rscratch1); 3204 } 3205 } 3206 3207 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3208 if (reachable(dst)) { 3209 InstructionMark im(this); 3210 relocate(dst.reloc()); 3211 const int short_size = 2; 3212 const int long_size = 6; 3213 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3214 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3215 // 0111 tttn #8-bit disp 3216 emit_int8(0x70 | cc); 3217 emit_int8((offs - short_size) & 0xFF); 3218 } else { 3219 // 0000 1111 1000 tttn #32-bit disp 3220 emit_int8(0x0F); 3221 emit_int8((unsigned char)(0x80 | cc)); 3222 emit_int32(offs - long_size); 3223 } 3224 } else { 3225 #ifdef ASSERT 3226 warning("reversing conditional branch"); 3227 #endif /* ASSERT */ 3228 Label skip; 3229 jccb(reverse[cc], skip); 3230 lea(rscratch1, dst); 3231 Assembler::jmp(rscratch1); 3232 bind(skip); 3233 } 3234 } 3235 3236 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3237 if (reachable(src)) { 3238 Assembler::ldmxcsr(as_Address(src)); 3239 } else { 3240 lea(rscratch1, src); 3241 Assembler::ldmxcsr(Address(rscratch1, 0)); 3242 } 3243 } 3244 3245 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3246 int off; 3247 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3248 off = offset(); 3249 movsbl(dst, src); // movsxb 3250 } else { 3251 off = load_unsigned_byte(dst, src); 3252 shll(dst, 24); 3253 sarl(dst, 24); 3254 } 3255 return off; 3256 } 3257 3258 // Note: load_signed_short used to be called load_signed_word. 3259 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3260 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3261 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3262 int MacroAssembler::load_signed_short(Register dst, Address src) { 3263 int off; 3264 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3265 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3266 // version but this is what 64bit has always done. This seems to imply 3267 // that users are only using 32bits worth. 3268 off = offset(); 3269 movswl(dst, src); // movsxw 3270 } else { 3271 off = load_unsigned_short(dst, src); 3272 shll(dst, 16); 3273 sarl(dst, 16); 3274 } 3275 return off; 3276 } 3277 3278 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3279 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3280 // and "3.9 Partial Register Penalties", p. 22). 3281 int off; 3282 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3283 off = offset(); 3284 movzbl(dst, src); // movzxb 3285 } else { 3286 xorl(dst, dst); 3287 off = offset(); 3288 movb(dst, src); 3289 } 3290 return off; 3291 } 3292 3293 // Note: load_unsigned_short used to be called load_unsigned_word. 3294 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3295 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3296 // and "3.9 Partial Register Penalties", p. 22). 3297 int off; 3298 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3299 off = offset(); 3300 movzwl(dst, src); // movzxw 3301 } else { 3302 xorl(dst, dst); 3303 off = offset(); 3304 movw(dst, src); 3305 } 3306 return off; 3307 } 3308 3309 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3310 switch (size_in_bytes) { 3311 #ifndef _LP64 3312 case 8: 3313 assert(dst2 != noreg, "second dest register required"); 3314 movl(dst, src); 3315 movl(dst2, src.plus_disp(BytesPerInt)); 3316 break; 3317 #else 3318 case 8: movq(dst, src); break; 3319 #endif 3320 case 4: movl(dst, src); break; 3321 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3322 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3323 default: ShouldNotReachHere(); 3324 } 3325 } 3326 3327 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3328 switch (size_in_bytes) { 3329 #ifndef _LP64 3330 case 8: 3331 assert(src2 != noreg, "second source register required"); 3332 movl(dst, src); 3333 movl(dst.plus_disp(BytesPerInt), src2); 3334 break; 3335 #else 3336 case 8: movq(dst, src); break; 3337 #endif 3338 case 4: movl(dst, src); break; 3339 case 2: movw(dst, src); break; 3340 case 1: movb(dst, src); break; 3341 default: ShouldNotReachHere(); 3342 } 3343 } 3344 3345 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3346 if (reachable(dst)) { 3347 movl(as_Address(dst), src); 3348 } else { 3349 lea(rscratch1, dst); 3350 movl(Address(rscratch1, 0), src); 3351 } 3352 } 3353 3354 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3355 if (reachable(src)) { 3356 movl(dst, as_Address(src)); 3357 } else { 3358 lea(rscratch1, src); 3359 movl(dst, Address(rscratch1, 0)); 3360 } 3361 } 3362 3363 // C++ bool manipulation 3364 3365 void MacroAssembler::movbool(Register dst, Address src) { 3366 if(sizeof(bool) == 1) 3367 movb(dst, src); 3368 else if(sizeof(bool) == 2) 3369 movw(dst, src); 3370 else if(sizeof(bool) == 4) 3371 movl(dst, src); 3372 else 3373 // unsupported 3374 ShouldNotReachHere(); 3375 } 3376 3377 void MacroAssembler::movbool(Address dst, bool boolconst) { 3378 if(sizeof(bool) == 1) 3379 movb(dst, (int) boolconst); 3380 else if(sizeof(bool) == 2) 3381 movw(dst, (int) boolconst); 3382 else if(sizeof(bool) == 4) 3383 movl(dst, (int) boolconst); 3384 else 3385 // unsupported 3386 ShouldNotReachHere(); 3387 } 3388 3389 void MacroAssembler::movbool(Address dst, Register src) { 3390 if(sizeof(bool) == 1) 3391 movb(dst, src); 3392 else if(sizeof(bool) == 2) 3393 movw(dst, src); 3394 else if(sizeof(bool) == 4) 3395 movl(dst, src); 3396 else 3397 // unsupported 3398 ShouldNotReachHere(); 3399 } 3400 3401 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3402 movb(as_Address(dst), src); 3403 } 3404 3405 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3406 if (reachable(src)) { 3407 movdl(dst, as_Address(src)); 3408 } else { 3409 lea(rscratch1, src); 3410 movdl(dst, Address(rscratch1, 0)); 3411 } 3412 } 3413 3414 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3415 if (reachable(src)) { 3416 movq(dst, as_Address(src)); 3417 } else { 3418 lea(rscratch1, src); 3419 movq(dst, Address(rscratch1, 0)); 3420 } 3421 } 3422 3423 void MacroAssembler::setvectmask(Register dst, Register src) { 3424 Assembler::movl(dst, 1); 3425 Assembler::shlxl(dst, dst, src); 3426 Assembler::decl(dst); 3427 Assembler::kmovdl(k1, dst); 3428 Assembler::movl(dst, src); 3429 } 3430 3431 void MacroAssembler::restorevectmask() { 3432 Assembler::knotwl(k1, k0); 3433 } 3434 3435 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3436 if (reachable(src)) { 3437 if (UseXmmLoadAndClearUpper) { 3438 movsd (dst, as_Address(src)); 3439 } else { 3440 movlpd(dst, as_Address(src)); 3441 } 3442 } else { 3443 lea(rscratch1, src); 3444 if (UseXmmLoadAndClearUpper) { 3445 movsd (dst, Address(rscratch1, 0)); 3446 } else { 3447 movlpd(dst, Address(rscratch1, 0)); 3448 } 3449 } 3450 } 3451 3452 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3453 if (reachable(src)) { 3454 movss(dst, as_Address(src)); 3455 } else { 3456 lea(rscratch1, src); 3457 movss(dst, Address(rscratch1, 0)); 3458 } 3459 } 3460 3461 void MacroAssembler::movptr(Register dst, Register src) { 3462 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3463 } 3464 3465 void MacroAssembler::movptr(Register dst, Address src) { 3466 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3467 } 3468 3469 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3470 void MacroAssembler::movptr(Register dst, intptr_t src) { 3471 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3472 } 3473 3474 void MacroAssembler::movptr(Address dst, Register src) { 3475 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3476 } 3477 3478 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 3479 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3480 Assembler::vextractf32x4(dst, src, 0); 3481 } else { 3482 Assembler::movdqu(dst, src); 3483 } 3484 } 3485 3486 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 3487 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3488 Assembler::vinsertf32x4(dst, dst, src, 0); 3489 } else { 3490 Assembler::movdqu(dst, src); 3491 } 3492 } 3493 3494 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 3495 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3496 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3497 } else { 3498 Assembler::movdqu(dst, src); 3499 } 3500 } 3501 3502 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) { 3503 if (reachable(src)) { 3504 movdqu(dst, as_Address(src)); 3505 } else { 3506 lea(scratchReg, src); 3507 movdqu(dst, Address(scratchReg, 0)); 3508 } 3509 } 3510 3511 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 3512 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3513 vextractf64x4_low(dst, src); 3514 } else { 3515 Assembler::vmovdqu(dst, src); 3516 } 3517 } 3518 3519 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 3520 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3521 vinsertf64x4_low(dst, src); 3522 } else { 3523 Assembler::vmovdqu(dst, src); 3524 } 3525 } 3526 3527 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 3528 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3529 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3530 } 3531 else { 3532 Assembler::vmovdqu(dst, src); 3533 } 3534 } 3535 3536 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { 3537 if (reachable(src)) { 3538 vmovdqu(dst, as_Address(src)); 3539 } 3540 else { 3541 lea(rscratch1, src); 3542 vmovdqu(dst, Address(rscratch1, 0)); 3543 } 3544 } 3545 3546 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3547 if (reachable(src)) { 3548 Assembler::movdqa(dst, as_Address(src)); 3549 } else { 3550 lea(rscratch1, src); 3551 Assembler::movdqa(dst, Address(rscratch1, 0)); 3552 } 3553 } 3554 3555 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3556 if (reachable(src)) { 3557 Assembler::movsd(dst, as_Address(src)); 3558 } else { 3559 lea(rscratch1, src); 3560 Assembler::movsd(dst, Address(rscratch1, 0)); 3561 } 3562 } 3563 3564 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3565 if (reachable(src)) { 3566 Assembler::movss(dst, as_Address(src)); 3567 } else { 3568 lea(rscratch1, src); 3569 Assembler::movss(dst, Address(rscratch1, 0)); 3570 } 3571 } 3572 3573 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3574 if (reachable(src)) { 3575 Assembler::mulsd(dst, as_Address(src)); 3576 } else { 3577 lea(rscratch1, src); 3578 Assembler::mulsd(dst, Address(rscratch1, 0)); 3579 } 3580 } 3581 3582 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3583 if (reachable(src)) { 3584 Assembler::mulss(dst, as_Address(src)); 3585 } else { 3586 lea(rscratch1, src); 3587 Assembler::mulss(dst, Address(rscratch1, 0)); 3588 } 3589 } 3590 3591 void MacroAssembler::null_check(Register reg, int offset) { 3592 if (needs_explicit_null_check(offset)) { 3593 // provoke OS NULL exception if reg = NULL by 3594 // accessing M[reg] w/o changing any (non-CC) registers 3595 // NOTE: cmpl is plenty here to provoke a segv 3596 cmpptr(rax, Address(reg, 0)); 3597 // Note: should probably use testl(rax, Address(reg, 0)); 3598 // may be shorter code (however, this version of 3599 // testl needs to be implemented first) 3600 } else { 3601 // nothing to do, (later) access of M[reg + offset] 3602 // will provoke OS NULL exception if reg = NULL 3603 } 3604 } 3605 3606 void MacroAssembler::os_breakpoint() { 3607 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3608 // (e.g., MSVC can't call ps() otherwise) 3609 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3610 } 3611 3612 #ifdef _LP64 3613 #define XSTATE_BV 0x200 3614 #endif 3615 3616 void MacroAssembler::pop_CPU_state() { 3617 pop_FPU_state(); 3618 pop_IU_state(); 3619 } 3620 3621 void MacroAssembler::pop_FPU_state() { 3622 #ifndef _LP64 3623 frstor(Address(rsp, 0)); 3624 #else 3625 fxrstor(Address(rsp, 0)); 3626 #endif 3627 addptr(rsp, FPUStateSizeInWords * wordSize); 3628 } 3629 3630 void MacroAssembler::pop_IU_state() { 3631 popa(); 3632 LP64_ONLY(addq(rsp, 8)); 3633 popf(); 3634 } 3635 3636 // Save Integer and Float state 3637 // Warning: Stack must be 16 byte aligned (64bit) 3638 void MacroAssembler::push_CPU_state() { 3639 push_IU_state(); 3640 push_FPU_state(); 3641 } 3642 3643 void MacroAssembler::push_FPU_state() { 3644 subptr(rsp, FPUStateSizeInWords * wordSize); 3645 #ifndef _LP64 3646 fnsave(Address(rsp, 0)); 3647 fwait(); 3648 #else 3649 fxsave(Address(rsp, 0)); 3650 #endif // LP64 3651 } 3652 3653 void MacroAssembler::push_IU_state() { 3654 // Push flags first because pusha kills them 3655 pushf(); 3656 // Make sure rsp stays 16-byte aligned 3657 LP64_ONLY(subq(rsp, 8)); 3658 pusha(); 3659 } 3660 3661 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 3662 if (!java_thread->is_valid()) { 3663 java_thread = rdi; 3664 get_thread(java_thread); 3665 } 3666 // we must set sp to zero to clear frame 3667 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3668 if (clear_fp) { 3669 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3670 } 3671 3672 // Always clear the pc because it could have been set by make_walkable() 3673 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3674 3675 } 3676 3677 void MacroAssembler::restore_rax(Register tmp) { 3678 if (tmp == noreg) pop(rax); 3679 else if (tmp != rax) mov(rax, tmp); 3680 } 3681 3682 void MacroAssembler::round_to(Register reg, int modulus) { 3683 addptr(reg, modulus - 1); 3684 andptr(reg, -modulus); 3685 } 3686 3687 void MacroAssembler::save_rax(Register tmp) { 3688 if (tmp == noreg) push(rax); 3689 else if (tmp != rax) mov(tmp, rax); 3690 } 3691 3692 // Write serialization page so VM thread can do a pseudo remote membar. 3693 // We use the current thread pointer to calculate a thread specific 3694 // offset to write to within the page. This minimizes bus traffic 3695 // due to cache line collision. 3696 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3697 movl(tmp, thread); 3698 shrl(tmp, os::get_serialize_page_shift_count()); 3699 andl(tmp, (os::vm_page_size() - sizeof(int))); 3700 3701 Address index(noreg, tmp, Address::times_1); 3702 ExternalAddress page(os::get_memory_serialize_page()); 3703 3704 // Size of store must match masking code above 3705 movl(as_Address(ArrayAddress(page, index)), tmp); 3706 } 3707 3708 // Calls to C land 3709 // 3710 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3711 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3712 // has to be reset to 0. This is required to allow proper stack traversal. 3713 void MacroAssembler::set_last_Java_frame(Register java_thread, 3714 Register last_java_sp, 3715 Register last_java_fp, 3716 address last_java_pc) { 3717 // determine java_thread register 3718 if (!java_thread->is_valid()) { 3719 java_thread = rdi; 3720 get_thread(java_thread); 3721 } 3722 // determine last_java_sp register 3723 if (!last_java_sp->is_valid()) { 3724 last_java_sp = rsp; 3725 } 3726 3727 // last_java_fp is optional 3728 3729 if (last_java_fp->is_valid()) { 3730 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3731 } 3732 3733 // last_java_pc is optional 3734 3735 if (last_java_pc != NULL) { 3736 lea(Address(java_thread, 3737 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3738 InternalAddress(last_java_pc)); 3739 3740 } 3741 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3742 } 3743 3744 void MacroAssembler::shlptr(Register dst, int imm8) { 3745 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3746 } 3747 3748 void MacroAssembler::shrptr(Register dst, int imm8) { 3749 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3750 } 3751 3752 void MacroAssembler::sign_extend_byte(Register reg) { 3753 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3754 movsbl(reg, reg); // movsxb 3755 } else { 3756 shll(reg, 24); 3757 sarl(reg, 24); 3758 } 3759 } 3760 3761 void MacroAssembler::sign_extend_short(Register reg) { 3762 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3763 movswl(reg, reg); // movsxw 3764 } else { 3765 shll(reg, 16); 3766 sarl(reg, 16); 3767 } 3768 } 3769 3770 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3771 assert(reachable(src), "Address should be reachable"); 3772 testl(dst, as_Address(src)); 3773 } 3774 3775 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3776 int dst_enc = dst->encoding(); 3777 int src_enc = src->encoding(); 3778 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3779 Assembler::pcmpeqb(dst, src); 3780 } else if ((dst_enc < 16) && (src_enc < 16)) { 3781 Assembler::pcmpeqb(dst, src); 3782 } else if (src_enc < 16) { 3783 subptr(rsp, 64); 3784 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3785 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3786 Assembler::pcmpeqb(xmm0, src); 3787 movdqu(dst, xmm0); 3788 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3789 addptr(rsp, 64); 3790 } else if (dst_enc < 16) { 3791 subptr(rsp, 64); 3792 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3793 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3794 Assembler::pcmpeqb(dst, xmm0); 3795 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3796 addptr(rsp, 64); 3797 } else { 3798 subptr(rsp, 64); 3799 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3800 subptr(rsp, 64); 3801 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3802 movdqu(xmm0, src); 3803 movdqu(xmm1, dst); 3804 Assembler::pcmpeqb(xmm1, xmm0); 3805 movdqu(dst, xmm1); 3806 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3807 addptr(rsp, 64); 3808 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3809 addptr(rsp, 64); 3810 } 3811 } 3812 3813 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3814 int dst_enc = dst->encoding(); 3815 int src_enc = src->encoding(); 3816 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3817 Assembler::pcmpeqw(dst, src); 3818 } else if ((dst_enc < 16) && (src_enc < 16)) { 3819 Assembler::pcmpeqw(dst, src); 3820 } else if (src_enc < 16) { 3821 subptr(rsp, 64); 3822 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3823 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3824 Assembler::pcmpeqw(xmm0, src); 3825 movdqu(dst, xmm0); 3826 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3827 addptr(rsp, 64); 3828 } else if (dst_enc < 16) { 3829 subptr(rsp, 64); 3830 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3831 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3832 Assembler::pcmpeqw(dst, xmm0); 3833 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3834 addptr(rsp, 64); 3835 } else { 3836 subptr(rsp, 64); 3837 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3838 subptr(rsp, 64); 3839 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3840 movdqu(xmm0, src); 3841 movdqu(xmm1, dst); 3842 Assembler::pcmpeqw(xmm1, xmm0); 3843 movdqu(dst, xmm1); 3844 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3845 addptr(rsp, 64); 3846 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3847 addptr(rsp, 64); 3848 } 3849 } 3850 3851 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3852 int dst_enc = dst->encoding(); 3853 if (dst_enc < 16) { 3854 Assembler::pcmpestri(dst, src, imm8); 3855 } else { 3856 subptr(rsp, 64); 3857 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3858 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3859 Assembler::pcmpestri(xmm0, src, imm8); 3860 movdqu(dst, xmm0); 3861 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3862 addptr(rsp, 64); 3863 } 3864 } 3865 3866 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3867 int dst_enc = dst->encoding(); 3868 int src_enc = src->encoding(); 3869 if ((dst_enc < 16) && (src_enc < 16)) { 3870 Assembler::pcmpestri(dst, src, imm8); 3871 } else if (src_enc < 16) { 3872 subptr(rsp, 64); 3873 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3874 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3875 Assembler::pcmpestri(xmm0, src, imm8); 3876 movdqu(dst, xmm0); 3877 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3878 addptr(rsp, 64); 3879 } else if (dst_enc < 16) { 3880 subptr(rsp, 64); 3881 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3882 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3883 Assembler::pcmpestri(dst, xmm0, imm8); 3884 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3885 addptr(rsp, 64); 3886 } else { 3887 subptr(rsp, 64); 3888 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3889 subptr(rsp, 64); 3890 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3891 movdqu(xmm0, src); 3892 movdqu(xmm1, dst); 3893 Assembler::pcmpestri(xmm1, xmm0, imm8); 3894 movdqu(dst, xmm1); 3895 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3896 addptr(rsp, 64); 3897 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3898 addptr(rsp, 64); 3899 } 3900 } 3901 3902 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3903 int dst_enc = dst->encoding(); 3904 int src_enc = src->encoding(); 3905 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3906 Assembler::pmovzxbw(dst, src); 3907 } else if ((dst_enc < 16) && (src_enc < 16)) { 3908 Assembler::pmovzxbw(dst, src); 3909 } else if (src_enc < 16) { 3910 subptr(rsp, 64); 3911 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3912 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3913 Assembler::pmovzxbw(xmm0, src); 3914 movdqu(dst, xmm0); 3915 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3916 addptr(rsp, 64); 3917 } else if (dst_enc < 16) { 3918 subptr(rsp, 64); 3919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3920 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3921 Assembler::pmovzxbw(dst, xmm0); 3922 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3923 addptr(rsp, 64); 3924 } else { 3925 subptr(rsp, 64); 3926 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3927 subptr(rsp, 64); 3928 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3929 movdqu(xmm0, src); 3930 movdqu(xmm1, dst); 3931 Assembler::pmovzxbw(xmm1, xmm0); 3932 movdqu(dst, xmm1); 3933 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3934 addptr(rsp, 64); 3935 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3936 addptr(rsp, 64); 3937 } 3938 } 3939 3940 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 3941 int dst_enc = dst->encoding(); 3942 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3943 Assembler::pmovzxbw(dst, src); 3944 } else if (dst_enc < 16) { 3945 Assembler::pmovzxbw(dst, src); 3946 } else { 3947 subptr(rsp, 64); 3948 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3949 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3950 Assembler::pmovzxbw(xmm0, src); 3951 movdqu(dst, xmm0); 3952 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3953 addptr(rsp, 64); 3954 } 3955 } 3956 3957 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 3958 int src_enc = src->encoding(); 3959 if (src_enc < 16) { 3960 Assembler::pmovmskb(dst, src); 3961 } else { 3962 subptr(rsp, 64); 3963 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3964 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3965 Assembler::pmovmskb(dst, xmm0); 3966 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3967 addptr(rsp, 64); 3968 } 3969 } 3970 3971 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 3972 int dst_enc = dst->encoding(); 3973 int src_enc = src->encoding(); 3974 if ((dst_enc < 16) && (src_enc < 16)) { 3975 Assembler::ptest(dst, src); 3976 } else if (src_enc < 16) { 3977 subptr(rsp, 64); 3978 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3979 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3980 Assembler::ptest(xmm0, src); 3981 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3982 addptr(rsp, 64); 3983 } else if (dst_enc < 16) { 3984 subptr(rsp, 64); 3985 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3986 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3987 Assembler::ptest(dst, xmm0); 3988 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3989 addptr(rsp, 64); 3990 } else { 3991 subptr(rsp, 64); 3992 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3993 subptr(rsp, 64); 3994 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3995 movdqu(xmm0, src); 3996 movdqu(xmm1, dst); 3997 Assembler::ptest(xmm1, xmm0); 3998 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3999 addptr(rsp, 64); 4000 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4001 addptr(rsp, 64); 4002 } 4003 } 4004 4005 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 4006 if (reachable(src)) { 4007 Assembler::sqrtsd(dst, as_Address(src)); 4008 } else { 4009 lea(rscratch1, src); 4010 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 4011 } 4012 } 4013 4014 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 4015 if (reachable(src)) { 4016 Assembler::sqrtss(dst, as_Address(src)); 4017 } else { 4018 lea(rscratch1, src); 4019 Assembler::sqrtss(dst, Address(rscratch1, 0)); 4020 } 4021 } 4022 4023 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 4024 if (reachable(src)) { 4025 Assembler::subsd(dst, as_Address(src)); 4026 } else { 4027 lea(rscratch1, src); 4028 Assembler::subsd(dst, Address(rscratch1, 0)); 4029 } 4030 } 4031 4032 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 4033 if (reachable(src)) { 4034 Assembler::subss(dst, as_Address(src)); 4035 } else { 4036 lea(rscratch1, src); 4037 Assembler::subss(dst, Address(rscratch1, 0)); 4038 } 4039 } 4040 4041 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 4042 if (reachable(src)) { 4043 Assembler::ucomisd(dst, as_Address(src)); 4044 } else { 4045 lea(rscratch1, src); 4046 Assembler::ucomisd(dst, Address(rscratch1, 0)); 4047 } 4048 } 4049 4050 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 4051 if (reachable(src)) { 4052 Assembler::ucomiss(dst, as_Address(src)); 4053 } else { 4054 lea(rscratch1, src); 4055 Assembler::ucomiss(dst, Address(rscratch1, 0)); 4056 } 4057 } 4058 4059 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 4060 // Used in sign-bit flipping with aligned address. 4061 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4062 if (reachable(src)) { 4063 Assembler::xorpd(dst, as_Address(src)); 4064 } else { 4065 lea(rscratch1, src); 4066 Assembler::xorpd(dst, Address(rscratch1, 0)); 4067 } 4068 } 4069 4070 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 4071 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4072 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4073 } 4074 else { 4075 Assembler::xorpd(dst, src); 4076 } 4077 } 4078 4079 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 4080 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4081 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4082 } else { 4083 Assembler::xorps(dst, src); 4084 } 4085 } 4086 4087 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4088 // Used in sign-bit flipping with aligned address. 4089 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4090 if (reachable(src)) { 4091 Assembler::xorps(dst, as_Address(src)); 4092 } else { 4093 lea(rscratch1, src); 4094 Assembler::xorps(dst, Address(rscratch1, 0)); 4095 } 4096 } 4097 4098 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4099 // Used in sign-bit flipping with aligned address. 4100 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4101 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4102 if (reachable(src)) { 4103 Assembler::pshufb(dst, as_Address(src)); 4104 } else { 4105 lea(rscratch1, src); 4106 Assembler::pshufb(dst, Address(rscratch1, 0)); 4107 } 4108 } 4109 4110 // AVX 3-operands instructions 4111 4112 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4113 if (reachable(src)) { 4114 vaddsd(dst, nds, as_Address(src)); 4115 } else { 4116 lea(rscratch1, src); 4117 vaddsd(dst, nds, Address(rscratch1, 0)); 4118 } 4119 } 4120 4121 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4122 if (reachable(src)) { 4123 vaddss(dst, nds, as_Address(src)); 4124 } else { 4125 lea(rscratch1, src); 4126 vaddss(dst, nds, Address(rscratch1, 0)); 4127 } 4128 } 4129 4130 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4131 int dst_enc = dst->encoding(); 4132 int nds_enc = nds->encoding(); 4133 int src_enc = src->encoding(); 4134 if ((dst_enc < 16) && (nds_enc < 16)) { 4135 vandps(dst, nds, negate_field, vector_len); 4136 } else if ((src_enc < 16) && (dst_enc < 16)) { 4137 movss(src, nds); 4138 vandps(dst, src, negate_field, vector_len); 4139 } else if (src_enc < 16) { 4140 movss(src, nds); 4141 vandps(src, src, negate_field, vector_len); 4142 movss(dst, src); 4143 } else if (dst_enc < 16) { 4144 movdqu(src, xmm0); 4145 movss(xmm0, nds); 4146 vandps(dst, xmm0, negate_field, vector_len); 4147 movdqu(xmm0, src); 4148 } else if (nds_enc < 16) { 4149 movdqu(src, xmm0); 4150 vandps(xmm0, nds, negate_field, vector_len); 4151 movss(dst, xmm0); 4152 movdqu(xmm0, src); 4153 } else { 4154 movdqu(src, xmm0); 4155 movss(xmm0, nds); 4156 vandps(xmm0, xmm0, negate_field, vector_len); 4157 movss(dst, xmm0); 4158 movdqu(xmm0, src); 4159 } 4160 } 4161 4162 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4163 int dst_enc = dst->encoding(); 4164 int nds_enc = nds->encoding(); 4165 int src_enc = src->encoding(); 4166 if ((dst_enc < 16) && (nds_enc < 16)) { 4167 vandpd(dst, nds, negate_field, vector_len); 4168 } else if ((src_enc < 16) && (dst_enc < 16)) { 4169 movsd(src, nds); 4170 vandpd(dst, src, negate_field, vector_len); 4171 } else if (src_enc < 16) { 4172 movsd(src, nds); 4173 vandpd(src, src, negate_field, vector_len); 4174 movsd(dst, src); 4175 } else if (dst_enc < 16) { 4176 movdqu(src, xmm0); 4177 movsd(xmm0, nds); 4178 vandpd(dst, xmm0, negate_field, vector_len); 4179 movdqu(xmm0, src); 4180 } else if (nds_enc < 16) { 4181 movdqu(src, xmm0); 4182 vandpd(xmm0, nds, negate_field, vector_len); 4183 movsd(dst, xmm0); 4184 movdqu(xmm0, src); 4185 } else { 4186 movdqu(src, xmm0); 4187 movsd(xmm0, nds); 4188 vandpd(xmm0, xmm0, negate_field, vector_len); 4189 movsd(dst, xmm0); 4190 movdqu(xmm0, src); 4191 } 4192 } 4193 4194 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4195 int dst_enc = dst->encoding(); 4196 int nds_enc = nds->encoding(); 4197 int src_enc = src->encoding(); 4198 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4199 Assembler::vpaddb(dst, nds, src, vector_len); 4200 } else if ((dst_enc < 16) && (src_enc < 16)) { 4201 Assembler::vpaddb(dst, dst, src, vector_len); 4202 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4203 // use nds as scratch for src 4204 evmovdqul(nds, src, Assembler::AVX_512bit); 4205 Assembler::vpaddb(dst, dst, nds, vector_len); 4206 } else if ((src_enc < 16) && (nds_enc < 16)) { 4207 // use nds as scratch for dst 4208 evmovdqul(nds, dst, Assembler::AVX_512bit); 4209 Assembler::vpaddb(nds, nds, src, vector_len); 4210 evmovdqul(dst, nds, Assembler::AVX_512bit); 4211 } else if (dst_enc < 16) { 4212 // use nds as scatch for xmm0 to hold src 4213 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4214 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4215 Assembler::vpaddb(dst, dst, xmm0, vector_len); 4216 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4217 } else { 4218 // worse case scenario, all regs are in the upper bank 4219 subptr(rsp, 64); 4220 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4221 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4222 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4223 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4224 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len); 4225 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4226 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4227 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4228 addptr(rsp, 64); 4229 } 4230 } 4231 4232 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4233 int dst_enc = dst->encoding(); 4234 int nds_enc = nds->encoding(); 4235 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4236 Assembler::vpaddb(dst, nds, src, vector_len); 4237 } else if (dst_enc < 16) { 4238 Assembler::vpaddb(dst, dst, src, vector_len); 4239 } else if (nds_enc < 16) { 4240 // implies dst_enc in upper bank with src as scratch 4241 evmovdqul(nds, dst, Assembler::AVX_512bit); 4242 Assembler::vpaddb(nds, nds, src, vector_len); 4243 evmovdqul(dst, nds, Assembler::AVX_512bit); 4244 } else { 4245 // worse case scenario, all regs in upper bank 4246 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4247 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4248 Assembler::vpaddb(xmm0, xmm0, src, vector_len); 4249 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4250 } 4251 } 4252 4253 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4254 int dst_enc = dst->encoding(); 4255 int nds_enc = nds->encoding(); 4256 int src_enc = src->encoding(); 4257 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4258 Assembler::vpaddw(dst, nds, src, vector_len); 4259 } else if ((dst_enc < 16) && (src_enc < 16)) { 4260 Assembler::vpaddw(dst, dst, src, vector_len); 4261 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4262 // use nds as scratch for src 4263 evmovdqul(nds, src, Assembler::AVX_512bit); 4264 Assembler::vpaddw(dst, dst, nds, vector_len); 4265 } else if ((src_enc < 16) && (nds_enc < 16)) { 4266 // use nds as scratch for dst 4267 evmovdqul(nds, dst, Assembler::AVX_512bit); 4268 Assembler::vpaddw(nds, nds, src, vector_len); 4269 evmovdqul(dst, nds, Assembler::AVX_512bit); 4270 } else if (dst_enc < 16) { 4271 // use nds as scatch for xmm0 to hold src 4272 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4273 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4274 Assembler::vpaddw(dst, dst, xmm0, vector_len); 4275 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4276 } else { 4277 // worse case scenario, all regs are in the upper bank 4278 subptr(rsp, 64); 4279 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4280 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4281 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4282 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4283 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len); 4284 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4285 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4286 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4287 addptr(rsp, 64); 4288 } 4289 } 4290 4291 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4292 int dst_enc = dst->encoding(); 4293 int nds_enc = nds->encoding(); 4294 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4295 Assembler::vpaddw(dst, nds, src, vector_len); 4296 } else if (dst_enc < 16) { 4297 Assembler::vpaddw(dst, dst, src, vector_len); 4298 } else if (nds_enc < 16) { 4299 // implies dst_enc in upper bank with src as scratch 4300 evmovdqul(nds, dst, Assembler::AVX_512bit); 4301 Assembler::vpaddw(nds, nds, src, vector_len); 4302 evmovdqul(dst, nds, Assembler::AVX_512bit); 4303 } else { 4304 // worse case scenario, all regs in upper bank 4305 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4306 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4307 Assembler::vpaddw(xmm0, xmm0, src, vector_len); 4308 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4309 } 4310 } 4311 4312 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4313 if (reachable(src)) { 4314 Assembler::vpand(dst, nds, as_Address(src), vector_len); 4315 } else { 4316 lea(rscratch1, src); 4317 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len); 4318 } 4319 } 4320 4321 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 4322 int dst_enc = dst->encoding(); 4323 int src_enc = src->encoding(); 4324 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4325 Assembler::vpbroadcastw(dst, src); 4326 } else if ((dst_enc < 16) && (src_enc < 16)) { 4327 Assembler::vpbroadcastw(dst, src); 4328 } else if (src_enc < 16) { 4329 subptr(rsp, 64); 4330 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4331 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4332 Assembler::vpbroadcastw(xmm0, src); 4333 movdqu(dst, xmm0); 4334 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4335 addptr(rsp, 64); 4336 } else if (dst_enc < 16) { 4337 subptr(rsp, 64); 4338 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4339 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4340 Assembler::vpbroadcastw(dst, xmm0); 4341 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4342 addptr(rsp, 64); 4343 } else { 4344 subptr(rsp, 64); 4345 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4346 subptr(rsp, 64); 4347 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4348 movdqu(xmm0, src); 4349 movdqu(xmm1, dst); 4350 Assembler::vpbroadcastw(xmm1, xmm0); 4351 movdqu(dst, xmm1); 4352 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4353 addptr(rsp, 64); 4354 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4355 addptr(rsp, 64); 4356 } 4357 } 4358 4359 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4360 int dst_enc = dst->encoding(); 4361 int nds_enc = nds->encoding(); 4362 int src_enc = src->encoding(); 4363 assert(dst_enc == nds_enc, ""); 4364 if ((dst_enc < 16) && (src_enc < 16)) { 4365 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4366 } else if (src_enc < 16) { 4367 subptr(rsp, 64); 4368 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4369 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4370 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len); 4371 movdqu(dst, xmm0); 4372 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4373 addptr(rsp, 64); 4374 } else if (dst_enc < 16) { 4375 subptr(rsp, 64); 4376 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4377 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4378 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len); 4379 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4380 addptr(rsp, 64); 4381 } else { 4382 subptr(rsp, 64); 4383 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4384 subptr(rsp, 64); 4385 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4386 movdqu(xmm0, src); 4387 movdqu(xmm1, dst); 4388 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len); 4389 movdqu(dst, xmm1); 4390 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4391 addptr(rsp, 64); 4392 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4393 addptr(rsp, 64); 4394 } 4395 } 4396 4397 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4398 int dst_enc = dst->encoding(); 4399 int nds_enc = nds->encoding(); 4400 int src_enc = src->encoding(); 4401 assert(dst_enc == nds_enc, ""); 4402 if ((dst_enc < 16) && (src_enc < 16)) { 4403 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4404 } else if (src_enc < 16) { 4405 subptr(rsp, 64); 4406 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4407 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4408 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len); 4409 movdqu(dst, xmm0); 4410 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4411 addptr(rsp, 64); 4412 } else if (dst_enc < 16) { 4413 subptr(rsp, 64); 4414 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4415 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4416 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len); 4417 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4418 addptr(rsp, 64); 4419 } else { 4420 subptr(rsp, 64); 4421 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4422 subptr(rsp, 64); 4423 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4424 movdqu(xmm0, src); 4425 movdqu(xmm1, dst); 4426 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len); 4427 movdqu(dst, xmm1); 4428 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4429 addptr(rsp, 64); 4430 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4431 addptr(rsp, 64); 4432 } 4433 } 4434 4435 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 4436 int dst_enc = dst->encoding(); 4437 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4438 Assembler::vpmovzxbw(dst, src, vector_len); 4439 } else if (dst_enc < 16) { 4440 Assembler::vpmovzxbw(dst, src, vector_len); 4441 } else { 4442 subptr(rsp, 64); 4443 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4444 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4445 Assembler::vpmovzxbw(xmm0, src, vector_len); 4446 movdqu(dst, xmm0); 4447 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4448 addptr(rsp, 64); 4449 } 4450 } 4451 4452 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 4453 int src_enc = src->encoding(); 4454 if (src_enc < 16) { 4455 Assembler::vpmovmskb(dst, src); 4456 } else { 4457 subptr(rsp, 64); 4458 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4459 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4460 Assembler::vpmovmskb(dst, xmm0); 4461 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4462 addptr(rsp, 64); 4463 } 4464 } 4465 4466 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4467 int dst_enc = dst->encoding(); 4468 int nds_enc = nds->encoding(); 4469 int src_enc = src->encoding(); 4470 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4471 Assembler::vpmullw(dst, nds, src, vector_len); 4472 } else if ((dst_enc < 16) && (src_enc < 16)) { 4473 Assembler::vpmullw(dst, dst, src, vector_len); 4474 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4475 // use nds as scratch for src 4476 evmovdqul(nds, src, Assembler::AVX_512bit); 4477 Assembler::vpmullw(dst, dst, nds, vector_len); 4478 } else if ((src_enc < 16) && (nds_enc < 16)) { 4479 // use nds as scratch for dst 4480 evmovdqul(nds, dst, Assembler::AVX_512bit); 4481 Assembler::vpmullw(nds, nds, src, vector_len); 4482 evmovdqul(dst, nds, Assembler::AVX_512bit); 4483 } else if (dst_enc < 16) { 4484 // use nds as scatch for xmm0 to hold src 4485 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4486 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4487 Assembler::vpmullw(dst, dst, xmm0, vector_len); 4488 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4489 } else { 4490 // worse case scenario, all regs are in the upper bank 4491 subptr(rsp, 64); 4492 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4493 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4494 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4495 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4496 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len); 4497 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4498 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4499 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4500 addptr(rsp, 64); 4501 } 4502 } 4503 4504 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4505 int dst_enc = dst->encoding(); 4506 int nds_enc = nds->encoding(); 4507 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4508 Assembler::vpmullw(dst, nds, src, vector_len); 4509 } else if (dst_enc < 16) { 4510 Assembler::vpmullw(dst, dst, src, vector_len); 4511 } else if (nds_enc < 16) { 4512 // implies dst_enc in upper bank with src as scratch 4513 evmovdqul(nds, dst, Assembler::AVX_512bit); 4514 Assembler::vpmullw(nds, nds, src, vector_len); 4515 evmovdqul(dst, nds, Assembler::AVX_512bit); 4516 } else { 4517 // worse case scenario, all regs in upper bank 4518 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4519 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4520 Assembler::vpmullw(xmm0, xmm0, src, vector_len); 4521 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4522 } 4523 } 4524 4525 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4526 int dst_enc = dst->encoding(); 4527 int nds_enc = nds->encoding(); 4528 int src_enc = src->encoding(); 4529 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4530 Assembler::vpsubb(dst, nds, src, vector_len); 4531 } else if ((dst_enc < 16) && (src_enc < 16)) { 4532 Assembler::vpsubb(dst, dst, src, vector_len); 4533 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4534 // use nds as scratch for src 4535 evmovdqul(nds, src, Assembler::AVX_512bit); 4536 Assembler::vpsubb(dst, dst, nds, vector_len); 4537 } else if ((src_enc < 16) && (nds_enc < 16)) { 4538 // use nds as scratch for dst 4539 evmovdqul(nds, dst, Assembler::AVX_512bit); 4540 Assembler::vpsubb(nds, nds, src, vector_len); 4541 evmovdqul(dst, nds, Assembler::AVX_512bit); 4542 } else if (dst_enc < 16) { 4543 // use nds as scatch for xmm0 to hold src 4544 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4545 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4546 Assembler::vpsubb(dst, dst, xmm0, vector_len); 4547 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4548 } else { 4549 // worse case scenario, all regs are in the upper bank 4550 subptr(rsp, 64); 4551 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4552 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4553 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4554 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4555 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len); 4556 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4557 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4558 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4559 addptr(rsp, 64); 4560 } 4561 } 4562 4563 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4564 int dst_enc = dst->encoding(); 4565 int nds_enc = nds->encoding(); 4566 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4567 Assembler::vpsubb(dst, nds, src, vector_len); 4568 } else if (dst_enc < 16) { 4569 Assembler::vpsubb(dst, dst, src, vector_len); 4570 } else if (nds_enc < 16) { 4571 // implies dst_enc in upper bank with src as scratch 4572 evmovdqul(nds, dst, Assembler::AVX_512bit); 4573 Assembler::vpsubb(nds, nds, src, vector_len); 4574 evmovdqul(dst, nds, Assembler::AVX_512bit); 4575 } else { 4576 // worse case scenario, all regs in upper bank 4577 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4578 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4579 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4580 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4581 } 4582 } 4583 4584 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4585 int dst_enc = dst->encoding(); 4586 int nds_enc = nds->encoding(); 4587 int src_enc = src->encoding(); 4588 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4589 Assembler::vpsubw(dst, nds, src, vector_len); 4590 } else if ((dst_enc < 16) && (src_enc < 16)) { 4591 Assembler::vpsubw(dst, dst, src, vector_len); 4592 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4593 // use nds as scratch for src 4594 evmovdqul(nds, src, Assembler::AVX_512bit); 4595 Assembler::vpsubw(dst, dst, nds, vector_len); 4596 } else if ((src_enc < 16) && (nds_enc < 16)) { 4597 // use nds as scratch for dst 4598 evmovdqul(nds, dst, Assembler::AVX_512bit); 4599 Assembler::vpsubw(nds, nds, src, vector_len); 4600 evmovdqul(dst, nds, Assembler::AVX_512bit); 4601 } else if (dst_enc < 16) { 4602 // use nds as scatch for xmm0 to hold src 4603 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4604 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4605 Assembler::vpsubw(dst, dst, xmm0, vector_len); 4606 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4607 } else { 4608 // worse case scenario, all regs are in the upper bank 4609 subptr(rsp, 64); 4610 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4611 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4612 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4613 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4614 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len); 4615 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4616 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4617 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4618 addptr(rsp, 64); 4619 } 4620 } 4621 4622 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4623 int dst_enc = dst->encoding(); 4624 int nds_enc = nds->encoding(); 4625 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4626 Assembler::vpsubw(dst, nds, src, vector_len); 4627 } else if (dst_enc < 16) { 4628 Assembler::vpsubw(dst, dst, src, vector_len); 4629 } else if (nds_enc < 16) { 4630 // implies dst_enc in upper bank with src as scratch 4631 evmovdqul(nds, dst, Assembler::AVX_512bit); 4632 Assembler::vpsubw(nds, nds, src, vector_len); 4633 evmovdqul(dst, nds, Assembler::AVX_512bit); 4634 } else { 4635 // worse case scenario, all regs in upper bank 4636 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4637 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4638 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4639 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4640 } 4641 } 4642 4643 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4644 int dst_enc = dst->encoding(); 4645 int nds_enc = nds->encoding(); 4646 int shift_enc = shift->encoding(); 4647 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4648 Assembler::vpsraw(dst, nds, shift, vector_len); 4649 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4650 Assembler::vpsraw(dst, dst, shift, vector_len); 4651 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4652 // use nds_enc as scratch with shift 4653 evmovdqul(nds, shift, Assembler::AVX_512bit); 4654 Assembler::vpsraw(dst, dst, nds, vector_len); 4655 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4656 // use nds as scratch with dst 4657 evmovdqul(nds, dst, Assembler::AVX_512bit); 4658 Assembler::vpsraw(nds, nds, shift, vector_len); 4659 evmovdqul(dst, nds, Assembler::AVX_512bit); 4660 } else if (dst_enc < 16) { 4661 // use nds to save a copy of xmm0 and hold shift 4662 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4663 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4664 Assembler::vpsraw(dst, dst, xmm0, vector_len); 4665 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4666 } else if (nds_enc < 16) { 4667 // use nds as dest as temps 4668 evmovdqul(nds, dst, Assembler::AVX_512bit); 4669 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4670 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4671 Assembler::vpsraw(nds, nds, xmm0, vector_len); 4672 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4673 evmovdqul(dst, nds, Assembler::AVX_512bit); 4674 } else { 4675 // worse case scenario, all regs are in the upper bank 4676 subptr(rsp, 64); 4677 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4678 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4679 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4680 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4681 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4682 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4683 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4684 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4685 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4686 addptr(rsp, 64); 4687 } 4688 } 4689 4690 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4691 int dst_enc = dst->encoding(); 4692 int nds_enc = nds->encoding(); 4693 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4694 Assembler::vpsraw(dst, nds, shift, vector_len); 4695 } else if (dst_enc < 16) { 4696 Assembler::vpsraw(dst, dst, shift, vector_len); 4697 } else if (nds_enc < 16) { 4698 // use nds as scratch 4699 evmovdqul(nds, dst, Assembler::AVX_512bit); 4700 Assembler::vpsraw(nds, nds, shift, vector_len); 4701 evmovdqul(dst, nds, Assembler::AVX_512bit); 4702 } else { 4703 // use nds as scratch for xmm0 4704 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4705 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4706 Assembler::vpsraw(xmm0, xmm0, shift, vector_len); 4707 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4708 } 4709 } 4710 4711 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4712 int dst_enc = dst->encoding(); 4713 int nds_enc = nds->encoding(); 4714 int shift_enc = shift->encoding(); 4715 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4716 Assembler::vpsrlw(dst, nds, shift, vector_len); 4717 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4718 Assembler::vpsrlw(dst, dst, shift, vector_len); 4719 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4720 // use nds_enc as scratch with shift 4721 evmovdqul(nds, shift, Assembler::AVX_512bit); 4722 Assembler::vpsrlw(dst, dst, nds, vector_len); 4723 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4724 // use nds as scratch with dst 4725 evmovdqul(nds, dst, Assembler::AVX_512bit); 4726 Assembler::vpsrlw(nds, nds, shift, vector_len); 4727 evmovdqul(dst, nds, Assembler::AVX_512bit); 4728 } else if (dst_enc < 16) { 4729 // use nds to save a copy of xmm0 and hold shift 4730 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4731 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4732 Assembler::vpsrlw(dst, dst, xmm0, vector_len); 4733 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4734 } else if (nds_enc < 16) { 4735 // use nds as dest as temps 4736 evmovdqul(nds, dst, Assembler::AVX_512bit); 4737 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4738 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4739 Assembler::vpsrlw(nds, nds, xmm0, vector_len); 4740 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4741 evmovdqul(dst, nds, Assembler::AVX_512bit); 4742 } else { 4743 // worse case scenario, all regs are in the upper bank 4744 subptr(rsp, 64); 4745 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4746 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4747 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4748 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4749 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4750 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4751 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4752 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4753 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4754 addptr(rsp, 64); 4755 } 4756 } 4757 4758 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4759 int dst_enc = dst->encoding(); 4760 int nds_enc = nds->encoding(); 4761 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4762 Assembler::vpsrlw(dst, nds, shift, vector_len); 4763 } else if (dst_enc < 16) { 4764 Assembler::vpsrlw(dst, dst, shift, vector_len); 4765 } else if (nds_enc < 16) { 4766 // use nds as scratch 4767 evmovdqul(nds, dst, Assembler::AVX_512bit); 4768 Assembler::vpsrlw(nds, nds, shift, vector_len); 4769 evmovdqul(dst, nds, Assembler::AVX_512bit); 4770 } else { 4771 // use nds as scratch for xmm0 4772 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4773 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4774 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len); 4775 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4776 } 4777 } 4778 4779 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4780 int dst_enc = dst->encoding(); 4781 int nds_enc = nds->encoding(); 4782 int shift_enc = shift->encoding(); 4783 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4784 Assembler::vpsllw(dst, nds, shift, vector_len); 4785 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4786 Assembler::vpsllw(dst, dst, shift, vector_len); 4787 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4788 // use nds_enc as scratch with shift 4789 evmovdqul(nds, shift, Assembler::AVX_512bit); 4790 Assembler::vpsllw(dst, dst, nds, vector_len); 4791 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4792 // use nds as scratch with dst 4793 evmovdqul(nds, dst, Assembler::AVX_512bit); 4794 Assembler::vpsllw(nds, nds, shift, vector_len); 4795 evmovdqul(dst, nds, Assembler::AVX_512bit); 4796 } else if (dst_enc < 16) { 4797 // use nds to save a copy of xmm0 and hold shift 4798 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4799 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4800 Assembler::vpsllw(dst, dst, xmm0, vector_len); 4801 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4802 } else if (nds_enc < 16) { 4803 // use nds as dest as temps 4804 evmovdqul(nds, dst, Assembler::AVX_512bit); 4805 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4806 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4807 Assembler::vpsllw(nds, nds, xmm0, vector_len); 4808 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4809 evmovdqul(dst, nds, Assembler::AVX_512bit); 4810 } else { 4811 // worse case scenario, all regs are in the upper bank 4812 subptr(rsp, 64); 4813 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4814 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4815 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4816 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4817 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4818 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4819 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4820 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4821 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4822 addptr(rsp, 64); 4823 } 4824 } 4825 4826 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4827 int dst_enc = dst->encoding(); 4828 int nds_enc = nds->encoding(); 4829 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4830 Assembler::vpsllw(dst, nds, shift, vector_len); 4831 } else if (dst_enc < 16) { 4832 Assembler::vpsllw(dst, dst, shift, vector_len); 4833 } else if (nds_enc < 16) { 4834 // use nds as scratch 4835 evmovdqul(nds, dst, Assembler::AVX_512bit); 4836 Assembler::vpsllw(nds, nds, shift, vector_len); 4837 evmovdqul(dst, nds, Assembler::AVX_512bit); 4838 } else { 4839 // use nds as scratch for xmm0 4840 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4841 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4842 Assembler::vpsllw(xmm0, xmm0, shift, vector_len); 4843 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4844 } 4845 } 4846 4847 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 4848 int dst_enc = dst->encoding(); 4849 int src_enc = src->encoding(); 4850 if ((dst_enc < 16) && (src_enc < 16)) { 4851 Assembler::vptest(dst, src); 4852 } else if (src_enc < 16) { 4853 subptr(rsp, 64); 4854 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4855 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4856 Assembler::vptest(xmm0, src); 4857 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4858 addptr(rsp, 64); 4859 } else if (dst_enc < 16) { 4860 subptr(rsp, 64); 4861 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4862 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4863 Assembler::vptest(dst, xmm0); 4864 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4865 addptr(rsp, 64); 4866 } else { 4867 subptr(rsp, 64); 4868 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4869 subptr(rsp, 64); 4870 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4871 movdqu(xmm0, src); 4872 movdqu(xmm1, dst); 4873 Assembler::vptest(xmm1, xmm0); 4874 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4875 addptr(rsp, 64); 4876 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4877 addptr(rsp, 64); 4878 } 4879 } 4880 4881 // This instruction exists within macros, ergo we cannot control its input 4882 // when emitted through those patterns. 4883 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4884 if (VM_Version::supports_avx512nobw()) { 4885 int dst_enc = dst->encoding(); 4886 int src_enc = src->encoding(); 4887 if (dst_enc == src_enc) { 4888 if (dst_enc < 16) { 4889 Assembler::punpcklbw(dst, src); 4890 } else { 4891 subptr(rsp, 64); 4892 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4893 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4894 Assembler::punpcklbw(xmm0, xmm0); 4895 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4896 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4897 addptr(rsp, 64); 4898 } 4899 } else { 4900 if ((src_enc < 16) && (dst_enc < 16)) { 4901 Assembler::punpcklbw(dst, src); 4902 } else if (src_enc < 16) { 4903 subptr(rsp, 64); 4904 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4905 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4906 Assembler::punpcklbw(xmm0, src); 4907 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4908 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4909 addptr(rsp, 64); 4910 } else if (dst_enc < 16) { 4911 subptr(rsp, 64); 4912 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4913 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4914 Assembler::punpcklbw(dst, xmm0); 4915 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4916 addptr(rsp, 64); 4917 } else { 4918 subptr(rsp, 64); 4919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4920 subptr(rsp, 64); 4921 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4922 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4923 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4924 Assembler::punpcklbw(xmm0, xmm1); 4925 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4926 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4927 addptr(rsp, 64); 4928 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4929 addptr(rsp, 64); 4930 } 4931 } 4932 } else { 4933 Assembler::punpcklbw(dst, src); 4934 } 4935 } 4936 4937 // This instruction exists within macros, ergo we cannot control its input 4938 // when emitted through those patterns. 4939 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 4940 if (VM_Version::supports_avx512nobw()) { 4941 int dst_enc = dst->encoding(); 4942 int src_enc = src->encoding(); 4943 if (dst_enc == src_enc) { 4944 if (dst_enc < 16) { 4945 Assembler::pshuflw(dst, src, mode); 4946 } else { 4947 subptr(rsp, 64); 4948 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4949 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4950 Assembler::pshuflw(xmm0, xmm0, mode); 4951 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4952 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4953 addptr(rsp, 64); 4954 } 4955 } else { 4956 if ((src_enc < 16) && (dst_enc < 16)) { 4957 Assembler::pshuflw(dst, src, mode); 4958 } else if (src_enc < 16) { 4959 subptr(rsp, 64); 4960 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4961 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4962 Assembler::pshuflw(xmm0, src, mode); 4963 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4964 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4965 addptr(rsp, 64); 4966 } else if (dst_enc < 16) { 4967 subptr(rsp, 64); 4968 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4969 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4970 Assembler::pshuflw(dst, xmm0, mode); 4971 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4972 addptr(rsp, 64); 4973 } else { 4974 subptr(rsp, 64); 4975 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4976 subptr(rsp, 64); 4977 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4978 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4979 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4980 Assembler::pshuflw(xmm0, xmm1, mode); 4981 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4982 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4983 addptr(rsp, 64); 4984 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4985 addptr(rsp, 64); 4986 } 4987 } 4988 } else { 4989 Assembler::pshuflw(dst, src, mode); 4990 } 4991 } 4992 4993 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4994 if (reachable(src)) { 4995 vandpd(dst, nds, as_Address(src), vector_len); 4996 } else { 4997 lea(rscratch1, src); 4998 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 4999 } 5000 } 5001 5002 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5003 if (reachable(src)) { 5004 vandps(dst, nds, as_Address(src), vector_len); 5005 } else { 5006 lea(rscratch1, src); 5007 vandps(dst, nds, Address(rscratch1, 0), vector_len); 5008 } 5009 } 5010 5011 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5012 if (reachable(src)) { 5013 vdivsd(dst, nds, as_Address(src)); 5014 } else { 5015 lea(rscratch1, src); 5016 vdivsd(dst, nds, Address(rscratch1, 0)); 5017 } 5018 } 5019 5020 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5021 if (reachable(src)) { 5022 vdivss(dst, nds, as_Address(src)); 5023 } else { 5024 lea(rscratch1, src); 5025 vdivss(dst, nds, Address(rscratch1, 0)); 5026 } 5027 } 5028 5029 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5030 if (reachable(src)) { 5031 vmulsd(dst, nds, as_Address(src)); 5032 } else { 5033 lea(rscratch1, src); 5034 vmulsd(dst, nds, Address(rscratch1, 0)); 5035 } 5036 } 5037 5038 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5039 if (reachable(src)) { 5040 vmulss(dst, nds, as_Address(src)); 5041 } else { 5042 lea(rscratch1, src); 5043 vmulss(dst, nds, Address(rscratch1, 0)); 5044 } 5045 } 5046 5047 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5048 if (reachable(src)) { 5049 vsubsd(dst, nds, as_Address(src)); 5050 } else { 5051 lea(rscratch1, src); 5052 vsubsd(dst, nds, Address(rscratch1, 0)); 5053 } 5054 } 5055 5056 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5057 if (reachable(src)) { 5058 vsubss(dst, nds, as_Address(src)); 5059 } else { 5060 lea(rscratch1, src); 5061 vsubss(dst, nds, Address(rscratch1, 0)); 5062 } 5063 } 5064 5065 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5066 int nds_enc = nds->encoding(); 5067 int dst_enc = dst->encoding(); 5068 bool dst_upper_bank = (dst_enc > 15); 5069 bool nds_upper_bank = (nds_enc > 15); 5070 if (VM_Version::supports_avx512novl() && 5071 (nds_upper_bank || dst_upper_bank)) { 5072 if (dst_upper_bank) { 5073 subptr(rsp, 64); 5074 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5075 movflt(xmm0, nds); 5076 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit); 5077 movflt(dst, xmm0); 5078 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5079 addptr(rsp, 64); 5080 } else { 5081 movflt(dst, nds); 5082 vxorps(dst, dst, src, Assembler::AVX_128bit); 5083 } 5084 } else { 5085 vxorps(dst, nds, src, Assembler::AVX_128bit); 5086 } 5087 } 5088 5089 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5090 int nds_enc = nds->encoding(); 5091 int dst_enc = dst->encoding(); 5092 bool dst_upper_bank = (dst_enc > 15); 5093 bool nds_upper_bank = (nds_enc > 15); 5094 if (VM_Version::supports_avx512novl() && 5095 (nds_upper_bank || dst_upper_bank)) { 5096 if (dst_upper_bank) { 5097 subptr(rsp, 64); 5098 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5099 movdbl(xmm0, nds); 5100 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit); 5101 movdbl(dst, xmm0); 5102 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5103 addptr(rsp, 64); 5104 } else { 5105 movdbl(dst, nds); 5106 vxorpd(dst, dst, src, Assembler::AVX_128bit); 5107 } 5108 } else { 5109 vxorpd(dst, nds, src, Assembler::AVX_128bit); 5110 } 5111 } 5112 5113 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5114 if (reachable(src)) { 5115 vxorpd(dst, nds, as_Address(src), vector_len); 5116 } else { 5117 lea(rscratch1, src); 5118 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 5119 } 5120 } 5121 5122 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5123 if (reachable(src)) { 5124 vxorps(dst, nds, as_Address(src), vector_len); 5125 } else { 5126 lea(rscratch1, src); 5127 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 5128 } 5129 } 5130 5131 5132 void MacroAssembler::resolve_jobject(Register value, 5133 Register thread, 5134 Register tmp) { 5135 assert_different_registers(value, thread, tmp); 5136 Label done, not_weak; 5137 testptr(value, value); 5138 jcc(Assembler::zero, done); // Use NULL as-is. 5139 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag. 5140 jcc(Assembler::zero, not_weak); 5141 // Resolve jweak. 5142 movptr(value, Address(value, -JNIHandles::weak_tag_value)); 5143 verify_oop(value); 5144 #if INCLUDE_ALL_GCS 5145 if (UseG1GC) { 5146 g1_write_barrier_pre(noreg /* obj */, 5147 value /* pre_val */, 5148 thread /* thread */, 5149 tmp /* tmp */, 5150 true /* tosca_live */, 5151 true /* expand_call */); 5152 } 5153 #endif // INCLUDE_ALL_GCS 5154 jmp(done); 5155 bind(not_weak); 5156 // Resolve (untagged) jobject. 5157 movptr(value, Address(value, 0)); 5158 verify_oop(value); 5159 bind(done); 5160 } 5161 5162 ////////////////////////////////////////////////////////////////////////////////// 5163 #if INCLUDE_ALL_GCS 5164 5165 void MacroAssembler::g1_write_barrier_pre(Register obj, 5166 Register pre_val, 5167 Register thread, 5168 Register tmp, 5169 bool tosca_live, 5170 bool expand_call) { 5171 5172 // If expand_call is true then we expand the call_VM_leaf macro 5173 // directly to skip generating the check by 5174 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 5175 5176 #ifdef _LP64 5177 assert(thread == r15_thread, "must be"); 5178 #endif // _LP64 5179 5180 Label done; 5181 Label runtime; 5182 5183 assert(pre_val != noreg, "check this code"); 5184 5185 if (obj != noreg) { 5186 assert_different_registers(obj, pre_val, tmp); 5187 assert(pre_val != rax, "check this code"); 5188 } 5189 5190 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5191 SATBMarkQueue::byte_offset_of_active())); 5192 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5193 SATBMarkQueue::byte_offset_of_index())); 5194 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5195 SATBMarkQueue::byte_offset_of_buf())); 5196 5197 5198 // Is marking active? 5199 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 5200 cmpl(in_progress, 0); 5201 } else { 5202 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 5203 cmpb(in_progress, 0); 5204 } 5205 jcc(Assembler::equal, done); 5206 5207 // Do we need to load the previous value? 5208 if (obj != noreg) { 5209 load_heap_oop(pre_val, Address(obj, 0)); 5210 } 5211 5212 // Is the previous value null? 5213 cmpptr(pre_val, (int32_t) NULL_WORD); 5214 jcc(Assembler::equal, done); 5215 5216 // Can we store original value in the thread's buffer? 5217 // Is index == 0? 5218 // (The index field is typed as size_t.) 5219 5220 movptr(tmp, index); // tmp := *index_adr 5221 cmpptr(tmp, 0); // tmp == 0? 5222 jcc(Assembler::equal, runtime); // If yes, goto runtime 5223 5224 subptr(tmp, wordSize); // tmp := tmp - wordSize 5225 movptr(index, tmp); // *index_adr := tmp 5226 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 5227 5228 // Record the previous value 5229 movptr(Address(tmp, 0), pre_val); 5230 jmp(done); 5231 5232 bind(runtime); 5233 // save the live input values 5234 if(tosca_live) push(rax); 5235 5236 if (obj != noreg && obj != rax) 5237 push(obj); 5238 5239 if (pre_val != rax) 5240 push(pre_val); 5241 5242 // Calling the runtime using the regular call_VM_leaf mechanism generates 5243 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 5244 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 5245 // 5246 // If we care generating the pre-barrier without a frame (e.g. in the 5247 // intrinsified Reference.get() routine) then ebp might be pointing to 5248 // the caller frame and so this check will most likely fail at runtime. 5249 // 5250 // Expanding the call directly bypasses the generation of the check. 5251 // So when we do not have have a full interpreter frame on the stack 5252 // expand_call should be passed true. 5253 5254 NOT_LP64( push(thread); ) 5255 5256 if (expand_call) { 5257 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 5258 pass_arg1(this, thread); 5259 pass_arg0(this, pre_val); 5260 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 5261 } else { 5262 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 5263 } 5264 5265 NOT_LP64( pop(thread); ) 5266 5267 // save the live input values 5268 if (pre_val != rax) 5269 pop(pre_val); 5270 5271 if (obj != noreg && obj != rax) 5272 pop(obj); 5273 5274 if(tosca_live) pop(rax); 5275 5276 bind(done); 5277 } 5278 5279 void MacroAssembler::g1_write_barrier_post(Register store_addr, 5280 Register new_val, 5281 Register thread, 5282 Register tmp, 5283 Register tmp2) { 5284 #ifdef _LP64 5285 assert(thread == r15_thread, "must be"); 5286 #endif // _LP64 5287 5288 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5289 DirtyCardQueue::byte_offset_of_index())); 5290 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5291 DirtyCardQueue::byte_offset_of_buf())); 5292 5293 CardTableModRefBS* ct = 5294 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 5295 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5296 5297 Label done; 5298 Label runtime; 5299 5300 // Does store cross heap regions? 5301 5302 movptr(tmp, store_addr); 5303 xorptr(tmp, new_val); 5304 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 5305 jcc(Assembler::equal, done); 5306 5307 // crosses regions, storing NULL? 5308 5309 cmpptr(new_val, (int32_t) NULL_WORD); 5310 jcc(Assembler::equal, done); 5311 5312 // storing region crossing non-NULL, is card already dirty? 5313 5314 const Register card_addr = tmp; 5315 const Register cardtable = tmp2; 5316 5317 movptr(card_addr, store_addr); 5318 shrptr(card_addr, CardTableModRefBS::card_shift); 5319 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 5320 // a valid address and therefore is not properly handled by the relocation code. 5321 movptr(cardtable, (intptr_t)ct->byte_map_base); 5322 addptr(card_addr, cardtable); 5323 5324 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 5325 jcc(Assembler::equal, done); 5326 5327 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 5328 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5329 jcc(Assembler::equal, done); 5330 5331 5332 // storing a region crossing, non-NULL oop, card is clean. 5333 // dirty card and log. 5334 5335 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5336 5337 cmpl(queue_index, 0); 5338 jcc(Assembler::equal, runtime); 5339 subl(queue_index, wordSize); 5340 movptr(tmp2, buffer); 5341 #ifdef _LP64 5342 movslq(rscratch1, queue_index); 5343 addq(tmp2, rscratch1); 5344 movq(Address(tmp2, 0), card_addr); 5345 #else 5346 addl(tmp2, queue_index); 5347 movl(Address(tmp2, 0), card_addr); 5348 #endif 5349 jmp(done); 5350 5351 bind(runtime); 5352 // save the live input values 5353 push(store_addr); 5354 push(new_val); 5355 #ifdef _LP64 5356 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 5357 #else 5358 push(thread); 5359 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 5360 pop(thread); 5361 #endif 5362 pop(new_val); 5363 pop(store_addr); 5364 5365 bind(done); 5366 } 5367 5368 #endif // INCLUDE_ALL_GCS 5369 ////////////////////////////////////////////////////////////////////////////////// 5370 5371 5372 void MacroAssembler::store_check(Register obj, Address dst) { 5373 store_check(obj); 5374 } 5375 5376 void MacroAssembler::store_check(Register obj) { 5377 // Does a store check for the oop in register obj. The content of 5378 // register obj is destroyed afterwards. 5379 BarrierSet* bs = Universe::heap()->barrier_set(); 5380 assert(bs->kind() == BarrierSet::CardTableForRS || 5381 bs->kind() == BarrierSet::CardTableExtension, 5382 "Wrong barrier set kind"); 5383 5384 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 5385 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5386 5387 shrptr(obj, CardTableModRefBS::card_shift); 5388 5389 Address card_addr; 5390 5391 // The calculation for byte_map_base is as follows: 5392 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 5393 // So this essentially converts an address to a displacement and it will 5394 // never need to be relocated. On 64bit however the value may be too 5395 // large for a 32bit displacement. 5396 intptr_t disp = (intptr_t) ct->byte_map_base; 5397 if (is_simm32(disp)) { 5398 card_addr = Address(noreg, obj, Address::times_1, disp); 5399 } else { 5400 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 5401 // displacement and done in a single instruction given favorable mapping and a 5402 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 5403 // entry and that entry is not properly handled by the relocation code. 5404 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 5405 Address index(noreg, obj, Address::times_1); 5406 card_addr = as_Address(ArrayAddress(cardtable, index)); 5407 } 5408 5409 int dirty = CardTableModRefBS::dirty_card_val(); 5410 if (UseCondCardMark) { 5411 Label L_already_dirty; 5412 if (UseConcMarkSweepGC) { 5413 membar(Assembler::StoreLoad); 5414 } 5415 cmpb(card_addr, dirty); 5416 jcc(Assembler::equal, L_already_dirty); 5417 movb(card_addr, dirty); 5418 bind(L_already_dirty); 5419 } else { 5420 movb(card_addr, dirty); 5421 } 5422 } 5423 5424 void MacroAssembler::subptr(Register dst, int32_t imm32) { 5425 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 5426 } 5427 5428 // Force generation of a 4 byte immediate value even if it fits into 8bit 5429 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 5430 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 5431 } 5432 5433 void MacroAssembler::subptr(Register dst, Register src) { 5434 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 5435 } 5436 5437 // C++ bool manipulation 5438 void MacroAssembler::testbool(Register dst) { 5439 if(sizeof(bool) == 1) 5440 testb(dst, 0xff); 5441 else if(sizeof(bool) == 2) { 5442 // testw implementation needed for two byte bools 5443 ShouldNotReachHere(); 5444 } else if(sizeof(bool) == 4) 5445 testl(dst, dst); 5446 else 5447 // unsupported 5448 ShouldNotReachHere(); 5449 } 5450 5451 void MacroAssembler::testptr(Register dst, Register src) { 5452 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 5453 } 5454 5455 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5456 void MacroAssembler::tlab_allocate(Register obj, 5457 Register var_size_in_bytes, 5458 int con_size_in_bytes, 5459 Register t1, 5460 Register t2, 5461 Label& slow_case) { 5462 assert_different_registers(obj, t1, t2); 5463 assert_different_registers(obj, var_size_in_bytes, t1); 5464 Register end = t2; 5465 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 5466 5467 verify_tlab(); 5468 5469 NOT_LP64(get_thread(thread)); 5470 5471 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 5472 if (var_size_in_bytes == noreg) { 5473 lea(end, Address(obj, con_size_in_bytes)); 5474 } else { 5475 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 5476 } 5477 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 5478 jcc(Assembler::above, slow_case); 5479 5480 // update the tlab top pointer 5481 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 5482 5483 // recover var_size_in_bytes if necessary 5484 if (var_size_in_bytes == end) { 5485 subptr(var_size_in_bytes, obj); 5486 } 5487 verify_tlab(); 5488 } 5489 5490 // Preserves rbx, and rdx. 5491 Register MacroAssembler::tlab_refill(Label& retry, 5492 Label& try_eden, 5493 Label& slow_case) { 5494 Register top = rax; 5495 Register t1 = rcx; // object size 5496 Register t2 = rsi; 5497 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 5498 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 5499 Label do_refill, discard_tlab; 5500 5501 if (!Universe::heap()->supports_inline_contig_alloc()) { 5502 // No allocation in the shared eden. 5503 jmp(slow_case); 5504 } 5505 5506 NOT_LP64(get_thread(thread_reg)); 5507 5508 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5509 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5510 5511 // calculate amount of free space 5512 subptr(t1, top); 5513 shrptr(t1, LogHeapWordSize); 5514 5515 // Retain tlab and allocate object in shared space if 5516 // the amount free in the tlab is too large to discard. 5517 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 5518 jcc(Assembler::lessEqual, discard_tlab); 5519 5520 // Retain 5521 // %%% yuck as movptr... 5522 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 5523 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 5524 if (TLABStats) { 5525 // increment number of slow_allocations 5526 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 5527 } 5528 jmp(try_eden); 5529 5530 bind(discard_tlab); 5531 if (TLABStats) { 5532 // increment number of refills 5533 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 5534 // accumulate wastage -- t1 is amount free in tlab 5535 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 5536 } 5537 5538 // if tlab is currently allocated (top or end != null) then 5539 // fill [top, end + alignment_reserve) with array object 5540 testptr(top, top); 5541 jcc(Assembler::zero, do_refill); 5542 5543 // set up the mark word 5544 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 5545 // set the length to the remaining space 5546 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 5547 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 5548 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 5549 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 5550 // set klass to intArrayKlass 5551 // dubious reloc why not an oop reloc? 5552 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 5553 // store klass last. concurrent gcs assumes klass length is valid if 5554 // klass field is not null. 5555 store_klass(top, t1); 5556 5557 movptr(t1, top); 5558 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5559 incr_allocated_bytes(thread_reg, t1, 0); 5560 5561 // refill the tlab with an eden allocation 5562 bind(do_refill); 5563 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5564 shlptr(t1, LogHeapWordSize); 5565 // allocate new tlab, address returned in top 5566 eden_allocate(top, t1, 0, t2, slow_case); 5567 5568 // Check that t1 was preserved in eden_allocate. 5569 #ifdef ASSERT 5570 if (UseTLAB) { 5571 Label ok; 5572 Register tsize = rsi; 5573 assert_different_registers(tsize, thread_reg, t1); 5574 push(tsize); 5575 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5576 shlptr(tsize, LogHeapWordSize); 5577 cmpptr(t1, tsize); 5578 jcc(Assembler::equal, ok); 5579 STOP("assert(t1 != tlab size)"); 5580 should_not_reach_here(); 5581 5582 bind(ok); 5583 pop(tsize); 5584 } 5585 #endif 5586 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 5587 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 5588 addptr(top, t1); 5589 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 5590 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 5591 5592 if (ZeroTLAB) { 5593 // This is a fast TLAB refill, therefore the GC is not notified of it. 5594 // So compiled code must fill the new TLAB with zeroes. 5595 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5596 zero_memory(top, t1, 0, t2); 5597 } 5598 5599 verify_tlab(); 5600 jmp(retry); 5601 5602 return thread_reg; // for use by caller 5603 } 5604 5605 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 5606 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 5607 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 5608 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 5609 Label done; 5610 5611 testptr(length_in_bytes, length_in_bytes); 5612 jcc(Assembler::zero, done); 5613 5614 // initialize topmost word, divide index by 2, check if odd and test if zero 5615 // note: for the remaining code to work, index must be a multiple of BytesPerWord 5616 #ifdef ASSERT 5617 { 5618 Label L; 5619 testptr(length_in_bytes, BytesPerWord - 1); 5620 jcc(Assembler::zero, L); 5621 stop("length must be a multiple of BytesPerWord"); 5622 bind(L); 5623 } 5624 #endif 5625 Register index = length_in_bytes; 5626 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 5627 if (UseIncDec) { 5628 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 5629 } else { 5630 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 5631 shrptr(index, 1); 5632 } 5633 #ifndef _LP64 5634 // index could have not been a multiple of 8 (i.e., bit 2 was set) 5635 { 5636 Label even; 5637 // note: if index was a multiple of 8, then it cannot 5638 // be 0 now otherwise it must have been 0 before 5639 // => if it is even, we don't need to check for 0 again 5640 jcc(Assembler::carryClear, even); 5641 // clear topmost word (no jump would be needed if conditional assignment worked here) 5642 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 5643 // index could be 0 now, must check again 5644 jcc(Assembler::zero, done); 5645 bind(even); 5646 } 5647 #endif // !_LP64 5648 // initialize remaining object fields: index is a multiple of 2 now 5649 { 5650 Label loop; 5651 bind(loop); 5652 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 5653 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 5654 decrement(index); 5655 jcc(Assembler::notZero, loop); 5656 } 5657 5658 bind(done); 5659 } 5660 5661 void MacroAssembler::incr_allocated_bytes(Register thread, 5662 Register var_size_in_bytes, 5663 int con_size_in_bytes, 5664 Register t1) { 5665 if (!thread->is_valid()) { 5666 #ifdef _LP64 5667 thread = r15_thread; 5668 #else 5669 assert(t1->is_valid(), "need temp reg"); 5670 thread = t1; 5671 get_thread(thread); 5672 #endif 5673 } 5674 5675 #ifdef _LP64 5676 if (var_size_in_bytes->is_valid()) { 5677 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5678 } else { 5679 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5680 } 5681 #else 5682 if (var_size_in_bytes->is_valid()) { 5683 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5684 } else { 5685 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5686 } 5687 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 5688 #endif 5689 } 5690 5691 // Look up the method for a megamorphic invokeinterface call. 5692 // The target method is determined by <intf_klass, itable_index>. 5693 // The receiver klass is in recv_klass. 5694 // On success, the result will be in method_result, and execution falls through. 5695 // On failure, execution transfers to the given label. 5696 void MacroAssembler::lookup_interface_method(Register recv_klass, 5697 Register intf_klass, 5698 RegisterOrConstant itable_index, 5699 Register method_result, 5700 Register scan_temp, 5701 Label& L_no_such_interface) { 5702 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 5703 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 5704 "caller must use same register for non-constant itable index as for method"); 5705 5706 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 5707 int vtable_base = in_bytes(Klass::vtable_start_offset()); 5708 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 5709 int scan_step = itableOffsetEntry::size() * wordSize; 5710 int vte_size = vtableEntry::size_in_bytes(); 5711 Address::ScaleFactor times_vte_scale = Address::times_ptr; 5712 assert(vte_size == wordSize, "else adjust times_vte_scale"); 5713 5714 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 5715 5716 // %%% Could store the aligned, prescaled offset in the klassoop. 5717 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 5718 5719 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 5720 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 5721 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 5722 5723 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 5724 // if (scan->interface() == intf) { 5725 // result = (klass + scan->offset() + itable_index); 5726 // } 5727 // } 5728 Label search, found_method; 5729 5730 for (int peel = 1; peel >= 0; peel--) { 5731 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 5732 cmpptr(intf_klass, method_result); 5733 5734 if (peel) { 5735 jccb(Assembler::equal, found_method); 5736 } else { 5737 jccb(Assembler::notEqual, search); 5738 // (invert the test to fall through to found_method...) 5739 } 5740 5741 if (!peel) break; 5742 5743 bind(search); 5744 5745 // Check that the previous entry is non-null. A null entry means that 5746 // the receiver class doesn't implement the interface, and wasn't the 5747 // same as when the caller was compiled. 5748 testptr(method_result, method_result); 5749 jcc(Assembler::zero, L_no_such_interface); 5750 addptr(scan_temp, scan_step); 5751 } 5752 5753 bind(found_method); 5754 5755 // Got a hit. 5756 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5757 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5758 } 5759 5760 5761 // virtual method calling 5762 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5763 RegisterOrConstant vtable_index, 5764 Register method_result) { 5765 const int base = in_bytes(Klass::vtable_start_offset()); 5766 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5767 Address vtable_entry_addr(recv_klass, 5768 vtable_index, Address::times_ptr, 5769 base + vtableEntry::method_offset_in_bytes()); 5770 movptr(method_result, vtable_entry_addr); 5771 } 5772 5773 5774 void MacroAssembler::check_klass_subtype(Register sub_klass, 5775 Register super_klass, 5776 Register temp_reg, 5777 Label& L_success) { 5778 Label L_failure; 5779 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5780 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5781 bind(L_failure); 5782 } 5783 5784 5785 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5786 Register super_klass, 5787 Register temp_reg, 5788 Label* L_success, 5789 Label* L_failure, 5790 Label* L_slow_path, 5791 RegisterOrConstant super_check_offset) { 5792 assert_different_registers(sub_klass, super_klass, temp_reg); 5793 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5794 if (super_check_offset.is_register()) { 5795 assert_different_registers(sub_klass, super_klass, 5796 super_check_offset.as_register()); 5797 } else if (must_load_sco) { 5798 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5799 } 5800 5801 Label L_fallthrough; 5802 int label_nulls = 0; 5803 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5804 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5805 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5806 assert(label_nulls <= 1, "at most one NULL in the batch"); 5807 5808 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5809 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5810 Address super_check_offset_addr(super_klass, sco_offset); 5811 5812 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5813 // range of a jccb. If this routine grows larger, reconsider at 5814 // least some of these. 5815 #define local_jcc(assembler_cond, label) \ 5816 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5817 else jcc( assembler_cond, label) /*omit semi*/ 5818 5819 // Hacked jmp, which may only be used just before L_fallthrough. 5820 #define final_jmp(label) \ 5821 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5822 else jmp(label) /*omit semi*/ 5823 5824 // If the pointers are equal, we are done (e.g., String[] elements). 5825 // This self-check enables sharing of secondary supertype arrays among 5826 // non-primary types such as array-of-interface. Otherwise, each such 5827 // type would need its own customized SSA. 5828 // We move this check to the front of the fast path because many 5829 // type checks are in fact trivially successful in this manner, 5830 // so we get a nicely predicted branch right at the start of the check. 5831 cmpptr(sub_klass, super_klass); 5832 local_jcc(Assembler::equal, *L_success); 5833 5834 // Check the supertype display: 5835 if (must_load_sco) { 5836 // Positive movl does right thing on LP64. 5837 movl(temp_reg, super_check_offset_addr); 5838 super_check_offset = RegisterOrConstant(temp_reg); 5839 } 5840 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 5841 cmpptr(super_klass, super_check_addr); // load displayed supertype 5842 5843 // This check has worked decisively for primary supers. 5844 // Secondary supers are sought in the super_cache ('super_cache_addr'). 5845 // (Secondary supers are interfaces and very deeply nested subtypes.) 5846 // This works in the same check above because of a tricky aliasing 5847 // between the super_cache and the primary super display elements. 5848 // (The 'super_check_addr' can address either, as the case requires.) 5849 // Note that the cache is updated below if it does not help us find 5850 // what we need immediately. 5851 // So if it was a primary super, we can just fail immediately. 5852 // Otherwise, it's the slow path for us (no success at this point). 5853 5854 if (super_check_offset.is_register()) { 5855 local_jcc(Assembler::equal, *L_success); 5856 cmpl(super_check_offset.as_register(), sc_offset); 5857 if (L_failure == &L_fallthrough) { 5858 local_jcc(Assembler::equal, *L_slow_path); 5859 } else { 5860 local_jcc(Assembler::notEqual, *L_failure); 5861 final_jmp(*L_slow_path); 5862 } 5863 } else if (super_check_offset.as_constant() == sc_offset) { 5864 // Need a slow path; fast failure is impossible. 5865 if (L_slow_path == &L_fallthrough) { 5866 local_jcc(Assembler::equal, *L_success); 5867 } else { 5868 local_jcc(Assembler::notEqual, *L_slow_path); 5869 final_jmp(*L_success); 5870 } 5871 } else { 5872 // No slow path; it's a fast decision. 5873 if (L_failure == &L_fallthrough) { 5874 local_jcc(Assembler::equal, *L_success); 5875 } else { 5876 local_jcc(Assembler::notEqual, *L_failure); 5877 final_jmp(*L_success); 5878 } 5879 } 5880 5881 bind(L_fallthrough); 5882 5883 #undef local_jcc 5884 #undef final_jmp 5885 } 5886 5887 5888 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5889 Register super_klass, 5890 Register temp_reg, 5891 Register temp2_reg, 5892 Label* L_success, 5893 Label* L_failure, 5894 bool set_cond_codes) { 5895 assert_different_registers(sub_klass, super_klass, temp_reg); 5896 if (temp2_reg != noreg) 5897 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5898 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5899 5900 Label L_fallthrough; 5901 int label_nulls = 0; 5902 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5903 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5904 assert(label_nulls <= 1, "at most one NULL in the batch"); 5905 5906 // a couple of useful fields in sub_klass: 5907 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5908 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5909 Address secondary_supers_addr(sub_klass, ss_offset); 5910 Address super_cache_addr( sub_klass, sc_offset); 5911 5912 // Do a linear scan of the secondary super-klass chain. 5913 // This code is rarely used, so simplicity is a virtue here. 5914 // The repne_scan instruction uses fixed registers, which we must spill. 5915 // Don't worry too much about pre-existing connections with the input regs. 5916 5917 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 5918 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 5919 5920 // Get super_klass value into rax (even if it was in rdi or rcx). 5921 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 5922 if (super_klass != rax || UseCompressedOops) { 5923 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 5924 mov(rax, super_klass); 5925 } 5926 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 5927 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 5928 5929 #ifndef PRODUCT 5930 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 5931 ExternalAddress pst_counter_addr((address) pst_counter); 5932 NOT_LP64( incrementl(pst_counter_addr) ); 5933 LP64_ONLY( lea(rcx, pst_counter_addr) ); 5934 LP64_ONLY( incrementl(Address(rcx, 0)) ); 5935 #endif //PRODUCT 5936 5937 // We will consult the secondary-super array. 5938 movptr(rdi, secondary_supers_addr); 5939 // Load the array length. (Positive movl does right thing on LP64.) 5940 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 5941 // Skip to start of data. 5942 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 5943 5944 // Scan RCX words at [RDI] for an occurrence of RAX. 5945 // Set NZ/Z based on last compare. 5946 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 5947 // not change flags (only scas instruction which is repeated sets flags). 5948 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 5949 5950 testptr(rax,rax); // Set Z = 0 5951 repne_scan(); 5952 5953 // Unspill the temp. registers: 5954 if (pushed_rdi) pop(rdi); 5955 if (pushed_rcx) pop(rcx); 5956 if (pushed_rax) pop(rax); 5957 5958 if (set_cond_codes) { 5959 // Special hack for the AD files: rdi is guaranteed non-zero. 5960 assert(!pushed_rdi, "rdi must be left non-NULL"); 5961 // Also, the condition codes are properly set Z/NZ on succeed/failure. 5962 } 5963 5964 if (L_failure == &L_fallthrough) 5965 jccb(Assembler::notEqual, *L_failure); 5966 else jcc(Assembler::notEqual, *L_failure); 5967 5968 // Success. Cache the super we found and proceed in triumph. 5969 movptr(super_cache_addr, super_klass); 5970 5971 if (L_success != &L_fallthrough) { 5972 jmp(*L_success); 5973 } 5974 5975 #undef IS_A_TEMP 5976 5977 bind(L_fallthrough); 5978 } 5979 5980 5981 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 5982 if (VM_Version::supports_cmov()) { 5983 cmovl(cc, dst, src); 5984 } else { 5985 Label L; 5986 jccb(negate_condition(cc), L); 5987 movl(dst, src); 5988 bind(L); 5989 } 5990 } 5991 5992 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 5993 if (VM_Version::supports_cmov()) { 5994 cmovl(cc, dst, src); 5995 } else { 5996 Label L; 5997 jccb(negate_condition(cc), L); 5998 movl(dst, src); 5999 bind(L); 6000 } 6001 } 6002 6003 void MacroAssembler::verify_oop(Register reg, const char* s) { 6004 if (!VerifyOops) return; 6005 6006 // Pass register number to verify_oop_subroutine 6007 const char* b = NULL; 6008 { 6009 ResourceMark rm; 6010 stringStream ss; 6011 ss.print("verify_oop: %s: %s", reg->name(), s); 6012 b = code_string(ss.as_string()); 6013 } 6014 BLOCK_COMMENT("verify_oop {"); 6015 #ifdef _LP64 6016 push(rscratch1); // save r10, trashed by movptr() 6017 #endif 6018 push(rax); // save rax, 6019 push(reg); // pass register argument 6020 ExternalAddress buffer((address) b); 6021 // avoid using pushptr, as it modifies scratch registers 6022 // and our contract is not to modify anything 6023 movptr(rax, buffer.addr()); 6024 push(rax); 6025 // call indirectly to solve generation ordering problem 6026 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6027 call(rax); 6028 // Caller pops the arguments (oop, message) and restores rax, r10 6029 BLOCK_COMMENT("} verify_oop"); 6030 } 6031 6032 6033 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 6034 Register tmp, 6035 int offset) { 6036 intptr_t value = *delayed_value_addr; 6037 if (value != 0) 6038 return RegisterOrConstant(value + offset); 6039 6040 // load indirectly to solve generation ordering problem 6041 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 6042 6043 #ifdef ASSERT 6044 { Label L; 6045 testptr(tmp, tmp); 6046 if (WizardMode) { 6047 const char* buf = NULL; 6048 { 6049 ResourceMark rm; 6050 stringStream ss; 6051 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 6052 buf = code_string(ss.as_string()); 6053 } 6054 jcc(Assembler::notZero, L); 6055 STOP(buf); 6056 } else { 6057 jccb(Assembler::notZero, L); 6058 hlt(); 6059 } 6060 bind(L); 6061 } 6062 #endif 6063 6064 if (offset != 0) 6065 addptr(tmp, offset); 6066 6067 return RegisterOrConstant(tmp); 6068 } 6069 6070 6071 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 6072 int extra_slot_offset) { 6073 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 6074 int stackElementSize = Interpreter::stackElementSize; 6075 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 6076 #ifdef ASSERT 6077 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 6078 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 6079 #endif 6080 Register scale_reg = noreg; 6081 Address::ScaleFactor scale_factor = Address::no_scale; 6082 if (arg_slot.is_constant()) { 6083 offset += arg_slot.as_constant() * stackElementSize; 6084 } else { 6085 scale_reg = arg_slot.as_register(); 6086 scale_factor = Address::times(stackElementSize); 6087 } 6088 offset += wordSize; // return PC is on stack 6089 return Address(rsp, scale_reg, scale_factor, offset); 6090 } 6091 6092 6093 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 6094 if (!VerifyOops) return; 6095 6096 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 6097 // Pass register number to verify_oop_subroutine 6098 const char* b = NULL; 6099 { 6100 ResourceMark rm; 6101 stringStream ss; 6102 ss.print("verify_oop_addr: %s", s); 6103 b = code_string(ss.as_string()); 6104 } 6105 #ifdef _LP64 6106 push(rscratch1); // save r10, trashed by movptr() 6107 #endif 6108 push(rax); // save rax, 6109 // addr may contain rsp so we will have to adjust it based on the push 6110 // we just did (and on 64 bit we do two pushes) 6111 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 6112 // stores rax into addr which is backwards of what was intended. 6113 if (addr.uses(rsp)) { 6114 lea(rax, addr); 6115 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 6116 } else { 6117 pushptr(addr); 6118 } 6119 6120 ExternalAddress buffer((address) b); 6121 // pass msg argument 6122 // avoid using pushptr, as it modifies scratch registers 6123 // and our contract is not to modify anything 6124 movptr(rax, buffer.addr()); 6125 push(rax); 6126 6127 // call indirectly to solve generation ordering problem 6128 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6129 call(rax); 6130 // Caller pops the arguments (addr, message) and restores rax, r10. 6131 } 6132 6133 void MacroAssembler::verify_tlab() { 6134 #ifdef ASSERT 6135 if (UseTLAB && VerifyOops) { 6136 Label next, ok; 6137 Register t1 = rsi; 6138 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 6139 6140 push(t1); 6141 NOT_LP64(push(thread_reg)); 6142 NOT_LP64(get_thread(thread_reg)); 6143 6144 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6145 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 6146 jcc(Assembler::aboveEqual, next); 6147 STOP("assert(top >= start)"); 6148 should_not_reach_here(); 6149 6150 bind(next); 6151 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 6152 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6153 jcc(Assembler::aboveEqual, ok); 6154 STOP("assert(top <= end)"); 6155 should_not_reach_here(); 6156 6157 bind(ok); 6158 NOT_LP64(pop(thread_reg)); 6159 pop(t1); 6160 } 6161 #endif 6162 } 6163 6164 class ControlWord { 6165 public: 6166 int32_t _value; 6167 6168 int rounding_control() const { return (_value >> 10) & 3 ; } 6169 int precision_control() const { return (_value >> 8) & 3 ; } 6170 bool precision() const { return ((_value >> 5) & 1) != 0; } 6171 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6172 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6173 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6174 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6175 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6176 6177 void print() const { 6178 // rounding control 6179 const char* rc; 6180 switch (rounding_control()) { 6181 case 0: rc = "round near"; break; 6182 case 1: rc = "round down"; break; 6183 case 2: rc = "round up "; break; 6184 case 3: rc = "chop "; break; 6185 }; 6186 // precision control 6187 const char* pc; 6188 switch (precision_control()) { 6189 case 0: pc = "24 bits "; break; 6190 case 1: pc = "reserved"; break; 6191 case 2: pc = "53 bits "; break; 6192 case 3: pc = "64 bits "; break; 6193 }; 6194 // flags 6195 char f[9]; 6196 f[0] = ' '; 6197 f[1] = ' '; 6198 f[2] = (precision ()) ? 'P' : 'p'; 6199 f[3] = (underflow ()) ? 'U' : 'u'; 6200 f[4] = (overflow ()) ? 'O' : 'o'; 6201 f[5] = (zero_divide ()) ? 'Z' : 'z'; 6202 f[6] = (denormalized()) ? 'D' : 'd'; 6203 f[7] = (invalid ()) ? 'I' : 'i'; 6204 f[8] = '\x0'; 6205 // output 6206 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 6207 } 6208 6209 }; 6210 6211 class StatusWord { 6212 public: 6213 int32_t _value; 6214 6215 bool busy() const { return ((_value >> 15) & 1) != 0; } 6216 bool C3() const { return ((_value >> 14) & 1) != 0; } 6217 bool C2() const { return ((_value >> 10) & 1) != 0; } 6218 bool C1() const { return ((_value >> 9) & 1) != 0; } 6219 bool C0() const { return ((_value >> 8) & 1) != 0; } 6220 int top() const { return (_value >> 11) & 7 ; } 6221 bool error_status() const { return ((_value >> 7) & 1) != 0; } 6222 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 6223 bool precision() const { return ((_value >> 5) & 1) != 0; } 6224 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6225 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6226 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6227 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6228 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6229 6230 void print() const { 6231 // condition codes 6232 char c[5]; 6233 c[0] = (C3()) ? '3' : '-'; 6234 c[1] = (C2()) ? '2' : '-'; 6235 c[2] = (C1()) ? '1' : '-'; 6236 c[3] = (C0()) ? '0' : '-'; 6237 c[4] = '\x0'; 6238 // flags 6239 char f[9]; 6240 f[0] = (error_status()) ? 'E' : '-'; 6241 f[1] = (stack_fault ()) ? 'S' : '-'; 6242 f[2] = (precision ()) ? 'P' : '-'; 6243 f[3] = (underflow ()) ? 'U' : '-'; 6244 f[4] = (overflow ()) ? 'O' : '-'; 6245 f[5] = (zero_divide ()) ? 'Z' : '-'; 6246 f[6] = (denormalized()) ? 'D' : '-'; 6247 f[7] = (invalid ()) ? 'I' : '-'; 6248 f[8] = '\x0'; 6249 // output 6250 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 6251 } 6252 6253 }; 6254 6255 class TagWord { 6256 public: 6257 int32_t _value; 6258 6259 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 6260 6261 void print() const { 6262 printf("%04x", _value & 0xFFFF); 6263 } 6264 6265 }; 6266 6267 class FPU_Register { 6268 public: 6269 int32_t _m0; 6270 int32_t _m1; 6271 int16_t _ex; 6272 6273 bool is_indefinite() const { 6274 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 6275 } 6276 6277 void print() const { 6278 char sign = (_ex < 0) ? '-' : '+'; 6279 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 6280 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 6281 }; 6282 6283 }; 6284 6285 class FPU_State { 6286 public: 6287 enum { 6288 register_size = 10, 6289 number_of_registers = 8, 6290 register_mask = 7 6291 }; 6292 6293 ControlWord _control_word; 6294 StatusWord _status_word; 6295 TagWord _tag_word; 6296 int32_t _error_offset; 6297 int32_t _error_selector; 6298 int32_t _data_offset; 6299 int32_t _data_selector; 6300 int8_t _register[register_size * number_of_registers]; 6301 6302 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 6303 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 6304 6305 const char* tag_as_string(int tag) const { 6306 switch (tag) { 6307 case 0: return "valid"; 6308 case 1: return "zero"; 6309 case 2: return "special"; 6310 case 3: return "empty"; 6311 } 6312 ShouldNotReachHere(); 6313 return NULL; 6314 } 6315 6316 void print() const { 6317 // print computation registers 6318 { int t = _status_word.top(); 6319 for (int i = 0; i < number_of_registers; i++) { 6320 int j = (i - t) & register_mask; 6321 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 6322 st(j)->print(); 6323 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 6324 } 6325 } 6326 printf("\n"); 6327 // print control registers 6328 printf("ctrl = "); _control_word.print(); printf("\n"); 6329 printf("stat = "); _status_word .print(); printf("\n"); 6330 printf("tags = "); _tag_word .print(); printf("\n"); 6331 } 6332 6333 }; 6334 6335 class Flag_Register { 6336 public: 6337 int32_t _value; 6338 6339 bool overflow() const { return ((_value >> 11) & 1) != 0; } 6340 bool direction() const { return ((_value >> 10) & 1) != 0; } 6341 bool sign() const { return ((_value >> 7) & 1) != 0; } 6342 bool zero() const { return ((_value >> 6) & 1) != 0; } 6343 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 6344 bool parity() const { return ((_value >> 2) & 1) != 0; } 6345 bool carry() const { return ((_value >> 0) & 1) != 0; } 6346 6347 void print() const { 6348 // flags 6349 char f[8]; 6350 f[0] = (overflow ()) ? 'O' : '-'; 6351 f[1] = (direction ()) ? 'D' : '-'; 6352 f[2] = (sign ()) ? 'S' : '-'; 6353 f[3] = (zero ()) ? 'Z' : '-'; 6354 f[4] = (auxiliary_carry()) ? 'A' : '-'; 6355 f[5] = (parity ()) ? 'P' : '-'; 6356 f[6] = (carry ()) ? 'C' : '-'; 6357 f[7] = '\x0'; 6358 // output 6359 printf("%08x flags = %s", _value, f); 6360 } 6361 6362 }; 6363 6364 class IU_Register { 6365 public: 6366 int32_t _value; 6367 6368 void print() const { 6369 printf("%08x %11d", _value, _value); 6370 } 6371 6372 }; 6373 6374 class IU_State { 6375 public: 6376 Flag_Register _eflags; 6377 IU_Register _rdi; 6378 IU_Register _rsi; 6379 IU_Register _rbp; 6380 IU_Register _rsp; 6381 IU_Register _rbx; 6382 IU_Register _rdx; 6383 IU_Register _rcx; 6384 IU_Register _rax; 6385 6386 void print() const { 6387 // computation registers 6388 printf("rax, = "); _rax.print(); printf("\n"); 6389 printf("rbx, = "); _rbx.print(); printf("\n"); 6390 printf("rcx = "); _rcx.print(); printf("\n"); 6391 printf("rdx = "); _rdx.print(); printf("\n"); 6392 printf("rdi = "); _rdi.print(); printf("\n"); 6393 printf("rsi = "); _rsi.print(); printf("\n"); 6394 printf("rbp, = "); _rbp.print(); printf("\n"); 6395 printf("rsp = "); _rsp.print(); printf("\n"); 6396 printf("\n"); 6397 // control registers 6398 printf("flgs = "); _eflags.print(); printf("\n"); 6399 } 6400 }; 6401 6402 6403 class CPU_State { 6404 public: 6405 FPU_State _fpu_state; 6406 IU_State _iu_state; 6407 6408 void print() const { 6409 printf("--------------------------------------------------\n"); 6410 _iu_state .print(); 6411 printf("\n"); 6412 _fpu_state.print(); 6413 printf("--------------------------------------------------\n"); 6414 } 6415 6416 }; 6417 6418 6419 static void _print_CPU_state(CPU_State* state) { 6420 state->print(); 6421 }; 6422 6423 6424 void MacroAssembler::print_CPU_state() { 6425 push_CPU_state(); 6426 push(rsp); // pass CPU state 6427 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 6428 addptr(rsp, wordSize); // discard argument 6429 pop_CPU_state(); 6430 } 6431 6432 6433 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 6434 static int counter = 0; 6435 FPU_State* fs = &state->_fpu_state; 6436 counter++; 6437 // For leaf calls, only verify that the top few elements remain empty. 6438 // We only need 1 empty at the top for C2 code. 6439 if( stack_depth < 0 ) { 6440 if( fs->tag_for_st(7) != 3 ) { 6441 printf("FPR7 not empty\n"); 6442 state->print(); 6443 assert(false, "error"); 6444 return false; 6445 } 6446 return true; // All other stack states do not matter 6447 } 6448 6449 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 6450 "bad FPU control word"); 6451 6452 // compute stack depth 6453 int i = 0; 6454 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 6455 int d = i; 6456 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 6457 // verify findings 6458 if (i != FPU_State::number_of_registers) { 6459 // stack not contiguous 6460 printf("%s: stack not contiguous at ST%d\n", s, i); 6461 state->print(); 6462 assert(false, "error"); 6463 return false; 6464 } 6465 // check if computed stack depth corresponds to expected stack depth 6466 if (stack_depth < 0) { 6467 // expected stack depth is -stack_depth or less 6468 if (d > -stack_depth) { 6469 // too many elements on the stack 6470 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 6471 state->print(); 6472 assert(false, "error"); 6473 return false; 6474 } 6475 } else { 6476 // expected stack depth is stack_depth 6477 if (d != stack_depth) { 6478 // wrong stack depth 6479 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 6480 state->print(); 6481 assert(false, "error"); 6482 return false; 6483 } 6484 } 6485 // everything is cool 6486 return true; 6487 } 6488 6489 6490 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 6491 if (!VerifyFPU) return; 6492 push_CPU_state(); 6493 push(rsp); // pass CPU state 6494 ExternalAddress msg((address) s); 6495 // pass message string s 6496 pushptr(msg.addr()); 6497 push(stack_depth); // pass stack depth 6498 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 6499 addptr(rsp, 3 * wordSize); // discard arguments 6500 // check for error 6501 { Label L; 6502 testl(rax, rax); 6503 jcc(Assembler::notZero, L); 6504 int3(); // break if error condition 6505 bind(L); 6506 } 6507 pop_CPU_state(); 6508 } 6509 6510 void MacroAssembler::restore_cpu_control_state_after_jni() { 6511 // Either restore the MXCSR register after returning from the JNI Call 6512 // or verify that it wasn't changed (with -Xcheck:jni flag). 6513 if (VM_Version::supports_sse()) { 6514 if (RestoreMXCSROnJNICalls) { 6515 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 6516 } else if (CheckJNICalls) { 6517 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 6518 } 6519 } 6520 if (VM_Version::supports_avx()) { 6521 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 6522 vzeroupper(); 6523 } 6524 6525 #ifndef _LP64 6526 // Either restore the x87 floating pointer control word after returning 6527 // from the JNI call or verify that it wasn't changed. 6528 if (CheckJNICalls) { 6529 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 6530 } 6531 #endif // _LP64 6532 } 6533 6534 void MacroAssembler::load_mirror(Register mirror, Register method) { 6535 // get mirror 6536 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 6537 movptr(mirror, Address(method, Method::const_offset())); 6538 movptr(mirror, Address(mirror, ConstMethod::constants_offset())); 6539 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes())); 6540 movptr(mirror, Address(mirror, mirror_offset)); 6541 } 6542 6543 void MacroAssembler::load_klass(Register dst, Register src) { 6544 #ifdef _LP64 6545 if (UseCompressedClassPointers) { 6546 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6547 decode_klass_not_null(dst); 6548 } else 6549 #endif 6550 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6551 } 6552 6553 void MacroAssembler::load_prototype_header(Register dst, Register src) { 6554 load_klass(dst, src); 6555 movptr(dst, Address(dst, Klass::prototype_header_offset())); 6556 } 6557 6558 void MacroAssembler::store_klass(Register dst, Register src) { 6559 #ifdef _LP64 6560 if (UseCompressedClassPointers) { 6561 encode_klass_not_null(src); 6562 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6563 } else 6564 #endif 6565 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6566 } 6567 6568 void MacroAssembler::load_heap_oop(Register dst, Address src) { 6569 #ifdef _LP64 6570 // FIXME: Must change all places where we try to load the klass. 6571 if (UseCompressedOops) { 6572 movl(dst, src); 6573 decode_heap_oop(dst); 6574 } else 6575 #endif 6576 movptr(dst, src); 6577 } 6578 6579 // Doesn't do verfication, generates fixed size code 6580 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 6581 #ifdef _LP64 6582 if (UseCompressedOops) { 6583 movl(dst, src); 6584 decode_heap_oop_not_null(dst); 6585 } else 6586 #endif 6587 movptr(dst, src); 6588 } 6589 6590 void MacroAssembler::store_heap_oop(Address dst, Register src) { 6591 #ifdef _LP64 6592 if (UseCompressedOops) { 6593 assert(!dst.uses(src), "not enough registers"); 6594 encode_heap_oop(src); 6595 movl(dst, src); 6596 } else 6597 #endif 6598 movptr(dst, src); 6599 } 6600 6601 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 6602 assert_different_registers(src1, tmp); 6603 #ifdef _LP64 6604 if (UseCompressedOops) { 6605 bool did_push = false; 6606 if (tmp == noreg) { 6607 tmp = rax; 6608 push(tmp); 6609 did_push = true; 6610 assert(!src2.uses(rsp), "can't push"); 6611 } 6612 load_heap_oop(tmp, src2); 6613 cmpptr(src1, tmp); 6614 if (did_push) pop(tmp); 6615 } else 6616 #endif 6617 cmpptr(src1, src2); 6618 } 6619 6620 // Used for storing NULLs. 6621 void MacroAssembler::store_heap_oop_null(Address dst) { 6622 #ifdef _LP64 6623 if (UseCompressedOops) { 6624 movl(dst, (int32_t)NULL_WORD); 6625 } else { 6626 movslq(dst, (int32_t)NULL_WORD); 6627 } 6628 #else 6629 movl(dst, (int32_t)NULL_WORD); 6630 #endif 6631 } 6632 6633 #ifdef _LP64 6634 void MacroAssembler::store_klass_gap(Register dst, Register src) { 6635 if (UseCompressedClassPointers) { 6636 // Store to klass gap in destination 6637 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 6638 } 6639 } 6640 6641 #ifdef ASSERT 6642 void MacroAssembler::verify_heapbase(const char* msg) { 6643 assert (UseCompressedOops, "should be compressed"); 6644 assert (Universe::heap() != NULL, "java heap should be initialized"); 6645 if (CheckCompressedOops) { 6646 Label ok; 6647 push(rscratch1); // cmpptr trashes rscratch1 6648 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6649 jcc(Assembler::equal, ok); 6650 STOP(msg); 6651 bind(ok); 6652 pop(rscratch1); 6653 } 6654 } 6655 #endif 6656 6657 // Algorithm must match oop.inline.hpp encode_heap_oop. 6658 void MacroAssembler::encode_heap_oop(Register r) { 6659 #ifdef ASSERT 6660 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 6661 #endif 6662 verify_oop(r, "broken oop in encode_heap_oop"); 6663 if (Universe::narrow_oop_base() == NULL) { 6664 if (Universe::narrow_oop_shift() != 0) { 6665 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6666 shrq(r, LogMinObjAlignmentInBytes); 6667 } 6668 return; 6669 } 6670 testq(r, r); 6671 cmovq(Assembler::equal, r, r12_heapbase); 6672 subq(r, r12_heapbase); 6673 shrq(r, LogMinObjAlignmentInBytes); 6674 } 6675 6676 void MacroAssembler::encode_heap_oop_not_null(Register r) { 6677 #ifdef ASSERT 6678 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 6679 if (CheckCompressedOops) { 6680 Label ok; 6681 testq(r, r); 6682 jcc(Assembler::notEqual, ok); 6683 STOP("null oop passed to encode_heap_oop_not_null"); 6684 bind(ok); 6685 } 6686 #endif 6687 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 6688 if (Universe::narrow_oop_base() != NULL) { 6689 subq(r, r12_heapbase); 6690 } 6691 if (Universe::narrow_oop_shift() != 0) { 6692 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6693 shrq(r, LogMinObjAlignmentInBytes); 6694 } 6695 } 6696 6697 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 6698 #ifdef ASSERT 6699 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 6700 if (CheckCompressedOops) { 6701 Label ok; 6702 testq(src, src); 6703 jcc(Assembler::notEqual, ok); 6704 STOP("null oop passed to encode_heap_oop_not_null2"); 6705 bind(ok); 6706 } 6707 #endif 6708 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 6709 if (dst != src) { 6710 movq(dst, src); 6711 } 6712 if (Universe::narrow_oop_base() != NULL) { 6713 subq(dst, r12_heapbase); 6714 } 6715 if (Universe::narrow_oop_shift() != 0) { 6716 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6717 shrq(dst, LogMinObjAlignmentInBytes); 6718 } 6719 } 6720 6721 void MacroAssembler::decode_heap_oop(Register r) { 6722 #ifdef ASSERT 6723 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 6724 #endif 6725 if (Universe::narrow_oop_base() == NULL) { 6726 if (Universe::narrow_oop_shift() != 0) { 6727 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6728 shlq(r, LogMinObjAlignmentInBytes); 6729 } 6730 } else { 6731 Label done; 6732 shlq(r, LogMinObjAlignmentInBytes); 6733 jccb(Assembler::equal, done); 6734 addq(r, r12_heapbase); 6735 bind(done); 6736 } 6737 verify_oop(r, "broken oop in decode_heap_oop"); 6738 } 6739 6740 void MacroAssembler::decode_heap_oop_not_null(Register r) { 6741 // Note: it will change flags 6742 assert (UseCompressedOops, "should only be used for compressed headers"); 6743 assert (Universe::heap() != NULL, "java heap should be initialized"); 6744 // Cannot assert, unverified entry point counts instructions (see .ad file) 6745 // vtableStubs also counts instructions in pd_code_size_limit. 6746 // Also do not verify_oop as this is called by verify_oop. 6747 if (Universe::narrow_oop_shift() != 0) { 6748 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6749 shlq(r, LogMinObjAlignmentInBytes); 6750 if (Universe::narrow_oop_base() != NULL) { 6751 addq(r, r12_heapbase); 6752 } 6753 } else { 6754 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6755 } 6756 } 6757 6758 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 6759 // Note: it will change flags 6760 assert (UseCompressedOops, "should only be used for compressed headers"); 6761 assert (Universe::heap() != NULL, "java heap should be initialized"); 6762 // Cannot assert, unverified entry point counts instructions (see .ad file) 6763 // vtableStubs also counts instructions in pd_code_size_limit. 6764 // Also do not verify_oop as this is called by verify_oop. 6765 if (Universe::narrow_oop_shift() != 0) { 6766 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6767 if (LogMinObjAlignmentInBytes == Address::times_8) { 6768 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6769 } else { 6770 if (dst != src) { 6771 movq(dst, src); 6772 } 6773 shlq(dst, LogMinObjAlignmentInBytes); 6774 if (Universe::narrow_oop_base() != NULL) { 6775 addq(dst, r12_heapbase); 6776 } 6777 } 6778 } else { 6779 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6780 if (dst != src) { 6781 movq(dst, src); 6782 } 6783 } 6784 } 6785 6786 void MacroAssembler::encode_klass_not_null(Register r) { 6787 if (Universe::narrow_klass_base() != NULL) { 6788 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6789 assert(r != r12_heapbase, "Encoding a klass in r12"); 6790 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6791 subq(r, r12_heapbase); 6792 } 6793 if (Universe::narrow_klass_shift() != 0) { 6794 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6795 shrq(r, LogKlassAlignmentInBytes); 6796 } 6797 if (Universe::narrow_klass_base() != NULL) { 6798 reinit_heapbase(); 6799 } 6800 } 6801 6802 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6803 if (dst == src) { 6804 encode_klass_not_null(src); 6805 } else { 6806 if (Universe::narrow_klass_base() != NULL) { 6807 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6808 negq(dst); 6809 addq(dst, src); 6810 } else { 6811 movptr(dst, src); 6812 } 6813 if (Universe::narrow_klass_shift() != 0) { 6814 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6815 shrq(dst, LogKlassAlignmentInBytes); 6816 } 6817 } 6818 } 6819 6820 // Function instr_size_for_decode_klass_not_null() counts the instructions 6821 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6822 // when (Universe::heap() != NULL). Hence, if the instructions they 6823 // generate change, then this method needs to be updated. 6824 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6825 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6826 if (Universe::narrow_klass_base() != NULL) { 6827 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6828 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6829 } else { 6830 // longest load decode klass function, mov64, leaq 6831 return 16; 6832 } 6833 } 6834 6835 // !!! If the instructions that get generated here change then function 6836 // instr_size_for_decode_klass_not_null() needs to get updated. 6837 void MacroAssembler::decode_klass_not_null(Register r) { 6838 // Note: it will change flags 6839 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6840 assert(r != r12_heapbase, "Decoding a klass in r12"); 6841 // Cannot assert, unverified entry point counts instructions (see .ad file) 6842 // vtableStubs also counts instructions in pd_code_size_limit. 6843 // Also do not verify_oop as this is called by verify_oop. 6844 if (Universe::narrow_klass_shift() != 0) { 6845 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6846 shlq(r, LogKlassAlignmentInBytes); 6847 } 6848 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6849 if (Universe::narrow_klass_base() != NULL) { 6850 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6851 addq(r, r12_heapbase); 6852 reinit_heapbase(); 6853 } 6854 } 6855 6856 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 6857 // Note: it will change flags 6858 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6859 if (dst == src) { 6860 decode_klass_not_null(dst); 6861 } else { 6862 // Cannot assert, unverified entry point counts instructions (see .ad file) 6863 // vtableStubs also counts instructions in pd_code_size_limit. 6864 // Also do not verify_oop as this is called by verify_oop. 6865 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6866 if (Universe::narrow_klass_shift() != 0) { 6867 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6868 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 6869 leaq(dst, Address(dst, src, Address::times_8, 0)); 6870 } else { 6871 addq(dst, src); 6872 } 6873 } 6874 } 6875 6876 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 6877 assert (UseCompressedOops, "should only be used for compressed headers"); 6878 assert (Universe::heap() != NULL, "java heap should be initialized"); 6879 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6880 int oop_index = oop_recorder()->find_index(obj); 6881 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6882 mov_narrow_oop(dst, oop_index, rspec); 6883 } 6884 6885 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 6886 assert (UseCompressedOops, "should only be used for compressed headers"); 6887 assert (Universe::heap() != NULL, "java heap should be initialized"); 6888 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6889 int oop_index = oop_recorder()->find_index(obj); 6890 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6891 mov_narrow_oop(dst, oop_index, rspec); 6892 } 6893 6894 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6895 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6896 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6897 int klass_index = oop_recorder()->find_index(k); 6898 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6899 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6900 } 6901 6902 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 6903 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6904 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6905 int klass_index = oop_recorder()->find_index(k); 6906 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6907 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6908 } 6909 6910 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 6911 assert (UseCompressedOops, "should only be used for compressed headers"); 6912 assert (Universe::heap() != NULL, "java heap should be initialized"); 6913 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6914 int oop_index = oop_recorder()->find_index(obj); 6915 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6916 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6917 } 6918 6919 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 6920 assert (UseCompressedOops, "should only be used for compressed headers"); 6921 assert (Universe::heap() != NULL, "java heap should be initialized"); 6922 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6923 int oop_index = oop_recorder()->find_index(obj); 6924 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6925 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6926 } 6927 6928 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 6929 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6930 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6931 int klass_index = oop_recorder()->find_index(k); 6932 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6933 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6934 } 6935 6936 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 6937 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6938 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6939 int klass_index = oop_recorder()->find_index(k); 6940 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6941 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6942 } 6943 6944 void MacroAssembler::reinit_heapbase() { 6945 if (UseCompressedOops || UseCompressedClassPointers) { 6946 if (Universe::heap() != NULL) { 6947 if (Universe::narrow_oop_base() == NULL) { 6948 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 6949 } else { 6950 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 6951 } 6952 } else { 6953 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6954 } 6955 } 6956 } 6957 6958 #endif // _LP64 6959 6960 6961 // C2 compiled method's prolog code. 6962 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 6963 6964 // WARNING: Initial instruction MUST be 5 bytes or longer so that 6965 // NativeJump::patch_verified_entry will be able to patch out the entry 6966 // code safely. The push to verify stack depth is ok at 5 bytes, 6967 // the frame allocation can be either 3 or 6 bytes. So if we don't do 6968 // stack bang then we must use the 6 byte frame allocation even if 6969 // we have no frame. :-( 6970 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 6971 6972 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 6973 // Remove word for return addr 6974 framesize -= wordSize; 6975 stack_bang_size -= wordSize; 6976 6977 // Calls to C2R adapters often do not accept exceptional returns. 6978 // We require that their callers must bang for them. But be careful, because 6979 // some VM calls (such as call site linkage) can use several kilobytes of 6980 // stack. But the stack safety zone should account for that. 6981 // See bugs 4446381, 4468289, 4497237. 6982 if (stack_bang_size > 0) { 6983 generate_stack_overflow_check(stack_bang_size); 6984 6985 // We always push rbp, so that on return to interpreter rbp, will be 6986 // restored correctly and we can correct the stack. 6987 push(rbp); 6988 // Save caller's stack pointer into RBP if the frame pointer is preserved. 6989 if (PreserveFramePointer) { 6990 mov(rbp, rsp); 6991 } 6992 // Remove word for ebp 6993 framesize -= wordSize; 6994 6995 // Create frame 6996 if (framesize) { 6997 subptr(rsp, framesize); 6998 } 6999 } else { 7000 // Create frame (force generation of a 4 byte immediate value) 7001 subptr_imm32(rsp, framesize); 7002 7003 // Save RBP register now. 7004 framesize -= wordSize; 7005 movptr(Address(rsp, framesize), rbp); 7006 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7007 if (PreserveFramePointer) { 7008 movptr(rbp, rsp); 7009 if (framesize > 0) { 7010 addptr(rbp, framesize); 7011 } 7012 } 7013 } 7014 7015 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 7016 framesize -= wordSize; 7017 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 7018 } 7019 7020 #ifndef _LP64 7021 // If method sets FPU control word do it now 7022 if (fp_mode_24b) { 7023 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 7024 } 7025 if (UseSSE >= 2 && VerifyFPU) { 7026 verify_FPU(0, "FPU stack must be clean on entry"); 7027 } 7028 #endif 7029 7030 #ifdef ASSERT 7031 if (VerifyStackAtCalls) { 7032 Label L; 7033 push(rax); 7034 mov(rax, rsp); 7035 andptr(rax, StackAlignmentInBytes-1); 7036 cmpptr(rax, StackAlignmentInBytes-wordSize); 7037 pop(rax); 7038 jcc(Assembler::equal, L); 7039 STOP("Stack is not properly aligned!"); 7040 bind(L); 7041 } 7042 #endif 7043 7044 } 7045 7046 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) { 7047 // cnt - number of qwords (8-byte words). 7048 // base - start address, qword aligned. 7049 // is_large - if optimizers know cnt is larger than InitArrayShortSize 7050 assert(base==rdi, "base register must be edi for rep stos"); 7051 assert(tmp==rax, "tmp register must be eax for rep stos"); 7052 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 7053 assert(InitArrayShortSize % BytesPerLong == 0, 7054 "InitArrayShortSize should be the multiple of BytesPerLong"); 7055 7056 Label DONE; 7057 7058 xorptr(tmp, tmp); 7059 7060 if (!is_large) { 7061 Label LOOP, LONG; 7062 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 7063 jccb(Assembler::greater, LONG); 7064 7065 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7066 7067 decrement(cnt); 7068 jccb(Assembler::negative, DONE); // Zero length 7069 7070 // Use individual pointer-sized stores for small counts: 7071 BIND(LOOP); 7072 movptr(Address(base, cnt, Address::times_ptr), tmp); 7073 decrement(cnt); 7074 jccb(Assembler::greaterEqual, LOOP); 7075 jmpb(DONE); 7076 7077 BIND(LONG); 7078 } 7079 7080 // Use longer rep-prefixed ops for non-small counts: 7081 if (UseFastStosb) { 7082 shlptr(cnt, 3); // convert to number of bytes 7083 rep_stosb(); 7084 } else { 7085 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7086 rep_stos(); 7087 } 7088 7089 BIND(DONE); 7090 } 7091 7092 #ifdef COMPILER2 7093 7094 // IndexOf for constant substrings with size >= 8 chars 7095 // which don't need to be loaded through stack. 7096 void MacroAssembler::string_indexofC8(Register str1, Register str2, 7097 Register cnt1, Register cnt2, 7098 int int_cnt2, Register result, 7099 XMMRegister vec, Register tmp, 7100 int ae) { 7101 ShortBranchVerifier sbv(this); 7102 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7103 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7104 7105 // This method uses the pcmpestri instruction with bound registers 7106 // inputs: 7107 // xmm - substring 7108 // rax - substring length (elements count) 7109 // mem - scanned string 7110 // rdx - string length (elements count) 7111 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7112 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7113 // outputs: 7114 // rcx - matched index in string 7115 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7116 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7117 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7118 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7119 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7120 7121 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 7122 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 7123 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 7124 7125 // Note, inline_string_indexOf() generates checks: 7126 // if (substr.count > string.count) return -1; 7127 // if (substr.count == 0) return 0; 7128 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars"); 7129 7130 // Load substring. 7131 if (ae == StrIntrinsicNode::UL) { 7132 pmovzxbw(vec, Address(str2, 0)); 7133 } else { 7134 movdqu(vec, Address(str2, 0)); 7135 } 7136 movl(cnt2, int_cnt2); 7137 movptr(result, str1); // string addr 7138 7139 if (int_cnt2 > stride) { 7140 jmpb(SCAN_TO_SUBSTR); 7141 7142 // Reload substr for rescan, this code 7143 // is executed only for large substrings (> 8 chars) 7144 bind(RELOAD_SUBSTR); 7145 if (ae == StrIntrinsicNode::UL) { 7146 pmovzxbw(vec, Address(str2, 0)); 7147 } else { 7148 movdqu(vec, Address(str2, 0)); 7149 } 7150 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 7151 7152 bind(RELOAD_STR); 7153 // We came here after the beginning of the substring was 7154 // matched but the rest of it was not so we need to search 7155 // again. Start from the next element after the previous match. 7156 7157 // cnt2 is number of substring reminding elements and 7158 // cnt1 is number of string reminding elements when cmp failed. 7159 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 7160 subl(cnt1, cnt2); 7161 addl(cnt1, int_cnt2); 7162 movl(cnt2, int_cnt2); // Now restore cnt2 7163 7164 decrementl(cnt1); // Shift to next element 7165 cmpl(cnt1, cnt2); 7166 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7167 7168 addptr(result, (1<<scale1)); 7169 7170 } // (int_cnt2 > 8) 7171 7172 // Scan string for start of substr in 16-byte vectors 7173 bind(SCAN_TO_SUBSTR); 7174 pcmpestri(vec, Address(result, 0), mode); 7175 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7176 subl(cnt1, stride); 7177 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7178 cmpl(cnt1, cnt2); 7179 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7180 addptr(result, 16); 7181 jmpb(SCAN_TO_SUBSTR); 7182 7183 // Found a potential substr 7184 bind(FOUND_CANDIDATE); 7185 // Matched whole vector if first element matched (tmp(rcx) == 0). 7186 if (int_cnt2 == stride) { 7187 jccb(Assembler::overflow, RET_FOUND); // OF == 1 7188 } else { // int_cnt2 > 8 7189 jccb(Assembler::overflow, FOUND_SUBSTR); 7190 } 7191 // After pcmpestri tmp(rcx) contains matched element index 7192 // Compute start addr of substr 7193 lea(result, Address(result, tmp, scale1)); 7194 7195 // Make sure string is still long enough 7196 subl(cnt1, tmp); 7197 cmpl(cnt1, cnt2); 7198 if (int_cnt2 == stride) { 7199 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7200 } else { // int_cnt2 > 8 7201 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 7202 } 7203 // Left less then substring. 7204 7205 bind(RET_NOT_FOUND); 7206 movl(result, -1); 7207 jmp(EXIT); 7208 7209 if (int_cnt2 > stride) { 7210 // This code is optimized for the case when whole substring 7211 // is matched if its head is matched. 7212 bind(MATCH_SUBSTR_HEAD); 7213 pcmpestri(vec, Address(result, 0), mode); 7214 // Reload only string if does not match 7215 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0 7216 7217 Label CONT_SCAN_SUBSTR; 7218 // Compare the rest of substring (> 8 chars). 7219 bind(FOUND_SUBSTR); 7220 // First 8 chars are already matched. 7221 negptr(cnt2); 7222 addptr(cnt2, stride); 7223 7224 bind(SCAN_SUBSTR); 7225 subl(cnt1, stride); 7226 cmpl(cnt2, -stride); // Do not read beyond substring 7227 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 7228 // Back-up strings to avoid reading beyond substring: 7229 // cnt1 = cnt1 - cnt2 + 8 7230 addl(cnt1, cnt2); // cnt2 is negative 7231 addl(cnt1, stride); 7232 movl(cnt2, stride); negptr(cnt2); 7233 bind(CONT_SCAN_SUBSTR); 7234 if (int_cnt2 < (int)G) { 7235 int tail_off1 = int_cnt2<<scale1; 7236 int tail_off2 = int_cnt2<<scale2; 7237 if (ae == StrIntrinsicNode::UL) { 7238 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2)); 7239 } else { 7240 movdqu(vec, Address(str2, cnt2, scale2, tail_off2)); 7241 } 7242 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode); 7243 } else { 7244 // calculate index in register to avoid integer overflow (int_cnt2*2) 7245 movl(tmp, int_cnt2); 7246 addptr(tmp, cnt2); 7247 if (ae == StrIntrinsicNode::UL) { 7248 pmovzxbw(vec, Address(str2, tmp, scale2, 0)); 7249 } else { 7250 movdqu(vec, Address(str2, tmp, scale2, 0)); 7251 } 7252 pcmpestri(vec, Address(result, tmp, scale1, 0), mode); 7253 } 7254 // Need to reload strings pointers if not matched whole vector 7255 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7256 addptr(cnt2, stride); 7257 jcc(Assembler::negative, SCAN_SUBSTR); 7258 // Fall through if found full substring 7259 7260 } // (int_cnt2 > 8) 7261 7262 bind(RET_FOUND); 7263 // Found result if we matched full small substring. 7264 // Compute substr offset 7265 subptr(result, str1); 7266 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7267 shrl(result, 1); // index 7268 } 7269 bind(EXIT); 7270 7271 } // string_indexofC8 7272 7273 // Small strings are loaded through stack if they cross page boundary. 7274 void MacroAssembler::string_indexof(Register str1, Register str2, 7275 Register cnt1, Register cnt2, 7276 int int_cnt2, Register result, 7277 XMMRegister vec, Register tmp, 7278 int ae) { 7279 ShortBranchVerifier sbv(this); 7280 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7281 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7282 7283 // 7284 // int_cnt2 is length of small (< 8 chars) constant substring 7285 // or (-1) for non constant substring in which case its length 7286 // is in cnt2 register. 7287 // 7288 // Note, inline_string_indexOf() generates checks: 7289 // if (substr.count > string.count) return -1; 7290 // if (substr.count == 0) return 0; 7291 // 7292 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7293 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0"); 7294 // This method uses the pcmpestri instruction with bound registers 7295 // inputs: 7296 // xmm - substring 7297 // rax - substring length (elements count) 7298 // mem - scanned string 7299 // rdx - string length (elements count) 7300 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7301 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7302 // outputs: 7303 // rcx - matched index in string 7304 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7305 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7306 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7307 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7308 7309 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 7310 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 7311 FOUND_CANDIDATE; 7312 7313 { //======================================================== 7314 // We don't know where these strings are located 7315 // and we can't read beyond them. Load them through stack. 7316 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 7317 7318 movptr(tmp, rsp); // save old SP 7319 7320 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 7321 if (int_cnt2 == (1>>scale2)) { // One byte 7322 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding"); 7323 load_unsigned_byte(result, Address(str2, 0)); 7324 movdl(vec, result); // move 32 bits 7325 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes 7326 // Not enough header space in 32-bit VM: 12+3 = 15. 7327 movl(result, Address(str2, -1)); 7328 shrl(result, 8); 7329 movdl(vec, result); // move 32 bits 7330 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char 7331 load_unsigned_short(result, Address(str2, 0)); 7332 movdl(vec, result); // move 32 bits 7333 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars 7334 movdl(vec, Address(str2, 0)); // move 32 bits 7335 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars 7336 movq(vec, Address(str2, 0)); // move 64 bits 7337 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7}) 7338 // Array header size is 12 bytes in 32-bit VM 7339 // + 6 bytes for 3 chars == 18 bytes, 7340 // enough space to load vec and shift. 7341 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 7342 if (ae == StrIntrinsicNode::UL) { 7343 int tail_off = int_cnt2-8; 7344 pmovzxbw(vec, Address(str2, tail_off)); 7345 psrldq(vec, -2*tail_off); 7346 } 7347 else { 7348 int tail_off = int_cnt2*(1<<scale2); 7349 movdqu(vec, Address(str2, tail_off-16)); 7350 psrldq(vec, 16-tail_off); 7351 } 7352 } 7353 } else { // not constant substring 7354 cmpl(cnt2, stride); 7355 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 7356 7357 // We can read beyond string if srt+16 does not cross page boundary 7358 // since heaps are aligned and mapped by pages. 7359 assert(os::vm_page_size() < (int)G, "default page should be small"); 7360 movl(result, str2); // We need only low 32 bits 7361 andl(result, (os::vm_page_size()-1)); 7362 cmpl(result, (os::vm_page_size()-16)); 7363 jccb(Assembler::belowEqual, CHECK_STR); 7364 7365 // Move small strings to stack to allow load 16 bytes into vec. 7366 subptr(rsp, 16); 7367 int stk_offset = wordSize-(1<<scale2); 7368 push(cnt2); 7369 7370 bind(COPY_SUBSTR); 7371 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) { 7372 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1)); 7373 movb(Address(rsp, cnt2, scale2, stk_offset), result); 7374 } else if (ae == StrIntrinsicNode::UU) { 7375 load_unsigned_short(result, Address(str2, cnt2, scale2, -2)); 7376 movw(Address(rsp, cnt2, scale2, stk_offset), result); 7377 } 7378 decrement(cnt2); 7379 jccb(Assembler::notZero, COPY_SUBSTR); 7380 7381 pop(cnt2); 7382 movptr(str2, rsp); // New substring address 7383 } // non constant 7384 7385 bind(CHECK_STR); 7386 cmpl(cnt1, stride); 7387 jccb(Assembler::aboveEqual, BIG_STRINGS); 7388 7389 // Check cross page boundary. 7390 movl(result, str1); // We need only low 32 bits 7391 andl(result, (os::vm_page_size()-1)); 7392 cmpl(result, (os::vm_page_size()-16)); 7393 jccb(Assembler::belowEqual, BIG_STRINGS); 7394 7395 subptr(rsp, 16); 7396 int stk_offset = -(1<<scale1); 7397 if (int_cnt2 < 0) { // not constant 7398 push(cnt2); 7399 stk_offset += wordSize; 7400 } 7401 movl(cnt2, cnt1); 7402 7403 bind(COPY_STR); 7404 if (ae == StrIntrinsicNode::LL) { 7405 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1)); 7406 movb(Address(rsp, cnt2, scale1, stk_offset), result); 7407 } else { 7408 load_unsigned_short(result, Address(str1, cnt2, scale1, -2)); 7409 movw(Address(rsp, cnt2, scale1, stk_offset), result); 7410 } 7411 decrement(cnt2); 7412 jccb(Assembler::notZero, COPY_STR); 7413 7414 if (int_cnt2 < 0) { // not constant 7415 pop(cnt2); 7416 } 7417 movptr(str1, rsp); // New string address 7418 7419 bind(BIG_STRINGS); 7420 // Load substring. 7421 if (int_cnt2 < 0) { // -1 7422 if (ae == StrIntrinsicNode::UL) { 7423 pmovzxbw(vec, Address(str2, 0)); 7424 } else { 7425 movdqu(vec, Address(str2, 0)); 7426 } 7427 push(cnt2); // substr count 7428 push(str2); // substr addr 7429 push(str1); // string addr 7430 } else { 7431 // Small (< 8 chars) constant substrings are loaded already. 7432 movl(cnt2, int_cnt2); 7433 } 7434 push(tmp); // original SP 7435 7436 } // Finished loading 7437 7438 //======================================================== 7439 // Start search 7440 // 7441 7442 movptr(result, str1); // string addr 7443 7444 if (int_cnt2 < 0) { // Only for non constant substring 7445 jmpb(SCAN_TO_SUBSTR); 7446 7447 // SP saved at sp+0 7448 // String saved at sp+1*wordSize 7449 // Substr saved at sp+2*wordSize 7450 // Substr count saved at sp+3*wordSize 7451 7452 // Reload substr for rescan, this code 7453 // is executed only for large substrings (> 8 chars) 7454 bind(RELOAD_SUBSTR); 7455 movptr(str2, Address(rsp, 2*wordSize)); 7456 movl(cnt2, Address(rsp, 3*wordSize)); 7457 if (ae == StrIntrinsicNode::UL) { 7458 pmovzxbw(vec, Address(str2, 0)); 7459 } else { 7460 movdqu(vec, Address(str2, 0)); 7461 } 7462 // We came here after the beginning of the substring was 7463 // matched but the rest of it was not so we need to search 7464 // again. Start from the next element after the previous match. 7465 subptr(str1, result); // Restore counter 7466 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7467 shrl(str1, 1); 7468 } 7469 addl(cnt1, str1); 7470 decrementl(cnt1); // Shift to next element 7471 cmpl(cnt1, cnt2); 7472 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7473 7474 addptr(result, (1<<scale1)); 7475 } // non constant 7476 7477 // Scan string for start of substr in 16-byte vectors 7478 bind(SCAN_TO_SUBSTR); 7479 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7480 pcmpestri(vec, Address(result, 0), mode); 7481 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7482 subl(cnt1, stride); 7483 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7484 cmpl(cnt1, cnt2); 7485 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7486 addptr(result, 16); 7487 7488 bind(ADJUST_STR); 7489 cmpl(cnt1, stride); // Do not read beyond string 7490 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7491 // Back-up string to avoid reading beyond string. 7492 lea(result, Address(result, cnt1, scale1, -16)); 7493 movl(cnt1, stride); 7494 jmpb(SCAN_TO_SUBSTR); 7495 7496 // Found a potential substr 7497 bind(FOUND_CANDIDATE); 7498 // After pcmpestri tmp(rcx) contains matched element index 7499 7500 // Make sure string is still long enough 7501 subl(cnt1, tmp); 7502 cmpl(cnt1, cnt2); 7503 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 7504 // Left less then substring. 7505 7506 bind(RET_NOT_FOUND); 7507 movl(result, -1); 7508 jmpb(CLEANUP); 7509 7510 bind(FOUND_SUBSTR); 7511 // Compute start addr of substr 7512 lea(result, Address(result, tmp, scale1)); 7513 if (int_cnt2 > 0) { // Constant substring 7514 // Repeat search for small substring (< 8 chars) 7515 // from new point without reloading substring. 7516 // Have to check that we don't read beyond string. 7517 cmpl(tmp, stride-int_cnt2); 7518 jccb(Assembler::greater, ADJUST_STR); 7519 // Fall through if matched whole substring. 7520 } else { // non constant 7521 assert(int_cnt2 == -1, "should be != 0"); 7522 7523 addl(tmp, cnt2); 7524 // Found result if we matched whole substring. 7525 cmpl(tmp, stride); 7526 jccb(Assembler::lessEqual, RET_FOUND); 7527 7528 // Repeat search for small substring (<= 8 chars) 7529 // from new point 'str1' without reloading substring. 7530 cmpl(cnt2, stride); 7531 // Have to check that we don't read beyond string. 7532 jccb(Assembler::lessEqual, ADJUST_STR); 7533 7534 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 7535 // Compare the rest of substring (> 8 chars). 7536 movptr(str1, result); 7537 7538 cmpl(tmp, cnt2); 7539 // First 8 chars are already matched. 7540 jccb(Assembler::equal, CHECK_NEXT); 7541 7542 bind(SCAN_SUBSTR); 7543 pcmpestri(vec, Address(str1, 0), mode); 7544 // Need to reload strings pointers if not matched whole vector 7545 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7546 7547 bind(CHECK_NEXT); 7548 subl(cnt2, stride); 7549 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 7550 addptr(str1, 16); 7551 if (ae == StrIntrinsicNode::UL) { 7552 addptr(str2, 8); 7553 } else { 7554 addptr(str2, 16); 7555 } 7556 subl(cnt1, stride); 7557 cmpl(cnt2, stride); // Do not read beyond substring 7558 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 7559 // Back-up strings to avoid reading beyond substring. 7560 7561 if (ae == StrIntrinsicNode::UL) { 7562 lea(str2, Address(str2, cnt2, scale2, -8)); 7563 lea(str1, Address(str1, cnt2, scale1, -16)); 7564 } else { 7565 lea(str2, Address(str2, cnt2, scale2, -16)); 7566 lea(str1, Address(str1, cnt2, scale1, -16)); 7567 } 7568 subl(cnt1, cnt2); 7569 movl(cnt2, stride); 7570 addl(cnt1, stride); 7571 bind(CONT_SCAN_SUBSTR); 7572 if (ae == StrIntrinsicNode::UL) { 7573 pmovzxbw(vec, Address(str2, 0)); 7574 } else { 7575 movdqu(vec, Address(str2, 0)); 7576 } 7577 jmp(SCAN_SUBSTR); 7578 7579 bind(RET_FOUND_LONG); 7580 movptr(str1, Address(rsp, wordSize)); 7581 } // non constant 7582 7583 bind(RET_FOUND); 7584 // Compute substr offset 7585 subptr(result, str1); 7586 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7587 shrl(result, 1); // index 7588 } 7589 bind(CLEANUP); 7590 pop(rsp); // restore SP 7591 7592 } // string_indexof 7593 7594 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 7595 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) { 7596 ShortBranchVerifier sbv(this); 7597 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7598 7599 int stride = 8; 7600 7601 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP, 7602 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP, 7603 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT, 7604 FOUND_SEQ_CHAR, DONE_LABEL; 7605 7606 movptr(result, str1); 7607 if (UseAVX >= 2) { 7608 cmpl(cnt1, stride); 7609 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7610 cmpl(cnt1, 2*stride); 7611 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT); 7612 movdl(vec1, ch); 7613 vpbroadcastw(vec1, vec1); 7614 vpxor(vec2, vec2); 7615 movl(tmp, cnt1); 7616 andl(tmp, 0xFFFFFFF0); //vector count (in chars) 7617 andl(cnt1,0x0000000F); //tail count (in chars) 7618 7619 bind(SCAN_TO_16_CHAR_LOOP); 7620 vmovdqu(vec3, Address(result, 0)); 7621 vpcmpeqw(vec3, vec3, vec1, 1); 7622 vptest(vec2, vec3); 7623 jcc(Assembler::carryClear, FOUND_CHAR); 7624 addptr(result, 32); 7625 subl(tmp, 2*stride); 7626 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP); 7627 jmp(SCAN_TO_8_CHAR); 7628 bind(SCAN_TO_8_CHAR_INIT); 7629 movdl(vec1, ch); 7630 pshuflw(vec1, vec1, 0x00); 7631 pshufd(vec1, vec1, 0); 7632 pxor(vec2, vec2); 7633 } 7634 bind(SCAN_TO_8_CHAR); 7635 cmpl(cnt1, stride); 7636 if (UseAVX >= 2) { 7637 jcc(Assembler::less, SCAN_TO_CHAR); 7638 } else { 7639 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7640 movdl(vec1, ch); 7641 pshuflw(vec1, vec1, 0x00); 7642 pshufd(vec1, vec1, 0); 7643 pxor(vec2, vec2); 7644 } 7645 movl(tmp, cnt1); 7646 andl(tmp, 0xFFFFFFF8); //vector count (in chars) 7647 andl(cnt1,0x00000007); //tail count (in chars) 7648 7649 bind(SCAN_TO_8_CHAR_LOOP); 7650 movdqu(vec3, Address(result, 0)); 7651 pcmpeqw(vec3, vec1); 7652 ptest(vec2, vec3); 7653 jcc(Assembler::carryClear, FOUND_CHAR); 7654 addptr(result, 16); 7655 subl(tmp, stride); 7656 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP); 7657 bind(SCAN_TO_CHAR); 7658 testl(cnt1, cnt1); 7659 jcc(Assembler::zero, RET_NOT_FOUND); 7660 bind(SCAN_TO_CHAR_LOOP); 7661 load_unsigned_short(tmp, Address(result, 0)); 7662 cmpl(ch, tmp); 7663 jccb(Assembler::equal, FOUND_SEQ_CHAR); 7664 addptr(result, 2); 7665 subl(cnt1, 1); 7666 jccb(Assembler::zero, RET_NOT_FOUND); 7667 jmp(SCAN_TO_CHAR_LOOP); 7668 7669 bind(RET_NOT_FOUND); 7670 movl(result, -1); 7671 jmpb(DONE_LABEL); 7672 7673 bind(FOUND_CHAR); 7674 if (UseAVX >= 2) { 7675 vpmovmskb(tmp, vec3); 7676 } else { 7677 pmovmskb(tmp, vec3); 7678 } 7679 bsfl(ch, tmp); 7680 addl(result, ch); 7681 7682 bind(FOUND_SEQ_CHAR); 7683 subptr(result, str1); 7684 shrl(result, 1); 7685 7686 bind(DONE_LABEL); 7687 } // string_indexof_char 7688 7689 // helper function for string_compare 7690 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 7691 Address::ScaleFactor scale, Address::ScaleFactor scale1, 7692 Address::ScaleFactor scale2, Register index, int ae) { 7693 if (ae == StrIntrinsicNode::LL) { 7694 load_unsigned_byte(elem1, Address(str1, index, scale, 0)); 7695 load_unsigned_byte(elem2, Address(str2, index, scale, 0)); 7696 } else if (ae == StrIntrinsicNode::UU) { 7697 load_unsigned_short(elem1, Address(str1, index, scale, 0)); 7698 load_unsigned_short(elem2, Address(str2, index, scale, 0)); 7699 } else { 7700 load_unsigned_byte(elem1, Address(str1, index, scale1, 0)); 7701 load_unsigned_short(elem2, Address(str2, index, scale2, 0)); 7702 } 7703 } 7704 7705 // Compare strings, used for char[] and byte[]. 7706 void MacroAssembler::string_compare(Register str1, Register str2, 7707 Register cnt1, Register cnt2, Register result, 7708 XMMRegister vec1, int ae) { 7709 ShortBranchVerifier sbv(this); 7710 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 7711 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3 7712 int stride, stride2, adr_stride, adr_stride1, adr_stride2; 7713 int stride2x2 = 0x40; 7714 Address::ScaleFactor scale = Address::no_scale; 7715 Address::ScaleFactor scale1 = Address::no_scale; 7716 Address::ScaleFactor scale2 = Address::no_scale; 7717 7718 if (ae != StrIntrinsicNode::LL) { 7719 stride2x2 = 0x20; 7720 } 7721 7722 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 7723 shrl(cnt2, 1); 7724 } 7725 // Compute the minimum of the string lengths and the 7726 // difference of the string lengths (stack). 7727 // Do the conditional move stuff 7728 movl(result, cnt1); 7729 subl(cnt1, cnt2); 7730 push(cnt1); 7731 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2) 7732 7733 // Is the minimum length zero? 7734 testl(cnt2, cnt2); 7735 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7736 if (ae == StrIntrinsicNode::LL) { 7737 // Load first bytes 7738 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0] 7739 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0] 7740 } else if (ae == StrIntrinsicNode::UU) { 7741 // Load first characters 7742 load_unsigned_short(result, Address(str1, 0)); 7743 load_unsigned_short(cnt1, Address(str2, 0)); 7744 } else { 7745 load_unsigned_byte(result, Address(str1, 0)); 7746 load_unsigned_short(cnt1, Address(str2, 0)); 7747 } 7748 subl(result, cnt1); 7749 jcc(Assembler::notZero, POP_LABEL); 7750 7751 if (ae == StrIntrinsicNode::UU) { 7752 // Divide length by 2 to get number of chars 7753 shrl(cnt2, 1); 7754 } 7755 cmpl(cnt2, 1); 7756 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7757 7758 // Check if the strings start at the same location and setup scale and stride 7759 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7760 cmpptr(str1, str2); 7761 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7762 if (ae == StrIntrinsicNode::LL) { 7763 scale = Address::times_1; 7764 stride = 16; 7765 } else { 7766 scale = Address::times_2; 7767 stride = 8; 7768 } 7769 } else { 7770 scale1 = Address::times_1; 7771 scale2 = Address::times_2; 7772 // scale not used 7773 stride = 8; 7774 } 7775 7776 if (UseAVX >= 2 && UseSSE42Intrinsics) { 7777 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 7778 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 7779 Label COMPARE_WIDE_VECTORS_LOOP_AVX2; 7780 Label COMPARE_TAIL_LONG; 7781 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3 7782 7783 int pcmpmask = 0x19; 7784 if (ae == StrIntrinsicNode::LL) { 7785 pcmpmask &= ~0x01; 7786 } 7787 7788 // Setup to compare 16-chars (32-bytes) vectors, 7789 // start from first character again because it has aligned address. 7790 if (ae == StrIntrinsicNode::LL) { 7791 stride2 = 32; 7792 } else { 7793 stride2 = 16; 7794 } 7795 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7796 adr_stride = stride << scale; 7797 } else { 7798 adr_stride1 = 8; //stride << scale1; 7799 adr_stride2 = 16; //stride << scale2; 7800 } 7801 7802 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7803 // rax and rdx are used by pcmpestri as elements counters 7804 movl(result, cnt2); 7805 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 7806 jcc(Assembler::zero, COMPARE_TAIL_LONG); 7807 7808 // fast path : compare first 2 8-char vectors. 7809 bind(COMPARE_16_CHARS); 7810 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7811 movdqu(vec1, Address(str1, 0)); 7812 } else { 7813 pmovzxbw(vec1, Address(str1, 0)); 7814 } 7815 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7816 jccb(Assembler::below, COMPARE_INDEX_CHAR); 7817 7818 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7819 movdqu(vec1, Address(str1, adr_stride)); 7820 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 7821 } else { 7822 pmovzxbw(vec1, Address(str1, adr_stride1)); 7823 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask); 7824 } 7825 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 7826 addl(cnt1, stride); 7827 7828 // Compare the characters at index in cnt1 7829 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character 7830 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7831 subl(result, cnt2); 7832 jmp(POP_LABEL); 7833 7834 // Setup the registers to start vector comparison loop 7835 bind(COMPARE_WIDE_VECTORS); 7836 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7837 lea(str1, Address(str1, result, scale)); 7838 lea(str2, Address(str2, result, scale)); 7839 } else { 7840 lea(str1, Address(str1, result, scale1)); 7841 lea(str2, Address(str2, result, scale2)); 7842 } 7843 subl(result, stride2); 7844 subl(cnt2, stride2); 7845 jcc(Assembler::zero, COMPARE_WIDE_TAIL); 7846 negptr(result); 7847 7848 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 7849 bind(COMPARE_WIDE_VECTORS_LOOP); 7850 7851 #ifdef _LP64 7852 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 7853 cmpl(cnt2, stride2x2); 7854 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); 7855 testl(cnt2, stride2x2-1); // cnt2 holds the vector count 7856 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40 7857 7858 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 7859 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7860 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit); 7861 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7862 } else { 7863 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit); 7864 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7865 } 7866 kortestql(k7, k7); 7867 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare 7868 addptr(result, stride2x2); // update since we already compared at this addr 7869 subl(cnt2, stride2x2); // and sub the size too 7870 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3); 7871 7872 vpxor(vec1, vec1); 7873 jmpb(COMPARE_WIDE_TAIL); 7874 }//if (VM_Version::supports_avx512vlbw()) 7875 #endif // _LP64 7876 7877 7878 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7879 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7880 vmovdqu(vec1, Address(str1, result, scale)); 7881 vpxor(vec1, Address(str2, result, scale)); 7882 } else { 7883 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit); 7884 vpxor(vec1, Address(str2, result, scale2)); 7885 } 7886 vptest(vec1, vec1); 7887 jcc(Assembler::notZero, VECTOR_NOT_EQUAL); 7888 addptr(result, stride2); 7889 subl(cnt2, stride2); 7890 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 7891 // clean upper bits of YMM registers 7892 vpxor(vec1, vec1); 7893 7894 // compare wide vectors tail 7895 bind(COMPARE_WIDE_TAIL); 7896 testptr(result, result); 7897 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7898 7899 movl(result, stride2); 7900 movl(cnt2, result); 7901 negptr(result); 7902 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7903 7904 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 7905 bind(VECTOR_NOT_EQUAL); 7906 // clean upper bits of YMM registers 7907 vpxor(vec1, vec1); 7908 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7909 lea(str1, Address(str1, result, scale)); 7910 lea(str2, Address(str2, result, scale)); 7911 } else { 7912 lea(str1, Address(str1, result, scale1)); 7913 lea(str2, Address(str2, result, scale2)); 7914 } 7915 jmp(COMPARE_16_CHARS); 7916 7917 // Compare tail chars, length between 1 to 15 chars 7918 bind(COMPARE_TAIL_LONG); 7919 movl(cnt2, result); 7920 cmpl(cnt2, stride); 7921 jcc(Assembler::less, COMPARE_SMALL_STR); 7922 7923 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7924 movdqu(vec1, Address(str1, 0)); 7925 } else { 7926 pmovzxbw(vec1, Address(str1, 0)); 7927 } 7928 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7929 jcc(Assembler::below, COMPARE_INDEX_CHAR); 7930 subptr(cnt2, stride); 7931 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7932 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7933 lea(str1, Address(str1, result, scale)); 7934 lea(str2, Address(str2, result, scale)); 7935 } else { 7936 lea(str1, Address(str1, result, scale1)); 7937 lea(str2, Address(str2, result, scale2)); 7938 } 7939 negptr(cnt2); 7940 jmpb(WHILE_HEAD_LABEL); 7941 7942 bind(COMPARE_SMALL_STR); 7943 } else if (UseSSE42Intrinsics) { 7944 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 7945 int pcmpmask = 0x19; 7946 // Setup to compare 8-char (16-byte) vectors, 7947 // start from first character again because it has aligned address. 7948 movl(result, cnt2); 7949 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 7950 if (ae == StrIntrinsicNode::LL) { 7951 pcmpmask &= ~0x01; 7952 } 7953 jcc(Assembler::zero, COMPARE_TAIL); 7954 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7955 lea(str1, Address(str1, result, scale)); 7956 lea(str2, Address(str2, result, scale)); 7957 } else { 7958 lea(str1, Address(str1, result, scale1)); 7959 lea(str2, Address(str2, result, scale2)); 7960 } 7961 negptr(result); 7962 7963 // pcmpestri 7964 // inputs: 7965 // vec1- substring 7966 // rax - negative string length (elements count) 7967 // mem - scanned string 7968 // rdx - string length (elements count) 7969 // pcmpmask - cmp mode: 11000 (string compare with negated result) 7970 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 7971 // outputs: 7972 // rcx - first mismatched element index 7973 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7974 7975 bind(COMPARE_WIDE_VECTORS); 7976 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7977 movdqu(vec1, Address(str1, result, scale)); 7978 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 7979 } else { 7980 pmovzxbw(vec1, Address(str1, result, scale1)); 7981 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 7982 } 7983 // After pcmpestri cnt1(rcx) contains mismatched element index 7984 7985 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 7986 addptr(result, stride); 7987 subptr(cnt2, stride); 7988 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 7989 7990 // compare wide vectors tail 7991 testptr(result, result); 7992 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7993 7994 movl(cnt2, stride); 7995 movl(result, stride); 7996 negptr(result); 7997 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7998 movdqu(vec1, Address(str1, result, scale)); 7999 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8000 } else { 8001 pmovzxbw(vec1, Address(str1, result, scale1)); 8002 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8003 } 8004 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 8005 8006 // Mismatched characters in the vectors 8007 bind(VECTOR_NOT_EQUAL); 8008 addptr(cnt1, result); 8009 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 8010 subl(result, cnt2); 8011 jmpb(POP_LABEL); 8012 8013 bind(COMPARE_TAIL); // limit is zero 8014 movl(cnt2, result); 8015 // Fallthru to tail compare 8016 } 8017 // Shift str2 and str1 to the end of the arrays, negate min 8018 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8019 lea(str1, Address(str1, cnt2, scale)); 8020 lea(str2, Address(str2, cnt2, scale)); 8021 } else { 8022 lea(str1, Address(str1, cnt2, scale1)); 8023 lea(str2, Address(str2, cnt2, scale2)); 8024 } 8025 decrementl(cnt2); // first character was compared already 8026 negptr(cnt2); 8027 8028 // Compare the rest of the elements 8029 bind(WHILE_HEAD_LABEL); 8030 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae); 8031 subl(result, cnt1); 8032 jccb(Assembler::notZero, POP_LABEL); 8033 increment(cnt2); 8034 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 8035 8036 // Strings are equal up to min length. Return the length difference. 8037 bind(LENGTH_DIFF_LABEL); 8038 pop(result); 8039 if (ae == StrIntrinsicNode::UU) { 8040 // Divide diff by 2 to get number of chars 8041 sarl(result, 1); 8042 } 8043 jmpb(DONE_LABEL); 8044 8045 #ifdef _LP64 8046 if (VM_Version::supports_avx512vlbw()) { 8047 8048 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED); 8049 8050 kmovql(cnt1, k7); 8051 notq(cnt1); 8052 bsfq(cnt2, cnt1); 8053 if (ae != StrIntrinsicNode::LL) { 8054 // Divide diff by 2 to get number of chars 8055 sarl(cnt2, 1); 8056 } 8057 addq(result, cnt2); 8058 if (ae == StrIntrinsicNode::LL) { 8059 load_unsigned_byte(cnt1, Address(str2, result)); 8060 load_unsigned_byte(result, Address(str1, result)); 8061 } else if (ae == StrIntrinsicNode::UU) { 8062 load_unsigned_short(cnt1, Address(str2, result, scale)); 8063 load_unsigned_short(result, Address(str1, result, scale)); 8064 } else { 8065 load_unsigned_short(cnt1, Address(str2, result, scale2)); 8066 load_unsigned_byte(result, Address(str1, result, scale1)); 8067 } 8068 subl(result, cnt1); 8069 jmpb(POP_LABEL); 8070 }//if (VM_Version::supports_avx512vlbw()) 8071 #endif // _LP64 8072 8073 // Discard the stored length difference 8074 bind(POP_LABEL); 8075 pop(cnt1); 8076 8077 // That's it 8078 bind(DONE_LABEL); 8079 if(ae == StrIntrinsicNode::UL) { 8080 negl(result); 8081 } 8082 8083 } 8084 8085 // Search for Non-ASCII character (Negative byte value) in a byte array, 8086 // return true if it has any and false otherwise. 8087 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java 8088 // @HotSpotIntrinsicCandidate 8089 // private static boolean hasNegatives(byte[] ba, int off, int len) { 8090 // for (int i = off; i < off + len; i++) { 8091 // if (ba[i] < 0) { 8092 // return true; 8093 // } 8094 // } 8095 // return false; 8096 // } 8097 void MacroAssembler::has_negatives(Register ary1, Register len, 8098 Register result, Register tmp1, 8099 XMMRegister vec1, XMMRegister vec2) { 8100 // rsi: byte array 8101 // rcx: len 8102 // rax: result 8103 ShortBranchVerifier sbv(this); 8104 assert_different_registers(ary1, len, result, tmp1); 8105 assert_different_registers(vec1, vec2); 8106 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE; 8107 8108 // len == 0 8109 testl(len, len); 8110 jcc(Assembler::zero, FALSE_LABEL); 8111 8112 if ((UseAVX > 2) && // AVX512 8113 VM_Version::supports_avx512vlbw() && 8114 VM_Version::supports_bmi2()) { 8115 8116 set_vector_masking(); // opening of the stub context for programming mask registers 8117 8118 Label test_64_loop, test_tail; 8119 Register tmp3_aliased = len; 8120 8121 movl(tmp1, len); 8122 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit); 8123 8124 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F 8125 andl(len, ~(64 - 1)); // vector count (in chars) 8126 jccb(Assembler::zero, test_tail); 8127 8128 lea(ary1, Address(ary1, len, Address::times_1)); 8129 negptr(len); 8130 8131 bind(test_64_loop); 8132 // Check whether our 64 elements of size byte contain negatives 8133 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit); 8134 kortestql(k2, k2); 8135 jcc(Assembler::notZero, TRUE_LABEL); 8136 8137 addptr(len, 64); 8138 jccb(Assembler::notZero, test_64_loop); 8139 8140 8141 bind(test_tail); 8142 // bail out when there is nothing to be done 8143 testl(tmp1, -1); 8144 jcc(Assembler::zero, FALSE_LABEL); 8145 8146 // Save k1 8147 kmovql(k3, k1); 8148 8149 // ~(~0 << len) applied up to two times (for 32-bit scenario) 8150 #ifdef _LP64 8151 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF); 8152 shlxq(tmp3_aliased, tmp3_aliased, tmp1); 8153 notq(tmp3_aliased); 8154 kmovql(k1, tmp3_aliased); 8155 #else 8156 Label k_init; 8157 jmp(k_init); 8158 8159 // We could not read 64-bits from a general purpose register thus we move 8160 // data required to compose 64 1's to the instruction stream 8161 // We emit 64 byte wide series of elements from 0..63 which later on would 8162 // be used as a compare targets with tail count contained in tmp1 register. 8163 // Result would be a k1 register having tmp1 consecutive number or 1 8164 // counting from least significant bit. 8165 address tmp = pc(); 8166 emit_int64(0x0706050403020100); 8167 emit_int64(0x0F0E0D0C0B0A0908); 8168 emit_int64(0x1716151413121110); 8169 emit_int64(0x1F1E1D1C1B1A1918); 8170 emit_int64(0x2726252423222120); 8171 emit_int64(0x2F2E2D2C2B2A2928); 8172 emit_int64(0x3736353433323130); 8173 emit_int64(0x3F3E3D3C3B3A3938); 8174 8175 bind(k_init); 8176 lea(len, InternalAddress(tmp)); 8177 // create mask to test for negative byte inside a vector 8178 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit); 8179 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit); 8180 8181 #endif 8182 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit); 8183 ktestq(k2, k1); 8184 // Restore k1 8185 kmovql(k1, k3); 8186 jcc(Assembler::notZero, TRUE_LABEL); 8187 8188 jmp(FALSE_LABEL); 8189 8190 clear_vector_masking(); // closing of the stub context for programming mask registers 8191 } else { 8192 movl(result, len); // copy 8193 8194 if (UseAVX == 2 && UseSSE >= 2) { 8195 // With AVX2, use 32-byte vector compare 8196 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8197 8198 // Compare 32-byte vectors 8199 andl(result, 0x0000001f); // tail count (in bytes) 8200 andl(len, 0xffffffe0); // vector count (in bytes) 8201 jccb(Assembler::zero, COMPARE_TAIL); 8202 8203 lea(ary1, Address(ary1, len, Address::times_1)); 8204 negptr(len); 8205 8206 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector 8207 movdl(vec2, tmp1); 8208 vpbroadcastd(vec2, vec2); 8209 8210 bind(COMPARE_WIDE_VECTORS); 8211 vmovdqu(vec1, Address(ary1, len, Address::times_1)); 8212 vptest(vec1, vec2); 8213 jccb(Assembler::notZero, TRUE_LABEL); 8214 addptr(len, 32); 8215 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8216 8217 testl(result, result); 8218 jccb(Assembler::zero, FALSE_LABEL); 8219 8220 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8221 vptest(vec1, vec2); 8222 jccb(Assembler::notZero, TRUE_LABEL); 8223 jmpb(FALSE_LABEL); 8224 8225 bind(COMPARE_TAIL); // len is zero 8226 movl(len, result); 8227 // Fallthru to tail compare 8228 } else if (UseSSE42Intrinsics) { 8229 // With SSE4.2, use double quad vector compare 8230 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8231 8232 // Compare 16-byte vectors 8233 andl(result, 0x0000000f); // tail count (in bytes) 8234 andl(len, 0xfffffff0); // vector count (in bytes) 8235 jccb(Assembler::zero, COMPARE_TAIL); 8236 8237 lea(ary1, Address(ary1, len, Address::times_1)); 8238 negptr(len); 8239 8240 movl(tmp1, 0x80808080); 8241 movdl(vec2, tmp1); 8242 pshufd(vec2, vec2, 0); 8243 8244 bind(COMPARE_WIDE_VECTORS); 8245 movdqu(vec1, Address(ary1, len, Address::times_1)); 8246 ptest(vec1, vec2); 8247 jccb(Assembler::notZero, TRUE_LABEL); 8248 addptr(len, 16); 8249 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8250 8251 testl(result, result); 8252 jccb(Assembler::zero, FALSE_LABEL); 8253 8254 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8255 ptest(vec1, vec2); 8256 jccb(Assembler::notZero, TRUE_LABEL); 8257 jmpb(FALSE_LABEL); 8258 8259 bind(COMPARE_TAIL); // len is zero 8260 movl(len, result); 8261 // Fallthru to tail compare 8262 } 8263 } 8264 // Compare 4-byte vectors 8265 andl(len, 0xfffffffc); // vector count (in bytes) 8266 jccb(Assembler::zero, COMPARE_CHAR); 8267 8268 lea(ary1, Address(ary1, len, Address::times_1)); 8269 negptr(len); 8270 8271 bind(COMPARE_VECTORS); 8272 movl(tmp1, Address(ary1, len, Address::times_1)); 8273 andl(tmp1, 0x80808080); 8274 jccb(Assembler::notZero, TRUE_LABEL); 8275 addptr(len, 4); 8276 jcc(Assembler::notZero, COMPARE_VECTORS); 8277 8278 // Compare trailing char (final 2 bytes), if any 8279 bind(COMPARE_CHAR); 8280 testl(result, 0x2); // tail char 8281 jccb(Assembler::zero, COMPARE_BYTE); 8282 load_unsigned_short(tmp1, Address(ary1, 0)); 8283 andl(tmp1, 0x00008080); 8284 jccb(Assembler::notZero, TRUE_LABEL); 8285 subptr(result, 2); 8286 lea(ary1, Address(ary1, 2)); 8287 8288 bind(COMPARE_BYTE); 8289 testl(result, 0x1); // tail byte 8290 jccb(Assembler::zero, FALSE_LABEL); 8291 load_unsigned_byte(tmp1, Address(ary1, 0)); 8292 andl(tmp1, 0x00000080); 8293 jccb(Assembler::notEqual, TRUE_LABEL); 8294 jmpb(FALSE_LABEL); 8295 8296 bind(TRUE_LABEL); 8297 movl(result, 1); // return true 8298 jmpb(DONE); 8299 8300 bind(FALSE_LABEL); 8301 xorl(result, result); // return false 8302 8303 // That's it 8304 bind(DONE); 8305 if (UseAVX >= 2 && UseSSE >= 2) { 8306 // clean upper bits of YMM registers 8307 vpxor(vec1, vec1); 8308 vpxor(vec2, vec2); 8309 } 8310 } 8311 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings. 8312 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2, 8313 Register limit, Register result, Register chr, 8314 XMMRegister vec1, XMMRegister vec2, bool is_char) { 8315 ShortBranchVerifier sbv(this); 8316 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE; 8317 8318 int length_offset = arrayOopDesc::length_offset_in_bytes(); 8319 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE); 8320 8321 if (is_array_equ) { 8322 // Check the input args 8323 cmpptr(ary1, ary2); 8324 jcc(Assembler::equal, TRUE_LABEL); 8325 8326 // Need additional checks for arrays_equals. 8327 testptr(ary1, ary1); 8328 jcc(Assembler::zero, FALSE_LABEL); 8329 testptr(ary2, ary2); 8330 jcc(Assembler::zero, FALSE_LABEL); 8331 8332 // Check the lengths 8333 movl(limit, Address(ary1, length_offset)); 8334 cmpl(limit, Address(ary2, length_offset)); 8335 jcc(Assembler::notEqual, FALSE_LABEL); 8336 } 8337 8338 // count == 0 8339 testl(limit, limit); 8340 jcc(Assembler::zero, TRUE_LABEL); 8341 8342 if (is_array_equ) { 8343 // Load array address 8344 lea(ary1, Address(ary1, base_offset)); 8345 lea(ary2, Address(ary2, base_offset)); 8346 } 8347 8348 if (is_array_equ && is_char) { 8349 // arrays_equals when used for char[]. 8350 shll(limit, 1); // byte count != 0 8351 } 8352 movl(result, limit); // copy 8353 8354 if (UseAVX >= 2) { 8355 // With AVX2, use 32-byte vector compare 8356 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8357 8358 // Compare 32-byte vectors 8359 andl(result, 0x0000001f); // tail count (in bytes) 8360 andl(limit, 0xffffffe0); // vector count (in bytes) 8361 jcc(Assembler::zero, COMPARE_TAIL); 8362 8363 lea(ary1, Address(ary1, limit, Address::times_1)); 8364 lea(ary2, Address(ary2, limit, Address::times_1)); 8365 negptr(limit); 8366 8367 bind(COMPARE_WIDE_VECTORS); 8368 8369 #ifdef _LP64 8370 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8371 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; 8372 8373 cmpl(limit, -64); 8374 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8375 8376 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8377 8378 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit); 8379 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit); 8380 kortestql(k7, k7); 8381 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8382 addptr(limit, 64); // update since we already compared at this addr 8383 cmpl(limit, -64); 8384 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8385 8386 // At this point we may still need to compare -limit+result bytes. 8387 // We could execute the next two instruction and just continue via non-wide path: 8388 // cmpl(limit, 0); 8389 // jcc(Assembler::equal, COMPARE_TAIL); // true 8390 // But since we stopped at the points ary{1,2}+limit which are 8391 // not farther than 64 bytes from the ends of arrays ary{1,2}+result 8392 // (|limit| <= 32 and result < 32), 8393 // we may just compare the last 64 bytes. 8394 // 8395 addptr(result, -64); // it is safe, bc we just came from this area 8396 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit); 8397 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit); 8398 kortestql(k7, k7); 8399 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8400 8401 jmp(TRUE_LABEL); 8402 8403 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8404 8405 }//if (VM_Version::supports_avx512vlbw()) 8406 #endif //_LP64 8407 8408 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 8409 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 8410 vpxor(vec1, vec2); 8411 8412 vptest(vec1, vec1); 8413 jcc(Assembler::notZero, FALSE_LABEL); 8414 addptr(limit, 32); 8415 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8416 8417 testl(result, result); 8418 jcc(Assembler::zero, TRUE_LABEL); 8419 8420 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8421 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 8422 vpxor(vec1, vec2); 8423 8424 vptest(vec1, vec1); 8425 jccb(Assembler::notZero, FALSE_LABEL); 8426 jmpb(TRUE_LABEL); 8427 8428 bind(COMPARE_TAIL); // limit is zero 8429 movl(limit, result); 8430 // Fallthru to tail compare 8431 } else if (UseSSE42Intrinsics) { 8432 // With SSE4.2, use double quad vector compare 8433 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8434 8435 // Compare 16-byte vectors 8436 andl(result, 0x0000000f); // tail count (in bytes) 8437 andl(limit, 0xfffffff0); // vector count (in bytes) 8438 jcc(Assembler::zero, COMPARE_TAIL); 8439 8440 lea(ary1, Address(ary1, limit, Address::times_1)); 8441 lea(ary2, Address(ary2, limit, Address::times_1)); 8442 negptr(limit); 8443 8444 bind(COMPARE_WIDE_VECTORS); 8445 movdqu(vec1, Address(ary1, limit, Address::times_1)); 8446 movdqu(vec2, Address(ary2, limit, Address::times_1)); 8447 pxor(vec1, vec2); 8448 8449 ptest(vec1, vec1); 8450 jcc(Assembler::notZero, FALSE_LABEL); 8451 addptr(limit, 16); 8452 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8453 8454 testl(result, result); 8455 jcc(Assembler::zero, TRUE_LABEL); 8456 8457 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8458 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 8459 pxor(vec1, vec2); 8460 8461 ptest(vec1, vec1); 8462 jccb(Assembler::notZero, FALSE_LABEL); 8463 jmpb(TRUE_LABEL); 8464 8465 bind(COMPARE_TAIL); // limit is zero 8466 movl(limit, result); 8467 // Fallthru to tail compare 8468 } 8469 8470 // Compare 4-byte vectors 8471 andl(limit, 0xfffffffc); // vector count (in bytes) 8472 jccb(Assembler::zero, COMPARE_CHAR); 8473 8474 lea(ary1, Address(ary1, limit, Address::times_1)); 8475 lea(ary2, Address(ary2, limit, Address::times_1)); 8476 negptr(limit); 8477 8478 bind(COMPARE_VECTORS); 8479 movl(chr, Address(ary1, limit, Address::times_1)); 8480 cmpl(chr, Address(ary2, limit, Address::times_1)); 8481 jccb(Assembler::notEqual, FALSE_LABEL); 8482 addptr(limit, 4); 8483 jcc(Assembler::notZero, COMPARE_VECTORS); 8484 8485 // Compare trailing char (final 2 bytes), if any 8486 bind(COMPARE_CHAR); 8487 testl(result, 0x2); // tail char 8488 jccb(Assembler::zero, COMPARE_BYTE); 8489 load_unsigned_short(chr, Address(ary1, 0)); 8490 load_unsigned_short(limit, Address(ary2, 0)); 8491 cmpl(chr, limit); 8492 jccb(Assembler::notEqual, FALSE_LABEL); 8493 8494 if (is_array_equ && is_char) { 8495 bind(COMPARE_BYTE); 8496 } else { 8497 lea(ary1, Address(ary1, 2)); 8498 lea(ary2, Address(ary2, 2)); 8499 8500 bind(COMPARE_BYTE); 8501 testl(result, 0x1); // tail byte 8502 jccb(Assembler::zero, TRUE_LABEL); 8503 load_unsigned_byte(chr, Address(ary1, 0)); 8504 load_unsigned_byte(limit, Address(ary2, 0)); 8505 cmpl(chr, limit); 8506 jccb(Assembler::notEqual, FALSE_LABEL); 8507 } 8508 bind(TRUE_LABEL); 8509 movl(result, 1); // return true 8510 jmpb(DONE); 8511 8512 bind(FALSE_LABEL); 8513 xorl(result, result); // return false 8514 8515 // That's it 8516 bind(DONE); 8517 if (UseAVX >= 2) { 8518 // clean upper bits of YMM registers 8519 vpxor(vec1, vec1); 8520 vpxor(vec2, vec2); 8521 } 8522 } 8523 8524 #endif 8525 8526 void MacroAssembler::generate_fill(BasicType t, bool aligned, 8527 Register to, Register value, Register count, 8528 Register rtmp, XMMRegister xtmp) { 8529 ShortBranchVerifier sbv(this); 8530 assert_different_registers(to, value, count, rtmp); 8531 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 8532 Label L_fill_2_bytes, L_fill_4_bytes; 8533 8534 int shift = -1; 8535 switch (t) { 8536 case T_BYTE: 8537 shift = 2; 8538 break; 8539 case T_SHORT: 8540 shift = 1; 8541 break; 8542 case T_INT: 8543 shift = 0; 8544 break; 8545 default: ShouldNotReachHere(); 8546 } 8547 8548 if (t == T_BYTE) { 8549 andl(value, 0xff); 8550 movl(rtmp, value); 8551 shll(rtmp, 8); 8552 orl(value, rtmp); 8553 } 8554 if (t == T_SHORT) { 8555 andl(value, 0xffff); 8556 } 8557 if (t == T_BYTE || t == T_SHORT) { 8558 movl(rtmp, value); 8559 shll(rtmp, 16); 8560 orl(value, rtmp); 8561 } 8562 8563 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 8564 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 8565 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 8566 // align source address at 4 bytes address boundary 8567 if (t == T_BYTE) { 8568 // One byte misalignment happens only for byte arrays 8569 testptr(to, 1); 8570 jccb(Assembler::zero, L_skip_align1); 8571 movb(Address(to, 0), value); 8572 increment(to); 8573 decrement(count); 8574 BIND(L_skip_align1); 8575 } 8576 // Two bytes misalignment happens only for byte and short (char) arrays 8577 testptr(to, 2); 8578 jccb(Assembler::zero, L_skip_align2); 8579 movw(Address(to, 0), value); 8580 addptr(to, 2); 8581 subl(count, 1<<(shift-1)); 8582 BIND(L_skip_align2); 8583 } 8584 if (UseSSE < 2) { 8585 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8586 // Fill 32-byte chunks 8587 subl(count, 8 << shift); 8588 jcc(Assembler::less, L_check_fill_8_bytes); 8589 align(16); 8590 8591 BIND(L_fill_32_bytes_loop); 8592 8593 for (int i = 0; i < 32; i += 4) { 8594 movl(Address(to, i), value); 8595 } 8596 8597 addptr(to, 32); 8598 subl(count, 8 << shift); 8599 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8600 BIND(L_check_fill_8_bytes); 8601 addl(count, 8 << shift); 8602 jccb(Assembler::zero, L_exit); 8603 jmpb(L_fill_8_bytes); 8604 8605 // 8606 // length is too short, just fill qwords 8607 // 8608 BIND(L_fill_8_bytes_loop); 8609 movl(Address(to, 0), value); 8610 movl(Address(to, 4), value); 8611 addptr(to, 8); 8612 BIND(L_fill_8_bytes); 8613 subl(count, 1 << (shift + 1)); 8614 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8615 // fall through to fill 4 bytes 8616 } else { 8617 Label L_fill_32_bytes; 8618 if (!UseUnalignedLoadStores) { 8619 // align to 8 bytes, we know we are 4 byte aligned to start 8620 testptr(to, 4); 8621 jccb(Assembler::zero, L_fill_32_bytes); 8622 movl(Address(to, 0), value); 8623 addptr(to, 4); 8624 subl(count, 1<<shift); 8625 } 8626 BIND(L_fill_32_bytes); 8627 { 8628 assert( UseSSE >= 2, "supported cpu only" ); 8629 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8630 if (UseAVX > 2) { 8631 movl(rtmp, 0xffff); 8632 kmovwl(k1, rtmp); 8633 } 8634 movdl(xtmp, value); 8635 if (UseAVX > 2 && UseUnalignedLoadStores) { 8636 // Fill 64-byte chunks 8637 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8638 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 8639 8640 subl(count, 16 << shift); 8641 jcc(Assembler::less, L_check_fill_32_bytes); 8642 align(16); 8643 8644 BIND(L_fill_64_bytes_loop); 8645 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 8646 addptr(to, 64); 8647 subl(count, 16 << shift); 8648 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8649 8650 BIND(L_check_fill_32_bytes); 8651 addl(count, 8 << shift); 8652 jccb(Assembler::less, L_check_fill_8_bytes); 8653 vmovdqu(Address(to, 0), xtmp); 8654 addptr(to, 32); 8655 subl(count, 8 << shift); 8656 8657 BIND(L_check_fill_8_bytes); 8658 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 8659 // Fill 64-byte chunks 8660 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8661 vpbroadcastd(xtmp, xtmp); 8662 8663 subl(count, 16 << shift); 8664 jcc(Assembler::less, L_check_fill_32_bytes); 8665 align(16); 8666 8667 BIND(L_fill_64_bytes_loop); 8668 vmovdqu(Address(to, 0), xtmp); 8669 vmovdqu(Address(to, 32), xtmp); 8670 addptr(to, 64); 8671 subl(count, 16 << shift); 8672 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8673 8674 BIND(L_check_fill_32_bytes); 8675 addl(count, 8 << shift); 8676 jccb(Assembler::less, L_check_fill_8_bytes); 8677 vmovdqu(Address(to, 0), xtmp); 8678 addptr(to, 32); 8679 subl(count, 8 << shift); 8680 8681 BIND(L_check_fill_8_bytes); 8682 // clean upper bits of YMM registers 8683 movdl(xtmp, value); 8684 pshufd(xtmp, xtmp, 0); 8685 } else { 8686 // Fill 32-byte chunks 8687 pshufd(xtmp, xtmp, 0); 8688 8689 subl(count, 8 << shift); 8690 jcc(Assembler::less, L_check_fill_8_bytes); 8691 align(16); 8692 8693 BIND(L_fill_32_bytes_loop); 8694 8695 if (UseUnalignedLoadStores) { 8696 movdqu(Address(to, 0), xtmp); 8697 movdqu(Address(to, 16), xtmp); 8698 } else { 8699 movq(Address(to, 0), xtmp); 8700 movq(Address(to, 8), xtmp); 8701 movq(Address(to, 16), xtmp); 8702 movq(Address(to, 24), xtmp); 8703 } 8704 8705 addptr(to, 32); 8706 subl(count, 8 << shift); 8707 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8708 8709 BIND(L_check_fill_8_bytes); 8710 } 8711 addl(count, 8 << shift); 8712 jccb(Assembler::zero, L_exit); 8713 jmpb(L_fill_8_bytes); 8714 8715 // 8716 // length is too short, just fill qwords 8717 // 8718 BIND(L_fill_8_bytes_loop); 8719 movq(Address(to, 0), xtmp); 8720 addptr(to, 8); 8721 BIND(L_fill_8_bytes); 8722 subl(count, 1 << (shift + 1)); 8723 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8724 } 8725 } 8726 // fill trailing 4 bytes 8727 BIND(L_fill_4_bytes); 8728 testl(count, 1<<shift); 8729 jccb(Assembler::zero, L_fill_2_bytes); 8730 movl(Address(to, 0), value); 8731 if (t == T_BYTE || t == T_SHORT) { 8732 addptr(to, 4); 8733 BIND(L_fill_2_bytes); 8734 // fill trailing 2 bytes 8735 testl(count, 1<<(shift-1)); 8736 jccb(Assembler::zero, L_fill_byte); 8737 movw(Address(to, 0), value); 8738 if (t == T_BYTE) { 8739 addptr(to, 2); 8740 BIND(L_fill_byte); 8741 // fill trailing byte 8742 testl(count, 1); 8743 jccb(Assembler::zero, L_exit); 8744 movb(Address(to, 0), value); 8745 } else { 8746 BIND(L_fill_byte); 8747 } 8748 } else { 8749 BIND(L_fill_2_bytes); 8750 } 8751 BIND(L_exit); 8752 } 8753 8754 // encode char[] to byte[] in ISO_8859_1 8755 //@HotSpotIntrinsicCandidate 8756 //private static int implEncodeISOArray(byte[] sa, int sp, 8757 //byte[] da, int dp, int len) { 8758 // int i = 0; 8759 // for (; i < len; i++) { 8760 // char c = StringUTF16.getChar(sa, sp++); 8761 // if (c > '\u00FF') 8762 // break; 8763 // da[dp++] = (byte)c; 8764 // } 8765 // return i; 8766 //} 8767 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 8768 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8769 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8770 Register tmp5, Register result) { 8771 8772 // rsi: src 8773 // rdi: dst 8774 // rdx: len 8775 // rcx: tmp5 8776 // rax: result 8777 ShortBranchVerifier sbv(this); 8778 assert_different_registers(src, dst, len, tmp5, result); 8779 Label L_done, L_copy_1_char, L_copy_1_char_exit; 8780 8781 // set result 8782 xorl(result, result); 8783 // check for zero length 8784 testl(len, len); 8785 jcc(Assembler::zero, L_done); 8786 8787 movl(result, len); 8788 8789 // Setup pointers 8790 lea(src, Address(src, len, Address::times_2)); // char[] 8791 lea(dst, Address(dst, len, Address::times_1)); // byte[] 8792 negptr(len); 8793 8794 if (UseSSE42Intrinsics || UseAVX >= 2) { 8795 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 8796 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 8797 8798 if (UseAVX >= 2) { 8799 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 8800 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8801 movdl(tmp1Reg, tmp5); 8802 vpbroadcastd(tmp1Reg, tmp1Reg); 8803 jmp(L_chars_32_check); 8804 8805 bind(L_copy_32_chars); 8806 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 8807 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 8808 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8809 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8810 jccb(Assembler::notZero, L_copy_32_chars_exit); 8811 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8812 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 8813 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 8814 8815 bind(L_chars_32_check); 8816 addptr(len, 32); 8817 jcc(Assembler::lessEqual, L_copy_32_chars); 8818 8819 bind(L_copy_32_chars_exit); 8820 subptr(len, 16); 8821 jccb(Assembler::greater, L_copy_16_chars_exit); 8822 8823 } else if (UseSSE42Intrinsics) { 8824 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8825 movdl(tmp1Reg, tmp5); 8826 pshufd(tmp1Reg, tmp1Reg, 0); 8827 jmpb(L_chars_16_check); 8828 } 8829 8830 bind(L_copy_16_chars); 8831 if (UseAVX >= 2) { 8832 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 8833 vptest(tmp2Reg, tmp1Reg); 8834 jcc(Assembler::notZero, L_copy_16_chars_exit); 8835 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 8836 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 8837 } else { 8838 if (UseAVX > 0) { 8839 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8840 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8841 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 8842 } else { 8843 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8844 por(tmp2Reg, tmp3Reg); 8845 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8846 por(tmp2Reg, tmp4Reg); 8847 } 8848 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8849 jccb(Assembler::notZero, L_copy_16_chars_exit); 8850 packuswb(tmp3Reg, tmp4Reg); 8851 } 8852 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 8853 8854 bind(L_chars_16_check); 8855 addptr(len, 16); 8856 jcc(Assembler::lessEqual, L_copy_16_chars); 8857 8858 bind(L_copy_16_chars_exit); 8859 if (UseAVX >= 2) { 8860 // clean upper bits of YMM registers 8861 vpxor(tmp2Reg, tmp2Reg); 8862 vpxor(tmp3Reg, tmp3Reg); 8863 vpxor(tmp4Reg, tmp4Reg); 8864 movdl(tmp1Reg, tmp5); 8865 pshufd(tmp1Reg, tmp1Reg, 0); 8866 } 8867 subptr(len, 8); 8868 jccb(Assembler::greater, L_copy_8_chars_exit); 8869 8870 bind(L_copy_8_chars); 8871 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 8872 ptest(tmp3Reg, tmp1Reg); 8873 jccb(Assembler::notZero, L_copy_8_chars_exit); 8874 packuswb(tmp3Reg, tmp1Reg); 8875 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 8876 addptr(len, 8); 8877 jccb(Assembler::lessEqual, L_copy_8_chars); 8878 8879 bind(L_copy_8_chars_exit); 8880 subptr(len, 8); 8881 jccb(Assembler::zero, L_done); 8882 } 8883 8884 bind(L_copy_1_char); 8885 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 8886 testl(tmp5, 0xff00); // check if Unicode char 8887 jccb(Assembler::notZero, L_copy_1_char_exit); 8888 movb(Address(dst, len, Address::times_1, 0), tmp5); 8889 addptr(len, 1); 8890 jccb(Assembler::less, L_copy_1_char); 8891 8892 bind(L_copy_1_char_exit); 8893 addptr(result, len); // len is negative count of not processed elements 8894 8895 bind(L_done); 8896 } 8897 8898 #ifdef _LP64 8899 /** 8900 * Helper for multiply_to_len(). 8901 */ 8902 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 8903 addq(dest_lo, src1); 8904 adcq(dest_hi, 0); 8905 addq(dest_lo, src2); 8906 adcq(dest_hi, 0); 8907 } 8908 8909 /** 8910 * Multiply 64 bit by 64 bit first loop. 8911 */ 8912 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 8913 Register y, Register y_idx, Register z, 8914 Register carry, Register product, 8915 Register idx, Register kdx) { 8916 // 8917 // jlong carry, x[], y[], z[]; 8918 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 8919 // huge_128 product = y[idx] * x[xstart] + carry; 8920 // z[kdx] = (jlong)product; 8921 // carry = (jlong)(product >>> 64); 8922 // } 8923 // z[xstart] = carry; 8924 // 8925 8926 Label L_first_loop, L_first_loop_exit; 8927 Label L_one_x, L_one_y, L_multiply; 8928 8929 decrementl(xstart); 8930 jcc(Assembler::negative, L_one_x); 8931 8932 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 8933 rorq(x_xstart, 32); // convert big-endian to little-endian 8934 8935 bind(L_first_loop); 8936 decrementl(idx); 8937 jcc(Assembler::negative, L_first_loop_exit); 8938 decrementl(idx); 8939 jcc(Assembler::negative, L_one_y); 8940 movq(y_idx, Address(y, idx, Address::times_4, 0)); 8941 rorq(y_idx, 32); // convert big-endian to little-endian 8942 bind(L_multiply); 8943 movq(product, x_xstart); 8944 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 8945 addq(product, carry); 8946 adcq(rdx, 0); 8947 subl(kdx, 2); 8948 movl(Address(z, kdx, Address::times_4, 4), product); 8949 shrq(product, 32); 8950 movl(Address(z, kdx, Address::times_4, 0), product); 8951 movq(carry, rdx); 8952 jmp(L_first_loop); 8953 8954 bind(L_one_y); 8955 movl(y_idx, Address(y, 0)); 8956 jmp(L_multiply); 8957 8958 bind(L_one_x); 8959 movl(x_xstart, Address(x, 0)); 8960 jmp(L_first_loop); 8961 8962 bind(L_first_loop_exit); 8963 } 8964 8965 /** 8966 * Multiply 64 bit by 64 bit and add 128 bit. 8967 */ 8968 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 8969 Register yz_idx, Register idx, 8970 Register carry, Register product, int offset) { 8971 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 8972 // z[kdx] = (jlong)product; 8973 8974 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 8975 rorq(yz_idx, 32); // convert big-endian to little-endian 8976 movq(product, x_xstart); 8977 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 8978 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 8979 rorq(yz_idx, 32); // convert big-endian to little-endian 8980 8981 add2_with_carry(rdx, product, carry, yz_idx); 8982 8983 movl(Address(z, idx, Address::times_4, offset+4), product); 8984 shrq(product, 32); 8985 movl(Address(z, idx, Address::times_4, offset), product); 8986 8987 } 8988 8989 /** 8990 * Multiply 128 bit by 128 bit. Unrolled inner loop. 8991 */ 8992 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 8993 Register yz_idx, Register idx, Register jdx, 8994 Register carry, Register product, 8995 Register carry2) { 8996 // jlong carry, x[], y[], z[]; 8997 // int kdx = ystart+1; 8998 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 8999 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 9000 // z[kdx+idx+1] = (jlong)product; 9001 // jlong carry2 = (jlong)(product >>> 64); 9002 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 9003 // z[kdx+idx] = (jlong)product; 9004 // carry = (jlong)(product >>> 64); 9005 // } 9006 // idx += 2; 9007 // if (idx > 0) { 9008 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 9009 // z[kdx+idx] = (jlong)product; 9010 // carry = (jlong)(product >>> 64); 9011 // } 9012 // 9013 9014 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9015 9016 movl(jdx, idx); 9017 andl(jdx, 0xFFFFFFFC); 9018 shrl(jdx, 2); 9019 9020 bind(L_third_loop); 9021 subl(jdx, 1); 9022 jcc(Assembler::negative, L_third_loop_exit); 9023 subl(idx, 4); 9024 9025 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 9026 movq(carry2, rdx); 9027 9028 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 9029 movq(carry, rdx); 9030 jmp(L_third_loop); 9031 9032 bind (L_third_loop_exit); 9033 9034 andl (idx, 0x3); 9035 jcc(Assembler::zero, L_post_third_loop_done); 9036 9037 Label L_check_1; 9038 subl(idx, 2); 9039 jcc(Assembler::negative, L_check_1); 9040 9041 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 9042 movq(carry, rdx); 9043 9044 bind (L_check_1); 9045 addl (idx, 0x2); 9046 andl (idx, 0x1); 9047 subl(idx, 1); 9048 jcc(Assembler::negative, L_post_third_loop_done); 9049 9050 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 9051 movq(product, x_xstart); 9052 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9053 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 9054 9055 add2_with_carry(rdx, product, yz_idx, carry); 9056 9057 movl(Address(z, idx, Address::times_4, 0), product); 9058 shrq(product, 32); 9059 9060 shlq(rdx, 32); 9061 orq(product, rdx); 9062 movq(carry, product); 9063 9064 bind(L_post_third_loop_done); 9065 } 9066 9067 /** 9068 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 9069 * 9070 */ 9071 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 9072 Register carry, Register carry2, 9073 Register idx, Register jdx, 9074 Register yz_idx1, Register yz_idx2, 9075 Register tmp, Register tmp3, Register tmp4) { 9076 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 9077 9078 // jlong carry, x[], y[], z[]; 9079 // int kdx = ystart+1; 9080 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9081 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 9082 // jlong carry2 = (jlong)(tmp3 >>> 64); 9083 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 9084 // carry = (jlong)(tmp4 >>> 64); 9085 // z[kdx+idx+1] = (jlong)tmp3; 9086 // z[kdx+idx] = (jlong)tmp4; 9087 // } 9088 // idx += 2; 9089 // if (idx > 0) { 9090 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 9091 // z[kdx+idx] = (jlong)yz_idx1; 9092 // carry = (jlong)(yz_idx1 >>> 64); 9093 // } 9094 // 9095 9096 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9097 9098 movl(jdx, idx); 9099 andl(jdx, 0xFFFFFFFC); 9100 shrl(jdx, 2); 9101 9102 bind(L_third_loop); 9103 subl(jdx, 1); 9104 jcc(Assembler::negative, L_third_loop_exit); 9105 subl(idx, 4); 9106 9107 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 9108 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 9109 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 9110 rorxq(yz_idx2, yz_idx2, 32); 9111 9112 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9113 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 9114 9115 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 9116 rorxq(yz_idx1, yz_idx1, 32); 9117 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9118 rorxq(yz_idx2, yz_idx2, 32); 9119 9120 if (VM_Version::supports_adx()) { 9121 adcxq(tmp3, carry); 9122 adoxq(tmp3, yz_idx1); 9123 9124 adcxq(tmp4, tmp); 9125 adoxq(tmp4, yz_idx2); 9126 9127 movl(carry, 0); // does not affect flags 9128 adcxq(carry2, carry); 9129 adoxq(carry2, carry); 9130 } else { 9131 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 9132 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 9133 } 9134 movq(carry, carry2); 9135 9136 movl(Address(z, idx, Address::times_4, 12), tmp3); 9137 shrq(tmp3, 32); 9138 movl(Address(z, idx, Address::times_4, 8), tmp3); 9139 9140 movl(Address(z, idx, Address::times_4, 4), tmp4); 9141 shrq(tmp4, 32); 9142 movl(Address(z, idx, Address::times_4, 0), tmp4); 9143 9144 jmp(L_third_loop); 9145 9146 bind (L_third_loop_exit); 9147 9148 andl (idx, 0x3); 9149 jcc(Assembler::zero, L_post_third_loop_done); 9150 9151 Label L_check_1; 9152 subl(idx, 2); 9153 jcc(Assembler::negative, L_check_1); 9154 9155 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 9156 rorxq(yz_idx1, yz_idx1, 32); 9157 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9158 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9159 rorxq(yz_idx2, yz_idx2, 32); 9160 9161 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 9162 9163 movl(Address(z, idx, Address::times_4, 4), tmp3); 9164 shrq(tmp3, 32); 9165 movl(Address(z, idx, Address::times_4, 0), tmp3); 9166 movq(carry, tmp4); 9167 9168 bind (L_check_1); 9169 addl (idx, 0x2); 9170 andl (idx, 0x1); 9171 subl(idx, 1); 9172 jcc(Assembler::negative, L_post_third_loop_done); 9173 movl(tmp4, Address(y, idx, Address::times_4, 0)); 9174 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 9175 movl(tmp4, Address(z, idx, Address::times_4, 0)); 9176 9177 add2_with_carry(carry2, tmp3, tmp4, carry); 9178 9179 movl(Address(z, idx, Address::times_4, 0), tmp3); 9180 shrq(tmp3, 32); 9181 9182 shlq(carry2, 32); 9183 orq(tmp3, carry2); 9184 movq(carry, tmp3); 9185 9186 bind(L_post_third_loop_done); 9187 } 9188 9189 /** 9190 * Code for BigInteger::multiplyToLen() instrinsic. 9191 * 9192 * rdi: x 9193 * rax: xlen 9194 * rsi: y 9195 * rcx: ylen 9196 * r8: z 9197 * r11: zlen 9198 * r12: tmp1 9199 * r13: tmp2 9200 * r14: tmp3 9201 * r15: tmp4 9202 * rbx: tmp5 9203 * 9204 */ 9205 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 9206 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 9207 ShortBranchVerifier sbv(this); 9208 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 9209 9210 push(tmp1); 9211 push(tmp2); 9212 push(tmp3); 9213 push(tmp4); 9214 push(tmp5); 9215 9216 push(xlen); 9217 push(zlen); 9218 9219 const Register idx = tmp1; 9220 const Register kdx = tmp2; 9221 const Register xstart = tmp3; 9222 9223 const Register y_idx = tmp4; 9224 const Register carry = tmp5; 9225 const Register product = xlen; 9226 const Register x_xstart = zlen; // reuse register 9227 9228 // First Loop. 9229 // 9230 // final static long LONG_MASK = 0xffffffffL; 9231 // int xstart = xlen - 1; 9232 // int ystart = ylen - 1; 9233 // long carry = 0; 9234 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9235 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 9236 // z[kdx] = (int)product; 9237 // carry = product >>> 32; 9238 // } 9239 // z[xstart] = (int)carry; 9240 // 9241 9242 movl(idx, ylen); // idx = ylen; 9243 movl(kdx, zlen); // kdx = xlen+ylen; 9244 xorq(carry, carry); // carry = 0; 9245 9246 Label L_done; 9247 9248 movl(xstart, xlen); 9249 decrementl(xstart); 9250 jcc(Assembler::negative, L_done); 9251 9252 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 9253 9254 Label L_second_loop; 9255 testl(kdx, kdx); 9256 jcc(Assembler::zero, L_second_loop); 9257 9258 Label L_carry; 9259 subl(kdx, 1); 9260 jcc(Assembler::zero, L_carry); 9261 9262 movl(Address(z, kdx, Address::times_4, 0), carry); 9263 shrq(carry, 32); 9264 subl(kdx, 1); 9265 9266 bind(L_carry); 9267 movl(Address(z, kdx, Address::times_4, 0), carry); 9268 9269 // Second and third (nested) loops. 9270 // 9271 // for (int i = xstart-1; i >= 0; i--) { // Second loop 9272 // carry = 0; 9273 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 9274 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 9275 // (z[k] & LONG_MASK) + carry; 9276 // z[k] = (int)product; 9277 // carry = product >>> 32; 9278 // } 9279 // z[i] = (int)carry; 9280 // } 9281 // 9282 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 9283 9284 const Register jdx = tmp1; 9285 9286 bind(L_second_loop); 9287 xorl(carry, carry); // carry = 0; 9288 movl(jdx, ylen); // j = ystart+1 9289 9290 subl(xstart, 1); // i = xstart-1; 9291 jcc(Assembler::negative, L_done); 9292 9293 push (z); 9294 9295 Label L_last_x; 9296 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 9297 subl(xstart, 1); // i = xstart-1; 9298 jcc(Assembler::negative, L_last_x); 9299 9300 if (UseBMI2Instructions) { 9301 movq(rdx, Address(x, xstart, Address::times_4, 0)); 9302 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 9303 } else { 9304 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9305 rorq(x_xstart, 32); // convert big-endian to little-endian 9306 } 9307 9308 Label L_third_loop_prologue; 9309 bind(L_third_loop_prologue); 9310 9311 push (x); 9312 push (xstart); 9313 push (ylen); 9314 9315 9316 if (UseBMI2Instructions) { 9317 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 9318 } else { // !UseBMI2Instructions 9319 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 9320 } 9321 9322 pop(ylen); 9323 pop(xlen); 9324 pop(x); 9325 pop(z); 9326 9327 movl(tmp3, xlen); 9328 addl(tmp3, 1); 9329 movl(Address(z, tmp3, Address::times_4, 0), carry); 9330 subl(tmp3, 1); 9331 jccb(Assembler::negative, L_done); 9332 9333 shrq(carry, 32); 9334 movl(Address(z, tmp3, Address::times_4, 0), carry); 9335 jmp(L_second_loop); 9336 9337 // Next infrequent code is moved outside loops. 9338 bind(L_last_x); 9339 if (UseBMI2Instructions) { 9340 movl(rdx, Address(x, 0)); 9341 } else { 9342 movl(x_xstart, Address(x, 0)); 9343 } 9344 jmp(L_third_loop_prologue); 9345 9346 bind(L_done); 9347 9348 pop(zlen); 9349 pop(xlen); 9350 9351 pop(tmp5); 9352 pop(tmp4); 9353 pop(tmp3); 9354 pop(tmp2); 9355 pop(tmp1); 9356 } 9357 9358 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 9359 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 9360 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 9361 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 9362 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 9363 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL; 9364 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 9365 Label SAME_TILL_END, DONE; 9366 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 9367 9368 //scale is in rcx in both Win64 and Unix 9369 ShortBranchVerifier sbv(this); 9370 9371 shlq(length); 9372 xorq(result, result); 9373 9374 if ((UseAVX > 2) && 9375 VM_Version::supports_avx512vlbw()) { 9376 set_vector_masking(); // opening of the stub context for programming mask registers 9377 cmpq(length, 64); 9378 jcc(Assembler::less, VECTOR32_TAIL); 9379 movq(tmp1, length); 9380 andq(tmp1, 0x3F); // tail count 9381 andq(length, ~(0x3F)); //vector count 9382 9383 bind(VECTOR64_LOOP); 9384 // AVX512 code to compare 64 byte vectors. 9385 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit); 9386 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 9387 kortestql(k7, k7); 9388 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 9389 addq(result, 64); 9390 subq(length, 64); 9391 jccb(Assembler::notZero, VECTOR64_LOOP); 9392 9393 //bind(VECTOR64_TAIL); 9394 testq(tmp1, tmp1); 9395 jcc(Assembler::zero, SAME_TILL_END); 9396 9397 bind(VECTOR64_TAIL); 9398 // AVX512 code to compare upto 63 byte vectors. 9399 // Save k1 9400 kmovql(k3, k1); 9401 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 9402 shlxq(tmp2, tmp2, tmp1); 9403 notq(tmp2); 9404 kmovql(k1, tmp2); 9405 9406 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit); 9407 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit); 9408 9409 ktestql(k7, k1); 9410 // Restore k1 9411 kmovql(k1, k3); 9412 jcc(Assembler::below, SAME_TILL_END); // not mismatch 9413 9414 bind(VECTOR64_NOT_EQUAL); 9415 kmovql(tmp1, k7); 9416 notq(tmp1); 9417 tzcntq(tmp1, tmp1); 9418 addq(result, tmp1); 9419 shrq(result); 9420 jmp(DONE); 9421 bind(VECTOR32_TAIL); 9422 clear_vector_masking(); // closing of the stub context for programming mask registers 9423 } 9424 9425 cmpq(length, 8); 9426 jcc(Assembler::equal, VECTOR8_LOOP); 9427 jcc(Assembler::less, VECTOR4_TAIL); 9428 9429 if (UseAVX >= 2) { 9430 9431 cmpq(length, 16); 9432 jcc(Assembler::equal, VECTOR16_LOOP); 9433 jcc(Assembler::less, VECTOR8_LOOP); 9434 9435 cmpq(length, 32); 9436 jccb(Assembler::less, VECTOR16_TAIL); 9437 9438 subq(length, 32); 9439 bind(VECTOR32_LOOP); 9440 vmovdqu(rymm0, Address(obja, result)); 9441 vmovdqu(rymm1, Address(objb, result)); 9442 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 9443 vptest(rymm2, rymm2); 9444 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 9445 addq(result, 32); 9446 subq(length, 32); 9447 jccb(Assembler::greaterEqual, VECTOR32_LOOP); 9448 addq(length, 32); 9449 jcc(Assembler::equal, SAME_TILL_END); 9450 //falling through if less than 32 bytes left //close the branch here. 9451 9452 bind(VECTOR16_TAIL); 9453 cmpq(length, 16); 9454 jccb(Assembler::less, VECTOR8_TAIL); 9455 bind(VECTOR16_LOOP); 9456 movdqu(rymm0, Address(obja, result)); 9457 movdqu(rymm1, Address(objb, result)); 9458 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 9459 ptest(rymm2, rymm2); 9460 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9461 addq(result, 16); 9462 subq(length, 16); 9463 jcc(Assembler::equal, SAME_TILL_END); 9464 //falling through if less than 16 bytes left 9465 } else {//regular intrinsics 9466 9467 cmpq(length, 16); 9468 jccb(Assembler::less, VECTOR8_TAIL); 9469 9470 subq(length, 16); 9471 bind(VECTOR16_LOOP); 9472 movdqu(rymm0, Address(obja, result)); 9473 movdqu(rymm1, Address(objb, result)); 9474 pxor(rymm0, rymm1); 9475 ptest(rymm0, rymm0); 9476 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9477 addq(result, 16); 9478 subq(length, 16); 9479 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 9480 addq(length, 16); 9481 jcc(Assembler::equal, SAME_TILL_END); 9482 //falling through if less than 16 bytes left 9483 } 9484 9485 bind(VECTOR8_TAIL); 9486 cmpq(length, 8); 9487 jccb(Assembler::less, VECTOR4_TAIL); 9488 bind(VECTOR8_LOOP); 9489 movq(tmp1, Address(obja, result)); 9490 movq(tmp2, Address(objb, result)); 9491 xorq(tmp1, tmp2); 9492 testq(tmp1, tmp1); 9493 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 9494 addq(result, 8); 9495 subq(length, 8); 9496 jcc(Assembler::equal, SAME_TILL_END); 9497 //falling through if less than 8 bytes left 9498 9499 bind(VECTOR4_TAIL); 9500 cmpq(length, 4); 9501 jccb(Assembler::less, BYTES_TAIL); 9502 bind(VECTOR4_LOOP); 9503 movl(tmp1, Address(obja, result)); 9504 xorl(tmp1, Address(objb, result)); 9505 testl(tmp1, tmp1); 9506 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 9507 addq(result, 4); 9508 subq(length, 4); 9509 jcc(Assembler::equal, SAME_TILL_END); 9510 //falling through if less than 4 bytes left 9511 9512 bind(BYTES_TAIL); 9513 bind(BYTES_LOOP); 9514 load_unsigned_byte(tmp1, Address(obja, result)); 9515 load_unsigned_byte(tmp2, Address(objb, result)); 9516 xorl(tmp1, tmp2); 9517 testl(tmp1, tmp1); 9518 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9519 decq(length); 9520 jccb(Assembler::zero, SAME_TILL_END); 9521 incq(result); 9522 load_unsigned_byte(tmp1, Address(obja, result)); 9523 load_unsigned_byte(tmp2, Address(objb, result)); 9524 xorl(tmp1, tmp2); 9525 testl(tmp1, tmp1); 9526 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9527 decq(length); 9528 jccb(Assembler::zero, SAME_TILL_END); 9529 incq(result); 9530 load_unsigned_byte(tmp1, Address(obja, result)); 9531 load_unsigned_byte(tmp2, Address(objb, result)); 9532 xorl(tmp1, tmp2); 9533 testl(tmp1, tmp1); 9534 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9535 jmpb(SAME_TILL_END); 9536 9537 if (UseAVX >= 2) { 9538 bind(VECTOR32_NOT_EQUAL); 9539 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 9540 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 9541 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 9542 vpmovmskb(tmp1, rymm0); 9543 bsfq(tmp1, tmp1); 9544 addq(result, tmp1); 9545 shrq(result); 9546 jmpb(DONE); 9547 } 9548 9549 bind(VECTOR16_NOT_EQUAL); 9550 if (UseAVX >= 2) { 9551 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 9552 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 9553 pxor(rymm0, rymm2); 9554 } else { 9555 pcmpeqb(rymm2, rymm2); 9556 pxor(rymm0, rymm1); 9557 pcmpeqb(rymm0, rymm1); 9558 pxor(rymm0, rymm2); 9559 } 9560 pmovmskb(tmp1, rymm0); 9561 bsfq(tmp1, tmp1); 9562 addq(result, tmp1); 9563 shrq(result); 9564 jmpb(DONE); 9565 9566 bind(VECTOR8_NOT_EQUAL); 9567 bind(VECTOR4_NOT_EQUAL); 9568 bsfq(tmp1, tmp1); 9569 shrq(tmp1, 3); 9570 addq(result, tmp1); 9571 bind(BYTES_NOT_EQUAL); 9572 shrq(result); 9573 jmpb(DONE); 9574 9575 bind(SAME_TILL_END); 9576 mov64(result, -1); 9577 9578 bind(DONE); 9579 } 9580 9581 //Helper functions for square_to_len() 9582 9583 /** 9584 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 9585 * Preserves x and z and modifies rest of the registers. 9586 */ 9587 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9588 // Perform square and right shift by 1 9589 // Handle odd xlen case first, then for even xlen do the following 9590 // jlong carry = 0; 9591 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 9592 // huge_128 product = x[j:j+1] * x[j:j+1]; 9593 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 9594 // z[i+2:i+3] = (jlong)(product >>> 1); 9595 // carry = (jlong)product; 9596 // } 9597 9598 xorq(tmp5, tmp5); // carry 9599 xorq(rdxReg, rdxReg); 9600 xorl(tmp1, tmp1); // index for x 9601 xorl(tmp4, tmp4); // index for z 9602 9603 Label L_first_loop, L_first_loop_exit; 9604 9605 testl(xlen, 1); 9606 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 9607 9608 // Square and right shift by 1 the odd element using 32 bit multiply 9609 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 9610 imulq(raxReg, raxReg); 9611 shrq(raxReg, 1); 9612 adcq(tmp5, 0); 9613 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 9614 incrementl(tmp1); 9615 addl(tmp4, 2); 9616 9617 // Square and right shift by 1 the rest using 64 bit multiply 9618 bind(L_first_loop); 9619 cmpptr(tmp1, xlen); 9620 jccb(Assembler::equal, L_first_loop_exit); 9621 9622 // Square 9623 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 9624 rorq(raxReg, 32); // convert big-endian to little-endian 9625 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 9626 9627 // Right shift by 1 and save carry 9628 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 9629 rcrq(rdxReg, 1); 9630 rcrq(raxReg, 1); 9631 adcq(tmp5, 0); 9632 9633 // Store result in z 9634 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 9635 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 9636 9637 // Update indices for x and z 9638 addl(tmp1, 2); 9639 addl(tmp4, 4); 9640 jmp(L_first_loop); 9641 9642 bind(L_first_loop_exit); 9643 } 9644 9645 9646 /** 9647 * Perform the following multiply add operation using BMI2 instructions 9648 * carry:sum = sum + op1*op2 + carry 9649 * op2 should be in rdx 9650 * op2 is preserved, all other registers are modified 9651 */ 9652 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 9653 // assert op2 is rdx 9654 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 9655 addq(sum, carry); 9656 adcq(tmp2, 0); 9657 addq(sum, op1); 9658 adcq(tmp2, 0); 9659 movq(carry, tmp2); 9660 } 9661 9662 /** 9663 * Perform the following multiply add operation: 9664 * carry:sum = sum + op1*op2 + carry 9665 * Preserves op1, op2 and modifies rest of registers 9666 */ 9667 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 9668 // rdx:rax = op1 * op2 9669 movq(raxReg, op2); 9670 mulq(op1); 9671 9672 // rdx:rax = sum + carry + rdx:rax 9673 addq(sum, carry); 9674 adcq(rdxReg, 0); 9675 addq(sum, raxReg); 9676 adcq(rdxReg, 0); 9677 9678 // carry:sum = rdx:sum 9679 movq(carry, rdxReg); 9680 } 9681 9682 /** 9683 * Add 64 bit long carry into z[] with carry propogation. 9684 * Preserves z and carry register values and modifies rest of registers. 9685 * 9686 */ 9687 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 9688 Label L_fourth_loop, L_fourth_loop_exit; 9689 9690 movl(tmp1, 1); 9691 subl(zlen, 2); 9692 addq(Address(z, zlen, Address::times_4, 0), carry); 9693 9694 bind(L_fourth_loop); 9695 jccb(Assembler::carryClear, L_fourth_loop_exit); 9696 subl(zlen, 2); 9697 jccb(Assembler::negative, L_fourth_loop_exit); 9698 addq(Address(z, zlen, Address::times_4, 0), tmp1); 9699 jmp(L_fourth_loop); 9700 bind(L_fourth_loop_exit); 9701 } 9702 9703 /** 9704 * Shift z[] left by 1 bit. 9705 * Preserves x, len, z and zlen registers and modifies rest of the registers. 9706 * 9707 */ 9708 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 9709 9710 Label L_fifth_loop, L_fifth_loop_exit; 9711 9712 // Fifth loop 9713 // Perform primitiveLeftShift(z, zlen, 1) 9714 9715 const Register prev_carry = tmp1; 9716 const Register new_carry = tmp4; 9717 const Register value = tmp2; 9718 const Register zidx = tmp3; 9719 9720 // int zidx, carry; 9721 // long value; 9722 // carry = 0; 9723 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 9724 // (carry:value) = (z[i] << 1) | carry ; 9725 // z[i] = value; 9726 // } 9727 9728 movl(zidx, zlen); 9729 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 9730 9731 bind(L_fifth_loop); 9732 decl(zidx); // Use decl to preserve carry flag 9733 decl(zidx); 9734 jccb(Assembler::negative, L_fifth_loop_exit); 9735 9736 if (UseBMI2Instructions) { 9737 movq(value, Address(z, zidx, Address::times_4, 0)); 9738 rclq(value, 1); 9739 rorxq(value, value, 32); 9740 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9741 } 9742 else { 9743 // clear new_carry 9744 xorl(new_carry, new_carry); 9745 9746 // Shift z[i] by 1, or in previous carry and save new carry 9747 movq(value, Address(z, zidx, Address::times_4, 0)); 9748 shlq(value, 1); 9749 adcl(new_carry, 0); 9750 9751 orq(value, prev_carry); 9752 rorq(value, 0x20); 9753 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9754 9755 // Set previous carry = new carry 9756 movl(prev_carry, new_carry); 9757 } 9758 jmp(L_fifth_loop); 9759 9760 bind(L_fifth_loop_exit); 9761 } 9762 9763 9764 /** 9765 * Code for BigInteger::squareToLen() intrinsic 9766 * 9767 * rdi: x 9768 * rsi: len 9769 * r8: z 9770 * rcx: zlen 9771 * r12: tmp1 9772 * r13: tmp2 9773 * r14: tmp3 9774 * r15: tmp4 9775 * rbx: tmp5 9776 * 9777 */ 9778 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9779 9780 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 9781 push(tmp1); 9782 push(tmp2); 9783 push(tmp3); 9784 push(tmp4); 9785 push(tmp5); 9786 9787 // First loop 9788 // Store the squares, right shifted one bit (i.e., divided by 2). 9789 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 9790 9791 // Add in off-diagonal sums. 9792 // 9793 // Second, third (nested) and fourth loops. 9794 // zlen +=2; 9795 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 9796 // carry = 0; 9797 // long op2 = x[xidx:xidx+1]; 9798 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 9799 // k -= 2; 9800 // long op1 = x[j:j+1]; 9801 // long sum = z[k:k+1]; 9802 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 9803 // z[k:k+1] = sum; 9804 // } 9805 // add_one_64(z, k, carry, tmp_regs); 9806 // } 9807 9808 const Register carry = tmp5; 9809 const Register sum = tmp3; 9810 const Register op1 = tmp4; 9811 Register op2 = tmp2; 9812 9813 push(zlen); 9814 push(len); 9815 addl(zlen,2); 9816 bind(L_second_loop); 9817 xorq(carry, carry); 9818 subl(zlen, 4); 9819 subl(len, 2); 9820 push(zlen); 9821 push(len); 9822 cmpl(len, 0); 9823 jccb(Assembler::lessEqual, L_second_loop_exit); 9824 9825 // Multiply an array by one 64 bit long. 9826 if (UseBMI2Instructions) { 9827 op2 = rdxReg; 9828 movq(op2, Address(x, len, Address::times_4, 0)); 9829 rorxq(op2, op2, 32); 9830 } 9831 else { 9832 movq(op2, Address(x, len, Address::times_4, 0)); 9833 rorq(op2, 32); 9834 } 9835 9836 bind(L_third_loop); 9837 decrementl(len); 9838 jccb(Assembler::negative, L_third_loop_exit); 9839 decrementl(len); 9840 jccb(Assembler::negative, L_last_x); 9841 9842 movq(op1, Address(x, len, Address::times_4, 0)); 9843 rorq(op1, 32); 9844 9845 bind(L_multiply); 9846 subl(zlen, 2); 9847 movq(sum, Address(z, zlen, Address::times_4, 0)); 9848 9849 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 9850 if (UseBMI2Instructions) { 9851 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 9852 } 9853 else { 9854 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9855 } 9856 9857 movq(Address(z, zlen, Address::times_4, 0), sum); 9858 9859 jmp(L_third_loop); 9860 bind(L_third_loop_exit); 9861 9862 // Fourth loop 9863 // Add 64 bit long carry into z with carry propogation. 9864 // Uses offsetted zlen. 9865 add_one_64(z, zlen, carry, tmp1); 9866 9867 pop(len); 9868 pop(zlen); 9869 jmp(L_second_loop); 9870 9871 // Next infrequent code is moved outside loops. 9872 bind(L_last_x); 9873 movl(op1, Address(x, 0)); 9874 jmp(L_multiply); 9875 9876 bind(L_second_loop_exit); 9877 pop(len); 9878 pop(zlen); 9879 pop(len); 9880 pop(zlen); 9881 9882 // Fifth loop 9883 // Shift z left 1 bit. 9884 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 9885 9886 // z[zlen-1] |= x[len-1] & 1; 9887 movl(tmp3, Address(x, len, Address::times_4, -4)); 9888 andl(tmp3, 1); 9889 orl(Address(z, zlen, Address::times_4, -4), tmp3); 9890 9891 pop(tmp5); 9892 pop(tmp4); 9893 pop(tmp3); 9894 pop(tmp2); 9895 pop(tmp1); 9896 } 9897 9898 /** 9899 * Helper function for mul_add() 9900 * Multiply the in[] by int k and add to out[] starting at offset offs using 9901 * 128 bit by 32 bit multiply and return the carry in tmp5. 9902 * Only quad int aligned length of in[] is operated on in this function. 9903 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 9904 * This function preserves out, in and k registers. 9905 * len and offset point to the appropriate index in "in" & "out" correspondingly 9906 * tmp5 has the carry. 9907 * other registers are temporary and are modified. 9908 * 9909 */ 9910 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 9911 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 9912 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9913 9914 Label L_first_loop, L_first_loop_exit; 9915 9916 movl(tmp1, len); 9917 shrl(tmp1, 2); 9918 9919 bind(L_first_loop); 9920 subl(tmp1, 1); 9921 jccb(Assembler::negative, L_first_loop_exit); 9922 9923 subl(len, 4); 9924 subl(offset, 4); 9925 9926 Register op2 = tmp2; 9927 const Register sum = tmp3; 9928 const Register op1 = tmp4; 9929 const Register carry = tmp5; 9930 9931 if (UseBMI2Instructions) { 9932 op2 = rdxReg; 9933 } 9934 9935 movq(op1, Address(in, len, Address::times_4, 8)); 9936 rorq(op1, 32); 9937 movq(sum, Address(out, offset, Address::times_4, 8)); 9938 rorq(sum, 32); 9939 if (UseBMI2Instructions) { 9940 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9941 } 9942 else { 9943 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9944 } 9945 // Store back in big endian from little endian 9946 rorq(sum, 0x20); 9947 movq(Address(out, offset, Address::times_4, 8), sum); 9948 9949 movq(op1, Address(in, len, Address::times_4, 0)); 9950 rorq(op1, 32); 9951 movq(sum, Address(out, offset, Address::times_4, 0)); 9952 rorq(sum, 32); 9953 if (UseBMI2Instructions) { 9954 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9955 } 9956 else { 9957 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9958 } 9959 // Store back in big endian from little endian 9960 rorq(sum, 0x20); 9961 movq(Address(out, offset, Address::times_4, 0), sum); 9962 9963 jmp(L_first_loop); 9964 bind(L_first_loop_exit); 9965 } 9966 9967 /** 9968 * Code for BigInteger::mulAdd() intrinsic 9969 * 9970 * rdi: out 9971 * rsi: in 9972 * r11: offs (out.length - offset) 9973 * rcx: len 9974 * r8: k 9975 * r12: tmp1 9976 * r13: tmp2 9977 * r14: tmp3 9978 * r15: tmp4 9979 * rbx: tmp5 9980 * Multiply the in[] by word k and add to out[], return the carry in rax 9981 */ 9982 void MacroAssembler::mul_add(Register out, Register in, Register offs, 9983 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 9984 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9985 9986 Label L_carry, L_last_in, L_done; 9987 9988 // carry = 0; 9989 // for (int j=len-1; j >= 0; j--) { 9990 // long product = (in[j] & LONG_MASK) * kLong + 9991 // (out[offs] & LONG_MASK) + carry; 9992 // out[offs--] = (int)product; 9993 // carry = product >>> 32; 9994 // } 9995 // 9996 push(tmp1); 9997 push(tmp2); 9998 push(tmp3); 9999 push(tmp4); 10000 push(tmp5); 10001 10002 Register op2 = tmp2; 10003 const Register sum = tmp3; 10004 const Register op1 = tmp4; 10005 const Register carry = tmp5; 10006 10007 if (UseBMI2Instructions) { 10008 op2 = rdxReg; 10009 movl(op2, k); 10010 } 10011 else { 10012 movl(op2, k); 10013 } 10014 10015 xorq(carry, carry); 10016 10017 //First loop 10018 10019 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 10020 //The carry is in tmp5 10021 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 10022 10023 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 10024 decrementl(len); 10025 jccb(Assembler::negative, L_carry); 10026 decrementl(len); 10027 jccb(Assembler::negative, L_last_in); 10028 10029 movq(op1, Address(in, len, Address::times_4, 0)); 10030 rorq(op1, 32); 10031 10032 subl(offs, 2); 10033 movq(sum, Address(out, offs, Address::times_4, 0)); 10034 rorq(sum, 32); 10035 10036 if (UseBMI2Instructions) { 10037 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10038 } 10039 else { 10040 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10041 } 10042 10043 // Store back in big endian from little endian 10044 rorq(sum, 0x20); 10045 movq(Address(out, offs, Address::times_4, 0), sum); 10046 10047 testl(len, len); 10048 jccb(Assembler::zero, L_carry); 10049 10050 //Multiply the last in[] entry, if any 10051 bind(L_last_in); 10052 movl(op1, Address(in, 0)); 10053 movl(sum, Address(out, offs, Address::times_4, -4)); 10054 10055 movl(raxReg, k); 10056 mull(op1); //tmp4 * eax -> edx:eax 10057 addl(sum, carry); 10058 adcl(rdxReg, 0); 10059 addl(sum, raxReg); 10060 adcl(rdxReg, 0); 10061 movl(carry, rdxReg); 10062 10063 movl(Address(out, offs, Address::times_4, -4), sum); 10064 10065 bind(L_carry); 10066 //return tmp5/carry as carry in rax 10067 movl(rax, carry); 10068 10069 bind(L_done); 10070 pop(tmp5); 10071 pop(tmp4); 10072 pop(tmp3); 10073 pop(tmp2); 10074 pop(tmp1); 10075 } 10076 #endif 10077 10078 /** 10079 * Emits code to update CRC-32 with a byte value according to constants in table 10080 * 10081 * @param [in,out]crc Register containing the crc. 10082 * @param [in]val Register containing the byte to fold into the CRC. 10083 * @param [in]table Register containing the table of crc constants. 10084 * 10085 * uint32_t crc; 10086 * val = crc_table[(val ^ crc) & 0xFF]; 10087 * crc = val ^ (crc >> 8); 10088 * 10089 */ 10090 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 10091 xorl(val, crc); 10092 andl(val, 0xFF); 10093 shrl(crc, 8); // unsigned shift 10094 xorl(crc, Address(table, val, Address::times_4, 0)); 10095 } 10096 10097 /** 10098 * Fold 128-bit data chunk 10099 */ 10100 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 10101 if (UseAVX > 0) { 10102 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 10103 vpclmulldq(xcrc, xK, xcrc); // [63:0] 10104 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 10105 pxor(xcrc, xtmp); 10106 } else { 10107 movdqa(xtmp, xcrc); 10108 pclmulhdq(xtmp, xK); // [123:64] 10109 pclmulldq(xcrc, xK); // [63:0] 10110 pxor(xcrc, xtmp); 10111 movdqu(xtmp, Address(buf, offset)); 10112 pxor(xcrc, xtmp); 10113 } 10114 } 10115 10116 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 10117 if (UseAVX > 0) { 10118 vpclmulhdq(xtmp, xK, xcrc); 10119 vpclmulldq(xcrc, xK, xcrc); 10120 pxor(xcrc, xbuf); 10121 pxor(xcrc, xtmp); 10122 } else { 10123 movdqa(xtmp, xcrc); 10124 pclmulhdq(xtmp, xK); 10125 pclmulldq(xcrc, xK); 10126 pxor(xcrc, xbuf); 10127 pxor(xcrc, xtmp); 10128 } 10129 } 10130 10131 /** 10132 * 8-bit folds to compute 32-bit CRC 10133 * 10134 * uint64_t xcrc; 10135 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 10136 */ 10137 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 10138 movdl(tmp, xcrc); 10139 andl(tmp, 0xFF); 10140 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 10141 psrldq(xcrc, 1); // unsigned shift one byte 10142 pxor(xcrc, xtmp); 10143 } 10144 10145 /** 10146 * uint32_t crc; 10147 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 10148 */ 10149 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 10150 movl(tmp, crc); 10151 andl(tmp, 0xFF); 10152 shrl(crc, 8); 10153 xorl(crc, Address(table, tmp, Address::times_4, 0)); 10154 } 10155 10156 /** 10157 * @param crc register containing existing CRC (32-bit) 10158 * @param buf register pointing to input byte buffer (byte*) 10159 * @param len register containing number of bytes 10160 * @param table register that will contain address of CRC table 10161 * @param tmp scratch register 10162 */ 10163 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 10164 assert_different_registers(crc, buf, len, table, tmp, rax); 10165 10166 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 10167 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 10168 10169 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 10170 // context for the registers used, where all instructions below are using 128-bit mode 10171 // On EVEX without VL and BW, these instructions will all be AVX. 10172 if (VM_Version::supports_avx512vlbw()) { 10173 movl(tmp, 0xffff); 10174 kmovwl(k1, tmp); 10175 } 10176 10177 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 10178 notl(crc); // ~crc 10179 cmpl(len, 16); 10180 jcc(Assembler::less, L_tail); 10181 10182 // Align buffer to 16 bytes 10183 movl(tmp, buf); 10184 andl(tmp, 0xF); 10185 jccb(Assembler::zero, L_aligned); 10186 subl(tmp, 16); 10187 addl(len, tmp); 10188 10189 align(4); 10190 BIND(L_align_loop); 10191 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10192 update_byte_crc32(crc, rax, table); 10193 increment(buf); 10194 incrementl(tmp); 10195 jccb(Assembler::less, L_align_loop); 10196 10197 BIND(L_aligned); 10198 movl(tmp, len); // save 10199 shrl(len, 4); 10200 jcc(Assembler::zero, L_tail_restore); 10201 10202 // Fold crc into first bytes of vector 10203 movdqa(xmm1, Address(buf, 0)); 10204 movdl(rax, xmm1); 10205 xorl(crc, rax); 10206 if (VM_Version::supports_sse4_1()) { 10207 pinsrd(xmm1, crc, 0); 10208 } else { 10209 pinsrw(xmm1, crc, 0); 10210 shrl(crc, 16); 10211 pinsrw(xmm1, crc, 1); 10212 } 10213 addptr(buf, 16); 10214 subl(len, 4); // len > 0 10215 jcc(Assembler::less, L_fold_tail); 10216 10217 movdqa(xmm2, Address(buf, 0)); 10218 movdqa(xmm3, Address(buf, 16)); 10219 movdqa(xmm4, Address(buf, 32)); 10220 addptr(buf, 48); 10221 subl(len, 3); 10222 jcc(Assembler::lessEqual, L_fold_512b); 10223 10224 // Fold total 512 bits of polynomial on each iteration, 10225 // 128 bits per each of 4 parallel streams. 10226 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 10227 10228 align(32); 10229 BIND(L_fold_512b_loop); 10230 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10231 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 10232 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 10233 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 10234 addptr(buf, 64); 10235 subl(len, 4); 10236 jcc(Assembler::greater, L_fold_512b_loop); 10237 10238 // Fold 512 bits to 128 bits. 10239 BIND(L_fold_512b); 10240 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10241 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 10242 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 10243 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 10244 10245 // Fold the rest of 128 bits data chunks 10246 BIND(L_fold_tail); 10247 addl(len, 3); 10248 jccb(Assembler::lessEqual, L_fold_128b); 10249 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10250 10251 BIND(L_fold_tail_loop); 10252 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10253 addptr(buf, 16); 10254 decrementl(len); 10255 jccb(Assembler::greater, L_fold_tail_loop); 10256 10257 // Fold 128 bits in xmm1 down into 32 bits in crc register. 10258 BIND(L_fold_128b); 10259 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 10260 if (UseAVX > 0) { 10261 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 10262 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 10263 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 10264 } else { 10265 movdqa(xmm2, xmm0); 10266 pclmulqdq(xmm2, xmm1, 0x1); 10267 movdqa(xmm3, xmm0); 10268 pand(xmm3, xmm2); 10269 pclmulqdq(xmm0, xmm3, 0x1); 10270 } 10271 psrldq(xmm1, 8); 10272 psrldq(xmm2, 4); 10273 pxor(xmm0, xmm1); 10274 pxor(xmm0, xmm2); 10275 10276 // 8 8-bit folds to compute 32-bit CRC. 10277 for (int j = 0; j < 4; j++) { 10278 fold_8bit_crc32(xmm0, table, xmm1, rax); 10279 } 10280 movdl(crc, xmm0); // mov 32 bits to general register 10281 for (int j = 0; j < 4; j++) { 10282 fold_8bit_crc32(crc, table, rax); 10283 } 10284 10285 BIND(L_tail_restore); 10286 movl(len, tmp); // restore 10287 BIND(L_tail); 10288 andl(len, 0xf); 10289 jccb(Assembler::zero, L_exit); 10290 10291 // Fold the rest of bytes 10292 align(4); 10293 BIND(L_tail_loop); 10294 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10295 update_byte_crc32(crc, rax, table); 10296 increment(buf); 10297 decrementl(len); 10298 jccb(Assembler::greater, L_tail_loop); 10299 10300 BIND(L_exit); 10301 notl(crc); // ~c 10302 } 10303 10304 #ifdef _LP64 10305 // S. Gueron / Information Processing Letters 112 (2012) 184 10306 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 10307 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 10308 // Output: the 64-bit carry-less product of B * CONST 10309 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 10310 Register tmp1, Register tmp2, Register tmp3) { 10311 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10312 if (n > 0) { 10313 addq(tmp3, n * 256 * 8); 10314 } 10315 // Q1 = TABLEExt[n][B & 0xFF]; 10316 movl(tmp1, in); 10317 andl(tmp1, 0x000000FF); 10318 shll(tmp1, 3); 10319 addq(tmp1, tmp3); 10320 movq(tmp1, Address(tmp1, 0)); 10321 10322 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10323 movl(tmp2, in); 10324 shrl(tmp2, 8); 10325 andl(tmp2, 0x000000FF); 10326 shll(tmp2, 3); 10327 addq(tmp2, tmp3); 10328 movq(tmp2, Address(tmp2, 0)); 10329 10330 shlq(tmp2, 8); 10331 xorq(tmp1, tmp2); 10332 10333 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10334 movl(tmp2, in); 10335 shrl(tmp2, 16); 10336 andl(tmp2, 0x000000FF); 10337 shll(tmp2, 3); 10338 addq(tmp2, tmp3); 10339 movq(tmp2, Address(tmp2, 0)); 10340 10341 shlq(tmp2, 16); 10342 xorq(tmp1, tmp2); 10343 10344 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10345 shrl(in, 24); 10346 andl(in, 0x000000FF); 10347 shll(in, 3); 10348 addq(in, tmp3); 10349 movq(in, Address(in, 0)); 10350 10351 shlq(in, 24); 10352 xorq(in, tmp1); 10353 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10354 } 10355 10356 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10357 Register in_out, 10358 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10359 XMMRegister w_xtmp2, 10360 Register tmp1, 10361 Register n_tmp2, Register n_tmp3) { 10362 if (is_pclmulqdq_supported) { 10363 movdl(w_xtmp1, in_out); // modified blindly 10364 10365 movl(tmp1, const_or_pre_comp_const_index); 10366 movdl(w_xtmp2, tmp1); 10367 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10368 10369 movdq(in_out, w_xtmp1); 10370 } else { 10371 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 10372 } 10373 } 10374 10375 // Recombination Alternative 2: No bit-reflections 10376 // T1 = (CRC_A * U1) << 1 10377 // T2 = (CRC_B * U2) << 1 10378 // C1 = T1 >> 32 10379 // C2 = T2 >> 32 10380 // T1 = T1 & 0xFFFFFFFF 10381 // T2 = T2 & 0xFFFFFFFF 10382 // T1 = CRC32(0, T1) 10383 // T2 = CRC32(0, T2) 10384 // C1 = C1 ^ T1 10385 // C2 = C2 ^ T2 10386 // CRC = C1 ^ C2 ^ CRC_C 10387 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10388 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10389 Register tmp1, Register tmp2, 10390 Register n_tmp3) { 10391 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10392 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10393 shlq(in_out, 1); 10394 movl(tmp1, in_out); 10395 shrq(in_out, 32); 10396 xorl(tmp2, tmp2); 10397 crc32(tmp2, tmp1, 4); 10398 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 10399 shlq(in1, 1); 10400 movl(tmp1, in1); 10401 shrq(in1, 32); 10402 xorl(tmp2, tmp2); 10403 crc32(tmp2, tmp1, 4); 10404 xorl(in1, tmp2); 10405 xorl(in_out, in1); 10406 xorl(in_out, in2); 10407 } 10408 10409 // Set N to predefined value 10410 // Subtract from a lenght of a buffer 10411 // execute in a loop: 10412 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 10413 // for i = 1 to N do 10414 // CRC_A = CRC32(CRC_A, A[i]) 10415 // CRC_B = CRC32(CRC_B, B[i]) 10416 // CRC_C = CRC32(CRC_C, C[i]) 10417 // end for 10418 // Recombine 10419 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10420 Register in_out1, Register in_out2, Register in_out3, 10421 Register tmp1, Register tmp2, Register tmp3, 10422 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10423 Register tmp4, Register tmp5, 10424 Register n_tmp6) { 10425 Label L_processPartitions; 10426 Label L_processPartition; 10427 Label L_exit; 10428 10429 bind(L_processPartitions); 10430 cmpl(in_out1, 3 * size); 10431 jcc(Assembler::less, L_exit); 10432 xorl(tmp1, tmp1); 10433 xorl(tmp2, tmp2); 10434 movq(tmp3, in_out2); 10435 addq(tmp3, size); 10436 10437 bind(L_processPartition); 10438 crc32(in_out3, Address(in_out2, 0), 8); 10439 crc32(tmp1, Address(in_out2, size), 8); 10440 crc32(tmp2, Address(in_out2, size * 2), 8); 10441 addq(in_out2, 8); 10442 cmpq(in_out2, tmp3); 10443 jcc(Assembler::less, L_processPartition); 10444 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10445 w_xtmp1, w_xtmp2, w_xtmp3, 10446 tmp4, tmp5, 10447 n_tmp6); 10448 addq(in_out2, 2 * size); 10449 subl(in_out1, 3 * size); 10450 jmp(L_processPartitions); 10451 10452 bind(L_exit); 10453 } 10454 #else 10455 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 10456 Register tmp1, Register tmp2, Register tmp3, 10457 XMMRegister xtmp1, XMMRegister xtmp2) { 10458 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10459 if (n > 0) { 10460 addl(tmp3, n * 256 * 8); 10461 } 10462 // Q1 = TABLEExt[n][B & 0xFF]; 10463 movl(tmp1, in_out); 10464 andl(tmp1, 0x000000FF); 10465 shll(tmp1, 3); 10466 addl(tmp1, tmp3); 10467 movq(xtmp1, Address(tmp1, 0)); 10468 10469 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10470 movl(tmp2, in_out); 10471 shrl(tmp2, 8); 10472 andl(tmp2, 0x000000FF); 10473 shll(tmp2, 3); 10474 addl(tmp2, tmp3); 10475 movq(xtmp2, Address(tmp2, 0)); 10476 10477 psllq(xtmp2, 8); 10478 pxor(xtmp1, xtmp2); 10479 10480 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10481 movl(tmp2, in_out); 10482 shrl(tmp2, 16); 10483 andl(tmp2, 0x000000FF); 10484 shll(tmp2, 3); 10485 addl(tmp2, tmp3); 10486 movq(xtmp2, Address(tmp2, 0)); 10487 10488 psllq(xtmp2, 16); 10489 pxor(xtmp1, xtmp2); 10490 10491 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10492 shrl(in_out, 24); 10493 andl(in_out, 0x000000FF); 10494 shll(in_out, 3); 10495 addl(in_out, tmp3); 10496 movq(xtmp2, Address(in_out, 0)); 10497 10498 psllq(xtmp2, 24); 10499 pxor(xtmp1, xtmp2); // Result in CXMM 10500 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10501 } 10502 10503 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10504 Register in_out, 10505 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10506 XMMRegister w_xtmp2, 10507 Register tmp1, 10508 Register n_tmp2, Register n_tmp3) { 10509 if (is_pclmulqdq_supported) { 10510 movdl(w_xtmp1, in_out); 10511 10512 movl(tmp1, const_or_pre_comp_const_index); 10513 movdl(w_xtmp2, tmp1); 10514 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10515 // Keep result in XMM since GPR is 32 bit in length 10516 } else { 10517 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 10518 } 10519 } 10520 10521 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10522 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10523 Register tmp1, Register tmp2, 10524 Register n_tmp3) { 10525 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10526 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10527 10528 psllq(w_xtmp1, 1); 10529 movdl(tmp1, w_xtmp1); 10530 psrlq(w_xtmp1, 32); 10531 movdl(in_out, w_xtmp1); 10532 10533 xorl(tmp2, tmp2); 10534 crc32(tmp2, tmp1, 4); 10535 xorl(in_out, tmp2); 10536 10537 psllq(w_xtmp2, 1); 10538 movdl(tmp1, w_xtmp2); 10539 psrlq(w_xtmp2, 32); 10540 movdl(in1, w_xtmp2); 10541 10542 xorl(tmp2, tmp2); 10543 crc32(tmp2, tmp1, 4); 10544 xorl(in1, tmp2); 10545 xorl(in_out, in1); 10546 xorl(in_out, in2); 10547 } 10548 10549 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10550 Register in_out1, Register in_out2, Register in_out3, 10551 Register tmp1, Register tmp2, Register tmp3, 10552 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10553 Register tmp4, Register tmp5, 10554 Register n_tmp6) { 10555 Label L_processPartitions; 10556 Label L_processPartition; 10557 Label L_exit; 10558 10559 bind(L_processPartitions); 10560 cmpl(in_out1, 3 * size); 10561 jcc(Assembler::less, L_exit); 10562 xorl(tmp1, tmp1); 10563 xorl(tmp2, tmp2); 10564 movl(tmp3, in_out2); 10565 addl(tmp3, size); 10566 10567 bind(L_processPartition); 10568 crc32(in_out3, Address(in_out2, 0), 4); 10569 crc32(tmp1, Address(in_out2, size), 4); 10570 crc32(tmp2, Address(in_out2, size*2), 4); 10571 crc32(in_out3, Address(in_out2, 0+4), 4); 10572 crc32(tmp1, Address(in_out2, size+4), 4); 10573 crc32(tmp2, Address(in_out2, size*2+4), 4); 10574 addl(in_out2, 8); 10575 cmpl(in_out2, tmp3); 10576 jcc(Assembler::less, L_processPartition); 10577 10578 push(tmp3); 10579 push(in_out1); 10580 push(in_out2); 10581 tmp4 = tmp3; 10582 tmp5 = in_out1; 10583 n_tmp6 = in_out2; 10584 10585 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10586 w_xtmp1, w_xtmp2, w_xtmp3, 10587 tmp4, tmp5, 10588 n_tmp6); 10589 10590 pop(in_out2); 10591 pop(in_out1); 10592 pop(tmp3); 10593 10594 addl(in_out2, 2 * size); 10595 subl(in_out1, 3 * size); 10596 jmp(L_processPartitions); 10597 10598 bind(L_exit); 10599 } 10600 #endif //LP64 10601 10602 #ifdef _LP64 10603 // Algorithm 2: Pipelined usage of the CRC32 instruction. 10604 // Input: A buffer I of L bytes. 10605 // Output: the CRC32C value of the buffer. 10606 // Notations: 10607 // Write L = 24N + r, with N = floor (L/24). 10608 // r = L mod 24 (0 <= r < 24). 10609 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 10610 // N quadwords, and R consists of r bytes. 10611 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 10612 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 10613 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 10614 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 10615 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10616 Register tmp1, Register tmp2, Register tmp3, 10617 Register tmp4, Register tmp5, Register tmp6, 10618 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10619 bool is_pclmulqdq_supported) { 10620 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10621 Label L_wordByWord; 10622 Label L_byteByByteProlog; 10623 Label L_byteByByte; 10624 Label L_exit; 10625 10626 if (is_pclmulqdq_supported ) { 10627 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10628 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 10629 10630 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10631 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10632 10633 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10634 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10635 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 10636 } else { 10637 const_or_pre_comp_const_index[0] = 1; 10638 const_or_pre_comp_const_index[1] = 0; 10639 10640 const_or_pre_comp_const_index[2] = 3; 10641 const_or_pre_comp_const_index[3] = 2; 10642 10643 const_or_pre_comp_const_index[4] = 5; 10644 const_or_pre_comp_const_index[5] = 4; 10645 } 10646 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10647 in2, in1, in_out, 10648 tmp1, tmp2, tmp3, 10649 w_xtmp1, w_xtmp2, w_xtmp3, 10650 tmp4, tmp5, 10651 tmp6); 10652 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10653 in2, in1, in_out, 10654 tmp1, tmp2, tmp3, 10655 w_xtmp1, w_xtmp2, w_xtmp3, 10656 tmp4, tmp5, 10657 tmp6); 10658 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10659 in2, in1, in_out, 10660 tmp1, tmp2, tmp3, 10661 w_xtmp1, w_xtmp2, w_xtmp3, 10662 tmp4, tmp5, 10663 tmp6); 10664 movl(tmp1, in2); 10665 andl(tmp1, 0x00000007); 10666 negl(tmp1); 10667 addl(tmp1, in2); 10668 addq(tmp1, in1); 10669 10670 BIND(L_wordByWord); 10671 cmpq(in1, tmp1); 10672 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10673 crc32(in_out, Address(in1, 0), 4); 10674 addq(in1, 4); 10675 jmp(L_wordByWord); 10676 10677 BIND(L_byteByByteProlog); 10678 andl(in2, 0x00000007); 10679 movl(tmp2, 1); 10680 10681 BIND(L_byteByByte); 10682 cmpl(tmp2, in2); 10683 jccb(Assembler::greater, L_exit); 10684 crc32(in_out, Address(in1, 0), 1); 10685 incq(in1); 10686 incl(tmp2); 10687 jmp(L_byteByByte); 10688 10689 BIND(L_exit); 10690 } 10691 #else 10692 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10693 Register tmp1, Register tmp2, Register tmp3, 10694 Register tmp4, Register tmp5, Register tmp6, 10695 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10696 bool is_pclmulqdq_supported) { 10697 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10698 Label L_wordByWord; 10699 Label L_byteByByteProlog; 10700 Label L_byteByByte; 10701 Label L_exit; 10702 10703 if (is_pclmulqdq_supported) { 10704 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10705 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 10706 10707 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10708 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10709 10710 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10711 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10712 } else { 10713 const_or_pre_comp_const_index[0] = 1; 10714 const_or_pre_comp_const_index[1] = 0; 10715 10716 const_or_pre_comp_const_index[2] = 3; 10717 const_or_pre_comp_const_index[3] = 2; 10718 10719 const_or_pre_comp_const_index[4] = 5; 10720 const_or_pre_comp_const_index[5] = 4; 10721 } 10722 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10723 in2, in1, in_out, 10724 tmp1, tmp2, tmp3, 10725 w_xtmp1, w_xtmp2, w_xtmp3, 10726 tmp4, tmp5, 10727 tmp6); 10728 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10729 in2, in1, in_out, 10730 tmp1, tmp2, tmp3, 10731 w_xtmp1, w_xtmp2, w_xtmp3, 10732 tmp4, tmp5, 10733 tmp6); 10734 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10735 in2, in1, in_out, 10736 tmp1, tmp2, tmp3, 10737 w_xtmp1, w_xtmp2, w_xtmp3, 10738 tmp4, tmp5, 10739 tmp6); 10740 movl(tmp1, in2); 10741 andl(tmp1, 0x00000007); 10742 negl(tmp1); 10743 addl(tmp1, in2); 10744 addl(tmp1, in1); 10745 10746 BIND(L_wordByWord); 10747 cmpl(in1, tmp1); 10748 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10749 crc32(in_out, Address(in1,0), 4); 10750 addl(in1, 4); 10751 jmp(L_wordByWord); 10752 10753 BIND(L_byteByByteProlog); 10754 andl(in2, 0x00000007); 10755 movl(tmp2, 1); 10756 10757 BIND(L_byteByByte); 10758 cmpl(tmp2, in2); 10759 jccb(Assembler::greater, L_exit); 10760 movb(tmp1, Address(in1, 0)); 10761 crc32(in_out, tmp1, 1); 10762 incl(in1); 10763 incl(tmp2); 10764 jmp(L_byteByByte); 10765 10766 BIND(L_exit); 10767 } 10768 #endif // LP64 10769 #undef BIND 10770 #undef BLOCK_COMMENT 10771 10772 // Compress char[] array to byte[]. 10773 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 10774 // @HotSpotIntrinsicCandidate 10775 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 10776 // for (int i = 0; i < len; i++) { 10777 // int c = src[srcOff++]; 10778 // if (c >>> 8 != 0) { 10779 // return 0; 10780 // } 10781 // dst[dstOff++] = (byte)c; 10782 // } 10783 // return len; 10784 // } 10785 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 10786 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 10787 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 10788 Register tmp5, Register result) { 10789 Label copy_chars_loop, return_length, return_zero, done, below_threshold; 10790 10791 // rsi: src 10792 // rdi: dst 10793 // rdx: len 10794 // rcx: tmp5 10795 // rax: result 10796 10797 // rsi holds start addr of source char[] to be compressed 10798 // rdi holds start addr of destination byte[] 10799 // rdx holds length 10800 10801 assert(len != result, ""); 10802 10803 // save length for return 10804 push(len); 10805 10806 if ((UseAVX > 2) && // AVX512 10807 VM_Version::supports_avx512vlbw() && 10808 VM_Version::supports_bmi2()) { 10809 10810 set_vector_masking(); // opening of the stub context for programming mask registers 10811 10812 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero; 10813 10814 // alignement 10815 Label post_alignement; 10816 10817 // if length of the string is less than 16, handle it in an old fashioned 10818 // way 10819 testl(len, -32); 10820 jcc(Assembler::zero, below_threshold); 10821 10822 // First check whether a character is compressable ( <= 0xFF). 10823 // Create mask to test for Unicode chars inside zmm vector 10824 movl(result, 0x00FF); 10825 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 10826 10827 // Save k1 10828 kmovql(k3, k1); 10829 10830 testl(len, -64); 10831 jcc(Assembler::zero, post_alignement); 10832 10833 movl(tmp5, dst); 10834 andl(tmp5, (32 - 1)); 10835 negl(tmp5); 10836 andl(tmp5, (32 - 1)); 10837 10838 // bail out when there is nothing to be done 10839 testl(tmp5, 0xFFFFFFFF); 10840 jcc(Assembler::zero, post_alignement); 10841 10842 // ~(~0 << len), where len is the # of remaining elements to process 10843 movl(result, 0xFFFFFFFF); 10844 shlxl(result, result, tmp5); 10845 notl(result); 10846 kmovdl(k1, result); 10847 10848 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10849 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10850 ktestd(k2, k1); 10851 jcc(Assembler::carryClear, restore_k1_return_zero); 10852 10853 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10854 10855 addptr(src, tmp5); 10856 addptr(src, tmp5); 10857 addptr(dst, tmp5); 10858 subl(len, tmp5); 10859 10860 bind(post_alignement); 10861 // end of alignement 10862 10863 movl(tmp5, len); 10864 andl(tmp5, (32 - 1)); // tail count (in chars) 10865 andl(len, ~(32 - 1)); // vector count (in chars) 10866 jcc(Assembler::zero, copy_loop_tail); 10867 10868 lea(src, Address(src, len, Address::times_2)); 10869 lea(dst, Address(dst, len, Address::times_1)); 10870 negptr(len); 10871 10872 bind(copy_32_loop); 10873 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit); 10874 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10875 kortestdl(k2, k2); 10876 jcc(Assembler::carryClear, restore_k1_return_zero); 10877 10878 // All elements in current processed chunk are valid candidates for 10879 // compression. Write a truncated byte elements to the memory. 10880 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 10881 addptr(len, 32); 10882 jcc(Assembler::notZero, copy_32_loop); 10883 10884 bind(copy_loop_tail); 10885 // bail out when there is nothing to be done 10886 testl(tmp5, 0xFFFFFFFF); 10887 // Restore k1 10888 kmovql(k1, k3); 10889 jcc(Assembler::zero, return_length); 10890 10891 movl(len, tmp5); 10892 10893 // ~(~0 << len), where len is the # of remaining elements to process 10894 movl(result, 0xFFFFFFFF); 10895 shlxl(result, result, len); 10896 notl(result); 10897 10898 kmovdl(k1, result); 10899 10900 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10901 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10902 ktestd(k2, k1); 10903 jcc(Assembler::carryClear, restore_k1_return_zero); 10904 10905 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10906 // Restore k1 10907 kmovql(k1, k3); 10908 jmp(return_length); 10909 10910 bind(restore_k1_return_zero); 10911 // Restore k1 10912 kmovql(k1, k3); 10913 jmp(return_zero); 10914 10915 clear_vector_masking(); // closing of the stub context for programming mask registers 10916 } 10917 if (UseSSE42Intrinsics) { 10918 Label copy_32_loop, copy_16, copy_tail; 10919 10920 bind(below_threshold); 10921 10922 movl(result, len); 10923 10924 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 10925 10926 // vectored compression 10927 andl(len, 0xfffffff0); // vector count (in chars) 10928 andl(result, 0x0000000f); // tail count (in chars) 10929 testl(len, len); 10930 jccb(Assembler::zero, copy_16); 10931 10932 // compress 16 chars per iter 10933 movdl(tmp1Reg, tmp5); 10934 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10935 pxor(tmp4Reg, tmp4Reg); 10936 10937 lea(src, Address(src, len, Address::times_2)); 10938 lea(dst, Address(dst, len, Address::times_1)); 10939 negptr(len); 10940 10941 bind(copy_32_loop); 10942 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 10943 por(tmp4Reg, tmp2Reg); 10944 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 10945 por(tmp4Reg, tmp3Reg); 10946 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 10947 jcc(Assembler::notZero, return_zero); 10948 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 10949 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 10950 addptr(len, 16); 10951 jcc(Assembler::notZero, copy_32_loop); 10952 10953 // compress next vector of 8 chars (if any) 10954 bind(copy_16); 10955 movl(len, result); 10956 andl(len, 0xfffffff8); // vector count (in chars) 10957 andl(result, 0x00000007); // tail count (in chars) 10958 testl(len, len); 10959 jccb(Assembler::zero, copy_tail); 10960 10961 movdl(tmp1Reg, tmp5); 10962 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10963 pxor(tmp3Reg, tmp3Reg); 10964 10965 movdqu(tmp2Reg, Address(src, 0)); 10966 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 10967 jccb(Assembler::notZero, return_zero); 10968 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 10969 movq(Address(dst, 0), tmp2Reg); 10970 addptr(src, 16); 10971 addptr(dst, 8); 10972 10973 bind(copy_tail); 10974 movl(len, result); 10975 } 10976 // compress 1 char per iter 10977 testl(len, len); 10978 jccb(Assembler::zero, return_length); 10979 lea(src, Address(src, len, Address::times_2)); 10980 lea(dst, Address(dst, len, Address::times_1)); 10981 negptr(len); 10982 10983 bind(copy_chars_loop); 10984 load_unsigned_short(result, Address(src, len, Address::times_2)); 10985 testl(result, 0xff00); // check if Unicode char 10986 jccb(Assembler::notZero, return_zero); 10987 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 10988 increment(len); 10989 jcc(Assembler::notZero, copy_chars_loop); 10990 10991 // if compression succeeded, return length 10992 bind(return_length); 10993 pop(result); 10994 jmpb(done); 10995 10996 // if compression failed, return 0 10997 bind(return_zero); 10998 xorl(result, result); 10999 addptr(rsp, wordSize); 11000 11001 bind(done); 11002 } 11003 11004 // Inflate byte[] array to char[]. 11005 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 11006 // @HotSpotIntrinsicCandidate 11007 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 11008 // for (int i = 0; i < len; i++) { 11009 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 11010 // } 11011 // } 11012 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 11013 XMMRegister tmp1, Register tmp2) { 11014 Label copy_chars_loop, done, below_threshold; 11015 // rsi: src 11016 // rdi: dst 11017 // rdx: len 11018 // rcx: tmp2 11019 11020 // rsi holds start addr of source byte[] to be inflated 11021 // rdi holds start addr of destination char[] 11022 // rdx holds length 11023 assert_different_registers(src, dst, len, tmp2); 11024 11025 if ((UseAVX > 2) && // AVX512 11026 VM_Version::supports_avx512vlbw() && 11027 VM_Version::supports_bmi2()) { 11028 11029 set_vector_masking(); // opening of the stub context for programming mask registers 11030 11031 Label copy_32_loop, copy_tail; 11032 Register tmp3_aliased = len; 11033 11034 // if length of the string is less than 16, handle it in an old fashioned 11035 // way 11036 testl(len, -16); 11037 jcc(Assembler::zero, below_threshold); 11038 11039 // In order to use only one arithmetic operation for the main loop we use 11040 // this pre-calculation 11041 movl(tmp2, len); 11042 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 11043 andl(len, -32); // vector count 11044 jccb(Assembler::zero, copy_tail); 11045 11046 lea(src, Address(src, len, Address::times_1)); 11047 lea(dst, Address(dst, len, Address::times_2)); 11048 negptr(len); 11049 11050 11051 // inflate 32 chars per iter 11052 bind(copy_32_loop); 11053 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 11054 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit); 11055 addptr(len, 32); 11056 jcc(Assembler::notZero, copy_32_loop); 11057 11058 bind(copy_tail); 11059 // bail out when there is nothing to be done 11060 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 11061 jcc(Assembler::zero, done); 11062 11063 // Save k1 11064 kmovql(k2, k1); 11065 11066 // ~(~0 << length), where length is the # of remaining elements to process 11067 movl(tmp3_aliased, -1); 11068 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 11069 notl(tmp3_aliased); 11070 kmovdl(k1, tmp3_aliased); 11071 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit); 11072 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit); 11073 11074 // Restore k1 11075 kmovql(k1, k2); 11076 jmp(done); 11077 11078 clear_vector_masking(); // closing of the stub context for programming mask registers 11079 } 11080 if (UseSSE42Intrinsics) { 11081 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 11082 11083 movl(tmp2, len); 11084 11085 if (UseAVX > 1) { 11086 andl(tmp2, (16 - 1)); 11087 andl(len, -16); 11088 jccb(Assembler::zero, copy_new_tail); 11089 } else { 11090 andl(tmp2, 0x00000007); // tail count (in chars) 11091 andl(len, 0xfffffff8); // vector count (in chars) 11092 jccb(Assembler::zero, copy_tail); 11093 } 11094 11095 // vectored inflation 11096 lea(src, Address(src, len, Address::times_1)); 11097 lea(dst, Address(dst, len, Address::times_2)); 11098 negptr(len); 11099 11100 if (UseAVX > 1) { 11101 bind(copy_16_loop); 11102 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 11103 vmovdqu(Address(dst, len, Address::times_2), tmp1); 11104 addptr(len, 16); 11105 jcc(Assembler::notZero, copy_16_loop); 11106 11107 bind(below_threshold); 11108 bind(copy_new_tail); 11109 if ((UseAVX > 2) && 11110 VM_Version::supports_avx512vlbw() && 11111 VM_Version::supports_bmi2()) { 11112 movl(tmp2, len); 11113 } else { 11114 movl(len, tmp2); 11115 } 11116 andl(tmp2, 0x00000007); 11117 andl(len, 0xFFFFFFF8); 11118 jccb(Assembler::zero, copy_tail); 11119 11120 pmovzxbw(tmp1, Address(src, 0)); 11121 movdqu(Address(dst, 0), tmp1); 11122 addptr(src, 8); 11123 addptr(dst, 2 * 8); 11124 11125 jmp(copy_tail, true); 11126 } 11127 11128 // inflate 8 chars per iter 11129 bind(copy_8_loop); 11130 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 11131 movdqu(Address(dst, len, Address::times_2), tmp1); 11132 addptr(len, 8); 11133 jcc(Assembler::notZero, copy_8_loop); 11134 11135 bind(copy_tail); 11136 movl(len, tmp2); 11137 11138 cmpl(len, 4); 11139 jccb(Assembler::less, copy_bytes); 11140 11141 movdl(tmp1, Address(src, 0)); // load 4 byte chars 11142 pmovzxbw(tmp1, tmp1); 11143 movq(Address(dst, 0), tmp1); 11144 subptr(len, 4); 11145 addptr(src, 4); 11146 addptr(dst, 8); 11147 11148 bind(copy_bytes); 11149 } 11150 testl(len, len); 11151 jccb(Assembler::zero, done); 11152 lea(src, Address(src, len, Address::times_1)); 11153 lea(dst, Address(dst, len, Address::times_2)); 11154 negptr(len); 11155 11156 // inflate 1 char per iter 11157 bind(copy_chars_loop); 11158 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 11159 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 11160 increment(len); 11161 jcc(Assembler::notZero, copy_chars_loop); 11162 11163 bind(done); 11164 } 11165 11166 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 11167 switch (cond) { 11168 // Note some conditions are synonyms for others 11169 case Assembler::zero: return Assembler::notZero; 11170 case Assembler::notZero: return Assembler::zero; 11171 case Assembler::less: return Assembler::greaterEqual; 11172 case Assembler::lessEqual: return Assembler::greater; 11173 case Assembler::greater: return Assembler::lessEqual; 11174 case Assembler::greaterEqual: return Assembler::less; 11175 case Assembler::below: return Assembler::aboveEqual; 11176 case Assembler::belowEqual: return Assembler::above; 11177 case Assembler::above: return Assembler::belowEqual; 11178 case Assembler::aboveEqual: return Assembler::below; 11179 case Assembler::overflow: return Assembler::noOverflow; 11180 case Assembler::noOverflow: return Assembler::overflow; 11181 case Assembler::negative: return Assembler::positive; 11182 case Assembler::positive: return Assembler::negative; 11183 case Assembler::parity: return Assembler::noParity; 11184 case Assembler::noParity: return Assembler::parity; 11185 } 11186 ShouldNotReachHere(); return Assembler::overflow; 11187 } 11188 11189 SkipIfEqual::SkipIfEqual( 11190 MacroAssembler* masm, const bool* flag_addr, bool value) { 11191 _masm = masm; 11192 _masm->cmp8(ExternalAddress((address)flag_addr), value); 11193 _masm->jcc(Assembler::equal, _label); 11194 } 11195 11196 SkipIfEqual::~SkipIfEqual() { 11197 _masm->bind(_label); 11198 } 11199 11200 // 32-bit Windows has its own fast-path implementation 11201 // of get_thread 11202 #if !defined(WIN32) || defined(_LP64) 11203 11204 // This is simply a call to Thread::current() 11205 void MacroAssembler::get_thread(Register thread) { 11206 if (thread != rax) { 11207 push(rax); 11208 } 11209 LP64_ONLY(push(rdi);) 11210 LP64_ONLY(push(rsi);) 11211 push(rdx); 11212 push(rcx); 11213 #ifdef _LP64 11214 push(r8); 11215 push(r9); 11216 push(r10); 11217 push(r11); 11218 #endif 11219 11220 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 11221 11222 #ifdef _LP64 11223 pop(r11); 11224 pop(r10); 11225 pop(r9); 11226 pop(r8); 11227 #endif 11228 pop(rcx); 11229 pop(rdx); 11230 LP64_ONLY(pop(rsi);) 11231 LP64_ONLY(pop(rdi);) 11232 if (thread != rax) { 11233 mov(thread, rax); 11234 pop(rax); 11235 } 11236 } 11237 11238 #endif