src/cpu/arm/vm/macroAssembler_arm.hpp

rev 12692 : 8176100: [REDO][REDO] G1 Needs pre barrier on dereference of weak JNI handles
Reviewed-by:

*** 1,7 ****
  /*
!  * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ----
  /*
!  * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 400,409 ****
--- 400,432 ----
    // Building block for CAS cases of biased locking: makes CAS and records statistics.
    // Optional slow_case label is used to transfer control if CAS fails. Otherwise leaves condition codes set.
    void biased_locking_enter_with_cas(Register obj_reg, Register old_mark_reg, Register new_mark_reg,
                                       Register tmp, Label& slow_case, int* counter_addr);
  
+   void resolve_jobject(Register value, Register tmp1, Register tmp2);
+ 
+ #if INCLUDE_ALL_GCS
+   // G1 pre-barrier.
+   // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
+   // If store_addr != noreg, then previous value is loaded from [store_addr];
+   // in such case store_addr and new_val registers are preserved;
+   // otherwise pre_val register is preserved.
+   void g1_write_barrier_pre(Register store_addr,
+                             Register new_val,
+                             Register pre_val,
+                             Register tmp1,
+                             Register tmp2);
+ 
+   // G1 post-barrier.
+   // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
+   void g1_write_barrier_post(Register store_addr,
+                              Register new_val,
+                              Register tmp1,
+                              Register tmp2,
+                              Register tmp3);
+ #endif // INCLUDE_ALL_GCS
+ 
  #ifndef AARCH64
    void nop() {
      mov(R0, R0);
    }