src/share/vm/opto/divnode.hpp

rev 8739 : 8004073: Implement C2 Ideal node specific dump() method
Summary: add Node::dump_rel() to dump a node and its related nodes (the notion of "related" depends on the node at hand); add Node::dump_comp() to dump a node in compact representation; add Node::dump_rel_comp() to dump a node and its related nodes in compact representation; add the required machinery; extend some C2 IR nodes with compact and related dumping
Reviewed-by:

*** 1,7 ****
  /*
!  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ----
  /*
!  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 47,56 ****
--- 47,60 ----
    virtual Node *Identity( PhaseTransform *phase );
    virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
    virtual const Type *Value( PhaseTransform *phase ) const;
    virtual const Type *bottom_type() const { return TypeInt::INT; }
    virtual uint ideal_reg() const { return Op_RegI; }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------DivLNode---------------------------------------
  // Long division
  class DivLNode : public Node {
*** 60,69 ****
--- 64,77 ----
    virtual Node *Identity( PhaseTransform *phase );
    virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
    virtual const Type *Value( PhaseTransform *phase ) const;
    virtual const Type *bottom_type() const { return TypeLong::LONG; }
    virtual uint ideal_reg() const { return Op_RegL; }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------DivFNode---------------------------------------
  // Float division
  class DivFNode : public Node {
*** 73,82 ****
--- 81,94 ----
    virtual Node *Identity( PhaseTransform *phase );
    virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
    virtual const Type *Value( PhaseTransform *phase ) const;
    virtual const Type *bottom_type() const { return Type::FLOAT; }
    virtual uint ideal_reg() const { return Op_RegF; }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------DivDNode---------------------------------------
  // Double division
  class DivDNode : public Node {
*** 86,95 ****
--- 98,111 ----
    virtual Node *Identity( PhaseTransform *phase );
    virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
    virtual const Type *Value( PhaseTransform *phase ) const;
    virtual const Type *bottom_type() const { return Type::DOUBLE; }
    virtual uint ideal_reg() const { return Op_RegD; }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------ModINode---------------------------------------
  // Integer modulus
  class ModINode : public Node {
*** 98,107 ****
--- 114,127 ----
    virtual int Opcode() const;
    virtual const Type *Value( PhaseTransform *phase ) const;
    virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
    virtual const Type *bottom_type() const { return TypeInt::INT; }
    virtual uint ideal_reg() const { return Op_RegI; }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------ModLNode---------------------------------------
  // Long modulus
  class ModLNode : public Node {
*** 110,119 ****
--- 130,143 ----
    virtual int Opcode() const;
    virtual const Type *Value( PhaseTransform *phase ) const;
    virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
    virtual const Type *bottom_type() const { return TypeLong::LONG; }
    virtual uint ideal_reg() const { return Op_RegL; }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------ModFNode---------------------------------------
  // Float Modulus
  class ModFNode : public Node {
*** 121,130 ****
--- 145,158 ----
    ModFNode( Node *c, Node *in1, Node *in2 ) : Node(c,in1, in2) {}
    virtual int Opcode() const;
    virtual const Type *Value( PhaseTransform *phase ) const;
    virtual const Type *bottom_type() const { return Type::FLOAT; }
    virtual uint ideal_reg() const { return Op_RegF; }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------ModDNode---------------------------------------
  // Double Modulus
  class ModDNode : public Node {
*** 132,141 ****
--- 160,173 ----
    ModDNode( Node *c, Node *in1, Node *in2 ) : Node(c, in1, in2) {}
    virtual int Opcode() const;
    virtual const Type *Value( PhaseTransform *phase ) const;
    virtual const Type *bottom_type() const { return Type::DOUBLE; }
    virtual uint ideal_reg() const { return Op_RegD; }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------DivModNode---------------------------------------
  // Division with remainder result.
  class DivModNode : public MultiNode {
*** 154,163 ****
--- 186,199 ----
    virtual bool is_CFG() const  { return false; }
    virtual uint ideal_reg() const { return NotAMachineReg; }
  
    ProjNode* div_proj() { return proj_out(div_proj_num); }
    ProjNode* mod_proj() { return proj_out(mod_proj_num); }
+ 
+ #ifndef PRODUCT
+   REL_IN_DATA_OUT_1;
+ #endif
  };
  
  //------------------------------DivModINode---------------------------------------
  // Integer division with remainder result.
  class DivModINode : public DivModNode {