1 //
   2 // Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved.
   3 // Copyright (c) 2012, 2017 SAP SE. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 //
  25 
  26 //
  27 // PPC64 Architecture Description File
  28 //
  29 
  30 //----------REGISTER DEFINITION BLOCK------------------------------------------
  31 // This information is used by the matcher and the register allocator to
  32 // describe individual registers and classes of registers within the target
  33 // architecture.
  34 register %{
  35 //----------Architecture Description Register Definitions----------------------
  36 // General Registers
  37 // "reg_def"  name (register save type, C convention save type,
  38 //                  ideal register type, encoding);
  39 //
  40 // Register Save Types:
  41 //
  42 //   NS  = No-Save:     The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method, &
  44 //                      that they do not need to be saved at call sites.
  45 //
  46 //   SOC = Save-On-Call: The register allocator assumes that these registers
  47 //                      can be used without saving upon entry to the method,
  48 //                      but that they must be saved at call sites.
  49 //                      These are called "volatiles" on ppc.
  50 //
  51 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, but they do not need to be saved at call
  54 //                      sites.
  55 //                      These are called "nonvolatiles" on ppc.
  56 //
  57 //   AS  = Always-Save:   The register allocator assumes that these registers
  58 //                      must be saved before using them upon entry to the
  59 //                      method, & that they must be saved at call sites.
  60 //
  61 // Ideal Register Type is used to determine how to save & restore a
  62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  64 //
  65 // The encoding number is the actual bit-pattern placed into the opcodes.
  66 //
  67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
  68 // Supplement Version 1.7 as of 2003-10-29.
  69 //
  70 // For each 64-bit register we must define two registers: the register
  71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
  72 // e.g. R3_H, which is needed by the allocator, but is not used
  73 // for stores, loads, etc.
  74 
  75 // ----------------------------
  76 // Integer/Long Registers
  77 // ----------------------------
  78 
  79   // PPC64 has 32 64-bit integer registers.
  80 
  81   // types: v = volatile, nv = non-volatile, s = system
  82   reg_def R0   ( SOC, SOC, Op_RegI,  0, R0->as_VMReg()         );  // v   used in prologs
  83   reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
  84   reg_def R1   ( NS,  NS,  Op_RegI,  1, R1->as_VMReg()         );  // s   SP
  85   reg_def R1_H ( NS,  NS,  Op_RegI, 99, R1->as_VMReg()->next() );
  86   reg_def R2   ( SOC, SOC, Op_RegI,  2, R2->as_VMReg()         );  // v   TOC
  87   reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
  88   reg_def R3   ( SOC, SOC, Op_RegI,  3, R3->as_VMReg()         );  // v   iarg1 & iret
  89   reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
  90   reg_def R4   ( SOC, SOC, Op_RegI,  4, R4->as_VMReg()         );  //     iarg2
  91   reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
  92   reg_def R5   ( SOC, SOC, Op_RegI,  5, R5->as_VMReg()         );  // v   iarg3
  93   reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
  94   reg_def R6   ( SOC, SOC, Op_RegI,  6, R6->as_VMReg()         );  // v   iarg4
  95   reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
  96   reg_def R7   ( SOC, SOC, Op_RegI,  7, R7->as_VMReg()         );  // v   iarg5
  97   reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
  98   reg_def R8   ( SOC, SOC, Op_RegI,  8, R8->as_VMReg()         );  // v   iarg6
  99   reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
 100   reg_def R9   ( SOC, SOC, Op_RegI,  9, R9->as_VMReg()         );  // v   iarg7
 101   reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
 102   reg_def R10  ( SOC, SOC, Op_RegI, 10, R10->as_VMReg()        );  // v   iarg8
 103   reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
 104   reg_def R11  ( SOC, SOC, Op_RegI, 11, R11->as_VMReg()        );  // v   ENV / scratch
 105   reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
 106   reg_def R12  ( SOC, SOC, Op_RegI, 12, R12->as_VMReg()        );  // v   scratch
 107   reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
 108   reg_def R13  ( NS,  NS,  Op_RegI, 13, R13->as_VMReg()        );  // s   system thread id
 109   reg_def R13_H( NS,  NS,  Op_RegI, 99, R13->as_VMReg()->next());
 110   reg_def R14  ( SOC, SOE, Op_RegI, 14, R14->as_VMReg()        );  // nv
 111   reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
 112   reg_def R15  ( SOC, SOE, Op_RegI, 15, R15->as_VMReg()        );  // nv
 113   reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
 114   reg_def R16  ( SOC, SOE, Op_RegI, 16, R16->as_VMReg()        );  // nv
 115   reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
 116   reg_def R17  ( SOC, SOE, Op_RegI, 17, R17->as_VMReg()        );  // nv
 117   reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
 118   reg_def R18  ( SOC, SOE, Op_RegI, 18, R18->as_VMReg()        );  // nv
 119   reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
 120   reg_def R19  ( SOC, SOE, Op_RegI, 19, R19->as_VMReg()        );  // nv
 121   reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
 122   reg_def R20  ( SOC, SOE, Op_RegI, 20, R20->as_VMReg()        );  // nv
 123   reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
 124   reg_def R21  ( SOC, SOE, Op_RegI, 21, R21->as_VMReg()        );  // nv
 125   reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
 126   reg_def R22  ( SOC, SOE, Op_RegI, 22, R22->as_VMReg()        );  // nv
 127   reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
 128   reg_def R23  ( SOC, SOE, Op_RegI, 23, R23->as_VMReg()        );  // nv
 129   reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
 130   reg_def R24  ( SOC, SOE, Op_RegI, 24, R24->as_VMReg()        );  // nv
 131   reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
 132   reg_def R25  ( SOC, SOE, Op_RegI, 25, R25->as_VMReg()        );  // nv
 133   reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
 134   reg_def R26  ( SOC, SOE, Op_RegI, 26, R26->as_VMReg()        );  // nv
 135   reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
 136   reg_def R27  ( SOC, SOE, Op_RegI, 27, R27->as_VMReg()        );  // nv
 137   reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
 138   reg_def R28  ( SOC, SOE, Op_RegI, 28, R28->as_VMReg()        );  // nv
 139   reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
 140   reg_def R29  ( SOC, SOE, Op_RegI, 29, R29->as_VMReg()        );  // nv
 141   reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
 142   reg_def R30  ( SOC, SOE, Op_RegI, 30, R30->as_VMReg()        );  // nv
 143   reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
 144   reg_def R31  ( SOC, SOE, Op_RegI, 31, R31->as_VMReg()        );  // nv
 145   reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
 146 
 147 
 148 // ----------------------------
 149 // Float/Double Registers
 150 // ----------------------------
 151 
 152   // Double Registers
 153   // The rules of ADL require that double registers be defined in pairs.
 154   // Each pair must be two 32-bit values, but not necessarily a pair of
 155   // single float registers. In each pair, ADLC-assigned register numbers
 156   // must be adjacent, with the lower number even. Finally, when the
 157   // CPU stores such a register pair to memory, the word associated with
 158   // the lower ADLC-assigned number must be stored to the lower address.
 159 
 160   // PPC64 has 32 64-bit floating-point registers. Each can store a single
 161   // or double precision floating-point value.
 162 
 163   // types: v = volatile, nv = non-volatile, s = system
 164   reg_def F0   ( SOC, SOC, Op_RegF,  0, F0->as_VMReg()         );  // v   scratch
 165   reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
 166   reg_def F1   ( SOC, SOC, Op_RegF,  1, F1->as_VMReg()         );  // v   farg1 & fret
 167   reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
 168   reg_def F2   ( SOC, SOC, Op_RegF,  2, F2->as_VMReg()         );  // v   farg2
 169   reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
 170   reg_def F3   ( SOC, SOC, Op_RegF,  3, F3->as_VMReg()         );  // v   farg3
 171   reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
 172   reg_def F4   ( SOC, SOC, Op_RegF,  4, F4->as_VMReg()         );  // v   farg4
 173   reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
 174   reg_def F5   ( SOC, SOC, Op_RegF,  5, F5->as_VMReg()         );  // v   farg5
 175   reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
 176   reg_def F6   ( SOC, SOC, Op_RegF,  6, F6->as_VMReg()         );  // v   farg6
 177   reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
 178   reg_def F7   ( SOC, SOC, Op_RegF,  7, F7->as_VMReg()         );  // v   farg7
 179   reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
 180   reg_def F8   ( SOC, SOC, Op_RegF,  8, F8->as_VMReg()         );  // v   farg8
 181   reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
 182   reg_def F9   ( SOC, SOC, Op_RegF,  9, F9->as_VMReg()         );  // v   farg9
 183   reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
 184   reg_def F10  ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()        );  // v   farg10
 185   reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
 186   reg_def F11  ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()        );  // v   farg11
 187   reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
 188   reg_def F12  ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()        );  // v   farg12
 189   reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
 190   reg_def F13  ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()        );  // v   farg13
 191   reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
 192   reg_def F14  ( SOC, SOE, Op_RegF, 14, F14->as_VMReg()        );  // nv
 193   reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
 194   reg_def F15  ( SOC, SOE, Op_RegF, 15, F15->as_VMReg()        );  // nv
 195   reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
 196   reg_def F16  ( SOC, SOE, Op_RegF, 16, F16->as_VMReg()        );  // nv
 197   reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
 198   reg_def F17  ( SOC, SOE, Op_RegF, 17, F17->as_VMReg()        );  // nv
 199   reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
 200   reg_def F18  ( SOC, SOE, Op_RegF, 18, F18->as_VMReg()        );  // nv
 201   reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
 202   reg_def F19  ( SOC, SOE, Op_RegF, 19, F19->as_VMReg()        );  // nv
 203   reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
 204   reg_def F20  ( SOC, SOE, Op_RegF, 20, F20->as_VMReg()        );  // nv
 205   reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
 206   reg_def F21  ( SOC, SOE, Op_RegF, 21, F21->as_VMReg()        );  // nv
 207   reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
 208   reg_def F22  ( SOC, SOE, Op_RegF, 22, F22->as_VMReg()        );  // nv
 209   reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
 210   reg_def F23  ( SOC, SOE, Op_RegF, 23, F23->as_VMReg()        );  // nv
 211   reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
 212   reg_def F24  ( SOC, SOE, Op_RegF, 24, F24->as_VMReg()        );  // nv
 213   reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
 214   reg_def F25  ( SOC, SOE, Op_RegF, 25, F25->as_VMReg()        );  // nv
 215   reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
 216   reg_def F26  ( SOC, SOE, Op_RegF, 26, F26->as_VMReg()        );  // nv
 217   reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
 218   reg_def F27  ( SOC, SOE, Op_RegF, 27, F27->as_VMReg()        );  // nv
 219   reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
 220   reg_def F28  ( SOC, SOE, Op_RegF, 28, F28->as_VMReg()        );  // nv
 221   reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
 222   reg_def F29  ( SOC, SOE, Op_RegF, 29, F29->as_VMReg()        );  // nv
 223   reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
 224   reg_def F30  ( SOC, SOE, Op_RegF, 30, F30->as_VMReg()        );  // nv
 225   reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
 226   reg_def F31  ( SOC, SOE, Op_RegF, 31, F31->as_VMReg()        );  // nv
 227   reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
 228 
 229 // ----------------------------
 230 // Special Registers
 231 // ----------------------------
 232 
 233 // Condition Codes Flag Registers
 234 
 235   // PPC64 has 8 condition code "registers" which are all contained
 236   // in the CR register.
 237 
 238   // types: v = volatile, nv = non-volatile, s = system
 239   reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg());  // v
 240   reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg());  // v
 241   reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg());  // nv
 242   reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg());  // nv
 243   reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg());  // nv
 244   reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg());  // v
 245   reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg());  // v
 246   reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg());  // v
 247 
 248   // Special registers of PPC64
 249 
 250   reg_def SR_XER(    SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg());     // v
 251   reg_def SR_LR(     SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg());      // v
 252   reg_def SR_CTR(    SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg());     // v
 253   reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg());  // v
 254   reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
 255   reg_def SR_PPR(    SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg());     // v
 256 
 257 // ----------------------------
 258 // Vector-Scalar Registers
 259 // ----------------------------
 260   reg_def VSR0 ( SOC, SOC, Op_VecX, 0, NULL);
 261   reg_def VSR1 ( SOC, SOC, Op_VecX, 1, NULL);
 262   reg_def VSR2 ( SOC, SOC, Op_VecX, 2, NULL);
 263   reg_def VSR3 ( SOC, SOC, Op_VecX, 3, NULL);
 264   reg_def VSR4 ( SOC, SOC, Op_VecX, 4, NULL);
 265   reg_def VSR5 ( SOC, SOC, Op_VecX, 5, NULL);
 266   reg_def VSR6 ( SOC, SOC, Op_VecX, 6, NULL);
 267   reg_def VSR7 ( SOC, SOC, Op_VecX, 7, NULL);
 268   reg_def VSR8 ( SOC, SOC, Op_VecX, 8, NULL);
 269   reg_def VSR9 ( SOC, SOC, Op_VecX, 9, NULL);
 270   reg_def VSR10 ( SOC, SOC, Op_VecX, 10, NULL);
 271   reg_def VSR11 ( SOC, SOC, Op_VecX, 11, NULL);
 272   reg_def VSR12 ( SOC, SOC, Op_VecX, 12, NULL);
 273   reg_def VSR13 ( SOC, SOC, Op_VecX, 13, NULL);
 274   reg_def VSR14 ( SOC, SOC, Op_VecX, 14, NULL);
 275   reg_def VSR15 ( SOC, SOC, Op_VecX, 15, NULL);
 276   reg_def VSR16 ( SOC, SOC, Op_VecX, 16, NULL);
 277   reg_def VSR17 ( SOC, SOC, Op_VecX, 17, NULL);
 278   reg_def VSR18 ( SOC, SOC, Op_VecX, 18, NULL);
 279   reg_def VSR19 ( SOC, SOC, Op_VecX, 19, NULL);
 280   reg_def VSR20 ( SOC, SOC, Op_VecX, 20, NULL);
 281   reg_def VSR21 ( SOC, SOC, Op_VecX, 21, NULL);
 282   reg_def VSR22 ( SOC, SOC, Op_VecX, 22, NULL);
 283   reg_def VSR23 ( SOC, SOC, Op_VecX, 23, NULL);
 284   reg_def VSR24 ( SOC, SOC, Op_VecX, 24, NULL);
 285   reg_def VSR25 ( SOC, SOC, Op_VecX, 25, NULL);
 286   reg_def VSR26 ( SOC, SOC, Op_VecX, 26, NULL);
 287   reg_def VSR27 ( SOC, SOC, Op_VecX, 27, NULL);
 288   reg_def VSR28 ( SOC, SOC, Op_VecX, 28, NULL);
 289   reg_def VSR29 ( SOC, SOC, Op_VecX, 29, NULL);
 290   reg_def VSR30 ( SOC, SOC, Op_VecX, 30, NULL);
 291   reg_def VSR31 ( SOC, SOC, Op_VecX, 31, NULL);
 292   reg_def VSR32 ( SOC, SOC, Op_VecX, 32, NULL);
 293   reg_def VSR33 ( SOC, SOC, Op_VecX, 33, NULL);
 294   reg_def VSR34 ( SOC, SOC, Op_VecX, 34, NULL);
 295   reg_def VSR35 ( SOC, SOC, Op_VecX, 35, NULL);
 296   reg_def VSR36 ( SOC, SOC, Op_VecX, 36, NULL);
 297   reg_def VSR37 ( SOC, SOC, Op_VecX, 37, NULL);
 298   reg_def VSR38 ( SOC, SOC, Op_VecX, 38, NULL);
 299   reg_def VSR39 ( SOC, SOC, Op_VecX, 39, NULL);
 300   reg_def VSR40 ( SOC, SOC, Op_VecX, 40, NULL);
 301   reg_def VSR41 ( SOC, SOC, Op_VecX, 41, NULL);
 302   reg_def VSR42 ( SOC, SOC, Op_VecX, 42, NULL);
 303   reg_def VSR43 ( SOC, SOC, Op_VecX, 43, NULL);
 304   reg_def VSR44 ( SOC, SOC, Op_VecX, 44, NULL);
 305   reg_def VSR45 ( SOC, SOC, Op_VecX, 45, NULL);
 306   reg_def VSR46 ( SOC, SOC, Op_VecX, 46, NULL);
 307   reg_def VSR47 ( SOC, SOC, Op_VecX, 47, NULL);
 308   reg_def VSR48 ( SOC, SOC, Op_VecX, 48, NULL);
 309   reg_def VSR49 ( SOC, SOC, Op_VecX, 49, NULL);
 310   reg_def VSR50 ( SOC, SOC, Op_VecX, 50, NULL);
 311   reg_def VSR51 ( SOC, SOC, Op_VecX, 51, NULL);
 312   reg_def VSR52 ( SOC, SOC, Op_VecX, 52, NULL);
 313   reg_def VSR53 ( SOC, SOC, Op_VecX, 53, NULL);
 314   reg_def VSR54 ( SOC, SOC, Op_VecX, 54, NULL);
 315   reg_def VSR55 ( SOC, SOC, Op_VecX, 55, NULL);
 316   reg_def VSR56 ( SOC, SOC, Op_VecX, 56, NULL);
 317   reg_def VSR57 ( SOC, SOC, Op_VecX, 57, NULL);
 318   reg_def VSR58 ( SOC, SOC, Op_VecX, 58, NULL);
 319   reg_def VSR59 ( SOC, SOC, Op_VecX, 59, NULL);
 320   reg_def VSR60 ( SOC, SOC, Op_VecX, 60, NULL);
 321   reg_def VSR61 ( SOC, SOC, Op_VecX, 61, NULL);
 322   reg_def VSR62 ( SOC, SOC, Op_VecX, 62, NULL);
 323   reg_def VSR63 ( SOC, SOC, Op_VecX, 63, NULL);
 324 
 325 // ----------------------------
 326 // Specify priority of register selection within phases of register
 327 // allocation. Highest priority is first. A useful heuristic is to
 328 // give registers a low priority when they are required by machine
 329 // instructions, like EAX and EDX on I486, and choose no-save registers
 330 // before save-on-call, & save-on-call before save-on-entry. Registers
 331 // which participate in fixed calling sequences should come last.
 332 // Registers which are used as pairs must fall on an even boundary.
 333 
 334 // It's worth about 1% on SPEC geomean to get this right.
 335 
 336 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 337 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
 338 // R3_num. Therefore, R3_num may not be (and in reality is not)
 339 // the same as R3->encoding()! Furthermore, we cannot make any
 340 // assumptions on ordering, e.g. R3_num may be less than R2_num.
 341 // Additionally, the function
 342 //   static enum RC rc_class(OptoReg::Name reg )
 343 // maps a given <register>_num value to its chunk type (except for flags)
 344 // and its current implementation relies on chunk0 and chunk1 having a
 345 // size of 64 each.
 346 
 347 // If you change this allocation class, please have a look at the
 348 // default values for the parameters RoundRobinIntegerRegIntervalStart
 349 // and RoundRobinFloatRegIntervalStart
 350 
 351 alloc_class chunk0 (
 352   // Chunk0 contains *all* 64 integer registers halves.
 353 
 354   // "non-volatile" registers
 355   R14, R14_H,
 356   R15, R15_H,
 357   R17, R17_H,
 358   R18, R18_H,
 359   R19, R19_H,
 360   R20, R20_H,
 361   R21, R21_H,
 362   R22, R22_H,
 363   R23, R23_H,
 364   R24, R24_H,
 365   R25, R25_H,
 366   R26, R26_H,
 367   R27, R27_H,
 368   R28, R28_H,
 369   R29, R29_H,
 370   R30, R30_H,
 371   R31, R31_H,
 372 
 373   // scratch/special registers
 374   R11, R11_H,
 375   R12, R12_H,
 376 
 377   // argument registers
 378   R10, R10_H,
 379   R9,  R9_H,
 380   R8,  R8_H,
 381   R7,  R7_H,
 382   R6,  R6_H,
 383   R5,  R5_H,
 384   R4,  R4_H,
 385   R3,  R3_H,
 386 
 387   // special registers, not available for allocation
 388   R16, R16_H,     // R16_thread
 389   R13, R13_H,     // system thread id
 390   R2,  R2_H,      // may be used for TOC
 391   R1,  R1_H,      // SP
 392   R0,  R0_H       // R0 (scratch)
 393 );
 394 
 395 // If you change this allocation class, please have a look at the
 396 // default values for the parameters RoundRobinIntegerRegIntervalStart
 397 // and RoundRobinFloatRegIntervalStart
 398 
 399 alloc_class chunk1 (
 400   // Chunk1 contains *all* 64 floating-point registers halves.
 401 
 402   // scratch register
 403   F0,  F0_H,
 404 
 405   // argument registers
 406   F13, F13_H,
 407   F12, F12_H,
 408   F11, F11_H,
 409   F10, F10_H,
 410   F9,  F9_H,
 411   F8,  F8_H,
 412   F7,  F7_H,
 413   F6,  F6_H,
 414   F5,  F5_H,
 415   F4,  F4_H,
 416   F3,  F3_H,
 417   F2,  F2_H,
 418   F1,  F1_H,
 419 
 420   // non-volatile registers
 421   F14, F14_H,
 422   F15, F15_H,
 423   F16, F16_H,
 424   F17, F17_H,
 425   F18, F18_H,
 426   F19, F19_H,
 427   F20, F20_H,
 428   F21, F21_H,
 429   F22, F22_H,
 430   F23, F23_H,
 431   F24, F24_H,
 432   F25, F25_H,
 433   F26, F26_H,
 434   F27, F27_H,
 435   F28, F28_H,
 436   F29, F29_H,
 437   F30, F30_H,
 438   F31, F31_H
 439 );
 440 
 441 alloc_class chunk2 (
 442   // Chunk2 contains *all* 8 condition code registers.
 443 
 444   CCR0,
 445   CCR1,
 446   CCR2,
 447   CCR3,
 448   CCR4,
 449   CCR5,
 450   CCR6,
 451   CCR7
 452 );
 453 
 454 alloc_class chunk3 (
 455   VSR0,
 456   VSR1,
 457   VSR2,
 458   VSR3,
 459   VSR4,
 460   VSR5,
 461   VSR6,
 462   VSR7,
 463   VSR8,
 464   VSR9,
 465   VSR10,
 466   VSR11,
 467   VSR12,
 468   VSR13,
 469   VSR14,
 470   VSR15,
 471   VSR16,
 472   VSR17,
 473   VSR18,
 474   VSR19,
 475   VSR20,
 476   VSR21,
 477   VSR22,
 478   VSR23,
 479   VSR24,
 480   VSR25,
 481   VSR26,
 482   VSR27,
 483   VSR28,
 484   VSR29,
 485   VSR30,
 486   VSR31,
 487   VSR32,
 488   VSR33,
 489   VSR34,
 490   VSR35,
 491   VSR36,
 492   VSR37,
 493   VSR38,
 494   VSR39,
 495   VSR40,
 496   VSR41,
 497   VSR42,
 498   VSR43,
 499   VSR44,
 500   VSR45,
 501   VSR46,
 502   VSR47,
 503   VSR48,
 504   VSR49,
 505   VSR50,
 506   VSR51,
 507   VSR52,
 508   VSR53,
 509   VSR54,
 510   VSR55,
 511   VSR56,
 512   VSR57,
 513   VSR58,
 514   VSR59,
 515   VSR60,
 516   VSR61,
 517   VSR62,
 518   VSR63
 519 );
 520 
 521 alloc_class chunk4 (
 522   // special registers
 523   // These registers are not allocated, but used for nodes generated by postalloc expand.
 524   SR_XER,
 525   SR_LR,
 526   SR_CTR,
 527   SR_VRSAVE,
 528   SR_SPEFSCR,
 529   SR_PPR
 530 );
 531 
 532 //-------Architecture Description Register Classes-----------------------
 533 
 534 // Several register classes are automatically defined based upon
 535 // information in this architecture description.
 536 
 537 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 538 // 2) reg_class compiler_method_oop_reg    ( as defined in frame section )
 539 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 540 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 541 //
 542 
 543 // ----------------------------
 544 // 32 Bit Register Classes
 545 // ----------------------------
 546 
 547 // We specify registers twice, once as read/write, and once read-only.
 548 // We use the read-only registers for source operands. With this, we
 549 // can include preset read only registers in this class, as a hard-coded
 550 // '0'-register. (We used to simulate this on ppc.)
 551 
 552 // 32 bit registers that can be read and written i.e. these registers
 553 // can be dest (or src) of normal instructions.
 554 reg_class bits32_reg_rw(
 555 /*R0*/              // R0
 556 /*R1*/              // SP
 557   R2,               // TOC
 558   R3,
 559   R4,
 560   R5,
 561   R6,
 562   R7,
 563   R8,
 564   R9,
 565   R10,
 566   R11,
 567   R12,
 568 /*R13*/             // system thread id
 569   R14,
 570   R15,
 571 /*R16*/             // R16_thread
 572   R17,
 573   R18,
 574   R19,
 575   R20,
 576   R21,
 577   R22,
 578   R23,
 579   R24,
 580   R25,
 581   R26,
 582   R27,
 583   R28,
 584 /*R29,*/             // global TOC
 585   R30,
 586   R31
 587 );
 588 
 589 // 32 bit registers that can only be read i.e. these registers can
 590 // only be src of all instructions.
 591 reg_class bits32_reg_ro(
 592 /*R0*/              // R0
 593 /*R1*/              // SP
 594   R2                // TOC
 595   R3,
 596   R4,
 597   R5,
 598   R6,
 599   R7,
 600   R8,
 601   R9,
 602   R10,
 603   R11,
 604   R12,
 605 /*R13*/             // system thread id
 606   R14,
 607   R15,
 608 /*R16*/             // R16_thread
 609   R17,
 610   R18,
 611   R19,
 612   R20,
 613   R21,
 614   R22,
 615   R23,
 616   R24,
 617   R25,
 618   R26,
 619   R27,
 620   R28,
 621 /*R29,*/
 622   R30,
 623   R31
 624 );
 625 
 626 reg_class rscratch1_bits32_reg(R11);
 627 reg_class rscratch2_bits32_reg(R12);
 628 reg_class rarg1_bits32_reg(R3);
 629 reg_class rarg2_bits32_reg(R4);
 630 reg_class rarg3_bits32_reg(R5);
 631 reg_class rarg4_bits32_reg(R6);
 632 
 633 // ----------------------------
 634 // 64 Bit Register Classes
 635 // ----------------------------
 636 // 64-bit build means 64-bit pointers means hi/lo pairs
 637 
 638 reg_class rscratch1_bits64_reg(R11_H, R11);
 639 reg_class rscratch2_bits64_reg(R12_H, R12);
 640 reg_class rarg1_bits64_reg(R3_H, R3);
 641 reg_class rarg2_bits64_reg(R4_H, R4);
 642 reg_class rarg3_bits64_reg(R5_H, R5);
 643 reg_class rarg4_bits64_reg(R6_H, R6);
 644 // Thread register, 'written' by tlsLoadP, see there.
 645 reg_class thread_bits64_reg(R16_H, R16);
 646 
 647 reg_class r19_bits64_reg(R19_H, R19);
 648 
 649 // 64 bit registers that can be read and written i.e. these registers
 650 // can be dest (or src) of normal instructions.
 651 reg_class bits64_reg_rw(
 652 /*R0_H,  R0*/     // R0
 653 /*R1_H,  R1*/     // SP
 654   R2_H,  R2,      // TOC
 655   R3_H,  R3,
 656   R4_H,  R4,
 657   R5_H,  R5,
 658   R6_H,  R6,
 659   R7_H,  R7,
 660   R8_H,  R8,
 661   R9_H,  R9,
 662   R10_H, R10,
 663   R11_H, R11,
 664   R12_H, R12,
 665 /*R13_H, R13*/   // system thread id
 666   R14_H, R14,
 667   R15_H, R15,
 668 /*R16_H, R16*/   // R16_thread
 669   R17_H, R17,
 670   R18_H, R18,
 671   R19_H, R19,
 672   R20_H, R20,
 673   R21_H, R21,
 674   R22_H, R22,
 675   R23_H, R23,
 676   R24_H, R24,
 677   R25_H, R25,
 678   R26_H, R26,
 679   R27_H, R27,
 680   R28_H, R28,
 681 /*R29_H, R29,*/
 682   R30_H, R30,
 683   R31_H, R31
 684 );
 685 
 686 // 64 bit registers used excluding r2, r11 and r12
 687 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
 688 // r2, r11 and r12 internally.
 689 reg_class bits64_reg_leaf_call(
 690 /*R0_H,  R0*/     // R0
 691 /*R1_H,  R1*/     // SP
 692 /*R2_H,  R2*/     // TOC
 693   R3_H,  R3,
 694   R4_H,  R4,
 695   R5_H,  R5,
 696   R6_H,  R6,
 697   R7_H,  R7,
 698   R8_H,  R8,
 699   R9_H,  R9,
 700   R10_H, R10,
 701 /*R11_H, R11*/
 702 /*R12_H, R12*/
 703 /*R13_H, R13*/   // system thread id
 704   R14_H, R14,
 705   R15_H, R15,
 706 /*R16_H, R16*/   // R16_thread
 707   R17_H, R17,
 708   R18_H, R18,
 709   R19_H, R19,
 710   R20_H, R20,
 711   R21_H, R21,
 712   R22_H, R22,
 713   R23_H, R23,
 714   R24_H, R24,
 715   R25_H, R25,
 716   R26_H, R26,
 717   R27_H, R27,
 718   R28_H, R28,
 719 /*R29_H, R29,*/
 720   R30_H, R30,
 721   R31_H, R31
 722 );
 723 
 724 // Used to hold the TOC to avoid collisions with expanded DynamicCall
 725 // which uses r19 as inline cache internally and expanded LeafCall which uses
 726 // r2, r11 and r12 internally.
 727 reg_class bits64_constant_table_base(
 728 /*R0_H,  R0*/     // R0
 729 /*R1_H,  R1*/     // SP
 730 /*R2_H,  R2*/     // TOC
 731   R3_H,  R3,
 732   R4_H,  R4,
 733   R5_H,  R5,
 734   R6_H,  R6,
 735   R7_H,  R7,
 736   R8_H,  R8,
 737   R9_H,  R9,
 738   R10_H, R10,
 739 /*R11_H, R11*/
 740 /*R12_H, R12*/
 741 /*R13_H, R13*/   // system thread id
 742   R14_H, R14,
 743   R15_H, R15,
 744 /*R16_H, R16*/   // R16_thread
 745   R17_H, R17,
 746   R18_H, R18,
 747 /*R19_H, R19*/
 748   R20_H, R20,
 749   R21_H, R21,
 750   R22_H, R22,
 751   R23_H, R23,
 752   R24_H, R24,
 753   R25_H, R25,
 754   R26_H, R26,
 755   R27_H, R27,
 756   R28_H, R28,
 757 /*R29_H, R29,*/
 758   R30_H, R30,
 759   R31_H, R31
 760 );
 761 
 762 // 64 bit registers that can only be read i.e. these registers can
 763 // only be src of all instructions.
 764 reg_class bits64_reg_ro(
 765 /*R0_H,  R0*/     // R0
 766   R1_H,  R1,
 767   R2_H,  R2,       // TOC
 768   R3_H,  R3,
 769   R4_H,  R4,
 770   R5_H,  R5,
 771   R6_H,  R6,
 772   R7_H,  R7,
 773   R8_H,  R8,
 774   R9_H,  R9,
 775   R10_H, R10,
 776   R11_H, R11,
 777   R12_H, R12,
 778 /*R13_H, R13*/   // system thread id
 779   R14_H, R14,
 780   R15_H, R15,
 781   R16_H, R16,    // R16_thread
 782   R17_H, R17,
 783   R18_H, R18,
 784   R19_H, R19,
 785   R20_H, R20,
 786   R21_H, R21,
 787   R22_H, R22,
 788   R23_H, R23,
 789   R24_H, R24,
 790   R25_H, R25,
 791   R26_H, R26,
 792   R27_H, R27,
 793   R28_H, R28,
 794 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
 795   R30_H, R30,
 796   R31_H, R31
 797 );
 798 
 799 
 800 // ----------------------------
 801 // Special Class for Condition Code Flags Register
 802 
 803 reg_class int_flags(
 804 /*CCR0*/             // scratch
 805 /*CCR1*/             // scratch
 806 /*CCR2*/             // nv!
 807 /*CCR3*/             // nv!
 808 /*CCR4*/             // nv!
 809   CCR5,
 810   CCR6,
 811   CCR7
 812 );
 813 
 814 reg_class int_flags_ro(
 815   CCR0,
 816   CCR1,
 817   CCR2,
 818   CCR3,
 819   CCR4,
 820   CCR5,
 821   CCR6,
 822   CCR7
 823 );
 824 
 825 reg_class int_flags_CR0(CCR0);
 826 reg_class int_flags_CR1(CCR1);
 827 reg_class int_flags_CR6(CCR6);
 828 reg_class ctr_reg(SR_CTR);
 829 
 830 // ----------------------------
 831 // Float Register Classes
 832 // ----------------------------
 833 
 834 reg_class flt_reg(
 835   F0,
 836   F1,
 837   F2,
 838   F3,
 839   F4,
 840   F5,
 841   F6,
 842   F7,
 843   F8,
 844   F9,
 845   F10,
 846   F11,
 847   F12,
 848   F13,
 849   F14,              // nv!
 850   F15,              // nv!
 851   F16,              // nv!
 852   F17,              // nv!
 853   F18,              // nv!
 854   F19,              // nv!
 855   F20,              // nv!
 856   F21,              // nv!
 857   F22,              // nv!
 858   F23,              // nv!
 859   F24,              // nv!
 860   F25,              // nv!
 861   F26,              // nv!
 862   F27,              // nv!
 863   F28,              // nv!
 864   F29,              // nv!
 865   F30,              // nv!
 866   F31               // nv!
 867 );
 868 
 869 // Double precision float registers have virtual `high halves' that
 870 // are needed by the allocator.
 871 reg_class dbl_reg(
 872   F0,  F0_H,
 873   F1,  F1_H,
 874   F2,  F2_H,
 875   F3,  F3_H,
 876   F4,  F4_H,
 877   F5,  F5_H,
 878   F6,  F6_H,
 879   F7,  F7_H,
 880   F8,  F8_H,
 881   F9,  F9_H,
 882   F10, F10_H,
 883   F11, F11_H,
 884   F12, F12_H,
 885   F13, F13_H,
 886   F14, F14_H,    // nv!
 887   F15, F15_H,    // nv!
 888   F16, F16_H,    // nv!
 889   F17, F17_H,    // nv!
 890   F18, F18_H,    // nv!
 891   F19, F19_H,    // nv!
 892   F20, F20_H,    // nv!
 893   F21, F21_H,    // nv!
 894   F22, F22_H,    // nv!
 895   F23, F23_H,    // nv!
 896   F24, F24_H,    // nv!
 897   F25, F25_H,    // nv!
 898   F26, F26_H,    // nv!
 899   F27, F27_H,    // nv!
 900   F28, F28_H,    // nv!
 901   F29, F29_H,    // nv!
 902   F30, F30_H,    // nv!
 903   F31, F31_H     // nv!
 904 );
 905 
 906 // ----------------------------
 907 // Vector-Scalar Register Class
 908 // ----------------------------
 909 
 910 reg_class vs_reg(
 911   VSR32,
 912   VSR33,
 913   VSR34,
 914   VSR35,
 915   VSR36,
 916   VSR37,
 917   VSR38,
 918   VSR39,
 919   VSR40,
 920   VSR41,
 921   VSR42,
 922   VSR43,
 923   VSR44,
 924   VSR45,
 925   VSR46,
 926   VSR47,
 927   VSR48,
 928   VSR49,
 929   VSR50,
 930   VSR51
 931 //  VSR52,     // nv!
 932 //  VSR53,     // nv!
 933 //  VSR54,     // nv!
 934 //  VSR55,     // nv!
 935 //  VSR56,     // nv!
 936 //  VSR57,     // nv!
 937 //  VSR58,     // nv!
 938 //  VSR59,     // nv!
 939 //  VSR60,     // nv!
 940 //  VSR61,     // nv!
 941 //  VSR62,     // nv!
 942 //  VSR63      // nv!
 943 );
 944 
 945  %}
 946 
 947 //----------DEFINITION BLOCK---------------------------------------------------
 948 // Define name --> value mappings to inform the ADLC of an integer valued name
 949 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 950 // Format:
 951 //        int_def  <name>         ( <int_value>, <expression>);
 952 // Generated Code in ad_<arch>.hpp
 953 //        #define  <name>   (<expression>)
 954 //        // value == <int_value>
 955 // Generated code in ad_<arch>.cpp adlc_verification()
 956 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 957 //
 958 definitions %{
 959   // The default cost (of an ALU instruction).
 960   int_def DEFAULT_COST_LOW        (     30,      30);
 961   int_def DEFAULT_COST            (    100,     100);
 962   int_def HUGE_COST               (1000000, 1000000);
 963 
 964   // Memory refs
 965   int_def MEMORY_REF_COST_LOW     (    200, DEFAULT_COST * 2);
 966   int_def MEMORY_REF_COST         (    300, DEFAULT_COST * 3);
 967 
 968   // Branches are even more expensive.
 969   int_def BRANCH_COST             (    900, DEFAULT_COST * 9);
 970   int_def CALL_COST               (   1300, DEFAULT_COST * 13);
 971 %}
 972 
 973 
 974 //----------SOURCE BLOCK-------------------------------------------------------
 975 // This is a block of C++ code which provides values, functions, and
 976 // definitions necessary in the rest of the architecture description.
 977 source_hpp %{
 978   // Header information of the source block.
 979   // Method declarations/definitions which are used outside
 980   // the ad-scope can conveniently be defined here.
 981   //
 982   // To keep related declarations/definitions/uses close together,
 983   // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 984 
 985   // Returns true if Node n is followed by a MemBar node that
 986   // will do an acquire. If so, this node must not do the acquire
 987   // operation.
 988   bool followed_by_acquire(const Node *n);
 989 %}
 990 
 991 source %{
 992 
 993 // Should the Matcher clone shifts on addressing modes, expecting them
 994 // to be subsumed into complex addressing expressions or compute them
 995 // into registers?
 996 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 997   return clone_base_plus_offset_address(m, mstack, address_visited);
 998 }
 999 
1000 void Compile::reshape_address(AddPNode* addp) {
1001 }
1002 
1003 // Optimize load-acquire.
1004 //
1005 // Check if acquire is unnecessary due to following operation that does
1006 // acquire anyways.
1007 // Walk the pattern:
1008 //
1009 //      n: Load.acq
1010 //           |
1011 //      MemBarAcquire
1012 //       |         |
1013 //  Proj(ctrl)  Proj(mem)
1014 //       |         |
1015 //   MemBarRelease/Volatile
1016 //
1017 bool followed_by_acquire(const Node *load) {
1018   assert(load->is_Load(), "So far implemented only for loads.");
1019 
1020   // Find MemBarAcquire.
1021   const Node *mba = NULL;
1022   for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
1023     const Node *out = load->fast_out(i);
1024     if (out->Opcode() == Op_MemBarAcquire) {
1025       if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
1026       mba = out;
1027       break;
1028     }
1029   }
1030   if (!mba) return false;
1031 
1032   // Find following MemBar node.
1033   //
1034   // The following node must be reachable by control AND memory
1035   // edge to assure no other operations are in between the two nodes.
1036   //
1037   // So first get the Proj node, mem_proj, to use it to iterate forward.
1038   Node *mem_proj = NULL;
1039   for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
1040     mem_proj = mba->fast_out(i);      // Runs out of bounds and asserts if Proj not found.
1041     assert(mem_proj->is_Proj(), "only projections here");
1042     ProjNode *proj = mem_proj->as_Proj();
1043     if (proj->_con == TypeFunc::Memory &&
1044         !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
1045       break;
1046   }
1047   assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
1048 
1049   // Search MemBar behind Proj. If there are other memory operations
1050   // behind the Proj we lost.
1051   for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
1052     Node *x = mem_proj->fast_out(j);
1053     // Proj might have an edge to a store or load node which precedes the membar.
1054     if (x->is_Mem()) return false;
1055 
1056     // On PPC64 release and volatile are implemented by an instruction
1057     // that also has acquire semantics. I.e. there is no need for an
1058     // acquire before these.
1059     int xop = x->Opcode();
1060     if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
1061       // Make sure we're not missing Call/Phi/MergeMem by checking
1062       // control edges. The control edge must directly lead back
1063       // to the MemBarAcquire
1064       Node *ctrl_proj = x->in(0);
1065       if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
1066         return true;
1067       }
1068     }
1069   }
1070 
1071   return false;
1072 }
1073 
1074 #define __ _masm.
1075 
1076 // Tertiary op of a LoadP or StoreP encoding.
1077 #define REGP_OP true
1078 
1079 // ****************************************************************************
1080 
1081 // REQUIRED FUNCTIONALITY
1082 
1083 // !!!!! Special hack to get all type of calls to specify the byte offset
1084 //       from the start of the call to the point where the return address
1085 //       will point.
1086 
1087 // PPC port: Removed use of lazy constant construct.
1088 
1089 int MachCallStaticJavaNode::ret_addr_offset() {
1090   // It's only a single branch-and-link instruction.
1091   return 4;
1092 }
1093 
1094 int MachCallDynamicJavaNode::ret_addr_offset() {
1095   // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1096   // postalloc expanded calls if we use inline caches and do not update method data.
1097   if (UseInlineCaches)
1098     return 4;
1099 
1100   int vtable_index = this->_vtable_index;
1101   if (vtable_index < 0) {
1102     // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1103     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1104     return 12;
1105   } else {
1106     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1107     return 24;
1108   }
1109 }
1110 
1111 int MachCallRuntimeNode::ret_addr_offset() {
1112 #if defined(ABI_ELFv2)
1113   return 28;
1114 #else
1115   return 40;
1116 #endif
1117 }
1118 
1119 //=============================================================================
1120 
1121 // condition code conversions
1122 
1123 static int cc_to_boint(int cc) {
1124   return Assembler::bcondCRbiIs0 | (cc & 8);
1125 }
1126 
1127 static int cc_to_inverse_boint(int cc) {
1128   return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1129 }
1130 
1131 static int cc_to_biint(int cc, int flags_reg) {
1132   return (flags_reg << 2) | (cc & 3);
1133 }
1134 
1135 //=============================================================================
1136 
1137 // Compute padding required for nodes which need alignment. The padding
1138 // is the number of bytes (not instructions) which will be inserted before
1139 // the instruction. The padding must match the size of a NOP instruction.
1140 
1141 // Currently not used on this platform.
1142 
1143 //=============================================================================
1144 
1145 // Indicate if the safepoint node needs the polling page as an input.
1146 bool SafePointNode::needs_polling_address_input() {
1147   // The address is loaded from thread by a seperate node.
1148   return true;
1149 }
1150 
1151 //=============================================================================
1152 
1153 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1154 void emit_break(CodeBuffer &cbuf) {
1155   MacroAssembler _masm(&cbuf);
1156   __ illtrap();
1157 }
1158 
1159 #ifndef PRODUCT
1160 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1161   st->print("BREAKPOINT");
1162 }
1163 #endif
1164 
1165 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1166   emit_break(cbuf);
1167 }
1168 
1169 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1170   return MachNode::size(ra_);
1171 }
1172 
1173 //=============================================================================
1174 
1175 void emit_nop(CodeBuffer &cbuf) {
1176   MacroAssembler _masm(&cbuf);
1177   __ nop();
1178 }
1179 
1180 static inline void emit_long(CodeBuffer &cbuf, int value) {
1181   *((int*)(cbuf.insts_end())) = value;
1182   cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1183 }
1184 
1185 //=============================================================================
1186 
1187 %} // interrupt source
1188 
1189 source_hpp %{ // Header information of the source block.
1190 
1191 //--------------------------------------------------------------
1192 //---<  Used for optimization in Compile::Shorten_branches  >---
1193 //--------------------------------------------------------------
1194 
1195 class CallStubImpl {
1196 
1197  public:
1198 
1199   // Emit call stub, compiled java to interpreter.
1200   static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1201 
1202   // Size of call trampoline stub.
1203   // This doesn't need to be accurate to the byte, but it
1204   // must be larger than or equal to the real size of the stub.
1205   static uint size_call_trampoline() {
1206     return MacroAssembler::trampoline_stub_size;
1207   }
1208 
1209   // number of relocations needed by a call trampoline stub
1210   static uint reloc_call_trampoline() {
1211     return 5;
1212   }
1213 
1214 };
1215 
1216 %} // end source_hpp
1217 
1218 source %{
1219 
1220 // Emit a trampoline stub for a call to a target which is too far away.
1221 //
1222 // code sequences:
1223 //
1224 // call-site:
1225 //   branch-and-link to <destination> or <trampoline stub>
1226 //
1227 // Related trampoline stub for this call-site in the stub section:
1228 //   load the call target from the constant pool
1229 //   branch via CTR (LR/link still points to the call-site above)
1230 
1231 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1232   address stub = __ emit_trampoline_stub(destination_toc_offset, insts_call_instruction_offset);
1233   if (stub == NULL) {
1234     ciEnv::current()->record_out_of_memory_failure();
1235   }
1236 }
1237 
1238 //=============================================================================
1239 
1240 // Emit an inline branch-and-link call and a related trampoline stub.
1241 //
1242 // code sequences:
1243 //
1244 // call-site:
1245 //   branch-and-link to <destination> or <trampoline stub>
1246 //
1247 // Related trampoline stub for this call-site in the stub section:
1248 //   load the call target from the constant pool
1249 //   branch via CTR (LR/link still points to the call-site above)
1250 //
1251 
1252 typedef struct {
1253   int insts_call_instruction_offset;
1254   int ret_addr_offset;
1255 } EmitCallOffsets;
1256 
1257 // Emit a branch-and-link instruction that branches to a trampoline.
1258 // - Remember the offset of the branch-and-link instruction.
1259 // - Add a relocation at the branch-and-link instruction.
1260 // - Emit a branch-and-link.
1261 // - Remember the return pc offset.
1262 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1263   EmitCallOffsets offsets = { -1, -1 };
1264   const int start_offset = __ offset();
1265   offsets.insts_call_instruction_offset = __ offset();
1266 
1267   // No entry point given, use the current pc.
1268   if (entry_point == NULL) entry_point = __ pc();
1269 
1270   // Put the entry point as a constant into the constant pool.
1271   const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
1272   if (entry_point_toc_addr == NULL) {
1273     ciEnv::current()->record_out_of_memory_failure();
1274     return offsets;
1275   }
1276   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1277 
1278   // Emit the trampoline stub which will be related to the branch-and-link below.
1279   CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1280   if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1281   __ relocate(rtype);
1282 
1283   // Note: At this point we do not have the address of the trampoline
1284   // stub, and the entry point might be too far away for bl, so __ pc()
1285   // serves as dummy and the bl will be patched later.
1286   __ bl((address) __ pc());
1287 
1288   offsets.ret_addr_offset = __ offset() - start_offset;
1289 
1290   return offsets;
1291 }
1292 
1293 //=============================================================================
1294 
1295 // Factory for creating loadConL* nodes for large/small constant pool.
1296 
1297 static inline jlong replicate_immF(float con) {
1298   // Replicate float con 2 times and pack into vector.
1299   int val = *((int*)&con);
1300   jlong lval = val;
1301   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1302   return lval;
1303 }
1304 
1305 //=============================================================================
1306 
1307 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1308 int Compile::ConstantTable::calculate_table_base_offset() const {
1309   return 0;  // absolute addressing, no offset
1310 }
1311 
1312 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1313 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1314   iRegPdstOper *op_dst = new iRegPdstOper();
1315   MachNode *m1 = new loadToc_hiNode();
1316   MachNode *m2 = new loadToc_loNode();
1317 
1318   m1->add_req(NULL);
1319   m2->add_req(NULL, m1);
1320   m1->_opnds[0] = op_dst;
1321   m2->_opnds[0] = op_dst;
1322   m2->_opnds[1] = op_dst;
1323   ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1324   ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1325   nodes->push(m1);
1326   nodes->push(m2);
1327 }
1328 
1329 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1330   // Is postalloc expanded.
1331   ShouldNotReachHere();
1332 }
1333 
1334 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1335   return 0;
1336 }
1337 
1338 #ifndef PRODUCT
1339 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1340   st->print("-- \t// MachConstantBaseNode (empty encoding)");
1341 }
1342 #endif
1343 
1344 //=============================================================================
1345 
1346 #ifndef PRODUCT
1347 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1348   Compile* C = ra_->C;
1349   const long framesize = C->frame_slots() << LogBytesPerInt;
1350 
1351   st->print("PROLOG\n\t");
1352   if (C->need_stack_bang(framesize)) {
1353     st->print("stack_overflow_check\n\t");
1354   }
1355 
1356   if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1357     st->print("save return pc\n\t");
1358     st->print("push frame %ld\n\t", -framesize);
1359   }
1360 }
1361 #endif
1362 
1363 // Macro used instead of the common __ to emulate the pipes of PPC.
1364 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1365 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1366 // still no scheduling of this code is possible, the micro scheduler is aware of the
1367 // code and can update its internal data. The following mechanism is used to achieve this:
1368 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1369 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1370 #if 0 // TODO: PPC port
1371 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1372                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1373                 _masm.
1374 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1375                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1376 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling())                 \
1377                   C->hb_scheduling()->_pdScheduling->advance_offset
1378 #else
1379 #define ___(op) if (UsePower6SchedulerPPC64)                                          \
1380                   Unimplemented();                                                    \
1381                 _masm.
1382 #define ___stop if (UsePower6SchedulerPPC64)                                          \
1383                   Unimplemented()
1384 #define ___advance if (UsePower6SchedulerPPC64)                                       \
1385                   Unimplemented()
1386 #endif
1387 
1388 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1389   Compile* C = ra_->C;
1390   MacroAssembler _masm(&cbuf);
1391 
1392   const long framesize = C->frame_size_in_bytes();
1393   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1394 
1395   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1396 
1397   const Register return_pc            = R20; // Must match return_addr() in frame section.
1398   const Register callers_sp           = R21;
1399   const Register push_frame_temp      = R22;
1400   const Register toc_temp             = R23;
1401   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1402 
1403   if (method_is_frameless) {
1404     // Add nop at beginning of all frameless methods to prevent any
1405     // oop instructions from getting overwritten by make_not_entrant
1406     // (patching attempt would fail).
1407     ___(nop) nop();
1408   } else {
1409     // Get return pc.
1410     ___(mflr) mflr(return_pc);
1411   }
1412 
1413   // Calls to C2R adapters often do not accept exceptional returns.
1414   // We require that their callers must bang for them. But be
1415   // careful, because some VM calls (such as call site linkage) can
1416   // use several kilobytes of stack. But the stack safety zone should
1417   // account for that. See bugs 4446381, 4468289, 4497237.
1418 
1419   int bangsize = C->bang_size_in_bytes();
1420   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1421   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1422     // Unfortunately we cannot use the function provided in
1423     // assembler.cpp as we have to emulate the pipes. So I had to
1424     // insert the code of generate_stack_overflow_check(), see
1425     // assembler.cpp for some illuminative comments.
1426     const int page_size = os::vm_page_size();
1427     int bang_end = JavaThread::stack_shadow_zone_size();
1428 
1429     // This is how far the previous frame's stack banging extended.
1430     const int bang_end_safe = bang_end;
1431 
1432     if (bangsize > page_size) {
1433       bang_end += bangsize;
1434     }
1435 
1436     int bang_offset = bang_end_safe;
1437 
1438     while (bang_offset <= bang_end) {
1439       // Need at least one stack bang at end of shadow zone.
1440 
1441       // Again I had to copy code, this time from assembler_ppc.cpp,
1442       // bang_stack_with_offset - see there for comments.
1443 
1444       // Stack grows down, caller passes positive offset.
1445       assert(bang_offset > 0, "must bang with positive offset");
1446 
1447       long stdoffset = -bang_offset;
1448 
1449       if (Assembler::is_simm(stdoffset, 16)) {
1450         // Signed 16 bit offset, a simple std is ok.
1451         if (UseLoadInstructionsForStackBangingPPC64) {
1452           ___(ld) ld(R0,  (int)(signed short)stdoffset, R1_SP);
1453         } else {
1454           ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1455         }
1456       } else if (Assembler::is_simm(stdoffset, 31)) {
1457         // Use largeoffset calculations for addis & ld/std.
1458         const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1459         const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1460 
1461         Register tmp = R11;
1462         ___(addis) addis(tmp, R1_SP, hi);
1463         if (UseLoadInstructionsForStackBangingPPC64) {
1464           ___(ld) ld(R0, lo, tmp);
1465         } else {
1466           ___(std) std(R0, lo, tmp);
1467         }
1468       } else {
1469         ShouldNotReachHere();
1470       }
1471 
1472       bang_offset += page_size;
1473     }
1474     // R11 trashed
1475   } // C->need_stack_bang(framesize) && UseStackBanging
1476 
1477   unsigned int bytes = (unsigned int)framesize;
1478   long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1479   ciMethod *currMethod = C->method();
1480 
1481   // Optimized version for most common case.
1482   if (UsePower6SchedulerPPC64 &&
1483       !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1484       !(false /* ConstantsALot TODO: PPC port*/)) {
1485     ___(or) mr(callers_sp, R1_SP);
1486     ___(std) std(return_pc, _abi(lr), R1_SP);
1487     ___(stdu) stdu(R1_SP, -offset, R1_SP);
1488     return;
1489   }
1490 
1491   if (!method_is_frameless) {
1492     // Get callers sp.
1493     ___(or) mr(callers_sp, R1_SP);
1494 
1495     // Push method's frame, modifies SP.
1496     assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1497     // The ABI is already accounted for in 'framesize' via the
1498     // 'out_preserve' area.
1499     Register tmp = push_frame_temp;
1500     // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1501     if (Assembler::is_simm(-offset, 16)) {
1502       ___(stdu) stdu(R1_SP, -offset, R1_SP);
1503     } else {
1504       long x = -offset;
1505       // Had to insert load_const(tmp, -offset).
1506       ___(addis)  lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1507       ___(ori)    ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1508       ___(rldicr) sldi(tmp, tmp, 32);
1509       ___(oris)   oris(tmp, tmp, (x & 0xffff0000) >> 16);
1510       ___(ori)    ori( tmp, tmp, (x & 0x0000ffff));
1511 
1512       ___(stdux) stdux(R1_SP, R1_SP, tmp);
1513     }
1514   }
1515 #if 0 // TODO: PPC port
1516   // For testing large constant pools, emit a lot of constants to constant pool.
1517   // "Randomize" const_size.
1518   if (ConstantsALot) {
1519     const int num_consts = const_size();
1520     for (int i = 0; i < num_consts; i++) {
1521       __ long_constant(0xB0B5B00BBABE);
1522     }
1523   }
1524 #endif
1525   if (!method_is_frameless) {
1526     // Save return pc.
1527     ___(std) std(return_pc, _abi(lr), callers_sp);
1528   }
1529 
1530   C->set_frame_complete(cbuf.insts_size());
1531 }
1532 #undef ___
1533 #undef ___stop
1534 #undef ___advance
1535 
1536 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1537   // Variable size. determine dynamically.
1538   return MachNode::size(ra_);
1539 }
1540 
1541 int MachPrologNode::reloc() const {
1542   // Return number of relocatable values contained in this instruction.
1543   return 1; // 1 reloc entry for load_const(toc).
1544 }
1545 
1546 //=============================================================================
1547 
1548 #ifndef PRODUCT
1549 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1550   Compile* C = ra_->C;
1551 
1552   st->print("EPILOG\n\t");
1553   st->print("restore return pc\n\t");
1554   st->print("pop frame\n\t");
1555 
1556   if (do_polling() && C->is_method_compilation()) {
1557     st->print("touch polling page\n\t");
1558   }
1559 }
1560 #endif
1561 
1562 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1563   Compile* C = ra_->C;
1564   MacroAssembler _masm(&cbuf);
1565 
1566   const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1567   assert(framesize >= 0, "negative frame-size?");
1568 
1569   const bool method_needs_polling = do_polling() && C->is_method_compilation();
1570   const bool method_is_frameless  = false /* TODO: PPC port C->is_frameless_method()*/;
1571   const Register return_pc        = R31;  // Must survive C-call to enable_stack_reserved_zone().
1572   const Register polling_page     = R12;
1573 
1574   if (!method_is_frameless) {
1575     // Restore return pc relative to callers' sp.
1576     __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1577   }
1578 
1579   if (method_needs_polling) {
1580     if (SafepointMechanism::uses_thread_local_poll()) {
1581       __ ld(polling_page, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1582     } else {
1583       __ load_const_optimized(polling_page, (long)(address) os::get_polling_page());
1584     }
1585   }
1586 
1587   if (!method_is_frameless) {
1588     // Move return pc to LR.
1589     __ mtlr(return_pc);
1590     // Pop frame (fixed frame-size).
1591     __ addi(R1_SP, R1_SP, (int)framesize);
1592   }
1593 
1594   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1595     __ reserved_stack_check(return_pc);
1596   }
1597 
1598   if (method_needs_polling) {
1599     // We need to mark the code position where the load from the safepoint
1600     // polling page was emitted as relocInfo::poll_return_type here.
1601     __ relocate(relocInfo::poll_return_type);
1602     __ load_from_polling_page(polling_page);
1603   }
1604 }
1605 
1606 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1607   // Variable size. Determine dynamically.
1608   return MachNode::size(ra_);
1609 }
1610 
1611 int MachEpilogNode::reloc() const {
1612   // Return number of relocatable values contained in this instruction.
1613   return 1; // 1 for load_from_polling_page.
1614 }
1615 
1616 const Pipeline * MachEpilogNode::pipeline() const {
1617   return MachNode::pipeline_class();
1618 }
1619 
1620 // This method seems to be obsolete. It is declared in machnode.hpp
1621 // and defined in all *.ad files, but it is never called. Should we
1622 // get rid of it?
1623 int MachEpilogNode::safepoint_offset() const {
1624   assert(do_polling(), "no return for this epilog node");
1625   return 0;
1626 }
1627 
1628 #if 0 // TODO: PPC port
1629 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1630   MacroAssembler _masm(&cbuf);
1631   if (LoadPollAddressFromThread) {
1632     _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1633   } else {
1634     _masm.nop();
1635   }
1636 }
1637 
1638 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1639   if (LoadPollAddressFromThread) {
1640     return 4;
1641   } else {
1642     return 4;
1643   }
1644 }
1645 
1646 #ifndef PRODUCT
1647 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1648   st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1649 }
1650 #endif
1651 
1652 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1653   return RSCRATCH1_BITS64_REG_mask();
1654 }
1655 #endif // PPC port
1656 
1657 // =============================================================================
1658 
1659 // Figure out which register class each belongs in: rc_int, rc_float, rc_vs or
1660 // rc_stack.
1661 enum RC { rc_bad, rc_int, rc_float, rc_vs, rc_stack };
1662 
1663 static enum RC rc_class(OptoReg::Name reg) {
1664   // Return the register class for the given register. The given register
1665   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1666   // enumeration in adGlobals_ppc.hpp.
1667 
1668   if (reg == OptoReg::Bad) return rc_bad;
1669 
1670   // We have 64 integer register halves, starting at index 0.
1671   if (reg < 64) return rc_int;
1672 
1673   // We have 64 floating-point register halves, starting at index 64.
1674   if (reg < 64+64) return rc_float;
1675 
1676   // We have 64 vector-scalar registers, starting at index 128.
1677   if (reg < 64+64+64) return rc_vs;
1678 
1679   // Between float regs & stack are the flags regs.
1680   assert(OptoReg::is_stack(reg) || reg < 64+64+64, "blow up if spilling flags");
1681 
1682   return rc_stack;
1683 }
1684 
1685 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1686                         bool do_print, Compile* C, outputStream *st) {
1687 
1688   assert(opcode == Assembler::LD_OPCODE   ||
1689          opcode == Assembler::STD_OPCODE  ||
1690          opcode == Assembler::LWZ_OPCODE  ||
1691          opcode == Assembler::STW_OPCODE  ||
1692          opcode == Assembler::LFD_OPCODE  ||
1693          opcode == Assembler::STFD_OPCODE ||
1694          opcode == Assembler::LFS_OPCODE  ||
1695          opcode == Assembler::STFS_OPCODE,
1696          "opcode not supported");
1697 
1698   if (cbuf) {
1699     int d =
1700       (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1701         Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1702       : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1703     emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1704   }
1705 #ifndef PRODUCT
1706   else if (do_print) {
1707     st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1708               op_str,
1709               Matcher::regName[reg],
1710               offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1711   }
1712 #endif
1713   return 4; // size
1714 }
1715 
1716 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1717   Compile* C = ra_->C;
1718 
1719   // Get registers to move.
1720   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1721   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1722   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1723   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1724 
1725   enum RC src_hi_rc = rc_class(src_hi);
1726   enum RC src_lo_rc = rc_class(src_lo);
1727   enum RC dst_hi_rc = rc_class(dst_hi);
1728   enum RC dst_lo_rc = rc_class(dst_lo);
1729 
1730   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1731   if (src_hi != OptoReg::Bad)
1732     assert((src_lo&1)==0 && src_lo+1==src_hi &&
1733            (dst_lo&1)==0 && dst_lo+1==dst_hi,
1734            "expected aligned-adjacent pairs");
1735   // Generate spill code!
1736   int size = 0;
1737 
1738   if (src_lo == dst_lo && src_hi == dst_hi)
1739     return size;            // Self copy, no move.
1740 
1741   if (bottom_type()->isa_vect() != NULL && ideal_reg() == Op_VecX) {
1742     // Memory->Memory Spill.
1743     if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1744       int src_offset = ra_->reg2offset(src_lo);
1745       int dst_offset = ra_->reg2offset(dst_lo);
1746       if (cbuf) {
1747         MacroAssembler _masm(cbuf);
1748         __ ld(R0, src_offset, R1_SP);
1749         __ std(R0, dst_offset, R1_SP);
1750         __ ld(R0, src_offset+8, R1_SP);
1751         __ std(R0, dst_offset+8, R1_SP);
1752       }
1753       size += 16;
1754     }
1755     // VectorSRegister->Memory Spill.
1756     else if (src_lo_rc == rc_vs && dst_lo_rc == rc_stack) {
1757       VectorSRegister Rsrc = as_VectorSRegister(Matcher::_regEncode[src_lo]);
1758       int dst_offset = ra_->reg2offset(dst_lo);
1759       if (cbuf) {
1760         MacroAssembler _masm(cbuf);
1761         __ addi(R0, R1_SP, dst_offset);
1762         __ stxvd2x(Rsrc, R0);
1763       }
1764       size += 8;
1765     }
1766     // Memory->VectorSRegister Spill.
1767     else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vs) {
1768       VectorSRegister Rdst = as_VectorSRegister(Matcher::_regEncode[dst_lo]);
1769       int src_offset = ra_->reg2offset(src_lo);
1770       if (cbuf) {
1771         MacroAssembler _masm(cbuf);
1772         __ addi(R0, R1_SP, src_offset);
1773         __ lxvd2x(Rdst, R0);
1774       }
1775       size += 8;
1776     }
1777     // VectorSRegister->VectorSRegister.
1778     else if (src_lo_rc == rc_vs && dst_lo_rc == rc_vs) {
1779       VectorSRegister Rsrc = as_VectorSRegister(Matcher::_regEncode[src_lo]);
1780       VectorSRegister Rdst = as_VectorSRegister(Matcher::_regEncode[dst_lo]);
1781       if (cbuf) {
1782         MacroAssembler _masm(cbuf);
1783         __ xxlor(Rdst, Rsrc, Rsrc);
1784       }
1785       size += 4;
1786     }
1787     else {
1788       ShouldNotReachHere(); // No VSR spill.
1789     }
1790     return size;
1791   }
1792 
1793   // --------------------------------------
1794   // Memory->Memory Spill. Use R0 to hold the value.
1795   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1796     int src_offset = ra_->reg2offset(src_lo);
1797     int dst_offset = ra_->reg2offset(dst_lo);
1798     if (src_hi != OptoReg::Bad) {
1799       assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1800              "expected same type of move for high parts");
1801       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE,  R0_num, src_offset, !do_size, C, st);
1802       if (!cbuf && !do_size) st->print("\n\t");
1803       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1804     } else {
1805       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1806       if (!cbuf && !do_size) st->print("\n\t");
1807       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1808     }
1809     return size;
1810   }
1811 
1812   // --------------------------------------
1813   // Check for float->int copy; requires a trip through memory.
1814   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1815     Unimplemented();
1816   }
1817 
1818   // --------------------------------------
1819   // Check for integer reg-reg copy.
1820   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1821       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1822       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1823       size = (Rsrc != Rdst) ? 4 : 0;
1824 
1825       if (cbuf) {
1826         MacroAssembler _masm(cbuf);
1827         if (size) {
1828           __ mr(Rdst, Rsrc);
1829         }
1830       }
1831 #ifndef PRODUCT
1832       else if (!do_size) {
1833         if (size) {
1834           st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1835         } else {
1836           st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1837         }
1838       }
1839 #endif
1840       return size;
1841   }
1842 
1843   // Check for integer store.
1844   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1845     int dst_offset = ra_->reg2offset(dst_lo);
1846     if (src_hi != OptoReg::Bad) {
1847       assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1848              "expected same type of move for high parts");
1849       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1850     } else {
1851       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1852     }
1853     return size;
1854   }
1855 
1856   // Check for integer load.
1857   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1858     int src_offset = ra_->reg2offset(src_lo);
1859     if (src_hi != OptoReg::Bad) {
1860       assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1861              "expected same type of move for high parts");
1862       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1863     } else {
1864       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1865     }
1866     return size;
1867   }
1868 
1869   // Check for float reg-reg copy.
1870   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1871     if (cbuf) {
1872       MacroAssembler _masm(cbuf);
1873       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1874       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1875       __ fmr(Rdst, Rsrc);
1876     }
1877 #ifndef PRODUCT
1878     else if (!do_size) {
1879       st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1880     }
1881 #endif
1882     return 4;
1883   }
1884 
1885   // Check for float store.
1886   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1887     int dst_offset = ra_->reg2offset(dst_lo);
1888     if (src_hi != OptoReg::Bad) {
1889       assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1890              "expected same type of move for high parts");
1891       size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1892     } else {
1893       size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1894     }
1895     return size;
1896   }
1897 
1898   // Check for float load.
1899   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1900     int src_offset = ra_->reg2offset(src_lo);
1901     if (src_hi != OptoReg::Bad) {
1902       assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1903              "expected same type of move for high parts");
1904       size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1905     } else {
1906       size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1907     }
1908     return size;
1909   }
1910 
1911   // --------------------------------------------------------------------
1912   // Check for hi bits still needing moving. Only happens for misaligned
1913   // arguments to native calls.
1914   if (src_hi == dst_hi)
1915     return size;               // Self copy; no move.
1916 
1917   assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1918   ShouldNotReachHere(); // Unimplemented
1919   return 0;
1920 }
1921 
1922 #ifndef PRODUCT
1923 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1924   if (!ra_)
1925     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1926   else
1927     implementation(NULL, ra_, false, st);
1928 }
1929 #endif
1930 
1931 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1932   implementation(&cbuf, ra_, false, NULL);
1933 }
1934 
1935 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1936   return implementation(NULL, ra_, true, NULL);
1937 }
1938 
1939 #if 0 // TODO: PPC port
1940 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1941 #ifndef PRODUCT
1942   if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1943 #endif
1944   assert(ra_->node_regs_max_index() != 0, "");
1945 
1946   // Get registers to move.
1947   OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1948   OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1949   OptoReg::Name dst_hi = ra_->get_reg_second(n);
1950   OptoReg::Name dst_lo = ra_->get_reg_first(n);
1951 
1952   enum RC src_lo_rc = rc_class(src_lo);
1953   enum RC dst_lo_rc = rc_class(dst_lo);
1954 
1955   if (src_lo == dst_lo && src_hi == dst_hi)
1956     return ppc64Opcode_none;            // Self copy, no move.
1957 
1958   // --------------------------------------
1959   // Memory->Memory Spill. Use R0 to hold the value.
1960   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1961     return ppc64Opcode_compound;
1962   }
1963 
1964   // --------------------------------------
1965   // Check for float->int copy; requires a trip through memory.
1966   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1967     Unimplemented();
1968   }
1969 
1970   // --------------------------------------
1971   // Check for integer reg-reg copy.
1972   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1973     Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1974     Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1975     if (Rsrc == Rdst) {
1976       return ppc64Opcode_none;
1977     } else {
1978       return ppc64Opcode_or;
1979     }
1980   }
1981 
1982   // Check for integer store.
1983   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1984     if (src_hi != OptoReg::Bad) {
1985       return ppc64Opcode_std;
1986     } else {
1987       return ppc64Opcode_stw;
1988     }
1989   }
1990 
1991   // Check for integer load.
1992   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1993     if (src_hi != OptoReg::Bad) {
1994       return ppc64Opcode_ld;
1995     } else {
1996       return ppc64Opcode_lwz;
1997     }
1998   }
1999 
2000   // Check for float reg-reg copy.
2001   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
2002     return ppc64Opcode_fmr;
2003   }
2004 
2005   // Check for float store.
2006   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
2007     if (src_hi != OptoReg::Bad) {
2008       return ppc64Opcode_stfd;
2009     } else {
2010       return ppc64Opcode_stfs;
2011     }
2012   }
2013 
2014   // Check for float load.
2015   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
2016     if (src_hi != OptoReg::Bad) {
2017       return ppc64Opcode_lfd;
2018     } else {
2019       return ppc64Opcode_lfs;
2020     }
2021   }
2022 
2023   // --------------------------------------------------------------------
2024   // Check for hi bits still needing moving. Only happens for misaligned
2025   // arguments to native calls.
2026   if (src_hi == dst_hi) {
2027     return ppc64Opcode_none;               // Self copy; no move.
2028   }
2029 
2030   ShouldNotReachHere();
2031   return ppc64Opcode_undefined;
2032 }
2033 #endif // PPC port
2034 
2035 #ifndef PRODUCT
2036 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2037   st->print("NOP \t// %d nops to pad for loops.", _count);
2038 }
2039 #endif
2040 
2041 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
2042   MacroAssembler _masm(&cbuf);
2043   // _count contains the number of nops needed for padding.
2044   for (int i = 0; i < _count; i++) {
2045     __ nop();
2046   }
2047 }
2048 
2049 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
2050   return _count * 4;
2051 }
2052 
2053 #ifndef PRODUCT
2054 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2055   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2056   char reg_str[128];
2057   ra_->dump_register(this, reg_str);
2058   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
2059 }
2060 #endif
2061 
2062 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2063   MacroAssembler _masm(&cbuf);
2064 
2065   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2066   int reg    = ra_->get_encode(this);
2067 
2068   if (Assembler::is_simm(offset, 16)) {
2069     __ addi(as_Register(reg), R1, offset);
2070   } else {
2071     ShouldNotReachHere();
2072   }
2073 }
2074 
2075 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
2076   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
2077   return 4;
2078 }
2079 
2080 #ifndef PRODUCT
2081 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2082   st->print_cr("---- MachUEPNode ----");
2083   st->print_cr("...");
2084 }
2085 #endif
2086 
2087 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2088   // This is the unverified entry point.
2089   MacroAssembler _masm(&cbuf);
2090 
2091   // Inline_cache contains a klass.
2092   Register ic_klass       = as_Register(Matcher::inline_cache_reg_encode());
2093   Register receiver_klass = R12_scratch2;  // tmp
2094 
2095   assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2096   assert(R11_scratch1 == R11, "need prologue scratch register");
2097 
2098   // Check for NULL argument if we don't have implicit null checks.
2099   if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2100     if (TrapBasedNullChecks) {
2101       __ trap_null_check(R3_ARG1);
2102     } else {
2103       Label valid;
2104       __ cmpdi(CCR0, R3_ARG1, 0);
2105       __ bne_predict_taken(CCR0, valid);
2106       // We have a null argument, branch to ic_miss_stub.
2107       __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2108                            relocInfo::runtime_call_type);
2109       __ bind(valid);
2110     }
2111   }
2112   // Assume argument is not NULL, load klass from receiver.
2113   __ load_klass(receiver_klass, R3_ARG1);
2114 
2115   if (TrapBasedICMissChecks) {
2116     __ trap_ic_miss_check(receiver_klass, ic_klass);
2117   } else {
2118     Label valid;
2119     __ cmpd(CCR0, receiver_klass, ic_klass);
2120     __ beq_predict_taken(CCR0, valid);
2121     // We have an unexpected klass, branch to ic_miss_stub.
2122     __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2123                          relocInfo::runtime_call_type);
2124     __ bind(valid);
2125   }
2126 
2127   // Argument is valid and klass is as expected, continue.
2128 }
2129 
2130 #if 0 // TODO: PPC port
2131 // Optimize UEP code on z (save a load_const() call in main path).
2132 int MachUEPNode::ep_offset() {
2133   return 0;
2134 }
2135 #endif
2136 
2137 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2138   // Variable size. Determine dynamically.
2139   return MachNode::size(ra_);
2140 }
2141 
2142 //=============================================================================
2143 
2144 %} // interrupt source
2145 
2146 source_hpp %{ // Header information of the source block.
2147 
2148 class HandlerImpl {
2149 
2150  public:
2151 
2152   static int emit_exception_handler(CodeBuffer &cbuf);
2153   static int emit_deopt_handler(CodeBuffer& cbuf);
2154 
2155   static uint size_exception_handler() {
2156     // The exception_handler is a b64_patchable.
2157     return MacroAssembler::b64_patchable_size;
2158   }
2159 
2160   static uint size_deopt_handler() {
2161     // The deopt_handler is a bl64_patchable.
2162     return MacroAssembler::bl64_patchable_size;
2163   }
2164 
2165 };
2166 
2167 %} // end source_hpp
2168 
2169 source %{
2170 
2171 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2172   MacroAssembler _masm(&cbuf);
2173 
2174   address base = __ start_a_stub(size_exception_handler());
2175   if (base == NULL) return 0; // CodeBuffer::expand failed
2176 
2177   int offset = __ offset();
2178   __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2179                        relocInfo::runtime_call_type);
2180   assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2181   __ end_a_stub();
2182 
2183   return offset;
2184 }
2185 
2186 // The deopt_handler is like the exception handler, but it calls to
2187 // the deoptimization blob instead of jumping to the exception blob.
2188 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2189   MacroAssembler _masm(&cbuf);
2190 
2191   address base = __ start_a_stub(size_deopt_handler());
2192   if (base == NULL) return 0; // CodeBuffer::expand failed
2193 
2194   int offset = __ offset();
2195   __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2196                         relocInfo::runtime_call_type);
2197   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2198   __ end_a_stub();
2199 
2200   return offset;
2201 }
2202 
2203 //=============================================================================
2204 
2205 // Use a frame slots bias for frameless methods if accessing the stack.
2206 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2207   if (as_Register(reg_enc) == R1_SP) {
2208     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2209   }
2210   return 0;
2211 }
2212 
2213 const bool Matcher::match_rule_supported(int opcode) {
2214   if (!has_match_rule(opcode))
2215     return false;
2216 
2217   switch (opcode) {
2218   case Op_SqrtD:
2219     return VM_Version::has_fsqrt();
2220   case Op_CountLeadingZerosI:
2221   case Op_CountLeadingZerosL:
2222   case Op_CountTrailingZerosI:
2223   case Op_CountTrailingZerosL:
2224     if (!UseCountLeadingZerosInstructionsPPC64)
2225       return false;
2226     break;
2227 
2228   case Op_PopCountI:
2229   case Op_PopCountL:
2230     return (UsePopCountInstruction && VM_Version::has_popcntw());
2231 
2232   case Op_StrComp:
2233     return SpecialStringCompareTo;
2234   case Op_StrEquals:
2235     return SpecialStringEquals;
2236   case Op_StrIndexOf:
2237     return SpecialStringIndexOf;
2238   case Op_StrIndexOfChar:
2239     return SpecialStringIndexOf;
2240   case Op_AddVB:
2241   case Op_AddVS:
2242   case Op_AddVI:
2243   case Op_AddVF:
2244   case Op_AddVL:
2245   case Op_AddVD:
2246   case Op_SubVB:
2247   case Op_SubVS:
2248   case Op_SubVI:
2249   case Op_SubVF:
2250   case Op_SubVL:
2251   case Op_SubVD:
2252   case Op_MulVS:
2253   case Op_MulVI:
2254   case Op_MulVF:
2255   case Op_MulVD:
2256   case Op_DivVF:
2257   case Op_DivVD:
2258   case Op_AbsVF:
2259   case Op_AbsVD:
2260   case Op_NegVF:
2261   case Op_NegVD:
2262   case Op_SqrtVF:
2263   case Op_SqrtVD:
2264   case Op_PopCountVI:
2265     return VM_Version::has_popcntb();
2266   }
2267 
2268   return true;  // Per default match rules are supported.
2269 }
2270 
2271 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2272 
2273   // TODO
2274   // identify extra cases that we might want to provide match rules for
2275   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2276   bool ret_value = match_rule_supported(opcode);
2277   // Add rules here.
2278 
2279   return ret_value;  // Per default match rules are supported.
2280 }
2281 
2282 const bool Matcher::has_predicated_vectors(void) {
2283   return false;
2284 }
2285 
2286 const int Matcher::float_pressure(int default_pressure_threshold) {
2287   return default_pressure_threshold;
2288 }
2289 
2290 int Matcher::regnum_to_fpu_offset(int regnum) {
2291   // No user for this method?
2292   Unimplemented();
2293   return 999;
2294 }
2295 
2296 const bool Matcher::convL2FSupported(void) {
2297   // fcfids can do the conversion (>= Power7).
2298   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2299   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2300 }
2301 
2302 // Vector width in bytes.
2303 const int Matcher::vector_width_in_bytes(BasicType bt) {
2304   if (SuperwordUseVSX) {
2305     assert(MaxVectorSize == 16, "");
2306     return 16;
2307   } else {
2308     assert(MaxVectorSize == 8, "");
2309     return 8;
2310   }
2311 }
2312 
2313 // Vector ideal reg.
2314 const uint Matcher::vector_ideal_reg(int size) {
2315   if (SuperwordUseVSX) {
2316     assert(MaxVectorSize == 16 && size == 16, "");
2317     return Op_VecX;
2318   } else {
2319     assert(MaxVectorSize == 8 && size == 8, "");
2320     return Op_RegL;
2321   }
2322 }
2323 
2324 const uint Matcher::vector_shift_count_ideal_reg(int size) {
2325   fatal("vector shift is not supported");
2326   return Node::NotAMachineReg;
2327 }
2328 
2329 // Limits on vector size (number of elements) loaded into vector.
2330 const int Matcher::max_vector_size(const BasicType bt) {
2331   assert(is_java_primitive(bt), "only primitive type vectors");
2332   return vector_width_in_bytes(bt)/type2aelembytes(bt);
2333 }
2334 
2335 const int Matcher::min_vector_size(const BasicType bt) {
2336   return max_vector_size(bt); // Same as max.
2337 }
2338 
2339 // PPC doesn't support misaligned vectors store/load.
2340 const bool Matcher::misaligned_vectors_ok() {
2341   return !AlignVector; // can be changed by flag
2342 }
2343 
2344 // PPC AES support not yet implemented
2345 const bool Matcher::pass_original_key_for_aes() {
2346   return false;
2347 }
2348 
2349 // RETURNS: whether this branch offset is short enough that a short
2350 // branch can be used.
2351 //
2352 // If the platform does not provide any short branch variants, then
2353 // this method should return `false' for offset 0.
2354 //
2355 // `Compile::Fill_buffer' will decide on basis of this information
2356 // whether to do the pass `Compile::Shorten_branches' at all.
2357 //
2358 // And `Compile::Shorten_branches' will decide on basis of this
2359 // information whether to replace particular branch sites by short
2360 // ones.
2361 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2362   // Is the offset within the range of a ppc64 pc relative branch?
2363   bool b;
2364 
2365   const int safety_zone = 3 * BytesPerInstWord;
2366   b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2367                          29 - 16 + 1 + 2);
2368   return b;
2369 }
2370 
2371 const bool Matcher::isSimpleConstant64(jlong value) {
2372   // Probably always true, even if a temp register is required.
2373   return true;
2374 }
2375 /* TODO: PPC port
2376 // Make a new machine dependent decode node (with its operands).
2377 MachTypeNode *Matcher::make_decode_node() {
2378   assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2379          "This method is only implemented for unscaled cOops mode so far");
2380   MachTypeNode *decode = new decodeN_unscaledNode();
2381   decode->set_opnd_array(0, new iRegPdstOper());
2382   decode->set_opnd_array(1, new iRegNsrcOper());
2383   return decode;
2384 }
2385 */
2386 
2387 // false => size gets scaled to BytesPerLong, ok.
2388 const bool Matcher::init_array_count_is_in_bytes = false;
2389 
2390 // Use conditional move (CMOVL) on Power7.
2391 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2392 
2393 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2394 // fsel doesn't accept a condition register as input, so this would be slightly different.
2395 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2396 
2397 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2398 const bool Matcher::require_postalloc_expand = true;
2399 
2400 // Do we need to mask the count passed to shift instructions or does
2401 // the cpu only look at the lower 5/6 bits anyway?
2402 // PowerPC requires masked shift counts.
2403 const bool Matcher::need_masked_shift_count = true;
2404 
2405 // This affects two different things:
2406 //  - how Decode nodes are matched
2407 //  - how ImplicitNullCheck opportunities are recognized
2408 // If true, the matcher will try to remove all Decodes and match them
2409 // (as operands) into nodes. NullChecks are not prepared to deal with
2410 // Decodes by final_graph_reshaping().
2411 // If false, final_graph_reshaping() forces the decode behind the Cmp
2412 // for a NullCheck. The matcher matches the Decode node into a register.
2413 // Implicit_null_check optimization moves the Decode along with the
2414 // memory operation back up before the NullCheck.
2415 bool Matcher::narrow_oop_use_complex_address() {
2416   // TODO: PPC port if (MatchDecodeNodes) return true;
2417   return false;
2418 }
2419 
2420 bool Matcher::narrow_klass_use_complex_address() {
2421   NOT_LP64(ShouldNotCallThis());
2422   assert(UseCompressedClassPointers, "only for compressed klass code");
2423   // TODO: PPC port if (MatchDecodeNodes) return true;
2424   return false;
2425 }
2426 
2427 bool Matcher::const_oop_prefer_decode() {
2428   // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
2429   return Universe::narrow_oop_base() == NULL;
2430 }
2431 
2432 bool Matcher::const_klass_prefer_decode() {
2433   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
2434   return Universe::narrow_klass_base() == NULL;
2435 }
2436 
2437 // Is it better to copy float constants, or load them directly from memory?
2438 // Intel can load a float constant from a direct address, requiring no
2439 // extra registers. Most RISCs will have to materialize an address into a
2440 // register first, so they would do better to copy the constant from stack.
2441 const bool Matcher::rematerialize_float_constants = false;
2442 
2443 // If CPU can load and store mis-aligned doubles directly then no fixup is
2444 // needed. Else we split the double into 2 integer pieces and move it
2445 // piece-by-piece. Only happens when passing doubles into C code as the
2446 // Java calling convention forces doubles to be aligned.
2447 const bool Matcher::misaligned_doubles_ok = true;
2448 
2449 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2450  Unimplemented();
2451 }
2452 
2453 // Advertise here if the CPU requires explicit rounding operations
2454 // to implement the UseStrictFP mode.
2455 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2456 
2457 // Do floats take an entire double register or just half?
2458 //
2459 // A float occupies a ppc64 double register. For the allocator, a
2460 // ppc64 double register appears as a pair of float registers.
2461 bool Matcher::float_in_double() { return true; }
2462 
2463 // Do ints take an entire long register or just half?
2464 // The relevant question is how the int is callee-saved:
2465 // the whole long is written but de-opt'ing will have to extract
2466 // the relevant 32 bits.
2467 const bool Matcher::int_in_long = true;
2468 
2469 // Constants for c2c and c calling conventions.
2470 
2471 const MachRegisterNumbers iarg_reg[8] = {
2472   R3_num, R4_num, R5_num, R6_num,
2473   R7_num, R8_num, R9_num, R10_num
2474 };
2475 
2476 const MachRegisterNumbers farg_reg[13] = {
2477   F1_num, F2_num, F3_num, F4_num,
2478   F5_num, F6_num, F7_num, F8_num,
2479   F9_num, F10_num, F11_num, F12_num,
2480   F13_num
2481 };
2482 
2483 const MachRegisterNumbers vsarg_reg[64] = {
2484   VSR0_num, VSR1_num, VSR2_num, VSR3_num,
2485   VSR4_num, VSR5_num, VSR6_num, VSR7_num,
2486   VSR8_num, VSR9_num, VSR10_num, VSR11_num,
2487   VSR12_num, VSR13_num, VSR14_num, VSR15_num,
2488   VSR16_num, VSR17_num, VSR18_num, VSR19_num,
2489   VSR20_num, VSR21_num, VSR22_num, VSR23_num,
2490   VSR24_num, VSR23_num, VSR24_num, VSR25_num,
2491   VSR28_num, VSR29_num, VSR30_num, VSR31_num,
2492   VSR32_num, VSR33_num, VSR34_num, VSR35_num,
2493   VSR36_num, VSR37_num, VSR38_num, VSR39_num,
2494   VSR40_num, VSR41_num, VSR42_num, VSR43_num,
2495   VSR44_num, VSR45_num, VSR46_num, VSR47_num,
2496   VSR48_num, VSR49_num, VSR50_num, VSR51_num,
2497   VSR52_num, VSR53_num, VSR54_num, VSR55_num,
2498   VSR56_num, VSR57_num, VSR58_num, VSR59_num,
2499   VSR60_num, VSR61_num, VSR62_num, VSR63_num
2500 };
2501 
2502 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2503 
2504 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2505 
2506 const int num_vsarg_registers = sizeof(vsarg_reg) / sizeof(vsarg_reg[0]);
2507 
2508 // Return whether or not this register is ever used as an argument. This
2509 // function is used on startup to build the trampoline stubs in generateOptoStub.
2510 // Registers not mentioned will be killed by the VM call in the trampoline, and
2511 // arguments in those registers not be available to the callee.
2512 bool Matcher::can_be_java_arg(int reg) {
2513   // We return true for all registers contained in iarg_reg[] and
2514   // farg_reg[] and their virtual halves.
2515   // We must include the virtual halves in order to get STDs and LDs
2516   // instead of STWs and LWs in the trampoline stubs.
2517 
2518   if (   reg == R3_num  || reg == R3_H_num
2519       || reg == R4_num  || reg == R4_H_num
2520       || reg == R5_num  || reg == R5_H_num
2521       || reg == R6_num  || reg == R6_H_num
2522       || reg == R7_num  || reg == R7_H_num
2523       || reg == R8_num  || reg == R8_H_num
2524       || reg == R9_num  || reg == R9_H_num
2525       || reg == R10_num || reg == R10_H_num)
2526     return true;
2527 
2528   if (   reg == F1_num  || reg == F1_H_num
2529       || reg == F2_num  || reg == F2_H_num
2530       || reg == F3_num  || reg == F3_H_num
2531       || reg == F4_num  || reg == F4_H_num
2532       || reg == F5_num  || reg == F5_H_num
2533       || reg == F6_num  || reg == F6_H_num
2534       || reg == F7_num  || reg == F7_H_num
2535       || reg == F8_num  || reg == F8_H_num
2536       || reg == F9_num  || reg == F9_H_num
2537       || reg == F10_num || reg == F10_H_num
2538       || reg == F11_num || reg == F11_H_num
2539       || reg == F12_num || reg == F12_H_num
2540       || reg == F13_num || reg == F13_H_num)
2541     return true;
2542 
2543   return false;
2544 }
2545 
2546 bool Matcher::is_spillable_arg(int reg) {
2547   return can_be_java_arg(reg);
2548 }
2549 
2550 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2551   return false;
2552 }
2553 
2554 // Register for DIVI projection of divmodI.
2555 RegMask Matcher::divI_proj_mask() {
2556   ShouldNotReachHere();
2557   return RegMask();
2558 }
2559 
2560 // Register for MODI projection of divmodI.
2561 RegMask Matcher::modI_proj_mask() {
2562   ShouldNotReachHere();
2563   return RegMask();
2564 }
2565 
2566 // Register for DIVL projection of divmodL.
2567 RegMask Matcher::divL_proj_mask() {
2568   ShouldNotReachHere();
2569   return RegMask();
2570 }
2571 
2572 // Register for MODL projection of divmodL.
2573 RegMask Matcher::modL_proj_mask() {
2574   ShouldNotReachHere();
2575   return RegMask();
2576 }
2577 
2578 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2579   return RegMask();
2580 }
2581 
2582 const bool Matcher::convi2l_type_required = true;
2583 
2584 %}
2585 
2586 //----------ENCODING BLOCK-----------------------------------------------------
2587 // This block specifies the encoding classes used by the compiler to output
2588 // byte streams. Encoding classes are parameterized macros used by
2589 // Machine Instruction Nodes in order to generate the bit encoding of the
2590 // instruction. Operands specify their base encoding interface with the
2591 // interface keyword. There are currently supported four interfaces,
2592 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2593 // operand to generate a function which returns its register number when
2594 // queried. CONST_INTER causes an operand to generate a function which
2595 // returns the value of the constant when queried. MEMORY_INTER causes an
2596 // operand to generate four functions which return the Base Register, the
2597 // Index Register, the Scale Value, and the Offset Value of the operand when
2598 // queried. COND_INTER causes an operand to generate six functions which
2599 // return the encoding code (ie - encoding bits for the instruction)
2600 // associated with each basic boolean condition for a conditional instruction.
2601 //
2602 // Instructions specify two basic values for encoding. Again, a function
2603 // is available to check if the constant displacement is an oop. They use the
2604 // ins_encode keyword to specify their encoding classes (which must be
2605 // a sequence of enc_class names, and their parameters, specified in
2606 // the encoding block), and they use the
2607 // opcode keyword to specify, in order, their primary, secondary, and
2608 // tertiary opcode. Only the opcode sections which a particular instruction
2609 // needs for encoding need to be specified.
2610 encode %{
2611   enc_class enc_unimplemented %{
2612     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2613     MacroAssembler _masm(&cbuf);
2614     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2615   %}
2616 
2617   enc_class enc_untested %{
2618 #ifdef ASSERT
2619     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2620     MacroAssembler _masm(&cbuf);
2621     __ untested("Untested mach node encoding in AD file.");
2622 #else
2623     // TODO: PPC port $archOpcode(ppc64Opcode_none);
2624 #endif
2625   %}
2626 
2627   enc_class enc_lbz(iRegIdst dst, memory mem) %{
2628     // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2629     MacroAssembler _masm(&cbuf);
2630     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2631     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2632   %}
2633 
2634   // Load acquire.
2635   enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2636     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2637     MacroAssembler _masm(&cbuf);
2638     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2639     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2640     __ twi_0($dst$$Register);
2641     __ isync();
2642   %}
2643 
2644   enc_class enc_lhz(iRegIdst dst, memory mem) %{
2645     // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2646 
2647     MacroAssembler _masm(&cbuf);
2648     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2649     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2650   %}
2651 
2652   // Load acquire.
2653   enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2654     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2655 
2656     MacroAssembler _masm(&cbuf);
2657     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2658     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2659     __ twi_0($dst$$Register);
2660     __ isync();
2661   %}
2662 
2663   enc_class enc_lwz(iRegIdst dst, memory mem) %{
2664     // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2665 
2666     MacroAssembler _masm(&cbuf);
2667     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2668     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2669   %}
2670 
2671   // Load acquire.
2672   enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2673     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2674 
2675     MacroAssembler _masm(&cbuf);
2676     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2677     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2678     __ twi_0($dst$$Register);
2679     __ isync();
2680   %}
2681 
2682   enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2683     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2684     MacroAssembler _masm(&cbuf);
2685     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2686     // Operand 'ds' requires 4-alignment.
2687     assert((Idisp & 0x3) == 0, "unaligned offset");
2688     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2689   %}
2690 
2691   // Load acquire.
2692   enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2693     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2694     MacroAssembler _masm(&cbuf);
2695     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2696     // Operand 'ds' requires 4-alignment.
2697     assert((Idisp & 0x3) == 0, "unaligned offset");
2698     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2699     __ twi_0($dst$$Register);
2700     __ isync();
2701   %}
2702 
2703   enc_class enc_lfd(RegF dst, memory mem) %{
2704     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2705     MacroAssembler _masm(&cbuf);
2706     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2707     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2708   %}
2709 
2710   enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2711     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2712 
2713     MacroAssembler _masm(&cbuf);
2714     int toc_offset = 0;
2715 
2716     address const_toc_addr;
2717     // Create a non-oop constant, no relocation needed.
2718     // If it is an IC, it has a virtual_call_Relocation.
2719     const_toc_addr = __ long_constant((jlong)$src$$constant);
2720     if (const_toc_addr == NULL) {
2721       ciEnv::current()->record_out_of_memory_failure();
2722       return;
2723     }
2724 
2725     // Get the constant's TOC offset.
2726     toc_offset = __ offset_to_method_toc(const_toc_addr);
2727 
2728     // Keep the current instruction offset in mind.
2729     ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2730 
2731     __ ld($dst$$Register, toc_offset, $toc$$Register);
2732   %}
2733 
2734   enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2735     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2736 
2737     MacroAssembler _masm(&cbuf);
2738 
2739     if (!ra_->C->in_scratch_emit_size()) {
2740       address const_toc_addr;
2741       // Create a non-oop constant, no relocation needed.
2742       // If it is an IC, it has a virtual_call_Relocation.
2743       const_toc_addr = __ long_constant((jlong)$src$$constant);
2744       if (const_toc_addr == NULL) {
2745         ciEnv::current()->record_out_of_memory_failure();
2746         return;
2747       }
2748 
2749       // Get the constant's TOC offset.
2750       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2751       // Store the toc offset of the constant.
2752       ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2753 
2754       // Also keep the current instruction offset in mind.
2755       ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2756     }
2757 
2758     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2759   %}
2760 
2761 %} // encode
2762 
2763 source %{
2764 
2765 typedef struct {
2766   loadConL_hiNode *_large_hi;
2767   loadConL_loNode *_large_lo;
2768   loadConLNode    *_small;
2769   MachNode        *_last;
2770 } loadConLNodesTuple;
2771 
2772 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2773                                              OptoReg::Name reg_second, OptoReg::Name reg_first) {
2774   loadConLNodesTuple nodes;
2775 
2776   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2777   if (large_constant_pool) {
2778     // Create new nodes.
2779     loadConL_hiNode *m1 = new loadConL_hiNode();
2780     loadConL_loNode *m2 = new loadConL_loNode();
2781 
2782     // inputs for new nodes
2783     m1->add_req(NULL, toc);
2784     m2->add_req(NULL, m1);
2785 
2786     // operands for new nodes
2787     m1->_opnds[0] = new iRegLdstOper(); // dst
2788     m1->_opnds[1] = immSrc;             // src
2789     m1->_opnds[2] = new iRegPdstOper(); // toc
2790     m2->_opnds[0] = new iRegLdstOper(); // dst
2791     m2->_opnds[1] = immSrc;             // src
2792     m2->_opnds[2] = new iRegLdstOper(); // base
2793 
2794     // Initialize ins_attrib TOC fields.
2795     m1->_const_toc_offset = -1;
2796     m2->_const_toc_offset_hi_node = m1;
2797 
2798     // Initialize ins_attrib instruction offset.
2799     m1->_cbuf_insts_offset = -1;
2800 
2801     // register allocation for new nodes
2802     ra_->set_pair(m1->_idx, reg_second, reg_first);
2803     ra_->set_pair(m2->_idx, reg_second, reg_first);
2804 
2805     // Create result.
2806     nodes._large_hi = m1;
2807     nodes._large_lo = m2;
2808     nodes._small = NULL;
2809     nodes._last = nodes._large_lo;
2810     assert(m2->bottom_type()->isa_long(), "must be long");
2811   } else {
2812     loadConLNode *m2 = new loadConLNode();
2813 
2814     // inputs for new nodes
2815     m2->add_req(NULL, toc);
2816 
2817     // operands for new nodes
2818     m2->_opnds[0] = new iRegLdstOper(); // dst
2819     m2->_opnds[1] = immSrc;             // src
2820     m2->_opnds[2] = new iRegPdstOper(); // toc
2821 
2822     // Initialize ins_attrib instruction offset.
2823     m2->_cbuf_insts_offset = -1;
2824 
2825     // register allocation for new nodes
2826     ra_->set_pair(m2->_idx, reg_second, reg_first);
2827 
2828     // Create result.
2829     nodes._large_hi = NULL;
2830     nodes._large_lo = NULL;
2831     nodes._small = m2;
2832     nodes._last = nodes._small;
2833     assert(m2->bottom_type()->isa_long(), "must be long");
2834   }
2835 
2836   return nodes;
2837 }
2838 
2839 typedef struct {
2840   loadConL_hiNode *_large_hi;
2841   loadConL_loNode *_large_lo;
2842   mtvsrdNode      *_moved;
2843   xxspltdNode     *_replicated;
2844   loadConLNode    *_small;
2845   MachNode        *_last;
2846 } loadConLReplicatedNodesTuple;
2847 
2848 loadConLReplicatedNodesTuple loadConLReplicatedNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2849                                                  vecXOper *dst, immI_0Oper *zero,
2850                                                  OptoReg::Name reg_second, OptoReg::Name reg_first,
2851                                                  OptoReg::Name reg_vec_second, OptoReg::Name reg_vec_first) {
2852   loadConLReplicatedNodesTuple nodes;
2853 
2854   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2855   if (large_constant_pool) {
2856     // Create new nodes.
2857     loadConL_hiNode *m1 = new  loadConL_hiNode();
2858     loadConL_loNode *m2 = new  loadConL_loNode();
2859     mtvsrdNode *m3 = new  mtvsrdNode();
2860     xxspltdNode *m4 = new  xxspltdNode();
2861 
2862     // inputs for new nodes
2863     m1->add_req(NULL, toc);
2864     m2->add_req(NULL, m1);
2865     m3->add_req(NULL, m2);
2866     m4->add_req(NULL, m3);
2867 
2868     // operands for new nodes
2869     m1->_opnds[0] = new  iRegLdstOper(); // dst
2870     m1->_opnds[1] = immSrc;              // src
2871     m1->_opnds[2] = new  iRegPdstOper(); // toc
2872 
2873     m2->_opnds[0] = new  iRegLdstOper(); // dst
2874     m2->_opnds[1] = immSrc;              // src
2875     m2->_opnds[2] = new  iRegLdstOper(); // base
2876 
2877     m3->_opnds[0] = new  vecXOper();     // dst
2878     m3->_opnds[1] = new  iRegLdstOper(); // src
2879 
2880     m4->_opnds[0] = new  vecXOper();     // dst
2881     m4->_opnds[1] = new  vecXOper();     // src
2882     m4->_opnds[2] = zero;
2883 
2884     // Initialize ins_attrib TOC fields.
2885     m1->_const_toc_offset = -1;
2886     m2->_const_toc_offset_hi_node = m1;
2887 
2888     // Initialize ins_attrib instruction offset.
2889     m1->_cbuf_insts_offset = -1;
2890 
2891     // register allocation for new nodes
2892     ra_->set_pair(m1->_idx, reg_second, reg_first);
2893     ra_->set_pair(m2->_idx, reg_second, reg_first);
2894     ra_->set1(m3->_idx, reg_second);
2895     ra_->set2(m3->_idx, reg_vec_first);
2896     ra_->set_pair(m4->_idx, reg_vec_second, reg_vec_first);
2897 
2898     // Create result.
2899     nodes._large_hi = m1;
2900     nodes._large_lo = m2;
2901     nodes._moved = m3;
2902     nodes._replicated = m4;
2903     nodes._small = NULL;
2904     nodes._last = nodes._replicated;
2905     assert(m2->bottom_type()->isa_long(), "must be long");
2906   } else {
2907     loadConLNode *m2 = new  loadConLNode();
2908     mtvsrdNode *m3 = new  mtvsrdNode();
2909     xxspltdNode *m4 = new  xxspltdNode();
2910 
2911     // inputs for new nodes
2912     m2->add_req(NULL, toc);
2913 
2914     // operands for new nodes
2915     m2->_opnds[0] = new  iRegLdstOper(); // dst
2916     m2->_opnds[1] = immSrc;              // src
2917     m2->_opnds[2] = new  iRegPdstOper(); // toc
2918 
2919     m3->_opnds[0] = new  vecXOper();     // dst
2920     m3->_opnds[1] = new  iRegLdstOper(); // src
2921 
2922     m4->_opnds[0] = new  vecXOper();     // dst
2923     m4->_opnds[1] = new  vecXOper();     // src
2924     m4->_opnds[2] = zero;
2925 
2926     // Initialize ins_attrib instruction offset.
2927     m2->_cbuf_insts_offset = -1;
2928     ra_->set1(m3->_idx, reg_second);
2929     ra_->set2(m3->_idx, reg_vec_first);
2930     ra_->set_pair(m4->_idx, reg_vec_second, reg_vec_first);
2931 
2932     // register allocation for new nodes
2933     ra_->set_pair(m2->_idx, reg_second, reg_first);
2934 
2935     // Create result.
2936     nodes._large_hi = NULL;
2937     nodes._large_lo = NULL;
2938     nodes._small = m2;
2939     nodes._moved = m3;
2940     nodes._replicated = m4;
2941     nodes._last = nodes._replicated;
2942     assert(m2->bottom_type()->isa_long(), "must be long");
2943   }
2944 
2945   return nodes;
2946 }
2947 
2948 %} // source
2949 
2950 encode %{
2951   // Postalloc expand emitter for loading a long constant from the method's TOC.
2952   // Enc_class needed as consttanttablebase is not supported by postalloc
2953   // expand.
2954   enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2955     // Create new nodes.
2956     loadConLNodesTuple loadConLNodes =
2957       loadConLNodesTuple_create(ra_, n_toc, op_src,
2958                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
2959 
2960     // Push new nodes.
2961     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2962     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
2963 
2964     // some asserts
2965     assert(nodes->length() >= 1, "must have created at least 1 node");
2966     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2967   %}
2968 
2969   enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2970     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2971 
2972     MacroAssembler _masm(&cbuf);
2973     int toc_offset = 0;
2974 
2975     intptr_t val = $src$$constant;
2976     relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2977     address const_toc_addr;
2978     if (constant_reloc == relocInfo::oop_type) {
2979       // Create an oop constant and a corresponding relocation.
2980       AddressLiteral a = __ allocate_oop_address((jobject)val);
2981       const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2982       __ relocate(a.rspec());
2983     } else if (constant_reloc == relocInfo::metadata_type) {
2984       AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2985       const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2986       __ relocate(a.rspec());
2987     } else {
2988       // Create a non-oop constant, no relocation needed.
2989       const_toc_addr = __ long_constant((jlong)$src$$constant);
2990     }
2991 
2992     if (const_toc_addr == NULL) {
2993       ciEnv::current()->record_out_of_memory_failure();
2994       return;
2995     }
2996     // Get the constant's TOC offset.
2997     toc_offset = __ offset_to_method_toc(const_toc_addr);
2998 
2999     __ ld($dst$$Register, toc_offset, $toc$$Register);
3000   %}
3001 
3002   enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
3003     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
3004 
3005     MacroAssembler _masm(&cbuf);
3006     if (!ra_->C->in_scratch_emit_size()) {
3007       intptr_t val = $src$$constant;
3008       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
3009       address const_toc_addr;
3010       if (constant_reloc == relocInfo::oop_type) {
3011         // Create an oop constant and a corresponding relocation.
3012         AddressLiteral a = __ allocate_oop_address((jobject)val);
3013         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
3014         __ relocate(a.rspec());
3015       } else if (constant_reloc == relocInfo::metadata_type) {
3016         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
3017         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
3018         __ relocate(a.rspec());
3019       } else {  // non-oop pointers, e.g. card mark base, heap top
3020         // Create a non-oop constant, no relocation needed.
3021         const_toc_addr = __ long_constant((jlong)$src$$constant);
3022       }
3023 
3024       if (const_toc_addr == NULL) {
3025         ciEnv::current()->record_out_of_memory_failure();
3026         return;
3027       }
3028       // Get the constant's TOC offset.
3029       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
3030       // Store the toc offset of the constant.
3031       ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
3032     }
3033 
3034     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
3035   %}
3036 
3037   // Postalloc expand emitter for loading a ptr constant from the method's TOC.
3038   // Enc_class needed as consttanttablebase is not supported by postalloc
3039   // expand.
3040   enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
3041     const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
3042     if (large_constant_pool) {
3043       // Create new nodes.
3044       loadConP_hiNode *m1 = new loadConP_hiNode();
3045       loadConP_loNode *m2 = new loadConP_loNode();
3046 
3047       // inputs for new nodes
3048       m1->add_req(NULL, n_toc);
3049       m2->add_req(NULL, m1);
3050 
3051       // operands for new nodes
3052       m1->_opnds[0] = new iRegPdstOper(); // dst
3053       m1->_opnds[1] = op_src;             // src
3054       m1->_opnds[2] = new iRegPdstOper(); // toc
3055       m2->_opnds[0] = new iRegPdstOper(); // dst
3056       m2->_opnds[1] = op_src;             // src
3057       m2->_opnds[2] = new iRegLdstOper(); // base
3058 
3059       // Initialize ins_attrib TOC fields.
3060       m1->_const_toc_offset = -1;
3061       m2->_const_toc_offset_hi_node = m1;
3062 
3063       // Register allocation for new nodes.
3064       ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3065       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3066 
3067       nodes->push(m1);
3068       nodes->push(m2);
3069       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
3070     } else {
3071       loadConPNode *m2 = new loadConPNode();
3072 
3073       // inputs for new nodes
3074       m2->add_req(NULL, n_toc);
3075 
3076       // operands for new nodes
3077       m2->_opnds[0] = new iRegPdstOper(); // dst
3078       m2->_opnds[1] = op_src;             // src
3079       m2->_opnds[2] = new iRegPdstOper(); // toc
3080 
3081       // Register allocation for new nodes.
3082       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3083 
3084       nodes->push(m2);
3085       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
3086     }
3087   %}
3088 
3089   // Enc_class needed as consttanttablebase is not supported by postalloc
3090   // expand.
3091   enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
3092     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
3093 
3094     MachNode *m2;
3095     if (large_constant_pool) {
3096       m2 = new loadConFCompNode();
3097     } else {
3098       m2 = new loadConFNode();
3099     }
3100     // inputs for new nodes
3101     m2->add_req(NULL, n_toc);
3102 
3103     // operands for new nodes
3104     m2->_opnds[0] = op_dst;
3105     m2->_opnds[1] = op_src;
3106     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
3107 
3108     // register allocation for new nodes
3109     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3110     nodes->push(m2);
3111   %}
3112 
3113   // Enc_class needed as consttanttablebase is not supported by postalloc
3114   // expand.
3115   enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
3116     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
3117 
3118     MachNode *m2;
3119     if (large_constant_pool) {
3120       m2 = new loadConDCompNode();
3121     } else {
3122       m2 = new loadConDNode();
3123     }
3124     // inputs for new nodes
3125     m2->add_req(NULL, n_toc);
3126 
3127     // operands for new nodes
3128     m2->_opnds[0] = op_dst;
3129     m2->_opnds[1] = op_src;
3130     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
3131 
3132     // register allocation for new nodes
3133     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3134     nodes->push(m2);
3135   %}
3136 
3137   enc_class enc_stw(iRegIsrc src, memory mem) %{
3138     // TODO: PPC port $archOpcode(ppc64Opcode_stw);
3139     MacroAssembler _masm(&cbuf);
3140     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3141     __ stw($src$$Register, Idisp, $mem$$base$$Register);
3142   %}
3143 
3144   enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
3145     // TODO: PPC port $archOpcode(ppc64Opcode_std);
3146     MacroAssembler _masm(&cbuf);
3147     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3148     // Operand 'ds' requires 4-alignment.
3149     assert((Idisp & 0x3) == 0, "unaligned offset");
3150     __ std($src$$Register, Idisp, $mem$$base$$Register);
3151   %}
3152 
3153   enc_class enc_stfs(RegF src, memory mem) %{
3154     // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
3155     MacroAssembler _masm(&cbuf);
3156     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3157     __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
3158   %}
3159 
3160   enc_class enc_stfd(RegF src, memory mem) %{
3161     // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
3162     MacroAssembler _masm(&cbuf);
3163     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3164     __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
3165   %}
3166 
3167   // Use release_store for card-marking to ensure that previous
3168   // oop-stores are visible before the card-mark change.
3169   enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
3170     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3171     // FIXME: Implement this as a cmove and use a fixed condition code
3172     // register which is written on every transition to compiled code,
3173     // e.g. in call-stub and when returning from runtime stubs.
3174     //
3175     // Proposed code sequence for the cmove implementation:
3176     //
3177     // Label skip_release;
3178     // __ beq(CCRfixed, skip_release);
3179     // __ release();
3180     // __ bind(skip_release);
3181     // __ stb(card mark);
3182 
3183     MacroAssembler _masm(&cbuf);
3184     Label skip_storestore;
3185 
3186 #if 0 // TODO: PPC port
3187     // Check CMSCollectorCardTableBarrierSetBSExt::_requires_release and do the
3188     // StoreStore barrier conditionally.
3189     __ lwz(R0, 0, $releaseFieldAddr$$Register);
3190     __ cmpwi($crx$$CondRegister, R0, 0);
3191     __ beq_predict_taken($crx$$CondRegister, skip_storestore);
3192 #endif
3193     __ li(R0, 0);
3194     __ membar(Assembler::StoreStore);
3195 #if 0 // TODO: PPC port
3196     __ bind(skip_storestore);
3197 #endif
3198 
3199     // Do the store.
3200     if ($mem$$index == 0) {
3201       __ stb(R0, $mem$$disp, $mem$$base$$Register);
3202     } else {
3203       assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
3204       __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
3205     }
3206   %}
3207 
3208   enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
3209 
3210     if (VM_Version::has_isel()) {
3211       // use isel instruction with Power 7
3212       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
3213       encodeP_subNode    *n_sub_base = new encodeP_subNode();
3214       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
3215       cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
3216 
3217       n_compare->add_req(n_region, n_src);
3218       n_compare->_opnds[0] = op_crx;
3219       n_compare->_opnds[1] = op_src;
3220       n_compare->_opnds[2] = new immL16Oper(0);
3221 
3222       n_sub_base->add_req(n_region, n_src);
3223       n_sub_base->_opnds[0] = op_dst;
3224       n_sub_base->_opnds[1] = op_src;
3225       n_sub_base->_bottom_type = _bottom_type;
3226 
3227       n_shift->add_req(n_region, n_sub_base);
3228       n_shift->_opnds[0] = op_dst;
3229       n_shift->_opnds[1] = op_dst;
3230       n_shift->_bottom_type = _bottom_type;
3231 
3232       n_cond_set->add_req(n_region, n_compare, n_shift);
3233       n_cond_set->_opnds[0] = op_dst;
3234       n_cond_set->_opnds[1] = op_crx;
3235       n_cond_set->_opnds[2] = op_dst;
3236       n_cond_set->_bottom_type = _bottom_type;
3237 
3238       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3239       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3240       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3241       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3242 
3243       nodes->push(n_compare);
3244       nodes->push(n_sub_base);
3245       nodes->push(n_shift);
3246       nodes->push(n_cond_set);
3247 
3248     } else {
3249       // before Power 7
3250       moveRegNode        *n_move     = new moveRegNode();
3251       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
3252       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
3253       cond_sub_baseNode  *n_sub_base = new cond_sub_baseNode();
3254 
3255       n_move->add_req(n_region, n_src);
3256       n_move->_opnds[0] = op_dst;
3257       n_move->_opnds[1] = op_src;
3258       ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
3259 
3260       n_compare->add_req(n_region, n_src);
3261       n_compare->add_prec(n_move);
3262 
3263       n_compare->_opnds[0] = op_crx;
3264       n_compare->_opnds[1] = op_src;
3265       n_compare->_opnds[2] = new immL16Oper(0);
3266 
3267       n_sub_base->add_req(n_region, n_compare, n_src);
3268       n_sub_base->_opnds[0] = op_dst;
3269       n_sub_base->_opnds[1] = op_crx;
3270       n_sub_base->_opnds[2] = op_src;
3271       n_sub_base->_bottom_type = _bottom_type;
3272 
3273       n_shift->add_req(n_region, n_sub_base);
3274       n_shift->_opnds[0] = op_dst;
3275       n_shift->_opnds[1] = op_dst;
3276       n_shift->_bottom_type = _bottom_type;
3277 
3278       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3279       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3280       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3281       ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3282 
3283       nodes->push(n_move);
3284       nodes->push(n_compare);
3285       nodes->push(n_sub_base);
3286       nodes->push(n_shift);
3287     }
3288 
3289     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3290   %}
3291 
3292   enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
3293 
3294     encodeP_subNode *n1 = new encodeP_subNode();
3295     n1->add_req(n_region, n_src);
3296     n1->_opnds[0] = op_dst;
3297     n1->_opnds[1] = op_src;
3298     n1->_bottom_type = _bottom_type;
3299 
3300     encodeP_shiftNode *n2 = new encodeP_shiftNode();
3301     n2->add_req(n_region, n1);
3302     n2->_opnds[0] = op_dst;
3303     n2->_opnds[1] = op_dst;
3304     n2->_bottom_type = _bottom_type;
3305     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3306     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3307 
3308     nodes->push(n1);
3309     nodes->push(n2);
3310     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3311   %}
3312 
3313   enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3314     decodeN_shiftNode *n_shift    = new decodeN_shiftNode();
3315     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
3316 
3317     n_compare->add_req(n_region, n_src);
3318     n_compare->_opnds[0] = op_crx;
3319     n_compare->_opnds[1] = op_src;
3320     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
3321 
3322     n_shift->add_req(n_region, n_src);
3323     n_shift->_opnds[0] = op_dst;
3324     n_shift->_opnds[1] = op_src;
3325     n_shift->_bottom_type = _bottom_type;
3326 
3327     if (VM_Version::has_isel()) {
3328       // use isel instruction with Power 7
3329 
3330       decodeN_addNode *n_add_base = new decodeN_addNode();
3331       n_add_base->add_req(n_region, n_shift);
3332       n_add_base->_opnds[0] = op_dst;
3333       n_add_base->_opnds[1] = op_dst;
3334       n_add_base->_bottom_type = _bottom_type;
3335 
3336       cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
3337       n_cond_set->add_req(n_region, n_compare, n_add_base);
3338       n_cond_set->_opnds[0] = op_dst;
3339       n_cond_set->_opnds[1] = op_crx;
3340       n_cond_set->_opnds[2] = op_dst;
3341       n_cond_set->_bottom_type = _bottom_type;
3342 
3343       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3344       ra_->set_oop(n_cond_set, true);
3345 
3346       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3347       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3348       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3349       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3350 
3351       nodes->push(n_compare);
3352       nodes->push(n_shift);
3353       nodes->push(n_add_base);
3354       nodes->push(n_cond_set);
3355 
3356     } else {
3357       // before Power 7
3358       cond_add_baseNode *n_add_base = new cond_add_baseNode();
3359 
3360       n_add_base->add_req(n_region, n_compare, n_shift);
3361       n_add_base->_opnds[0] = op_dst;
3362       n_add_base->_opnds[1] = op_crx;
3363       n_add_base->_opnds[2] = op_dst;
3364       n_add_base->_bottom_type = _bottom_type;
3365 
3366       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3367       ra_->set_oop(n_add_base, true);
3368 
3369       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3370       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3371       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3372 
3373       nodes->push(n_compare);
3374       nodes->push(n_shift);
3375       nodes->push(n_add_base);
3376     }
3377   %}
3378 
3379   enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3380     decodeN_shiftNode *n1 = new decodeN_shiftNode();
3381     n1->add_req(n_region, n_src);
3382     n1->_opnds[0] = op_dst;
3383     n1->_opnds[1] = op_src;
3384     n1->_bottom_type = _bottom_type;
3385 
3386     decodeN_addNode *n2 = new decodeN_addNode();
3387     n2->add_req(n_region, n1);
3388     n2->_opnds[0] = op_dst;
3389     n2->_opnds[1] = op_dst;
3390     n2->_bottom_type = _bottom_type;
3391     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3392     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3393 
3394     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3395     ra_->set_oop(n2, true);
3396 
3397     nodes->push(n1);
3398     nodes->push(n2);
3399   %}
3400 
3401   enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3402     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3403 
3404     MacroAssembler _masm(&cbuf);
3405     int cc        = $cmp$$cmpcode;
3406     int flags_reg = $crx$$reg;
3407     Label done;
3408     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3409     // Branch if not (cmp crx).
3410     __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3411     __ mr($dst$$Register, $src$$Register);
3412     // TODO PPC port __ endgroup_if_needed(_size == 12);
3413     __ bind(done);
3414   %}
3415 
3416   enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3417     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3418 
3419     MacroAssembler _masm(&cbuf);
3420     Label done;
3421     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3422     // Branch if not (cmp crx).
3423     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3424     __ li($dst$$Register, $src$$constant);
3425     // TODO PPC port __ endgroup_if_needed(_size == 12);
3426     __ bind(done);
3427   %}
3428 
3429   // This enc_class is needed so that scheduler gets proper
3430   // input mapping for latency computation.
3431   enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3432     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3433     MacroAssembler _masm(&cbuf);
3434     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3435   %}
3436 
3437   enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3438     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3439 
3440     MacroAssembler _masm(&cbuf);
3441 
3442     Label done;
3443     __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3444     __ li($dst$$Register, $zero$$constant);
3445     __ beq($crx$$CondRegister, done);
3446     __ li($dst$$Register, $notzero$$constant);
3447     __ bind(done);
3448   %}
3449 
3450   enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3451     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3452 
3453     MacroAssembler _masm(&cbuf);
3454 
3455     Label done;
3456     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3457     __ li($dst$$Register, $zero$$constant);
3458     __ beq($crx$$CondRegister, done);
3459     __ li($dst$$Register, $notzero$$constant);
3460     __ bind(done);
3461   %}
3462 
3463   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3464     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3465 
3466     MacroAssembler _masm(&cbuf);
3467     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3468     Label done;
3469     __ bso($crx$$CondRegister, done);
3470     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3471     // TODO PPC port __ endgroup_if_needed(_size == 12);
3472     __ bind(done);
3473   %}
3474 
3475   enc_class enc_cmove_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
3476     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3477 
3478     MacroAssembler _masm(&cbuf);
3479     Label done;
3480     __ bso($crx$$CondRegister, done);
3481     __ mffprd($dst$$Register, $src$$FloatRegister);
3482     // TODO PPC port __ endgroup_if_needed(_size == 12);
3483     __ bind(done);
3484   %}
3485 
3486   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3487     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3488 
3489     MacroAssembler _masm(&cbuf);
3490     Label d;   // dummy
3491     __ bind(d);
3492     Label* p = ($lbl$$label);
3493     // `p' is `NULL' when this encoding class is used only to
3494     // determine the size of the encoded instruction.
3495     Label& l = (NULL == p)? d : *(p);
3496     int cc = $cmp$$cmpcode;
3497     int flags_reg = $crx$$reg;
3498     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3499     int bhint = Assembler::bhintNoHint;
3500 
3501     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3502       if (_prob <= PROB_NEVER) {
3503         bhint = Assembler::bhintIsNotTaken;
3504       } else if (_prob >= PROB_ALWAYS) {
3505         bhint = Assembler::bhintIsTaken;
3506       }
3507     }
3508 
3509     __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3510           cc_to_biint(cc, flags_reg),
3511           l);
3512   %}
3513 
3514   enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3515     // The scheduler doesn't know about branch shortening, so we set the opcode
3516     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3517     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3518 
3519     MacroAssembler _masm(&cbuf);
3520     Label d;    // dummy
3521     __ bind(d);
3522     Label* p = ($lbl$$label);
3523     // `p' is `NULL' when this encoding class is used only to
3524     // determine the size of the encoded instruction.
3525     Label& l = (NULL == p)? d : *(p);
3526     int cc = $cmp$$cmpcode;
3527     int flags_reg = $crx$$reg;
3528     int bhint = Assembler::bhintNoHint;
3529 
3530     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3531       if (_prob <= PROB_NEVER) {
3532         bhint = Assembler::bhintIsNotTaken;
3533       } else if (_prob >= PROB_ALWAYS) {
3534         bhint = Assembler::bhintIsTaken;
3535       }
3536     }
3537 
3538     // Tell the conditional far branch to optimize itself when being relocated.
3539     __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3540                   cc_to_biint(cc, flags_reg),
3541                   l,
3542                   MacroAssembler::bc_far_optimize_on_relocate);
3543   %}
3544 
3545   // Branch used with Power6 scheduling (can be shortened without changing the node).
3546   enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3547     // The scheduler doesn't know about branch shortening, so we set the opcode
3548     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3549     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3550 
3551     MacroAssembler _masm(&cbuf);
3552     Label d;   // dummy
3553     __ bind(d);
3554     Label* p = ($lbl$$label);
3555     // `p' is `NULL' when this encoding class is used only to
3556     // determine the size of the encoded instruction.
3557     Label& l = (NULL == p)? d : *(p);
3558     int cc = $cmp$$cmpcode;
3559     int flags_reg = $crx$$reg;
3560     int bhint = Assembler::bhintNoHint;
3561 
3562     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3563       if (_prob <= PROB_NEVER) {
3564         bhint = Assembler::bhintIsNotTaken;
3565       } else if (_prob >= PROB_ALWAYS) {
3566         bhint = Assembler::bhintIsTaken;
3567       }
3568     }
3569 
3570 #if 0 // TODO: PPC port
3571     if (_size == 8) {
3572       // Tell the conditional far branch to optimize itself when being relocated.
3573       __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3574                     cc_to_biint(cc, flags_reg),
3575                     l,
3576                     MacroAssembler::bc_far_optimize_on_relocate);
3577     } else {
3578       __ bc    (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3579                     cc_to_biint(cc, flags_reg),
3580                     l);
3581     }
3582 #endif
3583     Unimplemented();
3584   %}
3585 
3586   // Postalloc expand emitter for loading a replicatef float constant from
3587   // the method's TOC.
3588   // Enc_class needed as consttanttablebase is not supported by postalloc
3589   // expand.
3590   enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3591     // Create new nodes.
3592 
3593     // Make an operand with the bit pattern to load as float.
3594     immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3595 
3596     loadConLNodesTuple loadConLNodes =
3597       loadConLNodesTuple_create(ra_, n_toc, op_repl,
3598                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
3599 
3600     // Push new nodes.
3601     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3602     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
3603 
3604     assert(nodes->length() >= 1, "must have created at least 1 node");
3605     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3606   %}
3607 
3608   enc_class postalloc_expand_load_replF_constant_vsx(vecX dst, immF src, iRegLdst toc, iRegLdst tmp) %{
3609     // Create new nodes.
3610 
3611     // Make an operand with the bit pattern to load as float.
3612     immLOper *op_repl = new  immLOper((jlong)replicate_immF(op_src->constantF()));
3613     immI_0Oper *op_zero = new  immI_0Oper(0);
3614 
3615     loadConLReplicatedNodesTuple loadConLNodes =
3616       loadConLReplicatedNodesTuple_create(C, ra_, n_toc, op_repl, op_dst, op_zero,
3617                                 ra_->get_reg_second(n_tmp), ra_->get_reg_first(n_tmp),
3618                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
3619 
3620     // Push new nodes.
3621     if (loadConLNodes._large_hi) { nodes->push(loadConLNodes._large_hi); }
3622     if (loadConLNodes._large_lo) { nodes->push(loadConLNodes._large_lo); }
3623     if (loadConLNodes._moved)    { nodes->push(loadConLNodes._moved); }
3624     if (loadConLNodes._last)     { nodes->push(loadConLNodes._last); }
3625 
3626     assert(nodes->length() >= 1, "must have created at least 1 node");
3627   %}
3628 
3629   // This enc_class is needed so that scheduler gets proper
3630   // input mapping for latency computation.
3631   enc_class enc_poll(immI dst, iRegLdst poll) %{
3632     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3633     // Fake operand dst needed for PPC scheduler.
3634     assert($dst$$constant == 0x0, "dst must be 0x0");
3635 
3636     MacroAssembler _masm(&cbuf);
3637     // Mark the code position where the load from the safepoint
3638     // polling page was emitted as relocInfo::poll_type.
3639     __ relocate(relocInfo::poll_type);
3640     __ load_from_polling_page($poll$$Register);
3641   %}
3642 
3643   // A Java static call or a runtime call.
3644   //
3645   // Branch-and-link relative to a trampoline.
3646   // The trampoline loads the target address and does a long branch to there.
3647   // In case we call java, the trampoline branches to a interpreter_stub
3648   // which loads the inline cache and the real call target from the constant pool.
3649   //
3650   // This basically looks like this:
3651   //
3652   // >>>> consts      -+  -+
3653   //                   |   |- offset1
3654   // [call target1]    | <-+
3655   // [IC cache]        |- offset2
3656   // [call target2] <--+
3657   //
3658   // <<<< consts
3659   // >>>> insts
3660   //
3661   // bl offset16               -+  -+             ??? // How many bits available?
3662   //                            |   |
3663   // <<<< insts                 |   |
3664   // >>>> stubs                 |   |
3665   //                            |   |- trampoline_stub_Reloc
3666   // trampoline stub:           | <-+
3667   //   r2 = toc                 |
3668   //   r2 = [r2 + offset1]      |       // Load call target1 from const section
3669   //   mtctr r2                 |
3670   //   bctr                     |- static_stub_Reloc
3671   // comp_to_interp_stub:   <---+
3672   //   r1 = toc
3673   //   ICreg = [r1 + IC_offset]         // Load IC from const section
3674   //   r1    = [r1 + offset2]           // Load call target2 from const section
3675   //   mtctr r1
3676   //   bctr
3677   //
3678   // <<<< stubs
3679   //
3680   // The call instruction in the code either
3681   // - Branches directly to a compiled method if the offset is encodable in instruction.
3682   // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3683   // - Branches to the compiled_to_interp stub if the target is interpreted.
3684   //
3685   // Further there are three relocations from the loads to the constants in
3686   // the constant section.
3687   //
3688   // Usage of r1 and r2 in the stubs allows to distinguish them.
3689   enc_class enc_java_static_call(method meth) %{
3690     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3691 
3692     MacroAssembler _masm(&cbuf);
3693     address entry_point = (address)$meth$$method;
3694 
3695     if (!_method) {
3696       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3697       emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3698     } else {
3699       // Remember the offset not the address.
3700       const int start_offset = __ offset();
3701 
3702       // The trampoline stub.
3703       // No entry point given, use the current pc.
3704       // Make sure branch fits into
3705       if (entry_point == 0) entry_point = __ pc();
3706 
3707       // Put the entry point as a constant into the constant pool.
3708       const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3709       if (entry_point_toc_addr == NULL) {
3710         ciEnv::current()->record_out_of_memory_failure();
3711         return;
3712       }
3713       const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3714 
3715       // Emit the trampoline stub which will be related to the branch-and-link below.
3716       CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3717       if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3718       int method_index = resolved_method_index(cbuf);
3719       __ relocate(_optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
3720                   : static_call_Relocation::spec(method_index));
3721 
3722       // The real call.
3723       // Note: At this point we do not have the address of the trampoline
3724       // stub, and the entry point might be too far away for bl, so __ pc()
3725       // serves as dummy and the bl will be patched later.
3726       cbuf.set_insts_mark();
3727       __ bl(__ pc());  // Emits a relocation.
3728 
3729       // The stub for call to interpreter.
3730       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3731       if (stub == NULL) {
3732         ciEnv::current()->record_failure("CodeCache is full");
3733         return;
3734       }
3735     }
3736   %}
3737 
3738   // Second node of expanded dynamic call - the call.
3739   enc_class enc_java_dynamic_call_sched(method meth) %{
3740     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3741 
3742     MacroAssembler _masm(&cbuf);
3743 
3744     if (!ra_->C->in_scratch_emit_size()) {
3745       // Create a call trampoline stub for the given method.
3746       const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3747       const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3748       if (entry_point_const == NULL) {
3749         ciEnv::current()->record_out_of_memory_failure();
3750         return;
3751       }
3752       const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3753       CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3754       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3755 
3756       // Build relocation at call site with ic position as data.
3757       assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3758              (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3759              "must have one, but can't have both");
3760       assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3761              (_load_ic_node != NULL    && _load_ic_node->_cbuf_insts_offset != -1),
3762              "must contain instruction offset");
3763       const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3764         ? _load_ic_hi_node->_cbuf_insts_offset
3765         : _load_ic_node->_cbuf_insts_offset;
3766       const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3767       assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3768              "should be load from TOC");
3769       int method_index = resolved_method_index(cbuf);
3770       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
3771     }
3772 
3773     // At this point I do not have the address of the trampoline stub,
3774     // and the entry point might be too far away for bl. Pc() serves
3775     // as dummy and bl will be patched later.
3776     __ bl((address) __ pc());
3777   %}
3778 
3779   // postalloc expand emitter for virtual calls.
3780   enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3781 
3782     // Create the nodes for loading the IC from the TOC.
3783     loadConLNodesTuple loadConLNodes_IC =
3784       loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3785                                 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3786 
3787     // Create the call node.
3788     CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3789     call->_method_handle_invoke = _method_handle_invoke;
3790     call->_vtable_index      = _vtable_index;
3791     call->_method            = _method;
3792     call->_bci               = _bci;
3793     call->_optimized_virtual = _optimized_virtual;
3794     call->_tf                = _tf;
3795     call->_entry_point       = _entry_point;
3796     call->_cnt               = _cnt;
3797     call->_argsize           = _argsize;
3798     call->_oop_map           = _oop_map;
3799     call->_jvms              = _jvms;
3800     call->_jvmadj            = _jvmadj;
3801     call->_in_rms            = _in_rms;
3802     call->_nesting           = _nesting;
3803     call->_override_symbolic_info = _override_symbolic_info;
3804 
3805     // New call needs all inputs of old call.
3806     // Req...
3807     for (uint i = 0; i < req(); ++i) {
3808       // The expanded node does not need toc any more.
3809       // Add the inline cache constant here instead. This expresses the
3810       // register of the inline cache must be live at the call.
3811       // Else we would have to adapt JVMState by -1.
3812       if (i == mach_constant_base_node_input()) {
3813         call->add_req(loadConLNodes_IC._last);
3814       } else {
3815         call->add_req(in(i));
3816       }
3817     }
3818     // ...as well as prec
3819     for (uint i = req(); i < len(); ++i) {
3820       call->add_prec(in(i));
3821     }
3822 
3823     // Remember nodes loading the inline cache into r19.
3824     call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3825     call->_load_ic_node    = loadConLNodes_IC._small;
3826 
3827     // Operands for new nodes.
3828     call->_opnds[0] = _opnds[0];
3829     call->_opnds[1] = _opnds[1];
3830 
3831     // Only the inline cache is associated with a register.
3832     assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3833 
3834     // Push new nodes.
3835     if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3836     if (loadConLNodes_IC._last)     nodes->push(loadConLNodes_IC._last);
3837     nodes->push(call);
3838   %}
3839 
3840   // Compound version of call dynamic
3841   // Toc is only passed so that it can be used in ins_encode statement.
3842   // In the code we have to use $constanttablebase.
3843   enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3844     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3845     MacroAssembler _masm(&cbuf);
3846     int start_offset = __ offset();
3847 
3848     Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3849 #if 0
3850     int vtable_index = this->_vtable_index;
3851     if (_vtable_index < 0) {
3852       // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3853       assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3854       Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3855 
3856       // Virtual call relocation will point to ic load.
3857       address virtual_call_meta_addr = __ pc();
3858       // Load a clear inline cache.
3859       AddressLiteral empty_ic((address) Universe::non_oop_word());
3860       bool success = __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc, /*fixed_size*/ true);
3861       if (!success) {
3862         ciEnv::current()->record_out_of_memory_failure();
3863         return;
3864       }
3865       // CALL to fixup routine.  Fixup routine uses ScopeDesc info
3866       // to determine who we intended to call.
3867       __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3868       emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3869       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3870              "Fix constant in ret_addr_offset()");
3871     } else {
3872       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3873       // Go thru the vtable. Get receiver klass. Receiver already
3874       // checked for non-null. If we'll go thru a C2I adapter, the
3875       // interpreter expects method in R19_method.
3876 
3877       __ load_klass(R11_scratch1, R3);
3878 
3879       int entry_offset = in_bytes(Klass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes();
3880       int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
3881       __ li(R19_method, v_off);
3882       __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3883       // NOTE: for vtable dispatches, the vtable entry will never be
3884       // null. However it may very well end up in handle_wrong_method
3885       // if the method is abstract for the particular class.
3886       __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3887       // Call target. Either compiled code or C2I adapter.
3888       __ mtctr(R11_scratch1);
3889       __ bctrl();
3890       if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3891         tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3892       }
3893       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3894              "Fix constant in ret_addr_offset()");
3895     }
3896 #endif
3897     Unimplemented();  // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3898   %}
3899 
3900   // a runtime call
3901   enc_class enc_java_to_runtime_call (method meth) %{
3902     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3903 
3904     MacroAssembler _masm(&cbuf);
3905     const address start_pc = __ pc();
3906 
3907 #if defined(ABI_ELFv2)
3908     address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3909     __ call_c(entry, relocInfo::runtime_call_type);
3910 #else
3911     // The function we're going to call.
3912     FunctionDescriptor fdtemp;
3913     const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3914 
3915     Register Rtoc = R12_scratch2;
3916     // Calculate the method's TOC.
3917     __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3918     // Put entry, env, toc into the constant pool, this needs up to 3 constant
3919     // pool entries; call_c_using_toc will optimize the call.
3920     bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3921     if (!success) {
3922       ciEnv::current()->record_out_of_memory_failure();
3923       return;
3924     }
3925 #endif
3926 
3927     // Check the ret_addr_offset.
3928     assert(((MachCallRuntimeNode*)this)->ret_addr_offset() ==  __ last_calls_return_pc() - start_pc,
3929            "Fix constant in ret_addr_offset()");
3930   %}
3931 
3932   // Move to ctr for leaf call.
3933   // This enc_class is needed so that scheduler gets proper
3934   // input mapping for latency computation.
3935   enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3936     // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3937     MacroAssembler _masm(&cbuf);
3938     __ mtctr($src$$Register);
3939   %}
3940 
3941   // Postalloc expand emitter for runtime leaf calls.
3942   enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3943     loadConLNodesTuple loadConLNodes_Entry;
3944 #if defined(ABI_ELFv2)
3945     jlong entry_address = (jlong) this->entry_point();
3946     assert(entry_address, "need address here");
3947     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3948                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3949 #else
3950     // Get the struct that describes the function we are about to call.
3951     FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3952     assert(fd, "need fd here");
3953     jlong entry_address = (jlong) fd->entry();
3954     // new nodes
3955     loadConLNodesTuple loadConLNodes_Env;
3956     loadConLNodesTuple loadConLNodes_Toc;
3957 
3958     // Create nodes and operands for loading the entry point.
3959     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3960                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3961 
3962 
3963     // Create nodes and operands for loading the env pointer.
3964     if (fd->env() != NULL) {
3965       loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3966                                                     OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3967     } else {
3968       loadConLNodes_Env._large_hi = NULL;
3969       loadConLNodes_Env._large_lo = NULL;
3970       loadConLNodes_Env._small    = NULL;
3971       loadConLNodes_Env._last = new loadConL16Node();
3972       loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3973       loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3974       ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3975     }
3976 
3977     // Create nodes and operands for loading the Toc point.
3978     loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3979                                                   OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3980 #endif // ABI_ELFv2
3981     // mtctr node
3982     MachNode *mtctr = new CallLeafDirect_mtctrNode();
3983 
3984     assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3985     mtctr->add_req(0, loadConLNodes_Entry._last);
3986 
3987     mtctr->_opnds[0] = new iRegLdstOper();
3988     mtctr->_opnds[1] = new iRegLdstOper();
3989 
3990     // call node
3991     MachCallLeafNode *call = new CallLeafDirectNode();
3992 
3993     call->_opnds[0] = _opnds[0];
3994     call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3995 
3996     // Make the new call node look like the old one.
3997     call->_name        = _name;
3998     call->_tf          = _tf;
3999     call->_entry_point = _entry_point;
4000     call->_cnt         = _cnt;
4001     call->_argsize     = _argsize;
4002     call->_oop_map     = _oop_map;
4003     guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
4004     call->_jvms        = NULL;
4005     call->_jvmadj      = _jvmadj;
4006     call->_in_rms      = _in_rms;
4007     call->_nesting     = _nesting;
4008 
4009 
4010     // New call needs all inputs of old call.
4011     // Req...
4012     for (uint i = 0; i < req(); ++i) {
4013       if (i != mach_constant_base_node_input()) {
4014         call->add_req(in(i));
4015       }
4016     }
4017 
4018     // These must be reqired edges, as the registers are live up to
4019     // the call. Else the constants are handled as kills.
4020     call->add_req(mtctr);
4021 #if !defined(ABI_ELFv2)
4022     call->add_req(loadConLNodes_Env._last);
4023     call->add_req(loadConLNodes_Toc._last);
4024 #endif
4025 
4026     // ...as well as prec
4027     for (uint i = req(); i < len(); ++i) {
4028       call->add_prec(in(i));
4029     }
4030 
4031     // registers
4032     ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
4033 
4034     // Insert the new nodes.
4035     if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
4036     if (loadConLNodes_Entry._last)     nodes->push(loadConLNodes_Entry._last);
4037 #if !defined(ABI_ELFv2)
4038     if (loadConLNodes_Env._large_hi)   nodes->push(loadConLNodes_Env._large_hi);
4039     if (loadConLNodes_Env._last)       nodes->push(loadConLNodes_Env._last);
4040     if (loadConLNodes_Toc._large_hi)   nodes->push(loadConLNodes_Toc._large_hi);
4041     if (loadConLNodes_Toc._last)       nodes->push(loadConLNodes_Toc._last);
4042 #endif
4043     nodes->push(mtctr);
4044     nodes->push(call);
4045   %}
4046 %}
4047 
4048 //----------FRAME--------------------------------------------------------------
4049 // Definition of frame structure and management information.
4050 
4051 frame %{
4052   // What direction does stack grow in (assumed to be same for native & Java).
4053   stack_direction(TOWARDS_LOW);
4054 
4055   // These two registers define part of the calling convention between
4056   // compiled code and the interpreter.
4057 
4058   // Inline Cache Register or method for I2C.
4059   inline_cache_reg(R19); // R19_method
4060 
4061   // Method Oop Register when calling interpreter.
4062   interpreter_method_oop_reg(R19); // R19_method
4063 
4064   // Optional: name the operand used by cisc-spilling to access
4065   // [stack_pointer + offset].
4066   cisc_spilling_operand_name(indOffset);
4067 
4068   // Number of stack slots consumed by a Monitor enter.
4069   sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
4070 
4071   // Compiled code's Frame Pointer.
4072   frame_pointer(R1); // R1_SP
4073 
4074   // Interpreter stores its frame pointer in a register which is
4075   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
4076   // interpreted java to compiled java.
4077   //
4078   // R14_state holds pointer to caller's cInterpreter.
4079   interpreter_frame_pointer(R14); // R14_state
4080 
4081   stack_alignment(frame::alignment_in_bytes);
4082 
4083   in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
4084 
4085   // Number of outgoing stack slots killed above the
4086   // out_preserve_stack_slots for calls to C. Supports the var-args
4087   // backing area for register parms.
4088   //
4089   varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
4090 
4091   // The after-PROLOG location of the return address. Location of
4092   // return address specifies a type (REG or STACK) and a number
4093   // representing the register number (i.e. - use a register name) or
4094   // stack slot.
4095   //
4096   // A: Link register is stored in stack slot ...
4097   // M:  ... but it's in the caller's frame according to PPC-64 ABI.
4098   // J: Therefore, we make sure that the link register is also in R11_scratch1
4099   //    at the end of the prolog.
4100   // B: We use R20, now.
4101   //return_addr(REG R20);
4102 
4103   // G: After reading the comments made by all the luminaries on their
4104   //    failure to tell the compiler where the return address really is,
4105   //    I hardly dare to try myself.  However, I'm convinced it's in slot
4106   //    4 what apparently works and saves us some spills.
4107   return_addr(STACK 4);
4108 
4109   // This is the body of the function
4110   //
4111   // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
4112   //                                  uint length,      // length of array
4113   //                                  bool is_outgoing)
4114   //
4115   // The `sig' array is to be updated. sig[j] represents the location
4116   // of the j-th argument, either a register or a stack slot.
4117 
4118   // Comment taken from i486.ad:
4119   // Body of function which returns an integer array locating
4120   // arguments either in registers or in stack slots. Passed an array
4121   // of ideal registers called "sig" and a "length" count. Stack-slot
4122   // offsets are based on outgoing arguments, i.e. a CALLER setting up
4123   // arguments for a CALLEE. Incoming stack arguments are
4124   // automatically biased by the preserve_stack_slots field above.
4125   calling_convention %{
4126     // No difference between ingoing/outgoing. Just pass false.
4127     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4128   %}
4129 
4130   // Comment taken from i486.ad:
4131   // Body of function which returns an integer array locating
4132   // arguments either in registers or in stack slots. Passed an array
4133   // of ideal registers called "sig" and a "length" count. Stack-slot
4134   // offsets are based on outgoing arguments, i.e. a CALLER setting up
4135   // arguments for a CALLEE. Incoming stack arguments are
4136   // automatically biased by the preserve_stack_slots field above.
4137   c_calling_convention %{
4138     // This is obviously always outgoing.
4139     // C argument in register AND stack slot.
4140     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
4141   %}
4142 
4143   // Location of native (C/C++) and interpreter return values. This
4144   // is specified to be the same as Java. In the 32-bit VM, long
4145   // values are actually returned from native calls in O0:O1 and
4146   // returned to the interpreter in I0:I1. The copying to and from
4147   // the register pairs is done by the appropriate call and epilog
4148   // opcodes. This simplifies the register allocator.
4149   c_return_value %{
4150     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
4151             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
4152             "only return normal values");
4153     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
4154     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
4155     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
4156     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
4157   %}
4158 
4159   // Location of compiled Java return values.  Same as C
4160   return_value %{
4161     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
4162             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
4163             "only return normal values");
4164     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
4165     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
4166     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
4167     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
4168   %}
4169 %}
4170 
4171 
4172 //----------ATTRIBUTES---------------------------------------------------------
4173 
4174 //----------Operand Attributes-------------------------------------------------
4175 op_attrib op_cost(1);          // Required cost attribute.
4176 
4177 //----------Instruction Attributes---------------------------------------------
4178 
4179 // Cost attribute. required.
4180 ins_attrib ins_cost(DEFAULT_COST);
4181 
4182 // Is this instruction a non-matching short branch variant of some
4183 // long branch? Not required.
4184 ins_attrib ins_short_branch(0);
4185 
4186 ins_attrib ins_is_TrapBasedCheckNode(true);
4187 
4188 // Number of constants.
4189 // This instruction uses the given number of constants
4190 // (optional attribute).
4191 // This is needed to determine in time whether the constant pool will
4192 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4193 // is determined. It's also used to compute the constant pool size
4194 // in Output().
4195 ins_attrib ins_num_consts(0);
4196 
4197 // Required alignment attribute (must be a power of 2) specifies the
4198 // alignment that some part of the instruction (not necessarily the
4199 // start) requires. If > 1, a compute_padding() function must be
4200 // provided for the instruction.
4201 ins_attrib ins_alignment(1);
4202 
4203 // Enforce/prohibit rematerializations.
4204 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4205 //   then rematerialization of that instruction is prohibited and the
4206 //   instruction's value will be spilled if necessary.
4207 //   Causes that MachNode::rematerialize() returns false.
4208 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4209 //   then rematerialization should be enforced and a copy of the instruction
4210 //   should be inserted if possible; rematerialization is not guaranteed.
4211 //   Note: this may result in rematerializations in front of every use.
4212 //   Causes that MachNode::rematerialize() can return true.
4213 // (optional attribute)
4214 ins_attrib ins_cannot_rematerialize(false);
4215 ins_attrib ins_should_rematerialize(false);
4216 
4217 // Instruction has variable size depending on alignment.
4218 ins_attrib ins_variable_size_depending_on_alignment(false);
4219 
4220 // Instruction is a nop.
4221 ins_attrib ins_is_nop(false);
4222 
4223 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4224 ins_attrib ins_use_mach_if_fast_lock_node(false);
4225 
4226 // Field for the toc offset of a constant.
4227 //
4228 // This is needed if the toc offset is not encodable as an immediate in
4229 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4230 // added to the toc, and from this a load with immediate is performed.
4231 // With postalloc expand, we get two nodes that require the same offset
4232 // but which don't know about each other. The offset is only known
4233 // when the constant is added to the constant pool during emitting.
4234 // It is generated in the 'hi'-node adding the upper bits, and saved
4235 // in this node.  The 'lo'-node has a link to the 'hi'-node and reads
4236 // the offset from there when it gets encoded.
4237 ins_attrib ins_field_const_toc_offset(0);
4238 ins_attrib ins_field_const_toc_offset_hi_node(0);
4239 
4240 // A field that can hold the instructions offset in the code buffer.
4241 // Set in the nodes emitter.
4242 ins_attrib ins_field_cbuf_insts_offset(-1);
4243 
4244 // Fields for referencing a call's load-IC-node.
4245 // If the toc offset can not be encoded as an immediate in a load, we
4246 // use two nodes.
4247 ins_attrib ins_field_load_ic_hi_node(0);
4248 ins_attrib ins_field_load_ic_node(0);
4249 
4250 //----------OPERANDS-----------------------------------------------------------
4251 // Operand definitions must precede instruction definitions for correct
4252 // parsing in the ADLC because operands constitute user defined types
4253 // which are used in instruction definitions.
4254 //
4255 // Formats are generated automatically for constants and base registers.
4256 
4257 operand vecX() %{
4258   constraint(ALLOC_IN_RC(vs_reg));
4259   match(VecX);
4260 
4261   format %{ %}
4262   interface(REG_INTER);
4263 %}
4264 
4265 //----------Simple Operands----------------------------------------------------
4266 // Immediate Operands
4267 
4268 // Integer Immediate: 32-bit
4269 operand immI() %{
4270   match(ConI);
4271   op_cost(40);
4272   format %{ %}
4273   interface(CONST_INTER);
4274 %}
4275 
4276 operand immI8() %{
4277   predicate(Assembler::is_simm(n->get_int(), 8));
4278   op_cost(0);
4279   match(ConI);
4280   format %{ %}
4281   interface(CONST_INTER);
4282 %}
4283 
4284 // Integer Immediate: 16-bit
4285 operand immI16() %{
4286   predicate(Assembler::is_simm(n->get_int(), 16));
4287   op_cost(0);
4288   match(ConI);
4289   format %{ %}
4290   interface(CONST_INTER);
4291 %}
4292 
4293 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4294 operand immIhi16() %{
4295   predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4296   match(ConI);
4297   op_cost(0);
4298   format %{ %}
4299   interface(CONST_INTER);
4300 %}
4301 
4302 operand immInegpow2() %{
4303   predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4304   match(ConI);
4305   op_cost(0);
4306   format %{ %}
4307   interface(CONST_INTER);
4308 %}
4309 
4310 operand immIpow2minus1() %{
4311   predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4312   match(ConI);
4313   op_cost(0);
4314   format %{ %}
4315   interface(CONST_INTER);
4316 %}
4317 
4318 operand immIpowerOf2() %{
4319   predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4320   match(ConI);
4321   op_cost(0);
4322   format %{ %}
4323   interface(CONST_INTER);
4324 %}
4325 
4326 // Unsigned Integer Immediate: the values 0-31
4327 operand uimmI5() %{
4328   predicate(Assembler::is_uimm(n->get_int(), 5));
4329   match(ConI);
4330   op_cost(0);
4331   format %{ %}
4332   interface(CONST_INTER);
4333 %}
4334 
4335 // Unsigned Integer Immediate: 6-bit
4336 operand uimmI6() %{
4337   predicate(Assembler::is_uimm(n->get_int(), 6));
4338   match(ConI);
4339   op_cost(0);
4340   format %{ %}
4341   interface(CONST_INTER);
4342 %}
4343 
4344 // Unsigned Integer Immediate:  6-bit int, greater than 32
4345 operand uimmI6_ge32() %{
4346   predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4347   match(ConI);
4348   op_cost(0);
4349   format %{ %}
4350   interface(CONST_INTER);
4351 %}
4352 
4353 // Unsigned Integer Immediate: 15-bit
4354 operand uimmI15() %{
4355   predicate(Assembler::is_uimm(n->get_int(), 15));
4356   match(ConI);
4357   op_cost(0);
4358   format %{ %}
4359   interface(CONST_INTER);
4360 %}
4361 
4362 // Unsigned Integer Immediate: 16-bit
4363 operand uimmI16() %{
4364   predicate(Assembler::is_uimm(n->get_int(), 16));
4365   match(ConI);
4366   op_cost(0);
4367   format %{ %}
4368   interface(CONST_INTER);
4369 %}
4370 
4371 // constant 'int 0'.
4372 operand immI_0() %{
4373   predicate(n->get_int() == 0);
4374   match(ConI);
4375   op_cost(0);
4376   format %{ %}
4377   interface(CONST_INTER);
4378 %}
4379 
4380 // constant 'int 1'.
4381 operand immI_1() %{
4382   predicate(n->get_int() == 1);
4383   match(ConI);
4384   op_cost(0);
4385   format %{ %}
4386   interface(CONST_INTER);
4387 %}
4388 
4389 // constant 'int -1'.
4390 operand immI_minus1() %{
4391   predicate(n->get_int() == -1);
4392   match(ConI);
4393   op_cost(0);
4394   format %{ %}
4395   interface(CONST_INTER);
4396 %}
4397 
4398 // int value 16.
4399 operand immI_16() %{
4400   predicate(n->get_int() == 16);
4401   match(ConI);
4402   op_cost(0);
4403   format %{ %}
4404   interface(CONST_INTER);
4405 %}
4406 
4407 // int value 24.
4408 operand immI_24() %{
4409   predicate(n->get_int() == 24);
4410   match(ConI);
4411   op_cost(0);
4412   format %{ %}
4413   interface(CONST_INTER);
4414 %}
4415 
4416 // Compressed oops constants
4417 // Pointer Immediate
4418 operand immN() %{
4419   match(ConN);
4420 
4421   op_cost(10);
4422   format %{ %}
4423   interface(CONST_INTER);
4424 %}
4425 
4426 // NULL Pointer Immediate
4427 operand immN_0() %{
4428   predicate(n->get_narrowcon() == 0);
4429   match(ConN);
4430 
4431   op_cost(0);
4432   format %{ %}
4433   interface(CONST_INTER);
4434 %}
4435 
4436 // Compressed klass constants
4437 operand immNKlass() %{
4438   match(ConNKlass);
4439 
4440   op_cost(0);
4441   format %{ %}
4442   interface(CONST_INTER);
4443 %}
4444 
4445 // This operand can be used to avoid matching of an instruct
4446 // with chain rule.
4447 operand immNKlass_NM() %{
4448   match(ConNKlass);
4449   predicate(false);
4450   op_cost(0);
4451   format %{ %}
4452   interface(CONST_INTER);
4453 %}
4454 
4455 // Pointer Immediate: 64-bit
4456 operand immP() %{
4457   match(ConP);
4458   op_cost(0);
4459   format %{ %}
4460   interface(CONST_INTER);
4461 %}
4462 
4463 // Operand to avoid match of loadConP.
4464 // This operand can be used to avoid matching of an instruct
4465 // with chain rule.
4466 operand immP_NM() %{
4467   match(ConP);
4468   predicate(false);
4469   op_cost(0);
4470   format %{ %}
4471   interface(CONST_INTER);
4472 %}
4473 
4474 // costant 'pointer 0'.
4475 operand immP_0() %{
4476   predicate(n->get_ptr() == 0);
4477   match(ConP);
4478   op_cost(0);
4479   format %{ %}
4480   interface(CONST_INTER);
4481 %}
4482 
4483 // pointer 0x0 or 0x1
4484 operand immP_0or1() %{
4485   predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4486   match(ConP);
4487   op_cost(0);
4488   format %{ %}
4489   interface(CONST_INTER);
4490 %}
4491 
4492 operand immL() %{
4493   match(ConL);
4494   op_cost(40);
4495   format %{ %}
4496   interface(CONST_INTER);
4497 %}
4498 
4499 operand immLmax30() %{
4500   predicate((n->get_long() <= 30));
4501   match(ConL);
4502   op_cost(0);
4503   format %{ %}
4504   interface(CONST_INTER);
4505 %}
4506 
4507 // Long Immediate: 16-bit
4508 operand immL16() %{
4509   predicate(Assembler::is_simm(n->get_long(), 16));
4510   match(ConL);
4511   op_cost(0);
4512   format %{ %}
4513   interface(CONST_INTER);
4514 %}
4515 
4516 // Long Immediate: 16-bit, 4-aligned
4517 operand immL16Alg4() %{
4518   predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4519   match(ConL);
4520   op_cost(0);
4521   format %{ %}
4522   interface(CONST_INTER);
4523 %}
4524 
4525 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4526 operand immL32hi16() %{
4527   predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4528   match(ConL);
4529   op_cost(0);
4530   format %{ %}
4531   interface(CONST_INTER);
4532 %}
4533 
4534 // Long Immediate: 32-bit
4535 operand immL32() %{
4536   predicate(Assembler::is_simm(n->get_long(), 32));
4537   match(ConL);
4538   op_cost(0);
4539   format %{ %}
4540   interface(CONST_INTER);
4541 %}
4542 
4543 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4544 operand immLhighest16() %{
4545   predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4546   match(ConL);
4547   op_cost(0);
4548   format %{ %}
4549   interface(CONST_INTER);
4550 %}
4551 
4552 operand immLnegpow2() %{
4553   predicate(is_power_of_2_long((jlong)-(n->get_long())));
4554   match(ConL);
4555   op_cost(0);
4556   format %{ %}
4557   interface(CONST_INTER);
4558 %}
4559 
4560 operand immLpow2minus1() %{
4561   predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4562             (n->get_long() != (jlong)0xffffffffffffffffL));
4563   match(ConL);
4564   op_cost(0);
4565   format %{ %}
4566   interface(CONST_INTER);
4567 %}
4568 
4569 // constant 'long 0'.
4570 operand immL_0() %{
4571   predicate(n->get_long() == 0L);
4572   match(ConL);
4573   op_cost(0);
4574   format %{ %}
4575   interface(CONST_INTER);
4576 %}
4577 
4578 // constat ' long -1'.
4579 operand immL_minus1() %{
4580   predicate(n->get_long() == -1L);
4581   match(ConL);
4582   op_cost(0);
4583   format %{ %}
4584   interface(CONST_INTER);
4585 %}
4586 
4587 // Long Immediate: low 32-bit mask
4588 operand immL_32bits() %{
4589   predicate(n->get_long() == 0xFFFFFFFFL);
4590   match(ConL);
4591   op_cost(0);
4592   format %{ %}
4593   interface(CONST_INTER);
4594 %}
4595 
4596 // Unsigned Long Immediate: 16-bit
4597 operand uimmL16() %{
4598   predicate(Assembler::is_uimm(n->get_long(), 16));
4599   match(ConL);
4600   op_cost(0);
4601   format %{ %}
4602   interface(CONST_INTER);
4603 %}
4604 
4605 // Float Immediate
4606 operand immF() %{
4607   match(ConF);
4608   op_cost(40);
4609   format %{ %}
4610   interface(CONST_INTER);
4611 %}
4612 
4613 // Float Immediate: +0.0f.
4614 operand immF_0() %{
4615   predicate(jint_cast(n->getf()) == 0);
4616   match(ConF);
4617 
4618   op_cost(0);
4619   format %{ %}
4620   interface(CONST_INTER);
4621 %}
4622 
4623 // Double Immediate
4624 operand immD() %{
4625   match(ConD);
4626   op_cost(40);
4627   format %{ %}
4628   interface(CONST_INTER);
4629 %}
4630 
4631 // Integer Register Operands
4632 // Integer Destination Register
4633 // See definition of reg_class bits32_reg_rw.
4634 operand iRegIdst() %{
4635   constraint(ALLOC_IN_RC(bits32_reg_rw));
4636   match(RegI);
4637   match(rscratch1RegI);
4638   match(rscratch2RegI);
4639   match(rarg1RegI);
4640   match(rarg2RegI);
4641   match(rarg3RegI);
4642   match(rarg4RegI);
4643   format %{ %}
4644   interface(REG_INTER);
4645 %}
4646 
4647 // Integer Source Register
4648 // See definition of reg_class bits32_reg_ro.
4649 operand iRegIsrc() %{
4650   constraint(ALLOC_IN_RC(bits32_reg_ro));
4651   match(RegI);
4652   match(rscratch1RegI);
4653   match(rscratch2RegI);
4654   match(rarg1RegI);
4655   match(rarg2RegI);
4656   match(rarg3RegI);
4657   match(rarg4RegI);
4658   format %{ %}
4659   interface(REG_INTER);
4660 %}
4661 
4662 operand rscratch1RegI() %{
4663   constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4664   match(iRegIdst);
4665   format %{ %}
4666   interface(REG_INTER);
4667 %}
4668 
4669 operand rscratch2RegI() %{
4670   constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4671   match(iRegIdst);
4672   format %{ %}
4673   interface(REG_INTER);
4674 %}
4675 
4676 operand rarg1RegI() %{
4677   constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4678   match(iRegIdst);
4679   format %{ %}
4680   interface(REG_INTER);
4681 %}
4682 
4683 operand rarg2RegI() %{
4684   constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4685   match(iRegIdst);
4686   format %{ %}
4687   interface(REG_INTER);
4688 %}
4689 
4690 operand rarg3RegI() %{
4691   constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4692   match(iRegIdst);
4693   format %{ %}
4694   interface(REG_INTER);
4695 %}
4696 
4697 operand rarg4RegI() %{
4698   constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4699   match(iRegIdst);
4700   format %{ %}
4701   interface(REG_INTER);
4702 %}
4703 
4704 operand rarg1RegL() %{
4705   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4706   match(iRegLdst);
4707   format %{ %}
4708   interface(REG_INTER);
4709 %}
4710 
4711 operand rarg2RegL() %{
4712   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4713   match(iRegLdst);
4714   format %{ %}
4715   interface(REG_INTER);
4716 %}
4717 
4718 operand rarg3RegL() %{
4719   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4720   match(iRegLdst);
4721   format %{ %}
4722   interface(REG_INTER);
4723 %}
4724 
4725 operand rarg4RegL() %{
4726   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4727   match(iRegLdst);
4728   format %{ %}
4729   interface(REG_INTER);
4730 %}
4731 
4732 // Pointer Destination Register
4733 // See definition of reg_class bits64_reg_rw.
4734 operand iRegPdst() %{
4735   constraint(ALLOC_IN_RC(bits64_reg_rw));
4736   match(RegP);
4737   match(rscratch1RegP);
4738   match(rscratch2RegP);
4739   match(rarg1RegP);
4740   match(rarg2RegP);
4741   match(rarg3RegP);
4742   match(rarg4RegP);
4743   format %{ %}
4744   interface(REG_INTER);
4745 %}
4746 
4747 // Pointer Destination Register
4748 // Operand not using r11 and r12 (killed in epilog).
4749 operand iRegPdstNoScratch() %{
4750   constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4751   match(RegP);
4752   match(rarg1RegP);
4753   match(rarg2RegP);
4754   match(rarg3RegP);
4755   match(rarg4RegP);
4756   format %{ %}
4757   interface(REG_INTER);
4758 %}
4759 
4760 // Pointer Source Register
4761 // See definition of reg_class bits64_reg_ro.
4762 operand iRegPsrc() %{
4763   constraint(ALLOC_IN_RC(bits64_reg_ro));
4764   match(RegP);
4765   match(iRegPdst);
4766   match(rscratch1RegP);
4767   match(rscratch2RegP);
4768   match(rarg1RegP);
4769   match(rarg2RegP);
4770   match(rarg3RegP);
4771   match(rarg4RegP);
4772   match(threadRegP);
4773   format %{ %}
4774   interface(REG_INTER);
4775 %}
4776 
4777 // Thread operand.
4778 operand threadRegP() %{
4779   constraint(ALLOC_IN_RC(thread_bits64_reg));
4780   match(iRegPdst);
4781   format %{ "R16" %}
4782   interface(REG_INTER);
4783 %}
4784 
4785 operand rscratch1RegP() %{
4786   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4787   match(iRegPdst);
4788   format %{ "R11" %}
4789   interface(REG_INTER);
4790 %}
4791 
4792 operand rscratch2RegP() %{
4793   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4794   match(iRegPdst);
4795   format %{ %}
4796   interface(REG_INTER);
4797 %}
4798 
4799 operand rarg1RegP() %{
4800   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4801   match(iRegPdst);
4802   format %{ %}
4803   interface(REG_INTER);
4804 %}
4805 
4806 operand rarg2RegP() %{
4807   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4808   match(iRegPdst);
4809   format %{ %}
4810   interface(REG_INTER);
4811 %}
4812 
4813 operand rarg3RegP() %{
4814   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4815   match(iRegPdst);
4816   format %{ %}
4817   interface(REG_INTER);
4818 %}
4819 
4820 operand rarg4RegP() %{
4821   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4822   match(iRegPdst);
4823   format %{ %}
4824   interface(REG_INTER);
4825 %}
4826 
4827 operand iRegNsrc() %{
4828   constraint(ALLOC_IN_RC(bits32_reg_ro));
4829   match(RegN);
4830   match(iRegNdst);
4831 
4832   format %{ %}
4833   interface(REG_INTER);
4834 %}
4835 
4836 operand iRegNdst() %{
4837   constraint(ALLOC_IN_RC(bits32_reg_rw));
4838   match(RegN);
4839 
4840   format %{ %}
4841   interface(REG_INTER);
4842 %}
4843 
4844 // Long Destination Register
4845 // See definition of reg_class bits64_reg_rw.
4846 operand iRegLdst() %{
4847   constraint(ALLOC_IN_RC(bits64_reg_rw));
4848   match(RegL);
4849   match(rscratch1RegL);
4850   match(rscratch2RegL);
4851   format %{ %}
4852   interface(REG_INTER);
4853 %}
4854 
4855 // Long Source Register
4856 // See definition of reg_class bits64_reg_ro.
4857 operand iRegLsrc() %{
4858   constraint(ALLOC_IN_RC(bits64_reg_ro));
4859   match(RegL);
4860   match(iRegLdst);
4861   match(rscratch1RegL);
4862   match(rscratch2RegL);
4863   format %{ %}
4864   interface(REG_INTER);
4865 %}
4866 
4867 // Special operand for ConvL2I.
4868 operand iRegL2Isrc(iRegLsrc reg) %{
4869   constraint(ALLOC_IN_RC(bits64_reg_ro));
4870   match(ConvL2I reg);
4871   format %{ "ConvL2I($reg)" %}
4872   interface(REG_INTER)
4873 %}
4874 
4875 operand rscratch1RegL() %{
4876   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4877   match(RegL);
4878   format %{ %}
4879   interface(REG_INTER);
4880 %}
4881 
4882 operand rscratch2RegL() %{
4883   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4884   match(RegL);
4885   format %{ %}
4886   interface(REG_INTER);
4887 %}
4888 
4889 // Condition Code Flag Registers
4890 operand flagsReg() %{
4891   constraint(ALLOC_IN_RC(int_flags));
4892   match(RegFlags);
4893   format %{ %}
4894   interface(REG_INTER);
4895 %}
4896 
4897 operand flagsRegSrc() %{
4898   constraint(ALLOC_IN_RC(int_flags_ro));
4899   match(RegFlags);
4900   match(flagsReg);
4901   match(flagsRegCR0);
4902   format %{ %}
4903   interface(REG_INTER);
4904 %}
4905 
4906 // Condition Code Flag Register CR0
4907 operand flagsRegCR0() %{
4908   constraint(ALLOC_IN_RC(int_flags_CR0));
4909   match(RegFlags);
4910   format %{ "CR0" %}
4911   interface(REG_INTER);
4912 %}
4913 
4914 operand flagsRegCR1() %{
4915   constraint(ALLOC_IN_RC(int_flags_CR1));
4916   match(RegFlags);
4917   format %{ "CR1" %}
4918   interface(REG_INTER);
4919 %}
4920 
4921 operand flagsRegCR6() %{
4922   constraint(ALLOC_IN_RC(int_flags_CR6));
4923   match(RegFlags);
4924   format %{ "CR6" %}
4925   interface(REG_INTER);
4926 %}
4927 
4928 operand regCTR() %{
4929   constraint(ALLOC_IN_RC(ctr_reg));
4930   // RegFlags should work. Introducing a RegSpecial type would cause a
4931   // lot of changes.
4932   match(RegFlags);
4933   format %{"SR_CTR" %}
4934   interface(REG_INTER);
4935 %}
4936 
4937 operand regD() %{
4938   constraint(ALLOC_IN_RC(dbl_reg));
4939   match(RegD);
4940   format %{ %}
4941   interface(REG_INTER);
4942 %}
4943 
4944 operand regF() %{
4945   constraint(ALLOC_IN_RC(flt_reg));
4946   match(RegF);
4947   format %{ %}
4948   interface(REG_INTER);
4949 %}
4950 
4951 // Special Registers
4952 
4953 // Method Register
4954 operand inline_cache_regP(iRegPdst reg) %{
4955   constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4956   match(reg);
4957   format %{ %}
4958   interface(REG_INTER);
4959 %}
4960 
4961 operand compiler_method_oop_regP(iRegPdst reg) %{
4962   constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4963   match(reg);
4964   format %{ %}
4965   interface(REG_INTER);
4966 %}
4967 
4968 operand interpreter_method_oop_regP(iRegPdst reg) %{
4969   constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4970   match(reg);
4971   format %{ %}
4972   interface(REG_INTER);
4973 %}
4974 
4975 // Operands to remove register moves in unscaled mode.
4976 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4977 operand iRegP2N(iRegPsrc reg) %{
4978   predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4979   constraint(ALLOC_IN_RC(bits64_reg_ro));
4980   match(EncodeP reg);
4981   format %{ "$reg" %}
4982   interface(REG_INTER)
4983 %}
4984 
4985 operand iRegN2P(iRegNsrc reg) %{
4986   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4987   constraint(ALLOC_IN_RC(bits32_reg_ro));
4988   match(DecodeN reg);
4989   format %{ "$reg" %}
4990   interface(REG_INTER)
4991 %}
4992 
4993 operand iRegN2P_klass(iRegNsrc reg) %{
4994   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4995   constraint(ALLOC_IN_RC(bits32_reg_ro));
4996   match(DecodeNKlass reg);
4997   format %{ "$reg" %}
4998   interface(REG_INTER)
4999 %}
5000 
5001 //----------Complex Operands---------------------------------------------------
5002 // Indirect Memory Reference
5003 operand indirect(iRegPsrc reg) %{
5004   constraint(ALLOC_IN_RC(bits64_reg_ro));
5005   match(reg);
5006   op_cost(100);
5007   format %{ "[$reg]" %}
5008   interface(MEMORY_INTER) %{
5009     base($reg);
5010     index(0x0);
5011     scale(0x0);
5012     disp(0x0);
5013   %}
5014 %}
5015 
5016 // Indirect with Offset
5017 operand indOffset16(iRegPsrc reg, immL16 offset) %{
5018   constraint(ALLOC_IN_RC(bits64_reg_ro));
5019   match(AddP reg offset);
5020   op_cost(100);
5021   format %{ "[$reg + $offset]" %}
5022   interface(MEMORY_INTER) %{
5023     base($reg);
5024     index(0x0);
5025     scale(0x0);
5026     disp($offset);
5027   %}
5028 %}
5029 
5030 // Indirect with 4-aligned Offset
5031 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
5032   constraint(ALLOC_IN_RC(bits64_reg_ro));
5033   match(AddP reg offset);
5034   op_cost(100);
5035   format %{ "[$reg + $offset]" %}
5036   interface(MEMORY_INTER) %{
5037     base($reg);
5038     index(0x0);
5039     scale(0x0);
5040     disp($offset);
5041   %}
5042 %}
5043 
5044 //----------Complex Operands for Compressed OOPs-------------------------------
5045 // Compressed OOPs with narrow_oop_shift == 0.
5046 
5047 // Indirect Memory Reference, compressed OOP
5048 operand indirectNarrow(iRegNsrc reg) %{
5049   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
5050   constraint(ALLOC_IN_RC(bits64_reg_ro));
5051   match(DecodeN reg);
5052   op_cost(100);
5053   format %{ "[$reg]" %}
5054   interface(MEMORY_INTER) %{
5055     base($reg);
5056     index(0x0);
5057     scale(0x0);
5058     disp(0x0);
5059   %}
5060 %}
5061 
5062 operand indirectNarrow_klass(iRegNsrc reg) %{
5063   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
5064   constraint(ALLOC_IN_RC(bits64_reg_ro));
5065   match(DecodeNKlass reg);
5066   op_cost(100);
5067   format %{ "[$reg]" %}
5068   interface(MEMORY_INTER) %{
5069     base($reg);
5070     index(0x0);
5071     scale(0x0);
5072     disp(0x0);
5073   %}
5074 %}
5075 
5076 // Indirect with Offset, compressed OOP
5077 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
5078   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
5079   constraint(ALLOC_IN_RC(bits64_reg_ro));
5080   match(AddP (DecodeN reg) offset);
5081   op_cost(100);
5082   format %{ "[$reg + $offset]" %}
5083   interface(MEMORY_INTER) %{
5084     base($reg);
5085     index(0x0);
5086     scale(0x0);
5087     disp($offset);
5088   %}
5089 %}
5090 
5091 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
5092   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
5093   constraint(ALLOC_IN_RC(bits64_reg_ro));
5094   match(AddP (DecodeNKlass reg) offset);
5095   op_cost(100);
5096   format %{ "[$reg + $offset]" %}
5097   interface(MEMORY_INTER) %{
5098     base($reg);
5099     index(0x0);
5100     scale(0x0);
5101     disp($offset);
5102   %}
5103 %}
5104 
5105 // Indirect with 4-aligned Offset, compressed OOP
5106 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
5107   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
5108   constraint(ALLOC_IN_RC(bits64_reg_ro));
5109   match(AddP (DecodeN reg) offset);
5110   op_cost(100);
5111   format %{ "[$reg + $offset]" %}
5112   interface(MEMORY_INTER) %{
5113     base($reg);
5114     index(0x0);
5115     scale(0x0);
5116     disp($offset);
5117   %}
5118 %}
5119 
5120 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
5121   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
5122   constraint(ALLOC_IN_RC(bits64_reg_ro));
5123   match(AddP (DecodeNKlass reg) offset);
5124   op_cost(100);
5125   format %{ "[$reg + $offset]" %}
5126   interface(MEMORY_INTER) %{
5127     base($reg);
5128     index(0x0);
5129     scale(0x0);
5130     disp($offset);
5131   %}
5132 %}
5133 
5134 //----------Special Memory Operands--------------------------------------------
5135 // Stack Slot Operand
5136 //
5137 // This operand is used for loading and storing temporary values on
5138 // the stack where a match requires a value to flow through memory.
5139 operand stackSlotI(sRegI reg) %{
5140   constraint(ALLOC_IN_RC(stack_slots));
5141   op_cost(100);
5142   //match(RegI);
5143   format %{ "[sp+$reg]" %}
5144   interface(MEMORY_INTER) %{
5145     base(0x1);   // R1_SP
5146     index(0x0);
5147     scale(0x0);
5148     disp($reg);  // Stack Offset
5149   %}
5150 %}
5151 
5152 operand stackSlotL(sRegL reg) %{
5153   constraint(ALLOC_IN_RC(stack_slots));
5154   op_cost(100);
5155   //match(RegL);
5156   format %{ "[sp+$reg]" %}
5157   interface(MEMORY_INTER) %{
5158     base(0x1);   // R1_SP
5159     index(0x0);
5160     scale(0x0);
5161     disp($reg);  // Stack Offset
5162   %}
5163 %}
5164 
5165 operand stackSlotP(sRegP reg) %{
5166   constraint(ALLOC_IN_RC(stack_slots));
5167   op_cost(100);
5168   //match(RegP);
5169   format %{ "[sp+$reg]" %}
5170   interface(MEMORY_INTER) %{
5171     base(0x1);   // R1_SP
5172     index(0x0);
5173     scale(0x0);
5174     disp($reg);  // Stack Offset
5175   %}
5176 %}
5177 
5178 operand stackSlotF(sRegF reg) %{
5179   constraint(ALLOC_IN_RC(stack_slots));
5180   op_cost(100);
5181   //match(RegF);
5182   format %{ "[sp+$reg]" %}
5183   interface(MEMORY_INTER) %{
5184     base(0x1);   // R1_SP
5185     index(0x0);
5186     scale(0x0);
5187     disp($reg);  // Stack Offset
5188   %}
5189 %}
5190 
5191 operand stackSlotD(sRegD reg) %{
5192   constraint(ALLOC_IN_RC(stack_slots));
5193   op_cost(100);
5194   //match(RegD);
5195   format %{ "[sp+$reg]" %}
5196   interface(MEMORY_INTER) %{
5197     base(0x1);   // R1_SP
5198     index(0x0);
5199     scale(0x0);
5200     disp($reg);  // Stack Offset
5201   %}
5202 %}
5203 
5204 // Operands for expressing Control Flow
5205 // NOTE: Label is a predefined operand which should not be redefined in
5206 //       the AD file. It is generically handled within the ADLC.
5207 
5208 //----------Conditional Branch Operands----------------------------------------
5209 // Comparison Op
5210 //
5211 // This is the operation of the comparison, and is limited to the
5212 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
5213 // (!=).
5214 //
5215 // Other attributes of the comparison, such as unsignedness, are specified
5216 // by the comparison instruction that sets a condition code flags register.
5217 // That result is represented by a flags operand whose subtype is appropriate
5218 // to the unsignedness (etc.) of the comparison.
5219 //
5220 // Later, the instruction which matches both the Comparison Op (a Bool) and
5221 // the flags (produced by the Cmp) specifies the coding of the comparison op
5222 // by matching a specific subtype of Bool operand below.
5223 
5224 // When used for floating point comparisons: unordered same as less.
5225 operand cmpOp() %{
5226   match(Bool);
5227   format %{ "" %}
5228   interface(COND_INTER) %{
5229                            // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
5230                            //           BO          &  BI
5231     equal(0xA);            // 10 10:   bcondCRbiIs1 & Condition::equal
5232     not_equal(0x2);        // 00 10:   bcondCRbiIs0 & Condition::equal
5233     less(0x8);             // 10 00:   bcondCRbiIs1 & Condition::less
5234     greater_equal(0x0);    // 00 00:   bcondCRbiIs0 & Condition::less
5235     less_equal(0x1);       // 00 01:   bcondCRbiIs0 & Condition::greater
5236     greater(0x9);          // 10 01:   bcondCRbiIs1 & Condition::greater
5237     overflow(0xB);         // 10 11:   bcondCRbiIs1 & Condition::summary_overflow
5238     no_overflow(0x3);      // 00 11:   bcondCRbiIs0 & Condition::summary_overflow
5239   %}
5240 %}
5241 
5242 //----------OPERAND CLASSES----------------------------------------------------
5243 // Operand Classes are groups of operands that are used to simplify
5244 // instruction definitions by not requiring the AD writer to specify
5245 // seperate instructions for every form of operand when the
5246 // instruction accepts multiple operand types with the same basic
5247 // encoding and format. The classic case of this is memory operands.
5248 // Indirect is not included since its use is limited to Compare & Swap.
5249 
5250 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
5251 // Memory operand where offsets are 4-aligned. Required for ld, std.
5252 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
5253 opclass indirectMemory(indirect, indirectNarrow);
5254 
5255 // Special opclass for I and ConvL2I.
5256 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5257 
5258 // Operand classes to match encode and decode. iRegN_P2N is only used
5259 // for storeN. I have never seen an encode node elsewhere.
5260 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5261 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
5262 
5263 //----------PIPELINE-----------------------------------------------------------
5264 
5265 pipeline %{
5266 
5267 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5268 // J. Res. & Dev., No. 1, Jan. 2002.
5269 
5270 //----------ATTRIBUTES---------------------------------------------------------
5271 attributes %{
5272 
5273   // Power4 instructions are of fixed length.
5274   fixed_size_instructions;
5275 
5276   // TODO: if `bundle' means number of instructions fetched
5277   // per cycle, this is 8. If `bundle' means Power4 `group', that is
5278   // max instructions issued per cycle, this is 5.
5279   max_instructions_per_bundle = 8;
5280 
5281   // A Power4 instruction is 4 bytes long.
5282   instruction_unit_size = 4;
5283 
5284   // The Power4 processor fetches 64 bytes...
5285   instruction_fetch_unit_size = 64;
5286 
5287   // ...in one line
5288   instruction_fetch_units = 1
5289 
5290   // Unused, list one so that array generated by adlc is not empty.
5291   // Aix compiler chokes if _nop_count = 0.
5292   nops(fxNop);
5293 %}
5294 
5295 //----------RESOURCES----------------------------------------------------------
5296 // Resources are the functional units available to the machine
5297 resources(
5298    PPC_BR,         // branch unit
5299    PPC_CR,         // condition unit
5300    PPC_FX1,        // integer arithmetic unit 1
5301    PPC_FX2,        // integer arithmetic unit 2
5302    PPC_LDST1,      // load/store unit 1
5303    PPC_LDST2,      // load/store unit 2
5304    PPC_FP1,        // float arithmetic unit 1
5305    PPC_FP2,        // float arithmetic unit 2
5306    PPC_LDST = PPC_LDST1 | PPC_LDST2,
5307    PPC_FX = PPC_FX1 | PPC_FX2,
5308    PPC_FP = PPC_FP1 | PPC_FP2
5309  );
5310 
5311 //----------PIPELINE DESCRIPTION-----------------------------------------------
5312 // Pipeline Description specifies the stages in the machine's pipeline
5313 pipe_desc(
5314    // Power4 longest pipeline path
5315    PPC_IF,   // instruction fetch
5316    PPC_IC,
5317    //PPC_BP, // branch prediction
5318    PPC_D0,   // decode
5319    PPC_D1,   // decode
5320    PPC_D2,   // decode
5321    PPC_D3,   // decode
5322    PPC_Xfer1,
5323    PPC_GD,   // group definition
5324    PPC_MP,   // map
5325    PPC_ISS,  // issue
5326    PPC_RF,   // resource fetch
5327    PPC_EX1,  // execute (all units)
5328    PPC_EX2,  // execute (FP, LDST)
5329    PPC_EX3,  // execute (FP, LDST)
5330    PPC_EX4,  // execute (FP)
5331    PPC_EX5,  // execute (FP)
5332    PPC_EX6,  // execute (FP)
5333    PPC_WB,   // write back
5334    PPC_Xfer2,
5335    PPC_CP
5336  );
5337 
5338 //----------PIPELINE CLASSES---------------------------------------------------
5339 // Pipeline Classes describe the stages in which input and output are
5340 // referenced by the hardware pipeline.
5341 
5342 // Simple pipeline classes.
5343 
5344 // Default pipeline class.
5345 pipe_class pipe_class_default() %{
5346   single_instruction;
5347   fixed_latency(2);
5348 %}
5349 
5350 // Pipeline class for empty instructions.
5351 pipe_class pipe_class_empty() %{
5352   single_instruction;
5353   fixed_latency(0);
5354 %}
5355 
5356 // Pipeline class for compares.
5357 pipe_class pipe_class_compare() %{
5358   single_instruction;
5359   fixed_latency(16);
5360 %}
5361 
5362 // Pipeline class for traps.
5363 pipe_class pipe_class_trap() %{
5364   single_instruction;
5365   fixed_latency(100);
5366 %}
5367 
5368 // Pipeline class for memory operations.
5369 pipe_class pipe_class_memory() %{
5370   single_instruction;
5371   fixed_latency(16);
5372 %}
5373 
5374 // Pipeline class for call.
5375 pipe_class pipe_class_call() %{
5376   single_instruction;
5377   fixed_latency(100);
5378 %}
5379 
5380 // Define the class for the Nop node.
5381 define %{
5382    MachNop = pipe_class_default;
5383 %}
5384 
5385 %}
5386 
5387 //----------INSTRUCTIONS-------------------------------------------------------
5388 
5389 // Naming of instructions:
5390 //   opA_operB / opA_operB_operC:
5391 //     Operation 'op' with one or two source operands 'oper'. Result
5392 //     type is A, source operand types are B and C.
5393 //     Iff A == B == C, B and C are left out.
5394 //
5395 // The instructions are ordered according to the following scheme:
5396 //  - loads
5397 //  - load constants
5398 //  - prefetch
5399 //  - store
5400 //  - encode/decode
5401 //  - membar
5402 //  - conditional moves
5403 //  - compare & swap
5404 //  - arithmetic and logic operations
5405 //    * int: Add, Sub, Mul, Div, Mod
5406 //    * int: lShift, arShift, urShift, rot
5407 //    * float: Add, Sub, Mul, Div
5408 //    * and, or, xor ...
5409 //  - register moves: float <-> int, reg <-> stack, repl
5410 //  - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5411 //  - conv (low level type cast requiring bit changes (sign extend etc)
5412 //  - compares, range & zero checks.
5413 //  - branches
5414 //  - complex operations, intrinsics, min, max, replicate
5415 //  - lock
5416 //  - Calls
5417 //
5418 // If there are similar instructions with different types they are sorted:
5419 // int before float
5420 // small before big
5421 // signed before unsigned
5422 // e.g., loadS before loadUS before loadI before loadF.
5423 
5424 
5425 //----------Load/Store Instructions--------------------------------------------
5426 
5427 //----------Load Instructions--------------------------------------------------
5428 
5429 // Converts byte to int.
5430 // As convB2I_reg, but without match rule.  The match rule of convB2I_reg
5431 // reuses the 'amount' operand, but adlc expects that operand specification
5432 // and operands in match rule are equivalent.
5433 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5434   effect(DEF dst, USE src);
5435   format %{ "EXTSB   $dst, $src \t// byte->int" %}
5436   size(4);
5437   ins_encode %{
5438     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5439     __ extsb($dst$$Register, $src$$Register);
5440   %}
5441   ins_pipe(pipe_class_default);
5442 %}
5443 
5444 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5445   // match-rule, false predicate
5446   match(Set dst (LoadB mem));
5447   predicate(false);
5448 
5449   format %{ "LBZ     $dst, $mem" %}
5450   size(4);
5451   ins_encode( enc_lbz(dst, mem) );
5452   ins_pipe(pipe_class_memory);
5453 %}
5454 
5455 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5456   // match-rule, false predicate
5457   match(Set dst (LoadB mem));
5458   predicate(false);
5459 
5460   format %{ "LBZ     $dst, $mem\n\t"
5461             "TWI     $dst\n\t"
5462             "ISYNC" %}
5463   size(12);
5464   ins_encode( enc_lbz_ac(dst, mem) );
5465   ins_pipe(pipe_class_memory);
5466 %}
5467 
5468 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5469 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5470   match(Set dst (LoadB mem));
5471   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5472   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5473   expand %{
5474     iRegIdst tmp;
5475     loadUB_indirect(tmp, mem);
5476     convB2I_reg_2(dst, tmp);
5477   %}
5478 %}
5479 
5480 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5481   match(Set dst (LoadB mem));
5482   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5483   expand %{
5484     iRegIdst tmp;
5485     loadUB_indirect_ac(tmp, mem);
5486     convB2I_reg_2(dst, tmp);
5487   %}
5488 %}
5489 
5490 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5491   // match-rule, false predicate
5492   match(Set dst (LoadB mem));
5493   predicate(false);
5494 
5495   format %{ "LBZ     $dst, $mem" %}
5496   size(4);
5497   ins_encode( enc_lbz(dst, mem) );
5498   ins_pipe(pipe_class_memory);
5499 %}
5500 
5501 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5502   // match-rule, false predicate
5503   match(Set dst (LoadB mem));
5504   predicate(false);
5505 
5506   format %{ "LBZ     $dst, $mem\n\t"
5507             "TWI     $dst\n\t"
5508             "ISYNC" %}
5509   size(12);
5510   ins_encode( enc_lbz_ac(dst, mem) );
5511   ins_pipe(pipe_class_memory);
5512 %}
5513 
5514 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5515 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5516   match(Set dst (LoadB mem));
5517   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5518   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5519 
5520   expand %{
5521     iRegIdst tmp;
5522     loadUB_indOffset16(tmp, mem);
5523     convB2I_reg_2(dst, tmp);
5524   %}
5525 %}
5526 
5527 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5528   match(Set dst (LoadB mem));
5529   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5530 
5531   expand %{
5532     iRegIdst tmp;
5533     loadUB_indOffset16_ac(tmp, mem);
5534     convB2I_reg_2(dst, tmp);
5535   %}
5536 %}
5537 
5538 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5539 instruct loadUB(iRegIdst dst, memory mem) %{
5540   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5541   match(Set dst (LoadUB mem));
5542   ins_cost(MEMORY_REF_COST);
5543 
5544   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int" %}
5545   size(4);
5546   ins_encode( enc_lbz(dst, mem) );
5547   ins_pipe(pipe_class_memory);
5548 %}
5549 
5550 // Load  Unsigned Byte (8bit UNsigned) acquire.
5551 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5552   match(Set dst (LoadUB mem));
5553   ins_cost(3*MEMORY_REF_COST);
5554 
5555   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5556             "TWI     $dst\n\t"
5557             "ISYNC" %}
5558   size(12);
5559   ins_encode( enc_lbz_ac(dst, mem) );
5560   ins_pipe(pipe_class_memory);
5561 %}
5562 
5563 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5564 instruct loadUB2L(iRegLdst dst, memory mem) %{
5565   match(Set dst (ConvI2L (LoadUB mem)));
5566   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5567   ins_cost(MEMORY_REF_COST);
5568 
5569   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long" %}
5570   size(4);
5571   ins_encode( enc_lbz(dst, mem) );
5572   ins_pipe(pipe_class_memory);
5573 %}
5574 
5575 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5576   match(Set dst (ConvI2L (LoadUB mem)));
5577   ins_cost(3*MEMORY_REF_COST);
5578 
5579   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5580             "TWI     $dst\n\t"
5581             "ISYNC" %}
5582   size(12);
5583   ins_encode( enc_lbz_ac(dst, mem) );
5584   ins_pipe(pipe_class_memory);
5585 %}
5586 
5587 // Load Short (16bit signed)
5588 instruct loadS(iRegIdst dst, memory mem) %{
5589   match(Set dst (LoadS mem));
5590   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5591   ins_cost(MEMORY_REF_COST);
5592 
5593   format %{ "LHA     $dst, $mem" %}
5594   size(4);
5595   ins_encode %{
5596     // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5597     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5598     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5599   %}
5600   ins_pipe(pipe_class_memory);
5601 %}
5602 
5603 // Load Short (16bit signed) acquire.
5604 instruct loadS_ac(iRegIdst dst, memory mem) %{
5605   match(Set dst (LoadS mem));
5606   ins_cost(3*MEMORY_REF_COST);
5607 
5608   format %{ "LHA     $dst, $mem\t acquire\n\t"
5609             "TWI     $dst\n\t"
5610             "ISYNC" %}
5611   size(12);
5612   ins_encode %{
5613     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5614     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5615     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5616     __ twi_0($dst$$Register);
5617     __ isync();
5618   %}
5619   ins_pipe(pipe_class_memory);
5620 %}
5621 
5622 // Load Char (16bit unsigned)
5623 instruct loadUS(iRegIdst dst, memory mem) %{
5624   match(Set dst (LoadUS mem));
5625   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5626   ins_cost(MEMORY_REF_COST);
5627 
5628   format %{ "LHZ     $dst, $mem" %}
5629   size(4);
5630   ins_encode( enc_lhz(dst, mem) );
5631   ins_pipe(pipe_class_memory);
5632 %}
5633 
5634 // Load Char (16bit unsigned) acquire.
5635 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5636   match(Set dst (LoadUS mem));
5637   ins_cost(3*MEMORY_REF_COST);
5638 
5639   format %{ "LHZ     $dst, $mem \t// acquire\n\t"
5640             "TWI     $dst\n\t"
5641             "ISYNC" %}
5642   size(12);
5643   ins_encode( enc_lhz_ac(dst, mem) );
5644   ins_pipe(pipe_class_memory);
5645 %}
5646 
5647 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5648 instruct loadUS2L(iRegLdst dst, memory mem) %{
5649   match(Set dst (ConvI2L (LoadUS mem)));
5650   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5651   ins_cost(MEMORY_REF_COST);
5652 
5653   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long" %}
5654   size(4);
5655   ins_encode( enc_lhz(dst, mem) );
5656   ins_pipe(pipe_class_memory);
5657 %}
5658 
5659 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5660 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5661   match(Set dst (ConvI2L (LoadUS mem)));
5662   ins_cost(3*MEMORY_REF_COST);
5663 
5664   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5665             "TWI     $dst\n\t"
5666             "ISYNC" %}
5667   size(12);
5668   ins_encode( enc_lhz_ac(dst, mem) );
5669   ins_pipe(pipe_class_memory);
5670 %}
5671 
5672 // Load Integer.
5673 instruct loadI(iRegIdst dst, memory mem) %{
5674   match(Set dst (LoadI mem));
5675   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5676   ins_cost(MEMORY_REF_COST);
5677 
5678   format %{ "LWZ     $dst, $mem" %}
5679   size(4);
5680   ins_encode( enc_lwz(dst, mem) );
5681   ins_pipe(pipe_class_memory);
5682 %}
5683 
5684 // Load Integer acquire.
5685 instruct loadI_ac(iRegIdst dst, memory mem) %{
5686   match(Set dst (LoadI mem));
5687   ins_cost(3*MEMORY_REF_COST);
5688 
5689   format %{ "LWZ     $dst, $mem \t// load acquire\n\t"
5690             "TWI     $dst\n\t"
5691             "ISYNC" %}
5692   size(12);
5693   ins_encode( enc_lwz_ac(dst, mem) );
5694   ins_pipe(pipe_class_memory);
5695 %}
5696 
5697 // Match loading integer and casting it to unsigned int in
5698 // long register.
5699 // LoadI + ConvI2L + AndL 0xffffffff.
5700 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5701   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5702   predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5703   ins_cost(MEMORY_REF_COST);
5704 
5705   format %{ "LWZ     $dst, $mem \t// zero-extend to long" %}
5706   size(4);
5707   ins_encode( enc_lwz(dst, mem) );
5708   ins_pipe(pipe_class_memory);
5709 %}
5710 
5711 // Match loading integer and casting it to long.
5712 instruct loadI2L(iRegLdst dst, memoryAlg4 mem) %{
5713   match(Set dst (ConvI2L (LoadI mem)));
5714   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5715   ins_cost(MEMORY_REF_COST);
5716 
5717   format %{ "LWA     $dst, $mem \t// loadI2L" %}
5718   size(4);
5719   ins_encode %{
5720     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5721     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5722     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5723   %}
5724   ins_pipe(pipe_class_memory);
5725 %}
5726 
5727 // Match loading integer and casting it to long - acquire.
5728 instruct loadI2L_ac(iRegLdst dst, memoryAlg4 mem) %{
5729   match(Set dst (ConvI2L (LoadI mem)));
5730   ins_cost(3*MEMORY_REF_COST);
5731 
5732   format %{ "LWA     $dst, $mem \t// loadI2L acquire"
5733             "TWI     $dst\n\t"
5734             "ISYNC" %}
5735   size(12);
5736   ins_encode %{
5737     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5738     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5739     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5740     __ twi_0($dst$$Register);
5741     __ isync();
5742   %}
5743   ins_pipe(pipe_class_memory);
5744 %}
5745 
5746 // Load Long - aligned
5747 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5748   match(Set dst (LoadL mem));
5749   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5750   ins_cost(MEMORY_REF_COST);
5751 
5752   format %{ "LD      $dst, $mem \t// long" %}
5753   size(4);
5754   ins_encode( enc_ld(dst, mem) );
5755   ins_pipe(pipe_class_memory);
5756 %}
5757 
5758 // Load Long - aligned acquire.
5759 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5760   match(Set dst (LoadL mem));
5761   ins_cost(3*MEMORY_REF_COST);
5762 
5763   format %{ "LD      $dst, $mem \t// long acquire\n\t"
5764             "TWI     $dst\n\t"
5765             "ISYNC" %}
5766   size(12);
5767   ins_encode( enc_ld_ac(dst, mem) );
5768   ins_pipe(pipe_class_memory);
5769 %}
5770 
5771 // Load Long - UNaligned
5772 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5773   match(Set dst (LoadL_unaligned mem));
5774   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5775   ins_cost(MEMORY_REF_COST);
5776 
5777   format %{ "LD      $dst, $mem \t// unaligned long" %}
5778   size(4);
5779   ins_encode( enc_ld(dst, mem) );
5780   ins_pipe(pipe_class_memory);
5781 %}
5782 
5783 // Load nodes for superwords
5784 
5785 // Load Aligned Packed Byte
5786 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5787   predicate(n->as_LoadVector()->memory_size() == 8);
5788   match(Set dst (LoadVector mem));
5789   ins_cost(MEMORY_REF_COST);
5790 
5791   format %{ "LD      $dst, $mem \t// load 8-byte Vector" %}
5792   size(4);
5793   ins_encode( enc_ld(dst, mem) );
5794   ins_pipe(pipe_class_memory);
5795 %}
5796 
5797 // Load Aligned Packed Byte
5798 instruct loadV16(vecX dst, indirect mem) %{
5799   predicate(n->as_LoadVector()->memory_size() == 16);
5800   match(Set dst (LoadVector mem));
5801   ins_cost(MEMORY_REF_COST);
5802 
5803   format %{ "LXVD2X      $dst, $mem \t// load 16-byte Vector" %}
5804   size(4);
5805   ins_encode %{
5806     __ lxvd2x($dst$$VectorSRegister, $mem$$Register);
5807   %}
5808   ins_pipe(pipe_class_default);
5809 %}
5810 
5811 // Load Range, range = array length (=jint)
5812 instruct loadRange(iRegIdst dst, memory mem) %{
5813   match(Set dst (LoadRange mem));
5814   ins_cost(MEMORY_REF_COST);
5815 
5816   format %{ "LWZ     $dst, $mem \t// range" %}
5817   size(4);
5818   ins_encode( enc_lwz(dst, mem) );
5819   ins_pipe(pipe_class_memory);
5820 %}
5821 
5822 // Load Compressed Pointer
5823 instruct loadN(iRegNdst dst, memory mem) %{
5824   match(Set dst (LoadN mem));
5825   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5826   ins_cost(MEMORY_REF_COST);
5827 
5828   format %{ "LWZ     $dst, $mem \t// load compressed ptr" %}
5829   size(4);
5830   ins_encode( enc_lwz(dst, mem) );
5831   ins_pipe(pipe_class_memory);
5832 %}
5833 
5834 // Load Compressed Pointer acquire.
5835 instruct loadN_ac(iRegNdst dst, memory mem) %{
5836   match(Set dst (LoadN mem));
5837   ins_cost(3*MEMORY_REF_COST);
5838 
5839   format %{ "LWZ     $dst, $mem \t// load acquire compressed ptr\n\t"
5840             "TWI     $dst\n\t"
5841             "ISYNC" %}
5842   size(12);
5843   ins_encode( enc_lwz_ac(dst, mem) );
5844   ins_pipe(pipe_class_memory);
5845 %}
5846 
5847 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5848 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5849   match(Set dst (DecodeN (LoadN mem)));
5850   predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5851   ins_cost(MEMORY_REF_COST);
5852 
5853   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5854   size(4);
5855   ins_encode( enc_lwz(dst, mem) );
5856   ins_pipe(pipe_class_memory);
5857 %}
5858 
5859 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5860   match(Set dst (DecodeNKlass (LoadNKlass mem)));
5861   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5862             _kids[0]->_leaf->as_Load()->is_unordered());
5863   ins_cost(MEMORY_REF_COST);
5864 
5865   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5866   size(4);
5867   ins_encode( enc_lwz(dst, mem) );
5868   ins_pipe(pipe_class_memory);
5869 %}
5870 
5871 // Load Pointer
5872 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5873   match(Set dst (LoadP mem));
5874   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5875   ins_cost(MEMORY_REF_COST);
5876 
5877   format %{ "LD      $dst, $mem \t// ptr" %}
5878   size(4);
5879   ins_encode( enc_ld(dst, mem) );
5880   ins_pipe(pipe_class_memory);
5881 %}
5882 
5883 // Load Pointer acquire.
5884 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5885   match(Set dst (LoadP mem));
5886   ins_cost(3*MEMORY_REF_COST);
5887 
5888   format %{ "LD      $dst, $mem \t// ptr acquire\n\t"
5889             "TWI     $dst\n\t"
5890             "ISYNC" %}
5891   size(12);
5892   ins_encode( enc_ld_ac(dst, mem) );
5893   ins_pipe(pipe_class_memory);
5894 %}
5895 
5896 // LoadP + CastP2L
5897 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5898   match(Set dst (CastP2X (LoadP mem)));
5899   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5900   ins_cost(MEMORY_REF_COST);
5901 
5902   format %{ "LD      $dst, $mem \t// ptr + p2x" %}
5903   size(4);
5904   ins_encode( enc_ld(dst, mem) );
5905   ins_pipe(pipe_class_memory);
5906 %}
5907 
5908 // Load compressed klass pointer.
5909 instruct loadNKlass(iRegNdst dst, memory mem) %{
5910   match(Set dst (LoadNKlass mem));
5911   ins_cost(MEMORY_REF_COST);
5912 
5913   format %{ "LWZ     $dst, $mem \t// compressed klass ptr" %}
5914   size(4);
5915   ins_encode( enc_lwz(dst, mem) );
5916   ins_pipe(pipe_class_memory);
5917 %}
5918 
5919 // Load Klass Pointer
5920 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5921   match(Set dst (LoadKlass mem));
5922   ins_cost(MEMORY_REF_COST);
5923 
5924   format %{ "LD      $dst, $mem \t// klass ptr" %}
5925   size(4);
5926   ins_encode( enc_ld(dst, mem) );
5927   ins_pipe(pipe_class_memory);
5928 %}
5929 
5930 // Load Float
5931 instruct loadF(regF dst, memory mem) %{
5932   match(Set dst (LoadF mem));
5933   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5934   ins_cost(MEMORY_REF_COST);
5935 
5936   format %{ "LFS     $dst, $mem" %}
5937   size(4);
5938   ins_encode %{
5939     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5940     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5941     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5942   %}
5943   ins_pipe(pipe_class_memory);
5944 %}
5945 
5946 // Load Float acquire.
5947 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5948   match(Set dst (LoadF mem));
5949   effect(TEMP cr0);
5950   ins_cost(3*MEMORY_REF_COST);
5951 
5952   format %{ "LFS     $dst, $mem \t// acquire\n\t"
5953             "FCMPU   cr0, $dst, $dst\n\t"
5954             "BNE     cr0, next\n"
5955             "next:\n\t"
5956             "ISYNC" %}
5957   size(16);
5958   ins_encode %{
5959     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5960     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5961     Label next;
5962     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5963     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5964     __ bne(CCR0, next);
5965     __ bind(next);
5966     __ isync();
5967   %}
5968   ins_pipe(pipe_class_memory);
5969 %}
5970 
5971 // Load Double - aligned
5972 instruct loadD(regD dst, memory mem) %{
5973   match(Set dst (LoadD mem));
5974   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5975   ins_cost(MEMORY_REF_COST);
5976 
5977   format %{ "LFD     $dst, $mem" %}
5978   size(4);
5979   ins_encode( enc_lfd(dst, mem) );
5980   ins_pipe(pipe_class_memory);
5981 %}
5982 
5983 // Load Double - aligned acquire.
5984 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5985   match(Set dst (LoadD mem));
5986   effect(TEMP cr0);
5987   ins_cost(3*MEMORY_REF_COST);
5988 
5989   format %{ "LFD     $dst, $mem \t// acquire\n\t"
5990             "FCMPU   cr0, $dst, $dst\n\t"
5991             "BNE     cr0, next\n"
5992             "next:\n\t"
5993             "ISYNC" %}
5994   size(16);
5995   ins_encode %{
5996     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5997     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5998     Label next;
5999     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
6000     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
6001     __ bne(CCR0, next);
6002     __ bind(next);
6003     __ isync();
6004   %}
6005   ins_pipe(pipe_class_memory);
6006 %}
6007 
6008 // Load Double - UNaligned
6009 instruct loadD_unaligned(regD dst, memory mem) %{
6010   match(Set dst (LoadD_unaligned mem));
6011   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
6012   ins_cost(MEMORY_REF_COST);
6013 
6014   format %{ "LFD     $dst, $mem" %}
6015   size(4);
6016   ins_encode( enc_lfd(dst, mem) );
6017   ins_pipe(pipe_class_memory);
6018 %}
6019 
6020 //----------Constants--------------------------------------------------------
6021 
6022 // Load MachConstantTableBase: add hi offset to global toc.
6023 // TODO: Handle hidden register r29 in bundler!
6024 instruct loadToc_hi(iRegLdst dst) %{
6025   effect(DEF dst);
6026   ins_cost(DEFAULT_COST);
6027 
6028   format %{ "ADDIS   $dst, R29, DISP.hi \t// load TOC hi" %}
6029   size(4);
6030   ins_encode %{
6031     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6032     __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
6033   %}
6034   ins_pipe(pipe_class_default);
6035 %}
6036 
6037 // Load MachConstantTableBase: add lo offset to global toc.
6038 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
6039   effect(DEF dst, USE src);
6040   ins_cost(DEFAULT_COST);
6041 
6042   format %{ "ADDI    $dst, $src, DISP.lo \t// load TOC lo" %}
6043   size(4);
6044   ins_encode %{
6045     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6046     __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
6047   %}
6048   ins_pipe(pipe_class_default);
6049 %}
6050 
6051 // Load 16-bit integer constant 0xssss????
6052 instruct loadConI16(iRegIdst dst, immI16 src) %{
6053   match(Set dst src);
6054 
6055   format %{ "LI      $dst, $src" %}
6056   size(4);
6057   ins_encode %{
6058     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6059     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6060   %}
6061   ins_pipe(pipe_class_default);
6062 %}
6063 
6064 // Load integer constant 0x????0000
6065 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
6066   match(Set dst src);
6067   ins_cost(DEFAULT_COST);
6068 
6069   format %{ "LIS     $dst, $src.hi" %}
6070   size(4);
6071   ins_encode %{
6072     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6073     // Lis sign extends 16-bit src then shifts it 16 bit to the left.
6074     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
6075   %}
6076   ins_pipe(pipe_class_default);
6077 %}
6078 
6079 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
6080 // and sign extended), this adds the low 16 bits.
6081 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
6082   // no match-rule, false predicate
6083   effect(DEF dst, USE src1, USE src2);
6084   predicate(false);
6085 
6086   format %{ "ORI     $dst, $src1.hi, $src2.lo" %}
6087   size(4);
6088   ins_encode %{
6089     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6090     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
6091   %}
6092   ins_pipe(pipe_class_default);
6093 %}
6094 
6095 instruct loadConI_Ex(iRegIdst dst, immI src) %{
6096   match(Set dst src);
6097   ins_cost(DEFAULT_COST*2);
6098 
6099   expand %{
6100     // Would like to use $src$$constant.
6101     immI16 srcLo %{ _opnds[1]->constant() %}
6102     // srcHi can be 0000 if srcLo sign-extends to a negative number.
6103     immIhi16 srcHi %{ _opnds[1]->constant() %}
6104     iRegIdst tmpI;
6105     loadConIhi16(tmpI, srcHi);
6106     loadConI32_lo16(dst, tmpI, srcLo);
6107   %}
6108 %}
6109 
6110 // No constant pool entries required.
6111 instruct loadConL16(iRegLdst dst, immL16 src) %{
6112   match(Set dst src);
6113 
6114   format %{ "LI      $dst, $src \t// long" %}
6115   size(4);
6116   ins_encode %{
6117     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6118     __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
6119   %}
6120   ins_pipe(pipe_class_default);
6121 %}
6122 
6123 // Load long constant 0xssssssss????0000
6124 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
6125   match(Set dst src);
6126   ins_cost(DEFAULT_COST);
6127 
6128   format %{ "LIS     $dst, $src.hi \t// long" %}
6129   size(4);
6130   ins_encode %{
6131     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6132     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
6133   %}
6134   ins_pipe(pipe_class_default);
6135 %}
6136 
6137 // To load a 32 bit constant: merge lower 16 bits into already loaded
6138 // high 16 bits.
6139 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
6140   // no match-rule, false predicate
6141   effect(DEF dst, USE src1, USE src2);
6142   predicate(false);
6143 
6144   format %{ "ORI     $dst, $src1, $src2.lo" %}
6145   size(4);
6146   ins_encode %{
6147     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6148     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
6149   %}
6150   ins_pipe(pipe_class_default);
6151 %}
6152 
6153 // Load 32-bit long constant
6154 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
6155   match(Set dst src);
6156   ins_cost(DEFAULT_COST*2);
6157 
6158   expand %{
6159     // Would like to use $src$$constant.
6160     immL16     srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
6161     // srcHi can be 0000 if srcLo sign-extends to a negative number.
6162     immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
6163     iRegLdst tmpL;
6164     loadConL32hi16(tmpL, srcHi);
6165     loadConL32_lo16(dst, tmpL, srcLo);
6166   %}
6167 %}
6168 
6169 // Load long constant 0x????000000000000.
6170 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
6171   match(Set dst src);
6172   ins_cost(DEFAULT_COST);
6173 
6174   expand %{
6175     immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
6176     immI shift32 %{ 32 %}
6177     iRegLdst tmpL;
6178     loadConL32hi16(tmpL, srcHi);
6179     lshiftL_regL_immI(dst, tmpL, shift32);
6180   %}
6181 %}
6182 
6183 // Expand node for constant pool load: small offset.
6184 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
6185   effect(DEF dst, USE src, USE toc);
6186   ins_cost(MEMORY_REF_COST);
6187 
6188   ins_num_consts(1);
6189   // Needed so that CallDynamicJavaDirect can compute the address of this
6190   // instruction for relocation.
6191   ins_field_cbuf_insts_offset(int);
6192 
6193   format %{ "LD      $dst, offset, $toc \t// load long $src from TOC" %}
6194   size(4);
6195   ins_encode( enc_load_long_constL(dst, src, toc) );
6196   ins_pipe(pipe_class_memory);
6197 %}
6198 
6199 // Expand node for constant pool load: large offset.
6200 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
6201   effect(DEF dst, USE src, USE toc);
6202   predicate(false);
6203 
6204   ins_num_consts(1);
6205   ins_field_const_toc_offset(int);
6206   // Needed so that CallDynamicJavaDirect can compute the address of this
6207   // instruction for relocation.
6208   ins_field_cbuf_insts_offset(int);
6209 
6210   format %{ "ADDIS   $dst, $toc, offset \t// load long $src from TOC (hi)" %}
6211   size(4);
6212   ins_encode( enc_load_long_constL_hi(dst, toc, src) );
6213   ins_pipe(pipe_class_default);
6214 %}
6215 
6216 // Expand node for constant pool load: large offset.
6217 // No constant pool entries required.
6218 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
6219   effect(DEF dst, USE src, USE base);
6220   predicate(false);
6221 
6222   ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
6223 
6224   format %{ "LD      $dst, offset, $base \t// load long $src from TOC (lo)" %}
6225   size(4);
6226   ins_encode %{
6227     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6228     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6229     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6230   %}
6231   ins_pipe(pipe_class_memory);
6232 %}
6233 
6234 // Load long constant from constant table. Expand in case of
6235 // offset > 16 bit is needed.
6236 // Adlc adds toc node MachConstantTableBase.
6237 instruct loadConL_Ex(iRegLdst dst, immL src) %{
6238   match(Set dst src);
6239   ins_cost(MEMORY_REF_COST);
6240 
6241   format %{ "LD      $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
6242   // We can not inline the enc_class for the expand as that does not support constanttablebase.
6243   postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
6244 %}
6245 
6246 // Load NULL as compressed oop.
6247 instruct loadConN0(iRegNdst dst, immN_0 src) %{
6248   match(Set dst src);
6249   ins_cost(DEFAULT_COST);
6250 
6251   format %{ "LI      $dst, $src \t// compressed ptr" %}
6252   size(4);
6253   ins_encode %{
6254     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6255     __ li($dst$$Register, 0);
6256   %}
6257   ins_pipe(pipe_class_default);
6258 %}
6259 
6260 // Load hi part of compressed oop constant.
6261 instruct loadConN_hi(iRegNdst dst, immN src) %{
6262   effect(DEF dst, USE src);
6263   ins_cost(DEFAULT_COST);
6264 
6265   format %{ "LIS     $dst, $src \t// narrow oop hi" %}
6266   size(4);
6267   ins_encode %{
6268     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6269     __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
6270   %}
6271   ins_pipe(pipe_class_default);
6272 %}
6273 
6274 // Add lo part of compressed oop constant to already loaded hi part.
6275 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6276   effect(DEF dst, USE src1, USE src2);
6277   ins_cost(DEFAULT_COST);
6278 
6279   format %{ "ORI     $dst, $src1, $src2 \t// narrow oop lo" %}
6280   size(4);
6281   ins_encode %{
6282     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6283     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6284     int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6285     RelocationHolder rspec = oop_Relocation::spec(oop_index);
6286     __ relocate(rspec, 1);
6287     __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6288   %}
6289   ins_pipe(pipe_class_default);
6290 %}
6291 
6292 instruct rldicl(iRegLdst dst, iRegLsrc src, immI16 shift, immI16 mask_begin) %{
6293   effect(DEF dst, USE src, USE shift, USE mask_begin);
6294 
6295   size(4);
6296   ins_encode %{
6297     __ rldicl($dst$$Register, $src$$Register, $shift$$constant, $mask_begin$$constant);
6298   %}
6299   ins_pipe(pipe_class_default);
6300 %}
6301 
6302 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6303 // leaving the upper 32 bits with sign-extension bits.
6304 // This clears these bits: dst = src & 0xFFFFFFFF.
6305 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6306 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6307   effect(DEF dst, USE src);
6308   predicate(false);
6309 
6310   format %{ "MASK    $dst, $src, 0xFFFFFFFF" %} // mask
6311   size(4);
6312   ins_encode %{
6313     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6314     __ clrldi($dst$$Register, $src$$Register, 0x20);
6315   %}
6316   ins_pipe(pipe_class_default);
6317 %}
6318 
6319 // Optimize DecodeN for disjoint base.
6320 // Load base of compressed oops into a register
6321 instruct loadBase(iRegLdst dst) %{
6322   effect(DEF dst);
6323 
6324   format %{ "LoadConst $dst, heapbase" %}
6325   ins_encode %{
6326     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6327     __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
6328   %}
6329   ins_pipe(pipe_class_default);
6330 %}
6331 
6332 // Loading ConN must be postalloc expanded so that edges between
6333 // the nodes are safe. They may not interfere with a safepoint.
6334 // GL TODO: This needs three instructions: better put this into the constant pool.
6335 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6336   match(Set dst src);
6337   ins_cost(DEFAULT_COST*2);
6338 
6339   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6340   postalloc_expand %{
6341     MachNode *m1 = new loadConN_hiNode();
6342     MachNode *m2 = new loadConN_loNode();
6343     MachNode *m3 = new clearMs32bNode();
6344     m1->add_req(NULL);
6345     m2->add_req(NULL, m1);
6346     m3->add_req(NULL, m2);
6347     m1->_opnds[0] = op_dst;
6348     m1->_opnds[1] = op_src;
6349     m2->_opnds[0] = op_dst;
6350     m2->_opnds[1] = op_dst;
6351     m2->_opnds[2] = op_src;
6352     m3->_opnds[0] = op_dst;
6353     m3->_opnds[1] = op_dst;
6354     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6355     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6356     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6357     nodes->push(m1);
6358     nodes->push(m2);
6359     nodes->push(m3);
6360   %}
6361 %}
6362 
6363 // We have seen a safepoint between the hi and lo parts, and this node was handled
6364 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6365 // not a narrow oop.
6366 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6367   match(Set dst src);
6368   effect(DEF dst, USE src);
6369   ins_cost(DEFAULT_COST);
6370 
6371   format %{ "LIS     $dst, $src \t// narrow klass hi" %}
6372   size(4);
6373   ins_encode %{
6374     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6375     intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6376     __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6377   %}
6378   ins_pipe(pipe_class_default);
6379 %}
6380 
6381 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6382 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6383   match(Set dst src1);
6384   effect(TEMP src2);
6385   ins_cost(DEFAULT_COST);
6386 
6387   format %{ "MASK    $dst, $src2, 0xFFFFFFFF" %} // mask
6388   size(4);
6389   ins_encode %{
6390     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6391     __ clrldi($dst$$Register, $src2$$Register, 0x20);
6392   %}
6393   ins_pipe(pipe_class_default);
6394 %}
6395 
6396 // This needs a match rule so that build_oop_map knows this is
6397 // not a narrow oop.
6398 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6399   match(Set dst src1);
6400   effect(TEMP src2);
6401   ins_cost(DEFAULT_COST);
6402 
6403   format %{ "ORI     $dst, $src1, $src2 \t// narrow klass lo" %}
6404   size(4);
6405   ins_encode %{
6406     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6407     intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6408     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6409     int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6410     RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6411 
6412     __ relocate(rspec, 1);
6413     __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6414   %}
6415   ins_pipe(pipe_class_default);
6416 %}
6417 
6418 // Loading ConNKlass must be postalloc expanded so that edges between
6419 // the nodes are safe. They may not interfere with a safepoint.
6420 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6421   match(Set dst src);
6422   ins_cost(DEFAULT_COST*2);
6423 
6424   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6425   postalloc_expand %{
6426     // Load high bits into register. Sign extended.
6427     MachNode *m1 = new loadConNKlass_hiNode();
6428     m1->add_req(NULL);
6429     m1->_opnds[0] = op_dst;
6430     m1->_opnds[1] = op_src;
6431     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6432     nodes->push(m1);
6433 
6434     MachNode *m2 = m1;
6435     if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6436       // Value might be 1-extended. Mask out these bits.
6437       m2 = new loadConNKlass_maskNode();
6438       m2->add_req(NULL, m1);
6439       m2->_opnds[0] = op_dst;
6440       m2->_opnds[1] = op_src;
6441       m2->_opnds[2] = op_dst;
6442       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6443       nodes->push(m2);
6444     }
6445 
6446     MachNode *m3 = new loadConNKlass_loNode();
6447     m3->add_req(NULL, m2);
6448     m3->_opnds[0] = op_dst;
6449     m3->_opnds[1] = op_src;
6450     m3->_opnds[2] = op_dst;
6451     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6452     nodes->push(m3);
6453   %}
6454 %}
6455 
6456 // 0x1 is used in object initialization (initial object header).
6457 // No constant pool entries required.
6458 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6459   match(Set dst src);
6460 
6461   format %{ "LI      $dst, $src \t// ptr" %}
6462   size(4);
6463   ins_encode %{
6464     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6465     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6466   %}
6467   ins_pipe(pipe_class_default);
6468 %}
6469 
6470 // Expand node for constant pool load: small offset.
6471 // The match rule is needed to generate the correct bottom_type(),
6472 // however this node should never match. The use of predicate is not
6473 // possible since ADLC forbids predicates for chain rules. The higher
6474 // costs do not prevent matching in this case. For that reason the
6475 // operand immP_NM with predicate(false) is used.
6476 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6477   match(Set dst src);
6478   effect(TEMP toc);
6479 
6480   ins_num_consts(1);
6481 
6482   format %{ "LD      $dst, offset, $toc \t// load ptr $src from TOC" %}
6483   size(4);
6484   ins_encode( enc_load_long_constP(dst, src, toc) );
6485   ins_pipe(pipe_class_memory);
6486 %}
6487 
6488 // Expand node for constant pool load: large offset.
6489 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6490   effect(DEF dst, USE src, USE toc);
6491   predicate(false);
6492 
6493   ins_num_consts(1);
6494   ins_field_const_toc_offset(int);
6495 
6496   format %{ "ADDIS   $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6497   size(4);
6498   ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6499   ins_pipe(pipe_class_default);
6500 %}
6501 
6502 // Expand node for constant pool load: large offset.
6503 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6504   match(Set dst src);
6505   effect(TEMP base);
6506 
6507   ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6508 
6509   format %{ "LD      $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6510   size(4);
6511   ins_encode %{
6512     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6513     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6514     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6515   %}
6516   ins_pipe(pipe_class_memory);
6517 %}
6518 
6519 // Load pointer constant from constant table. Expand in case an
6520 // offset > 16 bit is needed.
6521 // Adlc adds toc node MachConstantTableBase.
6522 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6523   match(Set dst src);
6524   ins_cost(MEMORY_REF_COST);
6525 
6526   // This rule does not use "expand" because then
6527   // the result type is not known to be an Oop.  An ADLC
6528   // enhancement will be needed to make that work - not worth it!
6529 
6530   // If this instruction rematerializes, it prolongs the live range
6531   // of the toc node, causing illegal graphs.
6532   // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6533   ins_cannot_rematerialize(true);
6534 
6535   format %{ "LD    $dst, offset, $constanttablebase \t//  load ptr $src from table, postalloc expanded" %}
6536   postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6537 %}
6538 
6539 // Expand node for constant pool load: small offset.
6540 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6541   effect(DEF dst, USE src, USE toc);
6542   ins_cost(MEMORY_REF_COST);
6543 
6544   ins_num_consts(1);
6545 
6546   format %{ "LFS     $dst, offset, $toc \t// load float $src from TOC" %}
6547   size(4);
6548   ins_encode %{
6549     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6550     address float_address = __ float_constant($src$$constant);
6551     if (float_address == NULL) {
6552       ciEnv::current()->record_out_of_memory_failure();
6553       return;
6554     }
6555     __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6556   %}
6557   ins_pipe(pipe_class_memory);
6558 %}
6559 
6560 // Expand node for constant pool load: large offset.
6561 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6562   effect(DEF dst, USE src, USE toc);
6563   ins_cost(MEMORY_REF_COST);
6564 
6565   ins_num_consts(1);
6566 
6567   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6568             "LFS     $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6569             "ADDIS   $toc, $toc, -offset_hi"%}
6570   size(12);
6571   ins_encode %{
6572     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6573     FloatRegister Rdst    = $dst$$FloatRegister;
6574     Register Rtoc         = $toc$$Register;
6575     address float_address = __ float_constant($src$$constant);
6576     if (float_address == NULL) {
6577       ciEnv::current()->record_out_of_memory_failure();
6578       return;
6579     }
6580     int offset            = __ offset_to_method_toc(float_address);
6581     int hi = (offset + (1<<15))>>16;
6582     int lo = offset - hi * (1<<16);
6583 
6584     __ addis(Rtoc, Rtoc, hi);
6585     __ lfs(Rdst, lo, Rtoc);
6586     __ addis(Rtoc, Rtoc, -hi);
6587   %}
6588   ins_pipe(pipe_class_memory);
6589 %}
6590 
6591 // Adlc adds toc node MachConstantTableBase.
6592 instruct loadConF_Ex(regF dst, immF src) %{
6593   match(Set dst src);
6594   ins_cost(MEMORY_REF_COST);
6595 
6596   // See loadConP.
6597   ins_cannot_rematerialize(true);
6598 
6599   format %{ "LFS     $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6600   postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6601 %}
6602 
6603 // Expand node for constant pool load: small offset.
6604 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6605   effect(DEF dst, USE src, USE toc);
6606   ins_cost(MEMORY_REF_COST);
6607 
6608   ins_num_consts(1);
6609 
6610   format %{ "LFD     $dst, offset, $toc \t// load double $src from TOC" %}
6611   size(4);
6612   ins_encode %{
6613     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6614     address float_address = __ double_constant($src$$constant);
6615     if (float_address == NULL) {
6616       ciEnv::current()->record_out_of_memory_failure();
6617       return;
6618     }
6619     int offset =  __ offset_to_method_toc(float_address);
6620     __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6621   %}
6622   ins_pipe(pipe_class_memory);
6623 %}
6624 
6625 // Expand node for constant pool load: large offset.
6626 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6627   effect(DEF dst, USE src, USE toc);
6628   ins_cost(MEMORY_REF_COST);
6629 
6630   ins_num_consts(1);
6631 
6632   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6633             "LFD     $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6634             "ADDIS   $toc, $toc, -offset_hi" %}
6635   size(12);
6636   ins_encode %{
6637     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6638     FloatRegister Rdst    = $dst$$FloatRegister;
6639     Register      Rtoc    = $toc$$Register;
6640     address float_address = __ double_constant($src$$constant);
6641     if (float_address == NULL) {
6642       ciEnv::current()->record_out_of_memory_failure();
6643       return;
6644     }
6645     int offset = __ offset_to_method_toc(float_address);
6646     int hi = (offset + (1<<15))>>16;
6647     int lo = offset - hi * (1<<16);
6648 
6649     __ addis(Rtoc, Rtoc, hi);
6650     __ lfd(Rdst, lo, Rtoc);
6651     __ addis(Rtoc, Rtoc, -hi);
6652   %}
6653   ins_pipe(pipe_class_memory);
6654 %}
6655 
6656 // Adlc adds toc node MachConstantTableBase.
6657 instruct loadConD_Ex(regD dst, immD src) %{
6658   match(Set dst src);
6659   ins_cost(MEMORY_REF_COST);
6660 
6661   // See loadConP.
6662   ins_cannot_rematerialize(true);
6663 
6664   format %{ "ConD    $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6665   postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6666 %}
6667 
6668 // Prefetch instructions.
6669 // Must be safe to execute with invalid address (cannot fault).
6670 
6671 // Special prefetch versions which use the dcbz instruction.
6672 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6673   match(PrefetchAllocation (AddP mem src));
6674   predicate(AllocatePrefetchStyle == 3);
6675   ins_cost(MEMORY_REF_COST);
6676 
6677   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6678   size(4);
6679   ins_encode %{
6680     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6681     __ dcbz($src$$Register, $mem$$base$$Register);
6682   %}
6683   ins_pipe(pipe_class_memory);
6684 %}
6685 
6686 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6687   match(PrefetchAllocation mem);
6688   predicate(AllocatePrefetchStyle == 3);
6689   ins_cost(MEMORY_REF_COST);
6690 
6691   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6692   size(4);
6693   ins_encode %{
6694     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6695     __ dcbz($mem$$base$$Register);
6696   %}
6697   ins_pipe(pipe_class_memory);
6698 %}
6699 
6700 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6701   match(PrefetchAllocation (AddP mem src));
6702   predicate(AllocatePrefetchStyle != 3);
6703   ins_cost(MEMORY_REF_COST);
6704 
6705   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6706   size(4);
6707   ins_encode %{
6708     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6709     __ dcbtst($src$$Register, $mem$$base$$Register);
6710   %}
6711   ins_pipe(pipe_class_memory);
6712 %}
6713 
6714 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6715   match(PrefetchAllocation mem);
6716   predicate(AllocatePrefetchStyle != 3);
6717   ins_cost(MEMORY_REF_COST);
6718 
6719   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6720   size(4);
6721   ins_encode %{
6722     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6723     __ dcbtst($mem$$base$$Register);
6724   %}
6725   ins_pipe(pipe_class_memory);
6726 %}
6727 
6728 //----------Store Instructions-------------------------------------------------
6729 
6730 // Store Byte
6731 instruct storeB(memory mem, iRegIsrc src) %{
6732   match(Set mem (StoreB mem src));
6733   ins_cost(MEMORY_REF_COST);
6734 
6735   format %{ "STB     $src, $mem \t// byte" %}
6736   size(4);
6737   ins_encode %{
6738     // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6739     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6740     __ stb($src$$Register, Idisp, $mem$$base$$Register);
6741   %}
6742   ins_pipe(pipe_class_memory);
6743 %}
6744 
6745 // Store Char/Short
6746 instruct storeC(memory mem, iRegIsrc src) %{
6747   match(Set mem (StoreC mem src));
6748   ins_cost(MEMORY_REF_COST);
6749 
6750   format %{ "STH     $src, $mem \t// short" %}
6751   size(4);
6752   ins_encode %{
6753     // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6754     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6755     __ sth($src$$Register, Idisp, $mem$$base$$Register);
6756   %}
6757   ins_pipe(pipe_class_memory);
6758 %}
6759 
6760 // Store Integer
6761 instruct storeI(memory mem, iRegIsrc src) %{
6762   match(Set mem (StoreI mem src));
6763   ins_cost(MEMORY_REF_COST);
6764 
6765   format %{ "STW     $src, $mem" %}
6766   size(4);
6767   ins_encode( enc_stw(src, mem) );
6768   ins_pipe(pipe_class_memory);
6769 %}
6770 
6771 // ConvL2I + StoreI.
6772 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6773   match(Set mem (StoreI mem (ConvL2I src)));
6774   ins_cost(MEMORY_REF_COST);
6775 
6776   format %{ "STW     l2i($src), $mem" %}
6777   size(4);
6778   ins_encode( enc_stw(src, mem) );
6779   ins_pipe(pipe_class_memory);
6780 %}
6781 
6782 // Store Long
6783 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6784   match(Set mem (StoreL mem src));
6785   ins_cost(MEMORY_REF_COST);
6786 
6787   format %{ "STD     $src, $mem \t// long" %}
6788   size(4);
6789   ins_encode( enc_std(src, mem) );
6790   ins_pipe(pipe_class_memory);
6791 %}
6792 
6793 // Store super word nodes.
6794 
6795 // Store Aligned Packed Byte long register to memory
6796 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6797   predicate(n->as_StoreVector()->memory_size() == 8);
6798   match(Set mem (StoreVector mem src));
6799   ins_cost(MEMORY_REF_COST);
6800 
6801   format %{ "STD     $mem, $src \t// packed8B" %}
6802   size(4);
6803   ins_encode( enc_std(src, mem) );
6804   ins_pipe(pipe_class_memory);
6805 %}
6806 
6807 // Store Packed Byte long register to memory
6808 instruct storeV16(indirect mem, vecX src) %{
6809   predicate(n->as_StoreVector()->memory_size() == 16);
6810   match(Set mem (StoreVector mem src));
6811   ins_cost(MEMORY_REF_COST);
6812 
6813   format %{ "STXVD2X     $mem, $src \t// store 16-byte Vector" %}
6814   size(4);
6815   ins_encode %{
6816     __ stxvd2x($src$$VectorSRegister, $mem$$Register);
6817   %}
6818   ins_pipe(pipe_class_default);
6819 %}
6820 
6821 // Store Compressed Oop
6822 instruct storeN(memory dst, iRegN_P2N src) %{
6823   match(Set dst (StoreN dst src));
6824   ins_cost(MEMORY_REF_COST);
6825 
6826   format %{ "STW     $src, $dst \t// compressed oop" %}
6827   size(4);
6828   ins_encode( enc_stw(src, dst) );
6829   ins_pipe(pipe_class_memory);
6830 %}
6831 
6832 // Store Compressed KLass
6833 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6834   match(Set dst (StoreNKlass dst src));
6835   ins_cost(MEMORY_REF_COST);
6836 
6837   format %{ "STW     $src, $dst \t// compressed klass" %}
6838   size(4);
6839   ins_encode( enc_stw(src, dst) );
6840   ins_pipe(pipe_class_memory);
6841 %}
6842 
6843 // Store Pointer
6844 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6845   match(Set dst (StoreP dst src));
6846   ins_cost(MEMORY_REF_COST);
6847 
6848   format %{ "STD     $src, $dst \t// ptr" %}
6849   size(4);
6850   ins_encode( enc_std(src, dst) );
6851   ins_pipe(pipe_class_memory);
6852 %}
6853 
6854 // Store Float
6855 instruct storeF(memory mem, regF src) %{
6856   match(Set mem (StoreF mem src));
6857   ins_cost(MEMORY_REF_COST);
6858 
6859   format %{ "STFS    $src, $mem" %}
6860   size(4);
6861   ins_encode( enc_stfs(src, mem) );
6862   ins_pipe(pipe_class_memory);
6863 %}
6864 
6865 // Store Double
6866 instruct storeD(memory mem, regD src) %{
6867   match(Set mem (StoreD mem src));
6868   ins_cost(MEMORY_REF_COST);
6869 
6870   format %{ "STFD    $src, $mem" %}
6871   size(4);
6872   ins_encode( enc_stfd(src, mem) );
6873   ins_pipe(pipe_class_memory);
6874 %}
6875 
6876 //----------Store Instructions With Zeros--------------------------------------
6877 
6878 // Card-mark for CMS garbage collection.
6879 // This cardmark does an optimization so that it must not always
6880 // do a releasing store. For this, it gets the address of
6881 // CMSCollectorCardTableBarrierSetBSExt::_requires_release as input.
6882 // (Using releaseFieldAddr in the match rule is a hack.)
6883 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6884   match(Set mem (StoreCM mem releaseFieldAddr));
6885   effect(TEMP crx);
6886   predicate(false);
6887   ins_cost(MEMORY_REF_COST);
6888 
6889   // See loadConP.
6890   ins_cannot_rematerialize(true);
6891 
6892   format %{ "STB     #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6893   ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6894   ins_pipe(pipe_class_memory);
6895 %}
6896 
6897 // Card-mark for CMS garbage collection.
6898 // This cardmark does an optimization so that it must not always
6899 // do a releasing store. For this, it needs the constant address of
6900 // CMSCollectorCardTableBarrierSetBSExt::_requires_release.
6901 // This constant address is split off here by expand so we can use
6902 // adlc / matcher functionality to load it from the constant section.
6903 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6904   match(Set mem (StoreCM mem zero));
6905   predicate(UseConcMarkSweepGC);
6906 
6907   expand %{
6908     immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableBarrierSetBSExt::requires_release_address() */ %}
6909     iRegLdst releaseFieldAddress;
6910     flagsReg crx;
6911     loadConL_Ex(releaseFieldAddress, baseImm);
6912     storeCM_CMS(mem, releaseFieldAddress, crx);
6913   %}
6914 %}
6915 
6916 instruct storeCM_G1(memory mem, immI_0 zero) %{
6917   match(Set mem (StoreCM mem zero));
6918   predicate(UseG1GC);
6919   ins_cost(MEMORY_REF_COST);
6920 
6921   ins_cannot_rematerialize(true);
6922 
6923   format %{ "STB     #0, $mem \t// CMS card-mark byte store (G1)" %}
6924   size(8);
6925   ins_encode %{
6926     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6927     __ li(R0, 0);
6928     //__ release(); // G1: oops are allowed to get visible after dirty marking
6929     guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6930     __ stb(R0, $mem$$disp, $mem$$base$$Register);
6931   %}
6932   ins_pipe(pipe_class_memory);
6933 %}
6934 
6935 // Convert oop pointer into compressed form.
6936 
6937 // Nodes for postalloc expand.
6938 
6939 // Shift node for expand.
6940 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6941   // The match rule is needed to make it a 'MachTypeNode'!
6942   match(Set dst (EncodeP src));
6943   predicate(false);
6944 
6945   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6946   size(4);
6947   ins_encode %{
6948     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6949     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6950   %}
6951   ins_pipe(pipe_class_default);
6952 %}
6953 
6954 // Add node for expand.
6955 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6956   // The match rule is needed to make it a 'MachTypeNode'!
6957   match(Set dst (EncodeP src));
6958   predicate(false);
6959 
6960   format %{ "SUB     $dst, $src, oop_base \t// encode" %}
6961   ins_encode %{
6962     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6963     __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6964   %}
6965   ins_pipe(pipe_class_default);
6966 %}
6967 
6968 // Conditional sub base.
6969 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6970   // The match rule is needed to make it a 'MachTypeNode'!
6971   match(Set dst (EncodeP (Binary crx src1)));
6972   predicate(false);
6973 
6974   format %{ "BEQ     $crx, done\n\t"
6975             "SUB     $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6976             "done:" %}
6977   ins_encode %{
6978     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6979     Label done;
6980     __ beq($crx$$CondRegister, done);
6981     __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6982     __ bind(done);
6983   %}
6984   ins_pipe(pipe_class_default);
6985 %}
6986 
6987 // Power 7 can use isel instruction
6988 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6989   // The match rule is needed to make it a 'MachTypeNode'!
6990   match(Set dst (EncodeP (Binary crx src1)));
6991   predicate(false);
6992 
6993   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6994   size(4);
6995   ins_encode %{
6996     // This is a Power7 instruction for which no machine description exists.
6997     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6998     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6999   %}
7000   ins_pipe(pipe_class_default);
7001 %}
7002 
7003 // Disjoint narrow oop base.
7004 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
7005   match(Set dst (EncodeP src));
7006   predicate(Universe::narrow_oop_base_disjoint());
7007 
7008   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
7009   size(4);
7010   ins_encode %{
7011     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7012     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
7013   %}
7014   ins_pipe(pipe_class_default);
7015 %}
7016 
7017 // shift != 0, base != 0
7018 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
7019   match(Set dst (EncodeP src));
7020   effect(TEMP crx);
7021   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
7022             Universe::narrow_oop_shift() != 0 &&
7023             Universe::narrow_oop_base_overlaps());
7024 
7025   format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
7026   postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
7027 %}
7028 
7029 // shift != 0, base != 0
7030 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
7031   match(Set dst (EncodeP src));
7032   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
7033             Universe::narrow_oop_shift() != 0 &&
7034             Universe::narrow_oop_base_overlaps());
7035 
7036   format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
7037   postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
7038 %}
7039 
7040 // shift != 0, base == 0
7041 // TODO: This is the same as encodeP_shift. Merge!
7042 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
7043   match(Set dst (EncodeP src));
7044   predicate(Universe::narrow_oop_shift() != 0 &&
7045             Universe::narrow_oop_base() ==0);
7046 
7047   format %{ "SRDI    $dst, $src, #3 \t// encodeP, $src != NULL" %}
7048   size(4);
7049   ins_encode %{
7050     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7051     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
7052   %}
7053   ins_pipe(pipe_class_default);
7054 %}
7055 
7056 // Compressed OOPs with narrow_oop_shift == 0.
7057 // shift == 0, base == 0
7058 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
7059   match(Set dst (EncodeP src));
7060   predicate(Universe::narrow_oop_shift() == 0);
7061 
7062   format %{ "MR      $dst, $src \t// Ptr->Narrow" %}
7063   // variable size, 0 or 4.
7064   ins_encode %{
7065     // TODO: PPC port $archOpcode(ppc64Opcode_or);
7066     __ mr_if_needed($dst$$Register, $src$$Register);
7067   %}
7068   ins_pipe(pipe_class_default);
7069 %}
7070 
7071 // Decode nodes.
7072 
7073 // Shift node for expand.
7074 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
7075   // The match rule is needed to make it a 'MachTypeNode'!
7076   match(Set dst (DecodeN src));
7077   predicate(false);
7078 
7079   format %{ "SLDI    $dst, $src, #3 \t// DecodeN" %}
7080   size(4);
7081   ins_encode %{
7082     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7083     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
7084   %}
7085   ins_pipe(pipe_class_default);
7086 %}
7087 
7088 // Add node for expand.
7089 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
7090   // The match rule is needed to make it a 'MachTypeNode'!
7091   match(Set dst (DecodeN src));
7092   predicate(false);
7093 
7094   format %{ "ADD     $dst, $src, heapbase \t// DecodeN, add oop base" %}
7095   ins_encode %{
7096     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7097     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
7098   %}
7099   ins_pipe(pipe_class_default);
7100 %}
7101 
7102 // conditianal add base for expand
7103 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
7104   // The match rule is needed to make it a 'MachTypeNode'!
7105   // NOTICE that the rule is nonsense - we just have to make sure that:
7106   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
7107   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
7108   match(Set dst (DecodeN (Binary crx src)));
7109   predicate(false);
7110 
7111   format %{ "BEQ     $crx, done\n\t"
7112             "ADD     $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
7113             "done:" %}
7114   ins_encode %{
7115     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7116     Label done;
7117     __ beq($crx$$CondRegister, done);
7118     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
7119     __ bind(done);
7120   %}
7121   ins_pipe(pipe_class_default);
7122 %}
7123 
7124 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
7125   // The match rule is needed to make it a 'MachTypeNode'!
7126   // NOTICE that the rule is nonsense - we just have to make sure that:
7127   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
7128   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
7129   match(Set dst (DecodeN (Binary crx src1)));
7130   predicate(false);
7131 
7132   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
7133   size(4);
7134   ins_encode %{
7135     // This is a Power7 instruction for which no machine description exists.
7136     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7137     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
7138   %}
7139   ins_pipe(pipe_class_default);
7140 %}
7141 
7142 //  shift != 0, base != 0
7143 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
7144   match(Set dst (DecodeN src));
7145   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
7146              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
7147             Universe::narrow_oop_shift() != 0 &&
7148             Universe::narrow_oop_base() != 0);
7149   ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
7150   effect(TEMP crx);
7151 
7152   format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
7153   postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
7154 %}
7155 
7156 // shift != 0, base == 0
7157 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
7158   match(Set dst (DecodeN src));
7159   predicate(Universe::narrow_oop_shift() != 0 &&
7160             Universe::narrow_oop_base() == 0);
7161 
7162   format %{ "SLDI    $dst, $src, #3 \t// DecodeN (zerobased)" %}
7163   size(4);
7164   ins_encode %{
7165     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7166     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
7167   %}
7168   ins_pipe(pipe_class_default);
7169 %}
7170 
7171 // Optimize DecodeN for disjoint base.
7172 // Shift narrow oop and or it into register that already contains the heap base.
7173 // Base == dst must hold, and is assured by construction in postaloc_expand.
7174 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
7175   match(Set dst (DecodeN src));
7176   effect(TEMP base);
7177   predicate(false);
7178 
7179   format %{ "RLDIMI  $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
7180   size(4);
7181   ins_encode %{
7182     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
7183     __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
7184   %}
7185   ins_pipe(pipe_class_default);
7186 %}
7187 
7188 // Optimize DecodeN for disjoint base.
7189 // This node requires only one cycle on the critical path.
7190 // We must postalloc_expand as we can not express use_def effects where
7191 // the used register is L and the def'ed register P.
7192 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
7193   match(Set dst (DecodeN src));
7194   effect(TEMP_DEF dst);
7195   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
7196              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
7197             Universe::narrow_oop_base_disjoint());
7198   ins_cost(DEFAULT_COST);
7199 
7200   format %{ "MOV     $dst, heapbase \t\n"
7201             "RLDIMI  $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
7202   postalloc_expand %{
7203     loadBaseNode *n1 = new loadBaseNode();
7204     n1->add_req(NULL);
7205     n1->_opnds[0] = op_dst;
7206 
7207     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
7208     n2->add_req(n_region, n_src, n1);
7209     n2->_opnds[0] = op_dst;
7210     n2->_opnds[1] = op_src;
7211     n2->_opnds[2] = op_dst;
7212     n2->_bottom_type = _bottom_type;
7213 
7214     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7215     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7216 
7217     nodes->push(n1);
7218     nodes->push(n2);
7219   %}
7220 %}
7221 
7222 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
7223   match(Set dst (DecodeN src));
7224   effect(TEMP_DEF dst, TEMP crx);
7225   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
7226              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
7227             Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
7228   ins_cost(3 * DEFAULT_COST);
7229 
7230   format %{ "DecodeN  $dst, $src \t// decode with disjoint base using isel" %}
7231   postalloc_expand %{
7232     loadBaseNode *n1 = new loadBaseNode();
7233     n1->add_req(NULL);
7234     n1->_opnds[0] = op_dst;
7235 
7236     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
7237     n_compare->add_req(n_region, n_src);
7238     n_compare->_opnds[0] = op_crx;
7239     n_compare->_opnds[1] = op_src;
7240     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
7241 
7242     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
7243     n2->add_req(n_region, n_src, n1);
7244     n2->_opnds[0] = op_dst;
7245     n2->_opnds[1] = op_src;
7246     n2->_opnds[2] = op_dst;
7247     n2->_bottom_type = _bottom_type;
7248 
7249     cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
7250     n_cond_set->add_req(n_region, n_compare, n2);
7251     n_cond_set->_opnds[0] = op_dst;
7252     n_cond_set->_opnds[1] = op_crx;
7253     n_cond_set->_opnds[2] = op_dst;
7254     n_cond_set->_bottom_type = _bottom_type;
7255 
7256     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
7257     ra_->set_oop(n_cond_set, true);
7258 
7259     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7260     ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
7261     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7262     ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7263 
7264     nodes->push(n1);
7265     nodes->push(n_compare);
7266     nodes->push(n2);
7267     nodes->push(n_cond_set);
7268   %}
7269 %}
7270 
7271 // src != 0, shift != 0, base != 0
7272 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
7273   match(Set dst (DecodeN src));
7274   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
7275              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
7276             Universe::narrow_oop_shift() != 0 &&
7277             Universe::narrow_oop_base() != 0);
7278   ins_cost(2 * DEFAULT_COST);
7279 
7280   format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
7281   postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
7282 %}
7283 
7284 // Compressed OOPs with narrow_oop_shift == 0.
7285 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
7286   match(Set dst (DecodeN src));
7287   predicate(Universe::narrow_oop_shift() == 0);
7288   ins_cost(DEFAULT_COST);
7289 
7290   format %{ "MR      $dst, $src \t// DecodeN (unscaled)" %}
7291   // variable size, 0 or 4.
7292   ins_encode %{
7293     // TODO: PPC port $archOpcode(ppc64Opcode_or);
7294     __ mr_if_needed($dst$$Register, $src$$Register);
7295   %}
7296   ins_pipe(pipe_class_default);
7297 %}
7298 
7299 // Convert compressed oop into int for vectors alignment masking.
7300 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
7301   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
7302   predicate(Universe::narrow_oop_shift() == 0);
7303   ins_cost(DEFAULT_COST);
7304 
7305   format %{ "MR      $dst, $src \t// (int)DecodeN (unscaled)" %}
7306   // variable size, 0 or 4.
7307   ins_encode %{
7308     // TODO: PPC port $archOpcode(ppc64Opcode_or);
7309     __ mr_if_needed($dst$$Register, $src$$Register);
7310   %}
7311   ins_pipe(pipe_class_default);
7312 %}
7313 
7314 // Convert klass pointer into compressed form.
7315 
7316 // Nodes for postalloc expand.
7317 
7318 // Shift node for expand.
7319 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
7320   // The match rule is needed to make it a 'MachTypeNode'!
7321   match(Set dst (EncodePKlass src));
7322   predicate(false);
7323 
7324   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
7325   size(4);
7326   ins_encode %{
7327     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7328     __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7329   %}
7330   ins_pipe(pipe_class_default);
7331 %}
7332 
7333 // Add node for expand.
7334 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7335   // The match rule is needed to make it a 'MachTypeNode'!
7336   match(Set dst (EncodePKlass (Binary base src)));
7337   predicate(false);
7338 
7339   format %{ "SUB     $dst, $base, $src \t// encode" %}
7340   size(4);
7341   ins_encode %{
7342     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7343     __ subf($dst$$Register, $base$$Register, $src$$Register);
7344   %}
7345   ins_pipe(pipe_class_default);
7346 %}
7347 
7348 // Disjoint narrow oop base.
7349 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7350   match(Set dst (EncodePKlass src));
7351   predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7352 
7353   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
7354   size(4);
7355   ins_encode %{
7356     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7357     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7358   %}
7359   ins_pipe(pipe_class_default);
7360 %}
7361 
7362 // shift != 0, base != 0
7363 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7364   match(Set dst (EncodePKlass (Binary base src)));
7365   predicate(false);
7366 
7367   format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7368   postalloc_expand %{
7369     encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7370     n1->add_req(n_region, n_base, n_src);
7371     n1->_opnds[0] = op_dst;
7372     n1->_opnds[1] = op_base;
7373     n1->_opnds[2] = op_src;
7374     n1->_bottom_type = _bottom_type;
7375 
7376     encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7377     n2->add_req(n_region, n1);
7378     n2->_opnds[0] = op_dst;
7379     n2->_opnds[1] = op_dst;
7380     n2->_bottom_type = _bottom_type;
7381     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7382     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7383 
7384     nodes->push(n1);
7385     nodes->push(n2);
7386   %}
7387 %}
7388 
7389 // shift != 0, base != 0
7390 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7391   match(Set dst (EncodePKlass src));
7392   //predicate(Universe::narrow_klass_shift() != 0 &&
7393   //          true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7394 
7395   //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7396   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7397   expand %{
7398     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7399     iRegLdst base;
7400     loadConL_Ex(base, baseImm);
7401     encodePKlass_not_null_Ex(dst, base, src);
7402   %}
7403 %}
7404 
7405 // Decode nodes.
7406 
7407 // Shift node for expand.
7408 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7409   // The match rule is needed to make it a 'MachTypeNode'!
7410   match(Set dst (DecodeNKlass src));
7411   predicate(false);
7412 
7413   format %{ "SLDI    $dst, $src, #3 \t// DecodeNKlass" %}
7414   size(4);
7415   ins_encode %{
7416     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7417     __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7418   %}
7419   ins_pipe(pipe_class_default);
7420 %}
7421 
7422 // Add node for expand.
7423 
7424 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7425   // The match rule is needed to make it a 'MachTypeNode'!
7426   match(Set dst (DecodeNKlass (Binary base src)));
7427   predicate(false);
7428 
7429   format %{ "ADD     $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7430   size(4);
7431   ins_encode %{
7432     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7433     __ add($dst$$Register, $base$$Register, $src$$Register);
7434   %}
7435   ins_pipe(pipe_class_default);
7436 %}
7437 
7438 // src != 0, shift != 0, base != 0
7439 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7440   match(Set dst (DecodeNKlass (Binary base src)));
7441   //effect(kill src); // We need a register for the immediate result after shifting.
7442   predicate(false);
7443 
7444   format %{ "DecodeNKlass $dst =  $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7445   postalloc_expand %{
7446     decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7447     n1->add_req(n_region, n_base, n_src);
7448     n1->_opnds[0] = op_dst;
7449     n1->_opnds[1] = op_base;
7450     n1->_opnds[2] = op_src;
7451     n1->_bottom_type = _bottom_type;
7452 
7453     decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7454     n2->add_req(n_region, n1);
7455     n2->_opnds[0] = op_dst;
7456     n2->_opnds[1] = op_dst;
7457     n2->_bottom_type = _bottom_type;
7458 
7459     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7460     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7461 
7462     nodes->push(n1);
7463     nodes->push(n2);
7464   %}
7465 %}
7466 
7467 // src != 0, shift != 0, base != 0
7468 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7469   match(Set dst (DecodeNKlass src));
7470   // predicate(Universe::narrow_klass_shift() != 0 &&
7471   //           Universe::narrow_klass_base() != 0);
7472 
7473   //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7474 
7475   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7476   expand %{
7477     // We add first, then we shift. Like this, we can get along with one register less.
7478     // But we have to load the base pre-shifted.
7479     immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7480     iRegLdst base;
7481     loadConL_Ex(base, baseImm);
7482     decodeNKlass_notNull_addBase_Ex(dst, base, src);
7483   %}
7484 %}
7485 
7486 //----------MemBar Instructions-----------------------------------------------
7487 // Memory barrier flavors
7488 
7489 instruct membar_acquire() %{
7490   match(LoadFence);
7491   ins_cost(4*MEMORY_REF_COST);
7492 
7493   format %{ "MEMBAR-acquire" %}
7494   size(4);
7495   ins_encode %{
7496     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7497     __ acquire();
7498   %}
7499   ins_pipe(pipe_class_default);
7500 %}
7501 
7502 instruct unnecessary_membar_acquire() %{
7503   match(MemBarAcquire);
7504   ins_cost(0);
7505 
7506   format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7507   size(0);
7508   ins_encode( /*empty*/ );
7509   ins_pipe(pipe_class_default);
7510 %}
7511 
7512 instruct membar_acquire_lock() %{
7513   match(MemBarAcquireLock);
7514   ins_cost(0);
7515 
7516   format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7517   size(0);
7518   ins_encode( /*empty*/ );
7519   ins_pipe(pipe_class_default);
7520 %}
7521 
7522 instruct membar_release() %{
7523   match(MemBarRelease);
7524   match(StoreFence);
7525   ins_cost(4*MEMORY_REF_COST);
7526 
7527   format %{ "MEMBAR-release" %}
7528   size(4);
7529   ins_encode %{
7530     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7531     __ release();
7532   %}
7533   ins_pipe(pipe_class_default);
7534 %}
7535 
7536 instruct membar_storestore() %{
7537   match(MemBarStoreStore);
7538   ins_cost(4*MEMORY_REF_COST);
7539 
7540   format %{ "MEMBAR-store-store" %}
7541   size(4);
7542   ins_encode %{
7543     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7544     __ membar(Assembler::StoreStore);
7545   %}
7546   ins_pipe(pipe_class_default);
7547 %}
7548 
7549 instruct membar_release_lock() %{
7550   match(MemBarReleaseLock);
7551   ins_cost(0);
7552 
7553   format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7554   size(0);
7555   ins_encode( /*empty*/ );
7556   ins_pipe(pipe_class_default);
7557 %}
7558 
7559 instruct membar_volatile() %{
7560   match(MemBarVolatile);
7561   ins_cost(4*MEMORY_REF_COST);
7562 
7563   format %{ "MEMBAR-volatile" %}
7564   size(4);
7565   ins_encode %{
7566     // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7567     __ fence();
7568   %}
7569   ins_pipe(pipe_class_default);
7570 %}
7571 
7572 // This optimization is wrong on PPC. The following pattern is not supported:
7573 //  MemBarVolatile
7574 //   ^        ^
7575 //   |        |
7576 //  CtrlProj MemProj
7577 //   ^        ^
7578 //   |        |
7579 //   |       Load
7580 //   |
7581 //  MemBarVolatile
7582 //
7583 //  The first MemBarVolatile could get optimized out! According to
7584 //  Vladimir, this pattern can not occur on Oracle platforms.
7585 //  However, it does occur on PPC64 (because of membars in
7586 //  inline_unsafe_load_store).
7587 //
7588 // Add this node again if we found a good solution for inline_unsafe_load_store().
7589 // Don't forget to look at the implementation of post_store_load_barrier again,
7590 // we did other fixes in that method.
7591 //instruct unnecessary_membar_volatile() %{
7592 //  match(MemBarVolatile);
7593 //  predicate(Matcher::post_store_load_barrier(n));
7594 //  ins_cost(0);
7595 //
7596 //  format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7597 //  size(0);
7598 //  ins_encode( /*empty*/ );
7599 //  ins_pipe(pipe_class_default);
7600 //%}
7601 
7602 instruct membar_CPUOrder() %{
7603   match(MemBarCPUOrder);
7604   ins_cost(0);
7605 
7606   format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7607   size(0);
7608   ins_encode( /*empty*/ );
7609   ins_pipe(pipe_class_default);
7610 %}
7611 
7612 //----------Conditional Move---------------------------------------------------
7613 
7614 // Cmove using isel.
7615 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7616   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7617   predicate(VM_Version::has_isel());
7618   ins_cost(DEFAULT_COST);
7619 
7620   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7621   size(4);
7622   ins_encode %{
7623     // This is a Power7 instruction for which no machine description
7624     // exists. Anyways, the scheduler should be off on Power7.
7625     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7626     int cc        = $cmp$$cmpcode;
7627     __ isel($dst$$Register, $crx$$CondRegister,
7628             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7629   %}
7630   ins_pipe(pipe_class_default);
7631 %}
7632 
7633 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7634   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7635   predicate(!VM_Version::has_isel());
7636   ins_cost(DEFAULT_COST+BRANCH_COST);
7637 
7638   ins_variable_size_depending_on_alignment(true);
7639 
7640   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7641   // Worst case is branch + move + stop, no stop without scheduler
7642   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7643   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7644   ins_pipe(pipe_class_default);
7645 %}
7646 
7647 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7648   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7649   ins_cost(DEFAULT_COST+BRANCH_COST);
7650 
7651   ins_variable_size_depending_on_alignment(true);
7652 
7653   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7654   // Worst case is branch + move + stop, no stop without scheduler
7655   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7656   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7657   ins_pipe(pipe_class_default);
7658 %}
7659 
7660 // Cmove using isel.
7661 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7662   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7663   predicate(VM_Version::has_isel());
7664   ins_cost(DEFAULT_COST);
7665 
7666   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7667   size(4);
7668   ins_encode %{
7669     // This is a Power7 instruction for which no machine description
7670     // exists. Anyways, the scheduler should be off on Power7.
7671     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7672     int cc        = $cmp$$cmpcode;
7673     __ isel($dst$$Register, $crx$$CondRegister,
7674             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7675   %}
7676   ins_pipe(pipe_class_default);
7677 %}
7678 
7679 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7680   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7681   predicate(!VM_Version::has_isel());
7682   ins_cost(DEFAULT_COST+BRANCH_COST);
7683 
7684   ins_variable_size_depending_on_alignment(true);
7685 
7686   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7687   // Worst case is branch + move + stop, no stop without scheduler.
7688   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7689   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7690   ins_pipe(pipe_class_default);
7691 %}
7692 
7693 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7694   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7695   ins_cost(DEFAULT_COST+BRANCH_COST);
7696 
7697   ins_variable_size_depending_on_alignment(true);
7698 
7699   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7700   // Worst case is branch + move + stop, no stop without scheduler.
7701   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7702   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7703   ins_pipe(pipe_class_default);
7704 %}
7705 
7706 // Cmove using isel.
7707 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7708   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7709   predicate(VM_Version::has_isel());
7710   ins_cost(DEFAULT_COST);
7711 
7712   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7713   size(4);
7714   ins_encode %{
7715     // This is a Power7 instruction for which no machine description
7716     // exists. Anyways, the scheduler should be off on Power7.
7717     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7718     int cc        = $cmp$$cmpcode;
7719     __ isel($dst$$Register, $crx$$CondRegister,
7720             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7721   %}
7722   ins_pipe(pipe_class_default);
7723 %}
7724 
7725 // Conditional move for RegN. Only cmov(reg, reg).
7726 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7727   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7728   predicate(!VM_Version::has_isel());
7729   ins_cost(DEFAULT_COST+BRANCH_COST);
7730 
7731   ins_variable_size_depending_on_alignment(true);
7732 
7733   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7734   // Worst case is branch + move + stop, no stop without scheduler.
7735   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7736   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7737   ins_pipe(pipe_class_default);
7738 %}
7739 
7740 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7741   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7742   ins_cost(DEFAULT_COST+BRANCH_COST);
7743 
7744   ins_variable_size_depending_on_alignment(true);
7745 
7746   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7747   // Worst case is branch + move + stop, no stop without scheduler.
7748   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7749   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7750   ins_pipe(pipe_class_default);
7751 %}
7752 
7753 // Cmove using isel.
7754 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7755   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7756   predicate(VM_Version::has_isel());
7757   ins_cost(DEFAULT_COST);
7758 
7759   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7760   size(4);
7761   ins_encode %{
7762     // This is a Power7 instruction for which no machine description
7763     // exists. Anyways, the scheduler should be off on Power7.
7764     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7765     int cc        = $cmp$$cmpcode;
7766     __ isel($dst$$Register, $crx$$CondRegister,
7767             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7768   %}
7769   ins_pipe(pipe_class_default);
7770 %}
7771 
7772 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7773   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7774   predicate(!VM_Version::has_isel());
7775   ins_cost(DEFAULT_COST+BRANCH_COST);
7776 
7777   ins_variable_size_depending_on_alignment(true);
7778 
7779   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7780   // Worst case is branch + move + stop, no stop without scheduler.
7781   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7782   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7783   ins_pipe(pipe_class_default);
7784 %}
7785 
7786 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7787   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7788   ins_cost(DEFAULT_COST+BRANCH_COST);
7789 
7790   ins_variable_size_depending_on_alignment(true);
7791 
7792   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7793   // Worst case is branch + move + stop, no stop without scheduler.
7794   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7795   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7796   ins_pipe(pipe_class_default);
7797 %}
7798 
7799 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7800   match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7801   ins_cost(DEFAULT_COST+BRANCH_COST);
7802 
7803   ins_variable_size_depending_on_alignment(true);
7804 
7805   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7806   // Worst case is branch + move + stop, no stop without scheduler.
7807   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7808   ins_encode %{
7809     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7810     Label done;
7811     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7812     // Branch if not (cmp crx).
7813     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7814     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7815     // TODO PPC port __ endgroup_if_needed(_size == 12);
7816     __ bind(done);
7817   %}
7818   ins_pipe(pipe_class_default);
7819 %}
7820 
7821 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7822   match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7823   ins_cost(DEFAULT_COST+BRANCH_COST);
7824 
7825   ins_variable_size_depending_on_alignment(true);
7826 
7827   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7828   // Worst case is branch + move + stop, no stop without scheduler.
7829   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7830   ins_encode %{
7831     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7832     Label done;
7833     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7834     // Branch if not (cmp crx).
7835     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7836     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7837     // TODO PPC port __ endgroup_if_needed(_size == 12);
7838     __ bind(done);
7839   %}
7840   ins_pipe(pipe_class_default);
7841 %}
7842 
7843 //----------Conditional_store--------------------------------------------------
7844 // Conditional-store of the updated heap-top.
7845 // Used during allocation of the shared heap.
7846 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7847 
7848 // As compareAndSwapL, but return flag register instead of boolean value in
7849 // int register.
7850 // Used by sun/misc/AtomicLongCSImpl.java.
7851 // Mem_ptr must be a memory operand, else this node does not get
7852 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7853 // can be rematerialized which leads to errors.
7854 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7855   match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7856   effect(TEMP cr0);
7857   format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7858   ins_encode %{
7859     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7860     __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7861                 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7862                 noreg, NULL, true);
7863   %}
7864   ins_pipe(pipe_class_default);
7865 %}
7866 
7867 // As compareAndSwapP, but return flag register instead of boolean value in
7868 // int register.
7869 // This instruction is matched if UseTLAB is off.
7870 // Mem_ptr must be a memory operand, else this node does not get
7871 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7872 // can be rematerialized which leads to errors.
7873 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7874   match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7875   ins_cost(2*MEMORY_REF_COST);
7876 
7877   format %{ "STDCX_  if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7878   ins_encode %{
7879     // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7880     __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7881   %}
7882   ins_pipe(pipe_class_memory);
7883 %}
7884 
7885 // Implement LoadPLocked. Must be ordered against changes of the memory location
7886 // by storePConditional.
7887 // Don't know whether this is ever used.
7888 instruct loadPLocked(iRegPdst dst, memory mem) %{
7889   match(Set dst (LoadPLocked mem));
7890   ins_cost(2*MEMORY_REF_COST);
7891 
7892   format %{ "LDARX   $dst, $mem \t// loadPLocked\n\t" %}
7893   size(4);
7894   ins_encode %{
7895     // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7896     __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7897   %}
7898   ins_pipe(pipe_class_memory);
7899 %}
7900 
7901 //----------Compare-And-Swap---------------------------------------------------
7902 
7903 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7904 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))"  cannot be
7905 // matched.
7906 
7907 // Strong versions:
7908 
7909 instruct compareAndSwapB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7910   match(Set res (CompareAndSwapB mem_ptr (Binary src1 src2)));
7911   predicate(VM_Version::has_lqarx());
7912   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7913   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7914   ins_encode %{
7915     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7916     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7917     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7918                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7919                 $res$$Register, true);
7920     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7921       __ isync();
7922     } else {
7923       __ sync();
7924     }
7925   %}
7926   ins_pipe(pipe_class_default);
7927 %}
7928 
7929 instruct compareAndSwapB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7930   match(Set res (CompareAndSwapB mem_ptr (Binary src1 src2)));
7931   predicate(!VM_Version::has_lqarx());
7932   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7933   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7934   ins_encode %{
7935     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7936     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7937     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7938                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7939                 $res$$Register, true);
7940     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7941       __ isync();
7942     } else {
7943       __ sync();
7944     }
7945   %}
7946   ins_pipe(pipe_class_default);
7947 %}
7948 
7949 instruct compareAndSwapS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7950   match(Set res (CompareAndSwapS mem_ptr (Binary src1 src2)));
7951   predicate(VM_Version::has_lqarx());
7952   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7953   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7954   ins_encode %{
7955     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7956     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7957     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7958                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7959                 $res$$Register, true);
7960     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7961       __ isync();
7962     } else {
7963       __ sync();
7964     }
7965   %}
7966   ins_pipe(pipe_class_default);
7967 %}
7968 
7969 instruct compareAndSwapS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7970   match(Set res (CompareAndSwapS mem_ptr (Binary src1 src2)));
7971   predicate(!VM_Version::has_lqarx());
7972   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7973   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7974   ins_encode %{
7975     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7976     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7977     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7978                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7979                 $res$$Register, true);
7980     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7981       __ isync();
7982     } else {
7983       __ sync();
7984     }
7985   %}
7986   ins_pipe(pipe_class_default);
7987 %}
7988 
7989 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7990   match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7991   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7992   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7993   ins_encode %{
7994     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7995     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7996     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7997                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7998                 $res$$Register, true);
7999     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8000       __ isync();
8001     } else {
8002       __ sync();
8003     }
8004   %}
8005   ins_pipe(pipe_class_default);
8006 %}
8007 
8008 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8009   match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
8010   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8011   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
8012   ins_encode %{
8013     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8014     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8015     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8016                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8017                 $res$$Register, true);
8018     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8019       __ isync();
8020     } else {
8021       __ sync();
8022     }
8023   %}
8024   ins_pipe(pipe_class_default);
8025 %}
8026 
8027 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8028   match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
8029   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8030   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
8031   ins_encode %{
8032     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8033     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8034     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8035                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8036                 $res$$Register, NULL, true);
8037     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8038       __ isync();
8039     } else {
8040       __ sync();
8041     }
8042   %}
8043   ins_pipe(pipe_class_default);
8044 %}
8045 
8046 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8047   match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
8048   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8049   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
8050   ins_encode %{
8051     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8052     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8053     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8054                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8055                 $res$$Register, NULL, true);
8056     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8057       __ isync();
8058     } else {
8059       __ sync();
8060     }
8061   %}
8062   ins_pipe(pipe_class_default);
8063 %}
8064 
8065 // Weak versions:
8066 
8067 instruct weakCompareAndSwapB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8068   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
8069   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
8070   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8071   format %{ "weak CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
8072   ins_encode %{
8073     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8074     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8075     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
8076                 MacroAssembler::MemBarNone,
8077                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8078   %}
8079   ins_pipe(pipe_class_default);
8080 %}
8081 
8082 instruct weakCompareAndSwapB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
8083   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
8084   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
8085   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
8086   format %{ "weak CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
8087   ins_encode %{
8088     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8089     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8090     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
8091                 MacroAssembler::MemBarNone,
8092                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8093   %}
8094   ins_pipe(pipe_class_default);
8095 %}
8096 
8097 instruct weakCompareAndSwapB_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8098   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
8099   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
8100   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8101   format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
8102   ins_encode %{
8103     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8104     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8105     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
8106                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
8107                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8108   %}
8109   ins_pipe(pipe_class_default);
8110 %}
8111 
8112 instruct weakCompareAndSwapB4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
8113   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
8114   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
8115   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
8116   format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
8117   ins_encode %{
8118     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8119     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8120     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
8121                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
8122                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8123   %}
8124   ins_pipe(pipe_class_default);
8125 %}
8126 
8127 instruct weakCompareAndSwapS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8128   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
8129   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
8130   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8131   format %{ "weak CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
8132   ins_encode %{
8133     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8134     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8135     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
8136                 MacroAssembler::MemBarNone,
8137                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8138   %}
8139   ins_pipe(pipe_class_default);
8140 %}
8141 
8142 instruct weakCompareAndSwapS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
8143   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
8144   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
8145   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
8146   format %{ "weak CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
8147   ins_encode %{
8148     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8149     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8150     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
8151                 MacroAssembler::MemBarNone,
8152                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8153   %}
8154   ins_pipe(pipe_class_default);
8155 %}
8156 
8157 instruct weakCompareAndSwapS_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8158   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
8159   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
8160   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8161   format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
8162   ins_encode %{
8163     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8164     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8165     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
8166                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
8167                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8168   %}
8169   ins_pipe(pipe_class_default);
8170 %}
8171 
8172 instruct weakCompareAndSwapS4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
8173   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
8174   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
8175   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
8176   format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
8177   ins_encode %{
8178     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8179     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8180     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
8181                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
8182                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8183   %}
8184   ins_pipe(pipe_class_default);
8185 %}
8186 
8187 instruct weakCompareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8188   match(Set res (WeakCompareAndSwapI mem_ptr (Binary src1 src2)));
8189   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8190   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8191   format %{ "weak CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
8192   ins_encode %{
8193     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8194     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8195     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8196                 MacroAssembler::MemBarNone,
8197                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8198   %}
8199   ins_pipe(pipe_class_default);
8200 %}
8201 
8202 instruct weakCompareAndSwapI_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8203   match(Set res (WeakCompareAndSwapI mem_ptr (Binary src1 src2)));
8204   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8205   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8206   format %{ "weak CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as bool" %}
8207   ins_encode %{
8208     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8209     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8210     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
8211     // value is never passed to caller.
8212     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8213                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
8214                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8215   %}
8216   ins_pipe(pipe_class_default);
8217 %}
8218 
8219 instruct weakCompareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8220   match(Set res (WeakCompareAndSwapN mem_ptr (Binary src1 src2)));
8221   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8222   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8223   format %{ "weak CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
8224   ins_encode %{
8225     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8226     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8227     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8228                 MacroAssembler::MemBarNone,
8229                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8230   %}
8231   ins_pipe(pipe_class_default);
8232 %}
8233 
8234 instruct weakCompareAndSwapN_acq_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8235   match(Set res (WeakCompareAndSwapN mem_ptr (Binary src1 src2)));
8236   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8237   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8238   format %{ "weak CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as bool" %}
8239   ins_encode %{
8240     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8241     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8242     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
8243     // value is never passed to caller.
8244     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8245                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
8246                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
8247   %}
8248   ins_pipe(pipe_class_default);
8249 %}
8250 
8251 instruct weakCompareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8252   match(Set res (WeakCompareAndSwapL mem_ptr (Binary src1 src2)));
8253   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8254   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8255   format %{ "weak CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
8256   ins_encode %{
8257     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8258     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8259     // value is never passed to caller.
8260     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8261                 MacroAssembler::MemBarNone,
8262                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
8263   %}
8264   ins_pipe(pipe_class_default);
8265 %}
8266 
8267 instruct weakCompareAndSwapL_acq_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8268   match(Set res (WeakCompareAndSwapL mem_ptr (Binary src1 src2)));
8269   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8270   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8271   format %{ "weak CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as bool" %}
8272   ins_encode %{
8273     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8274     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8275     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
8276     // value is never passed to caller.
8277     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8278                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
8279                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
8280   %}
8281   ins_pipe(pipe_class_default);
8282 %}
8283 
8284 instruct weakCompareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8285   match(Set res (WeakCompareAndSwapP mem_ptr (Binary src1 src2)));
8286   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8287   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8288   format %{ "weak CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
8289   ins_encode %{
8290     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8291     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8292     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8293                 MacroAssembler::MemBarNone,
8294                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
8295   %}
8296   ins_pipe(pipe_class_default);
8297 %}
8298 
8299 instruct weakCompareAndSwapP_acq_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8300   match(Set res (WeakCompareAndSwapP mem_ptr (Binary src1 src2)));
8301   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8302   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
8303   format %{ "weak CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
8304   ins_encode %{
8305     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8306     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8307     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
8308     // value is never passed to caller.
8309     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8310                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
8311                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
8312   %}
8313   ins_pipe(pipe_class_default);
8314 %}
8315 
8316 // CompareAndExchange
8317 
8318 instruct compareAndExchangeB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8319   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
8320   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
8321   effect(TEMP_DEF res, TEMP cr0);
8322   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as int" %}
8323   ins_encode %{
8324     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8325     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8326     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
8327                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8328                 noreg, true);
8329   %}
8330   ins_pipe(pipe_class_default);
8331 %}
8332 
8333 instruct compareAndExchangeB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
8334   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
8335   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
8336   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
8337   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as int" %}
8338   ins_encode %{
8339     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8340     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8341     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
8342                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8343                 noreg, true);
8344   %}
8345   ins_pipe(pipe_class_default);
8346 %}
8347 
8348 instruct compareAndExchangeB_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8349   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
8350   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
8351   effect(TEMP_DEF res, TEMP cr0);
8352   format %{ "CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as int" %}
8353   ins_encode %{
8354     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8355     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8356     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
8357                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8358                 noreg, true);
8359     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8360       __ isync();
8361     } else {
8362       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8363       __ sync();
8364     }
8365   %}
8366   ins_pipe(pipe_class_default);
8367 %}
8368 
8369 instruct compareAndExchangeB4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
8370   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
8371   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
8372   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
8373   format %{ "CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as int" %}
8374   ins_encode %{
8375     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8376     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8377     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
8378                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8379                 noreg, true);
8380     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8381       __ isync();
8382     } else {
8383       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8384       __ sync();
8385     }
8386   %}
8387   ins_pipe(pipe_class_default);
8388 %}
8389 
8390 instruct compareAndExchangeS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8391   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
8392   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
8393   effect(TEMP_DEF res, TEMP cr0);
8394   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as int" %}
8395   ins_encode %{
8396     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8397     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8398     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
8399                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8400                 noreg, true);
8401   %}
8402   ins_pipe(pipe_class_default);
8403 %}
8404 
8405 instruct compareAndExchangeS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
8406   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
8407   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
8408   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
8409   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as int" %}
8410   ins_encode %{
8411     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8412     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8413     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
8414                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8415                 noreg, true);
8416   %}
8417   ins_pipe(pipe_class_default);
8418 %}
8419 
8420 instruct compareAndExchangeS_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8421   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
8422   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
8423   effect(TEMP_DEF res, TEMP cr0);
8424   format %{ "CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as int" %}
8425   ins_encode %{
8426     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8427     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8428     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
8429                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8430                 noreg, true);
8431     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8432       __ isync();
8433     } else {
8434       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8435       __ sync();
8436     }
8437   %}
8438   ins_pipe(pipe_class_default);
8439 %}
8440 
8441 instruct compareAndExchangeS4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
8442   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
8443   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
8444   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
8445   format %{ "CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as int" %}
8446   ins_encode %{
8447     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8448     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8449     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
8450                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8451                 noreg, true);
8452     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8453       __ isync();
8454     } else {
8455       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8456       __ sync();
8457     }
8458   %}
8459   ins_pipe(pipe_class_default);
8460 %}
8461 
8462 instruct compareAndExchangeI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8463   match(Set res (CompareAndExchangeI mem_ptr (Binary src1 src2)));
8464   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8465   effect(TEMP_DEF res, TEMP cr0);
8466   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as int" %}
8467   ins_encode %{
8468     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8469     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8470     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8471                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8472                 noreg, true);
8473   %}
8474   ins_pipe(pipe_class_default);
8475 %}
8476 
8477 instruct compareAndExchangeI_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8478   match(Set res (CompareAndExchangeI mem_ptr (Binary src1 src2)));
8479   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8480   effect(TEMP_DEF res, TEMP cr0);
8481   format %{ "CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as int" %}
8482   ins_encode %{
8483     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8484     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8485     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8486                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8487                 noreg, true);
8488     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8489       __ isync();
8490     } else {
8491       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8492       __ sync();
8493     }
8494   %}
8495   ins_pipe(pipe_class_default);
8496 %}
8497 
8498 instruct compareAndExchangeN_regP_regN_regN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8499   match(Set res (CompareAndExchangeN mem_ptr (Binary src1 src2)));
8500   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8501   effect(TEMP_DEF res, TEMP cr0);
8502   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as narrow oop" %}
8503   ins_encode %{
8504     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8505     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8506     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8507                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8508                 noreg, true);
8509   %}
8510   ins_pipe(pipe_class_default);
8511 %}
8512 
8513 instruct compareAndExchangeN_acq_regP_regN_regN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8514   match(Set res (CompareAndExchangeN mem_ptr (Binary src1 src2)));
8515   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8516   effect(TEMP_DEF res, TEMP cr0);
8517   format %{ "CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as narrow oop" %}
8518   ins_encode %{
8519     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8520     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8521     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8522                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8523                 noreg, true);
8524     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8525       __ isync();
8526     } else {
8527       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8528       __ sync();
8529     }
8530   %}
8531   ins_pipe(pipe_class_default);
8532 %}
8533 
8534 instruct compareAndExchangeL_regP_regL_regL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8535   match(Set res (CompareAndExchangeL mem_ptr (Binary src1 src2)));
8536   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8537   effect(TEMP_DEF res, TEMP cr0);
8538   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as long" %}
8539   ins_encode %{
8540     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8541     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8542     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8543                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8544                 noreg, NULL, true);
8545   %}
8546   ins_pipe(pipe_class_default);
8547 %}
8548 
8549 instruct compareAndExchangeL_acq_regP_regL_regL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8550   match(Set res (CompareAndExchangeL mem_ptr (Binary src1 src2)));
8551   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8552   effect(TEMP_DEF res, TEMP cr0);
8553   format %{ "CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as long" %}
8554   ins_encode %{
8555     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8556     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8557     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8558                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8559                 noreg, NULL, true);
8560     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8561       __ isync();
8562     } else {
8563       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8564       __ sync();
8565     }
8566   %}
8567   ins_pipe(pipe_class_default);
8568 %}
8569 
8570 instruct compareAndExchangeP_regP_regP_regP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8571   match(Set res (CompareAndExchangeP mem_ptr (Binary src1 src2)));
8572   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8573   effect(TEMP_DEF res, TEMP cr0);
8574   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as ptr; ptr" %}
8575   ins_encode %{
8576     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8577     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8578     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8579                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8580                 noreg, NULL, true);
8581   %}
8582   ins_pipe(pipe_class_default);
8583 %}
8584 
8585 instruct compareAndExchangeP_acq_regP_regP_regP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8586   match(Set res (CompareAndExchangeP mem_ptr (Binary src1 src2)));
8587   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8588   effect(TEMP_DEF res, TEMP cr0);
8589   format %{ "CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as ptr; ptr" %}
8590   ins_encode %{
8591     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8592     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8593     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8594                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8595                 noreg, NULL, true);
8596     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8597       __ isync();
8598     } else {
8599       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8600       __ sync();
8601     }
8602   %}
8603   ins_pipe(pipe_class_default);
8604 %}
8605 
8606 // Special RMW
8607 
8608 instruct getAndAddB(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8609   match(Set res (GetAndAddB mem_ptr src));
8610   predicate(VM_Version::has_lqarx());
8611   effect(TEMP_DEF res, TEMP cr0);
8612   format %{ "GetAndAddB $res, $mem_ptr, $src" %}
8613   ins_encode %{
8614     __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
8615                   R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8616     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8617       __ isync();
8618     } else {
8619       __ sync();
8620     }
8621   %}
8622   ins_pipe(pipe_class_default);
8623 %}
8624 
8625 instruct getAndAddB4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8626   match(Set res (GetAndAddB mem_ptr src));
8627   predicate(!VM_Version::has_lqarx());
8628   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8629   format %{ "GetAndAddB $res, $mem_ptr, $src" %}
8630   ins_encode %{
8631     __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
8632                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8633     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8634       __ isync();
8635     } else {
8636       __ sync();
8637     }
8638   %}
8639   ins_pipe(pipe_class_default);
8640 %}
8641 
8642 instruct getAndAddS(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8643   match(Set res (GetAndAddS mem_ptr src));
8644   predicate(VM_Version::has_lqarx());
8645   effect(TEMP_DEF res, TEMP cr0);
8646   format %{ "GetAndAddS $res, $mem_ptr, $src" %}
8647   ins_encode %{
8648     __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
8649                   R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8650     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8651       __ isync();
8652     } else {
8653       __ sync();
8654     }
8655   %}
8656   ins_pipe(pipe_class_default);
8657 %}
8658 
8659 instruct getAndAddS4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8660   match(Set res (GetAndAddS mem_ptr src));
8661   predicate(!VM_Version::has_lqarx());
8662   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8663   format %{ "GetAndAddS $res, $mem_ptr, $src" %}
8664   ins_encode %{
8665     __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
8666                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8667     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8668       __ isync();
8669     } else {
8670       __ sync();
8671     }
8672   %}
8673   ins_pipe(pipe_class_default);
8674 %}
8675 
8676 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8677   match(Set res (GetAndAddI mem_ptr src));
8678   effect(TEMP_DEF res, TEMP cr0);
8679   format %{ "GetAndAddI $res, $mem_ptr, $src" %}
8680   ins_encode %{
8681     __ getandaddw($res$$Register, $src$$Register, $mem_ptr$$Register,
8682                   R0, MacroAssembler::cmpxchgx_hint_atomic_update());
8683     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8684       __ isync();
8685     } else {
8686       __ sync();
8687     }
8688   %}
8689   ins_pipe(pipe_class_default);
8690 %}
8691 
8692 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
8693   match(Set res (GetAndAddL mem_ptr src));
8694   effect(TEMP_DEF res, TEMP cr0);
8695   format %{ "GetAndAddL $res, $mem_ptr, $src" %}
8696   ins_encode %{
8697     __ getandaddd($res$$Register, $src$$Register, $mem_ptr$$Register,
8698                   R0, MacroAssembler::cmpxchgx_hint_atomic_update());
8699     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8700       __ isync();
8701     } else {
8702       __ sync();
8703     }
8704   %}
8705   ins_pipe(pipe_class_default);
8706 %}
8707 
8708 instruct getAndSetB(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8709   match(Set res (GetAndSetB mem_ptr src));
8710   predicate(VM_Version::has_lqarx());
8711   effect(TEMP_DEF res, TEMP cr0);
8712   format %{ "GetAndSetB $res, $mem_ptr, $src" %}
8713   ins_encode %{
8714     __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
8715                   noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8716     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8717       __ isync();
8718     } else {
8719       __ sync();
8720     }
8721   %}
8722   ins_pipe(pipe_class_default);
8723 %}
8724 
8725 instruct getAndSetB4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8726   match(Set res (GetAndSetB mem_ptr src));
8727   predicate(!VM_Version::has_lqarx());
8728   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8729   format %{ "GetAndSetB $res, $mem_ptr, $src" %}
8730   ins_encode %{
8731     __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
8732                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8733     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8734       __ isync();
8735     } else {
8736       __ sync();
8737     }
8738   %}
8739   ins_pipe(pipe_class_default);
8740 %}
8741 
8742 instruct getAndSetS(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8743   match(Set res (GetAndSetS mem_ptr src));
8744   predicate(VM_Version::has_lqarx());
8745   effect(TEMP_DEF res, TEMP cr0);
8746   format %{ "GetAndSetS $res, $mem_ptr, $src" %}
8747   ins_encode %{
8748     __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
8749                   noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8750     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8751       __ isync();
8752     } else {
8753       __ sync();
8754     }
8755   %}
8756   ins_pipe(pipe_class_default);
8757 %}
8758 
8759 instruct getAndSetS4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8760   match(Set res (GetAndSetS mem_ptr src));
8761   predicate(!VM_Version::has_lqarx());
8762   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8763   format %{ "GetAndSetS $res, $mem_ptr, $src" %}
8764   ins_encode %{
8765     __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
8766                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8767     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8768       __ isync();
8769     } else {
8770       __ sync();
8771     }
8772   %}
8773   ins_pipe(pipe_class_default);
8774 %}
8775 
8776 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8777   match(Set res (GetAndSetI mem_ptr src));
8778   effect(TEMP_DEF res, TEMP cr0);
8779   format %{ "GetAndSetI $res, $mem_ptr, $src" %}
8780   ins_encode %{
8781     __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
8782                   MacroAssembler::cmpxchgx_hint_atomic_update());
8783     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8784       __ isync();
8785     } else {
8786       __ sync();
8787     }
8788   %}
8789   ins_pipe(pipe_class_default);
8790 %}
8791 
8792 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
8793   match(Set res (GetAndSetL mem_ptr src));
8794   effect(TEMP_DEF res, TEMP cr0);
8795   format %{ "GetAndSetL $res, $mem_ptr, $src" %}
8796   ins_encode %{
8797     __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
8798                   MacroAssembler::cmpxchgx_hint_atomic_update());
8799     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8800       __ isync();
8801     } else {
8802       __ sync();
8803     }
8804   %}
8805   ins_pipe(pipe_class_default);
8806 %}
8807 
8808 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
8809   match(Set res (GetAndSetP mem_ptr src));
8810   effect(TEMP_DEF res, TEMP cr0);
8811   format %{ "GetAndSetP $res, $mem_ptr, $src" %}
8812   ins_encode %{
8813     __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
8814                   MacroAssembler::cmpxchgx_hint_atomic_update());
8815     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8816       __ isync();
8817     } else {
8818       __ sync();
8819     }
8820   %}
8821   ins_pipe(pipe_class_default);
8822 %}
8823 
8824 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
8825   match(Set res (GetAndSetN mem_ptr src));
8826   effect(TEMP_DEF res, TEMP cr0);
8827   format %{ "GetAndSetN $res, $mem_ptr, $src" %}
8828   ins_encode %{
8829     __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
8830                   MacroAssembler::cmpxchgx_hint_atomic_update());
8831     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8832       __ isync();
8833     } else {
8834       __ sync();
8835     }
8836   %}
8837   ins_pipe(pipe_class_default);
8838 %}
8839 
8840 //----------Arithmetic Instructions--------------------------------------------
8841 // Addition Instructions
8842 
8843 // Register Addition
8844 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
8845   match(Set dst (AddI src1 src2));
8846   format %{ "ADD     $dst, $src1, $src2" %}
8847   size(4);
8848   ins_encode %{
8849     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8850     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8851   %}
8852   ins_pipe(pipe_class_default);
8853 %}
8854 
8855 // Expand does not work with above instruct. (??)
8856 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8857   // no match-rule
8858   effect(DEF dst, USE src1, USE src2);
8859   format %{ "ADD     $dst, $src1, $src2" %}
8860   size(4);
8861   ins_encode %{
8862     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8863     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8864   %}
8865   ins_pipe(pipe_class_default);
8866 %}
8867 
8868 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8869   match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
8870   ins_cost(DEFAULT_COST*3);
8871 
8872   expand %{
8873     // FIXME: we should do this in the ideal world.
8874     iRegIdst tmp1;
8875     iRegIdst tmp2;
8876     addI_reg_reg(tmp1, src1, src2);
8877     addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
8878     addI_reg_reg(dst, tmp1, tmp2);
8879   %}
8880 %}
8881 
8882 // Immediate Addition
8883 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8884   match(Set dst (AddI src1 src2));
8885   format %{ "ADDI    $dst, $src1, $src2" %}
8886   size(4);
8887   ins_encode %{
8888     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8889     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
8890   %}
8891   ins_pipe(pipe_class_default);
8892 %}
8893 
8894 // Immediate Addition with 16-bit shifted operand
8895 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
8896   match(Set dst (AddI src1 src2));
8897   format %{ "ADDIS   $dst, $src1, $src2" %}
8898   size(4);
8899   ins_encode %{
8900     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
8901     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
8902   %}
8903   ins_pipe(pipe_class_default);
8904 %}
8905 
8906 // Long Addition
8907 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8908   match(Set dst (AddL src1 src2));
8909   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
8910   size(4);
8911   ins_encode %{
8912     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8913     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8914   %}
8915   ins_pipe(pipe_class_default);
8916 %}
8917 
8918 // Expand does not work with above instruct. (??)
8919 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8920   // no match-rule
8921   effect(DEF dst, USE src1, USE src2);
8922   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
8923   size(4);
8924   ins_encode %{
8925     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8926     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8927   %}
8928   ins_pipe(pipe_class_default);
8929 %}
8930 
8931 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
8932   match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
8933   ins_cost(DEFAULT_COST*3);
8934 
8935   expand %{
8936     // FIXME: we should do this in the ideal world.
8937     iRegLdst tmp1;
8938     iRegLdst tmp2;
8939     addL_reg_reg(tmp1, src1, src2);
8940     addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
8941     addL_reg_reg(dst, tmp1, tmp2);
8942   %}
8943 %}
8944 
8945 // AddL + ConvL2I.
8946 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8947   match(Set dst (ConvL2I (AddL src1 src2)));
8948 
8949   format %{ "ADD     $dst, $src1, $src2 \t// long + l2i" %}
8950   size(4);
8951   ins_encode %{
8952     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8953     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8954   %}
8955   ins_pipe(pipe_class_default);
8956 %}
8957 
8958 // No constant pool entries required.
8959 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8960   match(Set dst (AddL src1 src2));
8961 
8962   format %{ "ADDI    $dst, $src1, $src2" %}
8963   size(4);
8964   ins_encode %{
8965     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8966     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
8967   %}
8968   ins_pipe(pipe_class_default);
8969 %}
8970 
8971 // Long Immediate Addition with 16-bit shifted operand.
8972 // No constant pool entries required.
8973 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
8974   match(Set dst (AddL src1 src2));
8975 
8976   format %{ "ADDIS   $dst, $src1, $src2" %}
8977   size(4);
8978   ins_encode %{
8979     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
8980     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
8981   %}
8982   ins_pipe(pipe_class_default);
8983 %}
8984 
8985 // Pointer Register Addition
8986 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
8987   match(Set dst (AddP src1 src2));
8988   format %{ "ADD     $dst, $src1, $src2" %}
8989   size(4);
8990   ins_encode %{
8991     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8992     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8993   %}
8994   ins_pipe(pipe_class_default);
8995 %}
8996 
8997 // Pointer Immediate Addition
8998 // No constant pool entries required.
8999 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
9000   match(Set dst (AddP src1 src2));
9001 
9002   format %{ "ADDI    $dst, $src1, $src2" %}
9003   size(4);
9004   ins_encode %{
9005     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
9006     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
9007   %}
9008   ins_pipe(pipe_class_default);
9009 %}
9010 
9011 // Pointer Immediate Addition with 16-bit shifted operand.
9012 // No constant pool entries required.
9013 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
9014   match(Set dst (AddP src1 src2));
9015 
9016   format %{ "ADDIS   $dst, $src1, $src2" %}
9017   size(4);
9018   ins_encode %{
9019     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
9020     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
9021   %}
9022   ins_pipe(pipe_class_default);
9023 %}
9024 
9025 //---------------------
9026 // Subtraction Instructions
9027 
9028 // Register Subtraction
9029 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9030   match(Set dst (SubI src1 src2));
9031   format %{ "SUBF    $dst, $src2, $src1" %}
9032   size(4);
9033   ins_encode %{
9034     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
9035     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
9036   %}
9037   ins_pipe(pipe_class_default);
9038 %}
9039 
9040 // Immediate Subtraction
9041 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
9042 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
9043 
9044 // SubI from constant (using subfic).
9045 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
9046   match(Set dst (SubI src1 src2));
9047   format %{ "SUBI    $dst, $src1, $src2" %}
9048 
9049   size(4);
9050   ins_encode %{
9051     // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
9052     __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
9053   %}
9054   ins_pipe(pipe_class_default);
9055 %}
9056 
9057 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
9058 // positive integers and 0xF...F for negative ones.
9059 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
9060   // no match-rule, false predicate
9061   effect(DEF dst, USE src);
9062   predicate(false);
9063 
9064   format %{ "SRAWI   $dst, $src, #31" %}
9065   size(4);
9066   ins_encode %{
9067     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9068     __ srawi($dst$$Register, $src$$Register, 0x1f);
9069   %}
9070   ins_pipe(pipe_class_default);
9071 %}
9072 
9073 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
9074   match(Set dst (AbsI src));
9075   ins_cost(DEFAULT_COST*3);
9076 
9077   expand %{
9078     iRegIdst tmp1;
9079     iRegIdst tmp2;
9080     signmask32I_regI(tmp1, src);
9081     xorI_reg_reg(tmp2, tmp1, src);
9082     subI_reg_reg(dst, tmp2, tmp1);
9083   %}
9084 %}
9085 
9086 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
9087   match(Set dst (SubI zero src2));
9088   format %{ "NEG     $dst, $src2" %}
9089   size(4);
9090   ins_encode %{
9091     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
9092     __ neg($dst$$Register, $src2$$Register);
9093   %}
9094   ins_pipe(pipe_class_default);
9095 %}
9096 
9097 // Long subtraction
9098 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9099   match(Set dst (SubL src1 src2));
9100   format %{ "SUBF    $dst, $src2, $src1 \t// long" %}
9101   size(4);
9102   ins_encode %{
9103     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
9104     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
9105   %}
9106   ins_pipe(pipe_class_default);
9107 %}
9108 
9109 // SubL + convL2I.
9110 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9111   match(Set dst (ConvL2I (SubL src1 src2)));
9112 
9113   format %{ "SUBF    $dst, $src2, $src1 \t// long + l2i" %}
9114   size(4);
9115   ins_encode %{
9116     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
9117     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
9118   %}
9119   ins_pipe(pipe_class_default);
9120 %}
9121 
9122 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
9123 // positive longs and 0xF...F for negative ones.
9124 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
9125   // no match-rule, false predicate
9126   effect(DEF dst, USE src);
9127   predicate(false);
9128 
9129   format %{ "SRADI   $dst, $src, #63" %}
9130   size(4);
9131   ins_encode %{
9132     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
9133     __ sradi($dst$$Register, $src$$Register, 0x3f);
9134   %}
9135   ins_pipe(pipe_class_default);
9136 %}
9137 
9138 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
9139 // positive longs and 0xF...F for negative ones.
9140 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
9141   // no match-rule, false predicate
9142   effect(DEF dst, USE src);
9143   predicate(false);
9144 
9145   format %{ "SRADI   $dst, $src, #63" %}
9146   size(4);
9147   ins_encode %{
9148     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
9149     __ sradi($dst$$Register, $src$$Register, 0x3f);
9150   %}
9151   ins_pipe(pipe_class_default);
9152 %}
9153 
9154 // Long negation
9155 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
9156   match(Set dst (SubL zero src2));
9157   format %{ "NEG     $dst, $src2 \t// long" %}
9158   size(4);
9159   ins_encode %{
9160     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
9161     __ neg($dst$$Register, $src2$$Register);
9162   %}
9163   ins_pipe(pipe_class_default);
9164 %}
9165 
9166 // NegL + ConvL2I.
9167 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
9168   match(Set dst (ConvL2I (SubL zero src2)));
9169 
9170   format %{ "NEG     $dst, $src2 \t// long + l2i" %}
9171   size(4);
9172   ins_encode %{
9173     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
9174     __ neg($dst$$Register, $src2$$Register);
9175   %}
9176   ins_pipe(pipe_class_default);
9177 %}
9178 
9179 // Multiplication Instructions
9180 // Integer Multiplication
9181 
9182 // Register Multiplication
9183 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9184   match(Set dst (MulI src1 src2));
9185   ins_cost(DEFAULT_COST);
9186 
9187   format %{ "MULLW   $dst, $src1, $src2" %}
9188   size(4);
9189   ins_encode %{
9190     // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
9191     __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
9192   %}
9193   ins_pipe(pipe_class_default);
9194 %}
9195 
9196 // Immediate Multiplication
9197 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
9198   match(Set dst (MulI src1 src2));
9199   ins_cost(DEFAULT_COST);
9200 
9201   format %{ "MULLI   $dst, $src1, $src2" %}
9202   size(4);
9203   ins_encode %{
9204     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
9205     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
9206   %}
9207   ins_pipe(pipe_class_default);
9208 %}
9209 
9210 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9211   match(Set dst (MulL src1 src2));
9212   ins_cost(DEFAULT_COST);
9213 
9214   format %{ "MULLD   $dst $src1, $src2 \t// long" %}
9215   size(4);
9216   ins_encode %{
9217     // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
9218     __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
9219   %}
9220   ins_pipe(pipe_class_default);
9221 %}
9222 
9223 // Multiply high for optimized long division by constant.
9224 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9225   match(Set dst (MulHiL src1 src2));
9226   ins_cost(DEFAULT_COST);
9227 
9228   format %{ "MULHD   $dst $src1, $src2 \t// long" %}
9229   size(4);
9230   ins_encode %{
9231     // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
9232     __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
9233   %}
9234   ins_pipe(pipe_class_default);
9235 %}
9236 
9237 // Immediate Multiplication
9238 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
9239   match(Set dst (MulL src1 src2));
9240   ins_cost(DEFAULT_COST);
9241 
9242   format %{ "MULLI   $dst, $src1, $src2" %}
9243   size(4);
9244   ins_encode %{
9245     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
9246     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
9247   %}
9248   ins_pipe(pipe_class_default);
9249 %}
9250 
9251 // Integer Division with Immediate -1: Negate.
9252 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9253   match(Set dst (DivI src1 src2));
9254   ins_cost(DEFAULT_COST);
9255 
9256   format %{ "NEG     $dst, $src1 \t// /-1" %}
9257   size(4);
9258   ins_encode %{
9259     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
9260     __ neg($dst$$Register, $src1$$Register);
9261   %}
9262   ins_pipe(pipe_class_default);
9263 %}
9264 
9265 // Integer Division with constant, but not -1.
9266 // We should be able to improve this by checking the type of src2.
9267 // It might well be that src2 is known to be positive.
9268 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9269   match(Set dst (DivI src1 src2));
9270   predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
9271   ins_cost(2*DEFAULT_COST);
9272 
9273   format %{ "DIVW    $dst, $src1, $src2 \t// /not-1" %}
9274   size(4);
9275   ins_encode %{
9276     // TODO: PPC port $archOpcode(ppc64Opcode_divw);
9277     __ divw($dst$$Register, $src1$$Register, $src2$$Register);
9278   %}
9279   ins_pipe(pipe_class_default);
9280 %}
9281 
9282 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
9283   effect(USE_DEF dst, USE src1, USE crx);
9284   predicate(false);
9285 
9286   ins_variable_size_depending_on_alignment(true);
9287 
9288   format %{ "CMOVE   $dst, neg($src1), $crx" %}
9289   // Worst case is branch + move + stop, no stop without scheduler.
9290   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9291   ins_encode %{
9292     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
9293     Label done;
9294     __ bne($crx$$CondRegister, done);
9295     __ neg($dst$$Register, $src1$$Register);
9296     // TODO PPC port __ endgroup_if_needed(_size == 12);
9297     __ bind(done);
9298   %}
9299   ins_pipe(pipe_class_default);
9300 %}
9301 
9302 // Integer Division with Registers not containing constants.
9303 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9304   match(Set dst (DivI src1 src2));
9305   ins_cost(10*DEFAULT_COST);
9306 
9307   expand %{
9308     immI16 imm %{ (int)-1 %}
9309     flagsReg tmp1;
9310     cmpI_reg_imm16(tmp1, src2, imm);          // check src2 == -1
9311     divI_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
9312     cmovI_bne_negI_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
9313   %}
9314 %}
9315 
9316 // Long Division with Immediate -1: Negate.
9317 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9318   match(Set dst (DivL src1 src2));
9319   ins_cost(DEFAULT_COST);
9320 
9321   format %{ "NEG     $dst, $src1 \t// /-1, long" %}
9322   size(4);
9323   ins_encode %{
9324     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
9325     __ neg($dst$$Register, $src1$$Register);
9326   %}
9327   ins_pipe(pipe_class_default);
9328 %}
9329 
9330 // Long Division with constant, but not -1.
9331 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9332   match(Set dst (DivL src1 src2));
9333   predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
9334   ins_cost(2*DEFAULT_COST);
9335 
9336   format %{ "DIVD    $dst, $src1, $src2 \t// /not-1, long" %}
9337   size(4);
9338   ins_encode %{
9339     // TODO: PPC port $archOpcode(ppc64Opcode_divd);
9340     __ divd($dst$$Register, $src1$$Register, $src2$$Register);
9341   %}
9342   ins_pipe(pipe_class_default);
9343 %}
9344 
9345 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
9346   effect(USE_DEF dst, USE src1, USE crx);
9347   predicate(false);
9348 
9349   ins_variable_size_depending_on_alignment(true);
9350 
9351   format %{ "CMOVE   $dst, neg($src1), $crx" %}
9352   // Worst case is branch + move + stop, no stop without scheduler.
9353   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9354   ins_encode %{
9355     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
9356     Label done;
9357     __ bne($crx$$CondRegister, done);
9358     __ neg($dst$$Register, $src1$$Register);
9359     // TODO PPC port __ endgroup_if_needed(_size == 12);
9360     __ bind(done);
9361   %}
9362   ins_pipe(pipe_class_default);
9363 %}
9364 
9365 // Long Division with Registers not containing constants.
9366 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9367   match(Set dst (DivL src1 src2));
9368   ins_cost(10*DEFAULT_COST);
9369 
9370   expand %{
9371     immL16 imm %{ (int)-1 %}
9372     flagsReg tmp1;
9373     cmpL_reg_imm16(tmp1, src2, imm);          // check src2 == -1
9374     divL_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
9375     cmovL_bne_negL_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
9376   %}
9377 %}
9378 
9379 // Integer Remainder with registers.
9380 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9381   match(Set dst (ModI src1 src2));
9382   ins_cost(10*DEFAULT_COST);
9383 
9384   expand %{
9385     immI16 imm %{ (int)-1 %}
9386     flagsReg tmp1;
9387     iRegIdst tmp2;
9388     iRegIdst tmp3;
9389     cmpI_reg_imm16(tmp1, src2, imm);           // check src2 == -1
9390     divI_reg_regnotMinus1(tmp2, src1, src2);   // tmp2 = src1 / src2
9391     cmovI_bne_negI_reg(tmp2, tmp1, src1);      // cmove tmp2 = neg(src1) if src2 == -1
9392     mulI_reg_reg(tmp3, src2, tmp2);            // tmp3 = src2 * tmp2
9393     subI_reg_reg(dst, src1, tmp3);             // dst = src1 - tmp3
9394   %}
9395 %}
9396 
9397 // Long Remainder with registers
9398 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9399   match(Set dst (ModL src1 src2));
9400   ins_cost(10*DEFAULT_COST);
9401 
9402   expand %{
9403     immL16 imm %{ (int)-1 %}
9404     flagsReg tmp1;
9405     iRegLdst tmp2;
9406     iRegLdst tmp3;
9407     cmpL_reg_imm16(tmp1, src2, imm);             // check src2 == -1
9408     divL_reg_regnotMinus1(tmp2, src1, src2);     // tmp2 = src1 / src2
9409     cmovL_bne_negL_reg(tmp2, tmp1, src1);        // cmove tmp2 = neg(src1) if src2 == -1
9410     mulL_reg_reg(tmp3, src2, tmp2);              // tmp3 = src2 * tmp2
9411     subL_reg_reg(dst, src1, tmp3);               // dst = src1 - tmp3
9412   %}
9413 %}
9414 
9415 // Integer Shift Instructions
9416 
9417 // Register Shift Left
9418 
9419 // Clear all but the lowest #mask bits.
9420 // Used to normalize shift amounts in registers.
9421 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
9422   // no match-rule, false predicate
9423   effect(DEF dst, USE src, USE mask);
9424   predicate(false);
9425 
9426   format %{ "MASK    $dst, $src, $mask \t// clear $mask upper bits" %}
9427   size(4);
9428   ins_encode %{
9429     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9430     __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
9431   %}
9432   ins_pipe(pipe_class_default);
9433 %}
9434 
9435 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9436   // no match-rule, false predicate
9437   effect(DEF dst, USE src1, USE src2);
9438   predicate(false);
9439 
9440   format %{ "SLW     $dst, $src1, $src2" %}
9441   size(4);
9442   ins_encode %{
9443     // TODO: PPC port $archOpcode(ppc64Opcode_slw);
9444     __ slw($dst$$Register, $src1$$Register, $src2$$Register);
9445   %}
9446   ins_pipe(pipe_class_default);
9447 %}
9448 
9449 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9450   match(Set dst (LShiftI src1 src2));
9451   ins_cost(DEFAULT_COST*2);
9452   expand %{
9453     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
9454     iRegIdst tmpI;
9455     maskI_reg_imm(tmpI, src2, mask);
9456     lShiftI_reg_reg(dst, src1, tmpI);
9457   %}
9458 %}
9459 
9460 // Register Shift Left Immediate
9461 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9462   match(Set dst (LShiftI src1 src2));
9463 
9464   format %{ "SLWI    $dst, $src1, ($src2 & 0x1f)" %}
9465   size(4);
9466   ins_encode %{
9467     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9468     __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9469   %}
9470   ins_pipe(pipe_class_default);
9471 %}
9472 
9473 // AndI with negpow2-constant + LShiftI
9474 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
9475   match(Set dst (LShiftI (AndI src1 src2) src3));
9476   predicate(UseRotateAndMaskInstructionsPPC64);
9477 
9478   format %{ "RLWINM  $dst, lShiftI(AndI($src1, $src2), $src3)" %}
9479   size(4);
9480   ins_encode %{
9481     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
9482     long src2      = $src2$$constant;
9483     long src3      = $src3$$constant;
9484     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
9485     if (maskbits >= 32) {
9486       __ li($dst$$Register, 0); // addi
9487     } else {
9488       __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
9489     }
9490   %}
9491   ins_pipe(pipe_class_default);
9492 %}
9493 
9494 // RShiftI + AndI with negpow2-constant + LShiftI
9495 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
9496   match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
9497   predicate(UseRotateAndMaskInstructionsPPC64);
9498 
9499   format %{ "RLWINM  $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
9500   size(4);
9501   ins_encode %{
9502     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
9503     long src2      = $src2$$constant;
9504     long src3      = $src3$$constant;
9505     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
9506     if (maskbits >= 32) {
9507       __ li($dst$$Register, 0); // addi
9508     } else {
9509       __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
9510     }
9511   %}
9512   ins_pipe(pipe_class_default);
9513 %}
9514 
9515 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9516   // no match-rule, false predicate
9517   effect(DEF dst, USE src1, USE src2);
9518   predicate(false);
9519 
9520   format %{ "SLD     $dst, $src1, $src2" %}
9521   size(4);
9522   ins_encode %{
9523     // TODO: PPC port $archOpcode(ppc64Opcode_sld);
9524     __ sld($dst$$Register, $src1$$Register, $src2$$Register);
9525   %}
9526   ins_pipe(pipe_class_default);
9527 %}
9528 
9529 // Register Shift Left
9530 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9531   match(Set dst (LShiftL src1 src2));
9532   ins_cost(DEFAULT_COST*2);
9533   expand %{
9534     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9535     iRegIdst tmpI;
9536     maskI_reg_imm(tmpI, src2, mask);
9537     lShiftL_regL_regI(dst, src1, tmpI);
9538   %}
9539 %}
9540 
9541 // Register Shift Left Immediate
9542 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9543   match(Set dst (LShiftL src1 src2));
9544   format %{ "SLDI    $dst, $src1, ($src2 & 0x3f)" %}
9545   size(4);
9546   ins_encode %{
9547     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9548     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9549   %}
9550   ins_pipe(pipe_class_default);
9551 %}
9552 
9553 // If we shift more than 32 bits, we need not convert I2L.
9554 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
9555   match(Set dst (LShiftL (ConvI2L src1) src2));
9556   ins_cost(DEFAULT_COST);
9557 
9558   size(4);
9559   format %{ "SLDI    $dst, i2l($src1), $src2" %}
9560   ins_encode %{
9561     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9562     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9563   %}
9564   ins_pipe(pipe_class_default);
9565 %}
9566 
9567 // Shift a postivie int to the left.
9568 // Clrlsldi clears the upper 32 bits and shifts.
9569 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
9570   match(Set dst (LShiftL (ConvI2L src1) src2));
9571   predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
9572 
9573   format %{ "SLDI    $dst, i2l(positive_int($src1)), $src2" %}
9574   size(4);
9575   ins_encode %{
9576     // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
9577     __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
9578   %}
9579   ins_pipe(pipe_class_default);
9580 %}
9581 
9582 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9583   // no match-rule, false predicate
9584   effect(DEF dst, USE src1, USE src2);
9585   predicate(false);
9586 
9587   format %{ "SRAW    $dst, $src1, $src2" %}
9588   size(4);
9589   ins_encode %{
9590     // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
9591     __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
9592   %}
9593   ins_pipe(pipe_class_default);
9594 %}
9595 
9596 // Register Arithmetic Shift Right
9597 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9598   match(Set dst (RShiftI src1 src2));
9599   ins_cost(DEFAULT_COST*2);
9600   expand %{
9601     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
9602     iRegIdst tmpI;
9603     maskI_reg_imm(tmpI, src2, mask);
9604     arShiftI_reg_reg(dst, src1, tmpI);
9605   %}
9606 %}
9607 
9608 // Register Arithmetic Shift Right Immediate
9609 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9610   match(Set dst (RShiftI src1 src2));
9611 
9612   format %{ "SRAWI   $dst, $src1, ($src2 & 0x1f)" %}
9613   size(4);
9614   ins_encode %{
9615     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9616     __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9617   %}
9618   ins_pipe(pipe_class_default);
9619 %}
9620 
9621 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9622   // no match-rule, false predicate
9623   effect(DEF dst, USE src1, USE src2);
9624   predicate(false);
9625 
9626   format %{ "SRAD    $dst, $src1, $src2" %}
9627   size(4);
9628   ins_encode %{
9629     // TODO: PPC port $archOpcode(ppc64Opcode_srad);
9630     __ srad($dst$$Register, $src1$$Register, $src2$$Register);
9631   %}
9632   ins_pipe(pipe_class_default);
9633 %}
9634 
9635 // Register Shift Right Arithmetic Long
9636 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9637   match(Set dst (RShiftL src1 src2));
9638   ins_cost(DEFAULT_COST*2);
9639 
9640   expand %{
9641     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9642     iRegIdst tmpI;
9643     maskI_reg_imm(tmpI, src2, mask);
9644     arShiftL_regL_regI(dst, src1, tmpI);
9645   %}
9646 %}
9647 
9648 // Register Shift Right Immediate
9649 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9650   match(Set dst (RShiftL src1 src2));
9651 
9652   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f)" %}
9653   size(4);
9654   ins_encode %{
9655     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
9656     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9657   %}
9658   ins_pipe(pipe_class_default);
9659 %}
9660 
9661 // RShiftL + ConvL2I
9662 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
9663   match(Set dst (ConvL2I (RShiftL src1 src2)));
9664 
9665   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
9666   size(4);
9667   ins_encode %{
9668     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
9669     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9670   %}
9671   ins_pipe(pipe_class_default);
9672 %}
9673 
9674 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9675   // no match-rule, false predicate
9676   effect(DEF dst, USE src1, USE src2);
9677   predicate(false);
9678 
9679   format %{ "SRW     $dst, $src1, $src2" %}
9680   size(4);
9681   ins_encode %{
9682     // TODO: PPC port $archOpcode(ppc64Opcode_srw);
9683     __ srw($dst$$Register, $src1$$Register, $src2$$Register);
9684   %}
9685   ins_pipe(pipe_class_default);
9686 %}
9687 
9688 // Register Shift Right
9689 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9690   match(Set dst (URShiftI src1 src2));
9691   ins_cost(DEFAULT_COST*2);
9692 
9693   expand %{
9694     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
9695     iRegIdst tmpI;
9696     maskI_reg_imm(tmpI, src2, mask);
9697     urShiftI_reg_reg(dst, src1, tmpI);
9698   %}
9699 %}
9700 
9701 // Register Shift Right Immediate
9702 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9703   match(Set dst (URShiftI src1 src2));
9704 
9705   format %{ "SRWI    $dst, $src1, ($src2 & 0x1f)" %}
9706   size(4);
9707   ins_encode %{
9708     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9709     __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9710   %}
9711   ins_pipe(pipe_class_default);
9712 %}
9713 
9714 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9715   // no match-rule, false predicate
9716   effect(DEF dst, USE src1, USE src2);
9717   predicate(false);
9718 
9719   format %{ "SRD     $dst, $src1, $src2" %}
9720   size(4);
9721   ins_encode %{
9722     // TODO: PPC port $archOpcode(ppc64Opcode_srd);
9723     __ srd($dst$$Register, $src1$$Register, $src2$$Register);
9724   %}
9725   ins_pipe(pipe_class_default);
9726 %}
9727 
9728 // Register Shift Right
9729 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9730   match(Set dst (URShiftL src1 src2));
9731   ins_cost(DEFAULT_COST*2);
9732 
9733   expand %{
9734     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9735     iRegIdst tmpI;
9736     maskI_reg_imm(tmpI, src2, mask);
9737     urShiftL_regL_regI(dst, src1, tmpI);
9738   %}
9739 %}
9740 
9741 // Register Shift Right Immediate
9742 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9743   match(Set dst (URShiftL src1 src2));
9744 
9745   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f)" %}
9746   size(4);
9747   ins_encode %{
9748     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9749     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9750   %}
9751   ins_pipe(pipe_class_default);
9752 %}
9753 
9754 // URShiftL + ConvL2I.
9755 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
9756   match(Set dst (ConvL2I (URShiftL src1 src2)));
9757 
9758   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
9759   size(4);
9760   ins_encode %{
9761     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9762     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9763   %}
9764   ins_pipe(pipe_class_default);
9765 %}
9766 
9767 // Register Shift Right Immediate with a CastP2X
9768 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
9769   match(Set dst (URShiftL (CastP2X src1) src2));
9770 
9771   format %{ "SRDI    $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
9772   size(4);
9773   ins_encode %{
9774     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9775     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9776   %}
9777   ins_pipe(pipe_class_default);
9778 %}
9779 
9780 // Bitfield Extract: URShiftI + AndI
9781 instruct andI_urShiftI_regI_immI_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immI src2, immIpow2minus1 src3) %{
9782   match(Set dst (AndI (URShiftI src1 src2) src3));
9783 
9784   format %{ "EXTRDI  $dst, $src1, shift=$src2, mask=$src3 \t// int bitfield extract" %}
9785   size(4);
9786   ins_encode %{
9787     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9788     int rshift = ($src2$$constant) & 0x1f;
9789     int length = log2_long(((jlong) $src3$$constant) + 1);
9790     if (rshift + length > 32) {
9791       // if necessary, adjust mask to omit rotated bits.
9792       length = 32 - rshift;
9793     }
9794     __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
9795   %}
9796   ins_pipe(pipe_class_default);
9797 %}
9798 
9799 // Bitfield Extract: URShiftL + AndL
9800 instruct andL_urShiftL_regL_immI_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immI src2, immLpow2minus1 src3) %{
9801   match(Set dst (AndL (URShiftL src1 src2) src3));
9802 
9803   format %{ "EXTRDI  $dst, $src1, shift=$src2, mask=$src3 \t// long bitfield extract" %}
9804   size(4);
9805   ins_encode %{
9806     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9807     int rshift  = ($src2$$constant) & 0x3f;
9808     int length = log2_long(((jlong) $src3$$constant) + 1);
9809     if (rshift + length > 64) {
9810       // if necessary, adjust mask to omit rotated bits.
9811       length = 64 - rshift;
9812     }
9813     __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
9814   %}
9815   ins_pipe(pipe_class_default);
9816 %}
9817 
9818 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
9819   match(Set dst (ConvL2I (ConvI2L src)));
9820 
9821   format %{ "EXTSW   $dst, $src \t// int->int" %}
9822   size(4);
9823   ins_encode %{
9824     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9825     __ extsw($dst$$Register, $src$$Register);
9826   %}
9827   ins_pipe(pipe_class_default);
9828 %}
9829 
9830 //----------Rotate Instructions------------------------------------------------
9831 
9832 // Rotate Left by 8-bit immediate
9833 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
9834   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
9835   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9836 
9837   format %{ "ROTLWI  $dst, $src, $lshift" %}
9838   size(4);
9839   ins_encode %{
9840     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9841     __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
9842   %}
9843   ins_pipe(pipe_class_default);
9844 %}
9845 
9846 // Rotate Right by 8-bit immediate
9847 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
9848   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
9849   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9850 
9851   format %{ "ROTRWI  $dst, $rshift" %}
9852   size(4);
9853   ins_encode %{
9854     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9855     __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
9856   %}
9857   ins_pipe(pipe_class_default);
9858 %}
9859 
9860 //----------Floating Point Arithmetic Instructions-----------------------------
9861 
9862 // Add float single precision
9863 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
9864   match(Set dst (AddF src1 src2));
9865 
9866   format %{ "FADDS   $dst, $src1, $src2" %}
9867   size(4);
9868   ins_encode %{
9869     // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
9870     __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9871   %}
9872   ins_pipe(pipe_class_default);
9873 %}
9874 
9875 // Add float double precision
9876 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
9877   match(Set dst (AddD src1 src2));
9878 
9879   format %{ "FADD    $dst, $src1, $src2" %}
9880   size(4);
9881   ins_encode %{
9882     // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
9883     __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9884   %}
9885   ins_pipe(pipe_class_default);
9886 %}
9887 
9888 // Sub float single precision
9889 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
9890   match(Set dst (SubF src1 src2));
9891 
9892   format %{ "FSUBS   $dst, $src1, $src2" %}
9893   size(4);
9894   ins_encode %{
9895     // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
9896     __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9897   %}
9898   ins_pipe(pipe_class_default);
9899 %}
9900 
9901 // Sub float double precision
9902 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
9903   match(Set dst (SubD src1 src2));
9904   format %{ "FSUB    $dst, $src1, $src2" %}
9905   size(4);
9906   ins_encode %{
9907     // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
9908     __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9909   %}
9910   ins_pipe(pipe_class_default);
9911 %}
9912 
9913 // Mul float single precision
9914 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
9915   match(Set dst (MulF src1 src2));
9916   format %{ "FMULS   $dst, $src1, $src2" %}
9917   size(4);
9918   ins_encode %{
9919     // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
9920     __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9921   %}
9922   ins_pipe(pipe_class_default);
9923 %}
9924 
9925 // Mul float double precision
9926 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
9927   match(Set dst (MulD src1 src2));
9928   format %{ "FMUL    $dst, $src1, $src2" %}
9929   size(4);
9930   ins_encode %{
9931     // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
9932     __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9933   %}
9934   ins_pipe(pipe_class_default);
9935 %}
9936 
9937 // Div float single precision
9938 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
9939   match(Set dst (DivF src1 src2));
9940   format %{ "FDIVS   $dst, $src1, $src2" %}
9941   size(4);
9942   ins_encode %{
9943     // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
9944     __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9945   %}
9946   ins_pipe(pipe_class_default);
9947 %}
9948 
9949 // Div float double precision
9950 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
9951   match(Set dst (DivD src1 src2));
9952   format %{ "FDIV    $dst, $src1, $src2" %}
9953   size(4);
9954   ins_encode %{
9955     // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
9956     __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9957   %}
9958   ins_pipe(pipe_class_default);
9959 %}
9960 
9961 // Absolute float single precision
9962 instruct absF_reg(regF dst, regF src) %{
9963   match(Set dst (AbsF src));
9964   format %{ "FABS    $dst, $src \t// float" %}
9965   size(4);
9966   ins_encode %{
9967     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
9968     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
9969   %}
9970   ins_pipe(pipe_class_default);
9971 %}
9972 
9973 // Absolute float double precision
9974 instruct absD_reg(regD dst, regD src) %{
9975   match(Set dst (AbsD src));
9976   format %{ "FABS    $dst, $src \t// double" %}
9977   size(4);
9978   ins_encode %{
9979     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
9980     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
9981   %}
9982   ins_pipe(pipe_class_default);
9983 %}
9984 
9985 instruct negF_reg(regF dst, regF src) %{
9986   match(Set dst (NegF src));
9987   format %{ "FNEG    $dst, $src \t// float" %}
9988   size(4);
9989   ins_encode %{
9990     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
9991     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
9992   %}
9993   ins_pipe(pipe_class_default);
9994 %}
9995 
9996 instruct negD_reg(regD dst, regD src) %{
9997   match(Set dst (NegD src));
9998   format %{ "FNEG    $dst, $src \t// double" %}
9999   size(4);
10000   ins_encode %{
10001     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
10002     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
10003   %}
10004   ins_pipe(pipe_class_default);
10005 %}
10006 
10007 // AbsF + NegF.
10008 instruct negF_absF_reg(regF dst, regF src) %{
10009   match(Set dst (NegF (AbsF src)));
10010   format %{ "FNABS   $dst, $src \t// float" %}
10011   size(4);
10012   ins_encode %{
10013     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
10014     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
10015   %}
10016   ins_pipe(pipe_class_default);
10017 %}
10018 
10019 // AbsD + NegD.
10020 instruct negD_absD_reg(regD dst, regD src) %{
10021   match(Set dst (NegD (AbsD src)));
10022   format %{ "FNABS   $dst, $src \t// double" %}
10023   size(4);
10024   ins_encode %{
10025     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
10026     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
10027   %}
10028   ins_pipe(pipe_class_default);
10029 %}
10030 
10031 // VM_Version::has_fsqrt() decides if this node will be used.
10032 // Sqrt float double precision
10033 instruct sqrtD_reg(regD dst, regD src) %{
10034   match(Set dst (SqrtD src));
10035   format %{ "FSQRT   $dst, $src" %}
10036   size(4);
10037   ins_encode %{
10038     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
10039     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
10040   %}
10041   ins_pipe(pipe_class_default);
10042 %}
10043 
10044 // Single-precision sqrt.
10045 instruct sqrtF_reg(regF dst, regF src) %{
10046   match(Set dst (SqrtF src));
10047   predicate(VM_Version::has_fsqrts());
10048   ins_cost(DEFAULT_COST);
10049 
10050   format %{ "FSQRTS  $dst, $src" %}
10051   size(4);
10052   ins_encode %{
10053     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
10054     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
10055   %}
10056   ins_pipe(pipe_class_default);
10057 %}
10058 
10059 instruct roundDouble_nop(regD dst) %{
10060   match(Set dst (RoundDouble dst));
10061   ins_cost(0);
10062 
10063   format %{ " -- \t// RoundDouble not needed - empty" %}
10064   size(0);
10065   // PPC results are already "rounded" (i.e., normal-format IEEE).
10066   ins_encode( /*empty*/ );
10067   ins_pipe(pipe_class_default);
10068 %}
10069 
10070 instruct roundFloat_nop(regF dst) %{
10071   match(Set dst (RoundFloat dst));
10072   ins_cost(0);
10073 
10074   format %{ " -- \t// RoundFloat not needed - empty" %}
10075   size(0);
10076   // PPC results are already "rounded" (i.e., normal-format IEEE).
10077   ins_encode( /*empty*/ );
10078   ins_pipe(pipe_class_default);
10079 %}
10080 
10081 
10082 // Multiply-Accumulate
10083 // src1 * src2 + src3
10084 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10085   match(Set dst (FmaF src3 (Binary src1 src2)));
10086 
10087   format %{ "FMADDS  $dst, $src1, $src2, $src3" %}
10088   size(4);
10089   ins_encode %{
10090     // TODO: PPC port $archOpcode(ppc64Opcode_fmadds);
10091     __ fmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
10092   %}
10093   ins_pipe(pipe_class_default);
10094 %}
10095 
10096 // src1 * src2 + src3
10097 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10098   match(Set dst (FmaD src3 (Binary src1 src2)));
10099 
10100   format %{ "FMADD   $dst, $src1, $src2, $src3" %}
10101   size(4);
10102   ins_encode %{
10103     // TODO: PPC port $archOpcode(ppc64Opcode_fmadd);
10104     __ fmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
10105   %}
10106   ins_pipe(pipe_class_default);
10107 %}
10108 
10109 // -src1 * src2 + src3 = -(src1*src2-src3)
10110 instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10111   match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
10112   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
10113 
10114   format %{ "FNMSUBS $dst, $src1, $src2, $src3" %}
10115   size(4);
10116   ins_encode %{
10117     // TODO: PPC port $archOpcode(ppc64Opcode_fnmsubs);
10118     __ fnmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
10119   %}
10120   ins_pipe(pipe_class_default);
10121 %}
10122 
10123 // -src1 * src2 + src3 = -(src1*src2-src3)
10124 instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10125   match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
10126   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
10127 
10128   format %{ "FNMSUB  $dst, $src1, $src2, $src3" %}
10129   size(4);
10130   ins_encode %{
10131     // TODO: PPC port $archOpcode(ppc64Opcode_fnmsub);
10132     __ fnmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
10133   %}
10134   ins_pipe(pipe_class_default);
10135 %}
10136 
10137 // -src1 * src2 - src3 = -(src1*src2+src3)
10138 instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10139   match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
10140   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
10141 
10142   format %{ "FNMADDS $dst, $src1, $src2, $src3" %}
10143   size(4);
10144   ins_encode %{
10145     // TODO: PPC port $archOpcode(ppc64Opcode_fnmadds);
10146     __ fnmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
10147   %}
10148   ins_pipe(pipe_class_default);
10149 %}
10150 
10151 // -src1 * src2 - src3 = -(src1*src2+src3)
10152 instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10153   match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
10154   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
10155 
10156   format %{ "FNMADD  $dst, $src1, $src2, $src3" %}
10157   size(4);
10158   ins_encode %{
10159     // TODO: PPC port $archOpcode(ppc64Opcode_fnmadd);
10160     __ fnmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
10161   %}
10162   ins_pipe(pipe_class_default);
10163 %}
10164 
10165 // src1 * src2 - src3
10166 instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10167   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
10168 
10169   format %{ "FMSUBS  $dst, $src1, $src2, $src3" %}
10170   size(4);
10171   ins_encode %{
10172     // TODO: PPC port $archOpcode(ppc64Opcode_fmsubs);
10173     __ fmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
10174   %}
10175   ins_pipe(pipe_class_default);
10176 %}
10177 
10178 // src1 * src2 - src3
10179 instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10180   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
10181 
10182   format %{ "FMSUB   $dst, $src1, $src2, $src3" %}
10183   size(4);
10184   ins_encode %{
10185     // TODO: PPC port $archOpcode(ppc64Opcode_fmsub);
10186     __ fmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
10187   %}
10188   ins_pipe(pipe_class_default);
10189 %}
10190 
10191 
10192 //----------Logical Instructions-----------------------------------------------
10193 
10194 // And Instructions
10195 
10196 // Register And
10197 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
10198   match(Set dst (AndI src1 src2));
10199   format %{ "AND     $dst, $src1, $src2" %}
10200   size(4);
10201   ins_encode %{
10202     // TODO: PPC port $archOpcode(ppc64Opcode_and);
10203     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
10204   %}
10205   ins_pipe(pipe_class_default);
10206 %}
10207 
10208 // Left shifted Immediate And
10209 instruct andI_reg_immIhi16(iRegIdst dst, iRegIsrc src1, immIhi16  src2, flagsRegCR0 cr0) %{
10210   match(Set dst (AndI src1 src2));
10211   effect(KILL cr0);
10212   format %{ "ANDIS   $dst, $src1, $src2.hi" %}
10213   size(4);
10214   ins_encode %{
10215     // TODO: PPC port $archOpcode(ppc64Opcode_andis_);
10216     __ andis_($dst$$Register, $src1$$Register, (int)((unsigned short)(($src2$$constant & 0xFFFF0000) >> 16)));
10217   %}
10218   ins_pipe(pipe_class_default);
10219 %}
10220 
10221 // Immediate And
10222 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
10223   match(Set dst (AndI src1 src2));
10224   effect(KILL cr0);
10225 
10226   format %{ "ANDI    $dst, $src1, $src2" %}
10227   size(4);
10228   ins_encode %{
10229     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10230     // FIXME: avoid andi_ ?
10231     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
10232   %}
10233   ins_pipe(pipe_class_default);
10234 %}
10235 
10236 // Immediate And where the immediate is a negative power of 2.
10237 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
10238   match(Set dst (AndI src1 src2));
10239   format %{ "ANDWI   $dst, $src1, $src2" %}
10240   size(4);
10241   ins_encode %{
10242     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10243     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
10244   %}
10245   ins_pipe(pipe_class_default);
10246 %}
10247 
10248 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
10249   match(Set dst (AndI src1 src2));
10250   format %{ "ANDWI   $dst, $src1, $src2" %}
10251   size(4);
10252   ins_encode %{
10253     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
10254     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
10255   %}
10256   ins_pipe(pipe_class_default);
10257 %}
10258 
10259 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
10260   match(Set dst (AndI src1 src2));
10261   predicate(UseRotateAndMaskInstructionsPPC64);
10262   format %{ "ANDWI   $dst, $src1, $src2" %}
10263   size(4);
10264   ins_encode %{
10265     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
10266     __ rlwinm($dst$$Register, $src1$$Register, 0,
10267               (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
10268   %}
10269   ins_pipe(pipe_class_default);
10270 %}
10271 
10272 // Register And Long
10273 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
10274   match(Set dst (AndL src1 src2));
10275   ins_cost(DEFAULT_COST);
10276 
10277   format %{ "AND     $dst, $src1, $src2 \t// long" %}
10278   size(4);
10279   ins_encode %{
10280     // TODO: PPC port $archOpcode(ppc64Opcode_and);
10281     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
10282   %}
10283   ins_pipe(pipe_class_default);
10284 %}
10285 
10286 // Immediate And long
10287 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
10288   match(Set dst (AndL src1 src2));
10289   effect(KILL cr0);
10290 
10291   format %{ "ANDI    $dst, $src1, $src2 \t// long" %}
10292   size(4);
10293   ins_encode %{
10294     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10295     // FIXME: avoid andi_ ?
10296     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
10297   %}
10298   ins_pipe(pipe_class_default);
10299 %}
10300 
10301 // Immediate And Long where the immediate is a negative power of 2.
10302 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
10303   match(Set dst (AndL src1 src2));
10304   format %{ "ANDDI   $dst, $src1, $src2" %}
10305   size(4);
10306   ins_encode %{
10307     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10308     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
10309   %}
10310   ins_pipe(pipe_class_default);
10311 %}
10312 
10313 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
10314   match(Set dst (AndL src1 src2));
10315   format %{ "ANDDI   $dst, $src1, $src2" %}
10316   size(4);
10317   ins_encode %{
10318     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
10319     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
10320   %}
10321   ins_pipe(pipe_class_default);
10322 %}
10323 
10324 // AndL + ConvL2I.
10325 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
10326   match(Set dst (ConvL2I (AndL src1 src2)));
10327   ins_cost(DEFAULT_COST);
10328 
10329   format %{ "ANDDI   $dst, $src1, $src2 \t// long + l2i" %}
10330   size(4);
10331   ins_encode %{
10332     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
10333     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
10334   %}
10335   ins_pipe(pipe_class_default);
10336 %}
10337 
10338 // Or Instructions
10339 
10340 // Register Or
10341 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
10342   match(Set dst (OrI src1 src2));
10343   format %{ "OR      $dst, $src1, $src2" %}
10344   size(4);
10345   ins_encode %{
10346     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10347     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
10348   %}
10349   ins_pipe(pipe_class_default);
10350 %}
10351 
10352 // Expand does not work with above instruct. (??)
10353 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
10354   // no match-rule
10355   effect(DEF dst, USE src1, USE src2);
10356   format %{ "OR      $dst, $src1, $src2" %}
10357   size(4);
10358   ins_encode %{
10359     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10360     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
10361   %}
10362   ins_pipe(pipe_class_default);
10363 %}
10364 
10365 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
10366   match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
10367   ins_cost(DEFAULT_COST*3);
10368 
10369   expand %{
10370     // FIXME: we should do this in the ideal world.
10371     iRegIdst tmp1;
10372     iRegIdst tmp2;
10373     orI_reg_reg(tmp1, src1, src2);
10374     orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
10375     orI_reg_reg(dst, tmp1, tmp2);
10376   %}
10377 %}
10378 
10379 // Immediate Or
10380 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
10381   match(Set dst (OrI src1 src2));
10382   format %{ "ORI     $dst, $src1, $src2" %}
10383   size(4);
10384   ins_encode %{
10385     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
10386     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
10387   %}
10388   ins_pipe(pipe_class_default);
10389 %}
10390 
10391 // Register Or Long
10392 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
10393   match(Set dst (OrL src1 src2));
10394   ins_cost(DEFAULT_COST);
10395 
10396   size(4);
10397   format %{ "OR      $dst, $src1, $src2 \t// long" %}
10398   ins_encode %{
10399     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10400     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
10401   %}
10402   ins_pipe(pipe_class_default);
10403 %}
10404 
10405 // OrL + ConvL2I.
10406 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10407   match(Set dst (ConvL2I (OrL src1 src2)));
10408   ins_cost(DEFAULT_COST);
10409 
10410   format %{ "OR      $dst, $src1, $src2 \t// long + l2i" %}
10411   size(4);
10412   ins_encode %{
10413     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10414     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
10415   %}
10416   ins_pipe(pipe_class_default);
10417 %}
10418 
10419 // Immediate Or long
10420 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
10421   match(Set dst (OrL src1 con));
10422   ins_cost(DEFAULT_COST);
10423 
10424   format %{ "ORI     $dst, $src1, $con \t// long" %}
10425   size(4);
10426   ins_encode %{
10427     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
10428     __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
10429   %}
10430   ins_pipe(pipe_class_default);
10431 %}
10432 
10433 // Xor Instructions
10434 
10435 // Register Xor
10436 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
10437   match(Set dst (XorI src1 src2));
10438   format %{ "XOR     $dst, $src1, $src2" %}
10439   size(4);
10440   ins_encode %{
10441     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
10442     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
10443   %}
10444   ins_pipe(pipe_class_default);
10445 %}
10446 
10447 // Expand does not work with above instruct. (??)
10448 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
10449   // no match-rule
10450   effect(DEF dst, USE src1, USE src2);
10451   format %{ "XOR     $dst, $src1, $src2" %}
10452   size(4);
10453   ins_encode %{
10454     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
10455     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
10456   %}
10457   ins_pipe(pipe_class_default);
10458 %}
10459 
10460 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
10461   match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
10462   ins_cost(DEFAULT_COST*3);
10463 
10464   expand %{
10465     // FIXME: we should do this in the ideal world.
10466     iRegIdst tmp1;
10467     iRegIdst tmp2;
10468     xorI_reg_reg(tmp1, src1, src2);
10469     xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
10470     xorI_reg_reg(dst, tmp1, tmp2);
10471   %}
10472 %}
10473 
10474 // Immediate Xor
10475 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
10476   match(Set dst (XorI src1 src2));
10477   format %{ "XORI    $dst, $src1, $src2" %}
10478   size(4);
10479   ins_encode %{
10480     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
10481     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
10482   %}
10483   ins_pipe(pipe_class_default);
10484 %}
10485 
10486 // Register Xor Long
10487 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
10488   match(Set dst (XorL src1 src2));
10489   ins_cost(DEFAULT_COST);
10490 
10491   format %{ "XOR     $dst, $src1, $src2 \t// long" %}
10492   size(4);
10493   ins_encode %{
10494     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
10495     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
10496   %}
10497   ins_pipe(pipe_class_default);
10498 %}
10499 
10500 // XorL + ConvL2I.
10501 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10502   match(Set dst (ConvL2I (XorL src1 src2)));
10503   ins_cost(DEFAULT_COST);
10504 
10505   format %{ "XOR     $dst, $src1, $src2 \t// long + l2i" %}
10506   size(4);
10507   ins_encode %{
10508     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
10509     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
10510   %}
10511   ins_pipe(pipe_class_default);
10512 %}
10513 
10514 // Immediate Xor Long
10515 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
10516   match(Set dst (XorL src1 src2));
10517   ins_cost(DEFAULT_COST);
10518 
10519   format %{ "XORI    $dst, $src1, $src2 \t// long" %}
10520   size(4);
10521   ins_encode %{
10522     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
10523     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
10524   %}
10525   ins_pipe(pipe_class_default);
10526 %}
10527 
10528 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
10529   match(Set dst (XorI src1 src2));
10530   ins_cost(DEFAULT_COST);
10531 
10532   format %{ "NOT     $dst, $src1 ($src2)" %}
10533   size(4);
10534   ins_encode %{
10535     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
10536     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
10537   %}
10538   ins_pipe(pipe_class_default);
10539 %}
10540 
10541 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
10542   match(Set dst (XorL src1 src2));
10543   ins_cost(DEFAULT_COST);
10544 
10545   format %{ "NOT     $dst, $src1 ($src2) \t// long" %}
10546   size(4);
10547   ins_encode %{
10548     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
10549     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
10550   %}
10551   ins_pipe(pipe_class_default);
10552 %}
10553 
10554 // And-complement
10555 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
10556   match(Set dst (AndI (XorI src1 src2) src3));
10557   ins_cost(DEFAULT_COST);
10558 
10559   format %{ "ANDW    $dst, xori($src1, $src2), $src3" %}
10560   size(4);
10561   ins_encode( enc_andc(dst, src3, src1) );
10562   ins_pipe(pipe_class_default);
10563 %}
10564 
10565 // And-complement
10566 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
10567   // no match-rule, false predicate
10568   effect(DEF dst, USE src1, USE src2);
10569   predicate(false);
10570 
10571   format %{ "ANDC    $dst, $src1, $src2" %}
10572   size(4);
10573   ins_encode %{
10574     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
10575     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
10576   %}
10577   ins_pipe(pipe_class_default);
10578 %}
10579 
10580 //----------Moves between int/long and float/double----------------------------
10581 //
10582 // The following rules move values from int/long registers/stack-locations
10583 // to float/double registers/stack-locations and vice versa, without doing any
10584 // conversions. These rules are used to implement the bit-conversion methods
10585 // of java.lang.Float etc., e.g.
10586 //   int   floatToIntBits(float value)
10587 //   float intBitsToFloat(int bits)
10588 //
10589 // Notes on the implementation on ppc64:
10590 // For Power7 and earlier, the rules are limited to those which move between a
10591 // register and a stack-location, because we always have to go through memory
10592 // when moving between a float register and an integer register.
10593 // This restriction is removed in Power8 with the introduction of the mtfprd
10594 // and mffprd instructions.
10595 
10596 instruct moveL2D_reg(regD dst, iRegLsrc src) %{
10597   match(Set dst (MoveL2D src));
10598   predicate(VM_Version::has_mtfprd());
10599 
10600   format %{ "MTFPRD  $dst, $src" %}
10601   size(4);
10602   ins_encode %{
10603     __ mtfprd($dst$$FloatRegister, $src$$Register);
10604   %}
10605   ins_pipe(pipe_class_default);
10606 %}
10607 
10608 instruct moveI2D_reg(regD dst, iRegIsrc src) %{
10609   // no match-rule, false predicate
10610   effect(DEF dst, USE src);
10611   predicate(false);
10612 
10613   format %{ "MTFPRWA $dst, $src" %}
10614   size(4);
10615   ins_encode %{
10616     __ mtfprwa($dst$$FloatRegister, $src$$Register);
10617   %}
10618   ins_pipe(pipe_class_default);
10619 %}
10620 
10621 //---------- Chain stack slots between similar types --------
10622 
10623 // These are needed so that the rules below can match.
10624 
10625 // Load integer from stack slot
10626 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
10627   match(Set dst src);
10628   ins_cost(MEMORY_REF_COST);
10629 
10630   format %{ "LWZ     $dst, $src" %}
10631   size(4);
10632   ins_encode( enc_lwz(dst, src) );
10633   ins_pipe(pipe_class_memory);
10634 %}
10635 
10636 // Store integer to stack slot
10637 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
10638   match(Set dst src);
10639   ins_cost(MEMORY_REF_COST);
10640 
10641   format %{ "STW     $src, $dst \t// stk" %}
10642   size(4);
10643   ins_encode( enc_stw(src, dst) ); // rs=rt
10644   ins_pipe(pipe_class_memory);
10645 %}
10646 
10647 // Load long from stack slot
10648 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
10649   match(Set dst src);
10650   ins_cost(MEMORY_REF_COST);
10651 
10652   format %{ "LD      $dst, $src \t// long" %}
10653   size(4);
10654   ins_encode( enc_ld(dst, src) );
10655   ins_pipe(pipe_class_memory);
10656 %}
10657 
10658 // Store long to stack slot
10659 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
10660   match(Set dst src);
10661   ins_cost(MEMORY_REF_COST);
10662 
10663   format %{ "STD     $src, $dst \t// long" %}
10664   size(4);
10665   ins_encode( enc_std(src, dst) ); // rs=rt
10666   ins_pipe(pipe_class_memory);
10667 %}
10668 
10669 //----------Moves between int and float
10670 
10671 // Move float value from float stack-location to integer register.
10672 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
10673   match(Set dst (MoveF2I src));
10674   ins_cost(MEMORY_REF_COST);
10675 
10676   format %{ "LWZ     $dst, $src \t// MoveF2I" %}
10677   size(4);
10678   ins_encode( enc_lwz(dst, src) );
10679   ins_pipe(pipe_class_memory);
10680 %}
10681 
10682 // Move float value from float register to integer stack-location.
10683 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
10684   match(Set dst (MoveF2I src));
10685   ins_cost(MEMORY_REF_COST);
10686 
10687   format %{ "STFS    $src, $dst \t// MoveF2I" %}
10688   size(4);
10689   ins_encode( enc_stfs(src, dst) );
10690   ins_pipe(pipe_class_memory);
10691 %}
10692 
10693 // Move integer value from integer stack-location to float register.
10694 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
10695   match(Set dst (MoveI2F src));
10696   ins_cost(MEMORY_REF_COST);
10697 
10698   format %{ "LFS     $dst, $src \t// MoveI2F" %}
10699   size(4);
10700   ins_encode %{
10701     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
10702     int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
10703     __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
10704   %}
10705   ins_pipe(pipe_class_memory);
10706 %}
10707 
10708 // Move integer value from integer register to float stack-location.
10709 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
10710   match(Set dst (MoveI2F src));
10711   ins_cost(MEMORY_REF_COST);
10712 
10713   format %{ "STW     $src, $dst \t// MoveI2F" %}
10714   size(4);
10715   ins_encode( enc_stw(src, dst) );
10716   ins_pipe(pipe_class_memory);
10717 %}
10718 
10719 //----------Moves between long and float
10720 
10721 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
10722   // no match-rule, false predicate
10723   effect(DEF dst, USE src);
10724   predicate(false);
10725 
10726   format %{ "storeD  $src, $dst \t// STACK" %}
10727   size(4);
10728   ins_encode( enc_stfd(src, dst) );
10729   ins_pipe(pipe_class_default);
10730 %}
10731 
10732 //----------Moves between long and double
10733 
10734 // Move double value from double stack-location to long register.
10735 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
10736   match(Set dst (MoveD2L src));
10737   ins_cost(MEMORY_REF_COST);
10738   size(4);
10739   format %{ "LD      $dst, $src \t// MoveD2L" %}
10740   ins_encode( enc_ld(dst, src) );
10741   ins_pipe(pipe_class_memory);
10742 %}
10743 
10744 // Move double value from double register to long stack-location.
10745 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
10746   match(Set dst (MoveD2L src));
10747   effect(DEF dst, USE src);
10748   ins_cost(MEMORY_REF_COST);
10749 
10750   format %{ "STFD    $src, $dst \t// MoveD2L" %}
10751   size(4);
10752   ins_encode( enc_stfd(src, dst) );
10753   ins_pipe(pipe_class_memory);
10754 %}
10755 
10756 // Move long value from long stack-location to double register.
10757 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
10758   match(Set dst (MoveL2D src));
10759   ins_cost(MEMORY_REF_COST);
10760 
10761   format %{ "LFD     $dst, $src \t// MoveL2D" %}
10762   size(4);
10763   ins_encode( enc_lfd(dst, src) );
10764   ins_pipe(pipe_class_memory);
10765 %}
10766 
10767 // Move long value from long register to double stack-location.
10768 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
10769   match(Set dst (MoveL2D src));
10770   ins_cost(MEMORY_REF_COST);
10771 
10772   format %{ "STD     $src, $dst \t// MoveL2D" %}
10773   size(4);
10774   ins_encode( enc_std(src, dst) );
10775   ins_pipe(pipe_class_memory);
10776 %}
10777 
10778 //----------Register Move Instructions-----------------------------------------
10779 
10780 // Replicate for Superword
10781 
10782 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
10783   predicate(false);
10784   effect(DEF dst, USE src);
10785 
10786   format %{ "MR      $dst, $src \t// replicate " %}
10787   // variable size, 0 or 4.
10788   ins_encode %{
10789     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10790     __ mr_if_needed($dst$$Register, $src$$Register);
10791   %}
10792   ins_pipe(pipe_class_default);
10793 %}
10794 
10795 //----------Cast instructions (Java-level type cast)---------------------------
10796 
10797 // Cast Long to Pointer for unsafe natives.
10798 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
10799   match(Set dst (CastX2P src));
10800 
10801   format %{ "MR      $dst, $src \t// Long->Ptr" %}
10802   // variable size, 0 or 4.
10803   ins_encode %{
10804     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10805     __ mr_if_needed($dst$$Register, $src$$Register);
10806   %}
10807  ins_pipe(pipe_class_default);
10808 %}
10809 
10810 // Cast Pointer to Long for unsafe natives.
10811 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
10812   match(Set dst (CastP2X src));
10813 
10814   format %{ "MR      $dst, $src \t// Ptr->Long" %}
10815   // variable size, 0 or 4.
10816   ins_encode %{
10817     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10818     __ mr_if_needed($dst$$Register, $src$$Register);
10819   %}
10820   ins_pipe(pipe_class_default);
10821 %}
10822 
10823 instruct castPP(iRegPdst dst) %{
10824   match(Set dst (CastPP dst));
10825   format %{ " -- \t// castPP of $dst" %}
10826   size(0);
10827   ins_encode( /*empty*/ );
10828   ins_pipe(pipe_class_default);
10829 %}
10830 
10831 instruct castII(iRegIdst dst) %{
10832   match(Set dst (CastII dst));
10833   format %{ " -- \t// castII of $dst" %}
10834   size(0);
10835   ins_encode( /*empty*/ );
10836   ins_pipe(pipe_class_default);
10837 %}
10838 
10839 instruct checkCastPP(iRegPdst dst) %{
10840   match(Set dst (CheckCastPP dst));
10841   format %{ " -- \t// checkcastPP of $dst" %}
10842   size(0);
10843   ins_encode( /*empty*/ );
10844   ins_pipe(pipe_class_default);
10845 %}
10846 
10847 //----------Convert instructions-----------------------------------------------
10848 
10849 // Convert to boolean.
10850 
10851 // int_to_bool(src) : { 1   if src != 0
10852 //                    { 0   else
10853 //
10854 // strategy:
10855 // 1) Count leading zeros of 32 bit-value src,
10856 //    this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
10857 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
10858 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
10859 
10860 // convI2Bool
10861 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
10862   match(Set dst (Conv2B src));
10863   predicate(UseCountLeadingZerosInstructionsPPC64);
10864   ins_cost(DEFAULT_COST);
10865 
10866   expand %{
10867     immI shiftAmount %{ 0x5 %}
10868     uimmI16 mask %{ 0x1 %}
10869     iRegIdst tmp1;
10870     iRegIdst tmp2;
10871     countLeadingZerosI(tmp1, src);
10872     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
10873     xorI_reg_uimm16(dst, tmp2, mask);
10874   %}
10875 %}
10876 
10877 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
10878   match(Set dst (Conv2B src));
10879   effect(TEMP crx);
10880   predicate(!UseCountLeadingZerosInstructionsPPC64);
10881   ins_cost(DEFAULT_COST);
10882 
10883   format %{ "CMPWI   $crx, $src, #0 \t// convI2B"
10884             "LI      $dst, #0\n\t"
10885             "BEQ     $crx, done\n\t"
10886             "LI      $dst, #1\n"
10887             "done:" %}
10888   size(16);
10889   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
10890   ins_pipe(pipe_class_compare);
10891 %}
10892 
10893 // ConvI2B + XorI
10894 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
10895   match(Set dst (XorI (Conv2B src) mask));
10896   predicate(UseCountLeadingZerosInstructionsPPC64);
10897   ins_cost(DEFAULT_COST);
10898 
10899   expand %{
10900     immI shiftAmount %{ 0x5 %}
10901     iRegIdst tmp1;
10902     countLeadingZerosI(tmp1, src);
10903     urShiftI_reg_imm(dst, tmp1, shiftAmount);
10904   %}
10905 %}
10906 
10907 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
10908   match(Set dst (XorI (Conv2B src) mask));
10909   effect(TEMP crx);
10910   predicate(!UseCountLeadingZerosInstructionsPPC64);
10911   ins_cost(DEFAULT_COST);
10912 
10913   format %{ "CMPWI   $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
10914             "LI      $dst, #1\n\t"
10915             "BEQ     $crx, done\n\t"
10916             "LI      $dst, #0\n"
10917             "done:" %}
10918   size(16);
10919   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
10920   ins_pipe(pipe_class_compare);
10921 %}
10922 
10923 // AndI 0b0..010..0 + ConvI2B
10924 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
10925   match(Set dst (Conv2B (AndI src mask)));
10926   predicate(UseRotateAndMaskInstructionsPPC64);
10927   ins_cost(DEFAULT_COST);
10928 
10929   format %{ "RLWINM  $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
10930   size(4);
10931   ins_encode %{
10932     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
10933     __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
10934   %}
10935   ins_pipe(pipe_class_default);
10936 %}
10937 
10938 // Convert pointer to boolean.
10939 //
10940 // ptr_to_bool(src) : { 1   if src != 0
10941 //                    { 0   else
10942 //
10943 // strategy:
10944 // 1) Count leading zeros of 64 bit-value src,
10945 //    this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
10946 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
10947 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
10948 
10949 // ConvP2B
10950 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
10951   match(Set dst (Conv2B src));
10952   predicate(UseCountLeadingZerosInstructionsPPC64);
10953   ins_cost(DEFAULT_COST);
10954 
10955   expand %{
10956     immI shiftAmount %{ 0x6 %}
10957     uimmI16 mask %{ 0x1 %}
10958     iRegIdst tmp1;
10959     iRegIdst tmp2;
10960     countLeadingZerosP(tmp1, src);
10961     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
10962     xorI_reg_uimm16(dst, tmp2, mask);
10963   %}
10964 %}
10965 
10966 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
10967   match(Set dst (Conv2B src));
10968   effect(TEMP crx);
10969   predicate(!UseCountLeadingZerosInstructionsPPC64);
10970   ins_cost(DEFAULT_COST);
10971 
10972   format %{ "CMPDI   $crx, $src, #0 \t// convP2B"
10973             "LI      $dst, #0\n\t"
10974             "BEQ     $crx, done\n\t"
10975             "LI      $dst, #1\n"
10976             "done:" %}
10977   size(16);
10978   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
10979   ins_pipe(pipe_class_compare);
10980 %}
10981 
10982 // ConvP2B + XorI
10983 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
10984   match(Set dst (XorI (Conv2B src) mask));
10985   predicate(UseCountLeadingZerosInstructionsPPC64);
10986   ins_cost(DEFAULT_COST);
10987 
10988   expand %{
10989     immI shiftAmount %{ 0x6 %}
10990     iRegIdst tmp1;
10991     countLeadingZerosP(tmp1, src);
10992     urShiftI_reg_imm(dst, tmp1, shiftAmount);
10993   %}
10994 %}
10995 
10996 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
10997   match(Set dst (XorI (Conv2B src) mask));
10998   effect(TEMP crx);
10999   predicate(!UseCountLeadingZerosInstructionsPPC64);
11000   ins_cost(DEFAULT_COST);
11001 
11002   format %{ "CMPDI   $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
11003             "LI      $dst, #1\n\t"
11004             "BEQ     $crx, done\n\t"
11005             "LI      $dst, #0\n"
11006             "done:" %}
11007   size(16);
11008   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
11009   ins_pipe(pipe_class_compare);
11010 %}
11011 
11012 // if src1 < src2, return -1 else return 0
11013 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11014   match(Set dst (CmpLTMask src1 src2));
11015   ins_cost(DEFAULT_COST*4);
11016 
11017   expand %{
11018     iRegLdst src1s;
11019     iRegLdst src2s;
11020     iRegLdst diff;
11021     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11022     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11023     subL_reg_reg(diff, src1s, src2s);
11024     // Need to consider >=33 bit result, therefore we need signmaskL.
11025     signmask64I_regL(dst, diff);
11026   %}
11027 %}
11028 
11029 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
11030   match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
11031   format %{ "SRAWI   $dst, $src1, $src2 \t// CmpLTMask" %}
11032   size(4);
11033   ins_encode %{
11034     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
11035     __ srawi($dst$$Register, $src1$$Register, 0x1f);
11036   %}
11037   ins_pipe(pipe_class_default);
11038 %}
11039 
11040 //----------Arithmetic Conversion Instructions---------------------------------
11041 
11042 // Convert to Byte  -- nop
11043 // Convert to Short -- nop
11044 
11045 // Convert to Int
11046 
11047 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
11048   match(Set dst (RShiftI (LShiftI src amount) amount));
11049   format %{ "EXTSB   $dst, $src \t// byte->int" %}
11050   size(4);
11051   ins_encode %{
11052     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
11053     __ extsb($dst$$Register, $src$$Register);
11054   %}
11055   ins_pipe(pipe_class_default);
11056 %}
11057 
11058 instruct extsh(iRegIdst dst, iRegIsrc src) %{
11059   effect(DEF dst, USE src);
11060 
11061   size(4);
11062   ins_encode %{
11063     __ extsh($dst$$Register, $src$$Register);
11064   %}
11065   ins_pipe(pipe_class_default);
11066 %}
11067 
11068 // LShiftI 16 + RShiftI 16 converts short to int.
11069 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
11070   match(Set dst (RShiftI (LShiftI src amount) amount));
11071   format %{ "EXTSH   $dst, $src \t// short->int" %}
11072   size(4);
11073   ins_encode %{
11074     // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
11075     __ extsh($dst$$Register, $src$$Register);
11076   %}
11077   ins_pipe(pipe_class_default);
11078 %}
11079 
11080 // ConvL2I + ConvI2L: Sign extend int in long register.
11081 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
11082   match(Set dst (ConvI2L (ConvL2I src)));
11083 
11084   format %{ "EXTSW   $dst, $src \t// long->long" %}
11085   size(4);
11086   ins_encode %{
11087     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
11088     __ extsw($dst$$Register, $src$$Register);
11089   %}
11090   ins_pipe(pipe_class_default);
11091 %}
11092 
11093 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
11094   match(Set dst (ConvL2I src));
11095   format %{ "MR      $dst, $src \t// long->int" %}
11096   // variable size, 0 or 4
11097   ins_encode %{
11098     // TODO: PPC port $archOpcode(ppc64Opcode_or);
11099     __ mr_if_needed($dst$$Register, $src$$Register);
11100   %}
11101   ins_pipe(pipe_class_default);
11102 %}
11103 
11104 instruct convD2IRaw_regD(regD dst, regD src) %{
11105   // no match-rule, false predicate
11106   effect(DEF dst, USE src);
11107   predicate(false);
11108 
11109   format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
11110   size(4);
11111   ins_encode %{
11112     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
11113     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
11114   %}
11115   ins_pipe(pipe_class_default);
11116 %}
11117 
11118 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
11119   // no match-rule, false predicate
11120   effect(DEF dst, USE crx, USE src);
11121   predicate(false);
11122 
11123   ins_variable_size_depending_on_alignment(true);
11124 
11125   format %{ "cmovI   $crx, $dst, $src" %}
11126   // Worst case is branch + move + stop, no stop without scheduler.
11127   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
11128   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
11129   ins_pipe(pipe_class_default);
11130 %}
11131 
11132 instruct cmovI_bso_reg(iRegIdst dst, flagsRegSrc crx, regD src) %{
11133   // no match-rule, false predicate
11134   effect(DEF dst, USE crx, USE src);
11135   predicate(false);
11136 
11137   ins_variable_size_depending_on_alignment(true);
11138 
11139   format %{ "cmovI   $crx, $dst, $src" %}
11140   // Worst case is branch + move + stop, no stop without scheduler.
11141   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
11142   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
11143   ins_pipe(pipe_class_default);
11144 %}
11145 
11146 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
11147   // no match-rule, false predicate
11148   effect(DEF dst, USE crx, USE mem);
11149   predicate(false);
11150 
11151   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
11152   postalloc_expand %{
11153     //
11154     // replaces
11155     //
11156     //   region  dst  crx  mem
11157     //    \       |    |   /
11158     //     dst=cmovI_bso_stackSlotL_conLvalue0
11159     //
11160     // with
11161     //
11162     //   region  dst
11163     //    \       /
11164     //     dst=loadConI16(0)
11165     //      |
11166     //      ^  region  dst  crx  mem
11167     //      |   \       |    |    /
11168     //      dst=cmovI_bso_stackSlotL
11169     //
11170 
11171     // Create new nodes.
11172     MachNode *m1 = new loadConI16Node();
11173     MachNode *m2 = new cmovI_bso_stackSlotLNode();
11174 
11175     // inputs for new nodes
11176     m1->add_req(n_region);
11177     m2->add_req(n_region, n_crx, n_mem);
11178 
11179     // precedences for new nodes
11180     m2->add_prec(m1);
11181 
11182     // operands for new nodes
11183     m1->_opnds[0] = op_dst;
11184     m1->_opnds[1] = new immI16Oper(0);
11185 
11186     m2->_opnds[0] = op_dst;
11187     m2->_opnds[1] = op_crx;
11188     m2->_opnds[2] = op_mem;
11189 
11190     // registers for new nodes
11191     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11192     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11193 
11194     // Insert new nodes.
11195     nodes->push(m1);
11196     nodes->push(m2);
11197   %}
11198 %}
11199 
11200 instruct cmovI_bso_reg_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, regD src) %{
11201   // no match-rule, false predicate
11202   effect(DEF dst, USE crx, USE src);
11203   predicate(false);
11204 
11205   format %{ "CmovI   $dst, $crx, $src \t// postalloc expanded" %}
11206   postalloc_expand %{
11207     //
11208     // replaces
11209     //
11210     //   region  dst  crx  src
11211     //    \       |    |   /
11212     //     dst=cmovI_bso_reg_conLvalue0
11213     //
11214     // with
11215     //
11216     //   region  dst
11217     //    \       /
11218     //     dst=loadConI16(0)
11219     //      |
11220     //      ^  region  dst  crx  src
11221     //      |   \       |    |    /
11222     //      dst=cmovI_bso_reg
11223     //
11224 
11225     // Create new nodes.
11226     MachNode *m1 = new loadConI16Node();
11227     MachNode *m2 = new cmovI_bso_regNode();
11228 
11229     // inputs for new nodes
11230     m1->add_req(n_region);
11231     m2->add_req(n_region, n_crx, n_src);
11232 
11233     // precedences for new nodes
11234     m2->add_prec(m1);
11235 
11236     // operands for new nodes
11237     m1->_opnds[0] = op_dst;
11238     m1->_opnds[1] = new immI16Oper(0);
11239 
11240     m2->_opnds[0] = op_dst;
11241     m2->_opnds[1] = op_crx;
11242     m2->_opnds[2] = op_src;
11243 
11244     // registers for new nodes
11245     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11246     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11247 
11248     // Insert new nodes.
11249     nodes->push(m1);
11250     nodes->push(m2);
11251   %}
11252 %}
11253 
11254 // Double to Int conversion, NaN is mapped to 0.
11255 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
11256   match(Set dst (ConvD2I src));
11257   predicate(!VM_Version::has_mtfprd());
11258   ins_cost(DEFAULT_COST);
11259 
11260   expand %{
11261     regD tmpD;
11262     stackSlotL tmpS;
11263     flagsReg crx;
11264     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11265     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
11266     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
11267     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11268   %}
11269 %}
11270 
11271 // Double to Int conversion, NaN is mapped to 0. Special version for Power8.
11272 instruct convD2I_reg_mffprd_ExEx(iRegIdst dst, regD src) %{
11273   match(Set dst (ConvD2I src));
11274   predicate(VM_Version::has_mtfprd());
11275   ins_cost(DEFAULT_COST);
11276 
11277   expand %{
11278     regD tmpD;
11279     flagsReg crx;
11280     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11281     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
11282     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
11283   %}
11284 %}
11285 
11286 instruct convF2IRaw_regF(regF dst, regF src) %{
11287   // no match-rule, false predicate
11288   effect(DEF dst, USE src);
11289   predicate(false);
11290 
11291   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
11292   size(4);
11293   ins_encode %{
11294     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
11295     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
11296   %}
11297   ins_pipe(pipe_class_default);
11298 %}
11299 
11300 // Float to Int conversion, NaN is mapped to 0.
11301 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
11302   match(Set dst (ConvF2I src));
11303   predicate(!VM_Version::has_mtfprd());
11304   ins_cost(DEFAULT_COST);
11305 
11306   expand %{
11307     regF tmpF;
11308     stackSlotL tmpS;
11309     flagsReg crx;
11310     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11311     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
11312     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
11313     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11314   %}
11315 %}
11316 
11317 // Float to Int conversion, NaN is mapped to 0. Special version for Power8.
11318 instruct convF2I_regF_mffprd_ExEx(iRegIdst dst, regF src) %{
11319   match(Set dst (ConvF2I src));
11320   predicate(VM_Version::has_mtfprd());
11321   ins_cost(DEFAULT_COST);
11322 
11323   expand %{
11324     regF tmpF;
11325     flagsReg crx;
11326     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11327     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
11328     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
11329   %}
11330 %}
11331 
11332 // Convert to Long
11333 
11334 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
11335   match(Set dst (ConvI2L src));
11336   format %{ "EXTSW   $dst, $src \t// int->long" %}
11337   size(4);
11338   ins_encode %{
11339     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
11340     __ extsw($dst$$Register, $src$$Register);
11341   %}
11342   ins_pipe(pipe_class_default);
11343 %}
11344 
11345 // Zero-extend: convert unsigned int to long (convUI2L).
11346 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
11347   match(Set dst (AndL (ConvI2L src) mask));
11348   ins_cost(DEFAULT_COST);
11349 
11350   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
11351   size(4);
11352   ins_encode %{
11353     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
11354     __ clrldi($dst$$Register, $src$$Register, 32);
11355   %}
11356   ins_pipe(pipe_class_default);
11357 %}
11358 
11359 // Zero-extend: convert unsigned int to long in long register.
11360 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
11361   match(Set dst (AndL src mask));
11362   ins_cost(DEFAULT_COST);
11363 
11364   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
11365   size(4);
11366   ins_encode %{
11367     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
11368     __ clrldi($dst$$Register, $src$$Register, 32);
11369   %}
11370   ins_pipe(pipe_class_default);
11371 %}
11372 
11373 instruct convF2LRaw_regF(regF dst, regF src) %{
11374   // no match-rule, false predicate
11375   effect(DEF dst, USE src);
11376   predicate(false);
11377 
11378   format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
11379   size(4);
11380   ins_encode %{
11381     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
11382     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
11383   %}
11384   ins_pipe(pipe_class_default);
11385 %}
11386 
11387 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
11388   // no match-rule, false predicate
11389   effect(DEF dst, USE crx, USE src);
11390   predicate(false);
11391 
11392   ins_variable_size_depending_on_alignment(true);
11393 
11394   format %{ "cmovL   $crx, $dst, $src" %}
11395   // Worst case is branch + move + stop, no stop without scheduler.
11396   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
11397   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
11398   ins_pipe(pipe_class_default);
11399 %}
11400 
11401 instruct cmovL_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
11402   // no match-rule, false predicate
11403   effect(DEF dst, USE crx, USE src);
11404   predicate(false);
11405 
11406   ins_variable_size_depending_on_alignment(true);
11407 
11408   format %{ "cmovL   $crx, $dst, $src" %}
11409   // Worst case is branch + move + stop, no stop without scheduler.
11410   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
11411   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
11412   ins_pipe(pipe_class_default);
11413 %}
11414 
11415 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
11416   // no match-rule, false predicate
11417   effect(DEF dst, USE crx, USE mem);
11418   predicate(false);
11419 
11420   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
11421   postalloc_expand %{
11422     //
11423     // replaces
11424     //
11425     //   region  dst  crx  mem
11426     //    \       |    |   /
11427     //     dst=cmovL_bso_stackSlotL_conLvalue0
11428     //
11429     // with
11430     //
11431     //   region  dst
11432     //    \       /
11433     //     dst=loadConL16(0)
11434     //      |
11435     //      ^  region  dst  crx  mem
11436     //      |   \       |    |    /
11437     //      dst=cmovL_bso_stackSlotL
11438     //
11439 
11440     // Create new nodes.
11441     MachNode *m1 = new loadConL16Node();
11442     MachNode *m2 = new cmovL_bso_stackSlotLNode();
11443 
11444     // inputs for new nodes
11445     m1->add_req(n_region);
11446     m2->add_req(n_region, n_crx, n_mem);
11447     m2->add_prec(m1);
11448 
11449     // operands for new nodes
11450     m1->_opnds[0] = op_dst;
11451     m1->_opnds[1] = new immL16Oper(0);
11452     m2->_opnds[0] = op_dst;
11453     m2->_opnds[1] = op_crx;
11454     m2->_opnds[2] = op_mem;
11455 
11456     // registers for new nodes
11457     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11458     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11459 
11460     // Insert new nodes.
11461     nodes->push(m1);
11462     nodes->push(m2);
11463   %}
11464 %}
11465 
11466 instruct cmovL_bso_reg_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, regD src) %{
11467   // no match-rule, false predicate
11468   effect(DEF dst, USE crx, USE src);
11469   predicate(false);
11470 
11471   format %{ "CmovL   $dst, $crx, $src \t// postalloc expanded" %}
11472   postalloc_expand %{
11473     //
11474     // replaces
11475     //
11476     //   region  dst  crx  src
11477     //    \       |    |   /
11478     //     dst=cmovL_bso_reg_conLvalue0
11479     //
11480     // with
11481     //
11482     //   region  dst
11483     //    \       /
11484     //     dst=loadConL16(0)
11485     //      |
11486     //      ^  region  dst  crx  src
11487     //      |   \       |    |    /
11488     //      dst=cmovL_bso_reg
11489     //
11490 
11491     // Create new nodes.
11492     MachNode *m1 = new loadConL16Node();
11493     MachNode *m2 = new cmovL_bso_regNode();
11494 
11495     // inputs for new nodes
11496     m1->add_req(n_region);
11497     m2->add_req(n_region, n_crx, n_src);
11498     m2->add_prec(m1);
11499 
11500     // operands for new nodes
11501     m1->_opnds[0] = op_dst;
11502     m1->_opnds[1] = new immL16Oper(0);
11503     m2->_opnds[0] = op_dst;
11504     m2->_opnds[1] = op_crx;
11505     m2->_opnds[2] = op_src;
11506 
11507     // registers for new nodes
11508     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11509     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11510 
11511     // Insert new nodes.
11512     nodes->push(m1);
11513     nodes->push(m2);
11514   %}
11515 %}
11516 
11517 // Float to Long conversion, NaN is mapped to 0.
11518 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
11519   match(Set dst (ConvF2L src));
11520   predicate(!VM_Version::has_mtfprd());
11521   ins_cost(DEFAULT_COST);
11522 
11523   expand %{
11524     regF tmpF;
11525     stackSlotL tmpS;
11526     flagsReg crx;
11527     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11528     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11529     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
11530     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11531   %}
11532 %}
11533 
11534 // Float to Long conversion, NaN is mapped to 0. Special version for Power8.
11535 instruct convF2L_reg_mffprd_ExEx(iRegLdst dst, regF src) %{
11536   match(Set dst (ConvF2L src));
11537   predicate(VM_Version::has_mtfprd());
11538   ins_cost(DEFAULT_COST);
11539 
11540   expand %{
11541     regF tmpF;
11542     flagsReg crx;
11543     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11544     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11545     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
11546   %}
11547 %}
11548 
11549 instruct convD2LRaw_regD(regD dst, regD src) %{
11550   // no match-rule, false predicate
11551   effect(DEF dst, USE src);
11552   predicate(false);
11553 
11554   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
11555   size(4);
11556   ins_encode %{
11557     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
11558     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
11559   %}
11560   ins_pipe(pipe_class_default);
11561 %}
11562 
11563 // Double to Long conversion, NaN is mapped to 0.
11564 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
11565   match(Set dst (ConvD2L src));
11566   predicate(!VM_Version::has_mtfprd());
11567   ins_cost(DEFAULT_COST);
11568 
11569   expand %{
11570     regD tmpD;
11571     stackSlotL tmpS;
11572     flagsReg crx;
11573     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11574     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11575     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
11576     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11577   %}
11578 %}
11579 
11580 // Double to Long conversion, NaN is mapped to 0. Special version for Power8.
11581 instruct convD2L_reg_mffprd_ExEx(iRegLdst dst, regD src) %{
11582   match(Set dst (ConvD2L src));
11583   predicate(VM_Version::has_mtfprd());
11584   ins_cost(DEFAULT_COST);
11585 
11586   expand %{
11587     regD tmpD;
11588     flagsReg crx;
11589     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11590     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11591     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
11592   %}
11593 %}
11594 
11595 // Convert to Float
11596 
11597 // Placed here as needed in expand.
11598 instruct convL2DRaw_regD(regD dst, regD src) %{
11599   // no match-rule, false predicate
11600   effect(DEF dst, USE src);
11601   predicate(false);
11602 
11603   format %{ "FCFID $dst, $src \t// convL2D" %}
11604   size(4);
11605   ins_encode %{
11606     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11607     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
11608   %}
11609   ins_pipe(pipe_class_default);
11610 %}
11611 
11612 // Placed here as needed in expand.
11613 instruct convD2F_reg(regF dst, regD src) %{
11614   match(Set dst (ConvD2F src));
11615   format %{ "FRSP    $dst, $src \t// convD2F" %}
11616   size(4);
11617   ins_encode %{
11618     // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
11619     __ frsp($dst$$FloatRegister, $src$$FloatRegister);
11620   %}
11621   ins_pipe(pipe_class_default);
11622 %}
11623 
11624 // Integer to Float conversion.
11625 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
11626   match(Set dst (ConvI2F src));
11627   predicate(!VM_Version::has_fcfids());
11628   ins_cost(DEFAULT_COST);
11629 
11630   expand %{
11631     iRegLdst tmpL;
11632     stackSlotL tmpS;
11633     regD tmpD;
11634     regD tmpD2;
11635     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11636     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11637     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11638     convL2DRaw_regD(tmpD2, tmpD);        // Convert to double.
11639     convD2F_reg(dst, tmpD2);             // Convert double to float.
11640   %}
11641 %}
11642 
11643 instruct convL2FRaw_regF(regF dst, regD src) %{
11644   // no match-rule, false predicate
11645   effect(DEF dst, USE src);
11646   predicate(false);
11647 
11648   format %{ "FCFIDS $dst, $src \t// convL2F" %}
11649   size(4);
11650   ins_encode %{
11651     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11652     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
11653   %}
11654   ins_pipe(pipe_class_default);
11655 %}
11656 
11657 // Integer to Float conversion. Special version for Power7.
11658 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
11659   match(Set dst (ConvI2F src));
11660   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11661   ins_cost(DEFAULT_COST);
11662 
11663   expand %{
11664     iRegLdst tmpL;
11665     stackSlotL tmpS;
11666     regD tmpD;
11667     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11668     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11669     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11670     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11671   %}
11672 %}
11673 
11674 // Integer to Float conversion. Special version for Power8.
11675 instruct convI2F_ireg_mtfprd_Ex(regF dst, iRegIsrc src) %{
11676   match(Set dst (ConvI2F src));
11677   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11678   ins_cost(DEFAULT_COST);
11679 
11680   expand %{
11681     regD tmpD;
11682     moveI2D_reg(tmpD, src);
11683     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11684   %}
11685 %}
11686 
11687 // L2F to avoid runtime call.
11688 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
11689   match(Set dst (ConvL2F src));
11690   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11691   ins_cost(DEFAULT_COST);
11692 
11693   expand %{
11694     stackSlotL tmpS;
11695     regD tmpD;
11696     regL_to_stkL(tmpS, src);             // Store long to stack.
11697     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11698     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11699   %}
11700 %}
11701 
11702 // L2F to avoid runtime call.  Special version for Power8.
11703 instruct convL2F_ireg_mtfprd_Ex(regF dst, iRegLsrc src) %{
11704   match(Set dst (ConvL2F src));
11705   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11706   ins_cost(DEFAULT_COST);
11707 
11708   expand %{
11709     regD tmpD;
11710     moveL2D_reg(tmpD, src);
11711     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11712   %}
11713 %}
11714 
11715 // Moved up as used in expand.
11716 //instruct convD2F_reg(regF dst, regD src) %{%}
11717 
11718 // Convert to Double
11719 
11720 // Integer to Double conversion.
11721 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
11722   match(Set dst (ConvI2D src));
11723   predicate(!VM_Version::has_mtfprd());
11724   ins_cost(DEFAULT_COST);
11725 
11726   expand %{
11727     iRegLdst tmpL;
11728     stackSlotL tmpS;
11729     regD tmpD;
11730     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11731     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11732     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11733     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11734   %}
11735 %}
11736 
11737 // Integer to Double conversion. Special version for Power8.
11738 instruct convI2D_reg_mtfprd_Ex(regD dst, iRegIsrc src) %{
11739   match(Set dst (ConvI2D src));
11740   predicate(VM_Version::has_mtfprd());
11741   ins_cost(DEFAULT_COST);
11742 
11743   expand %{
11744     regD tmpD;
11745     moveI2D_reg(tmpD, src);
11746     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11747   %}
11748 %}
11749 
11750 // Long to Double conversion
11751 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
11752   match(Set dst (ConvL2D src));
11753   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
11754 
11755   expand %{
11756     regD tmpD;
11757     moveL2D_stack_reg(tmpD, src);
11758     convL2DRaw_regD(dst, tmpD);
11759   %}
11760 %}
11761 
11762 // Long to Double conversion. Special version for Power8.
11763 instruct convL2D_reg_mtfprd_Ex(regD dst, iRegLsrc src) %{
11764   match(Set dst (ConvL2D src));
11765   predicate(VM_Version::has_mtfprd());
11766   ins_cost(DEFAULT_COST);
11767 
11768   expand %{
11769     regD tmpD;
11770     moveL2D_reg(tmpD, src);
11771     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11772   %}
11773 %}
11774 
11775 instruct convF2D_reg(regD dst, regF src) %{
11776   match(Set dst (ConvF2D src));
11777   format %{ "FMR     $dst, $src \t// float->double" %}
11778   // variable size, 0 or 4
11779   ins_encode %{
11780     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11781     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
11782   %}
11783   ins_pipe(pipe_class_default);
11784 %}
11785 
11786 //----------Control Flow Instructions------------------------------------------
11787 // Compare Instructions
11788 
11789 // Compare Integers
11790 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
11791   match(Set crx (CmpI src1 src2));
11792   size(4);
11793   format %{ "CMPW    $crx, $src1, $src2" %}
11794   ins_encode %{
11795     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
11796     __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
11797   %}
11798   ins_pipe(pipe_class_compare);
11799 %}
11800 
11801 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
11802   match(Set crx (CmpI src1 src2));
11803   format %{ "CMPWI   $crx, $src1, $src2" %}
11804   size(4);
11805   ins_encode %{
11806     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
11807     __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11808   %}
11809   ins_pipe(pipe_class_compare);
11810 %}
11811 
11812 // (src1 & src2) == 0?
11813 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
11814   match(Set cr0 (CmpI (AndI src1 src2) zero));
11815   // r0 is killed
11816   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
11817   size(4);
11818   ins_encode %{
11819     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
11820     __ andi_(R0, $src1$$Register, $src2$$constant);
11821   %}
11822   ins_pipe(pipe_class_compare);
11823 %}
11824 
11825 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
11826   match(Set crx (CmpL src1 src2));
11827   format %{ "CMPD    $crx, $src1, $src2" %}
11828   size(4);
11829   ins_encode %{
11830     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
11831     __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
11832   %}
11833   ins_pipe(pipe_class_compare);
11834 %}
11835 
11836 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
11837   match(Set crx (CmpL src1 src2));
11838   format %{ "CMPDI   $crx, $src1, $src2" %}
11839   size(4);
11840   ins_encode %{
11841     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
11842     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11843   %}
11844   ins_pipe(pipe_class_compare);
11845 %}
11846 
11847 // Added CmpUL for LoopPredicate.
11848 instruct cmpUL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
11849   match(Set crx (CmpUL src1 src2));
11850   format %{ "CMPLD   $crx, $src1, $src2" %}
11851   size(4);
11852   ins_encode %{
11853     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11854     __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
11855   %}
11856   ins_pipe(pipe_class_compare);
11857 %}
11858 
11859 instruct cmpUL_reg_imm16(flagsReg crx, iRegLsrc src1, uimmL16 src2) %{
11860   match(Set crx (CmpUL src1 src2));
11861   format %{ "CMPLDI  $crx, $src1, $src2" %}
11862   size(4);
11863   ins_encode %{
11864     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
11865     __ cmpldi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11866   %}
11867   ins_pipe(pipe_class_compare);
11868 %}
11869 
11870 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
11871   match(Set cr0 (CmpL (AndL src1 src2) zero));
11872   // r0 is killed
11873   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
11874   size(4);
11875   ins_encode %{
11876     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
11877     __ and_(R0, $src1$$Register, $src2$$Register);
11878   %}
11879   ins_pipe(pipe_class_compare);
11880 %}
11881 
11882 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
11883   match(Set cr0 (CmpL (AndL src1 src2) zero));
11884   // r0 is killed
11885   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
11886   size(4);
11887   ins_encode %{
11888     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
11889     __ andi_(R0, $src1$$Register, $src2$$constant);
11890   %}
11891   ins_pipe(pipe_class_compare);
11892 %}
11893 
11894 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
11895   // no match-rule, false predicate
11896   effect(DEF dst, USE crx);
11897   predicate(false);
11898 
11899   ins_variable_size_depending_on_alignment(true);
11900 
11901   format %{ "cmovI   $crx, $dst, -1, 0, +1" %}
11902   // Worst case is branch + move + branch + move + stop, no stop without scheduler.
11903   size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
11904   ins_encode %{
11905     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
11906     Label done;
11907     // li(Rdst, 0);              // equal -> 0
11908     __ beq($crx$$CondRegister, done);
11909     __ li($dst$$Register, 1);    // greater -> +1
11910     __ bgt($crx$$CondRegister, done);
11911     __ li($dst$$Register, -1);   // unordered or less -> -1
11912     // TODO: PPC port__ endgroup_if_needed(_size == 20);
11913     __ bind(done);
11914   %}
11915   ins_pipe(pipe_class_compare);
11916 %}
11917 
11918 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
11919   // no match-rule, false predicate
11920   effect(DEF dst, USE crx);
11921   predicate(false);
11922 
11923   format %{ "CmovI    $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
11924   postalloc_expand %{
11925     //
11926     // replaces
11927     //
11928     //   region  crx
11929     //    \       |
11930     //     dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
11931     //
11932     // with
11933     //
11934     //   region
11935     //    \
11936     //     dst=loadConI16(0)
11937     //      |
11938     //      ^  region  crx
11939     //      |   \       |
11940     //      dst=cmovI_conIvalueMinus1_conIvalue1
11941     //
11942 
11943     // Create new nodes.
11944     MachNode *m1 = new loadConI16Node();
11945     MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
11946 
11947     // inputs for new nodes
11948     m1->add_req(n_region);
11949     m2->add_req(n_region, n_crx);
11950     m2->add_prec(m1);
11951 
11952     // operands for new nodes
11953     m1->_opnds[0] = op_dst;
11954     m1->_opnds[1] = new immI16Oper(0);
11955     m2->_opnds[0] = op_dst;
11956     m2->_opnds[1] = op_crx;
11957 
11958     // registers for new nodes
11959     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11960     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11961 
11962     // Insert new nodes.
11963     nodes->push(m1);
11964     nodes->push(m2);
11965   %}
11966 %}
11967 
11968 // Manifest a CmpL3 result in an integer register. Very painful.
11969 // This is the test to avoid.
11970 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
11971 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
11972   match(Set dst (CmpL3 src1 src2));
11973   ins_cost(DEFAULT_COST*5+BRANCH_COST);
11974 
11975   expand %{
11976     flagsReg tmp1;
11977     cmpL_reg_reg(tmp1, src1, src2);
11978     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
11979   %}
11980 %}
11981 
11982 // Implicit range checks.
11983 // A range check in the ideal world has one of the following shapes:
11984 //  - (If le (CmpU length index)), (IfTrue  throw exception)
11985 //  - (If lt (CmpU index length)), (IfFalse throw exception)
11986 //
11987 // Match range check 'If le (CmpU length index)'.
11988 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
11989   match(If cmp (CmpU src_length index));
11990   effect(USE labl);
11991   predicate(TrapBasedRangeChecks &&
11992             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
11993             PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
11994             (Matcher::branches_to_uncommon_trap(_leaf)));
11995 
11996   ins_is_TrapBasedCheckNode(true);
11997 
11998   format %{ "TWI     $index $cmp $src_length \t// RangeCheck => trap $labl" %}
11999   size(4);
12000   ins_encode %{
12001     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
12002     if ($cmp$$cmpcode == 0x1 /* less_equal */) {
12003       __ trap_range_check_le($src_length$$Register, $index$$constant);
12004     } else {
12005       // Both successors are uncommon traps, probability is 0.
12006       // Node got flipped during fixup flow.
12007       assert($cmp$$cmpcode == 0x9, "must be greater");
12008       __ trap_range_check_g($src_length$$Register, $index$$constant);
12009     }
12010   %}
12011   ins_pipe(pipe_class_trap);
12012 %}
12013 
12014 // Match range check 'If lt (CmpU index length)'.
12015 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
12016   match(If cmp (CmpU src_index src_length));
12017   effect(USE labl);
12018   predicate(TrapBasedRangeChecks &&
12019             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
12020             _leaf->as_If()->_prob >= PROB_ALWAYS &&
12021             (Matcher::branches_to_uncommon_trap(_leaf)));
12022 
12023   ins_is_TrapBasedCheckNode(true);
12024 
12025   format %{ "TW      $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
12026   size(4);
12027   ins_encode %{
12028     // TODO: PPC port $archOpcode(ppc64Opcode_tw);
12029     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
12030       __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
12031     } else {
12032       // Both successors are uncommon traps, probability is 0.
12033       // Node got flipped during fixup flow.
12034       assert($cmp$$cmpcode == 0x8, "must be less");
12035       __ trap_range_check_l($src_index$$Register, $src_length$$Register);
12036     }
12037   %}
12038   ins_pipe(pipe_class_trap);
12039 %}
12040 
12041 // Match range check 'If lt (CmpU index length)'.
12042 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
12043   match(If cmp (CmpU src_index length));
12044   effect(USE labl);
12045   predicate(TrapBasedRangeChecks &&
12046             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
12047             _leaf->as_If()->_prob >= PROB_ALWAYS &&
12048             (Matcher::branches_to_uncommon_trap(_leaf)));
12049 
12050   ins_is_TrapBasedCheckNode(true);
12051 
12052   format %{ "TWI     $src_index $cmp $length \t// RangeCheck => trap $labl" %}
12053   size(4);
12054   ins_encode %{
12055     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
12056     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
12057       __ trap_range_check_ge($src_index$$Register, $length$$constant);
12058     } else {
12059       // Both successors are uncommon traps, probability is 0.
12060       // Node got flipped during fixup flow.
12061       assert($cmp$$cmpcode == 0x8, "must be less");
12062       __ trap_range_check_l($src_index$$Register, $length$$constant);
12063     }
12064   %}
12065   ins_pipe(pipe_class_trap);
12066 %}
12067 
12068 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
12069   match(Set crx (CmpU src1 src2));
12070   format %{ "CMPLW   $crx, $src1, $src2 \t// unsigned" %}
12071   size(4);
12072   ins_encode %{
12073     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
12074     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
12075   %}
12076   ins_pipe(pipe_class_compare);
12077 %}
12078 
12079 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
12080   match(Set crx (CmpU src1 src2));
12081   size(4);
12082   format %{ "CMPLWI  $crx, $src1, $src2" %}
12083   ins_encode %{
12084     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
12085     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
12086   %}
12087   ins_pipe(pipe_class_compare);
12088 %}
12089 
12090 // Implicit zero checks (more implicit null checks).
12091 // No constant pool entries required.
12092 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
12093   match(If cmp (CmpN value zero));
12094   effect(USE labl);
12095   predicate(TrapBasedNullChecks &&
12096             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
12097             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
12098             Matcher::branches_to_uncommon_trap(_leaf));
12099   ins_cost(1);
12100 
12101   ins_is_TrapBasedCheckNode(true);
12102 
12103   format %{ "TDI     $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
12104   size(4);
12105   ins_encode %{
12106     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12107     if ($cmp$$cmpcode == 0xA) {
12108       __ trap_null_check($value$$Register);
12109     } else {
12110       // Both successors are uncommon traps, probability is 0.
12111       // Node got flipped during fixup flow.
12112       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
12113       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
12114     }
12115   %}
12116   ins_pipe(pipe_class_trap);
12117 %}
12118 
12119 // Compare narrow oops.
12120 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
12121   match(Set crx (CmpN src1 src2));
12122 
12123   size(4);
12124   ins_cost(2);
12125   format %{ "CMPLW   $crx, $src1, $src2 \t// compressed ptr" %}
12126   ins_encode %{
12127     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
12128     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
12129   %}
12130   ins_pipe(pipe_class_compare);
12131 %}
12132 
12133 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
12134   match(Set crx (CmpN src1 src2));
12135   // Make this more expensive than zeroCheckN_iReg_imm0.
12136   ins_cost(2);
12137 
12138   format %{ "CMPLWI  $crx, $src1, $src2 \t// compressed ptr" %}
12139   size(4);
12140   ins_encode %{
12141     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
12142     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
12143   %}
12144   ins_pipe(pipe_class_compare);
12145 %}
12146 
12147 // Implicit zero checks (more implicit null checks).
12148 // No constant pool entries required.
12149 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
12150   match(If cmp (CmpP value zero));
12151   effect(USE labl);
12152   predicate(TrapBasedNullChecks &&
12153             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
12154             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
12155             Matcher::branches_to_uncommon_trap(_leaf));
12156   ins_cost(1); // Should not be cheaper than zeroCheckN.
12157 
12158   ins_is_TrapBasedCheckNode(true);
12159 
12160   format %{ "TDI     $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
12161   size(4);
12162   ins_encode %{
12163     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12164     if ($cmp$$cmpcode == 0xA) {
12165       __ trap_null_check($value$$Register);
12166     } else {
12167       // Both successors are uncommon traps, probability is 0.
12168       // Node got flipped during fixup flow.
12169       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
12170       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
12171     }
12172   %}
12173   ins_pipe(pipe_class_trap);
12174 %}
12175 
12176 // Compare Pointers
12177 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
12178   match(Set crx (CmpP src1 src2));
12179   format %{ "CMPLD   $crx, $src1, $src2 \t// ptr" %}
12180   size(4);
12181   ins_encode %{
12182     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
12183     __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
12184   %}
12185   ins_pipe(pipe_class_compare);
12186 %}
12187 
12188 instruct cmpP_reg_null(flagsReg crx, iRegP_N2P src1, immP_0or1 src2) %{
12189   match(Set crx (CmpP src1 src2));
12190   format %{ "CMPLDI   $crx, $src1, $src2 \t// ptr" %}
12191   size(4);
12192   ins_encode %{
12193     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
12194     __ cmpldi($crx$$CondRegister, $src1$$Register, (int)((short)($src2$$constant & 0xFFFF)));
12195   %}
12196   ins_pipe(pipe_class_compare);
12197 %}
12198 
12199 // Used in postalloc expand.
12200 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
12201   // This match rule prevents reordering of node before a safepoint.
12202   // This only makes sense if this instructions is used exclusively
12203   // for the expansion of EncodeP!
12204   match(Set crx (CmpP src1 src2));
12205   predicate(false);
12206 
12207   format %{ "CMPDI   $crx, $src1, $src2" %}
12208   size(4);
12209   ins_encode %{
12210     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
12211     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
12212   %}
12213   ins_pipe(pipe_class_compare);
12214 %}
12215 
12216 //----------Float Compares----------------------------------------------------
12217 
12218 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
12219   // Needs matchrule, see cmpDUnordered.
12220   match(Set crx (CmpF src1 src2));
12221   // no match-rule, false predicate
12222   predicate(false);
12223 
12224   format %{ "cmpFUrd $crx, $src1, $src2" %}
12225   size(4);
12226   ins_encode %{
12227     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
12228     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
12229   %}
12230   ins_pipe(pipe_class_default);
12231 %}
12232 
12233 instruct cmov_bns_less(flagsReg crx) %{
12234   // no match-rule, false predicate
12235   effect(DEF crx);
12236   predicate(false);
12237 
12238   ins_variable_size_depending_on_alignment(true);
12239 
12240   format %{ "cmov    $crx" %}
12241   // Worst case is branch + move + stop, no stop without scheduler.
12242   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
12243   ins_encode %{
12244     // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
12245     Label done;
12246     __ bns($crx$$CondRegister, done);        // not unordered -> keep crx
12247     __ li(R0, 0);
12248     __ cmpwi($crx$$CondRegister, R0, 1);     // unordered -> set crx to 'less'
12249     // TODO PPC port __ endgroup_if_needed(_size == 16);
12250     __ bind(done);
12251   %}
12252   ins_pipe(pipe_class_default);
12253 %}
12254 
12255 // Compare floating, generate condition code.
12256 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
12257   // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
12258   //
12259   // The following code sequence occurs a lot in mpegaudio:
12260   //
12261   // block BXX:
12262   // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
12263   //    cmpFUrd CCR6, F11, F9
12264   // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
12265   //    cmov CCR6
12266   // 8: instruct branchConSched:
12267   //    B_FARle CCR6, B56  P=0.500000 C=-1.000000
12268   match(Set crx (CmpF src1 src2));
12269   ins_cost(DEFAULT_COST+BRANCH_COST);
12270 
12271   format %{ "CmpF    $crx, $src1, $src2 \t// postalloc expanded" %}
12272   postalloc_expand %{
12273     //
12274     // replaces
12275     //
12276     //   region  src1  src2
12277     //    \       |     |
12278     //     crx=cmpF_reg_reg
12279     //
12280     // with
12281     //
12282     //   region  src1  src2
12283     //    \       |     |
12284     //     crx=cmpFUnordered_reg_reg
12285     //      |
12286     //      ^  region
12287     //      |   \
12288     //      crx=cmov_bns_less
12289     //
12290 
12291     // Create new nodes.
12292     MachNode *m1 = new cmpFUnordered_reg_regNode();
12293     MachNode *m2 = new cmov_bns_lessNode();
12294 
12295     // inputs for new nodes
12296     m1->add_req(n_region, n_src1, n_src2);
12297     m2->add_req(n_region);
12298     m2->add_prec(m1);
12299 
12300     // operands for new nodes
12301     m1->_opnds[0] = op_crx;
12302     m1->_opnds[1] = op_src1;
12303     m1->_opnds[2] = op_src2;
12304     m2->_opnds[0] = op_crx;
12305 
12306     // registers for new nodes
12307     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12308     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12309 
12310     // Insert new nodes.
12311     nodes->push(m1);
12312     nodes->push(m2);
12313   %}
12314 %}
12315 
12316 // Compare float, generate -1,0,1
12317 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
12318   match(Set dst (CmpF3 src1 src2));
12319   ins_cost(DEFAULT_COST*5+BRANCH_COST);
12320 
12321   expand %{
12322     flagsReg tmp1;
12323     cmpFUnordered_reg_reg(tmp1, src1, src2);
12324     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12325   %}
12326 %}
12327 
12328 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
12329   // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
12330   // node right before the conditional move using it.
12331   // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
12332   // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
12333   // crashed in register allocation where the flags Reg between cmpDUnoredered and a
12334   // conditional move was supposed to be spilled.
12335   match(Set crx (CmpD src1 src2));
12336   // False predicate, shall not be matched.
12337   predicate(false);
12338 
12339   format %{ "cmpFUrd $crx, $src1, $src2" %}
12340   size(4);
12341   ins_encode %{
12342     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
12343     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
12344   %}
12345   ins_pipe(pipe_class_default);
12346 %}
12347 
12348 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
12349   match(Set crx (CmpD src1 src2));
12350   ins_cost(DEFAULT_COST+BRANCH_COST);
12351 
12352   format %{ "CmpD    $crx, $src1, $src2 \t// postalloc expanded" %}
12353   postalloc_expand %{
12354     //
12355     // replaces
12356     //
12357     //   region  src1  src2
12358     //    \       |     |
12359     //     crx=cmpD_reg_reg
12360     //
12361     // with
12362     //
12363     //   region  src1  src2
12364     //    \       |     |
12365     //     crx=cmpDUnordered_reg_reg
12366     //      |
12367     //      ^  region
12368     //      |   \
12369     //      crx=cmov_bns_less
12370     //
12371 
12372     // create new nodes
12373     MachNode *m1 = new cmpDUnordered_reg_regNode();
12374     MachNode *m2 = new cmov_bns_lessNode();
12375 
12376     // inputs for new nodes
12377     m1->add_req(n_region, n_src1, n_src2);
12378     m2->add_req(n_region);
12379     m2->add_prec(m1);
12380 
12381     // operands for new nodes
12382     m1->_opnds[0] = op_crx;
12383     m1->_opnds[1] = op_src1;
12384     m1->_opnds[2] = op_src2;
12385     m2->_opnds[0] = op_crx;
12386 
12387     // registers for new nodes
12388     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12389     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12390 
12391     // Insert new nodes.
12392     nodes->push(m1);
12393     nodes->push(m2);
12394   %}
12395 %}
12396 
12397 // Compare double, generate -1,0,1
12398 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12399   match(Set dst (CmpD3 src1 src2));
12400   ins_cost(DEFAULT_COST*5+BRANCH_COST);
12401 
12402   expand %{
12403     flagsReg tmp1;
12404     cmpDUnordered_reg_reg(tmp1, src1, src2);
12405     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12406   %}
12407 %}
12408 
12409 //----------Branches---------------------------------------------------------
12410 // Jump
12411 
12412 // Direct Branch.
12413 instruct branch(label labl) %{
12414   match(Goto);
12415   effect(USE labl);
12416   ins_cost(BRANCH_COST);
12417 
12418   format %{ "B       $labl" %}
12419   size(4);
12420   ins_encode %{
12421     // TODO: PPC port $archOpcode(ppc64Opcode_b);
12422      Label d;    // dummy
12423      __ bind(d);
12424      Label* p = $labl$$label;
12425      // `p' is `NULL' when this encoding class is used only to
12426      // determine the size of the encoded instruction.
12427      Label& l = (NULL == p)? d : *(p);
12428      __ b(l);
12429   %}
12430   ins_pipe(pipe_class_default);
12431 %}
12432 
12433 // Conditional Near Branch
12434 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
12435   // Same match rule as `branchConFar'.
12436   match(If cmp crx);
12437   effect(USE lbl);
12438   ins_cost(BRANCH_COST);
12439 
12440   // If set to 1 this indicates that the current instruction is a
12441   // short variant of a long branch. This avoids using this
12442   // instruction in first-pass matching. It will then only be used in
12443   // the `Shorten_branches' pass.
12444   ins_short_branch(1);
12445 
12446   format %{ "B$cmp     $crx, $lbl" %}
12447   size(4);
12448   ins_encode( enc_bc(crx, cmp, lbl) );
12449   ins_pipe(pipe_class_default);
12450 %}
12451 
12452 // This is for cases when the ppc64 `bc' instruction does not
12453 // reach far enough. So we emit a far branch here, which is more
12454 // expensive.
12455 //
12456 // Conditional Far Branch
12457 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
12458   // Same match rule as `branchCon'.
12459   match(If cmp crx);
12460   effect(USE crx, USE lbl);
12461   predicate(!false /* TODO: PPC port HB_Schedule*/);
12462   // Higher cost than `branchCon'.
12463   ins_cost(5*BRANCH_COST);
12464 
12465   // This is not a short variant of a branch, but the long variant.
12466   ins_short_branch(0);
12467 
12468   format %{ "B_FAR$cmp $crx, $lbl" %}
12469   size(8);
12470   ins_encode( enc_bc_far(crx, cmp, lbl) );
12471   ins_pipe(pipe_class_default);
12472 %}
12473 
12474 // Conditional Branch used with Power6 scheduler (can be far or short).
12475 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
12476   // Same match rule as `branchCon'.
12477   match(If cmp crx);
12478   effect(USE crx, USE lbl);
12479   predicate(false /* TODO: PPC port HB_Schedule*/);
12480   // Higher cost than `branchCon'.
12481   ins_cost(5*BRANCH_COST);
12482 
12483   // Actually size doesn't depend on alignment but on shortening.
12484   ins_variable_size_depending_on_alignment(true);
12485   // long variant.
12486   ins_short_branch(0);
12487 
12488   format %{ "B_FAR$cmp $crx, $lbl" %}
12489   size(8); // worst case
12490   ins_encode( enc_bc_short_far(crx, cmp, lbl) );
12491   ins_pipe(pipe_class_default);
12492 %}
12493 
12494 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
12495   match(CountedLoopEnd cmp crx);
12496   effect(USE labl);
12497   ins_cost(BRANCH_COST);
12498 
12499   // short variant.
12500   ins_short_branch(1);
12501 
12502   format %{ "B$cmp     $crx, $labl \t// counted loop end" %}
12503   size(4);
12504   ins_encode( enc_bc(crx, cmp, labl) );
12505   ins_pipe(pipe_class_default);
12506 %}
12507 
12508 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
12509   match(CountedLoopEnd cmp crx);
12510   effect(USE labl);
12511   predicate(!false /* TODO: PPC port HB_Schedule */);
12512   ins_cost(BRANCH_COST);
12513 
12514   // Long variant.
12515   ins_short_branch(0);
12516 
12517   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
12518   size(8);
12519   ins_encode( enc_bc_far(crx, cmp, labl) );
12520   ins_pipe(pipe_class_default);
12521 %}
12522 
12523 // Conditional Branch used with Power6 scheduler (can be far or short).
12524 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
12525   match(CountedLoopEnd cmp crx);
12526   effect(USE labl);
12527   predicate(false /* TODO: PPC port HB_Schedule */);
12528   // Higher cost than `branchCon'.
12529   ins_cost(5*BRANCH_COST);
12530 
12531   // Actually size doesn't depend on alignment but on shortening.
12532   ins_variable_size_depending_on_alignment(true);
12533   // Long variant.
12534   ins_short_branch(0);
12535 
12536   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
12537   size(8); // worst case
12538   ins_encode( enc_bc_short_far(crx, cmp, labl) );
12539   ins_pipe(pipe_class_default);
12540 %}
12541 
12542 // ============================================================================
12543 // Java runtime operations, intrinsics and other complex operations.
12544 
12545 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12546 // array for an instance of the superklass. Set a hidden internal cache on a
12547 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12548 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
12549 //
12550 // GL TODO: Improve this.
12551 // - result should not be a TEMP
12552 // - Add match rule as on sparc avoiding additional Cmp.
12553 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
12554                              iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
12555   match(Set result (PartialSubtypeCheck subklass superklass));
12556   effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
12557   ins_cost(DEFAULT_COST*10);
12558 
12559   format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
12560   ins_encode %{
12561     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12562     __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
12563                                      $tmp_klass$$Register, NULL, $result$$Register);
12564   %}
12565   ins_pipe(pipe_class_default);
12566 %}
12567 
12568 // inlined locking and unlocking
12569 
12570 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{
12571   match(Set crx (FastLock oop box));
12572   effect(TEMP tmp1, TEMP tmp2);
12573   predicate(!Compile::current()->use_rtm());
12574 
12575   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2" %}
12576   ins_encode %{
12577     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12578     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12579                                  $tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0,
12580                                  UseBiasedLocking && !UseOptoBiasInlining);
12581     // If locking was successfull, crx should indicate 'EQ'.
12582     // The compiler generates a branch to the runtime call to
12583     // _complete_monitor_locking_Java for the case where crx is 'NE'.
12584   %}
12585   ins_pipe(pipe_class_compare);
12586 %}
12587 
12588 // Separate version for TM. Use bound register for box to enable USE_KILL.
12589 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12590   match(Set crx (FastLock oop box));
12591   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
12592   predicate(Compile::current()->use_rtm());
12593 
12594   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
12595   ins_encode %{
12596     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12597     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12598                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12599                                  /*Biased Locking*/ false,
12600                                  _rtm_counters, _stack_rtm_counters,
12601                                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12602                                  /*TM*/ true, ra_->C->profile_rtm());
12603     // If locking was successfull, crx should indicate 'EQ'.
12604     // The compiler generates a branch to the runtime call to
12605     // _complete_monitor_locking_Java for the case where crx is 'NE'.
12606   %}
12607   ins_pipe(pipe_class_compare);
12608 %}
12609 
12610 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12611   match(Set crx (FastUnlock oop box));
12612   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
12613   predicate(!Compile::current()->use_rtm());
12614 
12615   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2" %}
12616   ins_encode %{
12617     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12618     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12619                                    $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12620                                    UseBiasedLocking && !UseOptoBiasInlining,
12621                                    false);
12622     // If unlocking was successfull, crx should indicate 'EQ'.
12623     // The compiler generates a branch to the runtime call to
12624     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
12625   %}
12626   ins_pipe(pipe_class_compare);
12627 %}
12628 
12629 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12630   match(Set crx (FastUnlock oop box));
12631   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
12632   predicate(Compile::current()->use_rtm());
12633 
12634   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2 (TM)" %}
12635   ins_encode %{
12636     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12637     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12638                                    $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12639                                    /*Biased Locking*/ false, /*TM*/ true);
12640     // If unlocking was successfull, crx should indicate 'EQ'.
12641     // The compiler generates a branch to the runtime call to
12642     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
12643   %}
12644   ins_pipe(pipe_class_compare);
12645 %}
12646 
12647 // Align address.
12648 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
12649   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
12650 
12651   format %{ "ANDDI   $dst, $src, $mask \t// next aligned address" %}
12652   size(4);
12653   ins_encode %{
12654     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
12655     __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
12656   %}
12657   ins_pipe(pipe_class_default);
12658 %}
12659 
12660 // Array size computation.
12661 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
12662   match(Set dst (SubL (CastP2X end) (CastP2X start)));
12663 
12664   format %{ "SUB     $dst, $end, $start \t// array size in bytes" %}
12665   size(4);
12666   ins_encode %{
12667     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
12668     __ subf($dst$$Register, $start$$Register, $end$$Register);
12669   %}
12670   ins_pipe(pipe_class_default);
12671 %}
12672 
12673 // Clear-array with constant short array length. The versions below can use dcbz with cnt > 30.
12674 instruct inlineCallClearArrayShort(immLmax30 cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
12675   match(Set dummy (ClearArray cnt base));
12676   effect(USE_KILL base, KILL ctr);
12677   ins_cost(2 * MEMORY_REF_COST);
12678 
12679   format %{ "ClearArray $cnt, $base" %}
12680   ins_encode %{
12681     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12682     __ clear_memory_constlen($base$$Register, $cnt$$constant, R0); // kills base, R0
12683   %}
12684   ins_pipe(pipe_class_default);
12685 %}
12686 
12687 // Clear-array with constant large array length.
12688 instruct inlineCallClearArrayLarge(immL cnt, rarg2RegP base, Universe dummy, iRegLdst tmp, regCTR ctr) %{
12689   match(Set dummy (ClearArray cnt base));
12690   effect(USE_KILL base, TEMP tmp, KILL ctr);
12691   ins_cost(3 * MEMORY_REF_COST);
12692 
12693   format %{ "ClearArray $cnt, $base \t// KILL $tmp" %}
12694   ins_encode %{
12695     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12696     __ clear_memory_doubleword($base$$Register, $tmp$$Register, R0, $cnt$$constant); // kills base, R0
12697   %}
12698   ins_pipe(pipe_class_default);
12699 %}
12700 
12701 // Clear-array with dynamic array length.
12702 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
12703   match(Set dummy (ClearArray cnt base));
12704   effect(USE_KILL cnt, USE_KILL base, KILL ctr);
12705   ins_cost(4 * MEMORY_REF_COST);
12706 
12707   format %{ "ClearArray $cnt, $base" %}
12708   ins_encode %{
12709     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12710     __ clear_memory_doubleword($base$$Register, $cnt$$Register, R0); // kills cnt, base, R0
12711   %}
12712   ins_pipe(pipe_class_default);
12713 %}
12714 
12715 instruct string_compareL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12716                          iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12717   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12718   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12719   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12720   ins_cost(300);
12721   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12722   ins_encode %{
12723     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12724     __ string_compare($str1$$Register, $str2$$Register,
12725                       $cnt1$$Register, $cnt2$$Register,
12726                       $tmp$$Register,
12727                       $result$$Register, StrIntrinsicNode::LL);
12728   %}
12729   ins_pipe(pipe_class_default);
12730 %}
12731 
12732 instruct string_compareU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12733                          iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12734   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12735   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12736   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12737   ins_cost(300);
12738   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12739   ins_encode %{
12740     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12741     __ string_compare($str1$$Register, $str2$$Register,
12742                       $cnt1$$Register, $cnt2$$Register,
12743                       $tmp$$Register,
12744                       $result$$Register, StrIntrinsicNode::UU);
12745   %}
12746   ins_pipe(pipe_class_default);
12747 %}
12748 
12749 instruct string_compareLU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12750                           iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12751   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12752   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12753   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12754   ins_cost(300);
12755   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12756   ins_encode %{
12757     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12758     __ string_compare($str1$$Register, $str2$$Register,
12759                       $cnt1$$Register, $cnt2$$Register,
12760                       $tmp$$Register,
12761                       $result$$Register, StrIntrinsicNode::LU);
12762   %}
12763   ins_pipe(pipe_class_default);
12764 %}
12765 
12766 instruct string_compareUL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12767                           iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12768   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12769   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12770   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12771   ins_cost(300);
12772   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12773   ins_encode %{
12774     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12775     __ string_compare($str2$$Register, $str1$$Register,
12776                       $cnt2$$Register, $cnt1$$Register,
12777                       $tmp$$Register,
12778                       $result$$Register, StrIntrinsicNode::UL);
12779   %}
12780   ins_pipe(pipe_class_default);
12781 %}
12782 
12783 instruct string_equalsL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
12784                         iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12785   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
12786   match(Set result (StrEquals (Binary str1 str2) cnt));
12787   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
12788   ins_cost(300);
12789   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
12790   ins_encode %{
12791     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12792     __ array_equals(false, $str1$$Register, $str2$$Register,
12793                     $cnt$$Register, $tmp$$Register,
12794                     $result$$Register, true /* byte */);
12795   %}
12796   ins_pipe(pipe_class_default);
12797 %}
12798 
12799 instruct string_equalsU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
12800                         iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12801   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
12802   match(Set result (StrEquals (Binary str1 str2) cnt));
12803   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
12804   ins_cost(300);
12805   format %{ "String Equals char[]  $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
12806   ins_encode %{
12807     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12808     __ array_equals(false, $str1$$Register, $str2$$Register,
12809                     $cnt$$Register, $tmp$$Register,
12810                     $result$$Register, false /* byte */);
12811   %}
12812   ins_pipe(pipe_class_default);
12813 %}
12814 
12815 instruct array_equalsB(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
12816                        iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
12817   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12818   match(Set result (AryEq ary1 ary2));
12819   effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
12820   ins_cost(300);
12821   format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
12822   ins_encode %{
12823     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12824     __ array_equals(true, $ary1$$Register, $ary2$$Register,
12825                     $tmp1$$Register, $tmp2$$Register,
12826                     $result$$Register, true /* byte */);
12827   %}
12828   ins_pipe(pipe_class_default);
12829 %}
12830 
12831 instruct array_equalsC(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
12832                        iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
12833   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12834   match(Set result (AryEq ary1 ary2));
12835   effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
12836   ins_cost(300);
12837   format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
12838   ins_encode %{
12839     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12840     __ array_equals(true, $ary1$$Register, $ary2$$Register,
12841                     $tmp1$$Register, $tmp2$$Register,
12842                     $result$$Register, false /* byte */);
12843   %}
12844   ins_pipe(pipe_class_default);
12845 %}
12846 
12847 instruct indexOf_imm1_char_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12848                              immP needleImm, immL offsetImm, immI_1 needlecntImm,
12849                              iRegIdst tmp1, iRegIdst tmp2,
12850                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12851   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12852   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12853   // Required for EA: check if it is still a type_array.
12854   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
12855   ins_cost(150);
12856 
12857   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12858             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12859 
12860   ins_encode %{
12861     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12862     immPOper *needleOper = (immPOper *)$needleImm;
12863     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12864     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12865     jchar chr;
12866 #ifdef VM_LITTLE_ENDIAN
12867     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
12868            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
12869 #else
12870     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
12871            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
12872 #endif
12873     __ string_indexof_char($result$$Register,
12874                            $haystack$$Register, $haycnt$$Register,
12875                            R0, chr,
12876                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12877   %}
12878   ins_pipe(pipe_class_compare);
12879 %}
12880 
12881 instruct indexOf_imm1_char_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12882                              immP needleImm, immL offsetImm, immI_1 needlecntImm,
12883                              iRegIdst tmp1, iRegIdst tmp2,
12884                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12885   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12886   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12887   // Required for EA: check if it is still a type_array.
12888   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
12889   ins_cost(150);
12890 
12891   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12892             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12893 
12894   ins_encode %{
12895     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12896     immPOper *needleOper = (immPOper *)$needleImm;
12897     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12898     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12899     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12900     __ string_indexof_char($result$$Register,
12901                            $haystack$$Register, $haycnt$$Register,
12902                            R0, chr,
12903                            $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
12904   %}
12905   ins_pipe(pipe_class_compare);
12906 %}
12907 
12908 instruct indexOf_imm1_char_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12909                               immP needleImm, immL offsetImm, immI_1 needlecntImm,
12910                               iRegIdst tmp1, iRegIdst tmp2,
12911                               flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12912   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12913   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12914   // Required for EA: check if it is still a type_array.
12915   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
12916   ins_cost(150);
12917 
12918   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12919             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12920 
12921   ins_encode %{
12922     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12923     immPOper *needleOper = (immPOper *)$needleImm;
12924     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12925     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12926     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12927     __ string_indexof_char($result$$Register,
12928                            $haystack$$Register, $haycnt$$Register,
12929                            R0, chr,
12930                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12931   %}
12932   ins_pipe(pipe_class_compare);
12933 %}
12934 
12935 instruct indexOf_imm1_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12936                         rscratch2RegP needle, immI_1 needlecntImm,
12937                         iRegIdst tmp1, iRegIdst tmp2,
12938                         flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12939   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12940   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12941   // Required for EA: check if it is still a type_array.
12942   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
12943             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12944             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12945   ins_cost(180);
12946 
12947   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12948             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
12949   ins_encode %{
12950     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12951     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12952     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12953     guarantee(needle_values, "sanity");
12954     jchar chr;
12955 #ifdef VM_LITTLE_ENDIAN
12956     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
12957            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
12958 #else
12959     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
12960            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
12961 #endif
12962     __ string_indexof_char($result$$Register,
12963                            $haystack$$Register, $haycnt$$Register,
12964                            R0, chr,
12965                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12966   %}
12967   ins_pipe(pipe_class_compare);
12968 %}
12969 
12970 instruct indexOf_imm1_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12971                         rscratch2RegP needle, immI_1 needlecntImm,
12972                         iRegIdst tmp1, iRegIdst tmp2,
12973                         flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12974   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12975   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12976   // Required for EA: check if it is still a type_array.
12977   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
12978             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12979             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12980   ins_cost(180);
12981 
12982   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12983             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
12984   ins_encode %{
12985     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12986     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12987     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12988     guarantee(needle_values, "sanity");
12989     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12990     __ string_indexof_char($result$$Register,
12991                            $haystack$$Register, $haycnt$$Register,
12992                            R0, chr,
12993                            $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
12994   %}
12995   ins_pipe(pipe_class_compare);
12996 %}
12997 
12998 instruct indexOf_imm1_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12999                          rscratch2RegP needle, immI_1 needlecntImm,
13000                          iRegIdst tmp1, iRegIdst tmp2,
13001                          flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
13002   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
13003   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
13004   // Required for EA: check if it is still a type_array.
13005   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
13006             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
13007             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
13008   ins_cost(180);
13009 
13010   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
13011             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
13012   ins_encode %{
13013     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13014     Node *ndl = in(operand_index($needle));  // The node that defines needle.
13015     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
13016     guarantee(needle_values, "sanity");
13017     jchar chr = (jchar)needle_values->element_value(0).as_byte();
13018     __ string_indexof_char($result$$Register,
13019                            $haystack$$Register, $haycnt$$Register,
13020                            R0, chr,
13021                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
13022   %}
13023   ins_pipe(pipe_class_compare);
13024 %}
13025 
13026 instruct indexOfChar_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
13027                        iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
13028                        flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
13029   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
13030   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
13031   ins_cost(180);
13032 
13033   format %{ "String IndexOfChar $haystack[0..$haycnt], $ch"
13034             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
13035   ins_encode %{
13036     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13037     __ string_indexof_char($result$$Register,
13038                            $haystack$$Register, $haycnt$$Register,
13039                            $ch$$Register, 0 /* this is not used if the character is already in a register */,
13040                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
13041   %}
13042   ins_pipe(pipe_class_compare);
13043 %}
13044 
13045 instruct indexOf_imm_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
13046                        iRegPsrc needle, uimmI15 needlecntImm,
13047                        iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
13048                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
13049   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
13050   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
13051          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
13052   // Required for EA: check if it is still a type_array.
13053   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
13054             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
13055             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
13056   ins_cost(250);
13057 
13058   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
13059             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
13060   ins_encode %{
13061     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13062     Node *ndl = in(operand_index($needle));  // The node that defines needle.
13063     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
13064 
13065     __ string_indexof($result$$Register,
13066                       $haystack$$Register, $haycnt$$Register,
13067                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
13068                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
13069   %}
13070   ins_pipe(pipe_class_compare);
13071 %}
13072 
13073 instruct indexOf_imm_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
13074                        iRegPsrc needle, uimmI15 needlecntImm,
13075                        iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
13076                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
13077   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
13078   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
13079          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
13080   // Required for EA: check if it is still a type_array.
13081   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
13082             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
13083             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
13084   ins_cost(250);
13085 
13086   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
13087             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
13088   ins_encode %{
13089     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13090     Node *ndl = in(operand_index($needle));  // The node that defines needle.
13091     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
13092 
13093     __ string_indexof($result$$Register,
13094                       $haystack$$Register, $haycnt$$Register,
13095                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
13096                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
13097   %}
13098   ins_pipe(pipe_class_compare);
13099 %}
13100 
13101 instruct indexOf_imm_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
13102                         iRegPsrc needle, uimmI15 needlecntImm,
13103                         iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
13104                         flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
13105   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
13106   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
13107          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
13108   // Required for EA: check if it is still a type_array.
13109   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
13110             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
13111             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
13112   ins_cost(250);
13113 
13114   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
13115             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
13116   ins_encode %{
13117     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13118     Node *ndl = in(operand_index($needle));  // The node that defines needle.
13119     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
13120 
13121     __ string_indexof($result$$Register,
13122                       $haystack$$Register, $haycnt$$Register,
13123                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
13124                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
13125   %}
13126   ins_pipe(pipe_class_compare);
13127 %}
13128 
13129 instruct indexOf_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
13130                    iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
13131                    flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
13132   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
13133   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
13134          TEMP_DEF result,
13135          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
13136   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
13137   ins_cost(300);
13138 
13139   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
13140              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
13141   ins_encode %{
13142     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13143     __ string_indexof($result$$Register,
13144                       $haystack$$Register, $haycnt$$Register,
13145                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
13146                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
13147   %}
13148   ins_pipe(pipe_class_compare);
13149 %}
13150 
13151 instruct indexOf_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
13152                    iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
13153                    flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
13154   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
13155   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
13156          TEMP_DEF result,
13157          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
13158   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
13159   ins_cost(300);
13160 
13161   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
13162              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
13163   ins_encode %{
13164     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13165     __ string_indexof($result$$Register,
13166                       $haystack$$Register, $haycnt$$Register,
13167                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
13168                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
13169   %}
13170   ins_pipe(pipe_class_compare);
13171 %}
13172 
13173 instruct indexOf_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
13174                     iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
13175                     flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
13176   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
13177   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
13178          TEMP_DEF result,
13179          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
13180   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
13181   ins_cost(300);
13182 
13183   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
13184              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
13185   ins_encode %{
13186     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13187     __ string_indexof($result$$Register,
13188                       $haystack$$Register, $haycnt$$Register,
13189                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
13190                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
13191   %}
13192   ins_pipe(pipe_class_compare);
13193 %}
13194 
13195 // char[] to byte[] compression
13196 instruct string_compress(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
13197                          iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
13198   match(Set result (StrCompressedCopy src (Binary dst len)));
13199   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
13200          USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
13201   ins_cost(300);
13202   format %{ "String Compress $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
13203   ins_encode %{
13204     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13205     Label Lskip, Ldone;
13206     __ li($result$$Register, 0);
13207     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
13208                           $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Ldone);
13209     __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
13210     __ beq(CCR0, Lskip);
13211     __ string_compress($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register, Ldone);
13212     __ bind(Lskip);
13213     __ mr($result$$Register, $len$$Register);
13214     __ bind(Ldone);
13215   %}
13216   ins_pipe(pipe_class_default);
13217 %}
13218 
13219 // byte[] to char[] inflation
13220 instruct string_inflate(Universe dummy, rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegLdst tmp1,
13221                         iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
13222   match(Set dummy (StrInflatedCopy src (Binary dst len)));
13223   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
13224   ins_cost(300);
13225   format %{ "String Inflate $src,$dst,$len \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
13226   ins_encode %{
13227     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13228     Label Ldone;
13229     __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
13230                          $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
13231     __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
13232     __ beq(CCR0, Ldone);
13233     __ string_inflate($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register);
13234     __ bind(Ldone);
13235   %}
13236   ins_pipe(pipe_class_default);
13237 %}
13238 
13239 // StringCoding.java intrinsics
13240 instruct has_negatives(rarg1RegP ary1, iRegIsrc len, iRegIdst result, iRegLdst tmp1, iRegLdst tmp2,
13241                        regCTR ctr, flagsRegCR0 cr0)
13242 %{
13243   match(Set result (HasNegatives ary1 len));
13244   effect(TEMP_DEF result, USE_KILL ary1, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0);
13245   ins_cost(300);
13246   format %{ "has negatives byte[] $ary1,$len -> $result \t// KILL $tmp1, $tmp2" %}
13247   ins_encode %{
13248     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13249     __ has_negatives($ary1$$Register, $len$$Register, $result$$Register,
13250                      $tmp1$$Register, $tmp2$$Register);
13251   %}
13252   ins_pipe(pipe_class_default);
13253 %}
13254 
13255 // encode char[] to byte[] in ISO_8859_1
13256 instruct encode_iso_array(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
13257                           iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
13258   match(Set result (EncodeISOArray src (Binary dst len)));
13259   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
13260          USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
13261   ins_cost(300);
13262   format %{ "Encode array $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
13263   ins_encode %{
13264     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13265     Label Lslow, Lfailure1, Lfailure2, Ldone;
13266     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
13267                           $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Lfailure1);
13268     __ rldicl_($result$$Register, $len$$Register, 0, 64-3); // Remaining characters.
13269     __ beq(CCR0, Ldone);
13270     __ bind(Lslow);
13271     __ string_compress($src$$Register, $dst$$Register, $result$$Register, $tmp2$$Register, Lfailure2);
13272     __ li($result$$Register, 0);
13273     __ b(Ldone);
13274 
13275     __ bind(Lfailure1);
13276     __ mr($result$$Register, $len$$Register);
13277     __ mfctr($tmp1$$Register);
13278     __ rldimi_($result$$Register, $tmp1$$Register, 3, 0); // Remaining characters.
13279     __ beq(CCR0, Ldone);
13280     __ b(Lslow);
13281 
13282     __ bind(Lfailure2);
13283     __ mfctr($result$$Register); // Remaining characters.
13284 
13285     __ bind(Ldone);
13286     __ subf($result$$Register, $result$$Register, $len$$Register);
13287   %}
13288   ins_pipe(pipe_class_default);
13289 %}
13290 
13291 
13292 //---------- Min/Max Instructions ---------------------------------------------
13293 
13294 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
13295   match(Set dst (MinI src1 src2));
13296   ins_cost(DEFAULT_COST*6);
13297 
13298   expand %{
13299     iRegLdst src1s;
13300     iRegLdst src2s;
13301     iRegLdst diff;
13302     iRegLdst sm;
13303     iRegLdst doz; // difference or zero
13304     convI2L_reg(src1s, src1); // Ensure proper sign extension.
13305     convI2L_reg(src2s, src2); // Ensure proper sign extension.
13306     subL_reg_reg(diff, src2s, src1s);
13307     // Need to consider >=33 bit result, therefore we need signmaskL.
13308     signmask64L_regL(sm, diff);
13309     andL_reg_reg(doz, diff, sm); // <=0
13310     addI_regL_regL(dst, doz, src1s);
13311   %}
13312 %}
13313 
13314 instruct minI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
13315   match(Set dst (MinI src1 src2));
13316   effect(KILL cr0);
13317   predicate(VM_Version::has_isel());
13318   ins_cost(DEFAULT_COST*2);
13319 
13320   ins_encode %{
13321     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13322     __ cmpw(CCR0, $src1$$Register, $src2$$Register);
13323     __ isel($dst$$Register, CCR0, Assembler::less, /*invert*/false, $src1$$Register, $src2$$Register);
13324   %}
13325   ins_pipe(pipe_class_default);
13326 %}
13327 
13328 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
13329   match(Set dst (MaxI src1 src2));
13330   ins_cost(DEFAULT_COST*6);
13331 
13332   expand %{
13333     iRegLdst src1s;
13334     iRegLdst src2s;
13335     iRegLdst diff;
13336     iRegLdst sm;
13337     iRegLdst doz; // difference or zero
13338     convI2L_reg(src1s, src1); // Ensure proper sign extension.
13339     convI2L_reg(src2s, src2); // Ensure proper sign extension.
13340     subL_reg_reg(diff, src2s, src1s);
13341     // Need to consider >=33 bit result, therefore we need signmaskL.
13342     signmask64L_regL(sm, diff);
13343     andcL_reg_reg(doz, diff, sm); // >=0
13344     addI_regL_regL(dst, doz, src1s);
13345   %}
13346 %}
13347 
13348 instruct maxI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
13349   match(Set dst (MaxI src1 src2));
13350   effect(KILL cr0);
13351   predicate(VM_Version::has_isel());
13352   ins_cost(DEFAULT_COST*2);
13353 
13354   ins_encode %{
13355     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13356     __ cmpw(CCR0, $src1$$Register, $src2$$Register);
13357     __ isel($dst$$Register, CCR0, Assembler::greater, /*invert*/false, $src1$$Register, $src2$$Register);
13358   %}
13359   ins_pipe(pipe_class_default);
13360 %}
13361 
13362 //---------- Population Count Instructions ------------------------------------
13363 
13364 // Popcnt for Power7.
13365 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
13366   match(Set dst (PopCountI src));
13367   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
13368   ins_cost(DEFAULT_COST);
13369 
13370   format %{ "POPCNTW $dst, $src" %}
13371   size(4);
13372   ins_encode %{
13373     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
13374     __ popcntw($dst$$Register, $src$$Register);
13375   %}
13376   ins_pipe(pipe_class_default);
13377 %}
13378 
13379 // Popcnt for Power7.
13380 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
13381   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
13382   match(Set dst (PopCountL src));
13383   ins_cost(DEFAULT_COST);
13384 
13385   format %{ "POPCNTD $dst, $src" %}
13386   size(4);
13387   ins_encode %{
13388     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
13389     __ popcntd($dst$$Register, $src$$Register);
13390   %}
13391   ins_pipe(pipe_class_default);
13392 %}
13393 
13394 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
13395   match(Set dst (CountLeadingZerosI src));
13396   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
13397   ins_cost(DEFAULT_COST);
13398 
13399   format %{ "CNTLZW  $dst, $src" %}
13400   size(4);
13401   ins_encode %{
13402     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
13403     __ cntlzw($dst$$Register, $src$$Register);
13404   %}
13405   ins_pipe(pipe_class_default);
13406 %}
13407 
13408 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
13409   match(Set dst (CountLeadingZerosL src));
13410   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
13411   ins_cost(DEFAULT_COST);
13412 
13413   format %{ "CNTLZD  $dst, $src" %}
13414   size(4);
13415   ins_encode %{
13416     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
13417     __ cntlzd($dst$$Register, $src$$Register);
13418   %}
13419   ins_pipe(pipe_class_default);
13420 %}
13421 
13422 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
13423   // no match-rule, false predicate
13424   effect(DEF dst, USE src);
13425   predicate(false);
13426 
13427   format %{ "CNTLZD  $dst, $src" %}
13428   size(4);
13429   ins_encode %{
13430     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
13431     __ cntlzd($dst$$Register, $src$$Register);
13432   %}
13433   ins_pipe(pipe_class_default);
13434 %}
13435 
13436 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
13437   match(Set dst (CountTrailingZerosI src));
13438   predicate(UseCountLeadingZerosInstructionsPPC64);
13439   ins_cost(DEFAULT_COST);
13440 
13441   expand %{
13442     immI16 imm1 %{ (int)-1 %}
13443     immI16 imm2 %{ (int)32 %}
13444     immI_minus1 m1 %{ -1 %}
13445     iRegIdst tmpI1;
13446     iRegIdst tmpI2;
13447     iRegIdst tmpI3;
13448     addI_reg_imm16(tmpI1, src, imm1);
13449     andcI_reg_reg(tmpI2, src, m1, tmpI1);
13450     countLeadingZerosI(tmpI3, tmpI2);
13451     subI_imm16_reg(dst, imm2, tmpI3);
13452   %}
13453 %}
13454 
13455 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
13456   match(Set dst (CountTrailingZerosL src));
13457   predicate(UseCountLeadingZerosInstructionsPPC64);
13458   ins_cost(DEFAULT_COST);
13459 
13460   expand %{
13461     immL16 imm1 %{ (long)-1 %}
13462     immI16 imm2 %{ (int)64 %}
13463     iRegLdst tmpL1;
13464     iRegLdst tmpL2;
13465     iRegIdst tmpL3;
13466     addL_reg_imm16(tmpL1, src, imm1);
13467     andcL_reg_reg(tmpL2, tmpL1, src);
13468     countLeadingZerosL(tmpL3, tmpL2);
13469     subI_imm16_reg(dst, imm2, tmpL3);
13470  %}
13471 %}
13472 
13473 // Expand nodes for byte_reverse_int.
13474 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
13475   effect(DEF dst, USE src, USE pos, USE shift);
13476   predicate(false);
13477 
13478   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
13479   size(4);
13480   ins_encode %{
13481     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
13482     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
13483   %}
13484   ins_pipe(pipe_class_default);
13485 %}
13486 
13487 // As insrwi_a, but with USE_DEF.
13488 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
13489   effect(USE_DEF dst, USE src, USE pos, USE shift);
13490   predicate(false);
13491 
13492   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
13493   size(4);
13494   ins_encode %{
13495     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
13496     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
13497   %}
13498   ins_pipe(pipe_class_default);
13499 %}
13500 
13501 // Just slightly faster than java implementation.
13502 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
13503   match(Set dst (ReverseBytesI src));
13504   ins_cost(7*DEFAULT_COST);
13505 
13506   expand %{
13507     immI16 imm24 %{ (int) 24 %}
13508     immI16 imm16 %{ (int) 16 %}
13509     immI16  imm8 %{ (int)  8 %}
13510     immI16  imm4 %{ (int)  4 %}
13511     immI16  imm0 %{ (int)  0 %}
13512     iRegLdst tmpI1;
13513     iRegLdst tmpI2;
13514     iRegLdst tmpI3;
13515 
13516     urShiftI_reg_imm(tmpI1, src, imm24);
13517     insrwi_a(dst, tmpI1, imm24, imm8);
13518     urShiftI_reg_imm(tmpI2, src, imm16);
13519     insrwi(dst, tmpI2, imm8, imm16);
13520     urShiftI_reg_imm(tmpI3, src, imm8);
13521     insrwi(dst, tmpI3, imm8, imm8);
13522     insrwi(dst, src, imm0, imm8);
13523   %}
13524 %}
13525 
13526 instruct bytes_reverse_long_Ex(iRegLdst dst, iRegLsrc src) %{
13527   match(Set dst (ReverseBytesL src));
13528   ins_cost(15*DEFAULT_COST);
13529 
13530   expand %{
13531     immI16 imm56 %{ (int) 56 %}
13532     immI16 imm48 %{ (int) 48 %}
13533     immI16 imm40 %{ (int) 40 %}
13534     immI16 imm32 %{ (int) 32 %}
13535     immI16 imm24 %{ (int) 24 %}
13536     immI16 imm16 %{ (int) 16 %}
13537     immI16  imm8 %{ (int)  8 %}
13538     immI16  imm0 %{ (int)  0 %}
13539     iRegLdst tmpL1;
13540     iRegLdst tmpL2;
13541     iRegLdst tmpL3;
13542     iRegLdst tmpL4;
13543     iRegLdst tmpL5;
13544     iRegLdst tmpL6;
13545 
13546                                         // src   : |a|b|c|d|e|f|g|h|
13547     rldicl(tmpL1, src, imm8, imm24);    // tmpL1 : | | | |e|f|g|h|a|
13548     rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |a| | | |e|
13549     rldicl(tmpL3, tmpL2, imm32, imm0);  // tmpL3 : | | | |e| | | |a|
13550     rldicl(tmpL1, src, imm16, imm24);   // tmpL1 : | | | |f|g|h|a|b|
13551     rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |b| | | |f|
13552     rldicl(tmpL4, tmpL2, imm40, imm0);  // tmpL4 : | | |f| | | |b| |
13553     orL_reg_reg(tmpL5, tmpL3, tmpL4);   // tmpL5 : | | |f|e| | |b|a|
13554     rldicl(tmpL1, src, imm24, imm24);   // tmpL1 : | | | |g|h|a|b|c|
13555     rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |c| | | |g|
13556     rldicl(tmpL3, tmpL2, imm48, imm0);  // tmpL3 : | |g| | | |c| | |
13557     rldicl(tmpL1, src, imm32, imm24);   // tmpL1 : | | | |h|a|b|c|d|
13558     rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |d| | | |h|
13559     rldicl(tmpL4, tmpL2, imm56, imm0);  // tmpL4 : |h| | | |d| | | |
13560     orL_reg_reg(tmpL6, tmpL3, tmpL4);   // tmpL6 : |h|g| | |d|c| | |
13561     orL_reg_reg(dst, tmpL5, tmpL6);     // dst   : |h|g|f|e|d|c|b|a|
13562   %}
13563 %}
13564 
13565 instruct bytes_reverse_ushort_Ex(iRegIdst dst, iRegIsrc src) %{
13566   match(Set dst (ReverseBytesUS src));
13567   ins_cost(2*DEFAULT_COST);
13568 
13569   expand %{
13570     immI16  imm16 %{ (int) 16 %}
13571     immI16   imm8 %{ (int)  8 %}
13572 
13573     urShiftI_reg_imm(dst, src, imm8);
13574     insrwi(dst, src, imm16, imm8);
13575   %}
13576 %}
13577 
13578 instruct bytes_reverse_short_Ex(iRegIdst dst, iRegIsrc src) %{
13579   match(Set dst (ReverseBytesS src));
13580   ins_cost(3*DEFAULT_COST);
13581 
13582   expand %{
13583     immI16  imm16 %{ (int) 16 %}
13584     immI16   imm8 %{ (int)  8 %}
13585     iRegLdst tmpI1;
13586 
13587     urShiftI_reg_imm(tmpI1, src, imm8);
13588     insrwi(tmpI1, src, imm16, imm8);
13589     extsh(dst, tmpI1);
13590   %}
13591 %}
13592 
13593 // Load Integer reversed byte order
13594 instruct loadI_reversed(iRegIdst dst, indirect mem) %{
13595   match(Set dst (ReverseBytesI (LoadI mem)));
13596   ins_cost(MEMORY_REF_COST);
13597 
13598   size(4);
13599   ins_encode %{
13600     __ lwbrx($dst$$Register, $mem$$Register);
13601   %}
13602   ins_pipe(pipe_class_default);
13603 %}
13604 
13605 // Load Long - aligned and reversed
13606 instruct loadL_reversed(iRegLdst dst, indirect mem) %{
13607   match(Set dst (ReverseBytesL (LoadL mem)));
13608   predicate(VM_Version::has_ldbrx());
13609   ins_cost(MEMORY_REF_COST);
13610 
13611   size(4);
13612   ins_encode %{
13613     __ ldbrx($dst$$Register, $mem$$Register);
13614   %}
13615   ins_pipe(pipe_class_default);
13616 %}
13617 
13618 // Load unsigned short / char reversed byte order
13619 instruct loadUS_reversed(iRegIdst dst, indirect mem) %{
13620   match(Set dst (ReverseBytesUS (LoadUS mem)));
13621   ins_cost(MEMORY_REF_COST);
13622 
13623   size(4);
13624   ins_encode %{
13625     __ lhbrx($dst$$Register, $mem$$Register);
13626   %}
13627   ins_pipe(pipe_class_default);
13628 %}
13629 
13630 // Load short reversed byte order
13631 instruct loadS_reversed(iRegIdst dst, indirect mem) %{
13632   match(Set dst (ReverseBytesS (LoadS mem)));
13633   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
13634 
13635   size(8);
13636   ins_encode %{
13637     __ lhbrx($dst$$Register, $mem$$Register);
13638     __ extsh($dst$$Register, $dst$$Register);
13639   %}
13640   ins_pipe(pipe_class_default);
13641 %}
13642 
13643 // Store Integer reversed byte order
13644 instruct storeI_reversed(iRegIsrc src, indirect mem) %{
13645   match(Set mem (StoreI mem (ReverseBytesI src)));
13646   ins_cost(MEMORY_REF_COST);
13647 
13648   size(4);
13649   ins_encode %{
13650     __ stwbrx($src$$Register, $mem$$Register);
13651   %}
13652   ins_pipe(pipe_class_default);
13653 %}
13654 
13655 // Store Long reversed byte order
13656 instruct storeL_reversed(iRegLsrc src, indirect mem) %{
13657   match(Set mem (StoreL mem (ReverseBytesL src)));
13658   predicate(VM_Version::has_stdbrx());
13659   ins_cost(MEMORY_REF_COST);
13660 
13661   size(4);
13662   ins_encode %{
13663     __ stdbrx($src$$Register, $mem$$Register);
13664   %}
13665   ins_pipe(pipe_class_default);
13666 %}
13667 
13668 // Store unsigned short / char reversed byte order
13669 instruct storeUS_reversed(iRegIsrc src, indirect mem) %{
13670   match(Set mem (StoreC mem (ReverseBytesUS src)));
13671   ins_cost(MEMORY_REF_COST);
13672 
13673   size(4);
13674   ins_encode %{
13675     __ sthbrx($src$$Register, $mem$$Register);
13676   %}
13677   ins_pipe(pipe_class_default);
13678 %}
13679 
13680 // Store short reversed byte order
13681 instruct storeS_reversed(iRegIsrc src, indirect mem) %{
13682   match(Set mem (StoreC mem (ReverseBytesS src)));
13683   ins_cost(MEMORY_REF_COST);
13684 
13685   size(4);
13686   ins_encode %{
13687     __ sthbrx($src$$Register, $mem$$Register);
13688   %}
13689   ins_pipe(pipe_class_default);
13690 %}
13691 
13692 instruct mtvsrwz(vecX temp1, iRegIsrc src) %{
13693   effect(DEF temp1, USE src);
13694 
13695   size(4);
13696   ins_encode %{
13697     __ mtvsrwz($temp1$$VectorSRegister, $src$$Register);
13698   %}
13699   ins_pipe(pipe_class_default);
13700 %}
13701 
13702 instruct xxspltw(vecX dst, vecX src, immI8 imm1) %{
13703   effect(DEF dst, USE src, USE imm1);
13704 
13705   size(4);
13706   ins_encode %{
13707     __ xxspltw($dst$$VectorSRegister, $src$$VectorSRegister, $imm1$$constant);
13708   %}
13709   ins_pipe(pipe_class_default);
13710 %}
13711 
13712 //---------- Replicate Vector Instructions ------------------------------------
13713 
13714 // Insrdi does replicate if src == dst.
13715 instruct repl32(iRegLdst dst) %{
13716   predicate(false);
13717   effect(USE_DEF dst);
13718 
13719   format %{ "INSRDI  $dst, #0, $dst, #32 \t// replicate" %}
13720   size(4);
13721   ins_encode %{
13722     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13723     __ insrdi($dst$$Register, $dst$$Register, 32, 0);
13724   %}
13725   ins_pipe(pipe_class_default);
13726 %}
13727 
13728 // Insrdi does replicate if src == dst.
13729 instruct repl48(iRegLdst dst) %{
13730   predicate(false);
13731   effect(USE_DEF dst);
13732 
13733   format %{ "INSRDI  $dst, #0, $dst, #48 \t// replicate" %}
13734   size(4);
13735   ins_encode %{
13736     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13737     __ insrdi($dst$$Register, $dst$$Register, 48, 0);
13738   %}
13739   ins_pipe(pipe_class_default);
13740 %}
13741 
13742 // Insrdi does replicate if src == dst.
13743 instruct repl56(iRegLdst dst) %{
13744   predicate(false);
13745   effect(USE_DEF dst);
13746 
13747   format %{ "INSRDI  $dst, #0, $dst, #56 \t// replicate" %}
13748   size(4);
13749   ins_encode %{
13750     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13751     __ insrdi($dst$$Register, $dst$$Register, 56, 0);
13752   %}
13753   ins_pipe(pipe_class_default);
13754 %}
13755 
13756 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13757   match(Set dst (ReplicateB src));
13758   predicate(n->as_Vector()->length() == 8);
13759   expand %{
13760     moveReg(dst, src);
13761     repl56(dst);
13762     repl48(dst);
13763     repl32(dst);
13764   %}
13765 %}
13766 
13767 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
13768   match(Set dst (ReplicateB zero));
13769   predicate(n->as_Vector()->length() == 8);
13770   format %{ "LI      $dst, #0 \t// replicate8B" %}
13771   size(4);
13772   ins_encode %{
13773     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13774     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13775   %}
13776   ins_pipe(pipe_class_default);
13777 %}
13778 
13779 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
13780   match(Set dst (ReplicateB src));
13781   predicate(n->as_Vector()->length() == 8);
13782   format %{ "LI      $dst, #-1 \t// replicate8B" %}
13783   size(4);
13784   ins_encode %{
13785     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13786     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13787   %}
13788   ins_pipe(pipe_class_default);
13789 %}
13790 
13791 instruct repl16B_reg_Ex(vecX dst, iRegIsrc src) %{
13792   match(Set dst (ReplicateB src));
13793   predicate(n->as_Vector()->length() == 16);
13794 
13795   expand %{
13796     iRegLdst tmpL;
13797     vecX tmpV;
13798     immI8  imm1 %{ (int)  1 %}
13799     moveReg(tmpL, src);
13800     repl56(tmpL);
13801     repl48(tmpL);
13802     mtvsrwz(tmpV, tmpL);
13803     xxspltw(dst, tmpV, imm1);
13804   %}
13805 %}
13806 
13807 instruct repl16B_immI0(vecX dst, immI_0 zero) %{
13808   match(Set dst (ReplicateB zero));
13809   predicate(n->as_Vector()->length() == 16);
13810 
13811   format %{ "XXLXOR      $dst, $zero \t// replicate16B" %}
13812   size(4);
13813   ins_encode %{
13814     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
13815   %}
13816   ins_pipe(pipe_class_default);
13817 %}
13818 
13819 instruct repl16B_immIminus1(vecX dst, immI_minus1 src) %{
13820   match(Set dst (ReplicateB src));
13821   predicate(n->as_Vector()->length() == 16);
13822 
13823   format %{ "XXLEQV      $dst, $src \t// replicate16B" %}
13824   size(4);
13825   ins_encode %{
13826     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
13827   %}
13828   ins_pipe(pipe_class_default);
13829 %}
13830 
13831 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13832   match(Set dst (ReplicateS src));
13833   predicate(n->as_Vector()->length() == 4);
13834   expand %{
13835     moveReg(dst, src);
13836     repl48(dst);
13837     repl32(dst);
13838   %}
13839 %}
13840 
13841 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
13842   match(Set dst (ReplicateS zero));
13843   predicate(n->as_Vector()->length() == 4);
13844   format %{ "LI      $dst, #0 \t// replicate4C" %}
13845   size(4);
13846   ins_encode %{
13847     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13848     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13849   %}
13850   ins_pipe(pipe_class_default);
13851 %}
13852 
13853 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
13854   match(Set dst (ReplicateS src));
13855   predicate(n->as_Vector()->length() == 4);
13856   format %{ "LI      $dst, -1 \t// replicate4C" %}
13857   size(4);
13858   ins_encode %{
13859     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13860     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13861   %}
13862   ins_pipe(pipe_class_default);
13863 %}
13864 
13865 instruct repl8S_reg_Ex(vecX dst, iRegIsrc src) %{
13866   match(Set dst (ReplicateS src));
13867   predicate(n->as_Vector()->length() == 8);
13868 
13869   expand %{
13870     iRegLdst tmpL;
13871     vecX tmpV;
13872     immI8  zero %{ (int)  0 %}
13873     moveReg(tmpL, src);
13874     repl48(tmpL);
13875     repl32(tmpL);
13876     mtvsrd(tmpV, tmpL);
13877     xxpermdi(dst, tmpV, tmpV, zero);
13878   %}
13879 %}
13880 
13881 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
13882   match(Set dst (ReplicateS zero));
13883   predicate(n->as_Vector()->length() == 8);
13884 
13885   format %{ "XXLXOR      $dst, $zero \t// replicate8S" %}
13886   size(4);
13887   ins_encode %{
13888     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
13889   %}
13890   ins_pipe(pipe_class_default);
13891 %}
13892 
13893 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
13894   match(Set dst (ReplicateS src));
13895   predicate(n->as_Vector()->length() == 8);
13896 
13897   format %{ "XXLEQV      $dst, $src \t// replicate16B" %}
13898   size(4);
13899   ins_encode %{
13900     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
13901   %}
13902   ins_pipe(pipe_class_default);
13903 %}
13904 
13905 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13906   match(Set dst (ReplicateI src));
13907   predicate(n->as_Vector()->length() == 2);
13908   ins_cost(2 * DEFAULT_COST);
13909   expand %{
13910     moveReg(dst, src);
13911     repl32(dst);
13912   %}
13913 %}
13914 
13915 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
13916   match(Set dst (ReplicateI zero));
13917   predicate(n->as_Vector()->length() == 2);
13918   format %{ "LI      $dst, #0 \t// replicate4C" %}
13919   size(4);
13920   ins_encode %{
13921     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13922     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13923   %}
13924   ins_pipe(pipe_class_default);
13925 %}
13926 
13927 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
13928   match(Set dst (ReplicateI src));
13929   predicate(n->as_Vector()->length() == 2);
13930   format %{ "LI      $dst, -1 \t// replicate4C" %}
13931   size(4);
13932   ins_encode %{
13933     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13934     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13935   %}
13936   ins_pipe(pipe_class_default);
13937 %}
13938 
13939 instruct repl4I_reg_Ex(vecX dst, iRegIsrc src) %{
13940   match(Set dst (ReplicateI src));
13941   predicate(n->as_Vector()->length() == 4);
13942   ins_cost(2 * DEFAULT_COST);
13943 
13944   expand %{
13945     iRegLdst tmpL;
13946     vecX tmpV;
13947     immI8  zero %{ (int)  0 %}
13948     moveReg(tmpL, src);
13949     repl32(tmpL);
13950     mtvsrd(tmpV, tmpL);
13951     xxpermdi(dst, tmpV, tmpV, zero);
13952   %}
13953 %}
13954 
13955 instruct repl4I_immI0(vecX dst, immI_0 zero) %{
13956   match(Set dst (ReplicateI zero));
13957   predicate(n->as_Vector()->length() == 4);
13958 
13959   format %{ "XXLXOR      $dst, $zero \t// replicate4I" %}
13960   size(4);
13961   ins_encode %{
13962     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
13963   %}
13964   ins_pipe(pipe_class_default);
13965 %}
13966 
13967 instruct repl4I_immIminus1(vecX dst, immI_minus1 src) %{
13968   match(Set dst (ReplicateI src));
13969   predicate(n->as_Vector()->length() == 4);
13970 
13971   format %{ "XXLEQV      $dst, $dst, $dst \t// replicate4I" %}
13972   size(4);
13973   ins_encode %{
13974     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
13975   %}
13976   ins_pipe(pipe_class_default);
13977 %}
13978 
13979 // Move float to int register via stack, replicate.
13980 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
13981   match(Set dst (ReplicateF src));
13982   predicate(n->as_Vector()->length() == 2);
13983   ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
13984   expand %{
13985     stackSlotL tmpS;
13986     iRegIdst tmpI;
13987     moveF2I_reg_stack(tmpS, src);   // Move float to stack.
13988     moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
13989     moveReg(dst, tmpI);             // Move int to long reg.
13990     repl32(dst);                    // Replicate bitpattern.
13991   %}
13992 %}
13993 
13994 // Replicate scalar constant to packed float values in Double register
13995 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
13996   match(Set dst (ReplicateF src));
13997   predicate(n->as_Vector()->length() == 2);
13998   ins_cost(5 * DEFAULT_COST);
13999 
14000   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
14001   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
14002 %}
14003 
14004 // Replicate scalar zero constant to packed float values in Double register
14005 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
14006   match(Set dst (ReplicateF zero));
14007   predicate(n->as_Vector()->length() == 2);
14008 
14009   format %{ "LI      $dst, #0 \t// replicate2F" %}
14010   ins_encode %{
14011     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14012     __ li($dst$$Register, 0x0);
14013   %}
14014   ins_pipe(pipe_class_default);
14015 %}
14016 
14017 
14018 //----------Vector Arithmetic Instructions--------------------------------------
14019 
14020 // Vector Addition Instructions
14021 
14022 instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{
14023   match(Set dst (AddVB src1 src2));
14024   predicate(n->as_Vector()->length() == 16);
14025   format %{ "VADDUBM  $dst,$src1,$src2\t// add packed16B" %}
14026   size(4);
14027   ins_encode %{
14028     __ vaddubm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14029   %}
14030   ins_pipe(pipe_class_default);
14031 %}
14032 
14033 instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{
14034   match(Set dst (AddVS src1 src2));
14035   predicate(n->as_Vector()->length() == 8);
14036   format %{ "VADDUHM  $dst,$src1,$src2\t// add packed8S" %}
14037   size(4);
14038   ins_encode %{
14039     __ vadduhm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14040   %}
14041   ins_pipe(pipe_class_default);
14042 %}
14043 
14044 instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{
14045   match(Set dst (AddVI src1 src2));
14046   predicate(n->as_Vector()->length() == 4);
14047   format %{ "VADDUWM  $dst,$src1,$src2\t// add packed4I" %}
14048   size(4);
14049   ins_encode %{
14050     __ vadduwm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14051   %}
14052   ins_pipe(pipe_class_default);
14053 %}
14054 
14055 instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{
14056   match(Set dst (AddVF src1 src2));
14057   predicate(n->as_Vector()->length() == 4);
14058   format %{ "VADDFP  $dst,$src1,$src2\t// add packed4F" %}
14059   size(4);
14060   ins_encode %{
14061     __ vaddfp($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14062   %}
14063   ins_pipe(pipe_class_default);
14064 %}
14065 
14066 instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{
14067   match(Set dst (AddVL src1 src2));
14068   predicate(n->as_Vector()->length() == 2);
14069   format %{ "VADDUDM  $dst,$src1,$src2\t// add packed2L" %}
14070   size(4);
14071   ins_encode %{
14072     __ vaddudm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14073   %}
14074   ins_pipe(pipe_class_default);
14075 %}
14076 
14077 instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{
14078   match(Set dst (AddVD src1 src2));
14079   predicate(n->as_Vector()->length() == 2);
14080   format %{ "XVADDDP  $dst,$src1,$src2\t// add packed2D" %}
14081   size(4);
14082   ins_encode %{
14083     __ xvadddp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14084   %}
14085   ins_pipe(pipe_class_default);
14086 %}
14087 
14088 // Vector Subtraction Instructions
14089 
14090 instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{
14091   match(Set dst (SubVB src1 src2));
14092   predicate(n->as_Vector()->length() == 16);
14093   format %{ "VSUBUBM  $dst,$src1,$src2\t// sub packed16B" %}
14094   size(4);
14095   ins_encode %{
14096     __ vsububm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14097   %}
14098   ins_pipe(pipe_class_default);
14099 %}
14100 
14101 instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{
14102   match(Set dst (SubVS src1 src2));
14103   predicate(n->as_Vector()->length() == 8);
14104   format %{ "VSUBUHM  $dst,$src1,$src2\t// sub packed8S" %}
14105   size(4);
14106   ins_encode %{
14107     __ vsubuhm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14108   %}
14109   ins_pipe(pipe_class_default);
14110 %}
14111 
14112 instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{
14113   match(Set dst (SubVI src1 src2));
14114   predicate(n->as_Vector()->length() == 4);
14115   format %{ "VSUBUWM  $dst,$src1,$src2\t// sub packed4I" %}
14116   size(4);
14117   ins_encode %{
14118     __ vsubuwm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14119   %}
14120   ins_pipe(pipe_class_default);
14121 %}
14122 
14123 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
14124   match(Set dst (SubVF src1 src2));
14125   predicate(n->as_Vector()->length() == 4);
14126   format %{ "VSUBFP  $dst,$src1,$src2\t// sub packed4F" %}
14127   size(4);
14128   ins_encode %{
14129     __ vsubfp($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14130   %}
14131   ins_pipe(pipe_class_default);
14132 %}
14133 
14134 instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{
14135   match(Set dst (SubVL src1 src2));
14136   predicate(n->as_Vector()->length() == 2);
14137   format %{ "VSUBUDM  $dst,$src1,$src2\t// sub packed2L" %}
14138   size(4);
14139   ins_encode %{
14140     __ vsubudm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14141   %}
14142   ins_pipe(pipe_class_default);
14143 %}
14144 
14145 instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{
14146   match(Set dst (SubVD src1 src2));
14147   predicate(n->as_Vector()->length() == 2);
14148   format %{ "XVSUBDP  $dst,$src1,$src2\t// sub packed2D" %}
14149   size(4);
14150   ins_encode %{
14151     __ xvsubdp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14152   %}
14153   ins_pipe(pipe_class_default);
14154 %}
14155 
14156 // Vector Multiplication Instructions
14157 
14158 instruct vmul8S_reg(vecX dst, vecX src1, vecX src2, vecX tmp) %{
14159   match(Set dst (MulVS src1 src2));
14160   predicate(n->as_Vector()->length() == 8);
14161   effect(TEMP tmp);
14162   format %{ "VSPLTISH  $tmp,0\t// mul packed8S" %}
14163   format %{ "VMLADDUHM  $dst,$src1,$src2\t// mul packed8S" %}
14164   size(8);
14165   ins_encode %{
14166     __ vspltish($tmp$$VectorSRegister->to_vr(), 0);
14167     __ vmladduhm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr(), $tmp$$VectorSRegister->to_vr());
14168   %}
14169   ins_pipe(pipe_class_default);
14170 %}
14171 
14172 instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{
14173   match(Set dst (MulVI src1 src2));
14174   predicate(n->as_Vector()->length() == 4);
14175   format %{ "VMULUWM  $dst,$src1,$src2\t// mul packed4I" %}
14176   size(4);
14177   ins_encode %{
14178     __ vmuluwm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14179   %}
14180   ins_pipe(pipe_class_default);
14181 %}
14182 
14183 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
14184   match(Set dst (MulVF src1 src2));
14185   predicate(n->as_Vector()->length() == 4);
14186   format %{ "XVMULSP  $dst,$src1,$src2\t// mul packed4F" %}
14187   size(4);
14188   ins_encode %{
14189     __ xvmulsp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14190   %}
14191   ins_pipe(pipe_class_default);
14192 %}
14193 
14194 instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
14195   match(Set dst (MulVD src1 src2));
14196   predicate(n->as_Vector()->length() == 2);
14197   format %{ "XVMULDP  $dst,$src1,$src2\t// mul packed2D" %}
14198   size(4);
14199   ins_encode %{
14200     __ xvmuldp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14201   %}
14202   ins_pipe(pipe_class_default);
14203 %}
14204 
14205 // Vector Division Instructions
14206 
14207 instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{
14208   match(Set dst (DivVF src1 src2));
14209   predicate(n->as_Vector()->length() == 4);
14210   format %{ "XVDIVSP  $dst,$src1,$src2\t// div packed4F" %}
14211   size(4);
14212   ins_encode %{
14213     __ xvdivsp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14214   %}
14215   ins_pipe(pipe_class_default);
14216 %}
14217 
14218 instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
14219   match(Set dst (DivVD src1 src2));
14220   predicate(n->as_Vector()->length() == 2);
14221   format %{ "XVDIVDP  $dst,$src1,$src2\t// div packed2D" %}
14222   size(4);
14223   ins_encode %{
14224     __ xvdivdp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14225   %}
14226   ins_pipe(pipe_class_default);
14227 %}
14228 
14229 // Vector Absolute Instructions
14230 
14231 instruct vabs4F_reg(vecX dst, vecX src) %{
14232   match(Set dst (AbsVF src));
14233   predicate(n->as_Vector()->length() == 4);
14234   format %{ "XVABSSP $dst,$src\t// absolute packed4F" %}
14235   size(4);
14236   ins_encode %{
14237     __ xvabssp($dst$$VectorSRegister, $src$$VectorSRegister);
14238   %}
14239   ins_pipe(pipe_class_default);
14240 %}
14241 
14242 instruct vabs2D_reg(vecX dst, vecX src) %{
14243   match(Set dst (AbsVD src));
14244   predicate(n->as_Vector()->length() == 2);
14245   format %{ "XVABSDP $dst,$src\t// absolute packed2D" %}
14246   size(4);
14247   ins_encode %{
14248     __ xvabsdp($dst$$VectorSRegister, $src$$VectorSRegister);
14249   %}
14250   ins_pipe(pipe_class_default);
14251 %}
14252 
14253 // Vector Negate Instructions
14254 
14255 instruct vneg4F_reg(vecX dst, vecX src) %{
14256   match(Set dst (NegVF src));
14257   predicate(n->as_Vector()->length() == 4);
14258   format %{ "XVNEGSP $dst,$src\t// negate packed4F" %}
14259   size(4);
14260   ins_encode %{
14261     __ xvnegsp($dst$$VectorSRegister, $src$$VectorSRegister);
14262   %}
14263   ins_pipe(pipe_class_default);
14264 %}
14265 
14266 instruct vneg2D_reg(vecX dst, vecX src) %{
14267   match(Set dst (NegVD src));
14268   predicate(n->as_Vector()->length() == 2);
14269   format %{ "XVNEGDP $dst,$src\t// negate packed2D" %}
14270   size(4);
14271   ins_encode %{
14272     __ xvnegdp($dst$$VectorSRegister, $src$$VectorSRegister);
14273   %}
14274   ins_pipe(pipe_class_default);
14275 %}
14276 
14277 // Vector Square Root Instructions
14278 
14279 instruct vsqrt4F_reg(vecX dst, vecX src) %{
14280   match(Set dst (SqrtVF src));
14281   predicate(n->as_Vector()->length() == 4);
14282   format %{ "XVSQRTSP $dst,$src\t// sqrt packed4F" %}
14283   size(4);
14284   ins_encode %{
14285     __ xvsqrtsp($dst$$VectorSRegister, $src$$VectorSRegister);
14286   %}
14287   ins_pipe(pipe_class_default);
14288 %}
14289 
14290 instruct vsqrt2D_reg(vecX dst, vecX src) %{
14291   match(Set dst (SqrtVD src));
14292   predicate(n->as_Vector()->length() == 2);
14293   format %{ "XVSQRTDP  $dst,$src\t// sqrt packed2D" %}
14294   size(4);
14295   ins_encode %{
14296     __ xvsqrtdp($dst$$VectorSRegister, $src$$VectorSRegister);
14297   %}
14298   ins_pipe(pipe_class_default);
14299 %}
14300 
14301 // Vector Population Count Instructions
14302 
14303 instruct vpopcnt4I_reg(vecX dst, vecX src) %{
14304   match(Set dst (PopCountVI src));
14305   predicate(n->as_Vector()->length() == 4);
14306   format %{ "VPOPCNTW $dst,$src\t// pop count packed4I" %}
14307   size(4);
14308   ins_encode %{
14309     __ vpopcntw($dst$$VectorSRegister->to_vr(), $src$$VectorSRegister->to_vr());
14310   %}
14311   ins_pipe(pipe_class_default);
14312 %}
14313 
14314 
14315 //----------Overflow Math Instructions-----------------------------------------
14316 
14317 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
14318 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
14319 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
14320 
14321 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
14322   match(Set cr0 (OverflowAddL op1 op2));
14323 
14324   format %{ "add_    $op1, $op2\t# overflow check long" %}
14325   ins_encode %{
14326     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14327     __ li(R0, 0);
14328     __ mtxer(R0); // clear XER.SO
14329     __ addo_(R0, $op1$$Register, $op2$$Register);
14330   %}
14331   ins_pipe(pipe_class_default);
14332 %}
14333 
14334 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
14335   match(Set cr0 (OverflowSubL op1 op2));
14336 
14337   format %{ "subfo_  R0, $op2, $op1\t# overflow check long" %}
14338   ins_encode %{
14339     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14340     __ li(R0, 0);
14341     __ mtxer(R0); // clear XER.SO
14342     __ subfo_(R0, $op2$$Register, $op1$$Register);
14343   %}
14344   ins_pipe(pipe_class_default);
14345 %}
14346 
14347 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
14348   match(Set cr0 (OverflowSubL zero op2));
14349 
14350   format %{ "nego_   R0, $op2\t# overflow check long" %}
14351   ins_encode %{
14352     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14353     __ li(R0, 0);
14354     __ mtxer(R0); // clear XER.SO
14355     __ nego_(R0, $op2$$Register);
14356   %}
14357   ins_pipe(pipe_class_default);
14358 %}
14359 
14360 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
14361   match(Set cr0 (OverflowMulL op1 op2));
14362 
14363   format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
14364   ins_encode %{
14365     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14366     __ li(R0, 0);
14367     __ mtxer(R0); // clear XER.SO
14368     __ mulldo_(R0, $op1$$Register, $op2$$Register);
14369   %}
14370   ins_pipe(pipe_class_default);
14371 %}
14372 
14373 
14374 instruct repl4F_reg_Ex(vecX dst, regF src) %{
14375   match(Set dst (ReplicateF src));
14376   predicate(n->as_Vector()->length() == 4);
14377   ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
14378   expand %{
14379     stackSlotL tmpS;
14380     iRegIdst tmpI;
14381     iRegLdst tmpL;
14382     vecX tmpV;
14383     immI8  zero %{ (int)  0 %}
14384 
14385     moveF2I_reg_stack(tmpS, src);   // Move float to stack.
14386     moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
14387     moveReg(tmpL, tmpI);             // Move int to long reg.
14388     repl32(tmpL);                    // Replicate bitpattern.
14389     mtvsrd(tmpV, tmpL);
14390     xxpermdi(dst, tmpV, tmpV, zero);
14391   %}
14392 %}
14393 
14394 instruct repl4F_immF_Ex(vecX dst, immF src, iRegLdst tmp) %{
14395   match(Set dst (ReplicateF src));
14396   predicate(n->as_Vector()->length() == 4);
14397   effect(TEMP tmp);
14398   ins_cost(10 * DEFAULT_COST);
14399 
14400   postalloc_expand( postalloc_expand_load_replF_constant_vsx(dst, src, constanttablebase, tmp) );
14401 %}
14402 
14403 instruct repl4F_immF0(vecX dst, immF_0 zero) %{
14404   match(Set dst (ReplicateF zero));
14405   predicate(n->as_Vector()->length() == 4);
14406 
14407   format %{ "XXLXOR      $dst, $zero \t// replicate4F" %}
14408   ins_encode %{
14409     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14410   %}
14411   ins_pipe(pipe_class_default);
14412 %}
14413 
14414 instruct repl2D_reg_Ex(vecX dst, regD src) %{
14415   match(Set dst (ReplicateD src));
14416   predicate(n->as_Vector()->length() == 2);
14417   expand %{
14418     stackSlotL tmpS;
14419     iRegLdst tmpL;
14420     iRegLdst tmp;
14421     vecX tmpV;
14422     immI8  zero %{ (int)  0 %}
14423     moveD2L_reg_stack(tmpS, src);
14424     moveD2L_stack_reg(tmpL, tmpS);
14425     mtvsrd(tmpV, tmpL);
14426     xxpermdi(dst, tmpV, tmpV, zero);
14427   %}
14428 %}
14429 
14430 instruct repl2D_immI0(vecX dst, immI_0 zero) %{
14431   match(Set dst (ReplicateD zero));
14432   predicate(n->as_Vector()->length() == 2);
14433 
14434   format %{ "XXLXOR      $dst, $zero \t// replicate2D" %}
14435   size(4);
14436   ins_encode %{
14437     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14438   %}
14439   ins_pipe(pipe_class_default);
14440 %}
14441 
14442 instruct repl2D_immIminus1(vecX dst, immI_minus1 src) %{
14443   match(Set dst (ReplicateD src));
14444   predicate(n->as_Vector()->length() == 2);
14445 
14446   format %{ "XXLEQV      $dst, $src \t// replicate16B" %}
14447   size(4);
14448   ins_encode %{
14449     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14450   %}
14451   ins_pipe(pipe_class_default);
14452 %}
14453 
14454 instruct mtvsrd(vecX dst, iRegLsrc src) %{
14455   predicate(false);
14456   effect(DEF dst, USE src);
14457 
14458   format %{ "MTVSRD      $dst, $src \t// Move to 16-byte register"%}
14459   size(4);
14460   ins_encode %{
14461     __ mtvsrd($dst$$VectorSRegister, $src$$Register);
14462   %}
14463   ins_pipe(pipe_class_default);
14464 %}
14465 
14466 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{
14467   effect(DEF dst, USE src, USE zero);
14468 
14469   format %{ "XXSPLATD      $dst, $src, $zero \t// Permute 16-byte register"%}
14470   size(4);
14471   ins_encode %{
14472     __ xxpermdi($dst$$VectorSRegister, $src$$VectorSRegister, $src$$VectorSRegister, $zero$$constant);
14473   %}
14474   ins_pipe(pipe_class_default);
14475 %}
14476 
14477 instruct xxpermdi(vecX dst, vecX src1, vecX src2, immI8 zero) %{
14478   effect(DEF dst, USE src1, USE src2, USE zero);
14479 
14480   format %{ "XXPERMDI      $dst, $src1, $src2, $zero \t// Permute 16-byte register"%}
14481   size(4);
14482   ins_encode %{
14483     __ xxpermdi($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister, $zero$$constant);
14484   %}
14485   ins_pipe(pipe_class_default);
14486 %}
14487 
14488 instruct repl2L_reg_Ex(vecX dst, iRegLsrc src) %{
14489   match(Set dst (ReplicateL src));
14490   predicate(n->as_Vector()->length() == 2);
14491   expand %{
14492     vecX tmpV;
14493     immI8  zero %{ (int)  0 %}
14494     mtvsrd(tmpV, src);
14495     xxpermdi(dst, tmpV, tmpV, zero);
14496   %}
14497 %}
14498 
14499 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
14500   match(Set dst (ReplicateL zero));
14501   predicate(n->as_Vector()->length() == 2);
14502 
14503   format %{ "XXLXOR      $dst, $zero \t// replicate2L" %}
14504   size(4);
14505   ins_encode %{
14506     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14507   %}
14508   ins_pipe(pipe_class_default);
14509 %}
14510 
14511 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
14512   match(Set dst (ReplicateL src));
14513   predicate(n->as_Vector()->length() == 2);
14514 
14515   format %{ "XXLEQV      $dst, $src \t// replicate16B" %}
14516   size(4);
14517   ins_encode %{
14518     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14519   %}
14520   ins_pipe(pipe_class_default);
14521 %}
14522 
14523 // ============================================================================
14524 // Safepoint Instruction
14525 
14526 instruct safePoint_poll(iRegPdst poll) %{
14527   match(SafePoint poll);
14528 
14529   // It caused problems to add the effect that r0 is killed, but this
14530   // effect no longer needs to be mentioned, since r0 is not contained
14531   // in a reg_class.
14532 
14533   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
14534   size(4);
14535   ins_encode( enc_poll(0x0, poll) );
14536   ins_pipe(pipe_class_default);
14537 %}
14538 
14539 // ============================================================================
14540 // Call Instructions
14541 
14542 // Call Java Static Instruction
14543 
14544 // Schedulable version of call static node.
14545 instruct CallStaticJavaDirect(method meth) %{
14546   match(CallStaticJava);
14547   effect(USE meth);
14548   ins_cost(CALL_COST);
14549 
14550   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
14551 
14552   format %{ "CALL,static $meth \t// ==> " %}
14553   size(4);
14554   ins_encode( enc_java_static_call(meth) );
14555   ins_pipe(pipe_class_call);
14556 %}
14557 
14558 // Call Java Dynamic Instruction
14559 
14560 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
14561 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
14562 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
14563 // The call destination must still be placed in the constant pool.
14564 instruct CallDynamicJavaDirectSched(method meth) %{
14565   match(CallDynamicJava); // To get all the data fields we need ...
14566   effect(USE meth);
14567   predicate(false);       // ... but never match.
14568 
14569   ins_field_load_ic_hi_node(loadConL_hiNode*);
14570   ins_field_load_ic_node(loadConLNode*);
14571   ins_num_consts(1 /* 1 patchable constant: call destination */);
14572 
14573   format %{ "BL        \t// dynamic $meth ==> " %}
14574   size(4);
14575   ins_encode( enc_java_dynamic_call_sched(meth) );
14576   ins_pipe(pipe_class_call);
14577 %}
14578 
14579 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
14580 // We use postalloc expanded calls if we use inline caches
14581 // and do not update method data.
14582 //
14583 // This instruction has two constants: inline cache (IC) and call destination.
14584 // Loading the inline cache will be postalloc expanded, thus leaving a call with
14585 // one constant.
14586 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
14587   match(CallDynamicJava);
14588   effect(USE meth);
14589   predicate(UseInlineCaches);
14590   ins_cost(CALL_COST);
14591 
14592   ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
14593 
14594   format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
14595   postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
14596 %}
14597 
14598 // Compound version of call dynamic java
14599 // We use postalloc expanded calls if we use inline caches
14600 // and do not update method data.
14601 instruct CallDynamicJavaDirect(method meth) %{
14602   match(CallDynamicJava);
14603   effect(USE meth);
14604   predicate(!UseInlineCaches);
14605   ins_cost(CALL_COST);
14606 
14607   // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
14608   ins_num_consts(4);
14609 
14610   format %{ "CALL,dynamic $meth \t// ==> " %}
14611   ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
14612   ins_pipe(pipe_class_call);
14613 %}
14614 
14615 // Call Runtime Instruction
14616 
14617 instruct CallRuntimeDirect(method meth) %{
14618   match(CallRuntime);
14619   effect(USE meth);
14620   ins_cost(CALL_COST);
14621 
14622   // Enc_java_to_runtime_call needs up to 3 constants: call target,
14623   // env for callee, C-toc.
14624   ins_num_consts(3);
14625 
14626   format %{ "CALL,runtime" %}
14627   ins_encode( enc_java_to_runtime_call(meth) );
14628   ins_pipe(pipe_class_call);
14629 %}
14630 
14631 // Call Leaf
14632 
14633 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
14634 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
14635   effect(DEF dst, USE src);
14636 
14637   ins_num_consts(1);
14638 
14639   format %{ "MTCTR   $src" %}
14640   size(4);
14641   ins_encode( enc_leaf_call_mtctr(src) );
14642   ins_pipe(pipe_class_default);
14643 %}
14644 
14645 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
14646 instruct CallLeafDirect(method meth) %{
14647   match(CallLeaf);   // To get the data all the data fields we need ...
14648   effect(USE meth);
14649   predicate(false);  // but never match.
14650 
14651   format %{ "BCTRL     \t// leaf call $meth ==> " %}
14652   size(4);
14653   ins_encode %{
14654     // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
14655     __ bctrl();
14656   %}
14657   ins_pipe(pipe_class_call);
14658 %}
14659 
14660 // postalloc expand of CallLeafDirect.
14661 // Load adress to call from TOC, then bl to it.
14662 instruct CallLeafDirect_Ex(method meth) %{
14663   match(CallLeaf);
14664   effect(USE meth);
14665   ins_cost(CALL_COST);
14666 
14667   // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
14668   // env for callee, C-toc.
14669   ins_num_consts(3);
14670 
14671   format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
14672   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
14673 %}
14674 
14675 // Call runtime without safepoint - same as CallLeaf.
14676 // postalloc expand of CallLeafNoFPDirect.
14677 // Load adress to call from TOC, then bl to it.
14678 instruct CallLeafNoFPDirect_Ex(method meth) %{
14679   match(CallLeafNoFP);
14680   effect(USE meth);
14681   ins_cost(CALL_COST);
14682 
14683   // Enc_java_to_runtime_call needs up to 3 constants: call target,
14684   // env for callee, C-toc.
14685   ins_num_consts(3);
14686 
14687   format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
14688   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
14689 %}
14690 
14691 // Tail Call; Jump from runtime stub to Java code.
14692 // Also known as an 'interprocedural jump'.
14693 // Target of jump will eventually return to caller.
14694 // TailJump below removes the return address.
14695 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
14696   match(TailCall jump_target method_oop);
14697   ins_cost(CALL_COST);
14698 
14699   format %{ "MTCTR   $jump_target \t// $method_oop holds method oop\n\t"
14700             "BCTR         \t// tail call" %}
14701   size(8);
14702   ins_encode %{
14703     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14704     __ mtctr($jump_target$$Register);
14705     __ bctr();
14706   %}
14707   ins_pipe(pipe_class_call);
14708 %}
14709 
14710 // Return Instruction
14711 instruct Ret() %{
14712   match(Return);
14713   format %{ "BLR      \t// branch to link register" %}
14714   size(4);
14715   ins_encode %{
14716     // TODO: PPC port $archOpcode(ppc64Opcode_blr);
14717     // LR is restored in MachEpilogNode. Just do the RET here.
14718     __ blr();
14719   %}
14720   ins_pipe(pipe_class_default);
14721 %}
14722 
14723 // Tail Jump; remove the return address; jump to target.
14724 // TailCall above leaves the return address around.
14725 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
14726 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
14727 // "restore" before this instruction (in Epilogue), we need to materialize it
14728 // in %i0.
14729 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
14730   match(TailJump jump_target ex_oop);
14731   ins_cost(CALL_COST);
14732 
14733   format %{ "LD      R4_ARG2 = LR\n\t"
14734             "MTCTR   $jump_target\n\t"
14735             "BCTR     \t// TailJump, exception oop: $ex_oop" %}
14736   size(12);
14737   ins_encode %{
14738     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14739     __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
14740     __ mtctr($jump_target$$Register);
14741     __ bctr();
14742   %}
14743   ins_pipe(pipe_class_call);
14744 %}
14745 
14746 // Create exception oop: created by stack-crawling runtime code.
14747 // Created exception is now available to this handler, and is setup
14748 // just prior to jumping to this handler. No code emitted.
14749 instruct CreateException(rarg1RegP ex_oop) %{
14750   match(Set ex_oop (CreateEx));
14751   ins_cost(0);
14752 
14753   format %{ " -- \t// exception oop; no code emitted" %}
14754   size(0);
14755   ins_encode( /*empty*/ );
14756   ins_pipe(pipe_class_default);
14757 %}
14758 
14759 // Rethrow exception: The exception oop will come in the first
14760 // argument position. Then JUMP (not call) to the rethrow stub code.
14761 instruct RethrowException() %{
14762   match(Rethrow);
14763   ins_cost(CALL_COST);
14764 
14765   format %{ "Jmp     rethrow_stub" %}
14766   ins_encode %{
14767     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14768     cbuf.set_insts_mark();
14769     __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
14770   %}
14771   ins_pipe(pipe_class_call);
14772 %}
14773 
14774 // Die now.
14775 instruct ShouldNotReachHere() %{
14776   match(Halt);
14777   ins_cost(CALL_COST);
14778 
14779   format %{ "ShouldNotReachHere" %}
14780   size(4);
14781   ins_encode %{
14782     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
14783     __ trap_should_not_reach_here();
14784   %}
14785   ins_pipe(pipe_class_default);
14786 %}
14787 
14788 // This name is KNOWN by the ADLC and cannot be changed.  The ADLC
14789 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
14790 // Get a DEF on threadRegP, no costs, no encoding, use
14791 // 'ins_should_rematerialize(true)' to avoid spilling.
14792 instruct tlsLoadP(threadRegP dst) %{
14793   match(Set dst (ThreadLocal));
14794   ins_cost(0);
14795 
14796   ins_should_rematerialize(true);
14797 
14798   format %{ " -- \t// $dst=Thread::current(), empty" %}
14799   size(0);
14800   ins_encode( /*empty*/ );
14801   ins_pipe(pipe_class_empty);
14802 %}
14803 
14804 //---Some PPC specific nodes---------------------------------------------------
14805 
14806 // Stop a group.
14807 instruct endGroup() %{
14808   ins_cost(0);
14809 
14810   ins_is_nop(true);
14811 
14812   format %{ "End Bundle (ori r1, r1, 0)" %}
14813   size(4);
14814   ins_encode %{
14815     // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
14816     __ endgroup();
14817   %}
14818   ins_pipe(pipe_class_default);
14819 %}
14820 
14821 // Nop instructions
14822 
14823 instruct fxNop() %{
14824   ins_cost(0);
14825 
14826   ins_is_nop(true);
14827 
14828   format %{ "fxNop" %}
14829   size(4);
14830   ins_encode %{
14831     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
14832     __ nop();
14833   %}
14834   ins_pipe(pipe_class_default);
14835 %}
14836 
14837 instruct fpNop0() %{
14838   ins_cost(0);
14839 
14840   ins_is_nop(true);
14841 
14842   format %{ "fpNop0" %}
14843   size(4);
14844   ins_encode %{
14845     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
14846     __ fpnop0();
14847   %}
14848   ins_pipe(pipe_class_default);
14849 %}
14850 
14851 instruct fpNop1() %{
14852   ins_cost(0);
14853 
14854   ins_is_nop(true);
14855 
14856   format %{ "fpNop1" %}
14857   size(4);
14858   ins_encode %{
14859     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
14860     __ fpnop1();
14861   %}
14862   ins_pipe(pipe_class_default);
14863 %}
14864 
14865 instruct brNop0() %{
14866   ins_cost(0);
14867   size(4);
14868   format %{ "brNop0" %}
14869   ins_encode %{
14870     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
14871     __ brnop0();
14872   %}
14873   ins_is_nop(true);
14874   ins_pipe(pipe_class_default);
14875 %}
14876 
14877 instruct brNop1() %{
14878   ins_cost(0);
14879 
14880   ins_is_nop(true);
14881 
14882   format %{ "brNop1" %}
14883   size(4);
14884   ins_encode %{
14885     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
14886     __ brnop1();
14887   %}
14888   ins_pipe(pipe_class_default);
14889 %}
14890 
14891 instruct brNop2() %{
14892   ins_cost(0);
14893 
14894   ins_is_nop(true);
14895 
14896   format %{ "brNop2" %}
14897   size(4);
14898   ins_encode %{
14899     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
14900     __ brnop2();
14901   %}
14902   ins_pipe(pipe_class_default);
14903 %}
14904 
14905 //----------PEEPHOLE RULES-----------------------------------------------------
14906 // These must follow all instruction definitions as they use the names
14907 // defined in the instructions definitions.
14908 //
14909 // peepmatch ( root_instr_name [preceeding_instruction]* );
14910 //
14911 // peepconstraint %{
14912 // (instruction_number.operand_name relational_op instruction_number.operand_name
14913 //  [, ...] );
14914 // // instruction numbers are zero-based using left to right order in peepmatch
14915 //
14916 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14917 // // provide an instruction_number.operand_name for each operand that appears
14918 // // in the replacement instruction's match rule
14919 //
14920 // ---------VM FLAGS---------------------------------------------------------
14921 //
14922 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14923 //
14924 // Each peephole rule is given an identifying number starting with zero and
14925 // increasing by one in the order seen by the parser. An individual peephole
14926 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
14927 // on the command-line.
14928 //
14929 // ---------CURRENT LIMITATIONS----------------------------------------------
14930 //
14931 // Only match adjacent instructions in same basic block
14932 // Only equality constraints
14933 // Only constraints between operands, not (0.dest_reg == EAX_enc)
14934 // Only one replacement instruction
14935 //
14936 // ---------EXAMPLE----------------------------------------------------------
14937 //
14938 // // pertinent parts of existing instructions in architecture description
14939 // instruct movI(eRegI dst, eRegI src) %{
14940 //   match(Set dst (CopyI src));
14941 // %}
14942 //
14943 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
14944 //   match(Set dst (AddI dst src));
14945 //   effect(KILL cr);
14946 // %}
14947 //
14948 // // Change (inc mov) to lea
14949 // peephole %{
14950 //   // increment preceeded by register-register move
14951 //   peepmatch ( incI_eReg movI );
14952 //   // require that the destination register of the increment
14953 //   // match the destination register of the move
14954 //   peepconstraint ( 0.dst == 1.dst );
14955 //   // construct a replacement instruction that sets
14956 //   // the destination to ( move's source register + one )
14957 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14958 // %}
14959 //
14960 // Implementation no longer uses movX instructions since
14961 // machine-independent system no longer uses CopyX nodes.
14962 //
14963 // peephole %{
14964 //   peepmatch ( incI_eReg movI );
14965 //   peepconstraint ( 0.dst == 1.dst );
14966 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14967 // %}
14968 //
14969 // peephole %{
14970 //   peepmatch ( decI_eReg movI );
14971 //   peepconstraint ( 0.dst == 1.dst );
14972 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14973 // %}
14974 //
14975 // peephole %{
14976 //   peepmatch ( addI_eReg_imm movI );
14977 //   peepconstraint ( 0.dst == 1.dst );
14978 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14979 // %}
14980 //
14981 // peephole %{
14982 //   peepmatch ( addP_eReg_imm movP );
14983 //   peepconstraint ( 0.dst == 1.dst );
14984 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
14985 // %}
14986 
14987 // // Change load of spilled value to only a spill
14988 // instruct storeI(memory mem, eRegI src) %{
14989 //   match(Set mem (StoreI mem src));
14990 // %}
14991 //
14992 // instruct loadI(eRegI dst, memory mem) %{
14993 //   match(Set dst (LoadI mem));
14994 // %}
14995 //
14996 peephole %{
14997   peepmatch ( loadI storeI );
14998   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
14999   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
15000 %}
15001 
15002 peephole %{
15003   peepmatch ( loadL storeL );
15004   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
15005   peepreplace ( storeL( 1.mem 1.mem 1.src ) );
15006 %}
15007 
15008 peephole %{
15009   peepmatch ( loadP storeP );
15010   peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
15011   peepreplace ( storeP( 1.dst 1.dst 1.src ) );
15012 %}
15013 
15014 //----------SMARTSPILL RULES---------------------------------------------------
15015 // These must follow all instruction definitions as they use the names
15016 // defined in the instructions definitions.