src/hotspot/cpu/ppc/ppc.ad

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2220   case Op_CountLeadingZerosI:
2221   case Op_CountLeadingZerosL:
2222   case Op_CountTrailingZerosI:
2223   case Op_CountTrailingZerosL:
2224     if (!UseCountLeadingZerosInstructionsPPC64)
2225       return false;
2226     break;
2227 
2228   case Op_PopCountI:
2229   case Op_PopCountL:
2230     return (UsePopCountInstruction && VM_Version::has_popcntw());
2231 
2232   case Op_StrComp:
2233     return SpecialStringCompareTo;
2234   case Op_StrEquals:
2235     return SpecialStringEquals;
2236   case Op_StrIndexOf:
2237     return SpecialStringIndexOf;
2238   case Op_StrIndexOfChar:
2239     return SpecialStringIndexOf;


























2240   }
2241 
2242   return true;  // Per default match rules are supported.
2243 }
2244 
2245 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2246 
2247   // TODO
2248   // identify extra cases that we might want to provide match rules for
2249   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2250   bool ret_value = match_rule_supported(opcode);
2251   // Add rules here.
2252 
2253   return ret_value;  // Per default match rules are supported.
2254 }
2255 
2256 const bool Matcher::has_predicated_vectors(void) {
2257   return false;
2258 }
2259 


10000     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
10001   %}
10002   ins_pipe(pipe_class_default);
10003 %}
10004 
10005 // VM_Version::has_fsqrt() decides if this node will be used.
10006 // Sqrt float double precision
10007 instruct sqrtD_reg(regD dst, regD src) %{
10008   match(Set dst (SqrtD src));
10009   format %{ "FSQRT   $dst, $src" %}
10010   size(4);
10011   ins_encode %{
10012     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
10013     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
10014   %}
10015   ins_pipe(pipe_class_default);
10016 %}
10017 
10018 // Single-precision sqrt.
10019 instruct sqrtF_reg(regF dst, regF src) %{
10020   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10021   predicate(VM_Version::has_fsqrts());
10022   ins_cost(DEFAULT_COST);
10023 
10024   format %{ "FSQRTS  $dst, $src" %}
10025   size(4);
10026   ins_encode %{
10027     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
10028     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
10029   %}
10030   ins_pipe(pipe_class_default);
10031 %}
10032 
10033 instruct roundDouble_nop(regD dst) %{
10034   match(Set dst (RoundDouble dst));
10035   ins_cost(0);
10036 
10037   format %{ " -- \t// RoundDouble not needed - empty" %}
10038   size(0);
10039   // PPC results are already "rounded" (i.e., normal-format IEEE).
10040   ins_encode( /*empty*/ );


13967 
13968 // Replicate scalar constant to packed float values in Double register
13969 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
13970   match(Set dst (ReplicateF src));
13971   predicate(n->as_Vector()->length() == 2);
13972   ins_cost(5 * DEFAULT_COST);
13973 
13974   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
13975   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
13976 %}
13977 
13978 // Replicate scalar zero constant to packed float values in Double register
13979 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
13980   match(Set dst (ReplicateF zero));
13981   predicate(n->as_Vector()->length() == 2);
13982 
13983   format %{ "LI      $dst, #0 \t// replicate2F" %}
13984   ins_encode %{
13985     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13986     __ li($dst$$Register, 0x0);









































































































































































































































































































13987   %}
13988   ins_pipe(pipe_class_default);
13989 %}
13990 
13991 
13992 //----------Overflow Math Instructions-----------------------------------------
13993 
13994 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
13995 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
13996 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
13997 
13998 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13999   match(Set cr0 (OverflowAddL op1 op2));
14000 
14001   format %{ "add_    $op1, $op2\t# overflow check long" %}
14002   ins_encode %{
14003     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14004     __ li(R0, 0);
14005     __ mtxer(R0); // clear XER.SO
14006     __ addo_(R0, $op1$$Register, $op2$$Register);




2220   case Op_CountLeadingZerosI:
2221   case Op_CountLeadingZerosL:
2222   case Op_CountTrailingZerosI:
2223   case Op_CountTrailingZerosL:
2224     if (!UseCountLeadingZerosInstructionsPPC64)
2225       return false;
2226     break;
2227 
2228   case Op_PopCountI:
2229   case Op_PopCountL:
2230     return (UsePopCountInstruction && VM_Version::has_popcntw());
2231 
2232   case Op_StrComp:
2233     return SpecialStringCompareTo;
2234   case Op_StrEquals:
2235     return SpecialStringEquals;
2236   case Op_StrIndexOf:
2237     return SpecialStringIndexOf;
2238   case Op_StrIndexOfChar:
2239     return SpecialStringIndexOf;
2240   case Op_AddVB:
2241   case Op_AddVS:
2242   case Op_AddVI:
2243   case Op_AddVF:
2244   case Op_AddVL:
2245   case Op_AddVD:
2246   case Op_SubVB:
2247   case Op_SubVS:
2248   case Op_SubVI:
2249   case Op_SubVF:
2250   case Op_SubVL:
2251   case Op_SubVD:
2252   case Op_MulVS:
2253   case Op_MulVI:
2254   case Op_MulVF:
2255   case Op_MulVD:
2256   case Op_DivVF:
2257   case Op_DivVD:
2258   case Op_AbsVF:
2259   case Op_AbsVD:
2260   case Op_NegVF:
2261   case Op_NegVD:
2262   case Op_SqrtVF:
2263   case Op_SqrtVD:
2264   case Op_PopCountVI:
2265     return VM_Version::has_popcntb();
2266   }
2267 
2268   return true;  // Per default match rules are supported.
2269 }
2270 
2271 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2272 
2273   // TODO
2274   // identify extra cases that we might want to provide match rules for
2275   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2276   bool ret_value = match_rule_supported(opcode);
2277   // Add rules here.
2278 
2279   return ret_value;  // Per default match rules are supported.
2280 }
2281 
2282 const bool Matcher::has_predicated_vectors(void) {
2283   return false;
2284 }
2285 


10026     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
10027   %}
10028   ins_pipe(pipe_class_default);
10029 %}
10030 
10031 // VM_Version::has_fsqrt() decides if this node will be used.
10032 // Sqrt float double precision
10033 instruct sqrtD_reg(regD dst, regD src) %{
10034   match(Set dst (SqrtD src));
10035   format %{ "FSQRT   $dst, $src" %}
10036   size(4);
10037   ins_encode %{
10038     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
10039     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
10040   %}
10041   ins_pipe(pipe_class_default);
10042 %}
10043 
10044 // Single-precision sqrt.
10045 instruct sqrtF_reg(regF dst, regF src) %{
10046   match(Set dst (SqrtF src));
10047   predicate(VM_Version::has_fsqrts());
10048   ins_cost(DEFAULT_COST);
10049 
10050   format %{ "FSQRTS  $dst, $src" %}
10051   size(4);
10052   ins_encode %{
10053     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
10054     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
10055   %}
10056   ins_pipe(pipe_class_default);
10057 %}
10058 
10059 instruct roundDouble_nop(regD dst) %{
10060   match(Set dst (RoundDouble dst));
10061   ins_cost(0);
10062 
10063   format %{ " -- \t// RoundDouble not needed - empty" %}
10064   size(0);
10065   // PPC results are already "rounded" (i.e., normal-format IEEE).
10066   ins_encode( /*empty*/ );


13993 
13994 // Replicate scalar constant to packed float values in Double register
13995 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
13996   match(Set dst (ReplicateF src));
13997   predicate(n->as_Vector()->length() == 2);
13998   ins_cost(5 * DEFAULT_COST);
13999 
14000   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
14001   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
14002 %}
14003 
14004 // Replicate scalar zero constant to packed float values in Double register
14005 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
14006   match(Set dst (ReplicateF zero));
14007   predicate(n->as_Vector()->length() == 2);
14008 
14009   format %{ "LI      $dst, #0 \t// replicate2F" %}
14010   ins_encode %{
14011     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14012     __ li($dst$$Register, 0x0);
14013   %}
14014   ins_pipe(pipe_class_default);
14015 %}
14016 
14017 
14018 //----------Vector Arithmetic Instructions--------------------------------------
14019 
14020 // Vector Addition Instructions
14021 
14022 instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{
14023   match(Set dst (AddVB src1 src2));
14024   predicate(n->as_Vector()->length() == 16);
14025   format %{ "VADDUBM  $dst,$src1,$src2\t// add packed16B" %}
14026   size(4);
14027   ins_encode %{
14028     __ vaddubm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14029   %}
14030   ins_pipe(pipe_class_default);
14031 %}
14032 
14033 instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{
14034   match(Set dst (AddVS src1 src2));
14035   predicate(n->as_Vector()->length() == 8);
14036   format %{ "VADDUHM  $dst,$src1,$src2\t// add packed8S" %}
14037   size(4);
14038   ins_encode %{
14039     __ vadduhm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14040   %}
14041   ins_pipe(pipe_class_default);
14042 %}
14043 
14044 instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{
14045   match(Set dst (AddVI src1 src2));
14046   predicate(n->as_Vector()->length() == 4);
14047   format %{ "VADDUWM  $dst,$src1,$src2\t// add packed4I" %}
14048   size(4);
14049   ins_encode %{
14050     __ vadduwm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14051   %}
14052   ins_pipe(pipe_class_default);
14053 %}
14054 
14055 instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{
14056   match(Set dst (AddVF src1 src2));
14057   predicate(n->as_Vector()->length() == 4);
14058   format %{ "VADDFP  $dst,$src1,$src2\t// add packed4F" %}
14059   size(4);
14060   ins_encode %{
14061     __ vaddfp($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14062   %}
14063   ins_pipe(pipe_class_default);
14064 %}
14065 
14066 instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{
14067   match(Set dst (AddVL src1 src2));
14068   predicate(n->as_Vector()->length() == 2);
14069   format %{ "VADDUDM  $dst,$src1,$src2\t// add packed2L" %}
14070   size(4);
14071   ins_encode %{
14072     __ vaddudm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14073   %}
14074   ins_pipe(pipe_class_default);
14075 %}
14076 
14077 instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{
14078   match(Set dst (AddVD src1 src2));
14079   predicate(n->as_Vector()->length() == 2);
14080   format %{ "XVADDDP  $dst,$src1,$src2\t// add packed2D" %}
14081   size(4);
14082   ins_encode %{
14083     __ xvadddp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14084   %}
14085   ins_pipe(pipe_class_default);
14086 %}
14087 
14088 // Vector Subtraction Instructions
14089 
14090 instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{
14091   match(Set dst (SubVB src1 src2));
14092   predicate(n->as_Vector()->length() == 16);
14093   format %{ "VSUBUBM  $dst,$src1,$src2\t// sub packed16B" %}
14094   size(4);
14095   ins_encode %{
14096     __ vsububm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14097   %}
14098   ins_pipe(pipe_class_default);
14099 %}
14100 
14101 instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{
14102   match(Set dst (SubVS src1 src2));
14103   predicate(n->as_Vector()->length() == 8);
14104   format %{ "VSUBUHM  $dst,$src1,$src2\t// sub packed8S" %}
14105   size(4);
14106   ins_encode %{
14107     __ vsubuhm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14108   %}
14109   ins_pipe(pipe_class_default);
14110 %}
14111 
14112 instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{
14113   match(Set dst (SubVI src1 src2));
14114   predicate(n->as_Vector()->length() == 4);
14115   format %{ "VSUBUWM  $dst,$src1,$src2\t// sub packed4I" %}
14116   size(4);
14117   ins_encode %{
14118     __ vsubuwm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14119   %}
14120   ins_pipe(pipe_class_default);
14121 %}
14122 
14123 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
14124   match(Set dst (SubVF src1 src2));
14125   predicate(n->as_Vector()->length() == 4);
14126   format %{ "VSUBFP  $dst,$src1,$src2\t// sub packed4F" %}
14127   size(4);
14128   ins_encode %{
14129     __ vsubfp($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14130   %}
14131   ins_pipe(pipe_class_default);
14132 %}
14133 
14134 instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{
14135   match(Set dst (SubVL src1 src2));
14136   predicate(n->as_Vector()->length() == 2);
14137   format %{ "VSUBUDM  $dst,$src1,$src2\t// sub packed2L" %}
14138   size(4);
14139   ins_encode %{
14140     __ vsubudm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14141   %}
14142   ins_pipe(pipe_class_default);
14143 %}
14144 
14145 instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{
14146   match(Set dst (SubVD src1 src2));
14147   predicate(n->as_Vector()->length() == 2);
14148   format %{ "XVSUBDP  $dst,$src1,$src2\t// sub packed2D" %}
14149   size(4);
14150   ins_encode %{
14151     __ xvsubdp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14152   %}
14153   ins_pipe(pipe_class_default);
14154 %}
14155 
14156 // Vector Multiplication Instructions
14157 
14158 instruct vmul8S_reg(vecX dst, vecX src1, vecX src2, vecX tmp) %{
14159   match(Set dst (MulVS src1 src2));
14160   predicate(n->as_Vector()->length() == 8);
14161   effect(TEMP tmp);
14162   format %{ "VSPLTISH  $tmp,0\t// mul packed8S" %}
14163   format %{ "VMLADDUHM  $dst,$src1,$src2\t// mul packed8S" %}
14164   size(8);
14165   ins_encode %{
14166     __ vspltish($tmp$$VectorSRegister->to_vr(), 0);
14167     __ vmladduhm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr(), $tmp$$VectorSRegister->to_vr());
14168   %}
14169   ins_pipe(pipe_class_default);
14170 %}
14171 
14172 instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{
14173   match(Set dst (MulVI src1 src2));
14174   predicate(n->as_Vector()->length() == 4);
14175   format %{ "VMULUWM  $dst,$src1,$src2\t// mul packed4I" %}
14176   size(4);
14177   ins_encode %{
14178     __ vmuluwm($dst$$VectorSRegister->to_vr(), $src1$$VectorSRegister->to_vr(), $src2$$VectorSRegister->to_vr());
14179   %}
14180   ins_pipe(pipe_class_default);
14181 %}
14182 
14183 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
14184   match(Set dst (MulVF src1 src2));
14185   predicate(n->as_Vector()->length() == 4);
14186   format %{ "XVMULSP  $dst,$src1,$src2\t// mul packed4F" %}
14187   size(4);
14188   ins_encode %{
14189     __ xvmulsp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14190   %}
14191   ins_pipe(pipe_class_default);
14192 %}
14193 
14194 instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
14195   match(Set dst (MulVD src1 src2));
14196   predicate(n->as_Vector()->length() == 2);
14197   format %{ "XVMULDP  $dst,$src1,$src2\t// mul packed2D" %}
14198   size(4);
14199   ins_encode %{
14200     __ xvmuldp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14201   %}
14202   ins_pipe(pipe_class_default);
14203 %}
14204 
14205 // Vector Division Instructions
14206 
14207 instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{
14208   match(Set dst (DivVF src1 src2));
14209   predicate(n->as_Vector()->length() == 4);
14210   format %{ "XVDIVSP  $dst,$src1,$src2\t// div packed4F" %}
14211   size(4);
14212   ins_encode %{
14213     __ xvdivsp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14214   %}
14215   ins_pipe(pipe_class_default);
14216 %}
14217 
14218 instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
14219   match(Set dst (DivVD src1 src2));
14220   predicate(n->as_Vector()->length() == 2);
14221   format %{ "XVDIVDP  $dst,$src1,$src2\t// div packed2D" %}
14222   size(4);
14223   ins_encode %{
14224     __ xvdivdp($dst$$VectorSRegister, $src1$$VectorSRegister, $src2$$VectorSRegister);
14225   %}
14226   ins_pipe(pipe_class_default);
14227 %}
14228 
14229 // Vector Absolute Instructions
14230 
14231 instruct vabs4F_reg(vecX dst, vecX src) %{
14232   match(Set dst (AbsVF src));
14233   predicate(n->as_Vector()->length() == 4);
14234   format %{ "XVABSSP $dst,$src\t// absolute packed4F" %}
14235   size(4);
14236   ins_encode %{
14237     __ xvabssp($dst$$VectorSRegister, $src$$VectorSRegister);
14238   %}
14239   ins_pipe(pipe_class_default);
14240 %}
14241 
14242 instruct vabs2D_reg(vecX dst, vecX src) %{
14243   match(Set dst (AbsVD src));
14244   predicate(n->as_Vector()->length() == 2);
14245   format %{ "XVABSDP $dst,$src\t// absolute packed2D" %}
14246   size(4);
14247   ins_encode %{
14248     __ xvabsdp($dst$$VectorSRegister, $src$$VectorSRegister);
14249   %}
14250   ins_pipe(pipe_class_default);
14251 %}
14252 
14253 // Vector Negate Instructions
14254 
14255 instruct vneg4F_reg(vecX dst, vecX src) %{
14256   match(Set dst (NegVF src));
14257   predicate(n->as_Vector()->length() == 4);
14258   format %{ "XVNEGSP $dst,$src\t// negate packed4F" %}
14259   size(4);
14260   ins_encode %{
14261     __ xvnegsp($dst$$VectorSRegister, $src$$VectorSRegister);
14262   %}
14263   ins_pipe(pipe_class_default);
14264 %}
14265 
14266 instruct vneg2D_reg(vecX dst, vecX src) %{
14267   match(Set dst (NegVD src));
14268   predicate(n->as_Vector()->length() == 2);
14269   format %{ "XVNEGDP $dst,$src\t// negate packed2D" %}
14270   size(4);
14271   ins_encode %{
14272     __ xvnegdp($dst$$VectorSRegister, $src$$VectorSRegister);
14273   %}
14274   ins_pipe(pipe_class_default);
14275 %}
14276 
14277 // Vector Square Root Instructions
14278 
14279 instruct vsqrt4F_reg(vecX dst, vecX src) %{
14280   match(Set dst (SqrtVF src));
14281   predicate(n->as_Vector()->length() == 4);
14282   format %{ "XVSQRTSP $dst,$src\t// sqrt packed4F" %}
14283   size(4);
14284   ins_encode %{
14285     __ xvsqrtsp($dst$$VectorSRegister, $src$$VectorSRegister);
14286   %}
14287   ins_pipe(pipe_class_default);
14288 %}
14289 
14290 instruct vsqrt2D_reg(vecX dst, vecX src) %{
14291   match(Set dst (SqrtVD src));
14292   predicate(n->as_Vector()->length() == 2);
14293   format %{ "XVSQRTDP  $dst,$src\t// sqrt packed2D" %}
14294   size(4);
14295   ins_encode %{
14296     __ xvsqrtdp($dst$$VectorSRegister, $src$$VectorSRegister);
14297   %}
14298   ins_pipe(pipe_class_default);
14299 %}
14300 
14301 // Vector Population Count Instructions
14302 
14303 instruct vpopcnt4I_reg(vecX dst, vecX src) %{
14304   match(Set dst (PopCountVI src));
14305   predicate(n->as_Vector()->length() == 4);
14306   format %{ "VPOPCNTW $dst,$src\t// pop count packed4I" %}
14307   size(4);
14308   ins_encode %{
14309     __ vpopcntw($dst$$VectorSRegister->to_vr(), $src$$VectorSRegister->to_vr());
14310   %}
14311   ins_pipe(pipe_class_default);
14312 %}
14313 
14314 
14315 //----------Overflow Math Instructions-----------------------------------------
14316 
14317 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
14318 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
14319 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
14320 
14321 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
14322   match(Set cr0 (OverflowAddL op1 op2));
14323 
14324   format %{ "add_    $op1, $op2\t# overflow check long" %}
14325   ins_encode %{
14326     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
14327     __ li(R0, 0);
14328     __ mtxer(R0); // clear XER.SO
14329     __ addo_(R0, $op1$$Register, $op2$$Register);