2236 case Op_SubVI:
2237 case Op_SubVF:
2238 case Op_SubVD:
2239 case Op_MulVS:
2240 case Op_MulVF:
2241 case Op_MulVD:
2242 case Op_DivVF:
2243 case Op_DivVD:
2244 case Op_AbsVF:
2245 case Op_AbsVD:
2246 case Op_NegVF:
2247 case Op_NegVD:
2248 case Op_SqrtVF:
2249 case Op_SqrtVD:
2250 case Op_AddVL:
2251 case Op_SubVL:
2252 case Op_MulVI:
2253 return SuperwordUseVSX;
2254 case Op_PopCountVI:
2255 return (SuperwordUseVSX && UsePopCountInstruction);
2256 }
2257
2258 return true; // Per default match rules are supported.
2259 }
2260
2261 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2262
2263 // TODO
2264 // identify extra cases that we might want to provide match rules for
2265 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2266 bool ret_value = match_rule_supported(opcode);
2267 // Add rules here.
2268
2269 return ret_value; // Per default match rules are supported.
2270 }
2271
2272 const bool Matcher::has_predicated_vectors(void) {
2273 return false;
2274 }
2275
12377 // registers for new nodes
12378 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12379 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12380
12381 // Insert new nodes.
12382 nodes->push(m1);
12383 nodes->push(m2);
12384 %}
12385 %}
12386
12387 // Compare double, generate -1,0,1
12388 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12389 match(Set dst (CmpD3 src1 src2));
12390 ins_cost(DEFAULT_COST*5+BRANCH_COST);
12391
12392 expand %{
12393 flagsReg tmp1;
12394 cmpDUnordered_reg_reg(tmp1, src1, src2);
12395 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12396 %}
12397 %}
12398
12399 //----------Branches---------------------------------------------------------
12400 // Jump
12401
12402 // Direct Branch.
12403 instruct branch(label labl) %{
12404 match(Goto);
12405 effect(USE labl);
12406 ins_cost(BRANCH_COST);
12407
12408 format %{ "B $labl" %}
12409 size(4);
12410 ins_encode %{
12411 // TODO: PPC port $archOpcode(ppc64Opcode_b);
12412 Label d; // dummy
12413 __ bind(d);
12414 Label* p = $labl$$label;
12415 // `p' is `NULL' when this encoding class is used only to
12416 // determine the size of the encoded instruction.
|
2236 case Op_SubVI:
2237 case Op_SubVF:
2238 case Op_SubVD:
2239 case Op_MulVS:
2240 case Op_MulVF:
2241 case Op_MulVD:
2242 case Op_DivVF:
2243 case Op_DivVD:
2244 case Op_AbsVF:
2245 case Op_AbsVD:
2246 case Op_NegVF:
2247 case Op_NegVD:
2248 case Op_SqrtVF:
2249 case Op_SqrtVD:
2250 case Op_AddVL:
2251 case Op_SubVL:
2252 case Op_MulVI:
2253 return SuperwordUseVSX;
2254 case Op_PopCountVI:
2255 return (SuperwordUseVSX && UsePopCountInstruction);
2256 case Op_DigitC:
2257 case Op_LowerCaseC:
2258 case Op_UpperCaseC:
2259 case Op_WhitespaceC:
2260 return VM_Version::has_darn();
2261 }
2262
2263 return true; // Per default match rules are supported.
2264 }
2265
2266 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2267
2268 // TODO
2269 // identify extra cases that we might want to provide match rules for
2270 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2271 bool ret_value = match_rule_supported(opcode);
2272 // Add rules here.
2273
2274 return ret_value; // Per default match rules are supported.
2275 }
2276
2277 const bool Matcher::has_predicated_vectors(void) {
2278 return false;
2279 }
2280
12382 // registers for new nodes
12383 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12384 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12385
12386 // Insert new nodes.
12387 nodes->push(m1);
12388 nodes->push(m2);
12389 %}
12390 %}
12391
12392 // Compare double, generate -1,0,1
12393 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12394 match(Set dst (CmpD3 src1 src2));
12395 ins_cost(DEFAULT_COST*5+BRANCH_COST);
12396
12397 expand %{
12398 flagsReg tmp1;
12399 cmpDUnordered_reg_reg(tmp1, src1, src2);
12400 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12401 %}
12402 %}
12403
12404 // Compare char
12405 instruct cmprb_DigitC_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12406 match(Set dst (DigitC src1));
12407 effect(TEMP src2, TEMP crx);
12408 ins_cost(3 * DEFAULT_COST);
12409
12410 format %{ "LI $src2, 0x3930\n\t"
12411 "CMPRB $crx, 0, $src1, $src2\n\t"
12412 "SETB $dst, $crx" %}
12413 size(12);
12414 ins_encode %{
12415 // 0x30: 0, 0x39: 9
12416 __ li($src2$$Register, 0x3930);
12417 // compare src1 with ranges 0x30 to 0x39
12418 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12419 __ setb($dst$$Register, $crx$$CondRegister);
12420 %}
12421 ins_pipe(pipe_class_default);
12422 %}
12423
12424 instruct cmprb_LowerCaseC_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12425 match(Set dst (LowerCaseC src1));
12426 effect(TEMP src2, TEMP crx);
12427 ins_cost(12 * DEFAULT_COST);
12428
12429 format %{ "LI $src2, 0x7A61\n\t"
12430 "CMPRB $crx, 0, $src1, $src2\n\t"
12431 "BGT $crx, done\n\t"
12432 "LIS $src2, (signed short)0xF6DF\n\t"
12433 "ORI $src2, $src2, 0xFFF8\n\t"
12434 "CMPRB $crx, 1, $src1, $src2\n\t"
12435 "BGT $crx, done\n\t"
12436 "LIS $src2, (signed short)0xAAB5\n\t"
12437 "ORI $src2, $src2, 0xBABA\n\t"
12438 "INSRDI $src2, $src2, 32, 0\n\t"
12439 "CMPEQB $crx, 1, $src1, $src2\n\t"
12440 "SETB $dst, $crx" %}
12441
12442 size(48);
12443 ins_encode %{
12444 Label done;
12445 // 0x61: a, 0x7A: z
12446 __ li($src2$$Register, 0x7A61);
12447 // compare src1 with ranges 0x61 to 0x7A
12448 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12449 __ bgt($crx$$CondRegister, done);
12450
12451 // 0xDF: sharp s, 0xFF: y with diaeresis, 0xF7 is not the lower case
12452 __ lis($src2$$Register, (signed short)0xF6DF);
12453 __ ori($src2$$Register, $src2$$Register, 0xFFF8);
12454 // compare src1 with ranges 0xDF to 0xF6 and 0xF8 to 0xFF
12455 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12456 __ bgt($crx$$CondRegister, done);
12457
12458 // 0xAA: feminine ordinal indicator
12459 // 0xB5: micro sign
12460 // 0xBA: masculine ordinal indicator
12461 __ lis($src2$$Register, (signed short)0xAAB5);
12462 __ ori($src2$$Register, $src2$$Register, 0xBABA);
12463 __ insrdi($src2$$Register, $src2$$Register, 32, 0);
12464 // compare src1 with 0xAA, 0xB5, and 0xBA
12465 __ cmpeqb($crx$$CondRegister, $src1$$Register, $src2$$Register);
12466
12467 __ bind(done);
12468 __ setb($dst$$Register, $crx$$CondRegister);
12469 %}
12470 ins_pipe(pipe_class_default);
12471 %}
12472
12473 instruct cmprb_UpperCaseC_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12474 match(Set dst (UpperCaseC src1));
12475 effect(TEMP src2, TEMP crx);
12476 ins_cost(7 * DEFAULT_COST);
12477
12478 format %{ "LI $src2, 0x5A41\n\t"
12479 "CMPRB $crx, 0, $src1, $src2\n\t"
12480 "BGT $crx, done\n\t"
12481 "LIS $src2, (signed short)0xD6C0\n\t"
12482 "ORI $src2, $src2, 0xDED8\n\t"
12483 "CMPRB $crx, 1, $src1, $src2\n\t"
12484 "SETB $dst, $crx" %}
12485
12486 size(28);
12487 ins_encode %{
12488 Label done;
12489 // 0x41: A, 0x5A: Z
12490 __ li($src2$$Register, 0x5A41);
12491 // compare src1 with a range 0x41 to 0x5A
12492 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12493 __ bgt($crx$$CondRegister, done);
12494
12495 // 0xC0: a with grave, 0xDE: thorn, 0xD7 is not the upper case
12496 __ lis($src2$$Register, (signed short)0xD6C0);
12497 __ ori($src2$$Register, $src2$$Register, 0xDED8);
12498 // compare src1 with ranges 0xC0 to 0xD6 and 0xD8 to 0xDE
12499 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12500
12501 __ bind(done);
12502 __ setb($dst$$Register, $crx$$CondRegister);
12503 %}
12504 ins_pipe(pipe_class_default);
12505 %}
12506
12507 instruct cmprb_WhitespaceC_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12508 match(Set dst (WhitespaceC src1));
12509 effect(TEMP src2, TEMP crx);
12510 ins_cost(4 * DEFAULT_COST);
12511
12512 format %{ "LI $src2, 0x0D09\n\t"
12513 "ADDIS $src2, 0x201C\n\t"
12514 "CMPRB $crx, 1, $src1, $src2\n\t"
12515 "SETB $dst, $crx" %}
12516 size(16);
12517 ins_encode %{
12518 // 0x09 to 0x0D, 0x1C to 0x20
12519 __ li($src2$$Register, 0x0D09);
12520 __ addis($src2$$Register, $src2$$Register, 0x0201C);
12521 // compare src with ranges 0x09 to 0x0D and 0x1C to 0x20
12522 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12523 __ setb($dst$$Register, $crx$$CondRegister);
12524 %}
12525 ins_pipe(pipe_class_default);
12526 %}
12527
12528 //----------Branches---------------------------------------------------------
12529 // Jump
12530
12531 // Direct Branch.
12532 instruct branch(label labl) %{
12533 match(Goto);
12534 effect(USE labl);
12535 ins_cost(BRANCH_COST);
12536
12537 format %{ "B $labl" %}
12538 size(4);
12539 ins_encode %{
12540 // TODO: PPC port $archOpcode(ppc64Opcode_b);
12541 Label d; // dummy
12542 __ bind(d);
12543 Label* p = $labl$$label;
12544 // `p' is `NULL' when this encoding class is used only to
12545 // determine the size of the encoded instruction.
|