962
963
964 //----------SOURCE BLOCK-------------------------------------------------------
965 // This is a block of C++ code which provides values, functions, and
966 // definitions necessary in the rest of the architecture description.
967 source_hpp %{
968 // Header information of the source block.
969 // Method declarations/definitions which are used outside
970 // the ad-scope can conveniently be defined here.
971 //
972 // To keep related declarations/definitions/uses close together,
973 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
974
975 // Returns true if Node n is followed by a MemBar node that
976 // will do an acquire. If so, this node must not do the acquire
977 // operation.
978 bool followed_by_acquire(const Node *n);
979 %}
980
981 source %{
982
983 // Should the Matcher clone shifts on addressing modes, expecting them
984 // to be subsumed into complex addressing expressions or compute them
985 // into registers?
986 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
987 return clone_base_plus_offset_address(m, mstack, address_visited);
988 }
989
990 void Compile::reshape_address(AddPNode* addp) {
991 }
992
993 // Optimize load-acquire.
994 //
995 // Check if acquire is unnecessary due to following operation that does
996 // acquire anyways.
997 // Walk the pattern:
998 //
999 // n: Load.acq
1000 // |
1001 // MemBarAcquire
1002 // | |
2236 case Op_SubVI:
2237 case Op_SubVF:
2238 case Op_SubVD:
2239 case Op_MulVS:
2240 case Op_MulVF:
2241 case Op_MulVD:
2242 case Op_DivVF:
2243 case Op_DivVD:
2244 case Op_AbsVF:
2245 case Op_AbsVD:
2246 case Op_NegVF:
2247 case Op_NegVD:
2248 case Op_SqrtVF:
2249 case Op_SqrtVD:
2250 case Op_AddVL:
2251 case Op_SubVL:
2252 case Op_MulVI:
2253 return SuperwordUseVSX;
2254 case Op_PopCountVI:
2255 return (SuperwordUseVSX && UsePopCountInstruction);
2256 }
2257
2258 return true; // Per default match rules are supported.
2259 }
2260
2261 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2262
2263 // TODO
2264 // identify extra cases that we might want to provide match rules for
2265 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2266 bool ret_value = match_rule_supported(opcode);
2267 // Add rules here.
2268
2269 return ret_value; // Per default match rules are supported.
2270 }
2271
2272 const bool Matcher::has_predicated_vectors(void) {
2273 return false;
2274 }
2275
12377 // registers for new nodes
12378 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12379 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12380
12381 // Insert new nodes.
12382 nodes->push(m1);
12383 nodes->push(m2);
12384 %}
12385 %}
12386
12387 // Compare double, generate -1,0,1
12388 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12389 match(Set dst (CmpD3 src1 src2));
12390 ins_cost(DEFAULT_COST*5+BRANCH_COST);
12391
12392 expand %{
12393 flagsReg tmp1;
12394 cmpDUnordered_reg_reg(tmp1, src1, src2);
12395 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12396 %}
12397 %}
12398
12399 //----------Branches---------------------------------------------------------
12400 // Jump
12401
12402 // Direct Branch.
12403 instruct branch(label labl) %{
12404 match(Goto);
12405 effect(USE labl);
12406 ins_cost(BRANCH_COST);
12407
12408 format %{ "B $labl" %}
12409 size(4);
12410 ins_encode %{
12411 // TODO: PPC port $archOpcode(ppc64Opcode_b);
12412 Label d; // dummy
12413 __ bind(d);
12414 Label* p = $labl$$label;
12415 // `p' is `NULL' when this encoding class is used only to
12416 // determine the size of the encoded instruction.
|
962
963
964 //----------SOURCE BLOCK-------------------------------------------------------
965 // This is a block of C++ code which provides values, functions, and
966 // definitions necessary in the rest of the architecture description.
967 source_hpp %{
968 // Header information of the source block.
969 // Method declarations/definitions which are used outside
970 // the ad-scope can conveniently be defined here.
971 //
972 // To keep related declarations/definitions/uses close together,
973 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
974
975 // Returns true if Node n is followed by a MemBar node that
976 // will do an acquire. If so, this node must not do the acquire
977 // operation.
978 bool followed_by_acquire(const Node *n);
979 %}
980
981 source %{
982 // Should the Matcher clone shifts on addressing modes, expecting them
983 // to be subsumed into complex addressing expressions or compute them
984 // into registers?
985 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
986 return clone_base_plus_offset_address(m, mstack, address_visited);
987 }
988
989 void Compile::reshape_address(AddPNode* addp) {
990 }
991
992 // Optimize load-acquire.
993 //
994 // Check if acquire is unnecessary due to following operation that does
995 // acquire anyways.
996 // Walk the pattern:
997 //
998 // n: Load.acq
999 // |
1000 // MemBarAcquire
1001 // | |
2235 case Op_SubVI:
2236 case Op_SubVF:
2237 case Op_SubVD:
2238 case Op_MulVS:
2239 case Op_MulVF:
2240 case Op_MulVD:
2241 case Op_DivVF:
2242 case Op_DivVD:
2243 case Op_AbsVF:
2244 case Op_AbsVD:
2245 case Op_NegVF:
2246 case Op_NegVD:
2247 case Op_SqrtVF:
2248 case Op_SqrtVD:
2249 case Op_AddVL:
2250 case Op_SubVL:
2251 case Op_MulVI:
2252 return SuperwordUseVSX;
2253 case Op_PopCountVI:
2254 return (SuperwordUseVSX && UsePopCountInstruction);
2255 case Op_DigitC:
2256 case Op_LowerCaseC:
2257 case Op_UpperCaseC:
2258 case Op_WhitespaceC:
2259 return VM_Version::has_darn();
2260 }
2261
2262 return true; // Per default match rules are supported.
2263 }
2264
2265 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2266
2267 // TODO
2268 // identify extra cases that we might want to provide match rules for
2269 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2270 bool ret_value = match_rule_supported(opcode);
2271 // Add rules here.
2272
2273 return ret_value; // Per default match rules are supported.
2274 }
2275
2276 const bool Matcher::has_predicated_vectors(void) {
2277 return false;
2278 }
2279
12381 // registers for new nodes
12382 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12383 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
12384
12385 // Insert new nodes.
12386 nodes->push(m1);
12387 nodes->push(m2);
12388 %}
12389 %}
12390
12391 // Compare double, generate -1,0,1
12392 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
12393 match(Set dst (CmpD3 src1 src2));
12394 ins_cost(DEFAULT_COST*5+BRANCH_COST);
12395
12396 expand %{
12397 flagsReg tmp1;
12398 cmpDUnordered_reg_reg(tmp1, src1, src2);
12399 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
12400 %}
12401 %}
12402
12403 // Compare char
12404 instruct cmprb_DigitC_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12405 match(Set dst (DigitC src1));
12406 effect(TEMP src2, TEMP crx);
12407 ins_cost(3 * DEFAULT_COST);
12408
12409 format %{ "LI $src2, 0x3930\n\t"
12410 "CMPRB $crx, 0, $src1, $src2\n\t"
12411 "SETB $dst, $crx" %}
12412 size(12);
12413 ins_encode %{
12414 // 0x30: 0, 0x39: 9
12415 __ li($src2$$Register, 0x3930);
12416 // compare src1 with ranges 0x30 to 0x39
12417 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12418 __ setb($dst$$Register, $crx$$CondRegister);
12419 %}
12420 ins_pipe(pipe_class_default);
12421 %}
12422
12423 instruct cmprb_LowerCaseC_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12424 match(Set dst (LowerCaseC src1));
12425 effect(TEMP src2, TEMP crx);
12426 ins_cost(12 * DEFAULT_COST);
12427
12428 format %{ "LI $src2, 0x7A61\n\t"
12429 "CMPRB $crx, 0, $src1, $src2\n\t"
12430 "BGT $crx, done\n\t"
12431 "LIS $src2, (signed short)0xF6DF\n\t"
12432 "ORI $src2, $src2, 0xFFF8\n\t"
12433 "CMPRB $crx, 1, $src1, $src2\n\t"
12434 "BGT $crx, done\n\t"
12435 "LIS $src2, (signed short)0xAAB5\n\t"
12436 "ORI $src2, $src2, 0xBABA\n\t"
12437 "INSRDI $src2, $src2, 32, 0\n\t"
12438 "CMPEQB $crx, 1, $src1, $src2\n\t"
12439 "SETB $dst, $crx" %}
12440
12441 size(48);
12442 ins_encode %{
12443 Label done;
12444 // 0x61: a, 0x7A: z
12445 __ li($src2$$Register, 0x7A61);
12446 // compare src1 with ranges 0x61 to 0x7A
12447 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12448 __ bgt($crx$$CondRegister, done);
12449
12450 // 0xDF: sharp s, 0xFF: y with diaeresis, 0xF7 is not the lower case
12451 __ lis($src2$$Register, (signed short)0xF6DF);
12452 __ ori($src2$$Register, $src2$$Register, 0xFFF8);
12453 // compare src1 with ranges 0xDF to 0xF6 and 0xF8 to 0xFF
12454 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12455 __ bgt($crx$$CondRegister, done);
12456
12457 // 0xAA: feminine ordinal indicator
12458 // 0xB5: micro sign
12459 // 0xBA: masculine ordinal indicator
12460 __ lis($src2$$Register, (signed short)0xAAB5);
12461 __ ori($src2$$Register, $src2$$Register, 0xBABA);
12462 __ insrdi($src2$$Register, $src2$$Register, 32, 0);
12463 // compare src1 with 0xAA, 0xB5, and 0xBA
12464 __ cmpeqb($crx$$CondRegister, $src1$$Register, $src2$$Register);
12465
12466 __ bind(done);
12467 __ setb($dst$$Register, $crx$$CondRegister);
12468 %}
12469 ins_pipe(pipe_class_default);
12470 %}
12471
12472 instruct cmprb_UpperCaseC_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12473 match(Set dst (UpperCaseC src1));
12474 effect(TEMP src2, TEMP crx);
12475 ins_cost(7 * DEFAULT_COST);
12476
12477 format %{ "LI $src2, 0x5A41\n\t"
12478 "CMPRB $crx, 0, $src1, $src2\n\t"
12479 "BGT $crx, done\n\t"
12480 "LIS $src2, (signed short)0xD6C0\n\t"
12481 "ORI $src2, $src2, 0xDED8\n\t"
12482 "CMPRB $crx, 1, $src1, $src2\n\t"
12483 "SETB $dst, $crx" %}
12484
12485 size(28);
12486 ins_encode %{
12487 Label done;
12488 // 0x41: A, 0x5A: Z
12489 __ li($src2$$Register, 0x5A41);
12490 // compare src1 with a range 0x41 to 0x5A
12491 __ cmprb($crx$$CondRegister, 0, $src1$$Register, $src2$$Register);
12492 __ bgt($crx$$CondRegister, done);
12493
12494 // 0xC0: a with grave, 0xDE: thorn, 0xD7 is not the upper case
12495 __ lis($src2$$Register, (signed short)0xD6C0);
12496 __ ori($src2$$Register, $src2$$Register, 0xDED8);
12497 // compare src1 with ranges 0xC0 to 0xD6 and 0xD8 to 0xDE
12498 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12499
12500 __ bind(done);
12501 __ setb($dst$$Register, $crx$$CondRegister);
12502 %}
12503 ins_pipe(pipe_class_default);
12504 %}
12505
12506 instruct cmprb_WhitespaceC_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsReg crx) %{
12507 match(Set dst (WhitespaceC src1));
12508 effect(TEMP src2, TEMP crx);
12509 ins_cost(4 * DEFAULT_COST);
12510
12511 format %{ "LI $src2, 0x0D09\n\t"
12512 "ADDIS $src2, 0x201C\n\t"
12513 "CMPRB $crx, 1, $src1, $src2\n\t"
12514 "SETB $dst, $crx" %}
12515 size(16);
12516 ins_encode %{
12517 // 0x09 to 0x0D, 0x1C to 0x20
12518 __ li($src2$$Register, 0x0D09);
12519 __ addis($src2$$Register, $src2$$Register, 0x0201C);
12520 // compare src with ranges 0x09 to 0x0D and 0x1C to 0x20
12521 __ cmprb($crx$$CondRegister, 1, $src1$$Register, $src2$$Register);
12522 __ setb($dst$$Register, $crx$$CondRegister);
12523 %}
12524 ins_pipe(pipe_class_default);
12525 %}
12526
12527 //----------Branches---------------------------------------------------------
12528 // Jump
12529
12530 // Direct Branch.
12531 instruct branch(label labl) %{
12532 match(Goto);
12533 effect(USE labl);
12534 ins_cost(BRANCH_COST);
12535
12536 format %{ "B $labl" %}
12537 size(4);
12538 ins_encode %{
12539 // TODO: PPC port $archOpcode(ppc64Opcode_b);
12540 Label d; // dummy
12541 __ bind(d);
12542 Label* p = $labl$$label;
12543 // `p' is `NULL' when this encoding class is used only to
12544 // determine the size of the encoded instruction.
|