src/hotspot/cpu/ppc/assembler_ppc.hpp
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*** 297,306 ****
--- 297,308 ----
CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1),
CMPI_OPCODE = (11u << OPCODE_SHIFT),
CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
CMPLI_OPCODE = (10u << OPCODE_SHIFT),
+ CMPRB_OPCODE = (31u << OPCODE_SHIFT | 192u << 1),
+ CMPEQB_OPCODE = (31u << OPCODE_SHIFT | 224u << 1),
ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
// Special purpose registers
MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
*** 334,343 ****
--- 336,346 ----
MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
+ SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1),
// condition register logic instructions
CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1),
CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1),
*** 1074,1084 ****
static int frb( int x) { return opp_u_field(x, 20, 16); }
static int frc( int x) { return opp_u_field(x, 25, 21); }
static int frs( int x) { return opp_u_field(x, 10, 6); }
static int frt( int x) { return opp_u_field(x, 10, 6); }
static int fxm( int x) { return opp_u_field(x, 19, 12); }
! static int l10( int x) { return opp_u_field(x, 10, 10); }
static int l14( int x) { return opp_u_field(x, 15, 14); }
static int l15( int x) { return opp_u_field(x, 15, 15); }
static int l910( int x) { return opp_u_field(x, 10, 9); }
static int e1215( int x) { return opp_u_field(x, 15, 12); }
static int lev( int x) { return opp_u_field(x, 26, 20); }
--- 1077,1087 ----
static int frb( int x) { return opp_u_field(x, 20, 16); }
static int frc( int x) { return opp_u_field(x, 25, 21); }
static int frs( int x) { return opp_u_field(x, 10, 6); }
static int frt( int x) { return opp_u_field(x, 10, 6); }
static int fxm( int x) { return opp_u_field(x, 19, 12); }
! static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); }
static int l14( int x) { return opp_u_field(x, 15, 14); }
static int l15( int x) { return opp_u_field(x, 15, 15); }
static int l910( int x) { return opp_u_field(x, 10, 9); }
static int e1215( int x) { return opp_u_field(x, 15, 12); }
static int lev( int x) { return opp_u_field(x, 26, 20); }
*** 1441,1450 ****
--- 1444,1457 ----
inline void cmplwi(ConditionRegister crx, Register a, int ui16);
inline void cmpldi(ConditionRegister crx, Register a, int ui16);
inline void cmplw( ConditionRegister crx, Register a, Register b);
inline void cmpld( ConditionRegister crx, Register a, Register b);
+ // >= Power9
+ inline void cmprb( ConditionRegister bf, int l, Register a, Register b);
+ inline void cmpeqb(ConditionRegister bf, Register a, Register b);
+
inline void isel( Register d, Register a, Register b, int bc);
// Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
// Set d = 0 if (cr.cc) equals 1, otherwise b.
inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
*** 1640,1649 ****
--- 1647,1658 ----
inline void mfctr(Register d);
inline void mtcrf(int fxm, Register s);
inline void mfcr( Register d);
inline void mcrf( ConditionRegister crd, ConditionRegister cra);
inline void mtcr( Register s);
+ // >= Power9
+ inline void setb( Register d, ConditionRegister cra);
// Special purpose registers
// Exception Register
inline void mtxer(Register s1);
inline void mfxer(Register d);