src/hotspot/cpu/ppc/assembler_ppc.hpp

Print this page




 380 
 381     STH_OPCODE   = (44u << OPCODE_SHIFT),
 382     STHX_OPCODE  = (31u << OPCODE_SHIFT | 407u << 1),
 383     STHU_OPCODE  = (45u << OPCODE_SHIFT),
 384     STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1),
 385 
 386     STB_OPCODE   = (38u << OPCODE_SHIFT),
 387     STBX_OPCODE  = (31u << OPCODE_SHIFT | 215u << 1),
 388     STBU_OPCODE  = (39u << OPCODE_SHIFT),
 389 
 390     EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
 391     EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
 392     EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1),               // X-FORM
 393 
 394     // 32 bit opcode encodings
 395 
 396     LWA_OPCODE    = (58u << OPCODE_SHIFT |   2u << XO_30_31_SHIFT), // DS-FORM
 397     LWAX_OPCODE   = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
 398 
 399     CNTLZW_OPCODE = (31u << OPCODE_SHIFT |  26u << XO_21_30_SHIFT), // X-FORM

 400 
 401     // 64 bit opcode encodings
 402 
 403     LD_OPCODE     = (58u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
 404     LDU_OPCODE    = (58u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
 405     LDX_OPCODE    = (31u << OPCODE_SHIFT |  21u << XO_21_30_SHIFT), // X-FORM
 406     LDBRX_OPCODE  = (31u << OPCODE_SHIFT | 532u << 1),              // X-FORM
 407 
 408     STD_OPCODE    = (62u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
 409     STDU_OPCODE   = (62u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
 410     STDUX_OPCODE  = (31u << OPCODE_SHIFT | 181u << 1),              // X-FORM
 411     STDX_OPCODE   = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
 412     STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1),              // X-FORM
 413 
 414     RLDICR_OPCODE = (30u << OPCODE_SHIFT |   1u << XO_27_29_SHIFT), // MD-FORM
 415     RLDICL_OPCODE = (30u << OPCODE_SHIFT |   0u << XO_27_29_SHIFT), // MD-FORM
 416     RLDIC_OPCODE  = (30u << OPCODE_SHIFT |   2u << XO_27_29_SHIFT), // MD-FORM
 417     RLDIMI_OPCODE = (30u << OPCODE_SHIFT |   3u << XO_27_29_SHIFT), // MD-FORM
 418 
 419     SRADI_OPCODE  = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
 420 
 421     SLD_OPCODE    = (31u << OPCODE_SHIFT |  27u << 1),              // X-FORM
 422     SRD_OPCODE    = (31u << OPCODE_SHIFT | 539u << 1),              // X-FORM
 423     SRAD_OPCODE   = (31u << OPCODE_SHIFT | 794u << 1),              // X-FORM
 424 
 425     MULLD_OPCODE  = (31u << OPCODE_SHIFT | 233u << 1),              // XO-FORM
 426     MULHD_OPCODE  = (31u << OPCODE_SHIFT |  73u << 1),              // XO-FORM
 427     MULHDU_OPCODE = (31u << OPCODE_SHIFT |   9u << 1),              // XO-FORM
 428     DIVD_OPCODE   = (31u << OPCODE_SHIFT | 489u << 1),              // XO-FORM
 429 
 430     CNTLZD_OPCODE = (31u << OPCODE_SHIFT |  58u << XO_21_30_SHIFT), // X-FORM

 431     NAND_OPCODE   = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
 432     NOR_OPCODE    = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
 433 
 434 
 435     // opcodes only used for floating arithmetic
 436     FADD_OPCODE   = (63u << OPCODE_SHIFT |  21u << 1),
 437     FADDS_OPCODE  = (59u << OPCODE_SHIFT |  21u << 1),
 438     FCMPU_OPCODE  = (63u << OPCODE_SHIFT |  00u << 1),
 439     FDIV_OPCODE   = (63u << OPCODE_SHIFT |  18u << 1),
 440     FDIVS_OPCODE  = (59u << OPCODE_SHIFT |  18u << 1),
 441     FMR_OPCODE    = (63u << OPCODE_SHIFT |  72u << 1),
 442     // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
 443     // on Power7.  Do not use.
 444     // MFFGPR_OPCODE  = (31u << OPCODE_SHIFT | 607u << 1),
 445     // MFTGPR_OPCODE  = (31u << OPCODE_SHIFT | 735u << 1),
 446     CMPB_OPCODE    = (31u << OPCODE_SHIFT |  508  << 1),
 447     POPCNTB_OPCODE = (31u << OPCODE_SHIFT |  122  << 1),
 448     POPCNTW_OPCODE = (31u << OPCODE_SHIFT |  378  << 1),
 449     POPCNTD_OPCODE = (31u << OPCODE_SHIFT |  506  << 1),
 450     FABS_OPCODE    = (63u << OPCODE_SHIFT |  264u << 1),


1483   inline void nop();
1484   // NOP for FP and BR units (different versions to allow them to be in one group)
1485   inline void fpnop0();
1486   inline void fpnop1();
1487   inline void brnop0();
1488   inline void brnop1();
1489   inline void brnop2();
1490 
1491   inline void mr(      Register d, Register s);
1492   inline void ori_opt( Register d, int ui16);
1493   inline void oris_opt(Register d, int ui16);
1494 
1495   // endgroup opcode for Power6
1496   inline void endgroup();
1497 
1498   // count instructions
1499   inline void cntlzw(  Register a, Register s);
1500   inline void cntlzw_( Register a, Register s);
1501   inline void cntlzd(  Register a, Register s);
1502   inline void cntlzd_( Register a, Register s);




1503 
1504   // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1505   inline void sld(     Register a, Register s, Register b);
1506   inline void sld_(    Register a, Register s, Register b);
1507   inline void slw(     Register a, Register s, Register b);
1508   inline void slw_(    Register a, Register s, Register b);
1509   inline void srd(     Register a, Register s, Register b);
1510   inline void srd_(    Register a, Register s, Register b);
1511   inline void srw(     Register a, Register s, Register b);
1512   inline void srw_(    Register a, Register s, Register b);
1513   inline void srad(    Register a, Register s, Register b);
1514   inline void srad_(   Register a, Register s, Register b);
1515   inline void sraw(    Register a, Register s, Register b);
1516   inline void sraw_(   Register a, Register s, Register b);
1517   inline void sradi(   Register a, Register s, int sh6);
1518   inline void sradi_(  Register a, Register s, int sh6);
1519   inline void srawi(   Register a, Register s, int sh5);
1520   inline void srawi_(  Register a, Register s, int sh5);
1521 
1522   // extended mnemonics for Shift Instructions




 380 
 381     STH_OPCODE   = (44u << OPCODE_SHIFT),
 382     STHX_OPCODE  = (31u << OPCODE_SHIFT | 407u << 1),
 383     STHU_OPCODE  = (45u << OPCODE_SHIFT),
 384     STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1),
 385 
 386     STB_OPCODE   = (38u << OPCODE_SHIFT),
 387     STBX_OPCODE  = (31u << OPCODE_SHIFT | 215u << 1),
 388     STBU_OPCODE  = (39u << OPCODE_SHIFT),
 389 
 390     EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
 391     EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
 392     EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1),               // X-FORM
 393 
 394     // 32 bit opcode encodings
 395 
 396     LWA_OPCODE    = (58u << OPCODE_SHIFT |   2u << XO_30_31_SHIFT), // DS-FORM
 397     LWAX_OPCODE   = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
 398 
 399     CNTLZW_OPCODE = (31u << OPCODE_SHIFT |  26u << XO_21_30_SHIFT), // X-FORM
 400     CNTTZW_OPCODE = (31u << OPCODE_SHIFT | 538u << XO_21_30_SHIFT), // X-FORM
 401 
 402     // 64 bit opcode encodings
 403 
 404     LD_OPCODE     = (58u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
 405     LDU_OPCODE    = (58u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
 406     LDX_OPCODE    = (31u << OPCODE_SHIFT |  21u << XO_21_30_SHIFT), // X-FORM
 407     LDBRX_OPCODE  = (31u << OPCODE_SHIFT | 532u << 1),              // X-FORM
 408 
 409     STD_OPCODE    = (62u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
 410     STDU_OPCODE   = (62u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
 411     STDUX_OPCODE  = (31u << OPCODE_SHIFT | 181u << 1),              // X-FORM
 412     STDX_OPCODE   = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
 413     STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1),              // X-FORM
 414 
 415     RLDICR_OPCODE = (30u << OPCODE_SHIFT |   1u << XO_27_29_SHIFT), // MD-FORM
 416     RLDICL_OPCODE = (30u << OPCODE_SHIFT |   0u << XO_27_29_SHIFT), // MD-FORM
 417     RLDIC_OPCODE  = (30u << OPCODE_SHIFT |   2u << XO_27_29_SHIFT), // MD-FORM
 418     RLDIMI_OPCODE = (30u << OPCODE_SHIFT |   3u << XO_27_29_SHIFT), // MD-FORM
 419 
 420     SRADI_OPCODE  = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
 421 
 422     SLD_OPCODE    = (31u << OPCODE_SHIFT |  27u << 1),              // X-FORM
 423     SRD_OPCODE    = (31u << OPCODE_SHIFT | 539u << 1),              // X-FORM
 424     SRAD_OPCODE   = (31u << OPCODE_SHIFT | 794u << 1),              // X-FORM
 425 
 426     MULLD_OPCODE  = (31u << OPCODE_SHIFT | 233u << 1),              // XO-FORM
 427     MULHD_OPCODE  = (31u << OPCODE_SHIFT |  73u << 1),              // XO-FORM
 428     MULHDU_OPCODE = (31u << OPCODE_SHIFT |   9u << 1),              // XO-FORM
 429     DIVD_OPCODE   = (31u << OPCODE_SHIFT | 489u << 1),              // XO-FORM
 430 
 431     CNTLZD_OPCODE = (31u << OPCODE_SHIFT |  58u << XO_21_30_SHIFT), // X-FORM
 432     CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM
 433     NAND_OPCODE   = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
 434     NOR_OPCODE    = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
 435 
 436 
 437     // opcodes only used for floating arithmetic
 438     FADD_OPCODE   = (63u << OPCODE_SHIFT |  21u << 1),
 439     FADDS_OPCODE  = (59u << OPCODE_SHIFT |  21u << 1),
 440     FCMPU_OPCODE  = (63u << OPCODE_SHIFT |  00u << 1),
 441     FDIV_OPCODE   = (63u << OPCODE_SHIFT |  18u << 1),
 442     FDIVS_OPCODE  = (59u << OPCODE_SHIFT |  18u << 1),
 443     FMR_OPCODE    = (63u << OPCODE_SHIFT |  72u << 1),
 444     // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
 445     // on Power7.  Do not use.
 446     // MFFGPR_OPCODE  = (31u << OPCODE_SHIFT | 607u << 1),
 447     // MFTGPR_OPCODE  = (31u << OPCODE_SHIFT | 735u << 1),
 448     CMPB_OPCODE    = (31u << OPCODE_SHIFT |  508  << 1),
 449     POPCNTB_OPCODE = (31u << OPCODE_SHIFT |  122  << 1),
 450     POPCNTW_OPCODE = (31u << OPCODE_SHIFT |  378  << 1),
 451     POPCNTD_OPCODE = (31u << OPCODE_SHIFT |  506  << 1),
 452     FABS_OPCODE    = (63u << OPCODE_SHIFT |  264u << 1),


1485   inline void nop();
1486   // NOP for FP and BR units (different versions to allow them to be in one group)
1487   inline void fpnop0();
1488   inline void fpnop1();
1489   inline void brnop0();
1490   inline void brnop1();
1491   inline void brnop2();
1492 
1493   inline void mr(      Register d, Register s);
1494   inline void ori_opt( Register d, int ui16);
1495   inline void oris_opt(Register d, int ui16);
1496 
1497   // endgroup opcode for Power6
1498   inline void endgroup();
1499 
1500   // count instructions
1501   inline void cntlzw(  Register a, Register s);
1502   inline void cntlzw_( Register a, Register s);
1503   inline void cntlzd(  Register a, Register s);
1504   inline void cntlzd_( Register a, Register s);
1505   inline void cnttzw(  Register a, Register s);
1506   inline void cnttzw_( Register a, Register s);
1507   inline void cnttzd(  Register a, Register s);
1508   inline void cnttzd_( Register a, Register s);
1509 
1510   // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1511   inline void sld(     Register a, Register s, Register b);
1512   inline void sld_(    Register a, Register s, Register b);
1513   inline void slw(     Register a, Register s, Register b);
1514   inline void slw_(    Register a, Register s, Register b);
1515   inline void srd(     Register a, Register s, Register b);
1516   inline void srd_(    Register a, Register s, Register b);
1517   inline void srw(     Register a, Register s, Register b);
1518   inline void srw_(    Register a, Register s, Register b);
1519   inline void srad(    Register a, Register s, Register b);
1520   inline void srad_(   Register a, Register s, Register b);
1521   inline void sraw(    Register a, Register s, Register b);
1522   inline void sraw_(   Register a, Register s, Register b);
1523   inline void sradi(   Register a, Register s, int sh6);
1524   inline void sradi_(  Register a, Register s, int sh6);
1525   inline void srawi(   Register a, Register s, int sh5);
1526   inline void srawi_(  Register a, Register s, int sh5);
1527 
1528   // extended mnemonics for Shift Instructions