109 product(uint64_t,DSCR_PPC64, (uintx)-1, \ 110 "Power8 or later: Specify encoded value for Data Stream Control " \ 111 "Register") \ 112 product(uint64_t,DSCR_DPFD_PPC64, 8, \ 113 "Power8 or later: DPFD (default prefetch depth) value of the " \ 114 "Data Stream Control Register." \ 115 " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch") \ 116 product(uint64_t,DSCR_URG_PPC64, 8, \ 117 "Power8 or later: URG (depth attainment urgency) value of the " \ 118 "Data Stream Control Register." \ 119 " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch") \ 120 \ 121 product(bool, UseLoadInstructionsForStackBangingPPC64, false, \ 122 "Use load instructions for stack banging.") \ 123 \ 124 /* special instructions */ \ 125 \ 126 product(bool, UseCountLeadingZerosInstructionsPPC64, true, \ 127 "Use count leading zeros instructions.") \ 128 \ 129 product(bool, UseExtendedLoadAndReserveInstructionsPPC64, false, \ 130 "Use extended versions of load-and-reserve instructions.") \ 131 \ 132 product(bool, UseRotateAndMaskInstructionsPPC64, true, \ 133 "Use rotate and mask instructions.") \ 134 \ 135 product(bool, UseStaticBranchPredictionInCompareAndSwapPPC64, true, \ 136 "Use static branch prediction hints in CAS operations.") \ 137 product(bool, UseStaticBranchPredictionForUncommonPathsPPC64, false, \ 138 "Use static branch prediction hints for uncommon paths.") \ 139 \ 140 product(bool, UsePower6SchedulerPPC64, false, \ 141 "Use Power6 Scheduler.") \ 142 \ 143 product(bool, InsertEndGroupPPC64, false, \ 144 "Insert EndGroup instructions to optimize for Power6.") \ 145 \ 146 /* Trap based checks. */ \ 147 /* Trap based checks use the ppc trap instructions to check certain */ \ 148 /* conditions. This instruction raises a SIGTRAP caught by the */ \ | 109 product(uint64_t,DSCR_PPC64, (uintx)-1, \ 110 "Power8 or later: Specify encoded value for Data Stream Control " \ 111 "Register") \ 112 product(uint64_t,DSCR_DPFD_PPC64, 8, \ 113 "Power8 or later: DPFD (default prefetch depth) value of the " \ 114 "Data Stream Control Register." \ 115 " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch") \ 116 product(uint64_t,DSCR_URG_PPC64, 8, \ 117 "Power8 or later: URG (depth attainment urgency) value of the " \ 118 "Data Stream Control Register." \ 119 " 0: hardware default, 1: none, 2-7: min-max, 8: don't touch") \ 120 \ 121 product(bool, UseLoadInstructionsForStackBangingPPC64, false, \ 122 "Use load instructions for stack banging.") \ 123 \ 124 /* special instructions */ \ 125 \ 126 product(bool, UseCountLeadingZerosInstructionsPPC64, true, \ 127 "Use count leading zeros instructions.") \ 128 \ 129 product(bool, UseCountTrailingZerosInstructionsPPC64, false, \ 130 "Use count trailing zeros instructions.") \ 131 \ 132 product(bool, UseExtendedLoadAndReserveInstructionsPPC64, false, \ 133 "Use extended versions of load-and-reserve instructions.") \ 134 \ 135 product(bool, UseRotateAndMaskInstructionsPPC64, true, \ 136 "Use rotate and mask instructions.") \ 137 \ 138 product(bool, UseStaticBranchPredictionInCompareAndSwapPPC64, true, \ 139 "Use static branch prediction hints in CAS operations.") \ 140 product(bool, UseStaticBranchPredictionForUncommonPathsPPC64, false, \ 141 "Use static branch prediction hints for uncommon paths.") \ 142 \ 143 product(bool, UsePower6SchedulerPPC64, false, \ 144 "Use Power6 Scheduler.") \ 145 \ 146 product(bool, InsertEndGroupPPC64, false, \ 147 "Insert EndGroup instructions to optimize for Power6.") \ 148 \ 149 /* Trap based checks. */ \ 150 /* Trap based checks use the ppc trap instructions to check certain */ \ 151 /* conditions. This instruction raises a SIGTRAP caught by the */ \ |