src/hotspot/cpu/ppc/ppc.ad

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2192 
2193 //=============================================================================
2194 
2195 // Use a frame slots bias for frameless methods if accessing the stack.
2196 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2197   if (as_Register(reg_enc) == R1_SP) {
2198     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2199   }
2200   return 0;
2201 }
2202 
2203 const bool Matcher::match_rule_supported(int opcode) {
2204   if (!has_match_rule(opcode))
2205     return false;
2206 
2207   switch (opcode) {
2208   case Op_SqrtD:
2209     return VM_Version::has_fsqrt();
2210   case Op_CountLeadingZerosI:
2211   case Op_CountLeadingZerosL:



2212   case Op_CountTrailingZerosI:
2213   case Op_CountTrailingZerosL:
2214     if (!UseCountLeadingZerosInstructionsPPC64)

2215       return false;
2216     break;
2217 
2218   case Op_PopCountI:
2219   case Op_PopCountL:
2220     return (UsePopCountInstruction && VM_Version::has_popcntw());
2221 
2222   case Op_StrComp:
2223     return SpecialStringCompareTo;
2224   case Op_StrEquals:
2225     return SpecialStringEquals;
2226   case Op_StrIndexOf:
2227   case Op_StrIndexOfChar:
2228     return SpecialStringIndexOf;
2229   case Op_AddVB:
2230   case Op_AddVS:
2231   case Op_AddVI:
2232   case Op_AddVF:
2233   case Op_AddVD:
2234   case Op_SubVB:


13408   %}
13409   ins_pipe(pipe_class_default);
13410 %}
13411 
13412 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
13413   // no match-rule, false predicate
13414   effect(DEF dst, USE src);
13415   predicate(false);
13416 
13417   format %{ "CNTLZD  $dst, $src" %}
13418   size(4);
13419   ins_encode %{
13420     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
13421     __ cntlzd($dst$$Register, $src$$Register);
13422   %}
13423   ins_pipe(pipe_class_default);
13424 %}
13425 
13426 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
13427   match(Set dst (CountTrailingZerosI src));
13428   predicate(UseCountLeadingZerosInstructionsPPC64);
13429   ins_cost(DEFAULT_COST);
13430 
13431   expand %{
13432     immI16 imm1 %{ (int)-1 %}
13433     immI16 imm2 %{ (int)32 %}
13434     immI_minus1 m1 %{ -1 %}
13435     iRegIdst tmpI1;
13436     iRegIdst tmpI2;
13437     iRegIdst tmpI3;
13438     addI_reg_imm16(tmpI1, src, imm1);
13439     andcI_reg_reg(tmpI2, src, m1, tmpI1);
13440     countLeadingZerosI(tmpI3, tmpI2);
13441     subI_imm16_reg(dst, imm2, tmpI3);
13442   %}
13443 %}
13444 













13445 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
13446   match(Set dst (CountTrailingZerosL src));
13447   predicate(UseCountLeadingZerosInstructionsPPC64);
13448   ins_cost(DEFAULT_COST);
13449 
13450   expand %{
13451     immL16 imm1 %{ (long)-1 %}
13452     immI16 imm2 %{ (int)64 %}
13453     iRegLdst tmpL1;
13454     iRegLdst tmpL2;
13455     iRegIdst tmpL3;
13456     addL_reg_imm16(tmpL1, src, imm1);
13457     andcL_reg_reg(tmpL2, tmpL1, src);
13458     countLeadingZerosL(tmpL3, tmpL2);
13459     subI_imm16_reg(dst, imm2, tmpL3);
13460  %}













13461 %}
13462 
13463 // Expand nodes for byte_reverse_int.
13464 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
13465   effect(DEF dst, USE src, USE pos, USE shift);
13466   predicate(false);
13467 
13468   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
13469   size(4);
13470   ins_encode %{
13471     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
13472     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
13473   %}
13474   ins_pipe(pipe_class_default);
13475 %}
13476 
13477 // As insrwi_a, but with USE_DEF.
13478 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
13479   effect(USE_DEF dst, USE src, USE pos, USE shift);
13480   predicate(false);




2192 
2193 //=============================================================================
2194 
2195 // Use a frame slots bias for frameless methods if accessing the stack.
2196 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2197   if (as_Register(reg_enc) == R1_SP) {
2198     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2199   }
2200   return 0;
2201 }
2202 
2203 const bool Matcher::match_rule_supported(int opcode) {
2204   if (!has_match_rule(opcode))
2205     return false;
2206 
2207   switch (opcode) {
2208   case Op_SqrtD:
2209     return VM_Version::has_fsqrt();
2210   case Op_CountLeadingZerosI:
2211   case Op_CountLeadingZerosL:
2212     if (!UseCountLeadingZerosInstructionsPPC64)
2213       return false;
2214     break;
2215   case Op_CountTrailingZerosI:
2216   case Op_CountTrailingZerosL:
2217     if (!UseCountLeadingZerosInstructionsPPC64 &&
2218         !UseCountTrailingZerosInstructionsPPC64)
2219       return false;
2220     break;
2221 
2222   case Op_PopCountI:
2223   case Op_PopCountL:
2224     return (UsePopCountInstruction && VM_Version::has_popcntw());
2225 
2226   case Op_StrComp:
2227     return SpecialStringCompareTo;
2228   case Op_StrEquals:
2229     return SpecialStringEquals;
2230   case Op_StrIndexOf:
2231   case Op_StrIndexOfChar:
2232     return SpecialStringIndexOf;
2233   case Op_AddVB:
2234   case Op_AddVS:
2235   case Op_AddVI:
2236   case Op_AddVF:
2237   case Op_AddVD:
2238   case Op_SubVB:


13412   %}
13413   ins_pipe(pipe_class_default);
13414 %}
13415 
13416 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
13417   // no match-rule, false predicate
13418   effect(DEF dst, USE src);
13419   predicate(false);
13420 
13421   format %{ "CNTLZD  $dst, $src" %}
13422   size(4);
13423   ins_encode %{
13424     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
13425     __ cntlzd($dst$$Register, $src$$Register);
13426   %}
13427   ins_pipe(pipe_class_default);
13428 %}
13429 
13430 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
13431   match(Set dst (CountTrailingZerosI src));
13432   predicate(UseCountLeadingZerosInstructionsPPC64 && !UseCountTrailingZerosInstructionsPPC64);
13433   ins_cost(DEFAULT_COST);
13434 
13435   expand %{
13436     immI16 imm1 %{ (int)-1 %}
13437     immI16 imm2 %{ (int)32 %}
13438     immI_minus1 m1 %{ -1 %}
13439     iRegIdst tmpI1;
13440     iRegIdst tmpI2;
13441     iRegIdst tmpI3;
13442     addI_reg_imm16(tmpI1, src, imm1);
13443     andcI_reg_reg(tmpI2, src, m1, tmpI1);
13444     countLeadingZerosI(tmpI3, tmpI2);
13445     subI_imm16_reg(dst, imm2, tmpI3);
13446   %}
13447 %}
13448 
13449 instruct countTrailingZerosI_cnttzw_Ex(iRegIdst dst, iRegIsrc src) %{
13450   match(Set dst (CountTrailingZerosI src));
13451   predicate(UseCountTrailingZerosInstructionsPPC64);
13452   ins_cost(DEFAULT_COST);
13453 
13454   format %{ "CNTTZW  $dst, $src" %}
13455   size(4);
13456   ins_encode %{
13457     __ cnttzw($dst$$Register, $src$$Register);
13458   %}
13459   ins_pipe(pipe_class_default);
13460 %}
13461 
13462 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
13463   match(Set dst (CountTrailingZerosL src));
13464   predicate(UseCountLeadingZerosInstructionsPPC64 && !UseCountTrailingZerosInstructionsPPC64);
13465   ins_cost(DEFAULT_COST);
13466 
13467   expand %{
13468     immL16 imm1 %{ (long)-1 %}
13469     immI16 imm2 %{ (int)64 %}
13470     iRegLdst tmpL1;
13471     iRegLdst tmpL2;
13472     iRegIdst tmpL3;
13473     addL_reg_imm16(tmpL1, src, imm1);
13474     andcL_reg_reg(tmpL2, tmpL1, src);
13475     countLeadingZerosL(tmpL3, tmpL2);
13476     subI_imm16_reg(dst, imm2, tmpL3);
13477  %}
13478 %}
13479 
13480 instruct countTrailingZerosL_cnttzd_Ex(iRegIdst dst, iRegLsrc src) %{
13481   match(Set dst (CountTrailingZerosL src));
13482   predicate(UseCountTrailingZerosInstructionsPPC64);
13483   ins_cost(DEFAULT_COST);
13484 
13485   format %{ "CNTTZD  $dst, $src" %}
13486   size(4);
13487   ins_encode %{
13488     __ cnttzd($dst$$Register, $src$$Register);
13489   %}
13490   ins_pipe(pipe_class_default);
13491 %}
13492 
13493 // Expand nodes for byte_reverse_int.
13494 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
13495   effect(DEF dst, USE src, USE pos, USE shift);
13496   predicate(false);
13497 
13498   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
13499   size(4);
13500   ins_encode %{
13501     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
13502     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
13503   %}
13504   ins_pipe(pipe_class_default);
13505 %}
13506 
13507 // As insrwi_a, but with USE_DEF.
13508 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
13509   effect(USE_DEF dst, USE src, USE pos, USE shift);
13510   predicate(false);