1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2018, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "jvm.h"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "utilities/align.hpp"
36 #include "utilities/defaultStream.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "vm_version_ppc.hpp"
39
40 #include <sys/sysinfo.h>
41
42 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
43 #include <sys/auxv.h>
44
45 #ifndef PPC_FEATURE2_HTM_NOSC
46 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
47 #endif
48 #endif
49
50 bool VM_Version::_is_determine_features_test_running = false;
51 uint64_t VM_Version::_dscr_val = 0;
52
53 #define MSG(flag) \
54 if (flag && !FLAG_IS_DEFAULT(flag)) \
55 jio_fprintf(defaultStream::error_stream(), \
56 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
57 " -XX:+" #flag " will be disabled!\n");
58
59 void VM_Version::initialize() {
60
61 // Test which instructions are supported and measure cache line size.
62 determine_features();
63
64 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
65 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
66 if (VM_Version::has_darn()) {
67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 9);
68 } else if (VM_Version::has_lqarx()) {
69 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
70 } else if (VM_Version::has_popcntw()) {
71 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
72 } else if (VM_Version::has_cmpb()) {
73 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
74 } else if (VM_Version::has_popcntb()) {
75 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
76 } else {
77 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
78 }
79 }
80
81 bool PowerArchitecturePPC64_ok = false;
82 switch (PowerArchitecturePPC64) {
83 case 9: if (!VM_Version::has_darn() ) break;
84 case 8: if (!VM_Version::has_lqarx() ) break;
85 case 7: if (!VM_Version::has_popcntw()) break;
86 case 6: if (!VM_Version::has_cmpb() ) break;
87 case 5: if (!VM_Version::has_popcntb()) break;
88 case 0: PowerArchitecturePPC64_ok = true; break;
89 default: break;
90 }
91 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
92 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
93
94 // Power 8: Configure Data Stream Control Register.
95 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
96 config_dscr();
97 }
98
99 if (!UseSIGTRAP) {
100 MSG(TrapBasedICMissChecks);
101 MSG(TrapBasedNotEntrantChecks);
102 MSG(TrapBasedNullChecks);
103 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
104 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
105 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
106 }
107
108 #ifdef COMPILER2
109 if (!UseSIGTRAP) {
110 MSG(TrapBasedRangeChecks);
111 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
112 }
113
114 // On Power6 test for section size.
115 if (PowerArchitecturePPC64 == 6) {
116 determine_section_size();
117 // TODO: PPC port } else {
118 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
119 }
120
121 if (PowerArchitecturePPC64 >= 8) {
122 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
123 FLAG_SET_ERGO(bool, SuperwordUseVSX, true);
124 }
125 } else {
126 if (SuperwordUseVSX) {
127 warning("SuperwordUseVSX specified, but needs at least Power8.");
128 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
129 }
130 }
131 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
132 #endif
133
134 // Create and print feature-string.
135 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
136 jio_snprintf(buf, sizeof(buf),
137 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
138 (has_fsqrt() ? " fsqrt" : ""),
139 (has_isel() ? " isel" : ""),
140 (has_lxarxeh() ? " lxarxeh" : ""),
141 (has_cmpb() ? " cmpb" : ""),
142 (has_popcntb() ? " popcntb" : ""),
143 (has_popcntw() ? " popcntw" : ""),
144 (has_fcfids() ? " fcfids" : ""),
145 (has_vand() ? " vand" : ""),
146 (has_lqarx() ? " lqarx" : ""),
147 (has_vcipher() ? " aes" : ""),
148 (has_vpmsumb() ? " vpmsumb" : ""),
149 (has_mfdscr() ? " mfdscr" : ""),
150 (has_vsx() ? " vsx" : ""),
151 (has_ldbrx() ? " ldbrx" : ""),
152 (has_stdbrx() ? " stdbrx" : ""),
153 (has_vshasig() ? " sha" : ""),
154 (has_tm() ? " rtm" : ""),
155 (has_darn() ? " darn" : "")
156 // Make sure number of %s matches num_features!
157 );
158 _features_string = os::strdup(buf);
159 if (Verbose) {
160 print_features();
161 }
162
163 // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
164 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
165 _supports_cx8 = true;
166
167 // Used by C1.
168 _supports_atomic_getset4 = true;
169 _supports_atomic_getadd4 = true;
170 _supports_atomic_getset8 = true;
171 _supports_atomic_getadd8 = true;
172
173 UseSSE = 0; // Only on x86 and x64
174
175 intx cache_line_size = L1_data_cache_line_size();
176
177 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
178
179 if (AllocatePrefetchStyle == 4) {
180 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
181 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
182 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
183 } else {
184 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
185 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
186 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
187 }
188
189 assert(AllocatePrefetchLines > 0, "invalid value");
190 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
191 AllocatePrefetchLines = 1; // Conservative value.
192 }
193
194 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
195 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
196 }
197
198 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
199
200 // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
201 // In all other cases, the implementation uses only generally available instructions.
202 if (!UseCRC32Intrinsics) {
203 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
204 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
205 }
206 }
207
208 // Implementation does not use any of the vector instructions available with Power8.
209 // Their exploitation is still pending (aka "work in progress").
210 if (!UseCRC32CIntrinsics) {
211 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
212 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
213 }
214 }
215
216 // TODO: Provide implementation.
217 if (UseAdler32Intrinsics) {
218 warning("Adler32Intrinsics not available on this CPU.");
219 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
220 }
221
222 // The AES intrinsic stubs require AES instruction support.
223 if (has_vcipher()) {
224 if (FLAG_IS_DEFAULT(UseAES)) {
225 UseAES = true;
226 }
227 } else if (UseAES) {
228 if (!FLAG_IS_DEFAULT(UseAES))
229 warning("AES instructions are not available on this CPU");
230 FLAG_SET_DEFAULT(UseAES, false);
231 }
232
233 if (UseAES && has_vcipher()) {
234 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
235 UseAESIntrinsics = true;
236 }
237 } else if (UseAESIntrinsics) {
238 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
239 warning("AES intrinsics are not available on this CPU");
240 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
241 }
242
243 if (UseAESCTRIntrinsics) {
244 warning("AES/CTR intrinsics are not available on this CPU");
245 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
246 }
247
248 if (UseGHASHIntrinsics) {
249 warning("GHASH intrinsics are not available on this CPU");
250 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
251 }
252
253 if (FLAG_IS_DEFAULT(UseFMA)) {
254 FLAG_SET_DEFAULT(UseFMA, true);
255 }
256
257 if (has_vshasig()) {
258 if (FLAG_IS_DEFAULT(UseSHA)) {
259 UseSHA = true;
260 }
261 } else if (UseSHA) {
262 if (!FLAG_IS_DEFAULT(UseSHA))
263 warning("SHA instructions are not available on this CPU");
264 FLAG_SET_DEFAULT(UseSHA, false);
265 }
266
267 if (UseSHA1Intrinsics) {
268 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
269 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
270 }
271
272 if (UseSHA && has_vshasig()) {
273 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
274 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
275 }
276 } else if (UseSHA256Intrinsics) {
277 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
278 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
279 }
280
281 if (UseSHA && has_vshasig()) {
282 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
283 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
284 }
285 } else if (UseSHA512Intrinsics) {
286 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
287 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
288 }
289
290 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
291 FLAG_SET_DEFAULT(UseSHA, false);
292 }
293
294 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
295 UseSquareToLenIntrinsic = true;
296 }
297 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
298 UseMulAddIntrinsic = true;
299 }
300 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
301 UseMultiplyToLenIntrinsic = true;
302 }
303 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
304 UseMontgomeryMultiplyIntrinsic = true;
305 }
306 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
307 UseMontgomerySquareIntrinsic = true;
308 }
309
310 if (UseVectorizedMismatchIntrinsic) {
311 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
312 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
313 }
314
315
316 // Adjust RTM (Restricted Transactional Memory) flags.
317 if (UseRTMLocking) {
318 // If CPU or OS do not support TM:
319 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
320 // setting during arguments processing. See use_biased_locking().
321 // VM_Version_init() is executed after UseBiasedLocking is used
322 // in Thread::allocate().
323 if (PowerArchitecturePPC64 < 8) {
324 vm_exit_during_initialization("RTM instructions are not available on this CPU.");
325 }
326
327 if (!has_tm()) {
328 vm_exit_during_initialization("RTM is not supported on this OS version.");
329 }
330 }
331
332 if (UseRTMLocking) {
333 #if INCLUDE_RTM_OPT
334 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
335 // RTM locking should be used only for applications with
336 // high lock contention. For now we do not use it by default.
337 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
338 }
339 #else
340 // Only C2 does RTM locking optimization.
341 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
342 // setting during arguments processing. See use_biased_locking().
343 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
344 #endif
345 } else { // !UseRTMLocking
346 if (UseRTMForStackLocks) {
347 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
348 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
349 }
350 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
351 }
352 if (UseRTMDeopt) {
353 FLAG_SET_DEFAULT(UseRTMDeopt, false);
354 }
355 if (PrintPreciseRTMLockingStatistics) {
356 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
357 }
358 }
359
360 // This machine allows unaligned memory accesses
361 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
362 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
363 }
364 }
365
366 bool VM_Version::use_biased_locking() {
367 #if INCLUDE_RTM_OPT
368 // RTM locking is most useful when there is high lock contention and
369 // low data contention. With high lock contention the lock is usually
370 // inflated and biased locking is not suitable for that case.
371 // RTM locking code requires that biased locking is off.
372 // Note: we can't switch off UseBiasedLocking in get_processor_features()
373 // because it is used by Thread::allocate() which is called before
374 // VM_Version::initialize().
375 if (UseRTMLocking && UseBiasedLocking) {
376 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
377 FLAG_SET_DEFAULT(UseBiasedLocking, false);
378 } else {
379 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
380 UseBiasedLocking = false;
381 }
382 }
383 #endif
384 return UseBiasedLocking;
385 }
386
387 void VM_Version::print_features() {
388 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
389 }
390
391 #ifdef COMPILER2
392 // Determine section size on power6: If section size is 8 instructions,
393 // there should be a difference between the two testloops of ~15 %. If
394 // no difference is detected the section is assumed to be 32 instructions.
395 void VM_Version::determine_section_size() {
396
397 int unroll = 80;
398
399 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
400
401 // Allocate space for the code.
402 ResourceMark rm;
403 CodeBuffer cb("detect_section_size", code_size, 0);
404 MacroAssembler* a = new MacroAssembler(&cb);
405
406 uint32_t *code = (uint32_t *)a->pc();
407 // Emit code.
408 void (*test1)() = (void(*)())(void *)a->function_entry();
409
410 Label l1;
411
412 a->li(R4, 1);
413 a->sldi(R4, R4, 28);
414 a->b(l1);
415 a->align(CodeEntryAlignment);
416
417 a->bind(l1);
418
419 for (int i = 0; i < unroll; i++) {
420 // Schleife 1
421 // ------- sector 0 ------------
422 // ;; 0
423 a->nop(); // 1
424 a->fpnop0(); // 2
425 a->fpnop1(); // 3
426 a->addi(R4,R4, -1); // 4
427
428 // ;; 1
429 a->nop(); // 5
430 a->fmr(F6, F6); // 6
431 a->fmr(F7, F7); // 7
432 a->endgroup(); // 8
433 // ------- sector 8 ------------
434
435 // ;; 2
436 a->nop(); // 9
437 a->nop(); // 10
438 a->fmr(F8, F8); // 11
439 a->fmr(F9, F9); // 12
440
441 // ;; 3
442 a->nop(); // 13
443 a->fmr(F10, F10); // 14
444 a->fmr(F11, F11); // 15
445 a->endgroup(); // 16
446 // -------- sector 16 -------------
447
448 // ;; 4
449 a->nop(); // 17
450 a->nop(); // 18
451 a->fmr(F15, F15); // 19
452 a->fmr(F16, F16); // 20
453
454 // ;; 5
455 a->nop(); // 21
456 a->fmr(F17, F17); // 22
457 a->fmr(F18, F18); // 23
458 a->endgroup(); // 24
459 // ------- sector 24 ------------
460
461 // ;; 6
462 a->nop(); // 25
463 a->nop(); // 26
464 a->fmr(F19, F19); // 27
465 a->fmr(F20, F20); // 28
466
467 // ;; 7
468 a->nop(); // 29
469 a->fmr(F21, F21); // 30
470 a->fmr(F22, F22); // 31
471 a->brnop0(); // 32
472
473 // ------- sector 32 ------------
474 }
475
476 // ;; 8
477 a->cmpdi(CCR0, R4, unroll); // 33
478 a->bge(CCR0, l1); // 34
479 a->blr();
480
481 // Emit code.
482 void (*test2)() = (void(*)())(void *)a->function_entry();
483 // uint32_t *code = (uint32_t *)a->pc();
484
485 Label l2;
486
487 a->li(R4, 1);
488 a->sldi(R4, R4, 28);
489 a->b(l2);
490 a->align(CodeEntryAlignment);
491
492 a->bind(l2);
493
494 for (int i = 0; i < unroll; i++) {
495 // Schleife 2
496 // ------- sector 0 ------------
497 // ;; 0
498 a->brnop0(); // 1
499 a->nop(); // 2
500 //a->cmpdi(CCR0, R4, unroll);
501 a->fpnop0(); // 3
502 a->fpnop1(); // 4
503 a->addi(R4,R4, -1); // 5
504
505 // ;; 1
506
507 a->nop(); // 6
508 a->fmr(F6, F6); // 7
509 a->fmr(F7, F7); // 8
510 // ------- sector 8 ---------------
511
512 // ;; 2
513 a->endgroup(); // 9
514
515 // ;; 3
516 a->nop(); // 10
517 a->nop(); // 11
518 a->fmr(F8, F8); // 12
519
520 // ;; 4
521 a->fmr(F9, F9); // 13
522 a->nop(); // 14
523 a->fmr(F10, F10); // 15
524
525 // ;; 5
526 a->fmr(F11, F11); // 16
527 // -------- sector 16 -------------
528
529 // ;; 6
530 a->endgroup(); // 17
531
532 // ;; 7
533 a->nop(); // 18
534 a->nop(); // 19
535 a->fmr(F15, F15); // 20
536
537 // ;; 8
538 a->fmr(F16, F16); // 21
539 a->nop(); // 22
540 a->fmr(F17, F17); // 23
541
542 // ;; 9
543 a->fmr(F18, F18); // 24
544 // -------- sector 24 -------------
545
546 // ;; 10
547 a->endgroup(); // 25
548
549 // ;; 11
550 a->nop(); // 26
551 a->nop(); // 27
552 a->fmr(F19, F19); // 28
553
554 // ;; 12
555 a->fmr(F20, F20); // 29
556 a->nop(); // 30
557 a->fmr(F21, F21); // 31
558
559 // ;; 13
560 a->fmr(F22, F22); // 32
561 }
562
563 // -------- sector 32 -------------
564 // ;; 14
565 a->cmpdi(CCR0, R4, unroll); // 33
566 a->bge(CCR0, l2); // 34
567
568 a->blr();
569 uint32_t *code_end = (uint32_t *)a->pc();
570 a->flush();
571
572 double loop1_seconds,loop2_seconds, rel_diff;
573 uint64_t start1, stop1;
574
575 start1 = os::current_thread_cpu_time(false);
576 (*test1)();
577 stop1 = os::current_thread_cpu_time(false);
578 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
579
580
581 start1 = os::current_thread_cpu_time(false);
582 (*test2)();
583 stop1 = os::current_thread_cpu_time(false);
584
585 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
586
587 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
588
589 if (PrintAssembly) {
590 ttyLocker ttyl;
591 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
592 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
593 tty->print_cr("Time loop1 :%f", loop1_seconds);
594 tty->print_cr("Time loop2 :%f", loop2_seconds);
595 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
596
597 if (rel_diff > 12.0) {
598 tty->print_cr("Section Size 8 Instructions");
599 } else{
600 tty->print_cr("Section Size 32 Instructions or Power5");
601 }
602 }
603
604 #if 0 // TODO: PPC port
605 // Set sector size (if not set explicitly).
606 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
607 if (rel_diff > 12.0) {
608 PdScheduling::power6SectorSize = 0x20;
609 } else {
610 PdScheduling::power6SectorSize = 0x80;
611 }
612 } else if (Power6SectorSize128PPC64) {
613 PdScheduling::power6SectorSize = 0x80;
614 } else {
615 PdScheduling::power6SectorSize = 0x20;
616 }
617 #endif
618 if (UsePower6SchedulerPPC64) Unimplemented();
619 }
620 #endif // COMPILER2
621
622 void VM_Version::determine_features() {
623 #if defined(ABI_ELFv2)
624 // 1 InstWord per call for the blr instruction.
625 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
626 #else
627 // 7 InstWords for each call (function descriptor + blr instruction).
628 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
629 #endif
630 int features = 0;
631
632 // create test area
633 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
634 char test_area[BUFFER_SIZE];
635 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
636
637 // Allocate space for the code.
638 ResourceMark rm;
639 CodeBuffer cb("detect_cpu_features", code_size, 0);
640 MacroAssembler* a = new MacroAssembler(&cb);
641
642 // Must be set to true so we can generate the test code.
643 _features = VM_Version::all_features_m;
644
645 // Emit code.
646 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
647 uint32_t *code = (uint32_t *)a->pc();
648 // Don't use R0 in ldarx.
649 // Keep R3_ARG1 unmodified, it contains &field (see below).
650 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
651 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
652 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
653 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
654 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
655 a->cmpb(R7, R5, R6); // code[4] -> cmpb
656 a->popcntb(R7, R5); // code[5] -> popcntb
657 a->popcntw(R7, R5); // code[6] -> popcntw
658 a->fcfids(F3, F4); // code[7] -> fcfids
659 a->vand(VR0, VR0, VR0); // code[8] -> vand
660 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
661 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
662 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
663 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
664 a->mfdscr(R0); // code[12] -> mfdscr
665 a->lxvd2x(VSR0, R3_ARG1); // code[13] -> vsx
666 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[14] -> ldbrx
667 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> stdbrx
668 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[16] -> vshasig
669 // rtm is determined by OS
670 a->darn(R7); // code[17] -> darn
671 a->blr();
672
673 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
674 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
675 a->dcbz(R3_ARG1); // R3_ARG1 = addr
676 a->blr();
677
678 uint32_t *code_end = (uint32_t *)a->pc();
679 a->flush();
680 _features = VM_Version::unknown_m;
681
682 // Print the detection code.
683 if (PrintAssembly) {
684 ttyLocker ttyl;
685 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
686 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
687 }
688
689 // Measure cache line size.
690 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
691 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
692 int count = 0; // count zeroed bytes
693 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
694 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
695 _L1_data_cache_line_size = count;
696
697 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
698 VM_Version::_is_determine_features_test_running = true;
699 // We must align the first argument to 16 bytes because of the lqarx check.
700 (*test)(align_up((address)mid_of_test_area, 16), 0);
701 VM_Version::_is_determine_features_test_running = false;
702
703 // determine which instructions are legal.
704 int feature_cntr = 0;
705 if (code[feature_cntr++]) features |= fsqrt_m;
706 if (code[feature_cntr++]) features |= fsqrts_m;
707 if (code[feature_cntr++]) features |= isel_m;
708 if (code[feature_cntr++]) features |= lxarxeh_m;
709 if (code[feature_cntr++]) features |= cmpb_m;
710 if (code[feature_cntr++]) features |= popcntb_m;
711 if (code[feature_cntr++]) features |= popcntw_m;
712 if (code[feature_cntr++]) features |= fcfids_m;
713 if (code[feature_cntr++]) features |= vand_m;
714 if (code[feature_cntr++]) features |= lqarx_m;
715 if (code[feature_cntr++]) features |= vcipher_m;
716 if (code[feature_cntr++]) features |= vpmsumb_m;
717 if (code[feature_cntr++]) features |= mfdscr_m;
718 if (code[feature_cntr++]) features |= vsx_m;
719 if (code[feature_cntr++]) features |= ldbrx_m;
720 if (code[feature_cntr++]) features |= stdbrx_m;
721 if (code[feature_cntr++]) features |= vshasig_m;
722 // feature rtm_m is determined by OS
723 if (code[feature_cntr++]) features |= darn_m;
724
725 // Print the detection code.
726 if (PrintAssembly) {
727 ttyLocker ttyl;
728 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
729 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
730 }
731
732 _features = features;
733
734 #ifdef AIX
735 // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
736 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
737 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
738 // The Java property os.version, which is used in RTM tests to decide
739 // whether the feature is available, only knows major and minor versions.
740 // We don't want to change this property, as user code might depend on it.
741 // So the tests can not check on subversion 3.30, and we only enable RTM
742 // with AIX 7.2.
743 if (has_lqarx()) { // POWER8 or above
744 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
745 _features |= rtm_m;
746 }
747 }
748 #endif
749 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
750 unsigned long auxv = getauxval(AT_HWCAP2);
751
752 if (auxv & PPC_FEATURE2_HTM_NOSC) {
753 if (auxv & PPC_FEATURE2_HAS_HTM) {
754 // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
755 // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
756 // POWER9 DD2.1 NV has a few issues that need a couple of firmware
757 // and kernel workarounds, so there is a new mode only supported
758 // on non-virtualized P9 machines called HTM with no Suspend Mode).
759 // TM on POWER9 D2.2+ NV is not supported at all by Linux.
760 _features |= rtm_m;
761 }
762 }
763 #endif
764 }
765
766 // Power 8: Configure Data Stream Control Register.
767 void VM_Version::config_dscr() {
768 // 7 InstWords for each call (function descriptor + blr instruction).
769 const int code_size = (2+2*7)*BytesPerInstWord;
770
771 // Allocate space for the code.
772 ResourceMark rm;
773 CodeBuffer cb("config_dscr", code_size, 0);
774 MacroAssembler* a = new MacroAssembler(&cb);
775
776 // Emit code.
777 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
778 uint32_t *code = (uint32_t *)a->pc();
779 a->mfdscr(R3);
780 a->blr();
781
782 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
783 a->mtdscr(R3);
784 a->blr();
785
786 uint32_t *code_end = (uint32_t *)a->pc();
787 a->flush();
788
789 // Print the detection code.
790 if (PrintAssembly) {
791 ttyLocker ttyl;
792 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
793 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
794 }
795
796 // Apply the configuration if needed.
797 _dscr_val = (*get_dscr)();
798 if (Verbose) {
799 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
800 }
801 bool change_requested = false;
802 if (DSCR_PPC64 != (uintx)-1) {
803 _dscr_val = DSCR_PPC64;
804 change_requested = true;
805 }
806 if (DSCR_DPFD_PPC64 <= 7) {
807 uint64_t mask = 0x7;
808 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
809 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
810 change_requested = true;
811 }
812 }
813 if (DSCR_URG_PPC64 <= 7) {
814 uint64_t mask = 0x7 << 6;
815 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
816 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
817 change_requested = true;
818 }
819 }
820 if (change_requested) {
821 (*set_dscr)(_dscr_val);
822 if (Verbose) {
823 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
824 }
825 }
826 }
827
828 static uint64_t saved_features = 0;
829
830 void VM_Version::allow_all() {
831 saved_features = _features;
832 _features = all_features_m;
833 }
834
835 void VM_Version::revert() {
836 _features = saved_features;
837 }