*** old/src/cpu/sparc/vm/nativeInst_sparc.cpp	Mon Jun  2 11:28:32 2014
--- new/src/cpu/sparc/vm/nativeInst_sparc.cpp	Mon Jun  2 11:28:32 2014

*** 688,840 ****
--- 688,697 ----
  #endif // ASSERT
  }
  
  // End code for unit testing implementation of NativeMovRegMem class
  
  //--------------------------------------------------------------------------------
  
  
  void NativeMovRegMemPatching::copy_instruction_to(address new_instruction_address) {
    Untested("copy_instruction_to");
    int instruction_size = next_instruction_address() - instruction_address();
    for (int i = 0; i < instruction_size; i += wordSize) {
      *(long*)(new_instruction_address + i) = *(long*)(address(this) + i);
    }
  }
  
  
  void NativeMovRegMemPatching::verify() {
    NativeInstruction::verify();
    // make sure code pattern is actually a "ld" or "st" of some sort.
    int i0 = long_at(0);
    int op3 = inv_op3(i0);
  
    assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
  
    if (!(is_op(i0, Assembler::ldst_op) &&
          inv_immed(i0) &&
          0 != (op3 < op3_ldst_int_limit
           ? (1 <<  op3                      ) & (op3_mask_ld  | op3_mask_st)
           : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) {
      int i1 = long_at(ldst_offset);
      Register rd = inv_rd(i0);
  
      op3 = inv_op3(i1);
      if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
           0 != (op3 < op3_ldst_int_limit
                ? (1 <<  op3                      ) & (op3_mask_ld  | op3_mask_st)
                : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
        fatal("not a ld* or st* op");
      }
    }
  }
  
  
  void NativeMovRegMemPatching::print() {
    if (is_immediate()) {
      tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %d]", p2i(instruction_address()), offset());
    } else {
      tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", p2i(instruction_address()));
    }
  }
  
  
  // Code for unit testing implementation of NativeMovRegMemPatching class
  void NativeMovRegMemPatching::test() {
  #ifdef ASSERT
    ResourceMark rm;
    CodeBuffer cb("test", 1000, 1000);
    MacroAssembler* a = new MacroAssembler(&cb);
    NativeMovRegMemPatching* nm;
    uint idx = 0;
    uint idx1;
    int offsets[] = {
      0x0,
      0xffffffff,
      0x7fffffff,
      0x80000000,
      4096,
      4097,
      0x20,
      0x4000,
    };
  
    VM_Version::allow_all();
  
    AddressLiteral al(0xffffffff, relocInfo::external_word_type);
    a->ldsw( G5, al.low10(), G4); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->ldsw( G5, I3, G4 ); idx++;
    a->ldsb( G5, al.low10(), G4); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->ldsb( G5, I3, G4 ); idx++;
    a->ldsh( G5, al.low10(), G4); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->ldsh( G5, I3, G4 ); idx++;
    a->lduw( G5, al.low10(), G4); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->lduw( G5, I3, G4 ); idx++;
    a->ldub( G5, al.low10(), G4); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->ldub( G5, I3, G4 ); idx++;
    a->lduh( G5, al.low10(), G4); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->lduh( G5, I3, G4 ); idx++;
    a->ldx(  G5, al.low10(), G4); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->ldx(  G5, I3, G4 ); idx++;
    a->ldd(  G5, al.low10(), G4); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->ldd(  G5, I3, G4 ); idx++;
    a->ldf(  FloatRegisterImpl::D, O2, -1, F14 ); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->ldf(  FloatRegisterImpl::S, O0, I3, F15 ); idx++;
  
    a->stw( G5, G4, al.low10()); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->stw( G5, G4, I3 ); idx++;
    a->stb( G5, G4, al.low10()); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->stb( G5, G4, I3 ); idx++;
    a->sth( G5, G4, al.low10()); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->sth( G5, G4, I3 ); idx++;
    a->stx( G5, G4, al.low10()); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->stx( G5, G4, I3 ); idx++;
    a->std( G5, G4, al.low10()); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->std( G5, G4, I3 ); idx++;
    a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
    a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3);
    a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
  
    nm = nativeMovRegMemPatching_at( cb.insts_begin() );
    nm->print();
    nm->set_offset( low10(0) );
    nm->print();
    nm->add_offset_in_bytes( low10(0xbb) * wordSize );
    nm->print();
  
    while (--idx) {
      nm = nativeMovRegMemPatching_at( nm->next_instruction_address() );
      nm->print();
      for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
        nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
        assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
               "check unit test");
        nm->print();
      }
      nm->add_offset_in_bytes( low10(0xbb) * wordSize );
      nm->print();
    }
  
    VM_Version::revert();
  #endif // ASSERT
  }
  // End code for unit testing implementation of NativeMovRegMemPatching class
  
  
  //--------------------------------------------------------------------------------
  
  
  void NativeJump::verify() {