1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/klass.inline.hpp"
38 #include "prims/methodHandles.hpp"
39 #include "runtime/biasedLocking.hpp"
40 #include "runtime/flags/flagSetting.hpp"
41 #include "runtime/interfaceSupport.inline.hpp"
42 #include "runtime/objectMonitor.hpp"
43 #include "runtime/os.hpp"
44 #include "runtime/safepoint.hpp"
45 #include "runtime/safepointMechanism.hpp"
46 #include "runtime/sharedRuntime.hpp"
47 #include "runtime/stubRoutines.hpp"
48 #include "runtime/thread.hpp"
49 #include "utilities/macros.hpp"
50 #include "crc32c.h"
51 #ifdef COMPILER2
52 #include "opto/intrinsicnode.hpp"
53 #endif
54
55 #ifdef PRODUCT
56 #define BLOCK_COMMENT(str) /* nothing */
57 #define STOP(error) stop(error)
58 #else
59 #define BLOCK_COMMENT(str) block_comment(str)
60 #define STOP(error) block_comment(error); stop(error)
61 #endif
62
63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
64
65 #ifdef ASSERT
66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
67 #endif
68
69 static Assembler::Condition reverse[] = {
70 Assembler::noOverflow /* overflow = 0x0 */ ,
71 Assembler::overflow /* noOverflow = 0x1 */ ,
72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
76 Assembler::above /* belowEqual = 0x6 */ ,
77 Assembler::belowEqual /* above = 0x7 */ ,
78 Assembler::positive /* negative = 0x8 */ ,
79 Assembler::negative /* positive = 0x9 */ ,
80 Assembler::noParity /* parity = 0xa */ ,
81 Assembler::parity /* noParity = 0xb */ ,
82 Assembler::greaterEqual /* less = 0xc */ ,
83 Assembler::less /* greaterEqual = 0xd */ ,
84 Assembler::greater /* lessEqual = 0xe */ ,
85 Assembler::lessEqual /* greater = 0xf, */
86
87 };
88
89
90 // Implementation of MacroAssembler
91
92 // First all the versions that have distinct versions depending on 32/64 bit
93 // Unless the difference is trivial (1 line or so).
94
95 #ifndef _LP64
96
97 // 32bit versions
98
99 Address MacroAssembler::as_Address(AddressLiteral adr) {
100 return Address(adr.target(), adr.rspec());
101 }
102
103 Address MacroAssembler::as_Address(ArrayAddress adr) {
104 return Address::make_array(adr);
105 }
106
107 void MacroAssembler::call_VM_leaf_base(address entry_point,
108 int number_of_arguments) {
109 call(RuntimeAddress(entry_point));
110 increment(rsp, number_of_arguments * wordSize);
111 }
112
113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
130 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
131 bs->obj_equals(this, src1, obj);
132 }
133
134 void MacroAssembler::cmpoop(Register src1, jobject obj) {
135 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
136 bs->obj_equals(this, src1, obj);
137 }
138
139 void MacroAssembler::extend_sign(Register hi, Register lo) {
140 // According to Intel Doc. AP-526, "Integer Divide", p.18.
141 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
142 cdql();
143 } else {
144 movl(hi, lo);
145 sarl(hi, 31);
146 }
147 }
148
149 void MacroAssembler::jC2(Register tmp, Label& L) {
150 // set parity bit if FPU flag C2 is set (via rax)
151 save_rax(tmp);
152 fwait(); fnstsw_ax();
153 sahf();
154 restore_rax(tmp);
155 // branch
156 jcc(Assembler::parity, L);
157 }
158
159 void MacroAssembler::jnC2(Register tmp, Label& L) {
160 // set parity bit if FPU flag C2 is set (via rax)
161 save_rax(tmp);
162 fwait(); fnstsw_ax();
163 sahf();
164 restore_rax(tmp);
165 // branch
166 jcc(Assembler::noParity, L);
167 }
168
169 // 32bit can do a case table jump in one instruction but we no longer allow the base
170 // to be installed in the Address class
171 void MacroAssembler::jump(ArrayAddress entry) {
172 jmp(as_Address(entry));
173 }
174
175 // Note: y_lo will be destroyed
176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
177 // Long compare for Java (semantics as described in JVM spec.)
178 Label high, low, done;
179
180 cmpl(x_hi, y_hi);
181 jcc(Assembler::less, low);
182 jcc(Assembler::greater, high);
183 // x_hi is the return register
184 xorl(x_hi, x_hi);
185 cmpl(x_lo, y_lo);
186 jcc(Assembler::below, low);
187 jcc(Assembler::equal, done);
188
189 bind(high);
190 xorl(x_hi, x_hi);
191 increment(x_hi);
192 jmp(done);
193
194 bind(low);
195 xorl(x_hi, x_hi);
196 decrementl(x_hi);
197
198 bind(done);
199 }
200
201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
202 mov_literal32(dst, (int32_t)src.target(), src.rspec());
203 }
204
205 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj) {
309 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
310 }
311
312 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
313 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
314 }
315
316 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
317 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
318 }
319
320 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
321 // scratch register is not used,
322 // it is defined to match parameters of 64-bit version of this method.
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
331 movl(as_Address(dst), src);
332 }
333
334 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
335 movl(dst, as_Address(src));
336 }
337
338 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
339 void MacroAssembler::movptr(Address dst, intptr_t src) {
340 movl(dst, src);
341 }
342
343
344 void MacroAssembler::pop_callee_saved_registers() {
345 pop(rcx);
346 pop(rdx);
347 pop(rdi);
348 pop(rsi);
349 }
350
351 void MacroAssembler::pop_fTOS() {
352 fld_d(Address(rsp, 0));
353 addl(rsp, 2 * wordSize);
354 }
355
356 void MacroAssembler::push_callee_saved_registers() {
357 push(rsi);
358 push(rdi);
359 push(rdx);
360 push(rcx);
361 }
362
363 void MacroAssembler::push_fTOS() {
364 subl(rsp, 2 * wordSize);
365 fstp_d(Address(rsp, 0));
366 }
367
368
369 void MacroAssembler::pushoop(jobject obj) {
370 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
371 }
372
373 void MacroAssembler::pushklass(Metadata* obj) {
374 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
375 }
376
377 void MacroAssembler::pushptr(AddressLiteral src) {
378 if (src.is_lval()) {
379 push_literal32((int32_t)src.target(), src.rspec());
380 } else {
381 pushl(as_Address(src));
382 }
383 }
384
385 void MacroAssembler::set_word_if_not_zero(Register dst) {
386 xorl(dst, dst);
387 set_byte_if_not_zero(dst);
388 }
389
390 static void pass_arg0(MacroAssembler* masm, Register arg) {
391 masm->push(arg);
392 }
393
394 static void pass_arg1(MacroAssembler* masm, Register arg) {
395 masm->push(arg);
396 }
397
398 static void pass_arg2(MacroAssembler* masm, Register arg) {
399 masm->push(arg);
400 }
401
402 static void pass_arg3(MacroAssembler* masm, Register arg) {
403 masm->push(arg);
404 }
405
406 #ifndef PRODUCT
407 extern "C" void findpc(intptr_t x);
408 #endif
409
410 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
411 // In order to get locks to work, we need to fake a in_VM state
412 JavaThread* thread = JavaThread::current();
413 JavaThreadState saved_state = thread->thread_state();
414 thread->set_thread_state(_thread_in_vm);
415 if (ShowMessageBoxOnError) {
416 JavaThread* thread = JavaThread::current();
417 JavaThreadState saved_state = thread->thread_state();
418 thread->set_thread_state(_thread_in_vm);
419 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
420 ttyLocker ttyl;
421 BytecodeCounter::print();
422 }
423 // To see where a verify_oop failed, get $ebx+40/X for this frame.
424 // This is the value of eip which points to where verify_oop will return.
425 if (os::message_box(msg, "Execution stopped, print registers?")) {
426 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
427 BREAKPOINT;
428 }
429 } else {
430 ttyLocker ttyl;
431 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
432 }
433 // Don't assert holding the ttyLock
434 assert(false, "DEBUG MESSAGE: %s", msg);
435 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
436 }
437
438 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
439 ttyLocker ttyl;
440 FlagSetting fs(Debugging, true);
441 tty->print_cr("eip = 0x%08x", eip);
442 #ifndef PRODUCT
443 if ((WizardMode || Verbose) && PrintMiscellaneous) {
444 tty->cr();
445 findpc(eip);
446 tty->cr();
447 }
448 #endif
449 #define PRINT_REG(rax) \
450 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
451 PRINT_REG(rax);
452 PRINT_REG(rbx);
453 PRINT_REG(rcx);
454 PRINT_REG(rdx);
455 PRINT_REG(rdi);
456 PRINT_REG(rsi);
457 PRINT_REG(rbp);
458 PRINT_REG(rsp);
459 #undef PRINT_REG
460 // Print some words near top of staack.
461 int* dump_sp = (int*) rsp;
462 for (int col1 = 0; col1 < 8; col1++) {
463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
464 os::print_location(tty, *dump_sp++);
465 }
466 for (int row = 0; row < 16; row++) {
467 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
468 for (int col = 0; col < 8; col++) {
469 tty->print(" 0x%08x", *dump_sp++);
470 }
471 tty->cr();
472 }
473 // Print some instructions around pc:
474 Disassembler::decode((address)eip-64, (address)eip);
475 tty->print_cr("--------");
476 Disassembler::decode((address)eip, (address)eip+32);
477 }
478
479 void MacroAssembler::stop(const char* msg) {
480 ExternalAddress message((address)msg);
481 // push address of message
482 pushptr(message.addr());
483 { Label L; call(L, relocInfo::none); bind(L); } // push eip
484 pusha(); // push registers
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
486 hlt();
487 }
488
489 void MacroAssembler::warn(const char* msg) {
490 push_CPU_state();
491
492 ExternalAddress message((address) msg);
493 // push address of message
494 pushptr(message.addr());
495
496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
497 addl(rsp, wordSize); // discard argument
498 pop_CPU_state();
499 }
500
501 void MacroAssembler::print_state() {
502 { Label L; call(L, relocInfo::none); bind(L); } // push eip
503 pusha(); // push registers
504
505 push_CPU_state();
506 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
507 pop_CPU_state();
508
509 popa();
510 addl(rsp, wordSize);
511 }
512
513 #else // _LP64
514
515 // 64 bit versions
516
517 Address MacroAssembler::as_Address(AddressLiteral adr) {
518 // amd64 always does this as a pc-rel
519 // we can be absolute or disp based on the instruction type
520 // jmp/call are displacements others are absolute
521 assert(!adr.is_lval(), "must be rval");
522 assert(reachable(adr), "must be");
523 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
524
525 }
526
527 Address MacroAssembler::as_Address(ArrayAddress adr) {
528 AddressLiteral base = adr.base();
529 lea(rscratch1, base);
530 Address index = adr.index();
531 assert(index._disp == 0, "must not have disp"); // maybe it can?
532 Address array(rscratch1, index._index, index._scale, index._disp);
533 return array;
534 }
535
536 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
537 Label L, E;
538
539 #ifdef _WIN64
540 // Windows always allocates space for it's register args
541 assert(num_args <= 4, "only register arguments supported");
542 subq(rsp, frame::arg_reg_save_area_bytes);
543 #endif
544
545 // Align stack if necessary
546 testl(rsp, 15);
547 jcc(Assembler::zero, L);
548
549 subq(rsp, 8);
550 {
551 call(RuntimeAddress(entry_point));
552 }
553 addq(rsp, 8);
554 jmp(E);
555
556 bind(L);
557 {
558 call(RuntimeAddress(entry_point));
559 }
560
561 bind(E);
562
563 #ifdef _WIN64
564 // restore stack pointer
565 addq(rsp, frame::arg_reg_save_area_bytes);
566 #endif
567
568 }
569
570 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
571 assert(!src2.is_lval(), "should use cmpptr");
572
573 if (reachable(src2)) {
574 cmpq(src1, as_Address(src2));
575 } else {
576 lea(rscratch1, src2);
577 Assembler::cmpq(src1, Address(rscratch1, 0));
578 }
579 }
580
581 int MacroAssembler::corrected_idivq(Register reg) {
582 // Full implementation of Java ldiv and lrem; checks for special
583 // case as described in JVM spec., p.243 & p.271. The function
584 // returns the (pc) offset of the idivl instruction - may be needed
585 // for implicit exceptions.
586 //
587 // normal case special case
588 //
589 // input : rax: dividend min_long
590 // reg: divisor (may not be eax/edx) -1
591 //
592 // output: rax: quotient (= rax idiv reg) min_long
593 // rdx: remainder (= rax irem reg) 0
594 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
595 static const int64_t min_long = 0x8000000000000000;
596 Label normal_case, special_case;
597
598 // check for special case
599 cmp64(rax, ExternalAddress((address) &min_long));
600 jcc(Assembler::notEqual, normal_case);
601 xorl(rdx, rdx); // prepare rdx for possible special case (where
602 // remainder = 0)
603 cmpq(reg, -1);
604 jcc(Assembler::equal, special_case);
605
606 // handle normal case
607 bind(normal_case);
608 cdqq();
609 int idivq_offset = offset();
610 idivq(reg);
611
612 // normal and special case exit
613 bind(special_case);
614
615 return idivq_offset;
616 }
617
618 void MacroAssembler::decrementq(Register reg, int value) {
619 if (value == min_jint) { subq(reg, value); return; }
620 if (value < 0) { incrementq(reg, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { decq(reg) ; return; }
623 /* else */ { subq(reg, value) ; return; }
624 }
625
626 void MacroAssembler::decrementq(Address dst, int value) {
627 if (value == min_jint) { subq(dst, value); return; }
628 if (value < 0) { incrementq(dst, -value); return; }
629 if (value == 0) { ; return; }
630 if (value == 1 && UseIncDec) { decq(dst) ; return; }
631 /* else */ { subq(dst, value) ; return; }
632 }
633
634 void MacroAssembler::incrementq(AddressLiteral dst) {
635 if (reachable(dst)) {
636 incrementq(as_Address(dst));
637 } else {
638 lea(rscratch1, dst);
639 incrementq(Address(rscratch1, 0));
640 }
641 }
642
643 void MacroAssembler::incrementq(Register reg, int value) {
644 if (value == min_jint) { addq(reg, value); return; }
645 if (value < 0) { decrementq(reg, -value); return; }
646 if (value == 0) { ; return; }
647 if (value == 1 && UseIncDec) { incq(reg) ; return; }
648 /* else */ { addq(reg, value) ; return; }
649 }
650
651 void MacroAssembler::incrementq(Address dst, int value) {
652 if (value == min_jint) { addq(dst, value); return; }
653 if (value < 0) { decrementq(dst, -value); return; }
654 if (value == 0) { ; return; }
655 if (value == 1 && UseIncDec) { incq(dst) ; return; }
656 /* else */ { addq(dst, value) ; return; }
657 }
658
659 // 32bit can do a case table jump in one instruction but we no longer allow the base
660 // to be installed in the Address class
661 void MacroAssembler::jump(ArrayAddress entry) {
662 lea(rscratch1, entry.base());
663 Address dispatch = entry.index();
664 assert(dispatch._base == noreg, "must be");
665 dispatch._base = rscratch1;
666 jmp(dispatch);
667 }
668
669 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
670 ShouldNotReachHere(); // 64bit doesn't use two regs
671 cmpq(x_lo, y_lo);
672 }
673
674 void MacroAssembler::lea(Register dst, AddressLiteral src) {
675 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
676 }
677
678 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
679 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
680 movptr(dst, rscratch1);
681 }
682
683 void MacroAssembler::leave() {
684 // %%% is this really better? Why not on 32bit too?
685 emit_int8((unsigned char)0xC9); // LEAVE
686 }
687
688 void MacroAssembler::lneg(Register hi, Register lo) {
689 ShouldNotReachHere(); // 64bit doesn't use two regs
690 negq(lo);
691 }
692
693 void MacroAssembler::movoop(Register dst, jobject obj) {
694 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
695 }
696
697 void MacroAssembler::movoop(Address dst, jobject obj) {
698 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
699 movq(dst, rscratch1);
700 }
701
702 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
703 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
704 }
705
706 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
707 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
708 movq(dst, rscratch1);
709 }
710
711 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
712 if (src.is_lval()) {
713 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
714 } else {
715 if (reachable(src)) {
716 movq(dst, as_Address(src));
717 } else {
718 lea(scratch, src);
719 movq(dst, Address(scratch, 0));
720 }
721 }
722 }
723
724 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
725 movq(as_Address(dst), src);
726 }
727
728 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
729 movq(dst, as_Address(src));
730 }
731
732 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
733 void MacroAssembler::movptr(Address dst, intptr_t src) {
734 mov64(rscratch1, src);
735 movq(dst, rscratch1);
736 }
737
738 // These are mostly for initializing NULL
739 void MacroAssembler::movptr(Address dst, int32_t src) {
740 movslq(dst, src);
741 }
742
743 void MacroAssembler::movptr(Register dst, int32_t src) {
744 mov64(dst, (intptr_t)src);
745 }
746
747 void MacroAssembler::pushoop(jobject obj) {
748 movoop(rscratch1, obj);
749 push(rscratch1);
750 }
751
752 void MacroAssembler::pushklass(Metadata* obj) {
753 mov_metadata(rscratch1, obj);
754 push(rscratch1);
755 }
756
757 void MacroAssembler::pushptr(AddressLiteral src) {
758 lea(rscratch1, src);
759 if (src.is_lval()) {
760 push(rscratch1);
761 } else {
762 pushq(Address(rscratch1, 0));
763 }
764 }
765
766 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
767 // we must set sp to zero to clear frame
768 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
769 // must clear fp, so that compiled frames are not confused; it is
770 // possible that we need it only for debugging
771 if (clear_fp) {
772 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
773 }
774
775 // Always clear the pc because it could have been set by make_walkable()
776 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
777 vzeroupper();
778 }
779
780 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
781 Register last_java_fp,
782 address last_java_pc) {
783 vzeroupper();
784 // determine last_java_sp register
785 if (!last_java_sp->is_valid()) {
786 last_java_sp = rsp;
787 }
788
789 // last_java_fp is optional
790 if (last_java_fp->is_valid()) {
791 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
792 last_java_fp);
793 }
794
795 // last_java_pc is optional
796 if (last_java_pc != NULL) {
797 Address java_pc(r15_thread,
798 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
799 lea(rscratch1, InternalAddress(last_java_pc));
800 movptr(java_pc, rscratch1);
801 }
802
803 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
804 }
805
806 static void pass_arg0(MacroAssembler* masm, Register arg) {
807 if (c_rarg0 != arg ) {
808 masm->mov(c_rarg0, arg);
809 }
810 }
811
812 static void pass_arg1(MacroAssembler* masm, Register arg) {
813 if (c_rarg1 != arg ) {
814 masm->mov(c_rarg1, arg);
815 }
816 }
817
818 static void pass_arg2(MacroAssembler* masm, Register arg) {
819 if (c_rarg2 != arg ) {
820 masm->mov(c_rarg2, arg);
821 }
822 }
823
824 static void pass_arg3(MacroAssembler* masm, Register arg) {
825 if (c_rarg3 != arg ) {
826 masm->mov(c_rarg3, arg);
827 }
828 }
829
830 void MacroAssembler::stop(const char* msg) {
831 address rip = pc();
832 pusha(); // get regs on stack
833 lea(c_rarg0, ExternalAddress((address) msg));
834 lea(c_rarg1, InternalAddress(rip));
835 movq(c_rarg2, rsp); // pass pointer to regs array
836 andq(rsp, -16); // align stack as required by ABI
837 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
838 hlt();
839 }
840
841 void MacroAssembler::warn(const char* msg) {
842 push(rbp);
843 movq(rbp, rsp);
844 andq(rsp, -16); // align stack as required by push_CPU_state and call
845 push_CPU_state(); // keeps alignment at 16 bytes
846 lea(c_rarg0, ExternalAddress((address) msg));
847 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
848 call(rax);
849 pop_CPU_state();
850 mov(rsp, rbp);
851 pop(rbp);
852 }
853
854 void MacroAssembler::print_state() {
855 address rip = pc();
856 pusha(); // get regs on stack
857 push(rbp);
858 movq(rbp, rsp);
859 andq(rsp, -16); // align stack as required by push_CPU_state and call
860 push_CPU_state(); // keeps alignment at 16 bytes
861
862 lea(c_rarg0, InternalAddress(rip));
863 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
864 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
865
866 pop_CPU_state();
867 mov(rsp, rbp);
868 pop(rbp);
869 popa();
870 }
871
872 #ifndef PRODUCT
873 extern "C" void findpc(intptr_t x);
874 #endif
875
876 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
877 // In order to get locks to work, we need to fake a in_VM state
878 if (ShowMessageBoxOnError) {
879 JavaThread* thread = JavaThread::current();
880 JavaThreadState saved_state = thread->thread_state();
881 thread->set_thread_state(_thread_in_vm);
882 #ifndef PRODUCT
883 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
884 ttyLocker ttyl;
885 BytecodeCounter::print();
886 }
887 #endif
888 // To see where a verify_oop failed, get $ebx+40/X for this frame.
889 // XXX correct this offset for amd64
890 // This is the value of eip which points to where verify_oop will return.
891 if (os::message_box(msg, "Execution stopped, print registers?")) {
892 print_state64(pc, regs);
893 BREAKPOINT;
894 assert(false, "start up GDB");
895 }
896 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
897 } else {
898 ttyLocker ttyl;
899 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
900 msg);
901 assert(false, "DEBUG MESSAGE: %s", msg);
902 }
903 }
904
905 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
906 ttyLocker ttyl;
907 FlagSetting fs(Debugging, true);
908 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
909 #ifndef PRODUCT
910 tty->cr();
911 findpc(pc);
912 tty->cr();
913 #endif
914 #define PRINT_REG(rax, value) \
915 { tty->print("%s = ", #rax); os::print_location(tty, value); }
916 PRINT_REG(rax, regs[15]);
917 PRINT_REG(rbx, regs[12]);
918 PRINT_REG(rcx, regs[14]);
919 PRINT_REG(rdx, regs[13]);
920 PRINT_REG(rdi, regs[8]);
921 PRINT_REG(rsi, regs[9]);
922 PRINT_REG(rbp, regs[10]);
923 PRINT_REG(rsp, regs[11]);
924 PRINT_REG(r8 , regs[7]);
925 PRINT_REG(r9 , regs[6]);
926 PRINT_REG(r10, regs[5]);
927 PRINT_REG(r11, regs[4]);
928 PRINT_REG(r12, regs[3]);
929 PRINT_REG(r13, regs[2]);
930 PRINT_REG(r14, regs[1]);
931 PRINT_REG(r15, regs[0]);
932 #undef PRINT_REG
933 // Print some words near top of staack.
934 int64_t* rsp = (int64_t*) regs[11];
935 int64_t* dump_sp = rsp;
936 for (int col1 = 0; col1 < 8; col1++) {
937 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
938 os::print_location(tty, *dump_sp++);
939 }
940 for (int row = 0; row < 25; row++) {
941 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
942 for (int col = 0; col < 4; col++) {
943 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
944 }
945 tty->cr();
946 }
947 // Print some instructions around pc:
948 Disassembler::decode((address)pc-64, (address)pc);
949 tty->print_cr("--------");
950 Disassembler::decode((address)pc, (address)pc+32);
951 }
952
953 #endif // _LP64
954
955 // Now versions that are common to 32/64 bit
956
957 void MacroAssembler::addptr(Register dst, int32_t imm32) {
958 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
959 }
960
961 void MacroAssembler::addptr(Register dst, Register src) {
962 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
963 }
964
965 void MacroAssembler::addptr(Address dst, Register src) {
966 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
967 }
968
969 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
970 if (reachable(src)) {
971 Assembler::addsd(dst, as_Address(src));
972 } else {
973 lea(rscratch1, src);
974 Assembler::addsd(dst, Address(rscratch1, 0));
975 }
976 }
977
978 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
979 if (reachable(src)) {
980 addss(dst, as_Address(src));
981 } else {
982 lea(rscratch1, src);
983 addss(dst, Address(rscratch1, 0));
984 }
985 }
986
987 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
988 if (reachable(src)) {
989 Assembler::addpd(dst, as_Address(src));
990 } else {
991 lea(rscratch1, src);
992 Assembler::addpd(dst, Address(rscratch1, 0));
993 }
994 }
995
996 void MacroAssembler::align(int modulus) {
997 align(modulus, offset());
998 }
999
1000 void MacroAssembler::align(int modulus, int target) {
1001 if (target % modulus != 0) {
1002 nop(modulus - (target % modulus));
1003 }
1004 }
1005
1006 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
1007 // Used in sign-masking with aligned address.
1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009 if (reachable(src)) {
1010 Assembler::andpd(dst, as_Address(src));
1011 } else {
1012 lea(rscratch1, src);
1013 Assembler::andpd(dst, Address(rscratch1, 0));
1014 }
1015 }
1016
1017 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1018 // Used in sign-masking with aligned address.
1019 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1020 if (reachable(src)) {
1021 Assembler::andps(dst, as_Address(src));
1022 } else {
1023 lea(rscratch1, src);
1024 Assembler::andps(dst, Address(rscratch1, 0));
1025 }
1026 }
1027
1028 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1029 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1030 }
1031
1032 void MacroAssembler::atomic_incl(Address counter_addr) {
1033 if (os::is_MP())
1034 lock();
1035 incrementl(counter_addr);
1036 }
1037
1038 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1039 if (reachable(counter_addr)) {
1040 atomic_incl(as_Address(counter_addr));
1041 } else {
1042 lea(scr, counter_addr);
1043 atomic_incl(Address(scr, 0));
1044 }
1045 }
1046
1047 #ifdef _LP64
1048 void MacroAssembler::atomic_incq(Address counter_addr) {
1049 if (os::is_MP())
1050 lock();
1051 incrementq(counter_addr);
1052 }
1053
1054 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1055 if (reachable(counter_addr)) {
1056 atomic_incq(as_Address(counter_addr));
1057 } else {
1058 lea(scr, counter_addr);
1059 atomic_incq(Address(scr, 0));
1060 }
1061 }
1062 #endif
1063
1064 // Writes to stack successive pages until offset reached to check for
1065 // stack overflow + shadow pages. This clobbers tmp.
1066 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1067 movptr(tmp, rsp);
1068 // Bang stack for total size given plus shadow page size.
1069 // Bang one page at a time because large size can bang beyond yellow and
1070 // red zones.
1071 Label loop;
1072 bind(loop);
1073 movl(Address(tmp, (-os::vm_page_size())), size );
1074 subptr(tmp, os::vm_page_size());
1075 subl(size, os::vm_page_size());
1076 jcc(Assembler::greater, loop);
1077
1078 // Bang down shadow pages too.
1079 // At this point, (tmp-0) is the last address touched, so don't
1080 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1081 // was post-decremented.) Skip this address by starting at i=1, and
1082 // touch a few more pages below. N.B. It is important to touch all
1083 // the way down including all pages in the shadow zone.
1084 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1085 // this could be any sized move but this is can be a debugging crumb
1086 // so the bigger the better.
1087 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1088 }
1089 }
1090
1091 void MacroAssembler::reserved_stack_check() {
1092 // testing if reserved zone needs to be enabled
1093 Label no_reserved_zone_enabling;
1094 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1095 NOT_LP64(get_thread(rsi);)
1096
1097 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1098 jcc(Assembler::below, no_reserved_zone_enabling);
1099
1100 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1101 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1102 should_not_reach_here();
1103
1104 bind(no_reserved_zone_enabling);
1105 }
1106
1107 int MacroAssembler::biased_locking_enter(Register lock_reg,
1108 Register obj_reg,
1109 Register swap_reg,
1110 Register tmp_reg,
1111 bool swap_reg_contains_mark,
1112 Label& done,
1113 Label* slow_case,
1114 BiasedLockingCounters* counters) {
1115 assert(UseBiasedLocking, "why call this otherwise?");
1116 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1117 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1118 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1119 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1120 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1121 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1122
1123 if (PrintBiasedLockingStatistics && counters == NULL) {
1124 counters = BiasedLocking::counters();
1125 }
1126 // Biased locking
1127 // See whether the lock is currently biased toward our thread and
1128 // whether the epoch is still valid
1129 // Note that the runtime guarantees sufficient alignment of JavaThread
1130 // pointers to allow age to be placed into low bits
1131 // First check to see whether biasing is even enabled for this object
1132 Label cas_label;
1133 int null_check_offset = -1;
1134 if (!swap_reg_contains_mark) {
1135 null_check_offset = offset();
1136 movptr(swap_reg, mark_addr);
1137 }
1138 movptr(tmp_reg, swap_reg);
1139 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1140 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1141 jcc(Assembler::notEqual, cas_label);
1142 // The bias pattern is present in the object's header. Need to check
1143 // whether the bias owner and the epoch are both still current.
1144 #ifndef _LP64
1145 // Note that because there is no current thread register on x86_32 we
1146 // need to store off the mark word we read out of the object to
1147 // avoid reloading it and needing to recheck invariants below. This
1148 // store is unfortunate but it makes the overall code shorter and
1149 // simpler.
1150 movptr(saved_mark_addr, swap_reg);
1151 #endif
1152 if (swap_reg_contains_mark) {
1153 null_check_offset = offset();
1154 }
1155 load_prototype_header(tmp_reg, obj_reg);
1156 #ifdef _LP64
1157 orptr(tmp_reg, r15_thread);
1158 xorptr(tmp_reg, swap_reg);
1159 Register header_reg = tmp_reg;
1160 #else
1161 xorptr(tmp_reg, swap_reg);
1162 get_thread(swap_reg);
1163 xorptr(swap_reg, tmp_reg);
1164 Register header_reg = swap_reg;
1165 #endif
1166 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1167 if (counters != NULL) {
1168 cond_inc32(Assembler::zero,
1169 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1170 }
1171 jcc(Assembler::equal, done);
1172
1173 Label try_revoke_bias;
1174 Label try_rebias;
1175
1176 // At this point we know that the header has the bias pattern and
1177 // that we are not the bias owner in the current epoch. We need to
1178 // figure out more details about the state of the header in order to
1179 // know what operations can be legally performed on the object's
1180 // header.
1181
1182 // If the low three bits in the xor result aren't clear, that means
1183 // the prototype header is no longer biased and we have to revoke
1184 // the bias on this object.
1185 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1186 jccb(Assembler::notZero, try_revoke_bias);
1187
1188 // Biasing is still enabled for this data type. See whether the
1189 // epoch of the current bias is still valid, meaning that the epoch
1190 // bits of the mark word are equal to the epoch bits of the
1191 // prototype header. (Note that the prototype header's epoch bits
1192 // only change at a safepoint.) If not, attempt to rebias the object
1193 // toward the current thread. Note that we must be absolutely sure
1194 // that the current epoch is invalid in order to do this because
1195 // otherwise the manipulations it performs on the mark word are
1196 // illegal.
1197 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1198 jccb(Assembler::notZero, try_rebias);
1199
1200 // The epoch of the current bias is still valid but we know nothing
1201 // about the owner; it might be set or it might be clear. Try to
1202 // acquire the bias of the object using an atomic operation. If this
1203 // fails we will go in to the runtime to revoke the object's bias.
1204 // Note that we first construct the presumed unbiased header so we
1205 // don't accidentally blow away another thread's valid bias.
1206 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1207 andptr(swap_reg,
1208 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1209 #ifdef _LP64
1210 movptr(tmp_reg, swap_reg);
1211 orptr(tmp_reg, r15_thread);
1212 #else
1213 get_thread(tmp_reg);
1214 orptr(tmp_reg, swap_reg);
1215 #endif
1216 if (os::is_MP()) {
1217 lock();
1218 }
1219 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1220 // If the biasing toward our thread failed, this means that
1221 // another thread succeeded in biasing it toward itself and we
1222 // need to revoke that bias. The revocation will occur in the
1223 // interpreter runtime in the slow case.
1224 if (counters != NULL) {
1225 cond_inc32(Assembler::zero,
1226 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1227 }
1228 if (slow_case != NULL) {
1229 jcc(Assembler::notZero, *slow_case);
1230 }
1231 jmp(done);
1232
1233 bind(try_rebias);
1234 // At this point we know the epoch has expired, meaning that the
1235 // current "bias owner", if any, is actually invalid. Under these
1236 // circumstances _only_, we are allowed to use the current header's
1237 // value as the comparison value when doing the cas to acquire the
1238 // bias in the current epoch. In other words, we allow transfer of
1239 // the bias from one thread to another directly in this situation.
1240 //
1241 // FIXME: due to a lack of registers we currently blow away the age
1242 // bits in this situation. Should attempt to preserve them.
1243 load_prototype_header(tmp_reg, obj_reg);
1244 #ifdef _LP64
1245 orptr(tmp_reg, r15_thread);
1246 #else
1247 get_thread(swap_reg);
1248 orptr(tmp_reg, swap_reg);
1249 movptr(swap_reg, saved_mark_addr);
1250 #endif
1251 if (os::is_MP()) {
1252 lock();
1253 }
1254 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1255 // If the biasing toward our thread failed, then another thread
1256 // succeeded in biasing it toward itself and we need to revoke that
1257 // bias. The revocation will occur in the runtime in the slow case.
1258 if (counters != NULL) {
1259 cond_inc32(Assembler::zero,
1260 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1261 }
1262 if (slow_case != NULL) {
1263 jcc(Assembler::notZero, *slow_case);
1264 }
1265 jmp(done);
1266
1267 bind(try_revoke_bias);
1268 // The prototype mark in the klass doesn't have the bias bit set any
1269 // more, indicating that objects of this data type are not supposed
1270 // to be biased any more. We are going to try to reset the mark of
1271 // this object to the prototype value and fall through to the
1272 // CAS-based locking scheme. Note that if our CAS fails, it means
1273 // that another thread raced us for the privilege of revoking the
1274 // bias of this particular object, so it's okay to continue in the
1275 // normal locking code.
1276 //
1277 // FIXME: due to a lack of registers we currently blow away the age
1278 // bits in this situation. Should attempt to preserve them.
1279 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1280 load_prototype_header(tmp_reg, obj_reg);
1281 if (os::is_MP()) {
1282 lock();
1283 }
1284 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1285 // Fall through to the normal CAS-based lock, because no matter what
1286 // the result of the above CAS, some thread must have succeeded in
1287 // removing the bias bit from the object's header.
1288 if (counters != NULL) {
1289 cond_inc32(Assembler::zero,
1290 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1291 }
1292
1293 bind(cas_label);
1294
1295 return null_check_offset;
1296 }
1297
1298 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1299 assert(UseBiasedLocking, "why call this otherwise?");
1300
1301 // Check for biased locking unlock case, which is a no-op
1302 // Note: we do not have to check the thread ID for two reasons.
1303 // First, the interpreter checks for IllegalMonitorStateException at
1304 // a higher level. Second, if the bias was revoked while we held the
1305 // lock, the object could not be rebiased toward another thread, so
1306 // the bias bit would be clear.
1307 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1308 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1309 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1310 jcc(Assembler::equal, done);
1311 }
1312
1313 #ifdef COMPILER2
1314
1315 #if INCLUDE_RTM_OPT
1316
1317 // Update rtm_counters based on abort status
1318 // input: abort_status
1319 // rtm_counters (RTMLockingCounters*)
1320 // flags are killed
1321 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1322
1323 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1324 if (PrintPreciseRTMLockingStatistics) {
1325 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1326 Label check_abort;
1327 testl(abort_status, (1<<i));
1328 jccb(Assembler::equal, check_abort);
1329 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1330 bind(check_abort);
1331 }
1332 }
1333 }
1334
1335 // Branch if (random & (count-1) != 0), count is 2^n
1336 // tmp, scr and flags are killed
1337 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1338 assert(tmp == rax, "");
1339 assert(scr == rdx, "");
1340 rdtsc(); // modifies EDX:EAX
1341 andptr(tmp, count-1);
1342 jccb(Assembler::notZero, brLabel);
1343 }
1344
1345 // Perform abort ratio calculation, set no_rtm bit if high ratio
1346 // input: rtm_counters_Reg (RTMLockingCounters* address)
1347 // tmpReg, rtm_counters_Reg and flags are killed
1348 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1349 Register rtm_counters_Reg,
1350 RTMLockingCounters* rtm_counters,
1351 Metadata* method_data) {
1352 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1353
1354 if (RTMLockingCalculationDelay > 0) {
1355 // Delay calculation
1356 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1357 testptr(tmpReg, tmpReg);
1358 jccb(Assembler::equal, L_done);
1359 }
1360 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1361 // Aborted transactions = abort_count * 100
1362 // All transactions = total_count * RTMTotalCountIncrRate
1363 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1364
1365 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1366 cmpptr(tmpReg, RTMAbortThreshold);
1367 jccb(Assembler::below, L_check_always_rtm2);
1368 imulptr(tmpReg, tmpReg, 100);
1369
1370 Register scrReg = rtm_counters_Reg;
1371 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1372 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1373 imulptr(scrReg, scrReg, RTMAbortRatio);
1374 cmpptr(tmpReg, scrReg);
1375 jccb(Assembler::below, L_check_always_rtm1);
1376 if (method_data != NULL) {
1377 // set rtm_state to "no rtm" in MDO
1378 mov_metadata(tmpReg, method_data);
1379 if (os::is_MP()) {
1380 lock();
1381 }
1382 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1383 }
1384 jmpb(L_done);
1385 bind(L_check_always_rtm1);
1386 // Reload RTMLockingCounters* address
1387 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1388 bind(L_check_always_rtm2);
1389 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1390 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1391 jccb(Assembler::below, L_done);
1392 if (method_data != NULL) {
1393 // set rtm_state to "always rtm" in MDO
1394 mov_metadata(tmpReg, method_data);
1395 if (os::is_MP()) {
1396 lock();
1397 }
1398 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1399 }
1400 bind(L_done);
1401 }
1402
1403 // Update counters and perform abort ratio calculation
1404 // input: abort_status_Reg
1405 // rtm_counters_Reg, flags are killed
1406 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1407 Register rtm_counters_Reg,
1408 RTMLockingCounters* rtm_counters,
1409 Metadata* method_data,
1410 bool profile_rtm) {
1411
1412 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1413 // update rtm counters based on rax value at abort
1414 // reads abort_status_Reg, updates flags
1415 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1416 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1417 if (profile_rtm) {
1418 // Save abort status because abort_status_Reg is used by following code.
1419 if (RTMRetryCount > 0) {
1420 push(abort_status_Reg);
1421 }
1422 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1423 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1424 // restore abort status
1425 if (RTMRetryCount > 0) {
1426 pop(abort_status_Reg);
1427 }
1428 }
1429 }
1430
1431 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1432 // inputs: retry_count_Reg
1433 // : abort_status_Reg
1434 // output: retry_count_Reg decremented by 1
1435 // flags are killed
1436 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1437 Label doneRetry;
1438 assert(abort_status_Reg == rax, "");
1439 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1440 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1441 // if reason is in 0x6 and retry count != 0 then retry
1442 andptr(abort_status_Reg, 0x6);
1443 jccb(Assembler::zero, doneRetry);
1444 testl(retry_count_Reg, retry_count_Reg);
1445 jccb(Assembler::zero, doneRetry);
1446 pause();
1447 decrementl(retry_count_Reg);
1448 jmp(retryLabel);
1449 bind(doneRetry);
1450 }
1451
1452 // Spin and retry if lock is busy,
1453 // inputs: box_Reg (monitor address)
1454 // : retry_count_Reg
1455 // output: retry_count_Reg decremented by 1
1456 // : clear z flag if retry count exceeded
1457 // tmp_Reg, scr_Reg, flags are killed
1458 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1459 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1460 Label SpinLoop, SpinExit, doneRetry;
1461 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1462
1463 testl(retry_count_Reg, retry_count_Reg);
1464 jccb(Assembler::zero, doneRetry);
1465 decrementl(retry_count_Reg);
1466 movptr(scr_Reg, RTMSpinLoopCount);
1467
1468 bind(SpinLoop);
1469 pause();
1470 decrementl(scr_Reg);
1471 jccb(Assembler::lessEqual, SpinExit);
1472 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1473 testptr(tmp_Reg, tmp_Reg);
1474 jccb(Assembler::notZero, SpinLoop);
1475
1476 bind(SpinExit);
1477 jmp(retryLabel);
1478 bind(doneRetry);
1479 incrementl(retry_count_Reg); // clear z flag
1480 }
1481
1482 // Use RTM for normal stack locks
1483 // Input: objReg (object to lock)
1484 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1485 Register retry_on_abort_count_Reg,
1486 RTMLockingCounters* stack_rtm_counters,
1487 Metadata* method_data, bool profile_rtm,
1488 Label& DONE_LABEL, Label& IsInflated) {
1489 assert(UseRTMForStackLocks, "why call this otherwise?");
1490 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1491 assert(tmpReg == rax, "");
1492 assert(scrReg == rdx, "");
1493 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1494
1495 if (RTMRetryCount > 0) {
1496 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1497 bind(L_rtm_retry);
1498 }
1499 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1500 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1501 jcc(Assembler::notZero, IsInflated);
1502
1503 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1504 Label L_noincrement;
1505 if (RTMTotalCountIncrRate > 1) {
1506 // tmpReg, scrReg and flags are killed
1507 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1508 }
1509 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1510 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1511 bind(L_noincrement);
1512 }
1513 xbegin(L_on_abort);
1514 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1515 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1516 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1517 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1518
1519 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1520 if (UseRTMXendForLockBusy) {
1521 xend();
1522 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1523 jmp(L_decrement_retry);
1524 }
1525 else {
1526 xabort(0);
1527 }
1528 bind(L_on_abort);
1529 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1530 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1531 }
1532 bind(L_decrement_retry);
1533 if (RTMRetryCount > 0) {
1534 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1535 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1536 }
1537 }
1538
1539 // Use RTM for inflating locks
1540 // inputs: objReg (object to lock)
1541 // boxReg (on-stack box address (displaced header location) - KILLED)
1542 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1543 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1544 Register scrReg, Register retry_on_busy_count_Reg,
1545 Register retry_on_abort_count_Reg,
1546 RTMLockingCounters* rtm_counters,
1547 Metadata* method_data, bool profile_rtm,
1548 Label& DONE_LABEL) {
1549 assert(UseRTMLocking, "why call this otherwise?");
1550 assert(tmpReg == rax, "");
1551 assert(scrReg == rdx, "");
1552 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1553 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1554
1555 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1556 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1557 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1558
1559 if (RTMRetryCount > 0) {
1560 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1561 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1562 bind(L_rtm_retry);
1563 }
1564 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1565 Label L_noincrement;
1566 if (RTMTotalCountIncrRate > 1) {
1567 // tmpReg, scrReg and flags are killed
1568 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1569 }
1570 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1571 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1572 bind(L_noincrement);
1573 }
1574 xbegin(L_on_abort);
1575 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1576 movptr(tmpReg, Address(tmpReg, owner_offset));
1577 testptr(tmpReg, tmpReg);
1578 jcc(Assembler::zero, DONE_LABEL);
1579 if (UseRTMXendForLockBusy) {
1580 xend();
1581 jmp(L_decrement_retry);
1582 }
1583 else {
1584 xabort(0);
1585 }
1586 bind(L_on_abort);
1587 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1588 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1589 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1590 }
1591 if (RTMRetryCount > 0) {
1592 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1593 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1594 }
1595
1596 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1597 testptr(tmpReg, tmpReg) ;
1598 jccb(Assembler::notZero, L_decrement_retry) ;
1599
1600 // Appears unlocked - try to swing _owner from null to non-null.
1601 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1602 #ifdef _LP64
1603 Register threadReg = r15_thread;
1604 #else
1605 get_thread(scrReg);
1606 Register threadReg = scrReg;
1607 #endif
1608 if (os::is_MP()) {
1609 lock();
1610 }
1611 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1612
1613 if (RTMRetryCount > 0) {
1614 // success done else retry
1615 jccb(Assembler::equal, DONE_LABEL) ;
1616 bind(L_decrement_retry);
1617 // Spin and retry if lock is busy.
1618 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1619 }
1620 else {
1621 bind(L_decrement_retry);
1622 }
1623 }
1624
1625 #endif // INCLUDE_RTM_OPT
1626
1627 // Fast_Lock and Fast_Unlock used by C2
1628
1629 // Because the transitions from emitted code to the runtime
1630 // monitorenter/exit helper stubs are so slow it's critical that
1631 // we inline both the stack-locking fast-path and the inflated fast path.
1632 //
1633 // See also: cmpFastLock and cmpFastUnlock.
1634 //
1635 // What follows is a specialized inline transliteration of the code
1636 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1637 // another option would be to emit TrySlowEnter and TrySlowExit methods
1638 // at startup-time. These methods would accept arguments as
1639 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1640 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1641 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1642 // In practice, however, the # of lock sites is bounded and is usually small.
1643 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1644 // if the processor uses simple bimodal branch predictors keyed by EIP
1645 // Since the helper routines would be called from multiple synchronization
1646 // sites.
1647 //
1648 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1649 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1650 // to those specialized methods. That'd give us a mostly platform-independent
1651 // implementation that the JITs could optimize and inline at their pleasure.
1652 // Done correctly, the only time we'd need to cross to native could would be
1653 // to park() or unpark() threads. We'd also need a few more unsafe operators
1654 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1655 // (b) explicit barriers or fence operations.
1656 //
1657 // TODO:
1658 //
1659 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1660 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1661 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1662 // the lock operators would typically be faster than reifying Self.
1663 //
1664 // * Ideally I'd define the primitives as:
1665 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1666 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1667 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1668 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1669 // Furthermore the register assignments are overconstrained, possibly resulting in
1670 // sub-optimal code near the synchronization site.
1671 //
1672 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1673 // Alternately, use a better sp-proximity test.
1674 //
1675 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1676 // Either one is sufficient to uniquely identify a thread.
1677 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1678 //
1679 // * Intrinsify notify() and notifyAll() for the common cases where the
1680 // object is locked by the calling thread but the waitlist is empty.
1681 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1682 //
1683 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1684 // But beware of excessive branch density on AMD Opterons.
1685 //
1686 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1687 // or failure of the fast-path. If the fast-path fails then we pass
1688 // control to the slow-path, typically in C. In Fast_Lock and
1689 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1690 // will emit a conditional branch immediately after the node.
1691 // So we have branches to branches and lots of ICC.ZF games.
1692 // Instead, it might be better to have C2 pass a "FailureLabel"
1693 // into Fast_Lock and Fast_Unlock. In the case of success, control
1694 // will drop through the node. ICC.ZF is undefined at exit.
1695 // In the case of failure, the node will branch directly to the
1696 // FailureLabel
1697
1698
1699 // obj: object to lock
1700 // box: on-stack box address (displaced header location) - KILLED
1701 // rax,: tmp -- KILLED
1702 // scr: tmp -- KILLED
1703 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1704 Register scrReg, Register cx1Reg, Register cx2Reg,
1705 BiasedLockingCounters* counters,
1706 RTMLockingCounters* rtm_counters,
1707 RTMLockingCounters* stack_rtm_counters,
1708 Metadata* method_data,
1709 bool use_rtm, bool profile_rtm) {
1710 // Ensure the register assignments are disjoint
1711 assert(tmpReg == rax, "");
1712
1713 if (use_rtm) {
1714 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1715 } else {
1716 assert(cx1Reg == noreg, "");
1717 assert(cx2Reg == noreg, "");
1718 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1719 }
1720
1721 if (counters != NULL) {
1722 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1723 }
1724 if (EmitSync & 1) {
1725 // set box->dhw = markOopDesc::unused_mark()
1726 // Force all sync thru slow-path: slow_enter() and slow_exit()
1727 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1728 cmpptr (rsp, (int32_t)NULL_WORD);
1729 } else {
1730 // Possible cases that we'll encounter in fast_lock
1731 // ------------------------------------------------
1732 // * Inflated
1733 // -- unlocked
1734 // -- Locked
1735 // = by self
1736 // = by other
1737 // * biased
1738 // -- by Self
1739 // -- by other
1740 // * neutral
1741 // * stack-locked
1742 // -- by self
1743 // = sp-proximity test hits
1744 // = sp-proximity test generates false-negative
1745 // -- by other
1746 //
1747
1748 Label IsInflated, DONE_LABEL;
1749
1750 // it's stack-locked, biased or neutral
1751 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1752 // order to reduce the number of conditional branches in the most common cases.
1753 // Beware -- there's a subtle invariant that fetch of the markword
1754 // at [FETCH], below, will never observe a biased encoding (*101b).
1755 // If this invariant is not held we risk exclusion (safety) failure.
1756 if (UseBiasedLocking && !UseOptoBiasInlining) {
1757 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1758 }
1759
1760 #if INCLUDE_RTM_OPT
1761 if (UseRTMForStackLocks && use_rtm) {
1762 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1763 stack_rtm_counters, method_data, profile_rtm,
1764 DONE_LABEL, IsInflated);
1765 }
1766 #endif // INCLUDE_RTM_OPT
1767
1768 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1769 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1770 jccb(Assembler::notZero, IsInflated);
1771
1772 // Attempt stack-locking ...
1773 orptr (tmpReg, markOopDesc::unlocked_value);
1774 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1775 if (os::is_MP()) {
1776 lock();
1777 }
1778 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1779 if (counters != NULL) {
1780 cond_inc32(Assembler::equal,
1781 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1782 }
1783 jcc(Assembler::equal, DONE_LABEL); // Success
1784
1785 // Recursive locking.
1786 // The object is stack-locked: markword contains stack pointer to BasicLock.
1787 // Locked by current thread if difference with current SP is less than one page.
1788 subptr(tmpReg, rsp);
1789 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1790 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1791 movptr(Address(boxReg, 0), tmpReg);
1792 if (counters != NULL) {
1793 cond_inc32(Assembler::equal,
1794 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1795 }
1796 jmp(DONE_LABEL);
1797
1798 bind(IsInflated);
1799 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1800
1801 #if INCLUDE_RTM_OPT
1802 // Use the same RTM locking code in 32- and 64-bit VM.
1803 if (use_rtm) {
1804 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1805 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1806 } else {
1807 #endif // INCLUDE_RTM_OPT
1808
1809 #ifndef _LP64
1810 // The object is inflated.
1811
1812 // boxReg refers to the on-stack BasicLock in the current frame.
1813 // We'd like to write:
1814 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1815 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1816 // additional latency as we have another ST in the store buffer that must drain.
1817
1818 if (EmitSync & 8192) {
1819 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1820 get_thread (scrReg);
1821 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1822 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1823 if (os::is_MP()) {
1824 lock();
1825 }
1826 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1827 } else
1828 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1829 // register juggle because we need tmpReg for cmpxchgptr below
1830 movptr(scrReg, boxReg);
1831 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1832
1833 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1834 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1835 // prefetchw [eax + Offset(_owner)-2]
1836 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1837 }
1838
1839 if ((EmitSync & 64) == 0) {
1840 // Optimistic form: consider XORL tmpReg,tmpReg
1841 movptr(tmpReg, NULL_WORD);
1842 } else {
1843 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1844 // Test-And-CAS instead of CAS
1845 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1846 testptr(tmpReg, tmpReg); // Locked ?
1847 jccb (Assembler::notZero, DONE_LABEL);
1848 }
1849
1850 // Appears unlocked - try to swing _owner from null to non-null.
1851 // Ideally, I'd manifest "Self" with get_thread and then attempt
1852 // to CAS the register containing Self into m->Owner.
1853 // But we don't have enough registers, so instead we can either try to CAS
1854 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1855 // we later store "Self" into m->Owner. Transiently storing a stack address
1856 // (rsp or the address of the box) into m->owner is harmless.
1857 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1858 if (os::is_MP()) {
1859 lock();
1860 }
1861 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1862 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1863 // If we weren't able to swing _owner from NULL to the BasicLock
1864 // then take the slow path.
1865 jccb (Assembler::notZero, DONE_LABEL);
1866 // update _owner from BasicLock to thread
1867 get_thread (scrReg); // beware: clobbers ICCs
1868 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1869 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1870
1871 // If the CAS fails we can either retry or pass control to the slow-path.
1872 // We use the latter tactic.
1873 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1874 // If the CAS was successful ...
1875 // Self has acquired the lock
1876 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1877 // Intentional fall-through into DONE_LABEL ...
1878 } else {
1879 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1880 movptr(boxReg, tmpReg);
1881
1882 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1883 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1884 // prefetchw [eax + Offset(_owner)-2]
1885 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1886 }
1887
1888 if ((EmitSync & 64) == 0) {
1889 // Optimistic form
1890 xorptr (tmpReg, tmpReg);
1891 } else {
1892 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1893 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1894 testptr(tmpReg, tmpReg); // Locked ?
1895 jccb (Assembler::notZero, DONE_LABEL);
1896 }
1897
1898 // Appears unlocked - try to swing _owner from null to non-null.
1899 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1900 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1901 get_thread (scrReg);
1902 if (os::is_MP()) {
1903 lock();
1904 }
1905 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1906
1907 // If the CAS fails we can either retry or pass control to the slow-path.
1908 // We use the latter tactic.
1909 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1910 // If the CAS was successful ...
1911 // Self has acquired the lock
1912 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1913 // Intentional fall-through into DONE_LABEL ...
1914 }
1915 #else // _LP64
1916 // It's inflated
1917 movq(scrReg, tmpReg);
1918 xorq(tmpReg, tmpReg);
1919
1920 if (os::is_MP()) {
1921 lock();
1922 }
1923 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1924 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1925 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1926 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1927 // Intentional fall-through into DONE_LABEL ...
1928 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1929 #endif // _LP64
1930 #if INCLUDE_RTM_OPT
1931 } // use_rtm()
1932 #endif
1933 // DONE_LABEL is a hot target - we'd really like to place it at the
1934 // start of cache line by padding with NOPs.
1935 // See the AMD and Intel software optimization manuals for the
1936 // most efficient "long" NOP encodings.
1937 // Unfortunately none of our alignment mechanisms suffice.
1938 bind(DONE_LABEL);
1939
1940 // At DONE_LABEL the icc ZFlag is set as follows ...
1941 // Fast_Unlock uses the same protocol.
1942 // ZFlag == 1 -> Success
1943 // ZFlag == 0 -> Failure - force control through the slow-path
1944 }
1945 }
1946
1947 // obj: object to unlock
1948 // box: box address (displaced header location), killed. Must be EAX.
1949 // tmp: killed, cannot be obj nor box.
1950 //
1951 // Some commentary on balanced locking:
1952 //
1953 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1954 // Methods that don't have provably balanced locking are forced to run in the
1955 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1956 // The interpreter provides two properties:
1957 // I1: At return-time the interpreter automatically and quietly unlocks any
1958 // objects acquired the current activation (frame). Recall that the
1959 // interpreter maintains an on-stack list of locks currently held by
1960 // a frame.
1961 // I2: If a method attempts to unlock an object that is not held by the
1962 // the frame the interpreter throws IMSX.
1963 //
1964 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1965 // B() doesn't have provably balanced locking so it runs in the interpreter.
1966 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1967 // is still locked by A().
1968 //
1969 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1970 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1971 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1972 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1973 // Arguably given that the spec legislates the JNI case as undefined our implementation
1974 // could reasonably *avoid* checking owner in Fast_Unlock().
1975 // In the interest of performance we elide m->Owner==Self check in unlock.
1976 // A perfectly viable alternative is to elide the owner check except when
1977 // Xcheck:jni is enabled.
1978
1979 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1980 assert(boxReg == rax, "");
1981 assert_different_registers(objReg, boxReg, tmpReg);
1982
1983 if (EmitSync & 4) {
1984 // Disable - inhibit all inlining. Force control through the slow-path
1985 cmpptr (rsp, 0);
1986 } else {
1987 Label DONE_LABEL, Stacked, CheckSucc;
1988
1989 // Critically, the biased locking test must have precedence over
1990 // and appear before the (box->dhw == 0) recursive stack-lock test.
1991 if (UseBiasedLocking && !UseOptoBiasInlining) {
1992 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1993 }
1994
1995 #if INCLUDE_RTM_OPT
1996 if (UseRTMForStackLocks && use_rtm) {
1997 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1998 Label L_regular_unlock;
1999 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
2000 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2001 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2002 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2003 xend(); // otherwise end...
2004 jmp(DONE_LABEL); // ... and we're done
2005 bind(L_regular_unlock);
2006 }
2007 #endif
2008
2009 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2010 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2011 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2012 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2013 jccb (Assembler::zero, Stacked);
2014
2015 // It's inflated.
2016 #if INCLUDE_RTM_OPT
2017 if (use_rtm) {
2018 Label L_regular_inflated_unlock;
2019 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2020 movptr(boxReg, Address(tmpReg, owner_offset));
2021 testptr(boxReg, boxReg);
2022 jccb(Assembler::notZero, L_regular_inflated_unlock);
2023 xend();
2024 jmpb(DONE_LABEL);
2025 bind(L_regular_inflated_unlock);
2026 }
2027 #endif
2028
2029 // Despite our balanced locking property we still check that m->_owner == Self
2030 // as java routines or native JNI code called by this thread might
2031 // have released the lock.
2032 // Refer to the comments in synchronizer.cpp for how we might encode extra
2033 // state in _succ so we can avoid fetching EntryList|cxq.
2034 //
2035 // I'd like to add more cases in fast_lock() and fast_unlock() --
2036 // such as recursive enter and exit -- but we have to be wary of
2037 // I$ bloat, T$ effects and BP$ effects.
2038 //
2039 // If there's no contention try a 1-0 exit. That is, exit without
2040 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2041 // we detect and recover from the race that the 1-0 exit admits.
2042 //
2043 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2044 // before it STs null into _owner, releasing the lock. Updates
2045 // to data protected by the critical section must be visible before
2046 // we drop the lock (and thus before any other thread could acquire
2047 // the lock and observe the fields protected by the lock).
2048 // IA32's memory-model is SPO, so STs are ordered with respect to
2049 // each other and there's no need for an explicit barrier (fence).
2050 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2051 #ifndef _LP64
2052 get_thread (boxReg);
2053 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2054 // prefetchw [ebx + Offset(_owner)-2]
2055 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2056 }
2057
2058 // Note that we could employ various encoding schemes to reduce
2059 // the number of loads below (currently 4) to just 2 or 3.
2060 // Refer to the comments in synchronizer.cpp.
2061 // In practice the chain of fetches doesn't seem to impact performance, however.
2062 xorptr(boxReg, boxReg);
2063 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2064 // Attempt to reduce branch density - AMD's branch predictor.
2065 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2066 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2067 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2068 jccb (Assembler::notZero, DONE_LABEL);
2069 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2070 jmpb (DONE_LABEL);
2071 } else {
2072 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2073 jccb (Assembler::notZero, DONE_LABEL);
2074 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2075 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2076 jccb (Assembler::notZero, CheckSucc);
2077 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2078 jmpb (DONE_LABEL);
2079 }
2080
2081 // The Following code fragment (EmitSync & 65536) improves the performance of
2082 // contended applications and contended synchronization microbenchmarks.
2083 // Unfortunately the emission of the code - even though not executed - causes regressions
2084 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2085 // with an equal number of never-executed NOPs results in the same regression.
2086 // We leave it off by default.
2087
2088 if ((EmitSync & 65536) != 0) {
2089 Label LSuccess, LGoSlowPath ;
2090
2091 bind (CheckSucc);
2092
2093 // Optional pre-test ... it's safe to elide this
2094 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2095 jccb(Assembler::zero, LGoSlowPath);
2096
2097 // We have a classic Dekker-style idiom:
2098 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2099 // There are a number of ways to implement the barrier:
2100 // (1) lock:andl &m->_owner, 0
2101 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2102 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2103 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2104 // (2) If supported, an explicit MFENCE is appealing.
2105 // In older IA32 processors MFENCE is slower than lock:add or xchg
2106 // particularly if the write-buffer is full as might be the case if
2107 // if stores closely precede the fence or fence-equivalent instruction.
2108 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2109 // as the situation has changed with Nehalem and Shanghai.
2110 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2111 // The $lines underlying the top-of-stack should be in M-state.
2112 // The locked add instruction is serializing, of course.
2113 // (4) Use xchg, which is serializing
2114 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2115 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2116 // The integer condition codes will tell us if succ was 0.
2117 // Since _succ and _owner should reside in the same $line and
2118 // we just stored into _owner, it's likely that the $line
2119 // remains in M-state for the lock:orl.
2120 //
2121 // We currently use (3), although it's likely that switching to (2)
2122 // is correct for the future.
2123
2124 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2125 if (os::is_MP()) {
2126 lock(); addptr(Address(rsp, 0), 0);
2127 }
2128 // Ratify _succ remains non-null
2129 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2130 jccb (Assembler::notZero, LSuccess);
2131
2132 xorptr(boxReg, boxReg); // box is really EAX
2133 if (os::is_MP()) { lock(); }
2134 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2135 // There's no successor so we tried to regrab the lock with the
2136 // placeholder value. If that didn't work, then another thread
2137 // grabbed the lock so we're done (and exit was a success).
2138 jccb (Assembler::notEqual, LSuccess);
2139 // Since we're low on registers we installed rsp as a placeholding in _owner.
2140 // Now install Self over rsp. This is safe as we're transitioning from
2141 // non-null to non=null
2142 get_thread (boxReg);
2143 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2144 // Intentional fall-through into LGoSlowPath ...
2145
2146 bind (LGoSlowPath);
2147 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2148 jmpb (DONE_LABEL);
2149
2150 bind (LSuccess);
2151 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2152 jmpb (DONE_LABEL);
2153 }
2154
2155 bind (Stacked);
2156 // It's not inflated and it's not recursively stack-locked and it's not biased.
2157 // It must be stack-locked.
2158 // Try to reset the header to displaced header.
2159 // The "box" value on the stack is stable, so we can reload
2160 // and be assured we observe the same value as above.
2161 movptr(tmpReg, Address(boxReg, 0));
2162 if (os::is_MP()) {
2163 lock();
2164 }
2165 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2166 // Intention fall-thru into DONE_LABEL
2167
2168 // DONE_LABEL is a hot target - we'd really like to place it at the
2169 // start of cache line by padding with NOPs.
2170 // See the AMD and Intel software optimization manuals for the
2171 // most efficient "long" NOP encodings.
2172 // Unfortunately none of our alignment mechanisms suffice.
2173 if ((EmitSync & 65536) == 0) {
2174 bind (CheckSucc);
2175 }
2176 #else // _LP64
2177 // It's inflated
2178 if (EmitSync & 1024) {
2179 // Emit code to check that _owner == Self
2180 // We could fold the _owner test into subsequent code more efficiently
2181 // than using a stand-alone check, but since _owner checking is off by
2182 // default we don't bother. We also might consider predicating the
2183 // _owner==Self check on Xcheck:jni or running on a debug build.
2184 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2185 xorptr(boxReg, r15_thread);
2186 } else {
2187 xorptr(boxReg, boxReg);
2188 }
2189 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2190 jccb (Assembler::notZero, DONE_LABEL);
2191 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2192 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2193 jccb (Assembler::notZero, CheckSucc);
2194 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2195 jmpb (DONE_LABEL);
2196
2197 if ((EmitSync & 65536) == 0) {
2198 // Try to avoid passing control into the slow_path ...
2199 Label LSuccess, LGoSlowPath ;
2200 bind (CheckSucc);
2201
2202 // The following optional optimization can be elided if necessary
2203 // Effectively: if (succ == null) goto SlowPath
2204 // The code reduces the window for a race, however,
2205 // and thus benefits performance.
2206 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2207 jccb (Assembler::zero, LGoSlowPath);
2208
2209 xorptr(boxReg, boxReg);
2210 if ((EmitSync & 16) && os::is_MP()) {
2211 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2212 } else {
2213 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2214 if (os::is_MP()) {
2215 // Memory barrier/fence
2216 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2217 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2218 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2219 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2220 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2221 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2222 lock(); addl(Address(rsp, 0), 0);
2223 }
2224 }
2225 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2226 jccb (Assembler::notZero, LSuccess);
2227
2228 // Rare inopportune interleaving - race.
2229 // The successor vanished in the small window above.
2230 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2231 // We need to ensure progress and succession.
2232 // Try to reacquire the lock.
2233 // If that fails then the new owner is responsible for succession and this
2234 // thread needs to take no further action and can exit via the fast path (success).
2235 // If the re-acquire succeeds then pass control into the slow path.
2236 // As implemented, this latter mode is horrible because we generated more
2237 // coherence traffic on the lock *and* artifically extended the critical section
2238 // length while by virtue of passing control into the slow path.
2239
2240 // box is really RAX -- the following CMPXCHG depends on that binding
2241 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2242 if (os::is_MP()) { lock(); }
2243 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2244 // There's no successor so we tried to regrab the lock.
2245 // If that didn't work, then another thread grabbed the
2246 // lock so we're done (and exit was a success).
2247 jccb (Assembler::notEqual, LSuccess);
2248 // Intentional fall-through into slow-path
2249
2250 bind (LGoSlowPath);
2251 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2252 jmpb (DONE_LABEL);
2253
2254 bind (LSuccess);
2255 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2256 jmpb (DONE_LABEL);
2257 }
2258
2259 bind (Stacked);
2260 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2261 if (os::is_MP()) { lock(); }
2262 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2263
2264 if (EmitSync & 65536) {
2265 bind (CheckSucc);
2266 }
2267 #endif
2268 bind(DONE_LABEL);
2269 }
2270 }
2271 #endif // COMPILER2
2272
2273 void MacroAssembler::c2bool(Register x) {
2274 // implements x == 0 ? 0 : 1
2275 // note: must only look at least-significant byte of x
2276 // since C-style booleans are stored in one byte
2277 // only! (was bug)
2278 andl(x, 0xFF);
2279 setb(Assembler::notZero, x);
2280 }
2281
2282 // Wouldn't need if AddressLiteral version had new name
2283 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2284 Assembler::call(L, rtype);
2285 }
2286
2287 void MacroAssembler::call(Register entry) {
2288 Assembler::call(entry);
2289 }
2290
2291 void MacroAssembler::call(AddressLiteral entry) {
2292 if (reachable(entry)) {
2293 Assembler::call_literal(entry.target(), entry.rspec());
2294 } else {
2295 lea(rscratch1, entry);
2296 Assembler::call(rscratch1);
2297 }
2298 }
2299
2300 void MacroAssembler::ic_call(address entry, jint method_index) {
2301 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2302 movptr(rax, (intptr_t)Universe::non_oop_word());
2303 call(AddressLiteral(entry, rh));
2304 }
2305
2306 // Implementation of call_VM versions
2307
2308 void MacroAssembler::call_VM(Register oop_result,
2309 address entry_point,
2310 bool check_exceptions) {
2311 Label C, E;
2312 call(C, relocInfo::none);
2313 jmp(E);
2314
2315 bind(C);
2316 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2317 ret(0);
2318
2319 bind(E);
2320 }
2321
2322 void MacroAssembler::call_VM(Register oop_result,
2323 address entry_point,
2324 Register arg_1,
2325 bool check_exceptions) {
2326 Label C, E;
2327 call(C, relocInfo::none);
2328 jmp(E);
2329
2330 bind(C);
2331 pass_arg1(this, arg_1);
2332 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2333 ret(0);
2334
2335 bind(E);
2336 }
2337
2338 void MacroAssembler::call_VM(Register oop_result,
2339 address entry_point,
2340 Register arg_1,
2341 Register arg_2,
2342 bool check_exceptions) {
2343 Label C, E;
2344 call(C, relocInfo::none);
2345 jmp(E);
2346
2347 bind(C);
2348
2349 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2350
2351 pass_arg2(this, arg_2);
2352 pass_arg1(this, arg_1);
2353 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2354 ret(0);
2355
2356 bind(E);
2357 }
2358
2359 void MacroAssembler::call_VM(Register oop_result,
2360 address entry_point,
2361 Register arg_1,
2362 Register arg_2,
2363 Register arg_3,
2364 bool check_exceptions) {
2365 Label C, E;
2366 call(C, relocInfo::none);
2367 jmp(E);
2368
2369 bind(C);
2370
2371 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2372 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2373 pass_arg3(this, arg_3);
2374
2375 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2376 pass_arg2(this, arg_2);
2377
2378 pass_arg1(this, arg_1);
2379 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2380 ret(0);
2381
2382 bind(E);
2383 }
2384
2385 void MacroAssembler::call_VM(Register oop_result,
2386 Register last_java_sp,
2387 address entry_point,
2388 int number_of_arguments,
2389 bool check_exceptions) {
2390 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2391 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2392 }
2393
2394 void MacroAssembler::call_VM(Register oop_result,
2395 Register last_java_sp,
2396 address entry_point,
2397 Register arg_1,
2398 bool check_exceptions) {
2399 pass_arg1(this, arg_1);
2400 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2401 }
2402
2403 void MacroAssembler::call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 Register arg_1,
2407 Register arg_2,
2408 bool check_exceptions) {
2409
2410 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2411 pass_arg2(this, arg_2);
2412 pass_arg1(this, arg_1);
2413 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2414 }
2415
2416 void MacroAssembler::call_VM(Register oop_result,
2417 Register last_java_sp,
2418 address entry_point,
2419 Register arg_1,
2420 Register arg_2,
2421 Register arg_3,
2422 bool check_exceptions) {
2423 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2424 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2425 pass_arg3(this, arg_3);
2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427 pass_arg2(this, arg_2);
2428 pass_arg1(this, arg_1);
2429 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2430 }
2431
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 int number_of_arguments,
2436 bool check_exceptions) {
2437 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2438 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2439 }
2440
2441 void MacroAssembler::super_call_VM(Register oop_result,
2442 Register last_java_sp,
2443 address entry_point,
2444 Register arg_1,
2445 bool check_exceptions) {
2446 pass_arg1(this, arg_1);
2447 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2448 }
2449
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451 Register last_java_sp,
2452 address entry_point,
2453 Register arg_1,
2454 Register arg_2,
2455 bool check_exceptions) {
2456
2457 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458 pass_arg2(this, arg_2);
2459 pass_arg1(this, arg_1);
2460 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2461 }
2462
2463 void MacroAssembler::super_call_VM(Register oop_result,
2464 Register last_java_sp,
2465 address entry_point,
2466 Register arg_1,
2467 Register arg_2,
2468 Register arg_3,
2469 bool check_exceptions) {
2470 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2471 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2472 pass_arg3(this, arg_3);
2473 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2474 pass_arg2(this, arg_2);
2475 pass_arg1(this, arg_1);
2476 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2477 }
2478
2479 void MacroAssembler::call_VM_base(Register oop_result,
2480 Register java_thread,
2481 Register last_java_sp,
2482 address entry_point,
2483 int number_of_arguments,
2484 bool check_exceptions) {
2485 // determine java_thread register
2486 if (!java_thread->is_valid()) {
2487 #ifdef _LP64
2488 java_thread = r15_thread;
2489 #else
2490 java_thread = rdi;
2491 get_thread(java_thread);
2492 #endif // LP64
2493 }
2494 // determine last_java_sp register
2495 if (!last_java_sp->is_valid()) {
2496 last_java_sp = rsp;
2497 }
2498 // debugging support
2499 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2500 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2501 #ifdef ASSERT
2502 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2503 // r12 is the heapbase.
2504 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2505 #endif // ASSERT
2506
2507 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2508 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2509
2510 // push java thread (becomes first argument of C function)
2511
2512 NOT_LP64(push(java_thread); number_of_arguments++);
2513 LP64_ONLY(mov(c_rarg0, r15_thread));
2514
2515 // set last Java frame before call
2516 assert(last_java_sp != rbp, "can't use ebp/rbp");
2517
2518 // Only interpreter should have to set fp
2519 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2520
2521 // do the call, remove parameters
2522 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2523
2524 // restore the thread (cannot use the pushed argument since arguments
2525 // may be overwritten by C code generated by an optimizing compiler);
2526 // however can use the register value directly if it is callee saved.
2527 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2528 // rdi & rsi (also r15) are callee saved -> nothing to do
2529 #ifdef ASSERT
2530 guarantee(java_thread != rax, "change this code");
2531 push(rax);
2532 { Label L;
2533 get_thread(rax);
2534 cmpptr(java_thread, rax);
2535 jcc(Assembler::equal, L);
2536 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2537 bind(L);
2538 }
2539 pop(rax);
2540 #endif
2541 } else {
2542 get_thread(java_thread);
2543 }
2544 // reset last Java frame
2545 // Only interpreter should have to clear fp
2546 reset_last_Java_frame(java_thread, true);
2547
2548 // C++ interp handles this in the interpreter
2549 check_and_handle_popframe(java_thread);
2550 check_and_handle_earlyret(java_thread);
2551
2552 if (check_exceptions) {
2553 // check for pending exceptions (java_thread is set upon return)
2554 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2555 #ifndef _LP64
2556 jump_cc(Assembler::notEqual,
2557 RuntimeAddress(StubRoutines::forward_exception_entry()));
2558 #else
2559 // This used to conditionally jump to forward_exception however it is
2560 // possible if we relocate that the branch will not reach. So we must jump
2561 // around so we can always reach
2562
2563 Label ok;
2564 jcc(Assembler::equal, ok);
2565 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2566 bind(ok);
2567 #endif // LP64
2568 }
2569
2570 // get oop result if there is one and reset the value in the thread
2571 if (oop_result->is_valid()) {
2572 get_vm_result(oop_result, java_thread);
2573 }
2574 }
2575
2576 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2577
2578 // Calculate the value for last_Java_sp
2579 // somewhat subtle. call_VM does an intermediate call
2580 // which places a return address on the stack just under the
2581 // stack pointer as the user finsihed with it. This allows
2582 // use to retrieve last_Java_pc from last_Java_sp[-1].
2583 // On 32bit we then have to push additional args on the stack to accomplish
2584 // the actual requested call. On 64bit call_VM only can use register args
2585 // so the only extra space is the return address that call_VM created.
2586 // This hopefully explains the calculations here.
2587
2588 #ifdef _LP64
2589 // We've pushed one address, correct last_Java_sp
2590 lea(rax, Address(rsp, wordSize));
2591 #else
2592 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2593 #endif // LP64
2594
2595 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2596
2597 }
2598
2599 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2600 void MacroAssembler::call_VM_leaf0(address entry_point) {
2601 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2602 }
2603
2604 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2605 call_VM_leaf_base(entry_point, number_of_arguments);
2606 }
2607
2608 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2609 pass_arg0(this, arg_0);
2610 call_VM_leaf(entry_point, 1);
2611 }
2612
2613 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2614
2615 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2616 pass_arg1(this, arg_1);
2617 pass_arg0(this, arg_0);
2618 call_VM_leaf(entry_point, 2);
2619 }
2620
2621 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2622 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2623 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2624 pass_arg2(this, arg_2);
2625 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2626 pass_arg1(this, arg_1);
2627 pass_arg0(this, arg_0);
2628 call_VM_leaf(entry_point, 3);
2629 }
2630
2631 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2632 pass_arg0(this, arg_0);
2633 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2634 }
2635
2636 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2637
2638 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2639 pass_arg1(this, arg_1);
2640 pass_arg0(this, arg_0);
2641 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2642 }
2643
2644 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2647 pass_arg2(this, arg_2);
2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2649 pass_arg1(this, arg_1);
2650 pass_arg0(this, arg_0);
2651 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2652 }
2653
2654 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2655 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2656 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2657 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2658 pass_arg3(this, arg_3);
2659 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2660 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2661 pass_arg2(this, arg_2);
2662 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2663 pass_arg1(this, arg_1);
2664 pass_arg0(this, arg_0);
2665 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2666 }
2667
2668 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2669 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2670 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2671 verify_oop(oop_result, "broken oop in call_VM_base");
2672 }
2673
2674 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2675 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2676 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2677 }
2678
2679 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2680 }
2681
2682 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2683 }
2684
2685 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2686 if (reachable(src1)) {
2687 cmpl(as_Address(src1), imm);
2688 } else {
2689 lea(rscratch1, src1);
2690 cmpl(Address(rscratch1, 0), imm);
2691 }
2692 }
2693
2694 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2695 assert(!src2.is_lval(), "use cmpptr");
2696 if (reachable(src2)) {
2697 cmpl(src1, as_Address(src2));
2698 } else {
2699 lea(rscratch1, src2);
2700 cmpl(src1, Address(rscratch1, 0));
2701 }
2702 }
2703
2704 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2705 Assembler::cmpl(src1, imm);
2706 }
2707
2708 void MacroAssembler::cmp32(Register src1, Address src2) {
2709 Assembler::cmpl(src1, src2);
2710 }
2711
2712 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2713 ucomisd(opr1, opr2);
2714
2715 Label L;
2716 if (unordered_is_less) {
2717 movl(dst, -1);
2718 jcc(Assembler::parity, L);
2719 jcc(Assembler::below , L);
2720 movl(dst, 0);
2721 jcc(Assembler::equal , L);
2722 increment(dst);
2723 } else { // unordered is greater
2724 movl(dst, 1);
2725 jcc(Assembler::parity, L);
2726 jcc(Assembler::above , L);
2727 movl(dst, 0);
2728 jcc(Assembler::equal , L);
2729 decrementl(dst);
2730 }
2731 bind(L);
2732 }
2733
2734 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2735 ucomiss(opr1, opr2);
2736
2737 Label L;
2738 if (unordered_is_less) {
2739 movl(dst, -1);
2740 jcc(Assembler::parity, L);
2741 jcc(Assembler::below , L);
2742 movl(dst, 0);
2743 jcc(Assembler::equal , L);
2744 increment(dst);
2745 } else { // unordered is greater
2746 movl(dst, 1);
2747 jcc(Assembler::parity, L);
2748 jcc(Assembler::above , L);
2749 movl(dst, 0);
2750 jcc(Assembler::equal , L);
2751 decrementl(dst);
2752 }
2753 bind(L);
2754 }
2755
2756
2757 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2758 if (reachable(src1)) {
2759 cmpb(as_Address(src1), imm);
2760 } else {
2761 lea(rscratch1, src1);
2762 cmpb(Address(rscratch1, 0), imm);
2763 }
2764 }
2765
2766 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2767 #ifdef _LP64
2768 if (src2.is_lval()) {
2769 movptr(rscratch1, src2);
2770 Assembler::cmpq(src1, rscratch1);
2771 } else if (reachable(src2)) {
2772 cmpq(src1, as_Address(src2));
2773 } else {
2774 lea(rscratch1, src2);
2775 Assembler::cmpq(src1, Address(rscratch1, 0));
2776 }
2777 #else
2778 if (src2.is_lval()) {
2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2780 } else {
2781 cmpl(src1, as_Address(src2));
2782 }
2783 #endif // _LP64
2784 }
2785
2786 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2787 assert(src2.is_lval(), "not a mem-mem compare");
2788 #ifdef _LP64
2789 // moves src2's literal address
2790 movptr(rscratch1, src2);
2791 Assembler::cmpq(src1, rscratch1);
2792 #else
2793 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2794 #endif // _LP64
2795 }
2796
2797 void MacroAssembler::cmpoop(Register src1, Register src2) {
2798 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2799 bs->obj_equals(this, src1, src2);
2800 }
2801
2802 void MacroAssembler::cmpoop(Register src1, Address src2) {
2803 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2804 bs->obj_equals(this, src1, src2);
2805 }
2806
2807 #ifdef _LP64
2808 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2809 movoop(rscratch1, src2);
2810 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2811 bs->obj_equals(this, src1, rscratch1);
2812 }
2813 #endif
2814
2815 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2816 if (reachable(adr)) {
2817 if (os::is_MP())
2818 lock();
2819 cmpxchgptr(reg, as_Address(adr));
2820 } else {
2821 lea(rscratch1, adr);
2822 if (os::is_MP())
2823 lock();
2824 cmpxchgptr(reg, Address(rscratch1, 0));
2825 }
2826 }
2827
2828 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2829 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2830 }
2831
2832 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2833 if (reachable(src)) {
2834 Assembler::comisd(dst, as_Address(src));
2835 } else {
2836 lea(rscratch1, src);
2837 Assembler::comisd(dst, Address(rscratch1, 0));
2838 }
2839 }
2840
2841 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2842 if (reachable(src)) {
2843 Assembler::comiss(dst, as_Address(src));
2844 } else {
2845 lea(rscratch1, src);
2846 Assembler::comiss(dst, Address(rscratch1, 0));
2847 }
2848 }
2849
2850
2851 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2852 Condition negated_cond = negate_condition(cond);
2853 Label L;
2854 jcc(negated_cond, L);
2855 pushf(); // Preserve flags
2856 atomic_incl(counter_addr);
2857 popf();
2858 bind(L);
2859 }
2860
2861 int MacroAssembler::corrected_idivl(Register reg) {
2862 // Full implementation of Java idiv and irem; checks for
2863 // special case as described in JVM spec., p.243 & p.271.
2864 // The function returns the (pc) offset of the idivl
2865 // instruction - may be needed for implicit exceptions.
2866 //
2867 // normal case special case
2868 //
2869 // input : rax,: dividend min_int
2870 // reg: divisor (may not be rax,/rdx) -1
2871 //
2872 // output: rax,: quotient (= rax, idiv reg) min_int
2873 // rdx: remainder (= rax, irem reg) 0
2874 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2875 const int min_int = 0x80000000;
2876 Label normal_case, special_case;
2877
2878 // check for special case
2879 cmpl(rax, min_int);
2880 jcc(Assembler::notEqual, normal_case);
2881 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2882 cmpl(reg, -1);
2883 jcc(Assembler::equal, special_case);
2884
2885 // handle normal case
2886 bind(normal_case);
2887 cdql();
2888 int idivl_offset = offset();
2889 idivl(reg);
2890
2891 // normal and special case exit
2892 bind(special_case);
2893
2894 return idivl_offset;
2895 }
2896
2897
2898
2899 void MacroAssembler::decrementl(Register reg, int value) {
2900 if (value == min_jint) {subl(reg, value) ; return; }
2901 if (value < 0) { incrementl(reg, -value); return; }
2902 if (value == 0) { ; return; }
2903 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2904 /* else */ { subl(reg, value) ; return; }
2905 }
2906
2907 void MacroAssembler::decrementl(Address dst, int value) {
2908 if (value == min_jint) {subl(dst, value) ; return; }
2909 if (value < 0) { incrementl(dst, -value); return; }
2910 if (value == 0) { ; return; }
2911 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2912 /* else */ { subl(dst, value) ; return; }
2913 }
2914
2915 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2916 assert (shift_value > 0, "illegal shift value");
2917 Label _is_positive;
2918 testl (reg, reg);
2919 jcc (Assembler::positive, _is_positive);
2920 int offset = (1 << shift_value) - 1 ;
2921
2922 if (offset == 1) {
2923 incrementl(reg);
2924 } else {
2925 addl(reg, offset);
2926 }
2927
2928 bind (_is_positive);
2929 sarl(reg, shift_value);
2930 }
2931
2932 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2933 if (reachable(src)) {
2934 Assembler::divsd(dst, as_Address(src));
2935 } else {
2936 lea(rscratch1, src);
2937 Assembler::divsd(dst, Address(rscratch1, 0));
2938 }
2939 }
2940
2941 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2942 if (reachable(src)) {
2943 Assembler::divss(dst, as_Address(src));
2944 } else {
2945 lea(rscratch1, src);
2946 Assembler::divss(dst, Address(rscratch1, 0));
2947 }
2948 }
2949
2950 // !defined(COMPILER2) is because of stupid core builds
2951 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2952 void MacroAssembler::empty_FPU_stack() {
2953 if (VM_Version::supports_mmx()) {
2954 emms();
2955 } else {
2956 for (int i = 8; i-- > 0; ) ffree(i);
2957 }
2958 }
2959 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2960
2961
2962 void MacroAssembler::enter() {
2963 push(rbp);
2964 mov(rbp, rsp);
2965 }
2966
2967 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2968 void MacroAssembler::fat_nop() {
2969 if (UseAddressNop) {
2970 addr_nop_5();
2971 } else {
2972 emit_int8(0x26); // es:
2973 emit_int8(0x2e); // cs:
2974 emit_int8(0x64); // fs:
2975 emit_int8(0x65); // gs:
2976 emit_int8((unsigned char)0x90);
2977 }
2978 }
2979
2980 void MacroAssembler::fcmp(Register tmp) {
2981 fcmp(tmp, 1, true, true);
2982 }
2983
2984 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2985 assert(!pop_right || pop_left, "usage error");
2986 if (VM_Version::supports_cmov()) {
2987 assert(tmp == noreg, "unneeded temp");
2988 if (pop_left) {
2989 fucomip(index);
2990 } else {
2991 fucomi(index);
2992 }
2993 if (pop_right) {
2994 fpop();
2995 }
2996 } else {
2997 assert(tmp != noreg, "need temp");
2998 if (pop_left) {
2999 if (pop_right) {
3000 fcompp();
3001 } else {
3002 fcomp(index);
3003 }
3004 } else {
3005 fcom(index);
3006 }
3007 // convert FPU condition into eflags condition via rax,
3008 save_rax(tmp);
3009 fwait(); fnstsw_ax();
3010 sahf();
3011 restore_rax(tmp);
3012 }
3013 // condition codes set as follows:
3014 //
3015 // CF (corresponds to C0) if x < y
3016 // PF (corresponds to C2) if unordered
3017 // ZF (corresponds to C3) if x = y
3018 }
3019
3020 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3021 fcmp2int(dst, unordered_is_less, 1, true, true);
3022 }
3023
3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3025 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3026 Label L;
3027 if (unordered_is_less) {
3028 movl(dst, -1);
3029 jcc(Assembler::parity, L);
3030 jcc(Assembler::below , L);
3031 movl(dst, 0);
3032 jcc(Assembler::equal , L);
3033 increment(dst);
3034 } else { // unordered is greater
3035 movl(dst, 1);
3036 jcc(Assembler::parity, L);
3037 jcc(Assembler::above , L);
3038 movl(dst, 0);
3039 jcc(Assembler::equal , L);
3040 decrementl(dst);
3041 }
3042 bind(L);
3043 }
3044
3045 void MacroAssembler::fld_d(AddressLiteral src) {
3046 fld_d(as_Address(src));
3047 }
3048
3049 void MacroAssembler::fld_s(AddressLiteral src) {
3050 fld_s(as_Address(src));
3051 }
3052
3053 void MacroAssembler::fld_x(AddressLiteral src) {
3054 Assembler::fld_x(as_Address(src));
3055 }
3056
3057 void MacroAssembler::fldcw(AddressLiteral src) {
3058 Assembler::fldcw(as_Address(src));
3059 }
3060
3061 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3062 if (reachable(src)) {
3063 Assembler::mulpd(dst, as_Address(src));
3064 } else {
3065 lea(rscratch1, src);
3066 Assembler::mulpd(dst, Address(rscratch1, 0));
3067 }
3068 }
3069
3070 void MacroAssembler::increase_precision() {
3071 subptr(rsp, BytesPerWord);
3072 fnstcw(Address(rsp, 0));
3073 movl(rax, Address(rsp, 0));
3074 orl(rax, 0x300);
3075 push(rax);
3076 fldcw(Address(rsp, 0));
3077 pop(rax);
3078 }
3079
3080 void MacroAssembler::restore_precision() {
3081 fldcw(Address(rsp, 0));
3082 addptr(rsp, BytesPerWord);
3083 }
3084
3085 void MacroAssembler::fpop() {
3086 ffree();
3087 fincstp();
3088 }
3089
3090 void MacroAssembler::load_float(Address src) {
3091 if (UseSSE >= 1) {
3092 movflt(xmm0, src);
3093 } else {
3094 LP64_ONLY(ShouldNotReachHere());
3095 NOT_LP64(fld_s(src));
3096 }
3097 }
3098
3099 void MacroAssembler::store_float(Address dst) {
3100 if (UseSSE >= 1) {
3101 movflt(dst, xmm0);
3102 } else {
3103 LP64_ONLY(ShouldNotReachHere());
3104 NOT_LP64(fstp_s(dst));
3105 }
3106 }
3107
3108 void MacroAssembler::load_double(Address src) {
3109 if (UseSSE >= 2) {
3110 movdbl(xmm0, src);
3111 } else {
3112 LP64_ONLY(ShouldNotReachHere());
3113 NOT_LP64(fld_d(src));
3114 }
3115 }
3116
3117 void MacroAssembler::store_double(Address dst) {
3118 if (UseSSE >= 2) {
3119 movdbl(dst, xmm0);
3120 } else {
3121 LP64_ONLY(ShouldNotReachHere());
3122 NOT_LP64(fstp_d(dst));
3123 }
3124 }
3125
3126 void MacroAssembler::push_zmm(XMMRegister reg) {
3127 lea(rsp, Address(rsp, -64)); // Use lea to not affect flags
3128 evmovdqul(Address(rsp, 0), reg, Assembler::AVX_512bit);
3129 }
3130
3131 void MacroAssembler::pop_zmm(XMMRegister reg) {
3132 evmovdqul(reg, Address(rsp, 0), Assembler::AVX_512bit);
3133 lea(rsp, Address(rsp, 64)); // Use lea to not affect flags
3134 }
3135
3136 void MacroAssembler::fremr(Register tmp) {
3137 save_rax(tmp);
3138 { Label L;
3139 bind(L);
3140 fprem();
3141 fwait(); fnstsw_ax();
3142 #ifdef _LP64
3143 testl(rax, 0x400);
3144 jcc(Assembler::notEqual, L);
3145 #else
3146 sahf();
3147 jcc(Assembler::parity, L);
3148 #endif // _LP64
3149 }
3150 restore_rax(tmp);
3151 // Result is in ST0.
3152 // Note: fxch & fpop to get rid of ST1
3153 // (otherwise FPU stack could overflow eventually)
3154 fxch(1);
3155 fpop();
3156 }
3157
3158 // dst = c = a * b + c
3159 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3160 Assembler::vfmadd231sd(c, a, b);
3161 if (dst != c) {
3162 movdbl(dst, c);
3163 }
3164 }
3165
3166 // dst = c = a * b + c
3167 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3168 Assembler::vfmadd231ss(c, a, b);
3169 if (dst != c) {
3170 movflt(dst, c);
3171 }
3172 }
3173
3174 // dst = c = a * b + c
3175 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3176 Assembler::vfmadd231pd(c, a, b, vector_len);
3177 if (dst != c) {
3178 vmovdqu(dst, c);
3179 }
3180 }
3181
3182 // dst = c = a * b + c
3183 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3184 Assembler::vfmadd231ps(c, a, b, vector_len);
3185 if (dst != c) {
3186 vmovdqu(dst, c);
3187 }
3188 }
3189
3190 // dst = c = a * b + c
3191 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3192 Assembler::vfmadd231pd(c, a, b, vector_len);
3193 if (dst != c) {
3194 vmovdqu(dst, c);
3195 }
3196 }
3197
3198 // dst = c = a * b + c
3199 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3200 Assembler::vfmadd231ps(c, a, b, vector_len);
3201 if (dst != c) {
3202 vmovdqu(dst, c);
3203 }
3204 }
3205
3206 void MacroAssembler::incrementl(AddressLiteral dst) {
3207 if (reachable(dst)) {
3208 incrementl(as_Address(dst));
3209 } else {
3210 lea(rscratch1, dst);
3211 incrementl(Address(rscratch1, 0));
3212 }
3213 }
3214
3215 void MacroAssembler::incrementl(ArrayAddress dst) {
3216 incrementl(as_Address(dst));
3217 }
3218
3219 void MacroAssembler::incrementl(Register reg, int value) {
3220 if (value == min_jint) {addl(reg, value) ; return; }
3221 if (value < 0) { decrementl(reg, -value); return; }
3222 if (value == 0) { ; return; }
3223 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3224 /* else */ { addl(reg, value) ; return; }
3225 }
3226
3227 void MacroAssembler::incrementl(Address dst, int value) {
3228 if (value == min_jint) {addl(dst, value) ; return; }
3229 if (value < 0) { decrementl(dst, -value); return; }
3230 if (value == 0) { ; return; }
3231 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3232 /* else */ { addl(dst, value) ; return; }
3233 }
3234
3235 void MacroAssembler::jump(AddressLiteral dst) {
3236 if (reachable(dst)) {
3237 jmp_literal(dst.target(), dst.rspec());
3238 } else {
3239 lea(rscratch1, dst);
3240 jmp(rscratch1);
3241 }
3242 }
3243
3244 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3245 if (reachable(dst)) {
3246 InstructionMark im(this);
3247 relocate(dst.reloc());
3248 const int short_size = 2;
3249 const int long_size = 6;
3250 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3251 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3252 // 0111 tttn #8-bit disp
3253 emit_int8(0x70 | cc);
3254 emit_int8((offs - short_size) & 0xFF);
3255 } else {
3256 // 0000 1111 1000 tttn #32-bit disp
3257 emit_int8(0x0F);
3258 emit_int8((unsigned char)(0x80 | cc));
3259 emit_int32(offs - long_size);
3260 }
3261 } else {
3262 #ifdef ASSERT
3263 warning("reversing conditional branch");
3264 #endif /* ASSERT */
3265 Label skip;
3266 jccb(reverse[cc], skip);
3267 lea(rscratch1, dst);
3268 Assembler::jmp(rscratch1);
3269 bind(skip);
3270 }
3271 }
3272
3273 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3274 if (reachable(src)) {
3275 Assembler::ldmxcsr(as_Address(src));
3276 } else {
3277 lea(rscratch1, src);
3278 Assembler::ldmxcsr(Address(rscratch1, 0));
3279 }
3280 }
3281
3282 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3283 int off;
3284 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3285 off = offset();
3286 movsbl(dst, src); // movsxb
3287 } else {
3288 off = load_unsigned_byte(dst, src);
3289 shll(dst, 24);
3290 sarl(dst, 24);
3291 }
3292 return off;
3293 }
3294
3295 // Note: load_signed_short used to be called load_signed_word.
3296 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3297 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3298 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3299 int MacroAssembler::load_signed_short(Register dst, Address src) {
3300 int off;
3301 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3302 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3303 // version but this is what 64bit has always done. This seems to imply
3304 // that users are only using 32bits worth.
3305 off = offset();
3306 movswl(dst, src); // movsxw
3307 } else {
3308 off = load_unsigned_short(dst, src);
3309 shll(dst, 16);
3310 sarl(dst, 16);
3311 }
3312 return off;
3313 }
3314
3315 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3316 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3317 // and "3.9 Partial Register Penalties", p. 22).
3318 int off;
3319 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3320 off = offset();
3321 movzbl(dst, src); // movzxb
3322 } else {
3323 xorl(dst, dst);
3324 off = offset();
3325 movb(dst, src);
3326 }
3327 return off;
3328 }
3329
3330 // Note: load_unsigned_short used to be called load_unsigned_word.
3331 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3332 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3333 // and "3.9 Partial Register Penalties", p. 22).
3334 int off;
3335 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3336 off = offset();
3337 movzwl(dst, src); // movzxw
3338 } else {
3339 xorl(dst, dst);
3340 off = offset();
3341 movw(dst, src);
3342 }
3343 return off;
3344 }
3345
3346 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3347 switch (size_in_bytes) {
3348 #ifndef _LP64
3349 case 8:
3350 assert(dst2 != noreg, "second dest register required");
3351 movl(dst, src);
3352 movl(dst2, src.plus_disp(BytesPerInt));
3353 break;
3354 #else
3355 case 8: movq(dst, src); break;
3356 #endif
3357 case 4: movl(dst, src); break;
3358 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3359 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3360 default: ShouldNotReachHere();
3361 }
3362 }
3363
3364 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3365 switch (size_in_bytes) {
3366 #ifndef _LP64
3367 case 8:
3368 assert(src2 != noreg, "second source register required");
3369 movl(dst, src);
3370 movl(dst.plus_disp(BytesPerInt), src2);
3371 break;
3372 #else
3373 case 8: movq(dst, src); break;
3374 #endif
3375 case 4: movl(dst, src); break;
3376 case 2: movw(dst, src); break;
3377 case 1: movb(dst, src); break;
3378 default: ShouldNotReachHere();
3379 }
3380 }
3381
3382 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3383 if (reachable(dst)) {
3384 movl(as_Address(dst), src);
3385 } else {
3386 lea(rscratch1, dst);
3387 movl(Address(rscratch1, 0), src);
3388 }
3389 }
3390
3391 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3392 if (reachable(src)) {
3393 movl(dst, as_Address(src));
3394 } else {
3395 lea(rscratch1, src);
3396 movl(dst, Address(rscratch1, 0));
3397 }
3398 }
3399
3400 // C++ bool manipulation
3401
3402 void MacroAssembler::movbool(Register dst, Address src) {
3403 if(sizeof(bool) == 1)
3404 movb(dst, src);
3405 else if(sizeof(bool) == 2)
3406 movw(dst, src);
3407 else if(sizeof(bool) == 4)
3408 movl(dst, src);
3409 else
3410 // unsupported
3411 ShouldNotReachHere();
3412 }
3413
3414 void MacroAssembler::movbool(Address dst, bool boolconst) {
3415 if(sizeof(bool) == 1)
3416 movb(dst, (int) boolconst);
3417 else if(sizeof(bool) == 2)
3418 movw(dst, (int) boolconst);
3419 else if(sizeof(bool) == 4)
3420 movl(dst, (int) boolconst);
3421 else
3422 // unsupported
3423 ShouldNotReachHere();
3424 }
3425
3426 void MacroAssembler::movbool(Address dst, Register src) {
3427 if(sizeof(bool) == 1)
3428 movb(dst, src);
3429 else if(sizeof(bool) == 2)
3430 movw(dst, src);
3431 else if(sizeof(bool) == 4)
3432 movl(dst, src);
3433 else
3434 // unsupported
3435 ShouldNotReachHere();
3436 }
3437
3438 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3439 movb(as_Address(dst), src);
3440 }
3441
3442 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3443 if (reachable(src)) {
3444 movdl(dst, as_Address(src));
3445 } else {
3446 lea(rscratch1, src);
3447 movdl(dst, Address(rscratch1, 0));
3448 }
3449 }
3450
3451 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3452 if (reachable(src)) {
3453 movq(dst, as_Address(src));
3454 } else {
3455 lea(rscratch1, src);
3456 movq(dst, Address(rscratch1, 0));
3457 }
3458 }
3459
3460 void MacroAssembler::setvectmask(Register dst, Register src) {
3461 Assembler::movl(dst, 1);
3462 Assembler::shlxl(dst, dst, src);
3463 Assembler::decl(dst);
3464 Assembler::kmovdl(k1, dst);
3465 Assembler::movl(dst, src);
3466 }
3467
3468 void MacroAssembler::restorevectmask() {
3469 Assembler::knotwl(k1, k0);
3470 }
3471
3472 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3473 if (reachable(src)) {
3474 if (UseXmmLoadAndClearUpper) {
3475 movsd (dst, as_Address(src));
3476 } else {
3477 movlpd(dst, as_Address(src));
3478 }
3479 } else {
3480 lea(rscratch1, src);
3481 if (UseXmmLoadAndClearUpper) {
3482 movsd (dst, Address(rscratch1, 0));
3483 } else {
3484 movlpd(dst, Address(rscratch1, 0));
3485 }
3486 }
3487 }
3488
3489 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3490 if (reachable(src)) {
3491 movss(dst, as_Address(src));
3492 } else {
3493 lea(rscratch1, src);
3494 movss(dst, Address(rscratch1, 0));
3495 }
3496 }
3497
3498 void MacroAssembler::movptr(Register dst, Register src) {
3499 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3500 }
3501
3502 void MacroAssembler::movptr(Register dst, Address src) {
3503 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3504 }
3505
3506 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3507 void MacroAssembler::movptr(Register dst, intptr_t src) {
3508 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3509 }
3510
3511 void MacroAssembler::movptr(Address dst, Register src) {
3512 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3513 }
3514
3515 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3516 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3517 Assembler::vextractf32x4(dst, src, 0);
3518 } else {
3519 Assembler::movdqu(dst, src);
3520 }
3521 }
3522
3523 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3524 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3525 Assembler::vinsertf32x4(dst, dst, src, 0);
3526 } else {
3527 Assembler::movdqu(dst, src);
3528 }
3529 }
3530
3531 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3532 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3533 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3534 } else {
3535 Assembler::movdqu(dst, src);
3536 }
3537 }
3538
3539 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3540 if (reachable(src)) {
3541 movdqu(dst, as_Address(src));
3542 } else {
3543 lea(scratchReg, src);
3544 movdqu(dst, Address(scratchReg, 0));
3545 }
3546 }
3547
3548 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3549 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3550 vextractf64x4_low(dst, src);
3551 } else {
3552 Assembler::vmovdqu(dst, src);
3553 }
3554 }
3555
3556 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3557 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3558 vinsertf64x4_low(dst, src);
3559 } else {
3560 Assembler::vmovdqu(dst, src);
3561 }
3562 }
3563
3564 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3565 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3566 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3567 }
3568 else {
3569 Assembler::vmovdqu(dst, src);
3570 }
3571 }
3572
3573 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3574 if (reachable(src)) {
3575 vmovdqu(dst, as_Address(src));
3576 }
3577 else {
3578 lea(rscratch1, src);
3579 vmovdqu(dst, Address(rscratch1, 0));
3580 }
3581 }
3582
3583 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3584 if (reachable(src)) {
3585 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3586 } else {
3587 lea(rscratch, src);
3588 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3589 }
3590 }
3591
3592 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3593 if (reachable(src)) {
3594 Assembler::movdqa(dst, as_Address(src));
3595 } else {
3596 lea(rscratch1, src);
3597 Assembler::movdqa(dst, Address(rscratch1, 0));
3598 }
3599 }
3600
3601 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3602 if (reachable(src)) {
3603 Assembler::movsd(dst, as_Address(src));
3604 } else {
3605 lea(rscratch1, src);
3606 Assembler::movsd(dst, Address(rscratch1, 0));
3607 }
3608 }
3609
3610 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3611 if (reachable(src)) {
3612 Assembler::movss(dst, as_Address(src));
3613 } else {
3614 lea(rscratch1, src);
3615 Assembler::movss(dst, Address(rscratch1, 0));
3616 }
3617 }
3618
3619 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3620 if (reachable(src)) {
3621 Assembler::mulsd(dst, as_Address(src));
3622 } else {
3623 lea(rscratch1, src);
3624 Assembler::mulsd(dst, Address(rscratch1, 0));
3625 }
3626 }
3627
3628 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3629 if (reachable(src)) {
3630 Assembler::mulss(dst, as_Address(src));
3631 } else {
3632 lea(rscratch1, src);
3633 Assembler::mulss(dst, Address(rscratch1, 0));
3634 }
3635 }
3636
3637 void MacroAssembler::null_check(Register reg, int offset) {
3638 if (needs_explicit_null_check(offset)) {
3639 // provoke OS NULL exception if reg = NULL by
3640 // accessing M[reg] w/o changing any (non-CC) registers
3641 // NOTE: cmpl is plenty here to provoke a segv
3642 cmpptr(rax, Address(reg, 0));
3643 // Note: should probably use testl(rax, Address(reg, 0));
3644 // may be shorter code (however, this version of
3645 // testl needs to be implemented first)
3646 } else {
3647 // nothing to do, (later) access of M[reg + offset]
3648 // will provoke OS NULL exception if reg = NULL
3649 }
3650 }
3651
3652 void MacroAssembler::os_breakpoint() {
3653 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3654 // (e.g., MSVC can't call ps() otherwise)
3655 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3656 }
3657
3658 void MacroAssembler::unimplemented(const char* what) {
3659 const char* buf = NULL;
3660 {
3661 ResourceMark rm;
3662 stringStream ss;
3663 ss.print("unimplemented: %s", what);
3664 buf = code_string(ss.as_string());
3665 }
3666 stop(buf);
3667 }
3668
3669 #ifdef _LP64
3670 #define XSTATE_BV 0x200
3671 #endif
3672
3673 void MacroAssembler::pop_CPU_state() {
3674 pop_FPU_state();
3675 pop_IU_state();
3676 }
3677
3678 void MacroAssembler::pop_FPU_state() {
3679 #ifndef _LP64
3680 frstor(Address(rsp, 0));
3681 #else
3682 fxrstor(Address(rsp, 0));
3683 #endif
3684 addptr(rsp, FPUStateSizeInWords * wordSize);
3685 }
3686
3687 void MacroAssembler::pop_IU_state() {
3688 popa();
3689 LP64_ONLY(addq(rsp, 8));
3690 popf();
3691 }
3692
3693 // Save Integer and Float state
3694 // Warning: Stack must be 16 byte aligned (64bit)
3695 void MacroAssembler::push_CPU_state() {
3696 push_IU_state();
3697 push_FPU_state();
3698 }
3699
3700 void MacroAssembler::push_FPU_state() {
3701 subptr(rsp, FPUStateSizeInWords * wordSize);
3702 #ifndef _LP64
3703 fnsave(Address(rsp, 0));
3704 fwait();
3705 #else
3706 fxsave(Address(rsp, 0));
3707 #endif // LP64
3708 }
3709
3710 void MacroAssembler::push_IU_state() {
3711 // Push flags first because pusha kills them
3712 pushf();
3713 // Make sure rsp stays 16-byte aligned
3714 LP64_ONLY(subq(rsp, 8));
3715 pusha();
3716 }
3717
3718 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3719 if (!java_thread->is_valid()) {
3720 java_thread = rdi;
3721 get_thread(java_thread);
3722 }
3723 // we must set sp to zero to clear frame
3724 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3725 if (clear_fp) {
3726 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3727 }
3728
3729 // Always clear the pc because it could have been set by make_walkable()
3730 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3731
3732 vzeroupper();
3733 }
3734
3735 void MacroAssembler::restore_rax(Register tmp) {
3736 if (tmp == noreg) pop(rax);
3737 else if (tmp != rax) mov(rax, tmp);
3738 }
3739
3740 void MacroAssembler::round_to(Register reg, int modulus) {
3741 addptr(reg, modulus - 1);
3742 andptr(reg, -modulus);
3743 }
3744
3745 void MacroAssembler::save_rax(Register tmp) {
3746 if (tmp == noreg) push(rax);
3747 else if (tmp != rax) mov(tmp, rax);
3748 }
3749
3750 // Write serialization page so VM thread can do a pseudo remote membar.
3751 // We use the current thread pointer to calculate a thread specific
3752 // offset to write to within the page. This minimizes bus traffic
3753 // due to cache line collision.
3754 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3755 movl(tmp, thread);
3756 shrl(tmp, os::get_serialize_page_shift_count());
3757 andl(tmp, (os::vm_page_size() - sizeof(int)));
3758
3759 Address index(noreg, tmp, Address::times_1);
3760 ExternalAddress page(os::get_memory_serialize_page());
3761
3762 // Size of store must match masking code above
3763 movl(as_Address(ArrayAddress(page, index)), tmp);
3764 }
3765
3766 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3767 if (SafepointMechanism::uses_thread_local_poll()) {
3768 #ifdef _LP64
3769 assert(thread_reg == r15_thread, "should be");
3770 #else
3771 if (thread_reg == noreg) {
3772 thread_reg = temp_reg;
3773 get_thread(thread_reg);
3774 }
3775 #endif
3776 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3777 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3778 } else {
3779 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3780 SafepointSynchronize::_not_synchronized);
3781 jcc(Assembler::notEqual, slow_path);
3782 }
3783 }
3784
3785 // Calls to C land
3786 //
3787 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3788 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3789 // has to be reset to 0. This is required to allow proper stack traversal.
3790 void MacroAssembler::set_last_Java_frame(Register java_thread,
3791 Register last_java_sp,
3792 Register last_java_fp,
3793 address last_java_pc) {
3794 vzeroupper();
3795 // determine java_thread register
3796 if (!java_thread->is_valid()) {
3797 java_thread = rdi;
3798 get_thread(java_thread);
3799 }
3800 // determine last_java_sp register
3801 if (!last_java_sp->is_valid()) {
3802 last_java_sp = rsp;
3803 }
3804
3805 // last_java_fp is optional
3806
3807 if (last_java_fp->is_valid()) {
3808 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3809 }
3810
3811 // last_java_pc is optional
3812
3813 if (last_java_pc != NULL) {
3814 lea(Address(java_thread,
3815 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3816 InternalAddress(last_java_pc));
3817
3818 }
3819 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3820 }
3821
3822 void MacroAssembler::shlptr(Register dst, int imm8) {
3823 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3824 }
3825
3826 void MacroAssembler::shrptr(Register dst, int imm8) {
3827 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3828 }
3829
3830 void MacroAssembler::sign_extend_byte(Register reg) {
3831 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3832 movsbl(reg, reg); // movsxb
3833 } else {
3834 shll(reg, 24);
3835 sarl(reg, 24);
3836 }
3837 }
3838
3839 void MacroAssembler::sign_extend_short(Register reg) {
3840 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3841 movswl(reg, reg); // movsxw
3842 } else {
3843 shll(reg, 16);
3844 sarl(reg, 16);
3845 }
3846 }
3847
3848 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3849 assert(reachable(src), "Address should be reachable");
3850 testl(dst, as_Address(src));
3851 }
3852
3853 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3854 int dst_enc = dst->encoding();
3855 int src_enc = src->encoding();
3856 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3857 Assembler::pcmpeqb(dst, src);
3858 } else if ((dst_enc < 16) && (src_enc < 16)) {
3859 Assembler::pcmpeqb(dst, src);
3860 } else if (src_enc < 16) {
3861 push_zmm(xmm0);
3862 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3863 Assembler::pcmpeqb(xmm0, src);
3864 movdqu(dst, xmm0);
3865 pop_zmm(xmm0);
3866 } else if (dst_enc < 16) {
3867 push_zmm(xmm0);
3868 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3869 Assembler::pcmpeqb(dst, xmm0);
3870 pop_zmm(xmm0);
3871 } else {
3872 push_zmm(xmm0);
3873 push_zmm(xmm1);
3874 movdqu(xmm0, src);
3875 movdqu(xmm1, dst);
3876 Assembler::pcmpeqb(xmm1, xmm0);
3877 movdqu(dst, xmm1);
3878 pop_zmm(xmm1);
3879 pop_zmm(xmm0);
3880 }
3881 }
3882
3883 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3884 int dst_enc = dst->encoding();
3885 int src_enc = src->encoding();
3886 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3887 Assembler::pcmpeqw(dst, src);
3888 } else if ((dst_enc < 16) && (src_enc < 16)) {
3889 Assembler::pcmpeqw(dst, src);
3890 } else if (src_enc < 16) {
3891 push_zmm(xmm0);
3892 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3893 Assembler::pcmpeqw(xmm0, src);
3894 movdqu(dst, xmm0);
3895 pop_zmm(xmm0);
3896 } else if (dst_enc < 16) {
3897 push_zmm(xmm0);
3898 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3899 Assembler::pcmpeqw(dst, xmm0);
3900 pop_zmm(xmm0);
3901 } else {
3902 push_zmm(xmm0);
3903 push_zmm(xmm1);
3904 movdqu(xmm0, src);
3905 movdqu(xmm1, dst);
3906 Assembler::pcmpeqw(xmm1, xmm0);
3907 movdqu(dst, xmm1);
3908 pop_zmm(xmm1);
3909 pop_zmm(xmm0);
3910 }
3911 }
3912
3913 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3914 int dst_enc = dst->encoding();
3915 if (dst_enc < 16) {
3916 Assembler::pcmpestri(dst, src, imm8);
3917 } else {
3918 push_zmm(xmm0);
3919 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3920 Assembler::pcmpestri(xmm0, src, imm8);
3921 movdqu(dst, xmm0);
3922 pop_zmm(xmm0);
3923 }
3924 }
3925
3926 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3927 int dst_enc = dst->encoding();
3928 int src_enc = src->encoding();
3929 if ((dst_enc < 16) && (src_enc < 16)) {
3930 Assembler::pcmpestri(dst, src, imm8);
3931 } else if (src_enc < 16) {
3932 push_zmm(xmm0);
3933 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3934 Assembler::pcmpestri(xmm0, src, imm8);
3935 movdqu(dst, xmm0);
3936 pop_zmm(xmm0);
3937 } else if (dst_enc < 16) {
3938 push_zmm(xmm0);
3939 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3940 Assembler::pcmpestri(dst, xmm0, imm8);
3941 pop_zmm(xmm0);
3942 } else {
3943 push_zmm(xmm0);
3944 push_zmm(xmm1);
3945 movdqu(xmm0, src);
3946 movdqu(xmm1, dst);
3947 Assembler::pcmpestri(xmm1, xmm0, imm8);
3948 movdqu(dst, xmm1);
3949 pop_zmm(xmm1);
3950 pop_zmm(xmm0);
3951 }
3952 }
3953
3954 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3955 int dst_enc = dst->encoding();
3956 int src_enc = src->encoding();
3957 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3958 Assembler::pmovzxbw(dst, src);
3959 } else if ((dst_enc < 16) && (src_enc < 16)) {
3960 Assembler::pmovzxbw(dst, src);
3961 } else if (src_enc < 16) {
3962 push_zmm(xmm0);
3963 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3964 Assembler::pmovzxbw(xmm0, src);
3965 movdqu(dst, xmm0);
3966 pop_zmm(xmm0);
3967 } else if (dst_enc < 16) {
3968 push_zmm(xmm0);
3969 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3970 Assembler::pmovzxbw(dst, xmm0);
3971 pop_zmm(xmm0);
3972 } else {
3973 push_zmm(xmm0);
3974 push_zmm(xmm1);
3975 movdqu(xmm0, src);
3976 movdqu(xmm1, dst);
3977 Assembler::pmovzxbw(xmm1, xmm0);
3978 movdqu(dst, xmm1);
3979 pop_zmm(xmm1);
3980 pop_zmm(xmm0);
3981 }
3982 }
3983
3984 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3985 int dst_enc = dst->encoding();
3986 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3987 Assembler::pmovzxbw(dst, src);
3988 } else if (dst_enc < 16) {
3989 Assembler::pmovzxbw(dst, src);
3990 } else {
3991 push_zmm(xmm0);
3992 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3993 Assembler::pmovzxbw(xmm0, src);
3994 movdqu(dst, xmm0);
3995 pop_zmm(xmm0);
3996 }
3997 }
3998
3999 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
4000 int src_enc = src->encoding();
4001 if (src_enc < 16) {
4002 Assembler::pmovmskb(dst, src);
4003 } else {
4004 push_zmm(xmm0);
4005 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4006 Assembler::pmovmskb(dst, xmm0);
4007 pop_zmm(xmm0);
4008 }
4009 }
4010
4011 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
4012 int dst_enc = dst->encoding();
4013 int src_enc = src->encoding();
4014 if ((dst_enc < 16) && (src_enc < 16)) {
4015 Assembler::ptest(dst, src);
4016 } else if (src_enc < 16) {
4017 push_zmm(xmm0);
4018 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4019 Assembler::ptest(xmm0, src);
4020 pop_zmm(xmm0);
4021 } else if (dst_enc < 16) {
4022 push_zmm(xmm0);
4023 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4024 Assembler::ptest(dst, xmm0);
4025 pop_zmm(xmm0);
4026 } else {
4027 push_zmm(xmm0);
4028 push_zmm(xmm1);
4029 movdqu(xmm0, src);
4030 movdqu(xmm1, dst);
4031 Assembler::ptest(xmm1, xmm0);
4032 pop_zmm(xmm1);
4033 pop_zmm(xmm0);
4034 }
4035 }
4036
4037 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4038 if (reachable(src)) {
4039 Assembler::sqrtsd(dst, as_Address(src));
4040 } else {
4041 lea(rscratch1, src);
4042 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4043 }
4044 }
4045
4046 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4047 if (reachable(src)) {
4048 Assembler::sqrtss(dst, as_Address(src));
4049 } else {
4050 lea(rscratch1, src);
4051 Assembler::sqrtss(dst, Address(rscratch1, 0));
4052 }
4053 }
4054
4055 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4056 if (reachable(src)) {
4057 Assembler::subsd(dst, as_Address(src));
4058 } else {
4059 lea(rscratch1, src);
4060 Assembler::subsd(dst, Address(rscratch1, 0));
4061 }
4062 }
4063
4064 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4065 if (reachable(src)) {
4066 Assembler::subss(dst, as_Address(src));
4067 } else {
4068 lea(rscratch1, src);
4069 Assembler::subss(dst, Address(rscratch1, 0));
4070 }
4071 }
4072
4073 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4074 if (reachable(src)) {
4075 Assembler::ucomisd(dst, as_Address(src));
4076 } else {
4077 lea(rscratch1, src);
4078 Assembler::ucomisd(dst, Address(rscratch1, 0));
4079 }
4080 }
4081
4082 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4083 if (reachable(src)) {
4084 Assembler::ucomiss(dst, as_Address(src));
4085 } else {
4086 lea(rscratch1, src);
4087 Assembler::ucomiss(dst, Address(rscratch1, 0));
4088 }
4089 }
4090
4091 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4092 // Used in sign-bit flipping with aligned address.
4093 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4094 if (reachable(src)) {
4095 Assembler::xorpd(dst, as_Address(src));
4096 } else {
4097 lea(rscratch1, src);
4098 Assembler::xorpd(dst, Address(rscratch1, 0));
4099 }
4100 }
4101
4102 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4103 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4104 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4105 }
4106 else {
4107 Assembler::xorpd(dst, src);
4108 }
4109 }
4110
4111 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4112 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4113 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4114 } else {
4115 Assembler::xorps(dst, src);
4116 }
4117 }
4118
4119 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4120 // Used in sign-bit flipping with aligned address.
4121 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4122 if (reachable(src)) {
4123 Assembler::xorps(dst, as_Address(src));
4124 } else {
4125 lea(rscratch1, src);
4126 Assembler::xorps(dst, Address(rscratch1, 0));
4127 }
4128 }
4129
4130 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4131 // Used in sign-bit flipping with aligned address.
4132 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4133 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4134 if (reachable(src)) {
4135 Assembler::pshufb(dst, as_Address(src));
4136 } else {
4137 lea(rscratch1, src);
4138 Assembler::pshufb(dst, Address(rscratch1, 0));
4139 }
4140 }
4141
4142 // AVX 3-operands instructions
4143
4144 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4145 if (reachable(src)) {
4146 vaddsd(dst, nds, as_Address(src));
4147 } else {
4148 lea(rscratch1, src);
4149 vaddsd(dst, nds, Address(rscratch1, 0));
4150 }
4151 }
4152
4153 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4154 if (reachable(src)) {
4155 vaddss(dst, nds, as_Address(src));
4156 } else {
4157 lea(rscratch1, src);
4158 vaddss(dst, nds, Address(rscratch1, 0));
4159 }
4160 }
4161
4162 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4163 int dst_enc = dst->encoding();
4164 int nds_enc = nds->encoding();
4165 int src_enc = src->encoding();
4166 if ((dst_enc < 16) && (nds_enc < 16)) {
4167 vandps(dst, nds, negate_field, vector_len);
4168 } else if ((src_enc < 16) && (dst_enc < 16)) {
4169 evmovdqul(src, nds, Assembler::AVX_512bit);
4170 vandps(dst, src, negate_field, vector_len);
4171 } else if (src_enc < 16) {
4172 evmovdqul(src, nds, Assembler::AVX_512bit);
4173 vandps(src, src, negate_field, vector_len);
4174 evmovdqul(dst, src, Assembler::AVX_512bit);
4175 } else if (dst_enc < 16) {
4176 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4177 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4178 vandps(dst, xmm0, negate_field, vector_len);
4179 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4180 } else {
4181 if (src_enc != dst_enc) {
4182 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4183 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4184 vandps(xmm0, xmm0, negate_field, vector_len);
4185 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4186 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4187 } else {
4188 push_zmm(xmm0);
4189 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4190 vandps(xmm0, xmm0, negate_field, vector_len);
4191 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4192 pop_zmm(xmm0);
4193 }
4194 }
4195 }
4196
4197 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4198 int dst_enc = dst->encoding();
4199 int nds_enc = nds->encoding();
4200 int src_enc = src->encoding();
4201 if ((dst_enc < 16) && (nds_enc < 16)) {
4202 vandpd(dst, nds, negate_field, vector_len);
4203 } else if ((src_enc < 16) && (dst_enc < 16)) {
4204 evmovdqul(src, nds, Assembler::AVX_512bit);
4205 vandpd(dst, src, negate_field, vector_len);
4206 } else if (src_enc < 16) {
4207 evmovdqul(src, nds, Assembler::AVX_512bit);
4208 vandpd(src, src, negate_field, vector_len);
4209 evmovdqul(dst, src, Assembler::AVX_512bit);
4210 } else if (dst_enc < 16) {
4211 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4212 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4213 vandpd(dst, xmm0, negate_field, vector_len);
4214 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4215 } else {
4216 if (src_enc != dst_enc) {
4217 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4218 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4219 vandpd(xmm0, xmm0, negate_field, vector_len);
4220 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4221 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4222 } else {
4223 push_zmm(xmm0);
4224 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4225 vandpd(xmm0, xmm0, negate_field, vector_len);
4226 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4227 pop_zmm(xmm0);
4228 }
4229 }
4230 }
4231
4232 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4233 int dst_enc = dst->encoding();
4234 int nds_enc = nds->encoding();
4235 int src_enc = src->encoding();
4236 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4237 Assembler::vpaddb(dst, nds, src, vector_len);
4238 } else if ((dst_enc < 16) && (src_enc < 16)) {
4239 Assembler::vpaddb(dst, dst, src, vector_len);
4240 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4241 // use nds as scratch for src
4242 evmovdqul(nds, src, Assembler::AVX_512bit);
4243 Assembler::vpaddb(dst, dst, nds, vector_len);
4244 } else if ((src_enc < 16) && (nds_enc < 16)) {
4245 // use nds as scratch for dst
4246 evmovdqul(nds, dst, Assembler::AVX_512bit);
4247 Assembler::vpaddb(nds, nds, src, vector_len);
4248 evmovdqul(dst, nds, Assembler::AVX_512bit);
4249 } else if (dst_enc < 16) {
4250 // use nds as scatch for xmm0 to hold src
4251 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4252 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4253 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4254 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4255 } else {
4256 // worse case scenario, all regs are in the upper bank
4257 push_zmm(xmm1);
4258 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4259 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4260 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4261 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4262 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4263 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4264 pop_zmm(xmm1);
4265 }
4266 }
4267
4268 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4269 int dst_enc = dst->encoding();
4270 int nds_enc = nds->encoding();
4271 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4272 Assembler::vpaddb(dst, nds, src, vector_len);
4273 } else if (dst_enc < 16) {
4274 Assembler::vpaddb(dst, dst, src, vector_len);
4275 } else if (nds_enc < 16) {
4276 // implies dst_enc in upper bank with src as scratch
4277 evmovdqul(nds, dst, Assembler::AVX_512bit);
4278 Assembler::vpaddb(nds, nds, src, vector_len);
4279 evmovdqul(dst, nds, Assembler::AVX_512bit);
4280 } else {
4281 // worse case scenario, all regs in upper bank
4282 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4283 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4284 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4285 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4286 }
4287 }
4288
4289 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4290 int dst_enc = dst->encoding();
4291 int nds_enc = nds->encoding();
4292 int src_enc = src->encoding();
4293 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4294 Assembler::vpaddw(dst, nds, src, vector_len);
4295 } else if ((dst_enc < 16) && (src_enc < 16)) {
4296 Assembler::vpaddw(dst, dst, src, vector_len);
4297 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4298 // use nds as scratch for src
4299 evmovdqul(nds, src, Assembler::AVX_512bit);
4300 Assembler::vpaddw(dst, dst, nds, vector_len);
4301 } else if ((src_enc < 16) && (nds_enc < 16)) {
4302 // use nds as scratch for dst
4303 evmovdqul(nds, dst, Assembler::AVX_512bit);
4304 Assembler::vpaddw(nds, nds, src, vector_len);
4305 evmovdqul(dst, nds, Assembler::AVX_512bit);
4306 } else if (dst_enc < 16) {
4307 // use nds as scatch for xmm0 to hold src
4308 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4309 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4310 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4311 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4312 } else {
4313 // worse case scenario, all regs are in the upper bank
4314 push_zmm(xmm1);
4315 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4316 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4317 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4318 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4319 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4320 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4321 pop_zmm(xmm1);
4322 }
4323 }
4324
4325 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4326 int dst_enc = dst->encoding();
4327 int nds_enc = nds->encoding();
4328 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4329 Assembler::vpaddw(dst, nds, src, vector_len);
4330 } else if (dst_enc < 16) {
4331 Assembler::vpaddw(dst, dst, src, vector_len);
4332 } else if (nds_enc < 16) {
4333 // implies dst_enc in upper bank with src as scratch
4334 evmovdqul(nds, dst, Assembler::AVX_512bit);
4335 Assembler::vpaddw(nds, nds, src, vector_len);
4336 evmovdqul(dst, nds, Assembler::AVX_512bit);
4337 } else {
4338 // worse case scenario, all regs in upper bank
4339 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4340 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4341 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4342 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4343 }
4344 }
4345
4346 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4347 if (reachable(src)) {
4348 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4349 } else {
4350 lea(rscratch1, src);
4351 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4352 }
4353 }
4354
4355 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4356 int dst_enc = dst->encoding();
4357 int src_enc = src->encoding();
4358 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4359 Assembler::vpbroadcastw(dst, src);
4360 } else if ((dst_enc < 16) && (src_enc < 16)) {
4361 Assembler::vpbroadcastw(dst, src);
4362 } else if (src_enc < 16) {
4363 push_zmm(xmm0);
4364 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4365 Assembler::vpbroadcastw(xmm0, src);
4366 movdqu(dst, xmm0);
4367 pop_zmm(xmm0);
4368 } else if (dst_enc < 16) {
4369 push_zmm(xmm0);
4370 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4371 Assembler::vpbroadcastw(dst, xmm0);
4372 pop_zmm(xmm0);
4373 } else {
4374 push_zmm(xmm0);
4375 push_zmm(xmm1);
4376 movdqu(xmm0, src);
4377 movdqu(xmm1, dst);
4378 Assembler::vpbroadcastw(xmm1, xmm0);
4379 movdqu(dst, xmm1);
4380 pop_zmm(xmm1);
4381 pop_zmm(xmm0);
4382 }
4383 }
4384
4385 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4386 int dst_enc = dst->encoding();
4387 int nds_enc = nds->encoding();
4388 int src_enc = src->encoding();
4389 assert(dst_enc == nds_enc, "");
4390 if ((dst_enc < 16) && (src_enc < 16)) {
4391 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4392 } else if (src_enc < 16) {
4393 push_zmm(xmm0);
4394 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4395 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4396 movdqu(dst, xmm0);
4397 pop_zmm(xmm0);
4398 } else if (dst_enc < 16) {
4399 push_zmm(xmm0);
4400 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4401 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4402 pop_zmm(xmm0);
4403 } else {
4404 push_zmm(xmm0);
4405 push_zmm(xmm1);
4406 movdqu(xmm0, src);
4407 movdqu(xmm1, dst);
4408 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4409 movdqu(dst, xmm1);
4410 pop_zmm(xmm1);
4411 pop_zmm(xmm0);
4412 }
4413 }
4414
4415 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4416 int dst_enc = dst->encoding();
4417 int nds_enc = nds->encoding();
4418 int src_enc = src->encoding();
4419 assert(dst_enc == nds_enc, "");
4420 if ((dst_enc < 16) && (src_enc < 16)) {
4421 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4422 } else if (src_enc < 16) {
4423 push_zmm(xmm0);
4424 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4425 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4426 movdqu(dst, xmm0);
4427 pop_zmm(xmm0);
4428 } else if (dst_enc < 16) {
4429 push_zmm(xmm0);
4430 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4431 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4432 pop_zmm(xmm0);
4433 } else {
4434 push_zmm(xmm0);
4435 push_zmm(xmm1);
4436 movdqu(xmm0, src);
4437 movdqu(xmm1, dst);
4438 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4439 movdqu(dst, xmm1);
4440 pop_zmm(xmm1);
4441 pop_zmm(xmm0);
4442 }
4443 }
4444
4445 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4446 int dst_enc = dst->encoding();
4447 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4448 Assembler::vpmovzxbw(dst, src, vector_len);
4449 } else if (dst_enc < 16) {
4450 Assembler::vpmovzxbw(dst, src, vector_len);
4451 } else {
4452 push_zmm(xmm0);
4453 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4454 Assembler::vpmovzxbw(xmm0, src, vector_len);
4455 movdqu(dst, xmm0);
4456 pop_zmm(xmm0);
4457 }
4458 }
4459
4460 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4461 int src_enc = src->encoding();
4462 if (src_enc < 16) {
4463 Assembler::vpmovmskb(dst, src);
4464 } else {
4465 push_zmm(xmm0);
4466 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4467 Assembler::vpmovmskb(dst, xmm0);
4468 pop_zmm(xmm0);
4469 }
4470 }
4471
4472 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4473 int dst_enc = dst->encoding();
4474 int nds_enc = nds->encoding();
4475 int src_enc = src->encoding();
4476 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4477 Assembler::vpmullw(dst, nds, src, vector_len);
4478 } else if ((dst_enc < 16) && (src_enc < 16)) {
4479 Assembler::vpmullw(dst, dst, src, vector_len);
4480 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4481 // use nds as scratch for src
4482 evmovdqul(nds, src, Assembler::AVX_512bit);
4483 Assembler::vpmullw(dst, dst, nds, vector_len);
4484 } else if ((src_enc < 16) && (nds_enc < 16)) {
4485 // use nds as scratch for dst
4486 evmovdqul(nds, dst, Assembler::AVX_512bit);
4487 Assembler::vpmullw(nds, nds, src, vector_len);
4488 evmovdqul(dst, nds, Assembler::AVX_512bit);
4489 } else if (dst_enc < 16) {
4490 // use nds as scatch for xmm0 to hold src
4491 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4492 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4493 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4494 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4495 } else {
4496 // worse case scenario, all regs are in the upper bank
4497 push_zmm(xmm1);
4498 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4499 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4500 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4501 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4502 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4503 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4504 pop_zmm(xmm1);
4505 }
4506 }
4507
4508 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4509 int dst_enc = dst->encoding();
4510 int nds_enc = nds->encoding();
4511 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4512 Assembler::vpmullw(dst, nds, src, vector_len);
4513 } else if (dst_enc < 16) {
4514 Assembler::vpmullw(dst, dst, src, vector_len);
4515 } else if (nds_enc < 16) {
4516 // implies dst_enc in upper bank with src as scratch
4517 evmovdqul(nds, dst, Assembler::AVX_512bit);
4518 Assembler::vpmullw(nds, nds, src, vector_len);
4519 evmovdqul(dst, nds, Assembler::AVX_512bit);
4520 } else {
4521 // worse case scenario, all regs in upper bank
4522 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4523 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4524 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4525 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4526 }
4527 }
4528
4529 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4530 int dst_enc = dst->encoding();
4531 int nds_enc = nds->encoding();
4532 int src_enc = src->encoding();
4533 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4534 Assembler::vpsubb(dst, nds, src, vector_len);
4535 } else if ((dst_enc < 16) && (src_enc < 16)) {
4536 Assembler::vpsubb(dst, dst, src, vector_len);
4537 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4538 // use nds as scratch for src
4539 evmovdqul(nds, src, Assembler::AVX_512bit);
4540 Assembler::vpsubb(dst, dst, nds, vector_len);
4541 } else if ((src_enc < 16) && (nds_enc < 16)) {
4542 // use nds as scratch for dst
4543 evmovdqul(nds, dst, Assembler::AVX_512bit);
4544 Assembler::vpsubb(nds, nds, src, vector_len);
4545 evmovdqul(dst, nds, Assembler::AVX_512bit);
4546 } else if (dst_enc < 16) {
4547 // use nds as scatch for xmm0 to hold src
4548 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4549 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4550 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4551 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4552 } else {
4553 // worse case scenario, all regs are in the upper bank
4554 push_zmm(xmm1);
4555 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4556 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4557 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4558 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4559 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4560 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4561 pop_zmm(xmm1);
4562 }
4563 }
4564
4565 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4566 int dst_enc = dst->encoding();
4567 int nds_enc = nds->encoding();
4568 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4569 Assembler::vpsubb(dst, nds, src, vector_len);
4570 } else if (dst_enc < 16) {
4571 Assembler::vpsubb(dst, dst, src, vector_len);
4572 } else if (nds_enc < 16) {
4573 // implies dst_enc in upper bank with src as scratch
4574 evmovdqul(nds, dst, Assembler::AVX_512bit);
4575 Assembler::vpsubb(nds, nds, src, vector_len);
4576 evmovdqul(dst, nds, Assembler::AVX_512bit);
4577 } else {
4578 // worse case scenario, all regs in upper bank
4579 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4580 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4581 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4582 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4583 }
4584 }
4585
4586 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4587 int dst_enc = dst->encoding();
4588 int nds_enc = nds->encoding();
4589 int src_enc = src->encoding();
4590 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4591 Assembler::vpsubw(dst, nds, src, vector_len);
4592 } else if ((dst_enc < 16) && (src_enc < 16)) {
4593 Assembler::vpsubw(dst, dst, src, vector_len);
4594 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4595 // use nds as scratch for src
4596 evmovdqul(nds, src, Assembler::AVX_512bit);
4597 Assembler::vpsubw(dst, dst, nds, vector_len);
4598 } else if ((src_enc < 16) && (nds_enc < 16)) {
4599 // use nds as scratch for dst
4600 evmovdqul(nds, dst, Assembler::AVX_512bit);
4601 Assembler::vpsubw(nds, nds, src, vector_len);
4602 evmovdqul(dst, nds, Assembler::AVX_512bit);
4603 } else if (dst_enc < 16) {
4604 // use nds as scatch for xmm0 to hold src
4605 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4606 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4607 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4608 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4609 } else {
4610 // worse case scenario, all regs are in the upper bank
4611 push_zmm(xmm1);
4612 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4613 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4614 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4615 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4616 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4617 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4618 pop_zmm(xmm1);
4619 }
4620 }
4621
4622 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4623 int dst_enc = dst->encoding();
4624 int nds_enc = nds->encoding();
4625 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4626 Assembler::vpsubw(dst, nds, src, vector_len);
4627 } else if (dst_enc < 16) {
4628 Assembler::vpsubw(dst, dst, src, vector_len);
4629 } else if (nds_enc < 16) {
4630 // implies dst_enc in upper bank with src as scratch
4631 evmovdqul(nds, dst, Assembler::AVX_512bit);
4632 Assembler::vpsubw(nds, nds, src, vector_len);
4633 evmovdqul(dst, nds, Assembler::AVX_512bit);
4634 } else {
4635 // worse case scenario, all regs in upper bank
4636 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4637 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4638 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4639 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4640 }
4641 }
4642
4643 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4644 int dst_enc = dst->encoding();
4645 int nds_enc = nds->encoding();
4646 int shift_enc = shift->encoding();
4647 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4648 Assembler::vpsraw(dst, nds, shift, vector_len);
4649 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4650 Assembler::vpsraw(dst, dst, shift, vector_len);
4651 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4652 // use nds_enc as scratch with shift
4653 evmovdqul(nds, shift, Assembler::AVX_512bit);
4654 Assembler::vpsraw(dst, dst, nds, vector_len);
4655 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4656 // use nds as scratch with dst
4657 evmovdqul(nds, dst, Assembler::AVX_512bit);
4658 Assembler::vpsraw(nds, nds, shift, vector_len);
4659 evmovdqul(dst, nds, Assembler::AVX_512bit);
4660 } else if (dst_enc < 16) {
4661 // use nds to save a copy of xmm0 and hold shift
4662 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4663 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4664 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4665 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4666 } else if (nds_enc < 16) {
4667 // use nds as dest as temps
4668 evmovdqul(nds, dst, Assembler::AVX_512bit);
4669 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4670 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4671 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4672 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4673 evmovdqul(dst, nds, Assembler::AVX_512bit);
4674 } else {
4675 // worse case scenario, all regs are in the upper bank
4676 push_zmm(xmm1);
4677 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4678 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4679 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4680 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4681 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4682 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4683 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4684 pop_zmm(xmm1);
4685 }
4686 }
4687
4688 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4689 int dst_enc = dst->encoding();
4690 int nds_enc = nds->encoding();
4691 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4692 Assembler::vpsraw(dst, nds, shift, vector_len);
4693 } else if (dst_enc < 16) {
4694 Assembler::vpsraw(dst, dst, shift, vector_len);
4695 } else if (nds_enc < 16) {
4696 // use nds as scratch
4697 evmovdqul(nds, dst, Assembler::AVX_512bit);
4698 Assembler::vpsraw(nds, nds, shift, vector_len);
4699 evmovdqul(dst, nds, Assembler::AVX_512bit);
4700 } else {
4701 // use nds as scratch for xmm0
4702 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4703 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4704 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4705 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4706 }
4707 }
4708
4709 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4710 int dst_enc = dst->encoding();
4711 int nds_enc = nds->encoding();
4712 int shift_enc = shift->encoding();
4713 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4714 Assembler::vpsrlw(dst, nds, shift, vector_len);
4715 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4716 Assembler::vpsrlw(dst, dst, shift, vector_len);
4717 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4718 // use nds_enc as scratch with shift
4719 evmovdqul(nds, shift, Assembler::AVX_512bit);
4720 Assembler::vpsrlw(dst, dst, nds, vector_len);
4721 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4722 // use nds as scratch with dst
4723 evmovdqul(nds, dst, Assembler::AVX_512bit);
4724 Assembler::vpsrlw(nds, nds, shift, vector_len);
4725 evmovdqul(dst, nds, Assembler::AVX_512bit);
4726 } else if (dst_enc < 16) {
4727 // use nds to save a copy of xmm0 and hold shift
4728 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4729 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4730 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4731 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4732 } else if (nds_enc < 16) {
4733 // use nds as dest as temps
4734 evmovdqul(nds, dst, Assembler::AVX_512bit);
4735 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4736 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4737 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4738 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4739 evmovdqul(dst, nds, Assembler::AVX_512bit);
4740 } else {
4741 // worse case scenario, all regs are in the upper bank
4742 push_zmm(xmm1);
4743 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4744 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4745 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4746 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4747 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4748 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4749 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4750 pop_zmm(xmm1);
4751 }
4752 }
4753
4754 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4755 int dst_enc = dst->encoding();
4756 int nds_enc = nds->encoding();
4757 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4758 Assembler::vpsrlw(dst, nds, shift, vector_len);
4759 } else if (dst_enc < 16) {
4760 Assembler::vpsrlw(dst, dst, shift, vector_len);
4761 } else if (nds_enc < 16) {
4762 // use nds as scratch
4763 evmovdqul(nds, dst, Assembler::AVX_512bit);
4764 Assembler::vpsrlw(nds, nds, shift, vector_len);
4765 evmovdqul(dst, nds, Assembler::AVX_512bit);
4766 } else {
4767 // use nds as scratch for xmm0
4768 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4769 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4770 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4771 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4772 }
4773 }
4774
4775 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4776 int dst_enc = dst->encoding();
4777 int nds_enc = nds->encoding();
4778 int shift_enc = shift->encoding();
4779 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4780 Assembler::vpsllw(dst, nds, shift, vector_len);
4781 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4782 Assembler::vpsllw(dst, dst, shift, vector_len);
4783 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4784 // use nds_enc as scratch with shift
4785 evmovdqul(nds, shift, Assembler::AVX_512bit);
4786 Assembler::vpsllw(dst, dst, nds, vector_len);
4787 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4788 // use nds as scratch with dst
4789 evmovdqul(nds, dst, Assembler::AVX_512bit);
4790 Assembler::vpsllw(nds, nds, shift, vector_len);
4791 evmovdqul(dst, nds, Assembler::AVX_512bit);
4792 } else if (dst_enc < 16) {
4793 // use nds to save a copy of xmm0 and hold shift
4794 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4795 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4796 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4797 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4798 } else if (nds_enc < 16) {
4799 // use nds as dest as temps
4800 evmovdqul(nds, dst, Assembler::AVX_512bit);
4801 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4802 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4803 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4804 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4805 evmovdqul(dst, nds, Assembler::AVX_512bit);
4806 } else {
4807 // worse case scenario, all regs are in the upper bank
4808 push_zmm(xmm1);
4809 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4810 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4811 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4812 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4813 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4814 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4815 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4816 pop_zmm(xmm1);
4817 }
4818 }
4819
4820 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4821 int dst_enc = dst->encoding();
4822 int nds_enc = nds->encoding();
4823 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4824 Assembler::vpsllw(dst, nds, shift, vector_len);
4825 } else if (dst_enc < 16) {
4826 Assembler::vpsllw(dst, dst, shift, vector_len);
4827 } else if (nds_enc < 16) {
4828 // use nds as scratch
4829 evmovdqul(nds, dst, Assembler::AVX_512bit);
4830 Assembler::vpsllw(nds, nds, shift, vector_len);
4831 evmovdqul(dst, nds, Assembler::AVX_512bit);
4832 } else {
4833 // use nds as scratch for xmm0
4834 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4835 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4836 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4837 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4838 }
4839 }
4840
4841 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4842 int dst_enc = dst->encoding();
4843 int src_enc = src->encoding();
4844 if ((dst_enc < 16) && (src_enc < 16)) {
4845 Assembler::vptest(dst, src);
4846 } else if (src_enc < 16) {
4847 push_zmm(xmm0);
4848 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4849 Assembler::vptest(xmm0, src);
4850 pop_zmm(xmm0);
4851 } else if (dst_enc < 16) {
4852 push_zmm(xmm0);
4853 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4854 Assembler::vptest(dst, xmm0);
4855 pop_zmm(xmm0);
4856 } else {
4857 push_zmm(xmm0);
4858 push_zmm(xmm1);
4859 movdqu(xmm0, src);
4860 movdqu(xmm1, dst);
4861 Assembler::vptest(xmm1, xmm0);
4862 pop_zmm(xmm1);
4863 pop_zmm(xmm0);
4864 }
4865 }
4866
4867 // This instruction exists within macros, ergo we cannot control its input
4868 // when emitted through those patterns.
4869 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4870 if (VM_Version::supports_avx512nobw()) {
4871 int dst_enc = dst->encoding();
4872 int src_enc = src->encoding();
4873 if (dst_enc == src_enc) {
4874 if (dst_enc < 16) {
4875 Assembler::punpcklbw(dst, src);
4876 } else {
4877 push_zmm(xmm0);
4878 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4879 Assembler::punpcklbw(xmm0, xmm0);
4880 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4881 pop_zmm(xmm0);
4882 }
4883 } else {
4884 if ((src_enc < 16) && (dst_enc < 16)) {
4885 Assembler::punpcklbw(dst, src);
4886 } else if (src_enc < 16) {
4887 push_zmm(xmm0);
4888 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4889 Assembler::punpcklbw(xmm0, src);
4890 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4891 pop_zmm(xmm0);
4892 } else if (dst_enc < 16) {
4893 push_zmm(xmm0);
4894 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4895 Assembler::punpcklbw(dst, xmm0);
4896 pop_zmm(xmm0);
4897 } else {
4898 push_zmm(xmm0);
4899 push_zmm(xmm1);
4900 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4901 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4902 Assembler::punpcklbw(xmm0, xmm1);
4903 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4904 pop_zmm(xmm1);
4905 pop_zmm(xmm0);
4906 }
4907 }
4908 } else {
4909 Assembler::punpcklbw(dst, src);
4910 }
4911 }
4912
4913 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
4914 if (VM_Version::supports_avx512vl()) {
4915 Assembler::pshufd(dst, src, mode);
4916 } else {
4917 int dst_enc = dst->encoding();
4918 if (dst_enc < 16) {
4919 Assembler::pshufd(dst, src, mode);
4920 } else {
4921 push_zmm(xmm0);
4922 Assembler::pshufd(xmm0, src, mode);
4923 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4924 pop_zmm(xmm0);
4925 }
4926 }
4927 }
4928
4929 // This instruction exists within macros, ergo we cannot control its input
4930 // when emitted through those patterns.
4931 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4932 if (VM_Version::supports_avx512nobw()) {
4933 int dst_enc = dst->encoding();
4934 int src_enc = src->encoding();
4935 if (dst_enc == src_enc) {
4936 if (dst_enc < 16) {
4937 Assembler::pshuflw(dst, src, mode);
4938 } else {
4939 push_zmm(xmm0);
4940 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4941 Assembler::pshuflw(xmm0, xmm0, mode);
4942 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4943 pop_zmm(xmm0);
4944 }
4945 } else {
4946 if ((src_enc < 16) && (dst_enc < 16)) {
4947 Assembler::pshuflw(dst, src, mode);
4948 } else if (src_enc < 16) {
4949 push_zmm(xmm0);
4950 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4951 Assembler::pshuflw(xmm0, src, mode);
4952 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4953 pop_zmm(xmm0);
4954 } else if (dst_enc < 16) {
4955 push_zmm(xmm0);
4956 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4957 Assembler::pshuflw(dst, xmm0, mode);
4958 pop_zmm(xmm0);
4959 } else {
4960 push_zmm(xmm0);
4961 push_zmm(xmm1);
4962 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4963 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4964 Assembler::pshuflw(xmm0, xmm1, mode);
4965 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4966 pop_zmm(xmm1);
4967 pop_zmm(xmm0);
4968 }
4969 }
4970 } else {
4971 Assembler::pshuflw(dst, src, mode);
4972 }
4973 }
4974
4975 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4976 if (reachable(src)) {
4977 vandpd(dst, nds, as_Address(src), vector_len);
4978 } else {
4979 lea(rscratch1, src);
4980 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4981 }
4982 }
4983
4984 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4985 if (reachable(src)) {
4986 vandps(dst, nds, as_Address(src), vector_len);
4987 } else {
4988 lea(rscratch1, src);
4989 vandps(dst, nds, Address(rscratch1, 0), vector_len);
4990 }
4991 }
4992
4993 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4994 if (reachable(src)) {
4995 vdivsd(dst, nds, as_Address(src));
4996 } else {
4997 lea(rscratch1, src);
4998 vdivsd(dst, nds, Address(rscratch1, 0));
4999 }
5000 }
5001
5002 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5003 if (reachable(src)) {
5004 vdivss(dst, nds, as_Address(src));
5005 } else {
5006 lea(rscratch1, src);
5007 vdivss(dst, nds, Address(rscratch1, 0));
5008 }
5009 }
5010
5011 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5012 if (reachable(src)) {
5013 vmulsd(dst, nds, as_Address(src));
5014 } else {
5015 lea(rscratch1, src);
5016 vmulsd(dst, nds, Address(rscratch1, 0));
5017 }
5018 }
5019
5020 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5021 if (reachable(src)) {
5022 vmulss(dst, nds, as_Address(src));
5023 } else {
5024 lea(rscratch1, src);
5025 vmulss(dst, nds, Address(rscratch1, 0));
5026 }
5027 }
5028
5029 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5030 if (reachable(src)) {
5031 vsubsd(dst, nds, as_Address(src));
5032 } else {
5033 lea(rscratch1, src);
5034 vsubsd(dst, nds, Address(rscratch1, 0));
5035 }
5036 }
5037
5038 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5039 if (reachable(src)) {
5040 vsubss(dst, nds, as_Address(src));
5041 } else {
5042 lea(rscratch1, src);
5043 vsubss(dst, nds, Address(rscratch1, 0));
5044 }
5045 }
5046
5047 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5048 int nds_enc = nds->encoding();
5049 int dst_enc = dst->encoding();
5050 bool dst_upper_bank = (dst_enc > 15);
5051 bool nds_upper_bank = (nds_enc > 15);
5052 if (VM_Version::supports_avx512novl() &&
5053 (nds_upper_bank || dst_upper_bank)) {
5054 if (dst_upper_bank) {
5055 push_zmm(xmm0);
5056 movflt(xmm0, nds);
5057 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5058 movflt(dst, xmm0);
5059 pop_zmm(xmm0);
5060 } else {
5061 movflt(dst, nds);
5062 vxorps(dst, dst, src, Assembler::AVX_128bit);
5063 }
5064 } else {
5065 vxorps(dst, nds, src, Assembler::AVX_128bit);
5066 }
5067 }
5068
5069 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5070 int nds_enc = nds->encoding();
5071 int dst_enc = dst->encoding();
5072 bool dst_upper_bank = (dst_enc > 15);
5073 bool nds_upper_bank = (nds_enc > 15);
5074 if (VM_Version::supports_avx512novl() &&
5075 (nds_upper_bank || dst_upper_bank)) {
5076 if (dst_upper_bank) {
5077 push_zmm(xmm0);
5078 movdbl(xmm0, nds);
5079 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5080 movdbl(dst, xmm0);
5081 pop_zmm(xmm0);
5082 } else {
5083 movdbl(dst, nds);
5084 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5085 }
5086 } else {
5087 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5088 }
5089 }
5090
5091 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5092 if (reachable(src)) {
5093 vxorpd(dst, nds, as_Address(src), vector_len);
5094 } else {
5095 lea(rscratch1, src);
5096 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5097 }
5098 }
5099
5100 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5101 if (reachable(src)) {
5102 vxorps(dst, nds, as_Address(src), vector_len);
5103 } else {
5104 lea(rscratch1, src);
5105 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5106 }
5107 }
5108
5109 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5110 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5111 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5112 // The inverted mask is sign-extended
5113 andptr(possibly_jweak, inverted_jweak_mask);
5114 }
5115
5116 void MacroAssembler::resolve_jobject(Register value,
5117 Register thread,
5118 Register tmp) {
5119 assert_different_registers(value, thread, tmp);
5120 Label done, not_weak;
5121 testptr(value, value);
5122 jcc(Assembler::zero, done); // Use NULL as-is.
5123 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5124 jcc(Assembler::zero, not_weak);
5125 // Resolve jweak.
5126 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5127 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
5128 verify_oop(value);
5129 jmp(done);
5130 bind(not_weak);
5131 // Resolve (untagged) jobject.
5132 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
5133 verify_oop(value);
5134 bind(done);
5135 }
5136
5137 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5138 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5139 }
5140
5141 // Force generation of a 4 byte immediate value even if it fits into 8bit
5142 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5143 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5144 }
5145
5146 void MacroAssembler::subptr(Register dst, Register src) {
5147 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5148 }
5149
5150 // C++ bool manipulation
5151 void MacroAssembler::testbool(Register dst) {
5152 if(sizeof(bool) == 1)
5153 testb(dst, 0xff);
5154 else if(sizeof(bool) == 2) {
5155 // testw implementation needed for two byte bools
5156 ShouldNotReachHere();
5157 } else if(sizeof(bool) == 4)
5158 testl(dst, dst);
5159 else
5160 // unsupported
5161 ShouldNotReachHere();
5162 }
5163
5164 void MacroAssembler::testptr(Register dst, Register src) {
5165 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5166 }
5167
5168 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5169 void MacroAssembler::tlab_allocate(Register thread, Register obj,
5170 Register var_size_in_bytes,
5171 int con_size_in_bytes,
5172 Register t1,
5173 Register t2,
5174 Label& slow_case) {
5175 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5176 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5177 }
5178
5179 // Defines obj, preserves var_size_in_bytes
5180 void MacroAssembler::eden_allocate(Register thread, Register obj,
5181 Register var_size_in_bytes,
5182 int con_size_in_bytes,
5183 Register t1,
5184 Label& slow_case) {
5185 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5186 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
5187 }
5188
5189 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5190 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5191 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5192 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5193 Label done;
5194
5195 testptr(length_in_bytes, length_in_bytes);
5196 jcc(Assembler::zero, done);
5197
5198 // initialize topmost word, divide index by 2, check if odd and test if zero
5199 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5200 #ifdef ASSERT
5201 {
5202 Label L;
5203 testptr(length_in_bytes, BytesPerWord - 1);
5204 jcc(Assembler::zero, L);
5205 stop("length must be a multiple of BytesPerWord");
5206 bind(L);
5207 }
5208 #endif
5209 Register index = length_in_bytes;
5210 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5211 if (UseIncDec) {
5212 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5213 } else {
5214 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5215 shrptr(index, 1);
5216 }
5217 #ifndef _LP64
5218 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5219 {
5220 Label even;
5221 // note: if index was a multiple of 8, then it cannot
5222 // be 0 now otherwise it must have been 0 before
5223 // => if it is even, we don't need to check for 0 again
5224 jcc(Assembler::carryClear, even);
5225 // clear topmost word (no jump would be needed if conditional assignment worked here)
5226 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5227 // index could be 0 now, must check again
5228 jcc(Assembler::zero, done);
5229 bind(even);
5230 }
5231 #endif // !_LP64
5232 // initialize remaining object fields: index is a multiple of 2 now
5233 {
5234 Label loop;
5235 bind(loop);
5236 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5237 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5238 decrement(index);
5239 jcc(Assembler::notZero, loop);
5240 }
5241
5242 bind(done);
5243 }
5244
5245 // Look up the method for a megamorphic invokeinterface call.
5246 // The target method is determined by <intf_klass, itable_index>.
5247 // The receiver klass is in recv_klass.
5248 // On success, the result will be in method_result, and execution falls through.
5249 // On failure, execution transfers to the given label.
5250 void MacroAssembler::lookup_interface_method(Register recv_klass,
5251 Register intf_klass,
5252 RegisterOrConstant itable_index,
5253 Register method_result,
5254 Register scan_temp,
5255 Label& L_no_such_interface,
5256 bool return_method) {
5257 assert_different_registers(recv_klass, intf_klass, scan_temp);
5258 assert_different_registers(method_result, intf_klass, scan_temp);
5259 assert(recv_klass != method_result || !return_method,
5260 "recv_klass can be destroyed when method isn't needed");
5261
5262 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5263 "caller must use same register for non-constant itable index as for method");
5264
5265 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5266 int vtable_base = in_bytes(Klass::vtable_start_offset());
5267 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5268 int scan_step = itableOffsetEntry::size() * wordSize;
5269 int vte_size = vtableEntry::size_in_bytes();
5270 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5271 assert(vte_size == wordSize, "else adjust times_vte_scale");
5272
5273 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5274
5275 // %%% Could store the aligned, prescaled offset in the klassoop.
5276 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5277
5278 if (return_method) {
5279 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5280 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5281 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5282 }
5283
5284 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5285 // if (scan->interface() == intf) {
5286 // result = (klass + scan->offset() + itable_index);
5287 // }
5288 // }
5289 Label search, found_method;
5290
5291 for (int peel = 1; peel >= 0; peel--) {
5292 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5293 cmpptr(intf_klass, method_result);
5294
5295 if (peel) {
5296 jccb(Assembler::equal, found_method);
5297 } else {
5298 jccb(Assembler::notEqual, search);
5299 // (invert the test to fall through to found_method...)
5300 }
5301
5302 if (!peel) break;
5303
5304 bind(search);
5305
5306 // Check that the previous entry is non-null. A null entry means that
5307 // the receiver class doesn't implement the interface, and wasn't the
5308 // same as when the caller was compiled.
5309 testptr(method_result, method_result);
5310 jcc(Assembler::zero, L_no_such_interface);
5311 addptr(scan_temp, scan_step);
5312 }
5313
5314 bind(found_method);
5315
5316 if (return_method) {
5317 // Got a hit.
5318 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5319 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5320 }
5321 }
5322
5323
5324 // virtual method calling
5325 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5326 RegisterOrConstant vtable_index,
5327 Register method_result) {
5328 const int base = in_bytes(Klass::vtable_start_offset());
5329 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5330 Address vtable_entry_addr(recv_klass,
5331 vtable_index, Address::times_ptr,
5332 base + vtableEntry::method_offset_in_bytes());
5333 movptr(method_result, vtable_entry_addr);
5334 }
5335
5336
5337 void MacroAssembler::check_klass_subtype(Register sub_klass,
5338 Register super_klass,
5339 Register temp_reg,
5340 Label& L_success) {
5341 Label L_failure;
5342 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5343 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5344 bind(L_failure);
5345 }
5346
5347
5348 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5349 Register super_klass,
5350 Register temp_reg,
5351 Label* L_success,
5352 Label* L_failure,
5353 Label* L_slow_path,
5354 RegisterOrConstant super_check_offset) {
5355 assert_different_registers(sub_klass, super_klass, temp_reg);
5356 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5357 if (super_check_offset.is_register()) {
5358 assert_different_registers(sub_klass, super_klass,
5359 super_check_offset.as_register());
5360 } else if (must_load_sco) {
5361 assert(temp_reg != noreg, "supply either a temp or a register offset");
5362 }
5363
5364 Label L_fallthrough;
5365 int label_nulls = 0;
5366 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5367 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5368 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5369 assert(label_nulls <= 1, "at most one NULL in the batch");
5370
5371 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5372 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5373 Address super_check_offset_addr(super_klass, sco_offset);
5374
5375 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5376 // range of a jccb. If this routine grows larger, reconsider at
5377 // least some of these.
5378 #define local_jcc(assembler_cond, label) \
5379 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5380 else jcc( assembler_cond, label) /*omit semi*/
5381
5382 // Hacked jmp, which may only be used just before L_fallthrough.
5383 #define final_jmp(label) \
5384 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5385 else jmp(label) /*omit semi*/
5386
5387 // If the pointers are equal, we are done (e.g., String[] elements).
5388 // This self-check enables sharing of secondary supertype arrays among
5389 // non-primary types such as array-of-interface. Otherwise, each such
5390 // type would need its own customized SSA.
5391 // We move this check to the front of the fast path because many
5392 // type checks are in fact trivially successful in this manner,
5393 // so we get a nicely predicted branch right at the start of the check.
5394 cmpptr(sub_klass, super_klass);
5395 local_jcc(Assembler::equal, *L_success);
5396
5397 // Check the supertype display:
5398 if (must_load_sco) {
5399 // Positive movl does right thing on LP64.
5400 movl(temp_reg, super_check_offset_addr);
5401 super_check_offset = RegisterOrConstant(temp_reg);
5402 }
5403 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5404 cmpptr(super_klass, super_check_addr); // load displayed supertype
5405
5406 // This check has worked decisively for primary supers.
5407 // Secondary supers are sought in the super_cache ('super_cache_addr').
5408 // (Secondary supers are interfaces and very deeply nested subtypes.)
5409 // This works in the same check above because of a tricky aliasing
5410 // between the super_cache and the primary super display elements.
5411 // (The 'super_check_addr' can address either, as the case requires.)
5412 // Note that the cache is updated below if it does not help us find
5413 // what we need immediately.
5414 // So if it was a primary super, we can just fail immediately.
5415 // Otherwise, it's the slow path for us (no success at this point).
5416
5417 if (super_check_offset.is_register()) {
5418 local_jcc(Assembler::equal, *L_success);
5419 cmpl(super_check_offset.as_register(), sc_offset);
5420 if (L_failure == &L_fallthrough) {
5421 local_jcc(Assembler::equal, *L_slow_path);
5422 } else {
5423 local_jcc(Assembler::notEqual, *L_failure);
5424 final_jmp(*L_slow_path);
5425 }
5426 } else if (super_check_offset.as_constant() == sc_offset) {
5427 // Need a slow path; fast failure is impossible.
5428 if (L_slow_path == &L_fallthrough) {
5429 local_jcc(Assembler::equal, *L_success);
5430 } else {
5431 local_jcc(Assembler::notEqual, *L_slow_path);
5432 final_jmp(*L_success);
5433 }
5434 } else {
5435 // No slow path; it's a fast decision.
5436 if (L_failure == &L_fallthrough) {
5437 local_jcc(Assembler::equal, *L_success);
5438 } else {
5439 local_jcc(Assembler::notEqual, *L_failure);
5440 final_jmp(*L_success);
5441 }
5442 }
5443
5444 bind(L_fallthrough);
5445
5446 #undef local_jcc
5447 #undef final_jmp
5448 }
5449
5450
5451 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5452 Register super_klass,
5453 Register temp_reg,
5454 Register temp2_reg,
5455 Label* L_success,
5456 Label* L_failure,
5457 bool set_cond_codes) {
5458 assert_different_registers(sub_klass, super_klass, temp_reg);
5459 if (temp2_reg != noreg)
5460 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5461 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5462
5463 Label L_fallthrough;
5464 int label_nulls = 0;
5465 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5466 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5467 assert(label_nulls <= 1, "at most one NULL in the batch");
5468
5469 // a couple of useful fields in sub_klass:
5470 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5471 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5472 Address secondary_supers_addr(sub_klass, ss_offset);
5473 Address super_cache_addr( sub_klass, sc_offset);
5474
5475 // Do a linear scan of the secondary super-klass chain.
5476 // This code is rarely used, so simplicity is a virtue here.
5477 // The repne_scan instruction uses fixed registers, which we must spill.
5478 // Don't worry too much about pre-existing connections with the input regs.
5479
5480 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5481 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5482
5483 // Get super_klass value into rax (even if it was in rdi or rcx).
5484 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5485 if (super_klass != rax || UseCompressedOops) {
5486 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5487 mov(rax, super_klass);
5488 }
5489 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5490 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5491
5492 #ifndef PRODUCT
5493 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5494 ExternalAddress pst_counter_addr((address) pst_counter);
5495 NOT_LP64( incrementl(pst_counter_addr) );
5496 LP64_ONLY( lea(rcx, pst_counter_addr) );
5497 LP64_ONLY( incrementl(Address(rcx, 0)) );
5498 #endif //PRODUCT
5499
5500 // We will consult the secondary-super array.
5501 movptr(rdi, secondary_supers_addr);
5502 // Load the array length. (Positive movl does right thing on LP64.)
5503 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5504 // Skip to start of data.
5505 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5506
5507 // Scan RCX words at [RDI] for an occurrence of RAX.
5508 // Set NZ/Z based on last compare.
5509 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5510 // not change flags (only scas instruction which is repeated sets flags).
5511 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5512
5513 testptr(rax,rax); // Set Z = 0
5514 repne_scan();
5515
5516 // Unspill the temp. registers:
5517 if (pushed_rdi) pop(rdi);
5518 if (pushed_rcx) pop(rcx);
5519 if (pushed_rax) pop(rax);
5520
5521 if (set_cond_codes) {
5522 // Special hack for the AD files: rdi is guaranteed non-zero.
5523 assert(!pushed_rdi, "rdi must be left non-NULL");
5524 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5525 }
5526
5527 if (L_failure == &L_fallthrough)
5528 jccb(Assembler::notEqual, *L_failure);
5529 else jcc(Assembler::notEqual, *L_failure);
5530
5531 // Success. Cache the super we found and proceed in triumph.
5532 movptr(super_cache_addr, super_klass);
5533
5534 if (L_success != &L_fallthrough) {
5535 jmp(*L_success);
5536 }
5537
5538 #undef IS_A_TEMP
5539
5540 bind(L_fallthrough);
5541 }
5542
5543
5544 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5545 if (VM_Version::supports_cmov()) {
5546 cmovl(cc, dst, src);
5547 } else {
5548 Label L;
5549 jccb(negate_condition(cc), L);
5550 movl(dst, src);
5551 bind(L);
5552 }
5553 }
5554
5555 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5556 if (VM_Version::supports_cmov()) {
5557 cmovl(cc, dst, src);
5558 } else {
5559 Label L;
5560 jccb(negate_condition(cc), L);
5561 movl(dst, src);
5562 bind(L);
5563 }
5564 }
5565
5566 void MacroAssembler::verify_oop(Register reg, const char* s) {
5567 if (!VerifyOops) return;
5568
5569 // Pass register number to verify_oop_subroutine
5570 const char* b = NULL;
5571 {
5572 ResourceMark rm;
5573 stringStream ss;
5574 ss.print("verify_oop: %s: %s", reg->name(), s);
5575 b = code_string(ss.as_string());
5576 }
5577 BLOCK_COMMENT("verify_oop {");
5578 #ifdef _LP64
5579 push(rscratch1); // save r10, trashed by movptr()
5580 #endif
5581 push(rax); // save rax,
5582 push(reg); // pass register argument
5583 ExternalAddress buffer((address) b);
5584 // avoid using pushptr, as it modifies scratch registers
5585 // and our contract is not to modify anything
5586 movptr(rax, buffer.addr());
5587 push(rax);
5588 // call indirectly to solve generation ordering problem
5589 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5590 call(rax);
5591 // Caller pops the arguments (oop, message) and restores rax, r10
5592 BLOCK_COMMENT("} verify_oop");
5593 }
5594
5595
5596 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5597 Register tmp,
5598 int offset) {
5599 intptr_t value = *delayed_value_addr;
5600 if (value != 0)
5601 return RegisterOrConstant(value + offset);
5602
5603 // load indirectly to solve generation ordering problem
5604 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5605
5606 #ifdef ASSERT
5607 { Label L;
5608 testptr(tmp, tmp);
5609 if (WizardMode) {
5610 const char* buf = NULL;
5611 {
5612 ResourceMark rm;
5613 stringStream ss;
5614 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5615 buf = code_string(ss.as_string());
5616 }
5617 jcc(Assembler::notZero, L);
5618 STOP(buf);
5619 } else {
5620 jccb(Assembler::notZero, L);
5621 hlt();
5622 }
5623 bind(L);
5624 }
5625 #endif
5626
5627 if (offset != 0)
5628 addptr(tmp, offset);
5629
5630 return RegisterOrConstant(tmp);
5631 }
5632
5633
5634 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5635 int extra_slot_offset) {
5636 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5637 int stackElementSize = Interpreter::stackElementSize;
5638 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5639 #ifdef ASSERT
5640 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5641 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5642 #endif
5643 Register scale_reg = noreg;
5644 Address::ScaleFactor scale_factor = Address::no_scale;
5645 if (arg_slot.is_constant()) {
5646 offset += arg_slot.as_constant() * stackElementSize;
5647 } else {
5648 scale_reg = arg_slot.as_register();
5649 scale_factor = Address::times(stackElementSize);
5650 }
5651 offset += wordSize; // return PC is on stack
5652 return Address(rsp, scale_reg, scale_factor, offset);
5653 }
5654
5655
5656 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5657 if (!VerifyOops) return;
5658
5659 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5660 // Pass register number to verify_oop_subroutine
5661 const char* b = NULL;
5662 {
5663 ResourceMark rm;
5664 stringStream ss;
5665 ss.print("verify_oop_addr: %s", s);
5666 b = code_string(ss.as_string());
5667 }
5668 #ifdef _LP64
5669 push(rscratch1); // save r10, trashed by movptr()
5670 #endif
5671 push(rax); // save rax,
5672 // addr may contain rsp so we will have to adjust it based on the push
5673 // we just did (and on 64 bit we do two pushes)
5674 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5675 // stores rax into addr which is backwards of what was intended.
5676 if (addr.uses(rsp)) {
5677 lea(rax, addr);
5678 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5679 } else {
5680 pushptr(addr);
5681 }
5682
5683 ExternalAddress buffer((address) b);
5684 // pass msg argument
5685 // avoid using pushptr, as it modifies scratch registers
5686 // and our contract is not to modify anything
5687 movptr(rax, buffer.addr());
5688 push(rax);
5689
5690 // call indirectly to solve generation ordering problem
5691 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5692 call(rax);
5693 // Caller pops the arguments (addr, message) and restores rax, r10.
5694 }
5695
5696 void MacroAssembler::verify_tlab() {
5697 #ifdef ASSERT
5698 if (UseTLAB && VerifyOops) {
5699 Label next, ok;
5700 Register t1 = rsi;
5701 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5702
5703 push(t1);
5704 NOT_LP64(push(thread_reg));
5705 NOT_LP64(get_thread(thread_reg));
5706
5707 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5708 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5709 jcc(Assembler::aboveEqual, next);
5710 STOP("assert(top >= start)");
5711 should_not_reach_here();
5712
5713 bind(next);
5714 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5715 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5716 jcc(Assembler::aboveEqual, ok);
5717 STOP("assert(top <= end)");
5718 should_not_reach_here();
5719
5720 bind(ok);
5721 NOT_LP64(pop(thread_reg));
5722 pop(t1);
5723 }
5724 #endif
5725 }
5726
5727 class ControlWord {
5728 public:
5729 int32_t _value;
5730
5731 int rounding_control() const { return (_value >> 10) & 3 ; }
5732 int precision_control() const { return (_value >> 8) & 3 ; }
5733 bool precision() const { return ((_value >> 5) & 1) != 0; }
5734 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5735 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5736 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5737 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5738 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5739
5740 void print() const {
5741 // rounding control
5742 const char* rc;
5743 switch (rounding_control()) {
5744 case 0: rc = "round near"; break;
5745 case 1: rc = "round down"; break;
5746 case 2: rc = "round up "; break;
5747 case 3: rc = "chop "; break;
5748 };
5749 // precision control
5750 const char* pc;
5751 switch (precision_control()) {
5752 case 0: pc = "24 bits "; break;
5753 case 1: pc = "reserved"; break;
5754 case 2: pc = "53 bits "; break;
5755 case 3: pc = "64 bits "; break;
5756 };
5757 // flags
5758 char f[9];
5759 f[0] = ' ';
5760 f[1] = ' ';
5761 f[2] = (precision ()) ? 'P' : 'p';
5762 f[3] = (underflow ()) ? 'U' : 'u';
5763 f[4] = (overflow ()) ? 'O' : 'o';
5764 f[5] = (zero_divide ()) ? 'Z' : 'z';
5765 f[6] = (denormalized()) ? 'D' : 'd';
5766 f[7] = (invalid ()) ? 'I' : 'i';
5767 f[8] = '\x0';
5768 // output
5769 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5770 }
5771
5772 };
5773
5774 class StatusWord {
5775 public:
5776 int32_t _value;
5777
5778 bool busy() const { return ((_value >> 15) & 1) != 0; }
5779 bool C3() const { return ((_value >> 14) & 1) != 0; }
5780 bool C2() const { return ((_value >> 10) & 1) != 0; }
5781 bool C1() const { return ((_value >> 9) & 1) != 0; }
5782 bool C0() const { return ((_value >> 8) & 1) != 0; }
5783 int top() const { return (_value >> 11) & 7 ; }
5784 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5785 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5786 bool precision() const { return ((_value >> 5) & 1) != 0; }
5787 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5788 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5789 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5790 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5791 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5792
5793 void print() const {
5794 // condition codes
5795 char c[5];
5796 c[0] = (C3()) ? '3' : '-';
5797 c[1] = (C2()) ? '2' : '-';
5798 c[2] = (C1()) ? '1' : '-';
5799 c[3] = (C0()) ? '0' : '-';
5800 c[4] = '\x0';
5801 // flags
5802 char f[9];
5803 f[0] = (error_status()) ? 'E' : '-';
5804 f[1] = (stack_fault ()) ? 'S' : '-';
5805 f[2] = (precision ()) ? 'P' : '-';
5806 f[3] = (underflow ()) ? 'U' : '-';
5807 f[4] = (overflow ()) ? 'O' : '-';
5808 f[5] = (zero_divide ()) ? 'Z' : '-';
5809 f[6] = (denormalized()) ? 'D' : '-';
5810 f[7] = (invalid ()) ? 'I' : '-';
5811 f[8] = '\x0';
5812 // output
5813 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5814 }
5815
5816 };
5817
5818 class TagWord {
5819 public:
5820 int32_t _value;
5821
5822 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5823
5824 void print() const {
5825 printf("%04x", _value & 0xFFFF);
5826 }
5827
5828 };
5829
5830 class FPU_Register {
5831 public:
5832 int32_t _m0;
5833 int32_t _m1;
5834 int16_t _ex;
5835
5836 bool is_indefinite() const {
5837 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5838 }
5839
5840 void print() const {
5841 char sign = (_ex < 0) ? '-' : '+';
5842 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5843 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5844 };
5845
5846 };
5847
5848 class FPU_State {
5849 public:
5850 enum {
5851 register_size = 10,
5852 number_of_registers = 8,
5853 register_mask = 7
5854 };
5855
5856 ControlWord _control_word;
5857 StatusWord _status_word;
5858 TagWord _tag_word;
5859 int32_t _error_offset;
5860 int32_t _error_selector;
5861 int32_t _data_offset;
5862 int32_t _data_selector;
5863 int8_t _register[register_size * number_of_registers];
5864
5865 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5866 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5867
5868 const char* tag_as_string(int tag) const {
5869 switch (tag) {
5870 case 0: return "valid";
5871 case 1: return "zero";
5872 case 2: return "special";
5873 case 3: return "empty";
5874 }
5875 ShouldNotReachHere();
5876 return NULL;
5877 }
5878
5879 void print() const {
5880 // print computation registers
5881 { int t = _status_word.top();
5882 for (int i = 0; i < number_of_registers; i++) {
5883 int j = (i - t) & register_mask;
5884 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5885 st(j)->print();
5886 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5887 }
5888 }
5889 printf("\n");
5890 // print control registers
5891 printf("ctrl = "); _control_word.print(); printf("\n");
5892 printf("stat = "); _status_word .print(); printf("\n");
5893 printf("tags = "); _tag_word .print(); printf("\n");
5894 }
5895
5896 };
5897
5898 class Flag_Register {
5899 public:
5900 int32_t _value;
5901
5902 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5903 bool direction() const { return ((_value >> 10) & 1) != 0; }
5904 bool sign() const { return ((_value >> 7) & 1) != 0; }
5905 bool zero() const { return ((_value >> 6) & 1) != 0; }
5906 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5907 bool parity() const { return ((_value >> 2) & 1) != 0; }
5908 bool carry() const { return ((_value >> 0) & 1) != 0; }
5909
5910 void print() const {
5911 // flags
5912 char f[8];
5913 f[0] = (overflow ()) ? 'O' : '-';
5914 f[1] = (direction ()) ? 'D' : '-';
5915 f[2] = (sign ()) ? 'S' : '-';
5916 f[3] = (zero ()) ? 'Z' : '-';
5917 f[4] = (auxiliary_carry()) ? 'A' : '-';
5918 f[5] = (parity ()) ? 'P' : '-';
5919 f[6] = (carry ()) ? 'C' : '-';
5920 f[7] = '\x0';
5921 // output
5922 printf("%08x flags = %s", _value, f);
5923 }
5924
5925 };
5926
5927 class IU_Register {
5928 public:
5929 int32_t _value;
5930
5931 void print() const {
5932 printf("%08x %11d", _value, _value);
5933 }
5934
5935 };
5936
5937 class IU_State {
5938 public:
5939 Flag_Register _eflags;
5940 IU_Register _rdi;
5941 IU_Register _rsi;
5942 IU_Register _rbp;
5943 IU_Register _rsp;
5944 IU_Register _rbx;
5945 IU_Register _rdx;
5946 IU_Register _rcx;
5947 IU_Register _rax;
5948
5949 void print() const {
5950 // computation registers
5951 printf("rax, = "); _rax.print(); printf("\n");
5952 printf("rbx, = "); _rbx.print(); printf("\n");
5953 printf("rcx = "); _rcx.print(); printf("\n");
5954 printf("rdx = "); _rdx.print(); printf("\n");
5955 printf("rdi = "); _rdi.print(); printf("\n");
5956 printf("rsi = "); _rsi.print(); printf("\n");
5957 printf("rbp, = "); _rbp.print(); printf("\n");
5958 printf("rsp = "); _rsp.print(); printf("\n");
5959 printf("\n");
5960 // control registers
5961 printf("flgs = "); _eflags.print(); printf("\n");
5962 }
5963 };
5964
5965
5966 class CPU_State {
5967 public:
5968 FPU_State _fpu_state;
5969 IU_State _iu_state;
5970
5971 void print() const {
5972 printf("--------------------------------------------------\n");
5973 _iu_state .print();
5974 printf("\n");
5975 _fpu_state.print();
5976 printf("--------------------------------------------------\n");
5977 }
5978
5979 };
5980
5981
5982 static void _print_CPU_state(CPU_State* state) {
5983 state->print();
5984 };
5985
5986
5987 void MacroAssembler::print_CPU_state() {
5988 push_CPU_state();
5989 push(rsp); // pass CPU state
5990 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5991 addptr(rsp, wordSize); // discard argument
5992 pop_CPU_state();
5993 }
5994
5995
5996 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5997 static int counter = 0;
5998 FPU_State* fs = &state->_fpu_state;
5999 counter++;
6000 // For leaf calls, only verify that the top few elements remain empty.
6001 // We only need 1 empty at the top for C2 code.
6002 if( stack_depth < 0 ) {
6003 if( fs->tag_for_st(7) != 3 ) {
6004 printf("FPR7 not empty\n");
6005 state->print();
6006 assert(false, "error");
6007 return false;
6008 }
6009 return true; // All other stack states do not matter
6010 }
6011
6012 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6013 "bad FPU control word");
6014
6015 // compute stack depth
6016 int i = 0;
6017 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6018 int d = i;
6019 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6020 // verify findings
6021 if (i != FPU_State::number_of_registers) {
6022 // stack not contiguous
6023 printf("%s: stack not contiguous at ST%d\n", s, i);
6024 state->print();
6025 assert(false, "error");
6026 return false;
6027 }
6028 // check if computed stack depth corresponds to expected stack depth
6029 if (stack_depth < 0) {
6030 // expected stack depth is -stack_depth or less
6031 if (d > -stack_depth) {
6032 // too many elements on the stack
6033 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6034 state->print();
6035 assert(false, "error");
6036 return false;
6037 }
6038 } else {
6039 // expected stack depth is stack_depth
6040 if (d != stack_depth) {
6041 // wrong stack depth
6042 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6043 state->print();
6044 assert(false, "error");
6045 return false;
6046 }
6047 }
6048 // everything is cool
6049 return true;
6050 }
6051
6052
6053 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6054 if (!VerifyFPU) return;
6055 push_CPU_state();
6056 push(rsp); // pass CPU state
6057 ExternalAddress msg((address) s);
6058 // pass message string s
6059 pushptr(msg.addr());
6060 push(stack_depth); // pass stack depth
6061 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6062 addptr(rsp, 3 * wordSize); // discard arguments
6063 // check for error
6064 { Label L;
6065 testl(rax, rax);
6066 jcc(Assembler::notZero, L);
6067 int3(); // break if error condition
6068 bind(L);
6069 }
6070 pop_CPU_state();
6071 }
6072
6073 void MacroAssembler::restore_cpu_control_state_after_jni() {
6074 // Either restore the MXCSR register after returning from the JNI Call
6075 // or verify that it wasn't changed (with -Xcheck:jni flag).
6076 if (VM_Version::supports_sse()) {
6077 if (RestoreMXCSROnJNICalls) {
6078 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6079 } else if (CheckJNICalls) {
6080 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6081 }
6082 }
6083 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6084 vzeroupper();
6085 // Reset k1 to 0xffff.
6086 if (VM_Version::supports_evex()) {
6087 push(rcx);
6088 movl(rcx, 0xffff);
6089 kmovwl(k1, rcx);
6090 pop(rcx);
6091 }
6092
6093 #ifndef _LP64
6094 // Either restore the x87 floating pointer control word after returning
6095 // from the JNI call or verify that it wasn't changed.
6096 if (CheckJNICalls) {
6097 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6098 }
6099 #endif // _LP64
6100 }
6101
6102 // ((OopHandle)result).resolve();
6103 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
6104 assert_different_registers(result, tmp);
6105
6106 // Only 64 bit platforms support GCs that require a tmp register
6107 // Only IN_HEAP loads require a thread_tmp register
6108 // OopHandle::resolve is an indirection like jobject.
6109 access_load_at(T_OBJECT, IN_NATIVE,
6110 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
6111 }
6112
6113 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
6114 // get mirror
6115 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6116 movptr(mirror, Address(method, Method::const_offset()));
6117 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6118 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6119 movptr(mirror, Address(mirror, mirror_offset));
6120 resolve_oop_handle(mirror, tmp);
6121 }
6122
6123 void MacroAssembler::load_klass(Register dst, Register src) {
6124 #ifdef _LP64
6125 if (UseCompressedClassPointers) {
6126 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6127 decode_klass_not_null(dst);
6128 } else
6129 #endif
6130 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6131 }
6132
6133 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6134 load_klass(dst, src);
6135 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6136 }
6137
6138 void MacroAssembler::store_klass(Register dst, Register src) {
6139 #ifdef _LP64
6140 if (UseCompressedClassPointers) {
6141 encode_klass_not_null(src);
6142 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6143 } else
6144 #endif
6145 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6146 }
6147
6148 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6149 Register tmp1, Register thread_tmp) {
6150 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6151 decorators = AccessInternal::decorator_fixup(decorators);
6152 bool as_raw = (decorators & AS_RAW) != 0;
6153 if (as_raw) {
6154 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6155 } else {
6156 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6157 }
6158 }
6159
6160 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
6161 Register tmp1, Register tmp2) {
6162 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6163 decorators = AccessInternal::decorator_fixup(decorators);
6164 bool as_raw = (decorators & AS_RAW) != 0;
6165 if (as_raw) {
6166 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
6167 } else {
6168 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
6169 }
6170 }
6171
6172 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
6173 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
6174 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
6175 decorators |= ACCESS_READ | ACCESS_WRITE;
6176 }
6177 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6178 return bs->resolve(this, decorators, obj);
6179 }
6180
6181 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6182 Register thread_tmp, DecoratorSet decorators) {
6183 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6184 }
6185
6186 // Doesn't do verfication, generates fixed size code
6187 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6188 Register thread_tmp, DecoratorSet decorators) {
6189 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6190 }
6191
6192 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
6193 Register tmp2, DecoratorSet decorators) {
6194 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
6195 }
6196
6197 // Used for storing NULLs.
6198 void MacroAssembler::store_heap_oop_null(Address dst) {
6199 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
6200 }
6201
6202 #ifdef _LP64
6203 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6204 if (UseCompressedClassPointers) {
6205 // Store to klass gap in destination
6206 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6207 }
6208 }
6209
6210 #ifdef ASSERT
6211 void MacroAssembler::verify_heapbase(const char* msg) {
6212 assert (UseCompressedOops, "should be compressed");
6213 assert (Universe::heap() != NULL, "java heap should be initialized");
6214 if (CheckCompressedOops) {
6215 Label ok;
6216 push(rscratch1); // cmpptr trashes rscratch1
6217 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6218 jcc(Assembler::equal, ok);
6219 STOP(msg);
6220 bind(ok);
6221 pop(rscratch1);
6222 }
6223 }
6224 #endif
6225
6226 // Algorithm must match oop.inline.hpp encode_heap_oop.
6227 void MacroAssembler::encode_heap_oop(Register r) {
6228 #ifdef ASSERT
6229 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6230 #endif
6231 verify_oop(r, "broken oop in encode_heap_oop");
6232 if (Universe::narrow_oop_base() == NULL) {
6233 if (Universe::narrow_oop_shift() != 0) {
6234 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6235 shrq(r, LogMinObjAlignmentInBytes);
6236 }
6237 return;
6238 }
6239 testq(r, r);
6240 cmovq(Assembler::equal, r, r12_heapbase);
6241 subq(r, r12_heapbase);
6242 shrq(r, LogMinObjAlignmentInBytes);
6243 }
6244
6245 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6246 #ifdef ASSERT
6247 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6248 if (CheckCompressedOops) {
6249 Label ok;
6250 testq(r, r);
6251 jcc(Assembler::notEqual, ok);
6252 STOP("null oop passed to encode_heap_oop_not_null");
6253 bind(ok);
6254 }
6255 #endif
6256 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6257 if (Universe::narrow_oop_base() != NULL) {
6258 subq(r, r12_heapbase);
6259 }
6260 if (Universe::narrow_oop_shift() != 0) {
6261 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6262 shrq(r, LogMinObjAlignmentInBytes);
6263 }
6264 }
6265
6266 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6267 #ifdef ASSERT
6268 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6269 if (CheckCompressedOops) {
6270 Label ok;
6271 testq(src, src);
6272 jcc(Assembler::notEqual, ok);
6273 STOP("null oop passed to encode_heap_oop_not_null2");
6274 bind(ok);
6275 }
6276 #endif
6277 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6278 if (dst != src) {
6279 movq(dst, src);
6280 }
6281 if (Universe::narrow_oop_base() != NULL) {
6282 subq(dst, r12_heapbase);
6283 }
6284 if (Universe::narrow_oop_shift() != 0) {
6285 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6286 shrq(dst, LogMinObjAlignmentInBytes);
6287 }
6288 }
6289
6290 void MacroAssembler::decode_heap_oop(Register r) {
6291 #ifdef ASSERT
6292 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6293 #endif
6294 if (Universe::narrow_oop_base() == NULL) {
6295 if (Universe::narrow_oop_shift() != 0) {
6296 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6297 shlq(r, LogMinObjAlignmentInBytes);
6298 }
6299 } else {
6300 Label done;
6301 shlq(r, LogMinObjAlignmentInBytes);
6302 jccb(Assembler::equal, done);
6303 addq(r, r12_heapbase);
6304 bind(done);
6305 }
6306 verify_oop(r, "broken oop in decode_heap_oop");
6307 }
6308
6309 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6310 // Note: it will change flags
6311 assert (UseCompressedOops, "should only be used for compressed headers");
6312 assert (Universe::heap() != NULL, "java heap should be initialized");
6313 // Cannot assert, unverified entry point counts instructions (see .ad file)
6314 // vtableStubs also counts instructions in pd_code_size_limit.
6315 // Also do not verify_oop as this is called by verify_oop.
6316 if (Universe::narrow_oop_shift() != 0) {
6317 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6318 shlq(r, LogMinObjAlignmentInBytes);
6319 if (Universe::narrow_oop_base() != NULL) {
6320 addq(r, r12_heapbase);
6321 }
6322 } else {
6323 assert (Universe::narrow_oop_base() == NULL, "sanity");
6324 }
6325 }
6326
6327 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6328 // Note: it will change flags
6329 assert (UseCompressedOops, "should only be used for compressed headers");
6330 assert (Universe::heap() != NULL, "java heap should be initialized");
6331 // Cannot assert, unverified entry point counts instructions (see .ad file)
6332 // vtableStubs also counts instructions in pd_code_size_limit.
6333 // Also do not verify_oop as this is called by verify_oop.
6334 if (Universe::narrow_oop_shift() != 0) {
6335 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6336 if (LogMinObjAlignmentInBytes == Address::times_8) {
6337 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6338 } else {
6339 if (dst != src) {
6340 movq(dst, src);
6341 }
6342 shlq(dst, LogMinObjAlignmentInBytes);
6343 if (Universe::narrow_oop_base() != NULL) {
6344 addq(dst, r12_heapbase);
6345 }
6346 }
6347 } else {
6348 assert (Universe::narrow_oop_base() == NULL, "sanity");
6349 if (dst != src) {
6350 movq(dst, src);
6351 }
6352 }
6353 }
6354
6355 void MacroAssembler::encode_klass_not_null(Register r) {
6356 if (Universe::narrow_klass_base() != NULL) {
6357 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6358 assert(r != r12_heapbase, "Encoding a klass in r12");
6359 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6360 subq(r, r12_heapbase);
6361 }
6362 if (Universe::narrow_klass_shift() != 0) {
6363 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6364 shrq(r, LogKlassAlignmentInBytes);
6365 }
6366 if (Universe::narrow_klass_base() != NULL) {
6367 reinit_heapbase();
6368 }
6369 }
6370
6371 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6372 if (dst == src) {
6373 encode_klass_not_null(src);
6374 } else {
6375 if (Universe::narrow_klass_base() != NULL) {
6376 mov64(dst, (int64_t)Universe::narrow_klass_base());
6377 negq(dst);
6378 addq(dst, src);
6379 } else {
6380 movptr(dst, src);
6381 }
6382 if (Universe::narrow_klass_shift() != 0) {
6383 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6384 shrq(dst, LogKlassAlignmentInBytes);
6385 }
6386 }
6387 }
6388
6389 // Function instr_size_for_decode_klass_not_null() counts the instructions
6390 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6391 // when (Universe::heap() != NULL). Hence, if the instructions they
6392 // generate change, then this method needs to be updated.
6393 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6394 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6395 if (Universe::narrow_klass_base() != NULL) {
6396 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6397 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6398 } else {
6399 // longest load decode klass function, mov64, leaq
6400 return 16;
6401 }
6402 }
6403
6404 // !!! If the instructions that get generated here change then function
6405 // instr_size_for_decode_klass_not_null() needs to get updated.
6406 void MacroAssembler::decode_klass_not_null(Register r) {
6407 // Note: it will change flags
6408 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6409 assert(r != r12_heapbase, "Decoding a klass in r12");
6410 // Cannot assert, unverified entry point counts instructions (see .ad file)
6411 // vtableStubs also counts instructions in pd_code_size_limit.
6412 // Also do not verify_oop as this is called by verify_oop.
6413 if (Universe::narrow_klass_shift() != 0) {
6414 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6415 shlq(r, LogKlassAlignmentInBytes);
6416 }
6417 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6418 if (Universe::narrow_klass_base() != NULL) {
6419 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6420 addq(r, r12_heapbase);
6421 reinit_heapbase();
6422 }
6423 }
6424
6425 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6426 // Note: it will change flags
6427 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6428 if (dst == src) {
6429 decode_klass_not_null(dst);
6430 } else {
6431 // Cannot assert, unverified entry point counts instructions (see .ad file)
6432 // vtableStubs also counts instructions in pd_code_size_limit.
6433 // Also do not verify_oop as this is called by verify_oop.
6434 mov64(dst, (int64_t)Universe::narrow_klass_base());
6435 if (Universe::narrow_klass_shift() != 0) {
6436 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6437 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6438 leaq(dst, Address(dst, src, Address::times_8, 0));
6439 } else {
6440 addq(dst, src);
6441 }
6442 }
6443 }
6444
6445 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6446 assert (UseCompressedOops, "should only be used for compressed headers");
6447 assert (Universe::heap() != NULL, "java heap should be initialized");
6448 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6449 int oop_index = oop_recorder()->find_index(obj);
6450 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6451 mov_narrow_oop(dst, oop_index, rspec);
6452 }
6453
6454 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6455 assert (UseCompressedOops, "should only be used for compressed headers");
6456 assert (Universe::heap() != NULL, "java heap should be initialized");
6457 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6458 int oop_index = oop_recorder()->find_index(obj);
6459 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6460 mov_narrow_oop(dst, oop_index, rspec);
6461 }
6462
6463 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6464 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6465 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6466 int klass_index = oop_recorder()->find_index(k);
6467 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6468 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6469 }
6470
6471 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6472 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6473 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6474 int klass_index = oop_recorder()->find_index(k);
6475 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6476 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6477 }
6478
6479 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6480 assert (UseCompressedOops, "should only be used for compressed headers");
6481 assert (Universe::heap() != NULL, "java heap should be initialized");
6482 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6483 int oop_index = oop_recorder()->find_index(obj);
6484 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6485 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6486 }
6487
6488 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6489 assert (UseCompressedOops, "should only be used for compressed headers");
6490 assert (Universe::heap() != NULL, "java heap should be initialized");
6491 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6492 int oop_index = oop_recorder()->find_index(obj);
6493 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6494 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6495 }
6496
6497 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6498 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6499 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6500 int klass_index = oop_recorder()->find_index(k);
6501 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6502 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6503 }
6504
6505 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6506 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6507 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6508 int klass_index = oop_recorder()->find_index(k);
6509 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6510 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6511 }
6512
6513 void MacroAssembler::reinit_heapbase() {
6514 if (UseCompressedOops || UseCompressedClassPointers) {
6515 if (Universe::heap() != NULL) {
6516 if (Universe::narrow_oop_base() == NULL) {
6517 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6518 } else {
6519 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6520 }
6521 } else {
6522 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6523 }
6524 }
6525 }
6526
6527 #endif // _LP64
6528
6529 // C2 compiled method's prolog code.
6530 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6531
6532 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6533 // NativeJump::patch_verified_entry will be able to patch out the entry
6534 // code safely. The push to verify stack depth is ok at 5 bytes,
6535 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6536 // stack bang then we must use the 6 byte frame allocation even if
6537 // we have no frame. :-(
6538 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6539
6540 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6541 // Remove word for return addr
6542 framesize -= wordSize;
6543 stack_bang_size -= wordSize;
6544
6545 // Calls to C2R adapters often do not accept exceptional returns.
6546 // We require that their callers must bang for them. But be careful, because
6547 // some VM calls (such as call site linkage) can use several kilobytes of
6548 // stack. But the stack safety zone should account for that.
6549 // See bugs 4446381, 4468289, 4497237.
6550 if (stack_bang_size > 0) {
6551 generate_stack_overflow_check(stack_bang_size);
6552
6553 // We always push rbp, so that on return to interpreter rbp, will be
6554 // restored correctly and we can correct the stack.
6555 push(rbp);
6556 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6557 if (PreserveFramePointer) {
6558 mov(rbp, rsp);
6559 }
6560 // Remove word for ebp
6561 framesize -= wordSize;
6562
6563 // Create frame
6564 if (framesize) {
6565 subptr(rsp, framesize);
6566 }
6567 } else {
6568 // Create frame (force generation of a 4 byte immediate value)
6569 subptr_imm32(rsp, framesize);
6570
6571 // Save RBP register now.
6572 framesize -= wordSize;
6573 movptr(Address(rsp, framesize), rbp);
6574 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6575 if (PreserveFramePointer) {
6576 movptr(rbp, rsp);
6577 if (framesize > 0) {
6578 addptr(rbp, framesize);
6579 }
6580 }
6581 }
6582
6583 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6584 framesize -= wordSize;
6585 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6586 }
6587
6588 #ifndef _LP64
6589 // If method sets FPU control word do it now
6590 if (fp_mode_24b) {
6591 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6592 }
6593 if (UseSSE >= 2 && VerifyFPU) {
6594 verify_FPU(0, "FPU stack must be clean on entry");
6595 }
6596 #endif
6597
6598 #ifdef ASSERT
6599 if (VerifyStackAtCalls) {
6600 Label L;
6601 push(rax);
6602 mov(rax, rsp);
6603 andptr(rax, StackAlignmentInBytes-1);
6604 cmpptr(rax, StackAlignmentInBytes-wordSize);
6605 pop(rax);
6606 jcc(Assembler::equal, L);
6607 STOP("Stack is not properly aligned!");
6608 bind(L);
6609 }
6610 #endif
6611
6612 }
6613
6614 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
6615 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
6616 // cnt - number of qwords (8-byte words).
6617 // base - start address, qword aligned.
6618 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6619 if (UseAVX >= 2) {
6620 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6621 } else {
6622 pxor(xtmp, xtmp);
6623 }
6624 jmp(L_zero_64_bytes);
6625
6626 BIND(L_loop);
6627 if (UseAVX >= 2) {
6628 vmovdqu(Address(base, 0), xtmp);
6629 vmovdqu(Address(base, 32), xtmp);
6630 } else {
6631 movdqu(Address(base, 0), xtmp);
6632 movdqu(Address(base, 16), xtmp);
6633 movdqu(Address(base, 32), xtmp);
6634 movdqu(Address(base, 48), xtmp);
6635 }
6636 addptr(base, 64);
6637
6638 BIND(L_zero_64_bytes);
6639 subptr(cnt, 8);
6640 jccb(Assembler::greaterEqual, L_loop);
6641 addptr(cnt, 4);
6642 jccb(Assembler::less, L_tail);
6643 // Copy trailing 32 bytes
6644 if (UseAVX >= 2) {
6645 vmovdqu(Address(base, 0), xtmp);
6646 } else {
6647 movdqu(Address(base, 0), xtmp);
6648 movdqu(Address(base, 16), xtmp);
6649 }
6650 addptr(base, 32);
6651 subptr(cnt, 4);
6652
6653 BIND(L_tail);
6654 addptr(cnt, 4);
6655 jccb(Assembler::lessEqual, L_end);
6656 decrement(cnt);
6657
6658 BIND(L_sloop);
6659 movq(Address(base, 0), xtmp);
6660 addptr(base, 8);
6661 decrement(cnt);
6662 jccb(Assembler::greaterEqual, L_sloop);
6663 BIND(L_end);
6664 }
6665
6666 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
6667 // cnt - number of qwords (8-byte words).
6668 // base - start address, qword aligned.
6669 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6670 assert(base==rdi, "base register must be edi for rep stos");
6671 assert(tmp==rax, "tmp register must be eax for rep stos");
6672 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6673 assert(InitArrayShortSize % BytesPerLong == 0,
6674 "InitArrayShortSize should be the multiple of BytesPerLong");
6675
6676 Label DONE;
6677
6678 if (!is_large || !UseXMMForObjInit) {
6679 xorptr(tmp, tmp);
6680 }
6681
6682 if (!is_large) {
6683 Label LOOP, LONG;
6684 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6685 jccb(Assembler::greater, LONG);
6686
6687 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6688
6689 decrement(cnt);
6690 jccb(Assembler::negative, DONE); // Zero length
6691
6692 // Use individual pointer-sized stores for small counts:
6693 BIND(LOOP);
6694 movptr(Address(base, cnt, Address::times_ptr), tmp);
6695 decrement(cnt);
6696 jccb(Assembler::greaterEqual, LOOP);
6697 jmpb(DONE);
6698
6699 BIND(LONG);
6700 }
6701
6702 // Use longer rep-prefixed ops for non-small counts:
6703 if (UseFastStosb) {
6704 shlptr(cnt, 3); // convert to number of bytes
6705 rep_stosb();
6706 } else if (UseXMMForObjInit) {
6707 movptr(tmp, base);
6708 xmm_clear_mem(tmp, cnt, xtmp);
6709 } else {
6710 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6711 rep_stos();
6712 }
6713
6714 BIND(DONE);
6715 }
6716
6717 #ifdef COMPILER2
6718
6719 // IndexOf for constant substrings with size >= 8 chars
6720 // which don't need to be loaded through stack.
6721 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6722 Register cnt1, Register cnt2,
6723 int int_cnt2, Register result,
6724 XMMRegister vec, Register tmp,
6725 int ae) {
6726 ShortBranchVerifier sbv(this);
6727 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6728 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6729
6730 // This method uses the pcmpestri instruction with bound registers
6731 // inputs:
6732 // xmm - substring
6733 // rax - substring length (elements count)
6734 // mem - scanned string
6735 // rdx - string length (elements count)
6736 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6737 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6738 // outputs:
6739 // rcx - matched index in string
6740 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6741 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6742 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6743 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6744 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6745
6746 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6747 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6748 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6749
6750 // Note, inline_string_indexOf() generates checks:
6751 // if (substr.count > string.count) return -1;
6752 // if (substr.count == 0) return 0;
6753 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
6754
6755 // Load substring.
6756 if (ae == StrIntrinsicNode::UL) {
6757 pmovzxbw(vec, Address(str2, 0));
6758 } else {
6759 movdqu(vec, Address(str2, 0));
6760 }
6761 movl(cnt2, int_cnt2);
6762 movptr(result, str1); // string addr
6763
6764 if (int_cnt2 > stride) {
6765 jmpb(SCAN_TO_SUBSTR);
6766
6767 // Reload substr for rescan, this code
6768 // is executed only for large substrings (> 8 chars)
6769 bind(RELOAD_SUBSTR);
6770 if (ae == StrIntrinsicNode::UL) {
6771 pmovzxbw(vec, Address(str2, 0));
6772 } else {
6773 movdqu(vec, Address(str2, 0));
6774 }
6775 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6776
6777 bind(RELOAD_STR);
6778 // We came here after the beginning of the substring was
6779 // matched but the rest of it was not so we need to search
6780 // again. Start from the next element after the previous match.
6781
6782 // cnt2 is number of substring reminding elements and
6783 // cnt1 is number of string reminding elements when cmp failed.
6784 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6785 subl(cnt1, cnt2);
6786 addl(cnt1, int_cnt2);
6787 movl(cnt2, int_cnt2); // Now restore cnt2
6788
6789 decrementl(cnt1); // Shift to next element
6790 cmpl(cnt1, cnt2);
6791 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6792
6793 addptr(result, (1<<scale1));
6794
6795 } // (int_cnt2 > 8)
6796
6797 // Scan string for start of substr in 16-byte vectors
6798 bind(SCAN_TO_SUBSTR);
6799 pcmpestri(vec, Address(result, 0), mode);
6800 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6801 subl(cnt1, stride);
6802 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6803 cmpl(cnt1, cnt2);
6804 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6805 addptr(result, 16);
6806 jmpb(SCAN_TO_SUBSTR);
6807
6808 // Found a potential substr
6809 bind(FOUND_CANDIDATE);
6810 // Matched whole vector if first element matched (tmp(rcx) == 0).
6811 if (int_cnt2 == stride) {
6812 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6813 } else { // int_cnt2 > 8
6814 jccb(Assembler::overflow, FOUND_SUBSTR);
6815 }
6816 // After pcmpestri tmp(rcx) contains matched element index
6817 // Compute start addr of substr
6818 lea(result, Address(result, tmp, scale1));
6819
6820 // Make sure string is still long enough
6821 subl(cnt1, tmp);
6822 cmpl(cnt1, cnt2);
6823 if (int_cnt2 == stride) {
6824 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6825 } else { // int_cnt2 > 8
6826 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6827 }
6828 // Left less then substring.
6829
6830 bind(RET_NOT_FOUND);
6831 movl(result, -1);
6832 jmp(EXIT);
6833
6834 if (int_cnt2 > stride) {
6835 // This code is optimized for the case when whole substring
6836 // is matched if its head is matched.
6837 bind(MATCH_SUBSTR_HEAD);
6838 pcmpestri(vec, Address(result, 0), mode);
6839 // Reload only string if does not match
6840 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
6841
6842 Label CONT_SCAN_SUBSTR;
6843 // Compare the rest of substring (> 8 chars).
6844 bind(FOUND_SUBSTR);
6845 // First 8 chars are already matched.
6846 negptr(cnt2);
6847 addptr(cnt2, stride);
6848
6849 bind(SCAN_SUBSTR);
6850 subl(cnt1, stride);
6851 cmpl(cnt2, -stride); // Do not read beyond substring
6852 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6853 // Back-up strings to avoid reading beyond substring:
6854 // cnt1 = cnt1 - cnt2 + 8
6855 addl(cnt1, cnt2); // cnt2 is negative
6856 addl(cnt1, stride);
6857 movl(cnt2, stride); negptr(cnt2);
6858 bind(CONT_SCAN_SUBSTR);
6859 if (int_cnt2 < (int)G) {
6860 int tail_off1 = int_cnt2<<scale1;
6861 int tail_off2 = int_cnt2<<scale2;
6862 if (ae == StrIntrinsicNode::UL) {
6863 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
6864 } else {
6865 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
6866 }
6867 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6868 } else {
6869 // calculate index in register to avoid integer overflow (int_cnt2*2)
6870 movl(tmp, int_cnt2);
6871 addptr(tmp, cnt2);
6872 if (ae == StrIntrinsicNode::UL) {
6873 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
6874 } else {
6875 movdqu(vec, Address(str2, tmp, scale2, 0));
6876 }
6877 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6878 }
6879 // Need to reload strings pointers if not matched whole vector
6880 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6881 addptr(cnt2, stride);
6882 jcc(Assembler::negative, SCAN_SUBSTR);
6883 // Fall through if found full substring
6884
6885 } // (int_cnt2 > 8)
6886
6887 bind(RET_FOUND);
6888 // Found result if we matched full small substring.
6889 // Compute substr offset
6890 subptr(result, str1);
6891 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6892 shrl(result, 1); // index
6893 }
6894 bind(EXIT);
6895
6896 } // string_indexofC8
6897
6898 // Small strings are loaded through stack if they cross page boundary.
6899 void MacroAssembler::string_indexof(Register str1, Register str2,
6900 Register cnt1, Register cnt2,
6901 int int_cnt2, Register result,
6902 XMMRegister vec, Register tmp,
6903 int ae) {
6904 ShortBranchVerifier sbv(this);
6905 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6906 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6907
6908 //
6909 // int_cnt2 is length of small (< 8 chars) constant substring
6910 // or (-1) for non constant substring in which case its length
6911 // is in cnt2 register.
6912 //
6913 // Note, inline_string_indexOf() generates checks:
6914 // if (substr.count > string.count) return -1;
6915 // if (substr.count == 0) return 0;
6916 //
6917 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6918 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
6919 // This method uses the pcmpestri instruction with bound registers
6920 // inputs:
6921 // xmm - substring
6922 // rax - substring length (elements count)
6923 // mem - scanned string
6924 // rdx - string length (elements count)
6925 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6926 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6927 // outputs:
6928 // rcx - matched index in string
6929 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6930 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6931 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6932 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6933
6934 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6935 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6936 FOUND_CANDIDATE;
6937
6938 { //========================================================
6939 // We don't know where these strings are located
6940 // and we can't read beyond them. Load them through stack.
6941 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6942
6943 movptr(tmp, rsp); // save old SP
6944
6945 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6946 if (int_cnt2 == (1>>scale2)) { // One byte
6947 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
6948 load_unsigned_byte(result, Address(str2, 0));
6949 movdl(vec, result); // move 32 bits
6950 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
6951 // Not enough header space in 32-bit VM: 12+3 = 15.
6952 movl(result, Address(str2, -1));
6953 shrl(result, 8);
6954 movdl(vec, result); // move 32 bits
6955 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
6956 load_unsigned_short(result, Address(str2, 0));
6957 movdl(vec, result); // move 32 bits
6958 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
6959 movdl(vec, Address(str2, 0)); // move 32 bits
6960 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
6961 movq(vec, Address(str2, 0)); // move 64 bits
6962 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
6963 // Array header size is 12 bytes in 32-bit VM
6964 // + 6 bytes for 3 chars == 18 bytes,
6965 // enough space to load vec and shift.
6966 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6967 if (ae == StrIntrinsicNode::UL) {
6968 int tail_off = int_cnt2-8;
6969 pmovzxbw(vec, Address(str2, tail_off));
6970 psrldq(vec, -2*tail_off);
6971 }
6972 else {
6973 int tail_off = int_cnt2*(1<<scale2);
6974 movdqu(vec, Address(str2, tail_off-16));
6975 psrldq(vec, 16-tail_off);
6976 }
6977 }
6978 } else { // not constant substring
6979 cmpl(cnt2, stride);
6980 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6981
6982 // We can read beyond string if srt+16 does not cross page boundary
6983 // since heaps are aligned and mapped by pages.
6984 assert(os::vm_page_size() < (int)G, "default page should be small");
6985 movl(result, str2); // We need only low 32 bits
6986 andl(result, (os::vm_page_size()-1));
6987 cmpl(result, (os::vm_page_size()-16));
6988 jccb(Assembler::belowEqual, CHECK_STR);
6989
6990 // Move small strings to stack to allow load 16 bytes into vec.
6991 subptr(rsp, 16);
6992 int stk_offset = wordSize-(1<<scale2);
6993 push(cnt2);
6994
6995 bind(COPY_SUBSTR);
6996 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
6997 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
6998 movb(Address(rsp, cnt2, scale2, stk_offset), result);
6999 } else if (ae == StrIntrinsicNode::UU) {
7000 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7001 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7002 }
7003 decrement(cnt2);
7004 jccb(Assembler::notZero, COPY_SUBSTR);
7005
7006 pop(cnt2);
7007 movptr(str2, rsp); // New substring address
7008 } // non constant
7009
7010 bind(CHECK_STR);
7011 cmpl(cnt1, stride);
7012 jccb(Assembler::aboveEqual, BIG_STRINGS);
7013
7014 // Check cross page boundary.
7015 movl(result, str1); // We need only low 32 bits
7016 andl(result, (os::vm_page_size()-1));
7017 cmpl(result, (os::vm_page_size()-16));
7018 jccb(Assembler::belowEqual, BIG_STRINGS);
7019
7020 subptr(rsp, 16);
7021 int stk_offset = -(1<<scale1);
7022 if (int_cnt2 < 0) { // not constant
7023 push(cnt2);
7024 stk_offset += wordSize;
7025 }
7026 movl(cnt2, cnt1);
7027
7028 bind(COPY_STR);
7029 if (ae == StrIntrinsicNode::LL) {
7030 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7031 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7032 } else {
7033 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7034 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7035 }
7036 decrement(cnt2);
7037 jccb(Assembler::notZero, COPY_STR);
7038
7039 if (int_cnt2 < 0) { // not constant
7040 pop(cnt2);
7041 }
7042 movptr(str1, rsp); // New string address
7043
7044 bind(BIG_STRINGS);
7045 // Load substring.
7046 if (int_cnt2 < 0) { // -1
7047 if (ae == StrIntrinsicNode::UL) {
7048 pmovzxbw(vec, Address(str2, 0));
7049 } else {
7050 movdqu(vec, Address(str2, 0));
7051 }
7052 push(cnt2); // substr count
7053 push(str2); // substr addr
7054 push(str1); // string addr
7055 } else {
7056 // Small (< 8 chars) constant substrings are loaded already.
7057 movl(cnt2, int_cnt2);
7058 }
7059 push(tmp); // original SP
7060
7061 } // Finished loading
7062
7063 //========================================================
7064 // Start search
7065 //
7066
7067 movptr(result, str1); // string addr
7068
7069 if (int_cnt2 < 0) { // Only for non constant substring
7070 jmpb(SCAN_TO_SUBSTR);
7071
7072 // SP saved at sp+0
7073 // String saved at sp+1*wordSize
7074 // Substr saved at sp+2*wordSize
7075 // Substr count saved at sp+3*wordSize
7076
7077 // Reload substr for rescan, this code
7078 // is executed only for large substrings (> 8 chars)
7079 bind(RELOAD_SUBSTR);
7080 movptr(str2, Address(rsp, 2*wordSize));
7081 movl(cnt2, Address(rsp, 3*wordSize));
7082 if (ae == StrIntrinsicNode::UL) {
7083 pmovzxbw(vec, Address(str2, 0));
7084 } else {
7085 movdqu(vec, Address(str2, 0));
7086 }
7087 // We came here after the beginning of the substring was
7088 // matched but the rest of it was not so we need to search
7089 // again. Start from the next element after the previous match.
7090 subptr(str1, result); // Restore counter
7091 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7092 shrl(str1, 1);
7093 }
7094 addl(cnt1, str1);
7095 decrementl(cnt1); // Shift to next element
7096 cmpl(cnt1, cnt2);
7097 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7098
7099 addptr(result, (1<<scale1));
7100 } // non constant
7101
7102 // Scan string for start of substr in 16-byte vectors
7103 bind(SCAN_TO_SUBSTR);
7104 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7105 pcmpestri(vec, Address(result, 0), mode);
7106 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7107 subl(cnt1, stride);
7108 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7109 cmpl(cnt1, cnt2);
7110 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7111 addptr(result, 16);
7112
7113 bind(ADJUST_STR);
7114 cmpl(cnt1, stride); // Do not read beyond string
7115 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7116 // Back-up string to avoid reading beyond string.
7117 lea(result, Address(result, cnt1, scale1, -16));
7118 movl(cnt1, stride);
7119 jmpb(SCAN_TO_SUBSTR);
7120
7121 // Found a potential substr
7122 bind(FOUND_CANDIDATE);
7123 // After pcmpestri tmp(rcx) contains matched element index
7124
7125 // Make sure string is still long enough
7126 subl(cnt1, tmp);
7127 cmpl(cnt1, cnt2);
7128 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7129 // Left less then substring.
7130
7131 bind(RET_NOT_FOUND);
7132 movl(result, -1);
7133 jmpb(CLEANUP);
7134
7135 bind(FOUND_SUBSTR);
7136 // Compute start addr of substr
7137 lea(result, Address(result, tmp, scale1));
7138 if (int_cnt2 > 0) { // Constant substring
7139 // Repeat search for small substring (< 8 chars)
7140 // from new point without reloading substring.
7141 // Have to check that we don't read beyond string.
7142 cmpl(tmp, stride-int_cnt2);
7143 jccb(Assembler::greater, ADJUST_STR);
7144 // Fall through if matched whole substring.
7145 } else { // non constant
7146 assert(int_cnt2 == -1, "should be != 0");
7147
7148 addl(tmp, cnt2);
7149 // Found result if we matched whole substring.
7150 cmpl(tmp, stride);
7151 jccb(Assembler::lessEqual, RET_FOUND);
7152
7153 // Repeat search for small substring (<= 8 chars)
7154 // from new point 'str1' without reloading substring.
7155 cmpl(cnt2, stride);
7156 // Have to check that we don't read beyond string.
7157 jccb(Assembler::lessEqual, ADJUST_STR);
7158
7159 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7160 // Compare the rest of substring (> 8 chars).
7161 movptr(str1, result);
7162
7163 cmpl(tmp, cnt2);
7164 // First 8 chars are already matched.
7165 jccb(Assembler::equal, CHECK_NEXT);
7166
7167 bind(SCAN_SUBSTR);
7168 pcmpestri(vec, Address(str1, 0), mode);
7169 // Need to reload strings pointers if not matched whole vector
7170 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7171
7172 bind(CHECK_NEXT);
7173 subl(cnt2, stride);
7174 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7175 addptr(str1, 16);
7176 if (ae == StrIntrinsicNode::UL) {
7177 addptr(str2, 8);
7178 } else {
7179 addptr(str2, 16);
7180 }
7181 subl(cnt1, stride);
7182 cmpl(cnt2, stride); // Do not read beyond substring
7183 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7184 // Back-up strings to avoid reading beyond substring.
7185
7186 if (ae == StrIntrinsicNode::UL) {
7187 lea(str2, Address(str2, cnt2, scale2, -8));
7188 lea(str1, Address(str1, cnt2, scale1, -16));
7189 } else {
7190 lea(str2, Address(str2, cnt2, scale2, -16));
7191 lea(str1, Address(str1, cnt2, scale1, -16));
7192 }
7193 subl(cnt1, cnt2);
7194 movl(cnt2, stride);
7195 addl(cnt1, stride);
7196 bind(CONT_SCAN_SUBSTR);
7197 if (ae == StrIntrinsicNode::UL) {
7198 pmovzxbw(vec, Address(str2, 0));
7199 } else {
7200 movdqu(vec, Address(str2, 0));
7201 }
7202 jmp(SCAN_SUBSTR);
7203
7204 bind(RET_FOUND_LONG);
7205 movptr(str1, Address(rsp, wordSize));
7206 } // non constant
7207
7208 bind(RET_FOUND);
7209 // Compute substr offset
7210 subptr(result, str1);
7211 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7212 shrl(result, 1); // index
7213 }
7214 bind(CLEANUP);
7215 pop(rsp); // restore SP
7216
7217 } // string_indexof
7218
7219 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7220 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7221 ShortBranchVerifier sbv(this);
7222 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7223
7224 int stride = 8;
7225
7226 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7227 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7228 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7229 FOUND_SEQ_CHAR, DONE_LABEL;
7230
7231 movptr(result, str1);
7232 if (UseAVX >= 2) {
7233 cmpl(cnt1, stride);
7234 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7235 cmpl(cnt1, 2*stride);
7236 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7237 movdl(vec1, ch);
7238 vpbroadcastw(vec1, vec1);
7239 vpxor(vec2, vec2);
7240 movl(tmp, cnt1);
7241 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7242 andl(cnt1,0x0000000F); //tail count (in chars)
7243
7244 bind(SCAN_TO_16_CHAR_LOOP);
7245 vmovdqu(vec3, Address(result, 0));
7246 vpcmpeqw(vec3, vec3, vec1, 1);
7247 vptest(vec2, vec3);
7248 jcc(Assembler::carryClear, FOUND_CHAR);
7249 addptr(result, 32);
7250 subl(tmp, 2*stride);
7251 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7252 jmp(SCAN_TO_8_CHAR);
7253 bind(SCAN_TO_8_CHAR_INIT);
7254 movdl(vec1, ch);
7255 pshuflw(vec1, vec1, 0x00);
7256 pshufd(vec1, vec1, 0);
7257 pxor(vec2, vec2);
7258 }
7259 bind(SCAN_TO_8_CHAR);
7260 cmpl(cnt1, stride);
7261 if (UseAVX >= 2) {
7262 jcc(Assembler::less, SCAN_TO_CHAR);
7263 } else {
7264 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7265 movdl(vec1, ch);
7266 pshuflw(vec1, vec1, 0x00);
7267 pshufd(vec1, vec1, 0);
7268 pxor(vec2, vec2);
7269 }
7270 movl(tmp, cnt1);
7271 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7272 andl(cnt1,0x00000007); //tail count (in chars)
7273
7274 bind(SCAN_TO_8_CHAR_LOOP);
7275 movdqu(vec3, Address(result, 0));
7276 pcmpeqw(vec3, vec1);
7277 ptest(vec2, vec3);
7278 jcc(Assembler::carryClear, FOUND_CHAR);
7279 addptr(result, 16);
7280 subl(tmp, stride);
7281 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7282 bind(SCAN_TO_CHAR);
7283 testl(cnt1, cnt1);
7284 jcc(Assembler::zero, RET_NOT_FOUND);
7285 bind(SCAN_TO_CHAR_LOOP);
7286 load_unsigned_short(tmp, Address(result, 0));
7287 cmpl(ch, tmp);
7288 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7289 addptr(result, 2);
7290 subl(cnt1, 1);
7291 jccb(Assembler::zero, RET_NOT_FOUND);
7292 jmp(SCAN_TO_CHAR_LOOP);
7293
7294 bind(RET_NOT_FOUND);
7295 movl(result, -1);
7296 jmpb(DONE_LABEL);
7297
7298 bind(FOUND_CHAR);
7299 if (UseAVX >= 2) {
7300 vpmovmskb(tmp, vec3);
7301 } else {
7302 pmovmskb(tmp, vec3);
7303 }
7304 bsfl(ch, tmp);
7305 addl(result, ch);
7306
7307 bind(FOUND_SEQ_CHAR);
7308 subptr(result, str1);
7309 shrl(result, 1);
7310
7311 bind(DONE_LABEL);
7312 } // string_indexof_char
7313
7314 // helper function for string_compare
7315 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7316 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7317 Address::ScaleFactor scale2, Register index, int ae) {
7318 if (ae == StrIntrinsicNode::LL) {
7319 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7320 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7321 } else if (ae == StrIntrinsicNode::UU) {
7322 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7323 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7324 } else {
7325 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7326 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7327 }
7328 }
7329
7330 // Compare strings, used for char[] and byte[].
7331 void MacroAssembler::string_compare(Register str1, Register str2,
7332 Register cnt1, Register cnt2, Register result,
7333 XMMRegister vec1, int ae) {
7334 ShortBranchVerifier sbv(this);
7335 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7336 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7337 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7338 int stride2x2 = 0x40;
7339 Address::ScaleFactor scale = Address::no_scale;
7340 Address::ScaleFactor scale1 = Address::no_scale;
7341 Address::ScaleFactor scale2 = Address::no_scale;
7342
7343 if (ae != StrIntrinsicNode::LL) {
7344 stride2x2 = 0x20;
7345 }
7346
7347 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7348 shrl(cnt2, 1);
7349 }
7350 // Compute the minimum of the string lengths and the
7351 // difference of the string lengths (stack).
7352 // Do the conditional move stuff
7353 movl(result, cnt1);
7354 subl(cnt1, cnt2);
7355 push(cnt1);
7356 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7357
7358 // Is the minimum length zero?
7359 testl(cnt2, cnt2);
7360 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7361 if (ae == StrIntrinsicNode::LL) {
7362 // Load first bytes
7363 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7364 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7365 } else if (ae == StrIntrinsicNode::UU) {
7366 // Load first characters
7367 load_unsigned_short(result, Address(str1, 0));
7368 load_unsigned_short(cnt1, Address(str2, 0));
7369 } else {
7370 load_unsigned_byte(result, Address(str1, 0));
7371 load_unsigned_short(cnt1, Address(str2, 0));
7372 }
7373 subl(result, cnt1);
7374 jcc(Assembler::notZero, POP_LABEL);
7375
7376 if (ae == StrIntrinsicNode::UU) {
7377 // Divide length by 2 to get number of chars
7378 shrl(cnt2, 1);
7379 }
7380 cmpl(cnt2, 1);
7381 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7382
7383 // Check if the strings start at the same location and setup scale and stride
7384 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7385 cmpptr(str1, str2);
7386 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7387 if (ae == StrIntrinsicNode::LL) {
7388 scale = Address::times_1;
7389 stride = 16;
7390 } else {
7391 scale = Address::times_2;
7392 stride = 8;
7393 }
7394 } else {
7395 scale1 = Address::times_1;
7396 scale2 = Address::times_2;
7397 // scale not used
7398 stride = 8;
7399 }
7400
7401 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7402 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7403 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7404 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7405 Label COMPARE_TAIL_LONG;
7406 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7407
7408 int pcmpmask = 0x19;
7409 if (ae == StrIntrinsicNode::LL) {
7410 pcmpmask &= ~0x01;
7411 }
7412
7413 // Setup to compare 16-chars (32-bytes) vectors,
7414 // start from first character again because it has aligned address.
7415 if (ae == StrIntrinsicNode::LL) {
7416 stride2 = 32;
7417 } else {
7418 stride2 = 16;
7419 }
7420 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7421 adr_stride = stride << scale;
7422 } else {
7423 adr_stride1 = 8; //stride << scale1;
7424 adr_stride2 = 16; //stride << scale2;
7425 }
7426
7427 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7428 // rax and rdx are used by pcmpestri as elements counters
7429 movl(result, cnt2);
7430 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7431 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7432
7433 // fast path : compare first 2 8-char vectors.
7434 bind(COMPARE_16_CHARS);
7435 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7436 movdqu(vec1, Address(str1, 0));
7437 } else {
7438 pmovzxbw(vec1, Address(str1, 0));
7439 }
7440 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7441 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7442
7443 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7444 movdqu(vec1, Address(str1, adr_stride));
7445 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7446 } else {
7447 pmovzxbw(vec1, Address(str1, adr_stride1));
7448 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7449 }
7450 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7451 addl(cnt1, stride);
7452
7453 // Compare the characters at index in cnt1
7454 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7455 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7456 subl(result, cnt2);
7457 jmp(POP_LABEL);
7458
7459 // Setup the registers to start vector comparison loop
7460 bind(COMPARE_WIDE_VECTORS);
7461 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7462 lea(str1, Address(str1, result, scale));
7463 lea(str2, Address(str2, result, scale));
7464 } else {
7465 lea(str1, Address(str1, result, scale1));
7466 lea(str2, Address(str2, result, scale2));
7467 }
7468 subl(result, stride2);
7469 subl(cnt2, stride2);
7470 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7471 negptr(result);
7472
7473 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7474 bind(COMPARE_WIDE_VECTORS_LOOP);
7475
7476 #ifdef _LP64
7477 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7478 cmpl(cnt2, stride2x2);
7479 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7480 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7481 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7482
7483 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7484 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7485 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7486 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7487 } else {
7488 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7489 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7490 }
7491 kortestql(k7, k7);
7492 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7493 addptr(result, stride2x2); // update since we already compared at this addr
7494 subl(cnt2, stride2x2); // and sub the size too
7495 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7496
7497 vpxor(vec1, vec1);
7498 jmpb(COMPARE_WIDE_TAIL);
7499 }//if (VM_Version::supports_avx512vlbw())
7500 #endif // _LP64
7501
7502
7503 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7504 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7505 vmovdqu(vec1, Address(str1, result, scale));
7506 vpxor(vec1, Address(str2, result, scale));
7507 } else {
7508 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7509 vpxor(vec1, Address(str2, result, scale2));
7510 }
7511 vptest(vec1, vec1);
7512 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7513 addptr(result, stride2);
7514 subl(cnt2, stride2);
7515 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7516 // clean upper bits of YMM registers
7517 vpxor(vec1, vec1);
7518
7519 // compare wide vectors tail
7520 bind(COMPARE_WIDE_TAIL);
7521 testptr(result, result);
7522 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7523
7524 movl(result, stride2);
7525 movl(cnt2, result);
7526 negptr(result);
7527 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7528
7529 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7530 bind(VECTOR_NOT_EQUAL);
7531 // clean upper bits of YMM registers
7532 vpxor(vec1, vec1);
7533 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7534 lea(str1, Address(str1, result, scale));
7535 lea(str2, Address(str2, result, scale));
7536 } else {
7537 lea(str1, Address(str1, result, scale1));
7538 lea(str2, Address(str2, result, scale2));
7539 }
7540 jmp(COMPARE_16_CHARS);
7541
7542 // Compare tail chars, length between 1 to 15 chars
7543 bind(COMPARE_TAIL_LONG);
7544 movl(cnt2, result);
7545 cmpl(cnt2, stride);
7546 jcc(Assembler::less, COMPARE_SMALL_STR);
7547
7548 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7549 movdqu(vec1, Address(str1, 0));
7550 } else {
7551 pmovzxbw(vec1, Address(str1, 0));
7552 }
7553 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7554 jcc(Assembler::below, COMPARE_INDEX_CHAR);
7555 subptr(cnt2, stride);
7556 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7557 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7558 lea(str1, Address(str1, result, scale));
7559 lea(str2, Address(str2, result, scale));
7560 } else {
7561 lea(str1, Address(str1, result, scale1));
7562 lea(str2, Address(str2, result, scale2));
7563 }
7564 negptr(cnt2);
7565 jmpb(WHILE_HEAD_LABEL);
7566
7567 bind(COMPARE_SMALL_STR);
7568 } else if (UseSSE42Intrinsics) {
7569 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7570 int pcmpmask = 0x19;
7571 // Setup to compare 8-char (16-byte) vectors,
7572 // start from first character again because it has aligned address.
7573 movl(result, cnt2);
7574 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
7575 if (ae == StrIntrinsicNode::LL) {
7576 pcmpmask &= ~0x01;
7577 }
7578 jcc(Assembler::zero, COMPARE_TAIL);
7579 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7580 lea(str1, Address(str1, result, scale));
7581 lea(str2, Address(str2, result, scale));
7582 } else {
7583 lea(str1, Address(str1, result, scale1));
7584 lea(str2, Address(str2, result, scale2));
7585 }
7586 negptr(result);
7587
7588 // pcmpestri
7589 // inputs:
7590 // vec1- substring
7591 // rax - negative string length (elements count)
7592 // mem - scanned string
7593 // rdx - string length (elements count)
7594 // pcmpmask - cmp mode: 11000 (string compare with negated result)
7595 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
7596 // outputs:
7597 // rcx - first mismatched element index
7598 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7599
7600 bind(COMPARE_WIDE_VECTORS);
7601 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7602 movdqu(vec1, Address(str1, result, scale));
7603 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7604 } else {
7605 pmovzxbw(vec1, Address(str1, result, scale1));
7606 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7607 }
7608 // After pcmpestri cnt1(rcx) contains mismatched element index
7609
7610 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
7611 addptr(result, stride);
7612 subptr(cnt2, stride);
7613 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
7614
7615 // compare wide vectors tail
7616 testptr(result, result);
7617 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7618
7619 movl(cnt2, stride);
7620 movl(result, stride);
7621 negptr(result);
7622 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7623 movdqu(vec1, Address(str1, result, scale));
7624 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7625 } else {
7626 pmovzxbw(vec1, Address(str1, result, scale1));
7627 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7628 }
7629 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
7630
7631 // Mismatched characters in the vectors
7632 bind(VECTOR_NOT_EQUAL);
7633 addptr(cnt1, result);
7634 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7635 subl(result, cnt2);
7636 jmpb(POP_LABEL);
7637
7638 bind(COMPARE_TAIL); // limit is zero
7639 movl(cnt2, result);
7640 // Fallthru to tail compare
7641 }
7642 // Shift str2 and str1 to the end of the arrays, negate min
7643 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7644 lea(str1, Address(str1, cnt2, scale));
7645 lea(str2, Address(str2, cnt2, scale));
7646 } else {
7647 lea(str1, Address(str1, cnt2, scale1));
7648 lea(str2, Address(str2, cnt2, scale2));
7649 }
7650 decrementl(cnt2); // first character was compared already
7651 negptr(cnt2);
7652
7653 // Compare the rest of the elements
7654 bind(WHILE_HEAD_LABEL);
7655 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
7656 subl(result, cnt1);
7657 jccb(Assembler::notZero, POP_LABEL);
7658 increment(cnt2);
7659 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
7660
7661 // Strings are equal up to min length. Return the length difference.
7662 bind(LENGTH_DIFF_LABEL);
7663 pop(result);
7664 if (ae == StrIntrinsicNode::UU) {
7665 // Divide diff by 2 to get number of chars
7666 sarl(result, 1);
7667 }
7668 jmpb(DONE_LABEL);
7669
7670 #ifdef _LP64
7671 if (VM_Version::supports_avx512vlbw()) {
7672
7673 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
7674
7675 kmovql(cnt1, k7);
7676 notq(cnt1);
7677 bsfq(cnt2, cnt1);
7678 if (ae != StrIntrinsicNode::LL) {
7679 // Divide diff by 2 to get number of chars
7680 sarl(cnt2, 1);
7681 }
7682 addq(result, cnt2);
7683 if (ae == StrIntrinsicNode::LL) {
7684 load_unsigned_byte(cnt1, Address(str2, result));
7685 load_unsigned_byte(result, Address(str1, result));
7686 } else if (ae == StrIntrinsicNode::UU) {
7687 load_unsigned_short(cnt1, Address(str2, result, scale));
7688 load_unsigned_short(result, Address(str1, result, scale));
7689 } else {
7690 load_unsigned_short(cnt1, Address(str2, result, scale2));
7691 load_unsigned_byte(result, Address(str1, result, scale1));
7692 }
7693 subl(result, cnt1);
7694 jmpb(POP_LABEL);
7695 }//if (VM_Version::supports_avx512vlbw())
7696 #endif // _LP64
7697
7698 // Discard the stored length difference
7699 bind(POP_LABEL);
7700 pop(cnt1);
7701
7702 // That's it
7703 bind(DONE_LABEL);
7704 if(ae == StrIntrinsicNode::UL) {
7705 negl(result);
7706 }
7707
7708 }
7709
7710 // Search for Non-ASCII character (Negative byte value) in a byte array,
7711 // return true if it has any and false otherwise.
7712 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
7713 // @HotSpotIntrinsicCandidate
7714 // private static boolean hasNegatives(byte[] ba, int off, int len) {
7715 // for (int i = off; i < off + len; i++) {
7716 // if (ba[i] < 0) {
7717 // return true;
7718 // }
7719 // }
7720 // return false;
7721 // }
7722 void MacroAssembler::has_negatives(Register ary1, Register len,
7723 Register result, Register tmp1,
7724 XMMRegister vec1, XMMRegister vec2) {
7725 // rsi: byte array
7726 // rcx: len
7727 // rax: result
7728 ShortBranchVerifier sbv(this);
7729 assert_different_registers(ary1, len, result, tmp1);
7730 assert_different_registers(vec1, vec2);
7731 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
7732
7733 // len == 0
7734 testl(len, len);
7735 jcc(Assembler::zero, FALSE_LABEL);
7736
7737 if ((UseAVX > 2) && // AVX512
7738 VM_Version::supports_avx512vlbw() &&
7739 VM_Version::supports_bmi2()) {
7740
7741 set_vector_masking(); // opening of the stub context for programming mask registers
7742
7743 Label test_64_loop, test_tail;
7744 Register tmp3_aliased = len;
7745
7746 movl(tmp1, len);
7747 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
7748
7749 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
7750 andl(len, ~(64 - 1)); // vector count (in chars)
7751 jccb(Assembler::zero, test_tail);
7752
7753 lea(ary1, Address(ary1, len, Address::times_1));
7754 negptr(len);
7755
7756 bind(test_64_loop);
7757 // Check whether our 64 elements of size byte contain negatives
7758 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
7759 kortestql(k2, k2);
7760 jcc(Assembler::notZero, TRUE_LABEL);
7761
7762 addptr(len, 64);
7763 jccb(Assembler::notZero, test_64_loop);
7764
7765
7766 bind(test_tail);
7767 // bail out when there is nothing to be done
7768 testl(tmp1, -1);
7769 jcc(Assembler::zero, FALSE_LABEL);
7770
7771 // Save k1
7772 kmovql(k3, k1);
7773
7774 // ~(~0 << len) applied up to two times (for 32-bit scenario)
7775 #ifdef _LP64
7776 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
7777 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
7778 notq(tmp3_aliased);
7779 kmovql(k1, tmp3_aliased);
7780 #else
7781 Label k_init;
7782 jmp(k_init);
7783
7784 // We could not read 64-bits from a general purpose register thus we move
7785 // data required to compose 64 1's to the instruction stream
7786 // We emit 64 byte wide series of elements from 0..63 which later on would
7787 // be used as a compare targets with tail count contained in tmp1 register.
7788 // Result would be a k1 register having tmp1 consecutive number or 1
7789 // counting from least significant bit.
7790 address tmp = pc();
7791 emit_int64(0x0706050403020100);
7792 emit_int64(0x0F0E0D0C0B0A0908);
7793 emit_int64(0x1716151413121110);
7794 emit_int64(0x1F1E1D1C1B1A1918);
7795 emit_int64(0x2726252423222120);
7796 emit_int64(0x2F2E2D2C2B2A2928);
7797 emit_int64(0x3736353433323130);
7798 emit_int64(0x3F3E3D3C3B3A3938);
7799
7800 bind(k_init);
7801 lea(len, InternalAddress(tmp));
7802 // create mask to test for negative byte inside a vector
7803 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
7804 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
7805
7806 #endif
7807 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
7808 ktestq(k2, k1);
7809 // Restore k1
7810 kmovql(k1, k3);
7811 jcc(Assembler::notZero, TRUE_LABEL);
7812
7813 jmp(FALSE_LABEL);
7814
7815 clear_vector_masking(); // closing of the stub context for programming mask registers
7816 } else {
7817 movl(result, len); // copy
7818
7819 if (UseAVX == 2 && UseSSE >= 2) {
7820 // With AVX2, use 32-byte vector compare
7821 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7822
7823 // Compare 32-byte vectors
7824 andl(result, 0x0000001f); // tail count (in bytes)
7825 andl(len, 0xffffffe0); // vector count (in bytes)
7826 jccb(Assembler::zero, COMPARE_TAIL);
7827
7828 lea(ary1, Address(ary1, len, Address::times_1));
7829 negptr(len);
7830
7831 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
7832 movdl(vec2, tmp1);
7833 vpbroadcastd(vec2, vec2);
7834
7835 bind(COMPARE_WIDE_VECTORS);
7836 vmovdqu(vec1, Address(ary1, len, Address::times_1));
7837 vptest(vec1, vec2);
7838 jccb(Assembler::notZero, TRUE_LABEL);
7839 addptr(len, 32);
7840 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7841
7842 testl(result, result);
7843 jccb(Assembler::zero, FALSE_LABEL);
7844
7845 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7846 vptest(vec1, vec2);
7847 jccb(Assembler::notZero, TRUE_LABEL);
7848 jmpb(FALSE_LABEL);
7849
7850 bind(COMPARE_TAIL); // len is zero
7851 movl(len, result);
7852 // Fallthru to tail compare
7853 } else if (UseSSE42Intrinsics) {
7854 // With SSE4.2, use double quad vector compare
7855 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7856
7857 // Compare 16-byte vectors
7858 andl(result, 0x0000000f); // tail count (in bytes)
7859 andl(len, 0xfffffff0); // vector count (in bytes)
7860 jccb(Assembler::zero, COMPARE_TAIL);
7861
7862 lea(ary1, Address(ary1, len, Address::times_1));
7863 negptr(len);
7864
7865 movl(tmp1, 0x80808080);
7866 movdl(vec2, tmp1);
7867 pshufd(vec2, vec2, 0);
7868
7869 bind(COMPARE_WIDE_VECTORS);
7870 movdqu(vec1, Address(ary1, len, Address::times_1));
7871 ptest(vec1, vec2);
7872 jccb(Assembler::notZero, TRUE_LABEL);
7873 addptr(len, 16);
7874 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7875
7876 testl(result, result);
7877 jccb(Assembler::zero, FALSE_LABEL);
7878
7879 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7880 ptest(vec1, vec2);
7881 jccb(Assembler::notZero, TRUE_LABEL);
7882 jmpb(FALSE_LABEL);
7883
7884 bind(COMPARE_TAIL); // len is zero
7885 movl(len, result);
7886 // Fallthru to tail compare
7887 }
7888 }
7889 // Compare 4-byte vectors
7890 andl(len, 0xfffffffc); // vector count (in bytes)
7891 jccb(Assembler::zero, COMPARE_CHAR);
7892
7893 lea(ary1, Address(ary1, len, Address::times_1));
7894 negptr(len);
7895
7896 bind(COMPARE_VECTORS);
7897 movl(tmp1, Address(ary1, len, Address::times_1));
7898 andl(tmp1, 0x80808080);
7899 jccb(Assembler::notZero, TRUE_LABEL);
7900 addptr(len, 4);
7901 jcc(Assembler::notZero, COMPARE_VECTORS);
7902
7903 // Compare trailing char (final 2 bytes), if any
7904 bind(COMPARE_CHAR);
7905 testl(result, 0x2); // tail char
7906 jccb(Assembler::zero, COMPARE_BYTE);
7907 load_unsigned_short(tmp1, Address(ary1, 0));
7908 andl(tmp1, 0x00008080);
7909 jccb(Assembler::notZero, TRUE_LABEL);
7910 subptr(result, 2);
7911 lea(ary1, Address(ary1, 2));
7912
7913 bind(COMPARE_BYTE);
7914 testl(result, 0x1); // tail byte
7915 jccb(Assembler::zero, FALSE_LABEL);
7916 load_unsigned_byte(tmp1, Address(ary1, 0));
7917 andl(tmp1, 0x00000080);
7918 jccb(Assembler::notEqual, TRUE_LABEL);
7919 jmpb(FALSE_LABEL);
7920
7921 bind(TRUE_LABEL);
7922 movl(result, 1); // return true
7923 jmpb(DONE);
7924
7925 bind(FALSE_LABEL);
7926 xorl(result, result); // return false
7927
7928 // That's it
7929 bind(DONE);
7930 if (UseAVX >= 2 && UseSSE >= 2) {
7931 // clean upper bits of YMM registers
7932 vpxor(vec1, vec1);
7933 vpxor(vec2, vec2);
7934 }
7935 }
7936 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
7937 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7938 Register limit, Register result, Register chr,
7939 XMMRegister vec1, XMMRegister vec2, bool is_char) {
7940 ShortBranchVerifier sbv(this);
7941 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
7942
7943 int length_offset = arrayOopDesc::length_offset_in_bytes();
7944 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
7945
7946 if (is_array_equ) {
7947 // Check the input args
7948 cmpoop(ary1, ary2);
7949 jcc(Assembler::equal, TRUE_LABEL);
7950
7951 // Need additional checks for arrays_equals.
7952 testptr(ary1, ary1);
7953 jcc(Assembler::zero, FALSE_LABEL);
7954 testptr(ary2, ary2);
7955 jcc(Assembler::zero, FALSE_LABEL);
7956
7957 // Check the lengths
7958 movl(limit, Address(ary1, length_offset));
7959 cmpl(limit, Address(ary2, length_offset));
7960 jcc(Assembler::notEqual, FALSE_LABEL);
7961 }
7962
7963 // count == 0
7964 testl(limit, limit);
7965 jcc(Assembler::zero, TRUE_LABEL);
7966
7967 if (is_array_equ) {
7968 // Load array address
7969 lea(ary1, Address(ary1, base_offset));
7970 lea(ary2, Address(ary2, base_offset));
7971 }
7972
7973 if (is_array_equ && is_char) {
7974 // arrays_equals when used for char[].
7975 shll(limit, 1); // byte count != 0
7976 }
7977 movl(result, limit); // copy
7978
7979 if (UseAVX >= 2) {
7980 // With AVX2, use 32-byte vector compare
7981 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7982
7983 // Compare 32-byte vectors
7984 andl(result, 0x0000001f); // tail count (in bytes)
7985 andl(limit, 0xffffffe0); // vector count (in bytes)
7986 jcc(Assembler::zero, COMPARE_TAIL);
7987
7988 lea(ary1, Address(ary1, limit, Address::times_1));
7989 lea(ary2, Address(ary2, limit, Address::times_1));
7990 negptr(limit);
7991
7992 bind(COMPARE_WIDE_VECTORS);
7993
7994 #ifdef _LP64
7995 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7996 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
7997
7998 cmpl(limit, -64);
7999 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8000
8001 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8002
8003 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8004 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8005 kortestql(k7, k7);
8006 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8007 addptr(limit, 64); // update since we already compared at this addr
8008 cmpl(limit, -64);
8009 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8010
8011 // At this point we may still need to compare -limit+result bytes.
8012 // We could execute the next two instruction and just continue via non-wide path:
8013 // cmpl(limit, 0);
8014 // jcc(Assembler::equal, COMPARE_TAIL); // true
8015 // But since we stopped at the points ary{1,2}+limit which are
8016 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8017 // (|limit| <= 32 and result < 32),
8018 // we may just compare the last 64 bytes.
8019 //
8020 addptr(result, -64); // it is safe, bc we just came from this area
8021 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8022 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8023 kortestql(k7, k7);
8024 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8025
8026 jmp(TRUE_LABEL);
8027
8028 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8029
8030 }//if (VM_Version::supports_avx512vlbw())
8031 #endif //_LP64
8032
8033 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8034 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8035 vpxor(vec1, vec2);
8036
8037 vptest(vec1, vec1);
8038 jcc(Assembler::notZero, FALSE_LABEL);
8039 addptr(limit, 32);
8040 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8041
8042 testl(result, result);
8043 jcc(Assembler::zero, TRUE_LABEL);
8044
8045 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8046 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8047 vpxor(vec1, vec2);
8048
8049 vptest(vec1, vec1);
8050 jccb(Assembler::notZero, FALSE_LABEL);
8051 jmpb(TRUE_LABEL);
8052
8053 bind(COMPARE_TAIL); // limit is zero
8054 movl(limit, result);
8055 // Fallthru to tail compare
8056 } else if (UseSSE42Intrinsics) {
8057 // With SSE4.2, use double quad vector compare
8058 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8059
8060 // Compare 16-byte vectors
8061 andl(result, 0x0000000f); // tail count (in bytes)
8062 andl(limit, 0xfffffff0); // vector count (in bytes)
8063 jcc(Assembler::zero, COMPARE_TAIL);
8064
8065 lea(ary1, Address(ary1, limit, Address::times_1));
8066 lea(ary2, Address(ary2, limit, Address::times_1));
8067 negptr(limit);
8068
8069 bind(COMPARE_WIDE_VECTORS);
8070 movdqu(vec1, Address(ary1, limit, Address::times_1));
8071 movdqu(vec2, Address(ary2, limit, Address::times_1));
8072 pxor(vec1, vec2);
8073
8074 ptest(vec1, vec1);
8075 jcc(Assembler::notZero, FALSE_LABEL);
8076 addptr(limit, 16);
8077 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8078
8079 testl(result, result);
8080 jcc(Assembler::zero, TRUE_LABEL);
8081
8082 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8083 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8084 pxor(vec1, vec2);
8085
8086 ptest(vec1, vec1);
8087 jccb(Assembler::notZero, FALSE_LABEL);
8088 jmpb(TRUE_LABEL);
8089
8090 bind(COMPARE_TAIL); // limit is zero
8091 movl(limit, result);
8092 // Fallthru to tail compare
8093 }
8094
8095 // Compare 4-byte vectors
8096 andl(limit, 0xfffffffc); // vector count (in bytes)
8097 jccb(Assembler::zero, COMPARE_CHAR);
8098
8099 lea(ary1, Address(ary1, limit, Address::times_1));
8100 lea(ary2, Address(ary2, limit, Address::times_1));
8101 negptr(limit);
8102
8103 bind(COMPARE_VECTORS);
8104 movl(chr, Address(ary1, limit, Address::times_1));
8105 cmpl(chr, Address(ary2, limit, Address::times_1));
8106 jccb(Assembler::notEqual, FALSE_LABEL);
8107 addptr(limit, 4);
8108 jcc(Assembler::notZero, COMPARE_VECTORS);
8109
8110 // Compare trailing char (final 2 bytes), if any
8111 bind(COMPARE_CHAR);
8112 testl(result, 0x2); // tail char
8113 jccb(Assembler::zero, COMPARE_BYTE);
8114 load_unsigned_short(chr, Address(ary1, 0));
8115 load_unsigned_short(limit, Address(ary2, 0));
8116 cmpl(chr, limit);
8117 jccb(Assembler::notEqual, FALSE_LABEL);
8118
8119 if (is_array_equ && is_char) {
8120 bind(COMPARE_BYTE);
8121 } else {
8122 lea(ary1, Address(ary1, 2));
8123 lea(ary2, Address(ary2, 2));
8124
8125 bind(COMPARE_BYTE);
8126 testl(result, 0x1); // tail byte
8127 jccb(Assembler::zero, TRUE_LABEL);
8128 load_unsigned_byte(chr, Address(ary1, 0));
8129 load_unsigned_byte(limit, Address(ary2, 0));
8130 cmpl(chr, limit);
8131 jccb(Assembler::notEqual, FALSE_LABEL);
8132 }
8133 bind(TRUE_LABEL);
8134 movl(result, 1); // return true
8135 jmpb(DONE);
8136
8137 bind(FALSE_LABEL);
8138 xorl(result, result); // return false
8139
8140 // That's it
8141 bind(DONE);
8142 if (UseAVX >= 2) {
8143 // clean upper bits of YMM registers
8144 vpxor(vec1, vec1);
8145 vpxor(vec2, vec2);
8146 }
8147 }
8148
8149 #endif
8150
8151 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8152 Register to, Register value, Register count,
8153 Register rtmp, XMMRegister xtmp) {
8154 ShortBranchVerifier sbv(this);
8155 assert_different_registers(to, value, count, rtmp);
8156 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8157 Label L_fill_2_bytes, L_fill_4_bytes;
8158
8159 int shift = -1;
8160 switch (t) {
8161 case T_BYTE:
8162 shift = 2;
8163 break;
8164 case T_SHORT:
8165 shift = 1;
8166 break;
8167 case T_INT:
8168 shift = 0;
8169 break;
8170 default: ShouldNotReachHere();
8171 }
8172
8173 if (t == T_BYTE) {
8174 andl(value, 0xff);
8175 movl(rtmp, value);
8176 shll(rtmp, 8);
8177 orl(value, rtmp);
8178 }
8179 if (t == T_SHORT) {
8180 andl(value, 0xffff);
8181 }
8182 if (t == T_BYTE || t == T_SHORT) {
8183 movl(rtmp, value);
8184 shll(rtmp, 16);
8185 orl(value, rtmp);
8186 }
8187
8188 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8189 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8190 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8191 // align source address at 4 bytes address boundary
8192 if (t == T_BYTE) {
8193 // One byte misalignment happens only for byte arrays
8194 testptr(to, 1);
8195 jccb(Assembler::zero, L_skip_align1);
8196 movb(Address(to, 0), value);
8197 increment(to);
8198 decrement(count);
8199 BIND(L_skip_align1);
8200 }
8201 // Two bytes misalignment happens only for byte and short (char) arrays
8202 testptr(to, 2);
8203 jccb(Assembler::zero, L_skip_align2);
8204 movw(Address(to, 0), value);
8205 addptr(to, 2);
8206 subl(count, 1<<(shift-1));
8207 BIND(L_skip_align2);
8208 }
8209 if (UseSSE < 2) {
8210 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8211 // Fill 32-byte chunks
8212 subl(count, 8 << shift);
8213 jcc(Assembler::less, L_check_fill_8_bytes);
8214 align(16);
8215
8216 BIND(L_fill_32_bytes_loop);
8217
8218 for (int i = 0; i < 32; i += 4) {
8219 movl(Address(to, i), value);
8220 }
8221
8222 addptr(to, 32);
8223 subl(count, 8 << shift);
8224 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8225 BIND(L_check_fill_8_bytes);
8226 addl(count, 8 << shift);
8227 jccb(Assembler::zero, L_exit);
8228 jmpb(L_fill_8_bytes);
8229
8230 //
8231 // length is too short, just fill qwords
8232 //
8233 BIND(L_fill_8_bytes_loop);
8234 movl(Address(to, 0), value);
8235 movl(Address(to, 4), value);
8236 addptr(to, 8);
8237 BIND(L_fill_8_bytes);
8238 subl(count, 1 << (shift + 1));
8239 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8240 // fall through to fill 4 bytes
8241 } else {
8242 Label L_fill_32_bytes;
8243 if (!UseUnalignedLoadStores) {
8244 // align to 8 bytes, we know we are 4 byte aligned to start
8245 testptr(to, 4);
8246 jccb(Assembler::zero, L_fill_32_bytes);
8247 movl(Address(to, 0), value);
8248 addptr(to, 4);
8249 subl(count, 1<<shift);
8250 }
8251 BIND(L_fill_32_bytes);
8252 {
8253 assert( UseSSE >= 2, "supported cpu only" );
8254 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8255 if (UseAVX > 2) {
8256 movl(rtmp, 0xffff);
8257 kmovwl(k1, rtmp);
8258 }
8259 movdl(xtmp, value);
8260 if (UseAVX > 2 && UseUnalignedLoadStores) {
8261 // Fill 64-byte chunks
8262 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8263 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8264
8265 subl(count, 16 << shift);
8266 jcc(Assembler::less, L_check_fill_32_bytes);
8267 align(16);
8268
8269 BIND(L_fill_64_bytes_loop);
8270 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8271 addptr(to, 64);
8272 subl(count, 16 << shift);
8273 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8274
8275 BIND(L_check_fill_32_bytes);
8276 addl(count, 8 << shift);
8277 jccb(Assembler::less, L_check_fill_8_bytes);
8278 vmovdqu(Address(to, 0), xtmp);
8279 addptr(to, 32);
8280 subl(count, 8 << shift);
8281
8282 BIND(L_check_fill_8_bytes);
8283 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8284 // Fill 64-byte chunks
8285 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8286 vpbroadcastd(xtmp, xtmp);
8287
8288 subl(count, 16 << shift);
8289 jcc(Assembler::less, L_check_fill_32_bytes);
8290 align(16);
8291
8292 BIND(L_fill_64_bytes_loop);
8293 vmovdqu(Address(to, 0), xtmp);
8294 vmovdqu(Address(to, 32), xtmp);
8295 addptr(to, 64);
8296 subl(count, 16 << shift);
8297 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8298
8299 BIND(L_check_fill_32_bytes);
8300 addl(count, 8 << shift);
8301 jccb(Assembler::less, L_check_fill_8_bytes);
8302 vmovdqu(Address(to, 0), xtmp);
8303 addptr(to, 32);
8304 subl(count, 8 << shift);
8305
8306 BIND(L_check_fill_8_bytes);
8307 // clean upper bits of YMM registers
8308 movdl(xtmp, value);
8309 pshufd(xtmp, xtmp, 0);
8310 } else {
8311 // Fill 32-byte chunks
8312 pshufd(xtmp, xtmp, 0);
8313
8314 subl(count, 8 << shift);
8315 jcc(Assembler::less, L_check_fill_8_bytes);
8316 align(16);
8317
8318 BIND(L_fill_32_bytes_loop);
8319
8320 if (UseUnalignedLoadStores) {
8321 movdqu(Address(to, 0), xtmp);
8322 movdqu(Address(to, 16), xtmp);
8323 } else {
8324 movq(Address(to, 0), xtmp);
8325 movq(Address(to, 8), xtmp);
8326 movq(Address(to, 16), xtmp);
8327 movq(Address(to, 24), xtmp);
8328 }
8329
8330 addptr(to, 32);
8331 subl(count, 8 << shift);
8332 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8333
8334 BIND(L_check_fill_8_bytes);
8335 }
8336 addl(count, 8 << shift);
8337 jccb(Assembler::zero, L_exit);
8338 jmpb(L_fill_8_bytes);
8339
8340 //
8341 // length is too short, just fill qwords
8342 //
8343 BIND(L_fill_8_bytes_loop);
8344 movq(Address(to, 0), xtmp);
8345 addptr(to, 8);
8346 BIND(L_fill_8_bytes);
8347 subl(count, 1 << (shift + 1));
8348 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8349 }
8350 }
8351 // fill trailing 4 bytes
8352 BIND(L_fill_4_bytes);
8353 testl(count, 1<<shift);
8354 jccb(Assembler::zero, L_fill_2_bytes);
8355 movl(Address(to, 0), value);
8356 if (t == T_BYTE || t == T_SHORT) {
8357 addptr(to, 4);
8358 BIND(L_fill_2_bytes);
8359 // fill trailing 2 bytes
8360 testl(count, 1<<(shift-1));
8361 jccb(Assembler::zero, L_fill_byte);
8362 movw(Address(to, 0), value);
8363 if (t == T_BYTE) {
8364 addptr(to, 2);
8365 BIND(L_fill_byte);
8366 // fill trailing byte
8367 testl(count, 1);
8368 jccb(Assembler::zero, L_exit);
8369 movb(Address(to, 0), value);
8370 } else {
8371 BIND(L_fill_byte);
8372 }
8373 } else {
8374 BIND(L_fill_2_bytes);
8375 }
8376 BIND(L_exit);
8377 }
8378
8379 // encode char[] to byte[] in ISO_8859_1
8380 //@HotSpotIntrinsicCandidate
8381 //private static int implEncodeISOArray(byte[] sa, int sp,
8382 //byte[] da, int dp, int len) {
8383 // int i = 0;
8384 // for (; i < len; i++) {
8385 // char c = StringUTF16.getChar(sa, sp++);
8386 // if (c > '\u00FF')
8387 // break;
8388 // da[dp++] = (byte)c;
8389 // }
8390 // return i;
8391 //}
8392 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8393 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8394 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8395 Register tmp5, Register result) {
8396
8397 // rsi: src
8398 // rdi: dst
8399 // rdx: len
8400 // rcx: tmp5
8401 // rax: result
8402 ShortBranchVerifier sbv(this);
8403 assert_different_registers(src, dst, len, tmp5, result);
8404 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8405
8406 // set result
8407 xorl(result, result);
8408 // check for zero length
8409 testl(len, len);
8410 jcc(Assembler::zero, L_done);
8411
8412 movl(result, len);
8413
8414 // Setup pointers
8415 lea(src, Address(src, len, Address::times_2)); // char[]
8416 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8417 negptr(len);
8418
8419 if (UseSSE42Intrinsics || UseAVX >= 2) {
8420 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8421 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8422
8423 if (UseAVX >= 2) {
8424 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8425 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8426 movdl(tmp1Reg, tmp5);
8427 vpbroadcastd(tmp1Reg, tmp1Reg);
8428 jmp(L_chars_32_check);
8429
8430 bind(L_copy_32_chars);
8431 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8432 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8433 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8434 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8435 jccb(Assembler::notZero, L_copy_32_chars_exit);
8436 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8437 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8438 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8439
8440 bind(L_chars_32_check);
8441 addptr(len, 32);
8442 jcc(Assembler::lessEqual, L_copy_32_chars);
8443
8444 bind(L_copy_32_chars_exit);
8445 subptr(len, 16);
8446 jccb(Assembler::greater, L_copy_16_chars_exit);
8447
8448 } else if (UseSSE42Intrinsics) {
8449 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8450 movdl(tmp1Reg, tmp5);
8451 pshufd(tmp1Reg, tmp1Reg, 0);
8452 jmpb(L_chars_16_check);
8453 }
8454
8455 bind(L_copy_16_chars);
8456 if (UseAVX >= 2) {
8457 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8458 vptest(tmp2Reg, tmp1Reg);
8459 jcc(Assembler::notZero, L_copy_16_chars_exit);
8460 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8461 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8462 } else {
8463 if (UseAVX > 0) {
8464 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8465 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8466 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8467 } else {
8468 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8469 por(tmp2Reg, tmp3Reg);
8470 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8471 por(tmp2Reg, tmp4Reg);
8472 }
8473 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8474 jccb(Assembler::notZero, L_copy_16_chars_exit);
8475 packuswb(tmp3Reg, tmp4Reg);
8476 }
8477 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8478
8479 bind(L_chars_16_check);
8480 addptr(len, 16);
8481 jcc(Assembler::lessEqual, L_copy_16_chars);
8482
8483 bind(L_copy_16_chars_exit);
8484 if (UseAVX >= 2) {
8485 // clean upper bits of YMM registers
8486 vpxor(tmp2Reg, tmp2Reg);
8487 vpxor(tmp3Reg, tmp3Reg);
8488 vpxor(tmp4Reg, tmp4Reg);
8489 movdl(tmp1Reg, tmp5);
8490 pshufd(tmp1Reg, tmp1Reg, 0);
8491 }
8492 subptr(len, 8);
8493 jccb(Assembler::greater, L_copy_8_chars_exit);
8494
8495 bind(L_copy_8_chars);
8496 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8497 ptest(tmp3Reg, tmp1Reg);
8498 jccb(Assembler::notZero, L_copy_8_chars_exit);
8499 packuswb(tmp3Reg, tmp1Reg);
8500 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8501 addptr(len, 8);
8502 jccb(Assembler::lessEqual, L_copy_8_chars);
8503
8504 bind(L_copy_8_chars_exit);
8505 subptr(len, 8);
8506 jccb(Assembler::zero, L_done);
8507 }
8508
8509 bind(L_copy_1_char);
8510 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8511 testl(tmp5, 0xff00); // check if Unicode char
8512 jccb(Assembler::notZero, L_copy_1_char_exit);
8513 movb(Address(dst, len, Address::times_1, 0), tmp5);
8514 addptr(len, 1);
8515 jccb(Assembler::less, L_copy_1_char);
8516
8517 bind(L_copy_1_char_exit);
8518 addptr(result, len); // len is negative count of not processed elements
8519
8520 bind(L_done);
8521 }
8522
8523 #ifdef _LP64
8524 /**
8525 * Helper for multiply_to_len().
8526 */
8527 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8528 addq(dest_lo, src1);
8529 adcq(dest_hi, 0);
8530 addq(dest_lo, src2);
8531 adcq(dest_hi, 0);
8532 }
8533
8534 /**
8535 * Multiply 64 bit by 64 bit first loop.
8536 */
8537 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8538 Register y, Register y_idx, Register z,
8539 Register carry, Register product,
8540 Register idx, Register kdx) {
8541 //
8542 // jlong carry, x[], y[], z[];
8543 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8544 // huge_128 product = y[idx] * x[xstart] + carry;
8545 // z[kdx] = (jlong)product;
8546 // carry = (jlong)(product >>> 64);
8547 // }
8548 // z[xstart] = carry;
8549 //
8550
8551 Label L_first_loop, L_first_loop_exit;
8552 Label L_one_x, L_one_y, L_multiply;
8553
8554 decrementl(xstart);
8555 jcc(Assembler::negative, L_one_x);
8556
8557 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8558 rorq(x_xstart, 32); // convert big-endian to little-endian
8559
8560 bind(L_first_loop);
8561 decrementl(idx);
8562 jcc(Assembler::negative, L_first_loop_exit);
8563 decrementl(idx);
8564 jcc(Assembler::negative, L_one_y);
8565 movq(y_idx, Address(y, idx, Address::times_4, 0));
8566 rorq(y_idx, 32); // convert big-endian to little-endian
8567 bind(L_multiply);
8568 movq(product, x_xstart);
8569 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8570 addq(product, carry);
8571 adcq(rdx, 0);
8572 subl(kdx, 2);
8573 movl(Address(z, kdx, Address::times_4, 4), product);
8574 shrq(product, 32);
8575 movl(Address(z, kdx, Address::times_4, 0), product);
8576 movq(carry, rdx);
8577 jmp(L_first_loop);
8578
8579 bind(L_one_y);
8580 movl(y_idx, Address(y, 0));
8581 jmp(L_multiply);
8582
8583 bind(L_one_x);
8584 movl(x_xstart, Address(x, 0));
8585 jmp(L_first_loop);
8586
8587 bind(L_first_loop_exit);
8588 }
8589
8590 /**
8591 * Multiply 64 bit by 64 bit and add 128 bit.
8592 */
8593 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8594 Register yz_idx, Register idx,
8595 Register carry, Register product, int offset) {
8596 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8597 // z[kdx] = (jlong)product;
8598
8599 movq(yz_idx, Address(y, idx, Address::times_4, offset));
8600 rorq(yz_idx, 32); // convert big-endian to little-endian
8601 movq(product, x_xstart);
8602 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8603 movq(yz_idx, Address(z, idx, Address::times_4, offset));
8604 rorq(yz_idx, 32); // convert big-endian to little-endian
8605
8606 add2_with_carry(rdx, product, carry, yz_idx);
8607
8608 movl(Address(z, idx, Address::times_4, offset+4), product);
8609 shrq(product, 32);
8610 movl(Address(z, idx, Address::times_4, offset), product);
8611
8612 }
8613
8614 /**
8615 * Multiply 128 bit by 128 bit. Unrolled inner loop.
8616 */
8617 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
8618 Register yz_idx, Register idx, Register jdx,
8619 Register carry, Register product,
8620 Register carry2) {
8621 // jlong carry, x[], y[], z[];
8622 // int kdx = ystart+1;
8623 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8624 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
8625 // z[kdx+idx+1] = (jlong)product;
8626 // jlong carry2 = (jlong)(product >>> 64);
8627 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
8628 // z[kdx+idx] = (jlong)product;
8629 // carry = (jlong)(product >>> 64);
8630 // }
8631 // idx += 2;
8632 // if (idx > 0) {
8633 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
8634 // z[kdx+idx] = (jlong)product;
8635 // carry = (jlong)(product >>> 64);
8636 // }
8637 //
8638
8639 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8640
8641 movl(jdx, idx);
8642 andl(jdx, 0xFFFFFFFC);
8643 shrl(jdx, 2);
8644
8645 bind(L_third_loop);
8646 subl(jdx, 1);
8647 jcc(Assembler::negative, L_third_loop_exit);
8648 subl(idx, 4);
8649
8650 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
8651 movq(carry2, rdx);
8652
8653 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
8654 movq(carry, rdx);
8655 jmp(L_third_loop);
8656
8657 bind (L_third_loop_exit);
8658
8659 andl (idx, 0x3);
8660 jcc(Assembler::zero, L_post_third_loop_done);
8661
8662 Label L_check_1;
8663 subl(idx, 2);
8664 jcc(Assembler::negative, L_check_1);
8665
8666 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
8667 movq(carry, rdx);
8668
8669 bind (L_check_1);
8670 addl (idx, 0x2);
8671 andl (idx, 0x1);
8672 subl(idx, 1);
8673 jcc(Assembler::negative, L_post_third_loop_done);
8674
8675 movl(yz_idx, Address(y, idx, Address::times_4, 0));
8676 movq(product, x_xstart);
8677 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8678 movl(yz_idx, Address(z, idx, Address::times_4, 0));
8679
8680 add2_with_carry(rdx, product, yz_idx, carry);
8681
8682 movl(Address(z, idx, Address::times_4, 0), product);
8683 shrq(product, 32);
8684
8685 shlq(rdx, 32);
8686 orq(product, rdx);
8687 movq(carry, product);
8688
8689 bind(L_post_third_loop_done);
8690 }
8691
8692 /**
8693 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
8694 *
8695 */
8696 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
8697 Register carry, Register carry2,
8698 Register idx, Register jdx,
8699 Register yz_idx1, Register yz_idx2,
8700 Register tmp, Register tmp3, Register tmp4) {
8701 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
8702
8703 // jlong carry, x[], y[], z[];
8704 // int kdx = ystart+1;
8705 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8706 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
8707 // jlong carry2 = (jlong)(tmp3 >>> 64);
8708 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
8709 // carry = (jlong)(tmp4 >>> 64);
8710 // z[kdx+idx+1] = (jlong)tmp3;
8711 // z[kdx+idx] = (jlong)tmp4;
8712 // }
8713 // idx += 2;
8714 // if (idx > 0) {
8715 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
8716 // z[kdx+idx] = (jlong)yz_idx1;
8717 // carry = (jlong)(yz_idx1 >>> 64);
8718 // }
8719 //
8720
8721 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8722
8723 movl(jdx, idx);
8724 andl(jdx, 0xFFFFFFFC);
8725 shrl(jdx, 2);
8726
8727 bind(L_third_loop);
8728 subl(jdx, 1);
8729 jcc(Assembler::negative, L_third_loop_exit);
8730 subl(idx, 4);
8731
8732 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
8733 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
8734 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
8735 rorxq(yz_idx2, yz_idx2, 32);
8736
8737 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8738 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
8739
8740 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
8741 rorxq(yz_idx1, yz_idx1, 32);
8742 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8743 rorxq(yz_idx2, yz_idx2, 32);
8744
8745 if (VM_Version::supports_adx()) {
8746 adcxq(tmp3, carry);
8747 adoxq(tmp3, yz_idx1);
8748
8749 adcxq(tmp4, tmp);
8750 adoxq(tmp4, yz_idx2);
8751
8752 movl(carry, 0); // does not affect flags
8753 adcxq(carry2, carry);
8754 adoxq(carry2, carry);
8755 } else {
8756 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
8757 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
8758 }
8759 movq(carry, carry2);
8760
8761 movl(Address(z, idx, Address::times_4, 12), tmp3);
8762 shrq(tmp3, 32);
8763 movl(Address(z, idx, Address::times_4, 8), tmp3);
8764
8765 movl(Address(z, idx, Address::times_4, 4), tmp4);
8766 shrq(tmp4, 32);
8767 movl(Address(z, idx, Address::times_4, 0), tmp4);
8768
8769 jmp(L_third_loop);
8770
8771 bind (L_third_loop_exit);
8772
8773 andl (idx, 0x3);
8774 jcc(Assembler::zero, L_post_third_loop_done);
8775
8776 Label L_check_1;
8777 subl(idx, 2);
8778 jcc(Assembler::negative, L_check_1);
8779
8780 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
8781 rorxq(yz_idx1, yz_idx1, 32);
8782 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8783 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8784 rorxq(yz_idx2, yz_idx2, 32);
8785
8786 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
8787
8788 movl(Address(z, idx, Address::times_4, 4), tmp3);
8789 shrq(tmp3, 32);
8790 movl(Address(z, idx, Address::times_4, 0), tmp3);
8791 movq(carry, tmp4);
8792
8793 bind (L_check_1);
8794 addl (idx, 0x2);
8795 andl (idx, 0x1);
8796 subl(idx, 1);
8797 jcc(Assembler::negative, L_post_third_loop_done);
8798 movl(tmp4, Address(y, idx, Address::times_4, 0));
8799 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
8800 movl(tmp4, Address(z, idx, Address::times_4, 0));
8801
8802 add2_with_carry(carry2, tmp3, tmp4, carry);
8803
8804 movl(Address(z, idx, Address::times_4, 0), tmp3);
8805 shrq(tmp3, 32);
8806
8807 shlq(carry2, 32);
8808 orq(tmp3, carry2);
8809 movq(carry, tmp3);
8810
8811 bind(L_post_third_loop_done);
8812 }
8813
8814 /**
8815 * Code for BigInteger::multiplyToLen() instrinsic.
8816 *
8817 * rdi: x
8818 * rax: xlen
8819 * rsi: y
8820 * rcx: ylen
8821 * r8: z
8822 * r11: zlen
8823 * r12: tmp1
8824 * r13: tmp2
8825 * r14: tmp3
8826 * r15: tmp4
8827 * rbx: tmp5
8828 *
8829 */
8830 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
8831 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
8832 ShortBranchVerifier sbv(this);
8833 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
8834
8835 push(tmp1);
8836 push(tmp2);
8837 push(tmp3);
8838 push(tmp4);
8839 push(tmp5);
8840
8841 push(xlen);
8842 push(zlen);
8843
8844 const Register idx = tmp1;
8845 const Register kdx = tmp2;
8846 const Register xstart = tmp3;
8847
8848 const Register y_idx = tmp4;
8849 const Register carry = tmp5;
8850 const Register product = xlen;
8851 const Register x_xstart = zlen; // reuse register
8852
8853 // First Loop.
8854 //
8855 // final static long LONG_MASK = 0xffffffffL;
8856 // int xstart = xlen - 1;
8857 // int ystart = ylen - 1;
8858 // long carry = 0;
8859 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8860 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
8861 // z[kdx] = (int)product;
8862 // carry = product >>> 32;
8863 // }
8864 // z[xstart] = (int)carry;
8865 //
8866
8867 movl(idx, ylen); // idx = ylen;
8868 movl(kdx, zlen); // kdx = xlen+ylen;
8869 xorq(carry, carry); // carry = 0;
8870
8871 Label L_done;
8872
8873 movl(xstart, xlen);
8874 decrementl(xstart);
8875 jcc(Assembler::negative, L_done);
8876
8877 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
8878
8879 Label L_second_loop;
8880 testl(kdx, kdx);
8881 jcc(Assembler::zero, L_second_loop);
8882
8883 Label L_carry;
8884 subl(kdx, 1);
8885 jcc(Assembler::zero, L_carry);
8886
8887 movl(Address(z, kdx, Address::times_4, 0), carry);
8888 shrq(carry, 32);
8889 subl(kdx, 1);
8890
8891 bind(L_carry);
8892 movl(Address(z, kdx, Address::times_4, 0), carry);
8893
8894 // Second and third (nested) loops.
8895 //
8896 // for (int i = xstart-1; i >= 0; i--) { // Second loop
8897 // carry = 0;
8898 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
8899 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
8900 // (z[k] & LONG_MASK) + carry;
8901 // z[k] = (int)product;
8902 // carry = product >>> 32;
8903 // }
8904 // z[i] = (int)carry;
8905 // }
8906 //
8907 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
8908
8909 const Register jdx = tmp1;
8910
8911 bind(L_second_loop);
8912 xorl(carry, carry); // carry = 0;
8913 movl(jdx, ylen); // j = ystart+1
8914
8915 subl(xstart, 1); // i = xstart-1;
8916 jcc(Assembler::negative, L_done);
8917
8918 push (z);
8919
8920 Label L_last_x;
8921 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
8922 subl(xstart, 1); // i = xstart-1;
8923 jcc(Assembler::negative, L_last_x);
8924
8925 if (UseBMI2Instructions) {
8926 movq(rdx, Address(x, xstart, Address::times_4, 0));
8927 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
8928 } else {
8929 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8930 rorq(x_xstart, 32); // convert big-endian to little-endian
8931 }
8932
8933 Label L_third_loop_prologue;
8934 bind(L_third_loop_prologue);
8935
8936 push (x);
8937 push (xstart);
8938 push (ylen);
8939
8940
8941 if (UseBMI2Instructions) {
8942 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
8943 } else { // !UseBMI2Instructions
8944 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
8945 }
8946
8947 pop(ylen);
8948 pop(xlen);
8949 pop(x);
8950 pop(z);
8951
8952 movl(tmp3, xlen);
8953 addl(tmp3, 1);
8954 movl(Address(z, tmp3, Address::times_4, 0), carry);
8955 subl(tmp3, 1);
8956 jccb(Assembler::negative, L_done);
8957
8958 shrq(carry, 32);
8959 movl(Address(z, tmp3, Address::times_4, 0), carry);
8960 jmp(L_second_loop);
8961
8962 // Next infrequent code is moved outside loops.
8963 bind(L_last_x);
8964 if (UseBMI2Instructions) {
8965 movl(rdx, Address(x, 0));
8966 } else {
8967 movl(x_xstart, Address(x, 0));
8968 }
8969 jmp(L_third_loop_prologue);
8970
8971 bind(L_done);
8972
8973 pop(zlen);
8974 pop(xlen);
8975
8976 pop(tmp5);
8977 pop(tmp4);
8978 pop(tmp3);
8979 pop(tmp2);
8980 pop(tmp1);
8981 }
8982
8983 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
8984 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
8985 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
8986 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
8987 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
8988 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
8989 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
8990 Label SAME_TILL_END, DONE;
8991 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
8992
8993 //scale is in rcx in both Win64 and Unix
8994 ShortBranchVerifier sbv(this);
8995
8996 shlq(length);
8997 xorq(result, result);
8998
8999 if ((UseAVX > 2) &&
9000 VM_Version::supports_avx512vlbw()) {
9001 set_vector_masking(); // opening of the stub context for programming mask registers
9002 cmpq(length, 64);
9003 jcc(Assembler::less, VECTOR32_TAIL);
9004 movq(tmp1, length);
9005 andq(tmp1, 0x3F); // tail count
9006 andq(length, ~(0x3F)); //vector count
9007
9008 bind(VECTOR64_LOOP);
9009 // AVX512 code to compare 64 byte vectors.
9010 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9011 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9012 kortestql(k7, k7);
9013 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9014 addq(result, 64);
9015 subq(length, 64);
9016 jccb(Assembler::notZero, VECTOR64_LOOP);
9017
9018 //bind(VECTOR64_TAIL);
9019 testq(tmp1, tmp1);
9020 jcc(Assembler::zero, SAME_TILL_END);
9021
9022 bind(VECTOR64_TAIL);
9023 // AVX512 code to compare upto 63 byte vectors.
9024 // Save k1
9025 kmovql(k3, k1);
9026 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9027 shlxq(tmp2, tmp2, tmp1);
9028 notq(tmp2);
9029 kmovql(k1, tmp2);
9030
9031 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9032 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9033
9034 ktestql(k7, k1);
9035 // Restore k1
9036 kmovql(k1, k3);
9037 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9038
9039 bind(VECTOR64_NOT_EQUAL);
9040 kmovql(tmp1, k7);
9041 notq(tmp1);
9042 tzcntq(tmp1, tmp1);
9043 addq(result, tmp1);
9044 shrq(result);
9045 jmp(DONE);
9046 bind(VECTOR32_TAIL);
9047 clear_vector_masking(); // closing of the stub context for programming mask registers
9048 }
9049
9050 cmpq(length, 8);
9051 jcc(Assembler::equal, VECTOR8_LOOP);
9052 jcc(Assembler::less, VECTOR4_TAIL);
9053
9054 if (UseAVX >= 2) {
9055
9056 cmpq(length, 16);
9057 jcc(Assembler::equal, VECTOR16_LOOP);
9058 jcc(Assembler::less, VECTOR8_LOOP);
9059
9060 cmpq(length, 32);
9061 jccb(Assembler::less, VECTOR16_TAIL);
9062
9063 subq(length, 32);
9064 bind(VECTOR32_LOOP);
9065 vmovdqu(rymm0, Address(obja, result));
9066 vmovdqu(rymm1, Address(objb, result));
9067 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9068 vptest(rymm2, rymm2);
9069 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9070 addq(result, 32);
9071 subq(length, 32);
9072 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9073 addq(length, 32);
9074 jcc(Assembler::equal, SAME_TILL_END);
9075 //falling through if less than 32 bytes left //close the branch here.
9076
9077 bind(VECTOR16_TAIL);
9078 cmpq(length, 16);
9079 jccb(Assembler::less, VECTOR8_TAIL);
9080 bind(VECTOR16_LOOP);
9081 movdqu(rymm0, Address(obja, result));
9082 movdqu(rymm1, Address(objb, result));
9083 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9084 ptest(rymm2, rymm2);
9085 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9086 addq(result, 16);
9087 subq(length, 16);
9088 jcc(Assembler::equal, SAME_TILL_END);
9089 //falling through if less than 16 bytes left
9090 } else {//regular intrinsics
9091
9092 cmpq(length, 16);
9093 jccb(Assembler::less, VECTOR8_TAIL);
9094
9095 subq(length, 16);
9096 bind(VECTOR16_LOOP);
9097 movdqu(rymm0, Address(obja, result));
9098 movdqu(rymm1, Address(objb, result));
9099 pxor(rymm0, rymm1);
9100 ptest(rymm0, rymm0);
9101 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9102 addq(result, 16);
9103 subq(length, 16);
9104 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9105 addq(length, 16);
9106 jcc(Assembler::equal, SAME_TILL_END);
9107 //falling through if less than 16 bytes left
9108 }
9109
9110 bind(VECTOR8_TAIL);
9111 cmpq(length, 8);
9112 jccb(Assembler::less, VECTOR4_TAIL);
9113 bind(VECTOR8_LOOP);
9114 movq(tmp1, Address(obja, result));
9115 movq(tmp2, Address(objb, result));
9116 xorq(tmp1, tmp2);
9117 testq(tmp1, tmp1);
9118 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9119 addq(result, 8);
9120 subq(length, 8);
9121 jcc(Assembler::equal, SAME_TILL_END);
9122 //falling through if less than 8 bytes left
9123
9124 bind(VECTOR4_TAIL);
9125 cmpq(length, 4);
9126 jccb(Assembler::less, BYTES_TAIL);
9127 bind(VECTOR4_LOOP);
9128 movl(tmp1, Address(obja, result));
9129 xorl(tmp1, Address(objb, result));
9130 testl(tmp1, tmp1);
9131 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9132 addq(result, 4);
9133 subq(length, 4);
9134 jcc(Assembler::equal, SAME_TILL_END);
9135 //falling through if less than 4 bytes left
9136
9137 bind(BYTES_TAIL);
9138 bind(BYTES_LOOP);
9139 load_unsigned_byte(tmp1, Address(obja, result));
9140 load_unsigned_byte(tmp2, Address(objb, result));
9141 xorl(tmp1, tmp2);
9142 testl(tmp1, tmp1);
9143 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9144 decq(length);
9145 jccb(Assembler::zero, SAME_TILL_END);
9146 incq(result);
9147 load_unsigned_byte(tmp1, Address(obja, result));
9148 load_unsigned_byte(tmp2, Address(objb, result));
9149 xorl(tmp1, tmp2);
9150 testl(tmp1, tmp1);
9151 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9152 decq(length);
9153 jccb(Assembler::zero, SAME_TILL_END);
9154 incq(result);
9155 load_unsigned_byte(tmp1, Address(obja, result));
9156 load_unsigned_byte(tmp2, Address(objb, result));
9157 xorl(tmp1, tmp2);
9158 testl(tmp1, tmp1);
9159 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9160 jmpb(SAME_TILL_END);
9161
9162 if (UseAVX >= 2) {
9163 bind(VECTOR32_NOT_EQUAL);
9164 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9165 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9166 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9167 vpmovmskb(tmp1, rymm0);
9168 bsfq(tmp1, tmp1);
9169 addq(result, tmp1);
9170 shrq(result);
9171 jmpb(DONE);
9172 }
9173
9174 bind(VECTOR16_NOT_EQUAL);
9175 if (UseAVX >= 2) {
9176 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9177 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9178 pxor(rymm0, rymm2);
9179 } else {
9180 pcmpeqb(rymm2, rymm2);
9181 pxor(rymm0, rymm1);
9182 pcmpeqb(rymm0, rymm1);
9183 pxor(rymm0, rymm2);
9184 }
9185 pmovmskb(tmp1, rymm0);
9186 bsfq(tmp1, tmp1);
9187 addq(result, tmp1);
9188 shrq(result);
9189 jmpb(DONE);
9190
9191 bind(VECTOR8_NOT_EQUAL);
9192 bind(VECTOR4_NOT_EQUAL);
9193 bsfq(tmp1, tmp1);
9194 shrq(tmp1, 3);
9195 addq(result, tmp1);
9196 bind(BYTES_NOT_EQUAL);
9197 shrq(result);
9198 jmpb(DONE);
9199
9200 bind(SAME_TILL_END);
9201 mov64(result, -1);
9202
9203 bind(DONE);
9204 }
9205
9206 //Helper functions for square_to_len()
9207
9208 /**
9209 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9210 * Preserves x and z and modifies rest of the registers.
9211 */
9212 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9213 // Perform square and right shift by 1
9214 // Handle odd xlen case first, then for even xlen do the following
9215 // jlong carry = 0;
9216 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9217 // huge_128 product = x[j:j+1] * x[j:j+1];
9218 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9219 // z[i+2:i+3] = (jlong)(product >>> 1);
9220 // carry = (jlong)product;
9221 // }
9222
9223 xorq(tmp5, tmp5); // carry
9224 xorq(rdxReg, rdxReg);
9225 xorl(tmp1, tmp1); // index for x
9226 xorl(tmp4, tmp4); // index for z
9227
9228 Label L_first_loop, L_first_loop_exit;
9229
9230 testl(xlen, 1);
9231 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9232
9233 // Square and right shift by 1 the odd element using 32 bit multiply
9234 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9235 imulq(raxReg, raxReg);
9236 shrq(raxReg, 1);
9237 adcq(tmp5, 0);
9238 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9239 incrementl(tmp1);
9240 addl(tmp4, 2);
9241
9242 // Square and right shift by 1 the rest using 64 bit multiply
9243 bind(L_first_loop);
9244 cmpptr(tmp1, xlen);
9245 jccb(Assembler::equal, L_first_loop_exit);
9246
9247 // Square
9248 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9249 rorq(raxReg, 32); // convert big-endian to little-endian
9250 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9251
9252 // Right shift by 1 and save carry
9253 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9254 rcrq(rdxReg, 1);
9255 rcrq(raxReg, 1);
9256 adcq(tmp5, 0);
9257
9258 // Store result in z
9259 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9260 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9261
9262 // Update indices for x and z
9263 addl(tmp1, 2);
9264 addl(tmp4, 4);
9265 jmp(L_first_loop);
9266
9267 bind(L_first_loop_exit);
9268 }
9269
9270
9271 /**
9272 * Perform the following multiply add operation using BMI2 instructions
9273 * carry:sum = sum + op1*op2 + carry
9274 * op2 should be in rdx
9275 * op2 is preserved, all other registers are modified
9276 */
9277 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9278 // assert op2 is rdx
9279 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9280 addq(sum, carry);
9281 adcq(tmp2, 0);
9282 addq(sum, op1);
9283 adcq(tmp2, 0);
9284 movq(carry, tmp2);
9285 }
9286
9287 /**
9288 * Perform the following multiply add operation:
9289 * carry:sum = sum + op1*op2 + carry
9290 * Preserves op1, op2 and modifies rest of registers
9291 */
9292 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9293 // rdx:rax = op1 * op2
9294 movq(raxReg, op2);
9295 mulq(op1);
9296
9297 // rdx:rax = sum + carry + rdx:rax
9298 addq(sum, carry);
9299 adcq(rdxReg, 0);
9300 addq(sum, raxReg);
9301 adcq(rdxReg, 0);
9302
9303 // carry:sum = rdx:sum
9304 movq(carry, rdxReg);
9305 }
9306
9307 /**
9308 * Add 64 bit long carry into z[] with carry propogation.
9309 * Preserves z and carry register values and modifies rest of registers.
9310 *
9311 */
9312 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9313 Label L_fourth_loop, L_fourth_loop_exit;
9314
9315 movl(tmp1, 1);
9316 subl(zlen, 2);
9317 addq(Address(z, zlen, Address::times_4, 0), carry);
9318
9319 bind(L_fourth_loop);
9320 jccb(Assembler::carryClear, L_fourth_loop_exit);
9321 subl(zlen, 2);
9322 jccb(Assembler::negative, L_fourth_loop_exit);
9323 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9324 jmp(L_fourth_loop);
9325 bind(L_fourth_loop_exit);
9326 }
9327
9328 /**
9329 * Shift z[] left by 1 bit.
9330 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9331 *
9332 */
9333 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9334
9335 Label L_fifth_loop, L_fifth_loop_exit;
9336
9337 // Fifth loop
9338 // Perform primitiveLeftShift(z, zlen, 1)
9339
9340 const Register prev_carry = tmp1;
9341 const Register new_carry = tmp4;
9342 const Register value = tmp2;
9343 const Register zidx = tmp3;
9344
9345 // int zidx, carry;
9346 // long value;
9347 // carry = 0;
9348 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9349 // (carry:value) = (z[i] << 1) | carry ;
9350 // z[i] = value;
9351 // }
9352
9353 movl(zidx, zlen);
9354 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9355
9356 bind(L_fifth_loop);
9357 decl(zidx); // Use decl to preserve carry flag
9358 decl(zidx);
9359 jccb(Assembler::negative, L_fifth_loop_exit);
9360
9361 if (UseBMI2Instructions) {
9362 movq(value, Address(z, zidx, Address::times_4, 0));
9363 rclq(value, 1);
9364 rorxq(value, value, 32);
9365 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9366 }
9367 else {
9368 // clear new_carry
9369 xorl(new_carry, new_carry);
9370
9371 // Shift z[i] by 1, or in previous carry and save new carry
9372 movq(value, Address(z, zidx, Address::times_4, 0));
9373 shlq(value, 1);
9374 adcl(new_carry, 0);
9375
9376 orq(value, prev_carry);
9377 rorq(value, 0x20);
9378 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9379
9380 // Set previous carry = new carry
9381 movl(prev_carry, new_carry);
9382 }
9383 jmp(L_fifth_loop);
9384
9385 bind(L_fifth_loop_exit);
9386 }
9387
9388
9389 /**
9390 * Code for BigInteger::squareToLen() intrinsic
9391 *
9392 * rdi: x
9393 * rsi: len
9394 * r8: z
9395 * rcx: zlen
9396 * r12: tmp1
9397 * r13: tmp2
9398 * r14: tmp3
9399 * r15: tmp4
9400 * rbx: tmp5
9401 *
9402 */
9403 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9404
9405 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9406 push(tmp1);
9407 push(tmp2);
9408 push(tmp3);
9409 push(tmp4);
9410 push(tmp5);
9411
9412 // First loop
9413 // Store the squares, right shifted one bit (i.e., divided by 2).
9414 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9415
9416 // Add in off-diagonal sums.
9417 //
9418 // Second, third (nested) and fourth loops.
9419 // zlen +=2;
9420 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9421 // carry = 0;
9422 // long op2 = x[xidx:xidx+1];
9423 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9424 // k -= 2;
9425 // long op1 = x[j:j+1];
9426 // long sum = z[k:k+1];
9427 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9428 // z[k:k+1] = sum;
9429 // }
9430 // add_one_64(z, k, carry, tmp_regs);
9431 // }
9432
9433 const Register carry = tmp5;
9434 const Register sum = tmp3;
9435 const Register op1 = tmp4;
9436 Register op2 = tmp2;
9437
9438 push(zlen);
9439 push(len);
9440 addl(zlen,2);
9441 bind(L_second_loop);
9442 xorq(carry, carry);
9443 subl(zlen, 4);
9444 subl(len, 2);
9445 push(zlen);
9446 push(len);
9447 cmpl(len, 0);
9448 jccb(Assembler::lessEqual, L_second_loop_exit);
9449
9450 // Multiply an array by one 64 bit long.
9451 if (UseBMI2Instructions) {
9452 op2 = rdxReg;
9453 movq(op2, Address(x, len, Address::times_4, 0));
9454 rorxq(op2, op2, 32);
9455 }
9456 else {
9457 movq(op2, Address(x, len, Address::times_4, 0));
9458 rorq(op2, 32);
9459 }
9460
9461 bind(L_third_loop);
9462 decrementl(len);
9463 jccb(Assembler::negative, L_third_loop_exit);
9464 decrementl(len);
9465 jccb(Assembler::negative, L_last_x);
9466
9467 movq(op1, Address(x, len, Address::times_4, 0));
9468 rorq(op1, 32);
9469
9470 bind(L_multiply);
9471 subl(zlen, 2);
9472 movq(sum, Address(z, zlen, Address::times_4, 0));
9473
9474 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9475 if (UseBMI2Instructions) {
9476 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9477 }
9478 else {
9479 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9480 }
9481
9482 movq(Address(z, zlen, Address::times_4, 0), sum);
9483
9484 jmp(L_third_loop);
9485 bind(L_third_loop_exit);
9486
9487 // Fourth loop
9488 // Add 64 bit long carry into z with carry propogation.
9489 // Uses offsetted zlen.
9490 add_one_64(z, zlen, carry, tmp1);
9491
9492 pop(len);
9493 pop(zlen);
9494 jmp(L_second_loop);
9495
9496 // Next infrequent code is moved outside loops.
9497 bind(L_last_x);
9498 movl(op1, Address(x, 0));
9499 jmp(L_multiply);
9500
9501 bind(L_second_loop_exit);
9502 pop(len);
9503 pop(zlen);
9504 pop(len);
9505 pop(zlen);
9506
9507 // Fifth loop
9508 // Shift z left 1 bit.
9509 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9510
9511 // z[zlen-1] |= x[len-1] & 1;
9512 movl(tmp3, Address(x, len, Address::times_4, -4));
9513 andl(tmp3, 1);
9514 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9515
9516 pop(tmp5);
9517 pop(tmp4);
9518 pop(tmp3);
9519 pop(tmp2);
9520 pop(tmp1);
9521 }
9522
9523 /**
9524 * Helper function for mul_add()
9525 * Multiply the in[] by int k and add to out[] starting at offset offs using
9526 * 128 bit by 32 bit multiply and return the carry in tmp5.
9527 * Only quad int aligned length of in[] is operated on in this function.
9528 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9529 * This function preserves out, in and k registers.
9530 * len and offset point to the appropriate index in "in" & "out" correspondingly
9531 * tmp5 has the carry.
9532 * other registers are temporary and are modified.
9533 *
9534 */
9535 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9536 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9537 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9538
9539 Label L_first_loop, L_first_loop_exit;
9540
9541 movl(tmp1, len);
9542 shrl(tmp1, 2);
9543
9544 bind(L_first_loop);
9545 subl(tmp1, 1);
9546 jccb(Assembler::negative, L_first_loop_exit);
9547
9548 subl(len, 4);
9549 subl(offset, 4);
9550
9551 Register op2 = tmp2;
9552 const Register sum = tmp3;
9553 const Register op1 = tmp4;
9554 const Register carry = tmp5;
9555
9556 if (UseBMI2Instructions) {
9557 op2 = rdxReg;
9558 }
9559
9560 movq(op1, Address(in, len, Address::times_4, 8));
9561 rorq(op1, 32);
9562 movq(sum, Address(out, offset, Address::times_4, 8));
9563 rorq(sum, 32);
9564 if (UseBMI2Instructions) {
9565 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9566 }
9567 else {
9568 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9569 }
9570 // Store back in big endian from little endian
9571 rorq(sum, 0x20);
9572 movq(Address(out, offset, Address::times_4, 8), sum);
9573
9574 movq(op1, Address(in, len, Address::times_4, 0));
9575 rorq(op1, 32);
9576 movq(sum, Address(out, offset, Address::times_4, 0));
9577 rorq(sum, 32);
9578 if (UseBMI2Instructions) {
9579 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9580 }
9581 else {
9582 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9583 }
9584 // Store back in big endian from little endian
9585 rorq(sum, 0x20);
9586 movq(Address(out, offset, Address::times_4, 0), sum);
9587
9588 jmp(L_first_loop);
9589 bind(L_first_loop_exit);
9590 }
9591
9592 /**
9593 * Code for BigInteger::mulAdd() intrinsic
9594 *
9595 * rdi: out
9596 * rsi: in
9597 * r11: offs (out.length - offset)
9598 * rcx: len
9599 * r8: k
9600 * r12: tmp1
9601 * r13: tmp2
9602 * r14: tmp3
9603 * r15: tmp4
9604 * rbx: tmp5
9605 * Multiply the in[] by word k and add to out[], return the carry in rax
9606 */
9607 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9608 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9609 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9610
9611 Label L_carry, L_last_in, L_done;
9612
9613 // carry = 0;
9614 // for (int j=len-1; j >= 0; j--) {
9615 // long product = (in[j] & LONG_MASK) * kLong +
9616 // (out[offs] & LONG_MASK) + carry;
9617 // out[offs--] = (int)product;
9618 // carry = product >>> 32;
9619 // }
9620 //
9621 push(tmp1);
9622 push(tmp2);
9623 push(tmp3);
9624 push(tmp4);
9625 push(tmp5);
9626
9627 Register op2 = tmp2;
9628 const Register sum = tmp3;
9629 const Register op1 = tmp4;
9630 const Register carry = tmp5;
9631
9632 if (UseBMI2Instructions) {
9633 op2 = rdxReg;
9634 movl(op2, k);
9635 }
9636 else {
9637 movl(op2, k);
9638 }
9639
9640 xorq(carry, carry);
9641
9642 //First loop
9643
9644 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
9645 //The carry is in tmp5
9646 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
9647
9648 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
9649 decrementl(len);
9650 jccb(Assembler::negative, L_carry);
9651 decrementl(len);
9652 jccb(Assembler::negative, L_last_in);
9653
9654 movq(op1, Address(in, len, Address::times_4, 0));
9655 rorq(op1, 32);
9656
9657 subl(offs, 2);
9658 movq(sum, Address(out, offs, Address::times_4, 0));
9659 rorq(sum, 32);
9660
9661 if (UseBMI2Instructions) {
9662 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9663 }
9664 else {
9665 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9666 }
9667
9668 // Store back in big endian from little endian
9669 rorq(sum, 0x20);
9670 movq(Address(out, offs, Address::times_4, 0), sum);
9671
9672 testl(len, len);
9673 jccb(Assembler::zero, L_carry);
9674
9675 //Multiply the last in[] entry, if any
9676 bind(L_last_in);
9677 movl(op1, Address(in, 0));
9678 movl(sum, Address(out, offs, Address::times_4, -4));
9679
9680 movl(raxReg, k);
9681 mull(op1); //tmp4 * eax -> edx:eax
9682 addl(sum, carry);
9683 adcl(rdxReg, 0);
9684 addl(sum, raxReg);
9685 adcl(rdxReg, 0);
9686 movl(carry, rdxReg);
9687
9688 movl(Address(out, offs, Address::times_4, -4), sum);
9689
9690 bind(L_carry);
9691 //return tmp5/carry as carry in rax
9692 movl(rax, carry);
9693
9694 bind(L_done);
9695 pop(tmp5);
9696 pop(tmp4);
9697 pop(tmp3);
9698 pop(tmp2);
9699 pop(tmp1);
9700 }
9701 #endif
9702
9703 /**
9704 * Emits code to update CRC-32 with a byte value according to constants in table
9705 *
9706 * @param [in,out]crc Register containing the crc.
9707 * @param [in]val Register containing the byte to fold into the CRC.
9708 * @param [in]table Register containing the table of crc constants.
9709 *
9710 * uint32_t crc;
9711 * val = crc_table[(val ^ crc) & 0xFF];
9712 * crc = val ^ (crc >> 8);
9713 *
9714 */
9715 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
9716 xorl(val, crc);
9717 andl(val, 0xFF);
9718 shrl(crc, 8); // unsigned shift
9719 xorl(crc, Address(table, val, Address::times_4, 0));
9720 }
9721
9722 /**
9723 * Fold four 128-bit data chunks
9724 */
9725 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
9726 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
9727 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
9728 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
9729 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
9730 }
9731
9732 /**
9733 * Fold 128-bit data chunk
9734 */
9735 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
9736 if (UseAVX > 0) {
9737 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
9738 vpclmulldq(xcrc, xK, xcrc); // [63:0]
9739 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
9740 pxor(xcrc, xtmp);
9741 } else {
9742 movdqa(xtmp, xcrc);
9743 pclmulhdq(xtmp, xK); // [123:64]
9744 pclmulldq(xcrc, xK); // [63:0]
9745 pxor(xcrc, xtmp);
9746 movdqu(xtmp, Address(buf, offset));
9747 pxor(xcrc, xtmp);
9748 }
9749 }
9750
9751 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
9752 if (UseAVX > 0) {
9753 vpclmulhdq(xtmp, xK, xcrc);
9754 vpclmulldq(xcrc, xK, xcrc);
9755 pxor(xcrc, xbuf);
9756 pxor(xcrc, xtmp);
9757 } else {
9758 movdqa(xtmp, xcrc);
9759 pclmulhdq(xtmp, xK);
9760 pclmulldq(xcrc, xK);
9761 pxor(xcrc, xbuf);
9762 pxor(xcrc, xtmp);
9763 }
9764 }
9765
9766 /**
9767 * 8-bit folds to compute 32-bit CRC
9768 *
9769 * uint64_t xcrc;
9770 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
9771 */
9772 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
9773 movdl(tmp, xcrc);
9774 andl(tmp, 0xFF);
9775 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
9776 psrldq(xcrc, 1); // unsigned shift one byte
9777 pxor(xcrc, xtmp);
9778 }
9779
9780 /**
9781 * uint32_t crc;
9782 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
9783 */
9784 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
9785 movl(tmp, crc);
9786 andl(tmp, 0xFF);
9787 shrl(crc, 8);
9788 xorl(crc, Address(table, tmp, Address::times_4, 0));
9789 }
9790
9791 /**
9792 * @param crc register containing existing CRC (32-bit)
9793 * @param buf register pointing to input byte buffer (byte*)
9794 * @param len register containing number of bytes
9795 * @param table register that will contain address of CRC table
9796 * @param tmp scratch register
9797 */
9798 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
9799 assert_different_registers(crc, buf, len, table, tmp, rax);
9800
9801 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
9802 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
9803
9804 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
9805 // context for the registers used, where all instructions below are using 128-bit mode
9806 // On EVEX without VL and BW, these instructions will all be AVX.
9807 if (VM_Version::supports_avx512vlbw()) {
9808 movl(tmp, 0xffff);
9809 kmovwl(k1, tmp);
9810 }
9811
9812 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
9813 notl(crc); // ~crc
9814 cmpl(len, 16);
9815 jcc(Assembler::less, L_tail);
9816
9817 // Align buffer to 16 bytes
9818 movl(tmp, buf);
9819 andl(tmp, 0xF);
9820 jccb(Assembler::zero, L_aligned);
9821 subl(tmp, 16);
9822 addl(len, tmp);
9823
9824 align(4);
9825 BIND(L_align_loop);
9826 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9827 update_byte_crc32(crc, rax, table);
9828 increment(buf);
9829 incrementl(tmp);
9830 jccb(Assembler::less, L_align_loop);
9831
9832 BIND(L_aligned);
9833 movl(tmp, len); // save
9834 shrl(len, 4);
9835 jcc(Assembler::zero, L_tail_restore);
9836
9837 // Fold total 512 bits of polynomial on each iteration
9838 if (VM_Version::supports_vpclmulqdq()) {
9839 Label Parallel_loop, L_No_Parallel;
9840
9841 cmpl(len, 8);
9842 jccb(Assembler::less, L_No_Parallel);
9843
9844 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9845 evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
9846 movdl(xmm5, crc);
9847 evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
9848 addptr(buf, 64);
9849 subl(len, 7);
9850 evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
9851
9852 BIND(Parallel_loop);
9853 fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
9854 addptr(buf, 64);
9855 subl(len, 4);
9856 jcc(Assembler::greater, Parallel_loop);
9857
9858 vextracti64x2(xmm2, xmm1, 0x01);
9859 vextracti64x2(xmm3, xmm1, 0x02);
9860 vextracti64x2(xmm4, xmm1, 0x03);
9861 jmp(L_fold_512b);
9862
9863 BIND(L_No_Parallel);
9864 }
9865 // Fold crc into first bytes of vector
9866 movdqa(xmm1, Address(buf, 0));
9867 movdl(rax, xmm1);
9868 xorl(crc, rax);
9869 if (VM_Version::supports_sse4_1()) {
9870 pinsrd(xmm1, crc, 0);
9871 } else {
9872 pinsrw(xmm1, crc, 0);
9873 shrl(crc, 16);
9874 pinsrw(xmm1, crc, 1);
9875 }
9876 addptr(buf, 16);
9877 subl(len, 4); // len > 0
9878 jcc(Assembler::less, L_fold_tail);
9879
9880 movdqa(xmm2, Address(buf, 0));
9881 movdqa(xmm3, Address(buf, 16));
9882 movdqa(xmm4, Address(buf, 32));
9883 addptr(buf, 48);
9884 subl(len, 3);
9885 jcc(Assembler::lessEqual, L_fold_512b);
9886
9887 // Fold total 512 bits of polynomial on each iteration,
9888 // 128 bits per each of 4 parallel streams.
9889 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9890
9891 align(32);
9892 BIND(L_fold_512b_loop);
9893 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9894 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
9895 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
9896 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
9897 addptr(buf, 64);
9898 subl(len, 4);
9899 jcc(Assembler::greater, L_fold_512b_loop);
9900
9901 // Fold 512 bits to 128 bits.
9902 BIND(L_fold_512b);
9903 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9904 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
9905 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
9906 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
9907
9908 // Fold the rest of 128 bits data chunks
9909 BIND(L_fold_tail);
9910 addl(len, 3);
9911 jccb(Assembler::lessEqual, L_fold_128b);
9912 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9913
9914 BIND(L_fold_tail_loop);
9915 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
9916 addptr(buf, 16);
9917 decrementl(len);
9918 jccb(Assembler::greater, L_fold_tail_loop);
9919
9920 // Fold 128 bits in xmm1 down into 32 bits in crc register.
9921 BIND(L_fold_128b);
9922 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
9923 if (UseAVX > 0) {
9924 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
9925 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
9926 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
9927 } else {
9928 movdqa(xmm2, xmm0);
9929 pclmulqdq(xmm2, xmm1, 0x1);
9930 movdqa(xmm3, xmm0);
9931 pand(xmm3, xmm2);
9932 pclmulqdq(xmm0, xmm3, 0x1);
9933 }
9934 psrldq(xmm1, 8);
9935 psrldq(xmm2, 4);
9936 pxor(xmm0, xmm1);
9937 pxor(xmm0, xmm2);
9938
9939 // 8 8-bit folds to compute 32-bit CRC.
9940 for (int j = 0; j < 4; j++) {
9941 fold_8bit_crc32(xmm0, table, xmm1, rax);
9942 }
9943 movdl(crc, xmm0); // mov 32 bits to general register
9944 for (int j = 0; j < 4; j++) {
9945 fold_8bit_crc32(crc, table, rax);
9946 }
9947
9948 BIND(L_tail_restore);
9949 movl(len, tmp); // restore
9950 BIND(L_tail);
9951 andl(len, 0xf);
9952 jccb(Assembler::zero, L_exit);
9953
9954 // Fold the rest of bytes
9955 align(4);
9956 BIND(L_tail_loop);
9957 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9958 update_byte_crc32(crc, rax, table);
9959 increment(buf);
9960 decrementl(len);
9961 jccb(Assembler::greater, L_tail_loop);
9962
9963 BIND(L_exit);
9964 notl(crc); // ~c
9965 }
9966
9967 #ifdef _LP64
9968 // S. Gueron / Information Processing Letters 112 (2012) 184
9969 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9970 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9971 // Output: the 64-bit carry-less product of B * CONST
9972 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9973 Register tmp1, Register tmp2, Register tmp3) {
9974 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9975 if (n > 0) {
9976 addq(tmp3, n * 256 * 8);
9977 }
9978 // Q1 = TABLEExt[n][B & 0xFF];
9979 movl(tmp1, in);
9980 andl(tmp1, 0x000000FF);
9981 shll(tmp1, 3);
9982 addq(tmp1, tmp3);
9983 movq(tmp1, Address(tmp1, 0));
9984
9985 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9986 movl(tmp2, in);
9987 shrl(tmp2, 8);
9988 andl(tmp2, 0x000000FF);
9989 shll(tmp2, 3);
9990 addq(tmp2, tmp3);
9991 movq(tmp2, Address(tmp2, 0));
9992
9993 shlq(tmp2, 8);
9994 xorq(tmp1, tmp2);
9995
9996 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9997 movl(tmp2, in);
9998 shrl(tmp2, 16);
9999 andl(tmp2, 0x000000FF);
10000 shll(tmp2, 3);
10001 addq(tmp2, tmp3);
10002 movq(tmp2, Address(tmp2, 0));
10003
10004 shlq(tmp2, 16);
10005 xorq(tmp1, tmp2);
10006
10007 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10008 shrl(in, 24);
10009 andl(in, 0x000000FF);
10010 shll(in, 3);
10011 addq(in, tmp3);
10012 movq(in, Address(in, 0));
10013
10014 shlq(in, 24);
10015 xorq(in, tmp1);
10016 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10017 }
10018
10019 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10020 Register in_out,
10021 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10022 XMMRegister w_xtmp2,
10023 Register tmp1,
10024 Register n_tmp2, Register n_tmp3) {
10025 if (is_pclmulqdq_supported) {
10026 movdl(w_xtmp1, in_out); // modified blindly
10027
10028 movl(tmp1, const_or_pre_comp_const_index);
10029 movdl(w_xtmp2, tmp1);
10030 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10031
10032 movdq(in_out, w_xtmp1);
10033 } else {
10034 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10035 }
10036 }
10037
10038 // Recombination Alternative 2: No bit-reflections
10039 // T1 = (CRC_A * U1) << 1
10040 // T2 = (CRC_B * U2) << 1
10041 // C1 = T1 >> 32
10042 // C2 = T2 >> 32
10043 // T1 = T1 & 0xFFFFFFFF
10044 // T2 = T2 & 0xFFFFFFFF
10045 // T1 = CRC32(0, T1)
10046 // T2 = CRC32(0, T2)
10047 // C1 = C1 ^ T1
10048 // C2 = C2 ^ T2
10049 // CRC = C1 ^ C2 ^ CRC_C
10050 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10051 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10052 Register tmp1, Register tmp2,
10053 Register n_tmp3) {
10054 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10055 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10056 shlq(in_out, 1);
10057 movl(tmp1, in_out);
10058 shrq(in_out, 32);
10059 xorl(tmp2, tmp2);
10060 crc32(tmp2, tmp1, 4);
10061 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10062 shlq(in1, 1);
10063 movl(tmp1, in1);
10064 shrq(in1, 32);
10065 xorl(tmp2, tmp2);
10066 crc32(tmp2, tmp1, 4);
10067 xorl(in1, tmp2);
10068 xorl(in_out, in1);
10069 xorl(in_out, in2);
10070 }
10071
10072 // Set N to predefined value
10073 // Subtract from a lenght of a buffer
10074 // execute in a loop:
10075 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10076 // for i = 1 to N do
10077 // CRC_A = CRC32(CRC_A, A[i])
10078 // CRC_B = CRC32(CRC_B, B[i])
10079 // CRC_C = CRC32(CRC_C, C[i])
10080 // end for
10081 // Recombine
10082 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10083 Register in_out1, Register in_out2, Register in_out3,
10084 Register tmp1, Register tmp2, Register tmp3,
10085 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10086 Register tmp4, Register tmp5,
10087 Register n_tmp6) {
10088 Label L_processPartitions;
10089 Label L_processPartition;
10090 Label L_exit;
10091
10092 bind(L_processPartitions);
10093 cmpl(in_out1, 3 * size);
10094 jcc(Assembler::less, L_exit);
10095 xorl(tmp1, tmp1);
10096 xorl(tmp2, tmp2);
10097 movq(tmp3, in_out2);
10098 addq(tmp3, size);
10099
10100 bind(L_processPartition);
10101 crc32(in_out3, Address(in_out2, 0), 8);
10102 crc32(tmp1, Address(in_out2, size), 8);
10103 crc32(tmp2, Address(in_out2, size * 2), 8);
10104 addq(in_out2, 8);
10105 cmpq(in_out2, tmp3);
10106 jcc(Assembler::less, L_processPartition);
10107 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10108 w_xtmp1, w_xtmp2, w_xtmp3,
10109 tmp4, tmp5,
10110 n_tmp6);
10111 addq(in_out2, 2 * size);
10112 subl(in_out1, 3 * size);
10113 jmp(L_processPartitions);
10114
10115 bind(L_exit);
10116 }
10117 #else
10118 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10119 Register tmp1, Register tmp2, Register tmp3,
10120 XMMRegister xtmp1, XMMRegister xtmp2) {
10121 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10122 if (n > 0) {
10123 addl(tmp3, n * 256 * 8);
10124 }
10125 // Q1 = TABLEExt[n][B & 0xFF];
10126 movl(tmp1, in_out);
10127 andl(tmp1, 0x000000FF);
10128 shll(tmp1, 3);
10129 addl(tmp1, tmp3);
10130 movq(xtmp1, Address(tmp1, 0));
10131
10132 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10133 movl(tmp2, in_out);
10134 shrl(tmp2, 8);
10135 andl(tmp2, 0x000000FF);
10136 shll(tmp2, 3);
10137 addl(tmp2, tmp3);
10138 movq(xtmp2, Address(tmp2, 0));
10139
10140 psllq(xtmp2, 8);
10141 pxor(xtmp1, xtmp2);
10142
10143 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10144 movl(tmp2, in_out);
10145 shrl(tmp2, 16);
10146 andl(tmp2, 0x000000FF);
10147 shll(tmp2, 3);
10148 addl(tmp2, tmp3);
10149 movq(xtmp2, Address(tmp2, 0));
10150
10151 psllq(xtmp2, 16);
10152 pxor(xtmp1, xtmp2);
10153
10154 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10155 shrl(in_out, 24);
10156 andl(in_out, 0x000000FF);
10157 shll(in_out, 3);
10158 addl(in_out, tmp3);
10159 movq(xtmp2, Address(in_out, 0));
10160
10161 psllq(xtmp2, 24);
10162 pxor(xtmp1, xtmp2); // Result in CXMM
10163 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10164 }
10165
10166 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10167 Register in_out,
10168 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10169 XMMRegister w_xtmp2,
10170 Register tmp1,
10171 Register n_tmp2, Register n_tmp3) {
10172 if (is_pclmulqdq_supported) {
10173 movdl(w_xtmp1, in_out);
10174
10175 movl(tmp1, const_or_pre_comp_const_index);
10176 movdl(w_xtmp2, tmp1);
10177 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10178 // Keep result in XMM since GPR is 32 bit in length
10179 } else {
10180 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10181 }
10182 }
10183
10184 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10185 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10186 Register tmp1, Register tmp2,
10187 Register n_tmp3) {
10188 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10189 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10190
10191 psllq(w_xtmp1, 1);
10192 movdl(tmp1, w_xtmp1);
10193 psrlq(w_xtmp1, 32);
10194 movdl(in_out, w_xtmp1);
10195
10196 xorl(tmp2, tmp2);
10197 crc32(tmp2, tmp1, 4);
10198 xorl(in_out, tmp2);
10199
10200 psllq(w_xtmp2, 1);
10201 movdl(tmp1, w_xtmp2);
10202 psrlq(w_xtmp2, 32);
10203 movdl(in1, w_xtmp2);
10204
10205 xorl(tmp2, tmp2);
10206 crc32(tmp2, tmp1, 4);
10207 xorl(in1, tmp2);
10208 xorl(in_out, in1);
10209 xorl(in_out, in2);
10210 }
10211
10212 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10213 Register in_out1, Register in_out2, Register in_out3,
10214 Register tmp1, Register tmp2, Register tmp3,
10215 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10216 Register tmp4, Register tmp5,
10217 Register n_tmp6) {
10218 Label L_processPartitions;
10219 Label L_processPartition;
10220 Label L_exit;
10221
10222 bind(L_processPartitions);
10223 cmpl(in_out1, 3 * size);
10224 jcc(Assembler::less, L_exit);
10225 xorl(tmp1, tmp1);
10226 xorl(tmp2, tmp2);
10227 movl(tmp3, in_out2);
10228 addl(tmp3, size);
10229
10230 bind(L_processPartition);
10231 crc32(in_out3, Address(in_out2, 0), 4);
10232 crc32(tmp1, Address(in_out2, size), 4);
10233 crc32(tmp2, Address(in_out2, size*2), 4);
10234 crc32(in_out3, Address(in_out2, 0+4), 4);
10235 crc32(tmp1, Address(in_out2, size+4), 4);
10236 crc32(tmp2, Address(in_out2, size*2+4), 4);
10237 addl(in_out2, 8);
10238 cmpl(in_out2, tmp3);
10239 jcc(Assembler::less, L_processPartition);
10240
10241 push(tmp3);
10242 push(in_out1);
10243 push(in_out2);
10244 tmp4 = tmp3;
10245 tmp5 = in_out1;
10246 n_tmp6 = in_out2;
10247
10248 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10249 w_xtmp1, w_xtmp2, w_xtmp3,
10250 tmp4, tmp5,
10251 n_tmp6);
10252
10253 pop(in_out2);
10254 pop(in_out1);
10255 pop(tmp3);
10256
10257 addl(in_out2, 2 * size);
10258 subl(in_out1, 3 * size);
10259 jmp(L_processPartitions);
10260
10261 bind(L_exit);
10262 }
10263 #endif //LP64
10264
10265 #ifdef _LP64
10266 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10267 // Input: A buffer I of L bytes.
10268 // Output: the CRC32C value of the buffer.
10269 // Notations:
10270 // Write L = 24N + r, with N = floor (L/24).
10271 // r = L mod 24 (0 <= r < 24).
10272 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10273 // N quadwords, and R consists of r bytes.
10274 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10275 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10276 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10277 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10278 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10279 Register tmp1, Register tmp2, Register tmp3,
10280 Register tmp4, Register tmp5, Register tmp6,
10281 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10282 bool is_pclmulqdq_supported) {
10283 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10284 Label L_wordByWord;
10285 Label L_byteByByteProlog;
10286 Label L_byteByByte;
10287 Label L_exit;
10288
10289 if (is_pclmulqdq_supported ) {
10290 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10291 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10292
10293 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10294 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10295
10296 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10297 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10298 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10299 } else {
10300 const_or_pre_comp_const_index[0] = 1;
10301 const_or_pre_comp_const_index[1] = 0;
10302
10303 const_or_pre_comp_const_index[2] = 3;
10304 const_or_pre_comp_const_index[3] = 2;
10305
10306 const_or_pre_comp_const_index[4] = 5;
10307 const_or_pre_comp_const_index[5] = 4;
10308 }
10309 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10310 in2, in1, in_out,
10311 tmp1, tmp2, tmp3,
10312 w_xtmp1, w_xtmp2, w_xtmp3,
10313 tmp4, tmp5,
10314 tmp6);
10315 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10316 in2, in1, in_out,
10317 tmp1, tmp2, tmp3,
10318 w_xtmp1, w_xtmp2, w_xtmp3,
10319 tmp4, tmp5,
10320 tmp6);
10321 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10322 in2, in1, in_out,
10323 tmp1, tmp2, tmp3,
10324 w_xtmp1, w_xtmp2, w_xtmp3,
10325 tmp4, tmp5,
10326 tmp6);
10327 movl(tmp1, in2);
10328 andl(tmp1, 0x00000007);
10329 negl(tmp1);
10330 addl(tmp1, in2);
10331 addq(tmp1, in1);
10332
10333 BIND(L_wordByWord);
10334 cmpq(in1, tmp1);
10335 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10336 crc32(in_out, Address(in1, 0), 4);
10337 addq(in1, 4);
10338 jmp(L_wordByWord);
10339
10340 BIND(L_byteByByteProlog);
10341 andl(in2, 0x00000007);
10342 movl(tmp2, 1);
10343
10344 BIND(L_byteByByte);
10345 cmpl(tmp2, in2);
10346 jccb(Assembler::greater, L_exit);
10347 crc32(in_out, Address(in1, 0), 1);
10348 incq(in1);
10349 incl(tmp2);
10350 jmp(L_byteByByte);
10351
10352 BIND(L_exit);
10353 }
10354 #else
10355 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10356 Register tmp1, Register tmp2, Register tmp3,
10357 Register tmp4, Register tmp5, Register tmp6,
10358 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10359 bool is_pclmulqdq_supported) {
10360 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10361 Label L_wordByWord;
10362 Label L_byteByByteProlog;
10363 Label L_byteByByte;
10364 Label L_exit;
10365
10366 if (is_pclmulqdq_supported) {
10367 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10368 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10369
10370 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10371 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10372
10373 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10374 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10375 } else {
10376 const_or_pre_comp_const_index[0] = 1;
10377 const_or_pre_comp_const_index[1] = 0;
10378
10379 const_or_pre_comp_const_index[2] = 3;
10380 const_or_pre_comp_const_index[3] = 2;
10381
10382 const_or_pre_comp_const_index[4] = 5;
10383 const_or_pre_comp_const_index[5] = 4;
10384 }
10385 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10386 in2, in1, in_out,
10387 tmp1, tmp2, tmp3,
10388 w_xtmp1, w_xtmp2, w_xtmp3,
10389 tmp4, tmp5,
10390 tmp6);
10391 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10392 in2, in1, in_out,
10393 tmp1, tmp2, tmp3,
10394 w_xtmp1, w_xtmp2, w_xtmp3,
10395 tmp4, tmp5,
10396 tmp6);
10397 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10398 in2, in1, in_out,
10399 tmp1, tmp2, tmp3,
10400 w_xtmp1, w_xtmp2, w_xtmp3,
10401 tmp4, tmp5,
10402 tmp6);
10403 movl(tmp1, in2);
10404 andl(tmp1, 0x00000007);
10405 negl(tmp1);
10406 addl(tmp1, in2);
10407 addl(tmp1, in1);
10408
10409 BIND(L_wordByWord);
10410 cmpl(in1, tmp1);
10411 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10412 crc32(in_out, Address(in1,0), 4);
10413 addl(in1, 4);
10414 jmp(L_wordByWord);
10415
10416 BIND(L_byteByByteProlog);
10417 andl(in2, 0x00000007);
10418 movl(tmp2, 1);
10419
10420 BIND(L_byteByByte);
10421 cmpl(tmp2, in2);
10422 jccb(Assembler::greater, L_exit);
10423 movb(tmp1, Address(in1, 0));
10424 crc32(in_out, tmp1, 1);
10425 incl(in1);
10426 incl(tmp2);
10427 jmp(L_byteByByte);
10428
10429 BIND(L_exit);
10430 }
10431 #endif // LP64
10432 #undef BIND
10433 #undef BLOCK_COMMENT
10434
10435 // Compress char[] array to byte[].
10436 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10437 // @HotSpotIntrinsicCandidate
10438 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10439 // for (int i = 0; i < len; i++) {
10440 // int c = src[srcOff++];
10441 // if (c >>> 8 != 0) {
10442 // return 0;
10443 // }
10444 // dst[dstOff++] = (byte)c;
10445 // }
10446 // return len;
10447 // }
10448 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10449 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10450 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10451 Register tmp5, Register result) {
10452 Label copy_chars_loop, return_length, return_zero, done;
10453
10454 // rsi: src
10455 // rdi: dst
10456 // rdx: len
10457 // rcx: tmp5
10458 // rax: result
10459
10460 // rsi holds start addr of source char[] to be compressed
10461 // rdi holds start addr of destination byte[]
10462 // rdx holds length
10463
10464 assert(len != result, "");
10465
10466 // save length for return
10467 push(len);
10468
10469 if ((UseAVX > 2) && // AVX512
10470 VM_Version::supports_avx512vlbw() &&
10471 VM_Version::supports_bmi2()) {
10472
10473 set_vector_masking(); // opening of the stub context for programming mask registers
10474
10475 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero, below_threshold;
10476
10477 // alignment
10478 Label post_alignment;
10479
10480 // if length of the string is less than 16, handle it in an old fashioned way
10481 testl(len, -32);
10482 jcc(Assembler::zero, below_threshold);
10483
10484 // First check whether a character is compressable ( <= 0xFF).
10485 // Create mask to test for Unicode chars inside zmm vector
10486 movl(result, 0x00FF);
10487 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10488
10489 // Save k1
10490 kmovql(k3, k1);
10491
10492 testl(len, -64);
10493 jcc(Assembler::zero, post_alignment);
10494
10495 movl(tmp5, dst);
10496 andl(tmp5, (32 - 1));
10497 negl(tmp5);
10498 andl(tmp5, (32 - 1));
10499
10500 // bail out when there is nothing to be done
10501 testl(tmp5, 0xFFFFFFFF);
10502 jcc(Assembler::zero, post_alignment);
10503
10504 // ~(~0 << len), where len is the # of remaining elements to process
10505 movl(result, 0xFFFFFFFF);
10506 shlxl(result, result, tmp5);
10507 notl(result);
10508 kmovdl(k1, result);
10509
10510 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10511 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10512 ktestd(k2, k1);
10513 jcc(Assembler::carryClear, restore_k1_return_zero);
10514
10515 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10516
10517 addptr(src, tmp5);
10518 addptr(src, tmp5);
10519 addptr(dst, tmp5);
10520 subl(len, tmp5);
10521
10522 bind(post_alignment);
10523 // end of alignment
10524
10525 movl(tmp5, len);
10526 andl(tmp5, (32 - 1)); // tail count (in chars)
10527 andl(len, ~(32 - 1)); // vector count (in chars)
10528 jcc(Assembler::zero, copy_loop_tail);
10529
10530 lea(src, Address(src, len, Address::times_2));
10531 lea(dst, Address(dst, len, Address::times_1));
10532 negptr(len);
10533
10534 bind(copy_32_loop);
10535 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10536 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10537 kortestdl(k2, k2);
10538 jcc(Assembler::carryClear, restore_k1_return_zero);
10539
10540 // All elements in current processed chunk are valid candidates for
10541 // compression. Write a truncated byte elements to the memory.
10542 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10543 addptr(len, 32);
10544 jcc(Assembler::notZero, copy_32_loop);
10545
10546 bind(copy_loop_tail);
10547 // bail out when there is nothing to be done
10548 testl(tmp5, 0xFFFFFFFF);
10549 // Restore k1
10550 kmovql(k1, k3);
10551 jcc(Assembler::zero, return_length);
10552
10553 movl(len, tmp5);
10554
10555 // ~(~0 << len), where len is the # of remaining elements to process
10556 movl(result, 0xFFFFFFFF);
10557 shlxl(result, result, len);
10558 notl(result);
10559
10560 kmovdl(k1, result);
10561
10562 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10563 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10564 ktestd(k2, k1);
10565 jcc(Assembler::carryClear, restore_k1_return_zero);
10566
10567 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10568 // Restore k1
10569 kmovql(k1, k3);
10570 jmp(return_length);
10571
10572 bind(restore_k1_return_zero);
10573 // Restore k1
10574 kmovql(k1, k3);
10575 jmp(return_zero);
10576
10577 clear_vector_masking(); // closing of the stub context for programming mask registers
10578
10579 bind(below_threshold);
10580 }
10581
10582 if (UseSSE42Intrinsics) {
10583 Label copy_32_loop, copy_16, copy_tail;
10584
10585 movl(result, len);
10586
10587 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10588
10589 // vectored compression
10590 andl(len, 0xfffffff0); // vector count (in chars)
10591 andl(result, 0x0000000f); // tail count (in chars)
10592 testl(len, len);
10593 jccb(Assembler::zero, copy_16);
10594
10595 // compress 16 chars per iter
10596 movdl(tmp1Reg, tmp5);
10597 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10598 pxor(tmp4Reg, tmp4Reg);
10599
10600 lea(src, Address(src, len, Address::times_2));
10601 lea(dst, Address(dst, len, Address::times_1));
10602 negptr(len);
10603
10604 bind(copy_32_loop);
10605 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10606 por(tmp4Reg, tmp2Reg);
10607 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10608 por(tmp4Reg, tmp3Reg);
10609 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10610 jcc(Assembler::notZero, return_zero);
10611 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10612 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10613 addptr(len, 16);
10614 jcc(Assembler::notZero, copy_32_loop);
10615
10616 // compress next vector of 8 chars (if any)
10617 bind(copy_16);
10618 movl(len, result);
10619 andl(len, 0xfffffff8); // vector count (in chars)
10620 andl(result, 0x00000007); // tail count (in chars)
10621 testl(len, len);
10622 jccb(Assembler::zero, copy_tail);
10623
10624 movdl(tmp1Reg, tmp5);
10625 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10626 pxor(tmp3Reg, tmp3Reg);
10627
10628 movdqu(tmp2Reg, Address(src, 0));
10629 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10630 jccb(Assembler::notZero, return_zero);
10631 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10632 movq(Address(dst, 0), tmp2Reg);
10633 addptr(src, 16);
10634 addptr(dst, 8);
10635
10636 bind(copy_tail);
10637 movl(len, result);
10638 }
10639 // compress 1 char per iter
10640 testl(len, len);
10641 jccb(Assembler::zero, return_length);
10642 lea(src, Address(src, len, Address::times_2));
10643 lea(dst, Address(dst, len, Address::times_1));
10644 negptr(len);
10645
10646 bind(copy_chars_loop);
10647 load_unsigned_short(result, Address(src, len, Address::times_2));
10648 testl(result, 0xff00); // check if Unicode char
10649 jccb(Assembler::notZero, return_zero);
10650 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
10651 increment(len);
10652 jcc(Assembler::notZero, copy_chars_loop);
10653
10654 // if compression succeeded, return length
10655 bind(return_length);
10656 pop(result);
10657 jmpb(done);
10658
10659 // if compression failed, return 0
10660 bind(return_zero);
10661 xorl(result, result);
10662 addptr(rsp, wordSize);
10663
10664 bind(done);
10665 }
10666
10667 // Inflate byte[] array to char[].
10668 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
10669 // @HotSpotIntrinsicCandidate
10670 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
10671 // for (int i = 0; i < len; i++) {
10672 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
10673 // }
10674 // }
10675 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
10676 XMMRegister tmp1, Register tmp2) {
10677 Label copy_chars_loop, done, below_threshold;
10678 // rsi: src
10679 // rdi: dst
10680 // rdx: len
10681 // rcx: tmp2
10682
10683 // rsi holds start addr of source byte[] to be inflated
10684 // rdi holds start addr of destination char[]
10685 // rdx holds length
10686 assert_different_registers(src, dst, len, tmp2);
10687
10688 if ((UseAVX > 2) && // AVX512
10689 VM_Version::supports_avx512vlbw() &&
10690 VM_Version::supports_bmi2()) {
10691
10692 set_vector_masking(); // opening of the stub context for programming mask registers
10693
10694 Label copy_32_loop, copy_tail;
10695 Register tmp3_aliased = len;
10696
10697 // if length of the string is less than 16, handle it in an old fashioned way
10698 testl(len, -16);
10699 jcc(Assembler::zero, below_threshold);
10700
10701 // In order to use only one arithmetic operation for the main loop we use
10702 // this pre-calculation
10703 movl(tmp2, len);
10704 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
10705 andl(len, -32); // vector count
10706 jccb(Assembler::zero, copy_tail);
10707
10708 lea(src, Address(src, len, Address::times_1));
10709 lea(dst, Address(dst, len, Address::times_2));
10710 negptr(len);
10711
10712
10713 // inflate 32 chars per iter
10714 bind(copy_32_loop);
10715 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
10716 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
10717 addptr(len, 32);
10718 jcc(Assembler::notZero, copy_32_loop);
10719
10720 bind(copy_tail);
10721 // bail out when there is nothing to be done
10722 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
10723 jcc(Assembler::zero, done);
10724
10725 // Save k1
10726 kmovql(k2, k1);
10727
10728 // ~(~0 << length), where length is the # of remaining elements to process
10729 movl(tmp3_aliased, -1);
10730 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
10731 notl(tmp3_aliased);
10732 kmovdl(k1, tmp3_aliased);
10733 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
10734 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
10735
10736 // Restore k1
10737 kmovql(k1, k2);
10738 jmp(done);
10739
10740 clear_vector_masking(); // closing of the stub context for programming mask registers
10741 }
10742 if (UseSSE42Intrinsics) {
10743 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
10744
10745 movl(tmp2, len);
10746
10747 if (UseAVX > 1) {
10748 andl(tmp2, (16 - 1));
10749 andl(len, -16);
10750 jccb(Assembler::zero, copy_new_tail);
10751 } else {
10752 andl(tmp2, 0x00000007); // tail count (in chars)
10753 andl(len, 0xfffffff8); // vector count (in chars)
10754 jccb(Assembler::zero, copy_tail);
10755 }
10756
10757 // vectored inflation
10758 lea(src, Address(src, len, Address::times_1));
10759 lea(dst, Address(dst, len, Address::times_2));
10760 negptr(len);
10761
10762 if (UseAVX > 1) {
10763 bind(copy_16_loop);
10764 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
10765 vmovdqu(Address(dst, len, Address::times_2), tmp1);
10766 addptr(len, 16);
10767 jcc(Assembler::notZero, copy_16_loop);
10768
10769 bind(below_threshold);
10770 bind(copy_new_tail);
10771 if ((UseAVX > 2) &&
10772 VM_Version::supports_avx512vlbw() &&
10773 VM_Version::supports_bmi2()) {
10774 movl(tmp2, len);
10775 } else {
10776 movl(len, tmp2);
10777 }
10778 andl(tmp2, 0x00000007);
10779 andl(len, 0xFFFFFFF8);
10780 jccb(Assembler::zero, copy_tail);
10781
10782 pmovzxbw(tmp1, Address(src, 0));
10783 movdqu(Address(dst, 0), tmp1);
10784 addptr(src, 8);
10785 addptr(dst, 2 * 8);
10786
10787 jmp(copy_tail, true);
10788 }
10789
10790 // inflate 8 chars per iter
10791 bind(copy_8_loop);
10792 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
10793 movdqu(Address(dst, len, Address::times_2), tmp1);
10794 addptr(len, 8);
10795 jcc(Assembler::notZero, copy_8_loop);
10796
10797 bind(copy_tail);
10798 movl(len, tmp2);
10799
10800 cmpl(len, 4);
10801 jccb(Assembler::less, copy_bytes);
10802
10803 movdl(tmp1, Address(src, 0)); // load 4 byte chars
10804 pmovzxbw(tmp1, tmp1);
10805 movq(Address(dst, 0), tmp1);
10806 subptr(len, 4);
10807 addptr(src, 4);
10808 addptr(dst, 8);
10809
10810 bind(copy_bytes);
10811 } else {
10812 bind(below_threshold);
10813 }
10814
10815 testl(len, len);
10816 jccb(Assembler::zero, done);
10817 lea(src, Address(src, len, Address::times_1));
10818 lea(dst, Address(dst, len, Address::times_2));
10819 negptr(len);
10820
10821 // inflate 1 char per iter
10822 bind(copy_chars_loop);
10823 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
10824 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
10825 increment(len);
10826 jcc(Assembler::notZero, copy_chars_loop);
10827
10828 bind(done);
10829 }
10830
10831 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10832 switch (cond) {
10833 // Note some conditions are synonyms for others
10834 case Assembler::zero: return Assembler::notZero;
10835 case Assembler::notZero: return Assembler::zero;
10836 case Assembler::less: return Assembler::greaterEqual;
10837 case Assembler::lessEqual: return Assembler::greater;
10838 case Assembler::greater: return Assembler::lessEqual;
10839 case Assembler::greaterEqual: return Assembler::less;
10840 case Assembler::below: return Assembler::aboveEqual;
10841 case Assembler::belowEqual: return Assembler::above;
10842 case Assembler::above: return Assembler::belowEqual;
10843 case Assembler::aboveEqual: return Assembler::below;
10844 case Assembler::overflow: return Assembler::noOverflow;
10845 case Assembler::noOverflow: return Assembler::overflow;
10846 case Assembler::negative: return Assembler::positive;
10847 case Assembler::positive: return Assembler::negative;
10848 case Assembler::parity: return Assembler::noParity;
10849 case Assembler::noParity: return Assembler::parity;
10850 }
10851 ShouldNotReachHere(); return Assembler::overflow;
10852 }
10853
10854 SkipIfEqual::SkipIfEqual(
10855 MacroAssembler* masm, const bool* flag_addr, bool value) {
10856 _masm = masm;
10857 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10858 _masm->jcc(Assembler::equal, _label);
10859 }
10860
10861 SkipIfEqual::~SkipIfEqual() {
10862 _masm->bind(_label);
10863 }
10864
10865 // 32-bit Windows has its own fast-path implementation
10866 // of get_thread
10867 #if !defined(WIN32) || defined(_LP64)
10868
10869 // This is simply a call to Thread::current()
10870 void MacroAssembler::get_thread(Register thread) {
10871 if (thread != rax) {
10872 push(rax);
10873 }
10874 LP64_ONLY(push(rdi);)
10875 LP64_ONLY(push(rsi);)
10876 push(rdx);
10877 push(rcx);
10878 #ifdef _LP64
10879 push(r8);
10880 push(r9);
10881 push(r10);
10882 push(r11);
10883 #endif
10884
10885 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10886
10887 #ifdef _LP64
10888 pop(r11);
10889 pop(r10);
10890 pop(r9);
10891 pop(r8);
10892 #endif
10893 pop(rcx);
10894 pop(rdx);
10895 LP64_ONLY(pop(rsi);)
10896 LP64_ONLY(pop(rdi);)
10897 if (thread != rax) {
10898 mov(thread, rax);
10899 pop(rax);
10900 }
10901 }
10902
10903 #endif