852 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
853 // Note2:
854 // SPARC -d32 has 24 registers available for integral values,
855 // but only 10 of these are safe for 64-bit longs.
856 // Using set_reg_pressure(2) for both int and long means
857 // the allocator will believe it can fit 26 longs into
858 // registers. Using 2 for longs and 1 for ints means the
859 // allocator will attempt to put 52 integers into registers.
860 // The settings below limit this problem to methods with
861 // many long values which are being run on 32-bit SPARC.
862 //
863 // ------------------- reg_pressure --------------------
864 // Each entry is reg_pressure_per_value,number_of_regs
865 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
866 // IA32 2 1 1 1 1 6 6
867 // IA64 1 1 1 1 1 50 41
868 // SPARC 2 2 2 2 2 48 (24) 52 (26)
869 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
870 // AMD64 1 1 1 1 1 14 15
871 // -----------------------------------------------------
872 #if defined(SPARC)
873 lrg.set_reg_pressure(2); // use for v9 as well
874 #else
875 lrg.set_reg_pressure(1); // normally one value per register
876 #endif
877 if( n_type->isa_oop_ptr() ) {
878 lrg._is_oop = 1;
879 }
880 break;
881 case Op_RegL: // Check for long or double
882 case Op_RegD:
883 lrg.set_num_regs(2);
884 // Define platform specific register pressure
885 #if defined(SPARC) || defined(ARM32)
886 lrg.set_reg_pressure(2);
887 #elif defined(IA32)
888 if( ireg == Op_RegL ) {
889 lrg.set_reg_pressure(2);
890 } else {
891 lrg.set_reg_pressure(1);
892 }
893 #else
894 lrg.set_reg_pressure(1); // normally one value per register
895 #endif
896 // If this def of a double forces a mis-aligned double,
897 // flag as '_fat_proj' - really flag as allowing misalignment
898 // AND changes how we count interferences. A mis-aligned
899 // double can interfere with TWO aligned pairs, or effectively
900 // FOUR registers!
901 if (rm.is_misaligned_pair()) {
902 lrg._fat_proj = 1;
903 lrg._is_bound = 1;
904 }
905 break;
906 case Op_RegF:
907 case Op_RegI:
908 case Op_RegN:
909 case Op_RegFlags:
910 case 0: // not an ideal register
911 lrg.set_num_regs(1);
912 #ifdef SPARC
913 lrg.set_reg_pressure(2);
914 #else
915 lrg.set_reg_pressure(1);
916 #endif
917 break;
918 case Op_VecS:
919 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
920 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
921 lrg.set_num_regs(RegMask::SlotsPerVecS);
922 lrg.set_reg_pressure(1);
923 break;
924 case Op_VecD:
925 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
926 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
927 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
928 lrg.set_num_regs(RegMask::SlotsPerVecD);
929 lrg.set_reg_pressure(1);
930 break;
931 case Op_VecX:
932 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
933 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
934 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
935 lrg.set_num_regs(RegMask::SlotsPerVecX);
936 lrg.set_reg_pressure(1);
1469 tty->print(" removed ");
1470 rm.SUBTRACT(lrg->mask());
1471 rm.dump();
1472 tty->print(" leaving ");
1473 lrg->mask().dump();
1474 tty->cr();
1475 }
1476 #endif
1477 }
1478 }
1479 }
1480 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1481 // Aligned pairs need aligned masks
1482 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1483 if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1484 lrg->clear_to_sets();
1485 }
1486
1487 // Check if a color is available and if so pick the color
1488 OptoReg::Name reg = choose_color( *lrg, chunk );
1489 #ifdef SPARC
1490 debug_only(lrg->compute_set_mask_size());
1491 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1492 #endif
1493
1494 //---------------
1495 // If we fail to color and the AllStack flag is set, trigger
1496 // a chunk-rollover event
1497 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1498 // Bump register mask up to next stack chunk
1499 chunk += RegMask::CHUNK_SIZE;
1500 lrg->Set_All();
1501
1502 goto retry_next_chunk;
1503 }
1504
1505 //---------------
1506 // Did we get a color?
1507 else if( OptoReg::is_valid(reg)) {
1508 #ifndef PRODUCT
1509 RegMask avail_rm = lrg->mask();
1510 #endif
1511
1512 // Record selected register
|
852 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
853 // Note2:
854 // SPARC -d32 has 24 registers available for integral values,
855 // but only 10 of these are safe for 64-bit longs.
856 // Using set_reg_pressure(2) for both int and long means
857 // the allocator will believe it can fit 26 longs into
858 // registers. Using 2 for longs and 1 for ints means the
859 // allocator will attempt to put 52 integers into registers.
860 // The settings below limit this problem to methods with
861 // many long values which are being run on 32-bit SPARC.
862 //
863 // ------------------- reg_pressure --------------------
864 // Each entry is reg_pressure_per_value,number_of_regs
865 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
866 // IA32 2 1 1 1 1 6 6
867 // IA64 1 1 1 1 1 50 41
868 // SPARC 2 2 2 2 2 48 (24) 52 (26)
869 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
870 // AMD64 1 1 1 1 1 14 15
871 // -----------------------------------------------------
872 lrg.set_reg_pressure(1); // normally one value per register
873 if( n_type->isa_oop_ptr() ) {
874 lrg._is_oop = 1;
875 }
876 break;
877 case Op_RegL: // Check for long or double
878 case Op_RegD:
879 lrg.set_num_regs(2);
880 // Define platform specific register pressure
881 #if defined(ARM32)
882 lrg.set_reg_pressure(2);
883 #elif defined(IA32)
884 if( ireg == Op_RegL ) {
885 lrg.set_reg_pressure(2);
886 } else {
887 lrg.set_reg_pressure(1);
888 }
889 #else
890 lrg.set_reg_pressure(1); // normally one value per register
891 #endif
892 // If this def of a double forces a mis-aligned double,
893 // flag as '_fat_proj' - really flag as allowing misalignment
894 // AND changes how we count interferences. A mis-aligned
895 // double can interfere with TWO aligned pairs, or effectively
896 // FOUR registers!
897 if (rm.is_misaligned_pair()) {
898 lrg._fat_proj = 1;
899 lrg._is_bound = 1;
900 }
901 break;
902 case Op_RegF:
903 case Op_RegI:
904 case Op_RegN:
905 case Op_RegFlags:
906 case 0: // not an ideal register
907 lrg.set_num_regs(1);
908 lrg.set_reg_pressure(1);
909 break;
910 case Op_VecS:
911 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
912 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
913 lrg.set_num_regs(RegMask::SlotsPerVecS);
914 lrg.set_reg_pressure(1);
915 break;
916 case Op_VecD:
917 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
918 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
919 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
920 lrg.set_num_regs(RegMask::SlotsPerVecD);
921 lrg.set_reg_pressure(1);
922 break;
923 case Op_VecX:
924 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
925 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
926 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
927 lrg.set_num_regs(RegMask::SlotsPerVecX);
928 lrg.set_reg_pressure(1);
1461 tty->print(" removed ");
1462 rm.SUBTRACT(lrg->mask());
1463 rm.dump();
1464 tty->print(" leaving ");
1465 lrg->mask().dump();
1466 tty->cr();
1467 }
1468 #endif
1469 }
1470 }
1471 }
1472 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1473 // Aligned pairs need aligned masks
1474 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1475 if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1476 lrg->clear_to_sets();
1477 }
1478
1479 // Check if a color is available and if so pick the color
1480 OptoReg::Name reg = choose_color( *lrg, chunk );
1481
1482 //---------------
1483 // If we fail to color and the AllStack flag is set, trigger
1484 // a chunk-rollover event
1485 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1486 // Bump register mask up to next stack chunk
1487 chunk += RegMask::CHUNK_SIZE;
1488 lrg->Set_All();
1489
1490 goto retry_next_chunk;
1491 }
1492
1493 //---------------
1494 // Did we get a color?
1495 else if( OptoReg::is_valid(reg)) {
1496 #ifndef PRODUCT
1497 RegMask avail_rm = lrg->mask();
1498 #endif
1499
1500 // Record selected register
|