1 /* 2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_ASSEMBLER_SPARC_INLINE_HPP 26 #define CPU_SPARC_ASSEMBLER_SPARC_INLINE_HPP 27 28 #include "asm/assembler.hpp" 29 30 31 inline void Assembler::avoid_pipeline_stall() { 32 #ifdef VALIDATE_PIPELINE 33 if (_hazard_state == PcHazard) { 34 assert(is_cbcond_before() || is_rdpc_before(), "PC-hazard not preceeded by CBCOND or RDPC."); 35 assert_no_delay("Must not have PC-hazard state in delay-slot."); 36 nop(); 37 _hazard_state = NoHazard; 38 } 39 #endif 40 41 bool post_cond = is_cbcond_before(); 42 bool post_rdpc = is_rdpc_before(); 43 44 if (post_cond || post_rdpc) { 45 nop(); 46 #ifdef VALIDATE_PIPELINE 47 if (_hazard_state != PcHazard) { 48 assert(post_cond, "CBCOND before when no hazard @0x%p\n", pc()); 49 assert(post_rdpc, "RDPC before when no hazard @0x%p\n", pc()); 50 } 51 #endif 52 } 53 } 54 55 inline void Assembler::check_delay() { 56 #ifdef VALIDATE_PIPELINE 57 guarantee(_delay_state != AtDelay, "Use delayed() when filling delay-slot"); 58 _delay_state = NoDelay; 59 #endif 60 } 61 62 inline void Assembler::emit_int32(int32_t x) { 63 check_delay(); 64 #ifdef VALIDATE_PIPELINE 65 _hazard_state = NoHazard; 66 #endif 67 AbstractAssembler::emit_int32(x); 68 } 69 70 inline void Assembler::emit_data(int32_t x) { 71 emit_int32(x); 72 } 73 74 inline void Assembler::emit_data(int32_t x, relocInfo::relocType rtype) { 75 relocate(rtype); 76 emit_int32(x); 77 } 78 79 inline void Assembler::emit_data(int32_t x, RelocationHolder const &rspec) { 80 relocate(rspec); 81 emit_int32(x); 82 } 83 84 85 inline void Assembler::add(Register s1, Register s2, Register d) { 86 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2)); 87 } 88 inline void Assembler::add(Register s1, int simm13a, Register d) { 89 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 90 } 91 92 inline void Assembler::addcc(Register s1, Register s2, Register d) { 93 emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 94 } 95 inline void Assembler::addcc(Register s1, int simm13a, Register d) { 96 emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 97 } 98 inline void Assembler::addc(Register s1, Register s2, Register d) { 99 emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | rs2(s2)); 100 } 101 inline void Assembler::addc(Register s1, int simm13a, Register d) { 102 emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 103 } 104 inline void Assembler::addccc(Register s1, Register s2, Register d) { 105 emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 106 } 107 inline void Assembler::addccc(Register s1, int simm13a, Register d) { 108 emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 109 } 110 111 inline void Assembler::aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 112 aes_only(); 113 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D)); 114 } 115 inline void Assembler::aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 116 aes_only(); 117 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D)); 118 } 119 inline void Assembler::aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 120 aes_only(); 121 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D)); 122 } 123 inline void Assembler::aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 124 aes_only(); 125 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D)); 126 } 127 inline void Assembler::aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 128 aes_only(); 129 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D)); 130 } 131 inline void Assembler::aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 132 aes_only(); 133 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D)); 134 } 135 inline void Assembler::aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 136 aes_only(); 137 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D)); 138 } 139 inline void Assembler::aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 140 aes_only(); 141 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D)); 142 } 143 inline void Assembler::aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d) { 144 aes_only(); 145 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D)); 146 } 147 148 // 3-operand AES instructions 149 150 inline void Assembler::aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d) { 151 aes_only(); 152 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D)); 153 } 154 inline void Assembler::aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d) { 155 aes_only(); 156 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D)); 157 } 158 159 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt) { 160 avoid_pipeline_stall(); 161 cti(); 162 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); 163 induce_delay_slot(); 164 } 165 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, Label &L) { 166 // Note[+]: All assembly emit routines using the 'target()' branch back-patch 167 // resolver must call 'avoid_pipeline_stall()' prior to calling 'target()' 168 // (we must do so even though the call will be made, as here, in the above 169 // implementation of 'bpr()', invoked below). The reason is the assumption 170 // made in 'target()', where using the current PC as the address for back- 171 // patching prevents any additional code to be emitted _after_ the address 172 // has been set (implicitly) in order to refer to the correct instruction. 173 avoid_pipeline_stall(); 174 bpr(c, a, p, s1, target(L)); 175 } 176 177 inline void Assembler::fb(Condition c, bool a, address d, relocInfo::relocType rt) { 178 v9_dep(); 179 avoid_pipeline_stall(); 180 cti(); 181 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 182 induce_delay_slot(); 183 } 184 inline void Assembler::fb(Condition c, bool a, Label &L) { 185 avoid_pipeline_stall(); 186 fb(c, a, target(L)); 187 } 188 189 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 190 avoid_pipeline_stall(); 191 cti(); 192 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 193 induce_delay_slot(); 194 } 195 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, Label &L) { 196 avoid_pipeline_stall(); 197 fbp(c, a, cc, p, target(L)); 198 } 199 200 inline void Assembler::br(Condition c, bool a, address d, relocInfo::relocType rt) { 201 v9_dep(); 202 avoid_pipeline_stall(); 203 cti(); 204 emit_data(op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 205 induce_delay_slot(); 206 } 207 inline void Assembler::br(Condition c, bool a, Label &L) { 208 avoid_pipeline_stall(); 209 br(c, a, target(L)); 210 } 211 212 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 213 avoid_pipeline_stall(); 214 cti(); 215 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 216 induce_delay_slot(); 217 } 218 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, Label &L) { 219 avoid_pipeline_stall(); 220 bp(c, a, cc, p, target(L)); 221 } 222 223 // compare and branch 224 inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label &L) { 225 avoid_pipeline_stall(); 226 cti(); 227 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); 228 induce_pc_hazard(); 229 } 230 inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label &L) { 231 avoid_pipeline_stall(); 232 cti(); 233 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); 234 induce_pc_hazard(); 235 } 236 237 inline void Assembler::call(address d, relocInfo::relocType rt) { 238 avoid_pipeline_stall(); 239 cti(); 240 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); 241 induce_delay_slot(); 242 assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 243 } 244 inline void Assembler::call(Label &L, relocInfo::relocType rt) { 245 avoid_pipeline_stall(); 246 call(target(L), rt); 247 } 248 249 inline void Assembler::call(address d, RelocationHolder const &rspec) { 250 avoid_pipeline_stall(); 251 cti(); 252 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rspec); 253 induce_delay_slot(); 254 assert(rspec.type() != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 255 } 256 257 inline void Assembler::casa(Register s1, Register s2, Register d, int ia) { 258 emit_int32(op(ldst_op) | rd(d) | op3(casa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 259 } 260 inline void Assembler::casxa(Register s1, Register s2, Register d, int ia) { 261 emit_int32(op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 262 } 263 264 inline void Assembler::udiv(Register s1, Register s2, Register d) { 265 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | rs2(s2)); 266 } 267 inline void Assembler::udiv(Register s1, int simm13a, Register d) { 268 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 269 } 270 inline void Assembler::sdiv(Register s1, Register s2, Register d) { 271 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | rs2(s2)); 272 } 273 inline void Assembler::sdiv(Register s1, int simm13a, Register d) { 274 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 275 } 276 inline void Assembler::udivcc(Register s1, Register s2, Register d) { 277 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 278 } 279 inline void Assembler::udivcc(Register s1, int simm13a, Register d) { 280 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 281 } 282 inline void Assembler::sdivcc(Register s1, Register s2, Register d) { 283 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 284 } 285 inline void Assembler::sdivcc(Register s1, int simm13a, Register d) { 286 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 287 } 288 289 inline void Assembler::done() { 290 cti(); 291 emit_int32(op(arith_op) | fcn(0) | op3(done_op3)); 292 } 293 inline void Assembler::retry() { 294 cti(); 295 emit_int32(op(arith_op) | fcn(1) | op3(retry_op3)); 296 } 297 298 inline void Assembler::fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 299 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); 300 } 301 inline void Assembler::fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 302 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); 303 } 304 305 inline void Assembler::fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { 306 emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); 307 } 308 inline void Assembler::fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { 309 emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); 310 } 311 312 inline void Assembler::ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 313 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); 314 } 315 inline void Assembler::ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 316 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); 317 } 318 319 inline void Assembler::ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d) { 320 emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); 321 } 322 323 inline void Assembler::fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 324 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); 325 } 326 inline void Assembler::fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 327 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); 328 } 329 330 inline void Assembler::fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 331 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); 332 } 333 inline void Assembler::fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 334 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); 335 } 336 inline void Assembler::fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 337 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); 338 } 339 inline void Assembler::fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 340 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); 341 } 342 inline void Assembler::fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d) { 343 emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); 344 } 345 inline void Assembler::fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 346 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); 347 } 348 349 inline void Assembler::fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 350 vis1_only(); 351 emit_int32(op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); 352 } 353 354 inline void Assembler::fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 355 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); 356 } 357 358 inline void Assembler::fmadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 359 fmaf_only(); 360 emit_int32(op(arith_op) | fd(d, w) | op3(stpartialf_op3) | fs1(s1, w) | fs3(s3, w) | op5(w) | fs2(s2, w)); 361 } 362 inline void Assembler::fmsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 363 fmaf_only(); 364 emit_int32(op(arith_op) | fd(d, w) | op3(stpartialf_op3) | fs1(s1, w) | fs3(s3, w) | op5(0x4 + w) | fs2(s2, w)); 365 } 366 367 inline void Assembler::fnmadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 368 fmaf_only(); 369 emit_int32(op(arith_op) | fd(d, w) | op3(stpartialf_op3) | fs1(s1, w) | fs3(s3, w) | op5(0xc + w) | fs2(s2, w)); 370 } 371 inline void Assembler::fnmsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 372 fmaf_only(); 373 emit_int32(op(arith_op) | fd(d, w) | op3(stpartialf_op3) | fs1(s1, w) | fs3(s3, w) | op5(0x8 + w) | fs2(s2, w)); 374 } 375 376 inline void Assembler::flush(Register s1, Register s2) { 377 emit_int32(op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); 378 } 379 inline void Assembler::flush(Register s1, int simm13a) { 380 emit_data(op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 381 } 382 383 inline void Assembler::flushw() { 384 emit_int32(op(arith_op) | op3(flushw_op3)); 385 } 386 387 inline void Assembler::illtrap(int const22a) { 388 emit_int32(op(branch_op) | u_field(const22a, 21, 0)); 389 } 390 391 inline void Assembler::impdep1(int id1, int const19a) { 392 emit_int32(op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); 393 } 394 inline void Assembler::impdep2(int id1, int const19a) { 395 emit_int32(op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); 396 } 397 398 inline void Assembler::jmpl(Register s1, Register s2, Register d) { 399 avoid_pipeline_stall(); 400 cti(); 401 emit_int32(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); 402 induce_delay_slot(); 403 } 404 inline void Assembler::jmpl(Register s1, int simm13a, Register d, RelocationHolder const &rspec) { 405 avoid_pipeline_stall(); 406 cti(); 407 emit_data(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 408 induce_delay_slot(); 409 } 410 411 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { 412 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2)); 413 } 414 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const &rspec) { 415 emit_data(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 416 } 417 418 inline void Assembler::ldd(Register s1, Register s2, FloatRegister d) { 419 assert(d->is_even(), "not even"); 420 ldf(FloatRegisterImpl::D, s1, s2, d); 421 } 422 inline void Assembler::ldd(Register s1, int simm13a, FloatRegister d) { 423 assert(d->is_even(), "not even"); 424 ldf(FloatRegisterImpl::D, s1, simm13a, d); 425 } 426 427 inline void Assembler::ldxfsr(Register s1, Register s2) { 428 emit_int32(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2)); 429 } 430 inline void Assembler::ldxfsr(Register s1, int simm13a) { 431 emit_data(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 432 } 433 434 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d) { 435 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2)); 436 } 437 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { 438 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 439 } 440 441 inline void Assembler::ldsb(Register s1, Register s2, Register d) { 442 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2)); 443 } 444 inline void Assembler::ldsb(Register s1, int simm13a, Register d) { 445 emit_data(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 446 } 447 448 inline void Assembler::ldsh(Register s1, Register s2, Register d) { 449 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2)); 450 } 451 inline void Assembler::ldsh(Register s1, int simm13a, Register d) { 452 emit_data(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 453 } 454 inline void Assembler::ldsw(Register s1, Register s2, Register d) { 455 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2)); 456 } 457 inline void Assembler::ldsw(Register s1, int simm13a, Register d) { 458 emit_data(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 459 } 460 inline void Assembler::ldub(Register s1, Register s2, Register d) { 461 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2)); 462 } 463 inline void Assembler::ldub(Register s1, int simm13a, Register d) { 464 emit_data(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 465 } 466 inline void Assembler::lduh(Register s1, Register s2, Register d) { 467 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2)); 468 } 469 inline void Assembler::lduh(Register s1, int simm13a, Register d) { 470 emit_data(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 471 } 472 inline void Assembler::lduw(Register s1, Register s2, Register d) { 473 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2)); 474 } 475 inline void Assembler::lduw(Register s1, int simm13a, Register d) { 476 emit_data(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 477 } 478 479 inline void Assembler::ldx(Register s1, Register s2, Register d) { 480 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2)); 481 } 482 inline void Assembler::ldx(Register s1, int simm13a, Register d) { 483 emit_data(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 484 } 485 486 inline void Assembler::ldsba(Register s1, Register s2, int ia, Register d) { 487 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 488 } 489 inline void Assembler::ldsba(Register s1, int simm13a, Register d) { 490 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 491 } 492 inline void Assembler::ldsha(Register s1, Register s2, int ia, Register d) { 493 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 494 } 495 inline void Assembler::ldsha(Register s1, int simm13a, Register d) { 496 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 497 } 498 inline void Assembler::ldswa(Register s1, Register s2, int ia, Register d) { 499 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 500 } 501 inline void Assembler::ldswa(Register s1, int simm13a, Register d) { 502 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 503 } 504 inline void Assembler::lduba(Register s1, Register s2, int ia, Register d) { 505 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 506 } 507 inline void Assembler::lduba(Register s1, int simm13a, Register d) { 508 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 509 } 510 inline void Assembler::lduha(Register s1, Register s2, int ia, Register d) { 511 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 512 } 513 inline void Assembler::lduha(Register s1, int simm13a, Register d) { 514 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 515 } 516 inline void Assembler::lduwa(Register s1, Register s2, int ia, Register d) { 517 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 518 } 519 inline void Assembler::lduwa(Register s1, int simm13a, Register d) { 520 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 521 } 522 inline void Assembler::ldxa(Register s1, Register s2, int ia, Register d) { 523 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 524 } 525 inline void Assembler::ldxa(Register s1, int simm13a, Register d) { 526 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 527 } 528 529 inline void Assembler::and3(Register s1, Register s2, Register d) { 530 emit_int32(op(arith_op) | rd(d) | op3(and_op3) | rs1(s1) | rs2(s2)); 531 } 532 inline void Assembler::and3(Register s1, int simm13a, Register d) { 533 emit_int32(op(arith_op) | rd(d) | op3(and_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 534 } 535 inline void Assembler::andcc(Register s1, Register s2, Register d) { 536 emit_int32(op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 537 } 538 inline void Assembler::andcc(Register s1, int simm13a, Register d) { 539 emit_int32(op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 540 } 541 inline void Assembler::andn(Register s1, Register s2, Register d) { 542 emit_int32(op(arith_op) | rd(d) | op3(andn_op3) | rs1(s1) | rs2(s2)); 543 } 544 inline void Assembler::andn(Register s1, int simm13a, Register d) { 545 emit_int32(op(arith_op) | rd(d) | op3(andn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 546 } 547 inline void Assembler::andncc(Register s1, Register s2, Register d) { 548 emit_int32(op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 549 } 550 inline void Assembler::andncc(Register s1, int simm13a, Register d) { 551 emit_int32(op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 552 } 553 inline void Assembler::or3(Register s1, Register s2, Register d) { 554 emit_int32(op(arith_op) | rd(d) | op3(or_op3) | rs1(s1) | rs2(s2)); 555 } 556 inline void Assembler::or3(Register s1, int simm13a, Register d) { 557 emit_int32(op(arith_op) | rd(d) | op3(or_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 558 } 559 inline void Assembler::orcc(Register s1, Register s2, Register d) { 560 emit_int32(op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 561 } 562 inline void Assembler::orcc(Register s1, int simm13a, Register d) { 563 emit_int32(op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 564 } 565 inline void Assembler::orn(Register s1, Register s2, Register d) { 566 emit_int32(op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2)); 567 } 568 inline void Assembler::orn(Register s1, int simm13a, Register d) { 569 emit_int32(op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 570 } 571 inline void Assembler::orncc(Register s1, Register s2, Register d) { 572 emit_int32(op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 573 } 574 inline void Assembler::orncc(Register s1, int simm13a, Register d) { 575 emit_int32(op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 576 } 577 inline void Assembler::xor3(Register s1, Register s2, Register d) { 578 emit_int32(op(arith_op) | rd(d) | op3(xor_op3) | rs1(s1) | rs2(s2)); 579 } 580 inline void Assembler::xor3(Register s1, int simm13a, Register d) { 581 emit_int32(op(arith_op) | rd(d) | op3(xor_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 582 } 583 inline void Assembler::xorcc(Register s1, Register s2, Register d) { 584 emit_int32(op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 585 } 586 inline void Assembler::xorcc(Register s1, int simm13a, Register d) { 587 emit_int32(op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 588 } 589 inline void Assembler::xnor(Register s1, Register s2, Register d) { 590 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3) | rs1(s1) | rs2(s2)); 591 } 592 inline void Assembler::xnor(Register s1, int simm13a, Register d) { 593 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 594 } 595 inline void Assembler::xnorcc(Register s1, Register s2, Register d) { 596 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 597 } 598 inline void Assembler::xnorcc(Register s1, int simm13a, Register d) { 599 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 600 } 601 602 inline void Assembler::membar(Membar_mask_bits const7a) { 603 emit_int32(op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field(int(const7a), 6, 0)); 604 } 605 606 inline void Assembler::fmov(FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d) { 607 emit_int32(op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); 608 } 609 610 inline void Assembler::fmov(FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d) { 611 emit_int32(op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); 612 } 613 614 inline void Assembler::movcc(Condition c, bool floatCC, CC cca, Register s2, Register d) { 615 emit_int32(op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2)); 616 } 617 inline void Assembler::movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d) { 618 emit_int32(op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11)); 619 } 620 621 inline void Assembler::movr(RCondition c, Register s1, Register s2, Register d) { 622 emit_int32(op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2)); 623 } 624 inline void Assembler::movr(RCondition c, Register s1, int simm10a, Register d) { 625 emit_int32(op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10)); 626 } 627 628 inline void Assembler::mulx(Register s1, Register s2, Register d) { 629 emit_int32(op(arith_op) | rd(d) | op3(mulx_op3) | rs1(s1) | rs2(s2)); 630 } 631 inline void Assembler::mulx(Register s1, int simm13a, Register d) { 632 emit_int32(op(arith_op) | rd(d) | op3(mulx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 633 } 634 inline void Assembler::sdivx(Register s1, Register s2, Register d) { 635 emit_int32(op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2)); 636 } 637 inline void Assembler::sdivx(Register s1, int simm13a, Register d) { 638 emit_int32(op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 639 } 640 inline void Assembler::udivx(Register s1, Register s2, Register d) { 641 emit_int32(op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2)); 642 } 643 inline void Assembler::udivx(Register s1, int simm13a, Register d) { 644 emit_int32(op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 645 } 646 647 inline void Assembler::umul(Register s1, Register s2, Register d) { 648 emit_int32(op(arith_op) | rd(d) | op3(umul_op3) | rs1(s1) | rs2(s2)); 649 } 650 inline void Assembler::umul(Register s1, int simm13a, Register d) { 651 emit_int32(op(arith_op) | rd(d) | op3(umul_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 652 } 653 inline void Assembler::smul(Register s1, Register s2, Register d) { 654 emit_int32(op(arith_op) | rd(d) | op3(smul_op3) | rs1(s1) | rs2(s2)); 655 } 656 inline void Assembler::smul(Register s1, int simm13a, Register d) { 657 emit_int32(op(arith_op) | rd(d) | op3(smul_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 658 } 659 inline void Assembler::umulcc(Register s1, Register s2, Register d) { 660 emit_int32(op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 661 } 662 inline void Assembler::umulcc(Register s1, int simm13a, Register d) { 663 emit_int32(op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 664 } 665 inline void Assembler::smulcc(Register s1, Register s2, Register d) { 666 emit_int32(op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 667 } 668 inline void Assembler::smulcc(Register s1, int simm13a, Register d) { 669 emit_int32(op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 670 } 671 672 inline void Assembler::nop() { 673 emit_int32(op(branch_op) | op2(sethi_op2)); 674 } 675 676 inline void Assembler::sw_count() { 677 emit_int32(op(branch_op) | op2(sethi_op2) | 0x3f0); 678 } 679 680 inline void Assembler::popc(Register s, Register d) { 681 emit_int32(op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); 682 } 683 inline void Assembler::popc(int simm13a, Register d) { 684 emit_int32(op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); 685 } 686 687 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { 688 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2)); 689 } 690 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { 691 emit_data(op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 692 } 693 694 inline void Assembler::prefetcha(Register s1, Register s2, int ia, PrefetchFcn f) { 695 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 696 } 697 inline void Assembler::prefetcha(Register s1, int simm13a, PrefetchFcn f) { 698 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 699 } 700 701 inline void Assembler::rdy(Register d) { 702 v9_dep(); 703 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); 704 } 705 inline void Assembler::rdccr(Register d) { 706 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); 707 } 708 inline void Assembler::rdasi(Register d) { 709 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); 710 } 711 inline void Assembler::rdtick(Register d) { 712 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); 713 } 714 inline void Assembler::rdpc(Register d) { 715 avoid_pipeline_stall(); 716 cti(); 717 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); 718 induce_pc_hazard(); 719 } 720 inline void Assembler::rdfprs(Register d) { 721 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); 722 } 723 724 inline void Assembler::rett(Register s1, Register s2) { 725 cti(); 726 emit_int32(op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); 727 induce_delay_slot(); 728 } 729 inline void Assembler::rett(Register s1, int simm13a, relocInfo::relocType rt) { 730 cti(); 731 emit_data(op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); 732 induce_delay_slot(); 733 } 734 735 inline void Assembler::save(Register s1, Register s2, Register d) { 736 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2)); 737 } 738 inline void Assembler::save(Register s1, int simm13a, Register d) { 739 // make sure frame is at least large enough for the register save area 740 assert(-simm13a >= 16 * wordSize, "frame too small"); 741 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 742 } 743 744 inline void Assembler::restore(Register s1, Register s2, Register d) { 745 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2)); 746 } 747 inline void Assembler::restore(Register s1, int simm13a, Register d) { 748 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 749 } 750 751 // pp 216 752 753 inline void Assembler::saved() { 754 emit_int32(op(arith_op) | fcn(0) | op3(saved_op3)); 755 } 756 inline void Assembler::restored() { 757 emit_int32(op(arith_op) | fcn(1) | op3(saved_op3)); 758 } 759 760 inline void Assembler::sethi(int imm22a, Register d, RelocationHolder const &rspec) { 761 emit_data(op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); 762 } 763 764 inline void Assembler::sll(Register s1, Register s2, Register d) { 765 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2)); 766 } 767 inline void Assembler::sll(Register s1, int imm5a, Register d) { 768 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 769 } 770 inline void Assembler::srl(Register s1, Register s2, Register d) { 771 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2)); 772 } 773 inline void Assembler::srl(Register s1, int imm5a, Register d) { 774 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 775 } 776 inline void Assembler::sra(Register s1, Register s2, Register d) { 777 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2)); 778 } 779 inline void Assembler::sra(Register s1, int imm5a, Register d) { 780 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 781 } 782 783 inline void Assembler::sllx(Register s1, Register s2, Register d) { 784 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2)); 785 } 786 inline void Assembler::sllx(Register s1, int imm6a, Register d) { 787 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 788 } 789 inline void Assembler::srlx(Register s1, Register s2, Register d) { 790 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2)); 791 } 792 inline void Assembler::srlx(Register s1, int imm6a, Register d) { 793 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 794 } 795 inline void Assembler::srax(Register s1, Register s2, Register d) { 796 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2)); 797 } 798 inline void Assembler::srax(Register s1, int imm6a, Register d) { 799 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 800 } 801 802 inline void Assembler::sir(int simm13a) { 803 emit_int32(op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); 804 } 805 806 // pp 221 807 808 inline void Assembler::stbar() { 809 emit_int32(op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); 810 } 811 812 // pp 222 813 814 inline void Assembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { 815 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2)); 816 } 817 inline void Assembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { 818 emit_data(op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 819 } 820 821 inline void Assembler::std(FloatRegister d, Register s1, Register s2) { 822 assert(d->is_even(), "not even"); 823 stf(FloatRegisterImpl::D, d, s1, s2); 824 } 825 inline void Assembler::std(FloatRegister d, Register s1, int simm13a) { 826 assert(d->is_even(), "not even"); 827 stf(FloatRegisterImpl::D, d, s1, simm13a); 828 } 829 830 inline void Assembler::stxfsr(Register s1, Register s2) { 831 emit_int32(op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2)); 832 } 833 inline void Assembler::stxfsr(Register s1, int simm13a) { 834 emit_data(op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 835 } 836 837 inline void Assembler::stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia) { 838 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2)); 839 } 840 inline void Assembler::stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { 841 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 842 } 843 844 // p 226 845 846 inline void Assembler::stb(Register d, Register s1, Register s2) { 847 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2)); 848 } 849 inline void Assembler::stb(Register d, Register s1, int simm13a) { 850 emit_data(op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 851 } 852 inline void Assembler::sth(Register d, Register s1, Register s2) { 853 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2)); 854 } 855 inline void Assembler::sth(Register d, Register s1, int simm13a) { 856 emit_data(op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 857 } 858 inline void Assembler::stw(Register d, Register s1, Register s2) { 859 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2)); 860 } 861 inline void Assembler::stw(Register d, Register s1, int simm13a) { 862 emit_data(op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 863 } 864 865 866 inline void Assembler::stx(Register d, Register s1, Register s2) { 867 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2)); 868 } 869 inline void Assembler::stx(Register d, Register s1, int simm13a) { 870 emit_data(op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 871 } 872 873 inline void Assembler::stba(Register d, Register s1, Register s2, int ia) { 874 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 875 } 876 inline void Assembler::stba(Register d, Register s1, int simm13a) { 877 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 878 } 879 inline void Assembler::stha(Register d, Register s1, Register s2, int ia) { 880 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 881 } 882 inline void Assembler::stha(Register d, Register s1, int simm13a) { 883 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 884 } 885 inline void Assembler::stwa(Register d, Register s1, Register s2, int ia) { 886 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 887 } 888 inline void Assembler::stwa(Register d, Register s1, int simm13a) { 889 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 890 } 891 inline void Assembler::stxa(Register d, Register s1, Register s2, int ia) { 892 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 893 } 894 inline void Assembler::stxa(Register d, Register s1, int simm13a) { 895 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 896 } 897 inline void Assembler::stda(Register d, Register s1, Register s2, int ia) { 898 emit_int32(op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 899 } 900 inline void Assembler::stda(Register d, Register s1, int simm13a) { 901 emit_int32(op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 902 } 903 904 // pp 230 905 906 inline void Assembler::sub(Register s1, Register s2, Register d) { 907 emit_int32(op(arith_op) | rd(d) | op3(sub_op3) | rs1(s1) | rs2(s2)); 908 } 909 inline void Assembler::sub(Register s1, int simm13a, Register d) { 910 emit_int32(op(arith_op) | rd(d) | op3(sub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 911 } 912 913 inline void Assembler::subcc(Register s1, Register s2, Register d) { 914 emit_int32(op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 915 } 916 inline void Assembler::subcc(Register s1, int simm13a, Register d) { 917 emit_int32(op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 918 } 919 inline void Assembler::subc(Register s1, Register s2, Register d) { 920 emit_int32(op(arith_op) | rd(d) | op3(subc_op3) | rs1(s1) | rs2(s2)); 921 } 922 inline void Assembler::subc(Register s1, int simm13a, Register d) { 923 emit_int32(op(arith_op) | rd(d) | op3(subc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 924 } 925 inline void Assembler::subccc(Register s1, Register s2, Register d) { 926 emit_int32(op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 927 } 928 inline void Assembler::subccc(Register s1, int simm13a, Register d) { 929 emit_int32(op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 930 } 931 932 // pp 231 933 934 inline void Assembler::swap(Register s1, Register s2, Register d) { 935 v9_dep(); 936 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2)); 937 } 938 inline void Assembler::swap(Register s1, int simm13a, Register d) { 939 v9_dep(); 940 emit_data(op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 941 } 942 943 inline void Assembler::swapa(Register s1, Register s2, int ia, Register d) { 944 v9_dep(); 945 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 946 } 947 inline void Assembler::swapa(Register s1, int simm13a, Register d) { 948 v9_dep(); 949 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 950 } 951 952 // pp 234, note op in book is wrong, see pp 268 953 954 inline void Assembler::taddcc(Register s1, Register s2, Register d) { 955 emit_int32(op(arith_op) | rd(d) | op3(taddcc_op3) | rs1(s1) | rs2(s2)); 956 } 957 inline void Assembler::taddcc(Register s1, int simm13a, Register d) { 958 emit_int32(op(arith_op) | rd(d) | op3(taddcc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 959 } 960 961 // pp 235 962 963 inline void Assembler::tsubcc(Register s1, Register s2, Register d) { 964 emit_int32(op(arith_op) | rd(d) | op3(tsubcc_op3) | rs1(s1) | rs2(s2)); 965 } 966 inline void Assembler::tsubcc(Register s1, int simm13a, Register d) { 967 emit_int32(op(arith_op) | rd(d) | op3(tsubcc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 968 } 969 970 // pp 237 971 972 inline void Assembler::trap(Condition c, CC cc, Register s1, Register s2) { 973 emit_int32(op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); 974 } 975 inline void Assembler::trap(Condition c, CC cc, Register s1, int trapa) { 976 emit_int32(op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); 977 } 978 // simple uncond. trap 979 inline void Assembler::trap(int trapa) { 980 trap(always, icc, G0, trapa); 981 } 982 983 inline void Assembler::wry(Register d) { 984 v9_dep(); 985 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); 986 } 987 inline void Assembler::wrccr(Register s) { 988 emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); 989 } 990 inline void Assembler::wrccr(Register s, int simm13a) { 991 emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25) | immed(true) | simm(simm13a, 13)); 992 } 993 inline void Assembler::wrasi(Register d) { 994 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); 995 } 996 // wrasi(d, imm) stores (d xor imm) to asi 997 inline void Assembler::wrasi(Register d, int simm13a) { 998 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); 999 } 1000 inline void Assembler::wrfprs(Register d) { 1001 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); 1002 } 1003 1004 inline void Assembler::alignaddr(Register s1, Register s2, Register d) { 1005 vis1_only(); 1006 emit_int32(op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); 1007 } 1008 1009 inline void Assembler::faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d) { 1010 vis1_only(); 1011 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); 1012 } 1013 1014 inline void Assembler::fzero(FloatRegisterImpl::Width w, FloatRegister d) { 1015 vis1_only(); 1016 emit_int32(op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); 1017 } 1018 1019 inline void Assembler::fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d) { 1020 vis1_only(); 1021 emit_int32(op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); 1022 } 1023 1024 inline void Assembler::fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d) { 1025 vis1_only(); 1026 emit_int32(op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); 1027 } 1028 1029 inline void Assembler::fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d) { 1030 vis1_only(); 1031 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); 1032 } 1033 1034 inline void Assembler::stpartialf(Register s1, Register s2, FloatRegister d, int ia) { 1035 vis1_only(); 1036 emit_int32(op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 1037 } 1038 1039 // VIS2 instructions 1040 1041 inline void Assembler::edge8n(Register s1, Register s2, Register d) { 1042 vis2_only(); 1043 emit_int32(op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); 1044 } 1045 1046 inline void Assembler::bmask(Register s1, Register s2, Register d) { 1047 vis2_only(); 1048 emit_int32(op(arith_op) | rd(d) | op3(bmask_op3) | rs1(s1) | opf(bmask_opf) | rs2(s2)); 1049 } 1050 inline void Assembler::bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d) { 1051 vis2_only(); 1052 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(bshuffle_op3) | fs1(s1, FloatRegisterImpl::D) | opf(bshuffle_opf) | fs2(s2, FloatRegisterImpl::D)); 1053 } 1054 1055 // VIS3 instructions 1056 1057 inline void Assembler::addxc(Register s1, Register s2, Register d) { 1058 vis3_only(); 1059 emit_int32(op(arith_op) | rd(d) | op3(addx_op3) | rs1(s1) | opf(addxc_opf) | rs2(s2)); 1060 } 1061 inline void Assembler::addxccc(Register s1, Register s2, Register d) { 1062 vis3_only(); 1063 emit_int32(op(arith_op) | rd(d) | op3(addx_op3) | rs1(s1) | opf(addxccc_opf) | rs2(s2)); 1064 } 1065 1066 inline void Assembler::movstosw(FloatRegister s, Register d) { 1067 vis3_only(); 1068 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); 1069 } 1070 inline void Assembler::movstouw(FloatRegister s, Register d) { 1071 vis3_only(); 1072 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); 1073 } 1074 inline void Assembler::movdtox(FloatRegister s, Register d) { 1075 vis3_only(); 1076 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); 1077 } 1078 1079 inline void Assembler::movwtos(Register s, FloatRegister d) { 1080 vis3_only(); 1081 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); 1082 } 1083 inline void Assembler::movxtod(Register s, FloatRegister d) { 1084 vis3_only(); 1085 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); 1086 } 1087 1088 inline void Assembler::xmulx(Register s1, Register s2, Register d) { 1089 vis3_only(); 1090 emit_int32(op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); 1091 } 1092 inline void Assembler::xmulxhi(Register s1, Register s2, Register d) { 1093 vis3_only(); 1094 emit_int32(op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); 1095 } 1096 inline void Assembler::umulxhi(Register s1, Register s2, Register d) { 1097 vis3_only(); 1098 emit_int32(op(arith_op) | rd(d) | op3(umulx_op3) | rs1(s1) | opf(umulxhi_opf) | rs2(s2)); 1099 } 1100 1101 // Crypto SHA instructions 1102 1103 inline void Assembler::sha1() { 1104 sha1_only(); 1105 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha1_opf)); 1106 } 1107 inline void Assembler::sha256() { 1108 sha256_only(); 1109 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha256_opf)); 1110 } 1111 inline void Assembler::sha512() { 1112 sha512_only(); 1113 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha512_opf)); 1114 } 1115 1116 // CRC32C instruction 1117 1118 inline void Assembler::crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d) { 1119 crc32c_only(); 1120 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D)); 1121 } 1122 1123 // MPMUL instruction 1124 1125 inline void Assembler::mpmul(int uimm5) { 1126 mpmul_only(); 1127 emit_int32(op(arith_op) | rd(0) | op3(mpmul_op3) | rs1(0) | opf(mpmul_opf) | uimm(uimm5, 5)); 1128 } 1129 1130 #endif // CPU_SPARC_ASSEMBLER_SPARC_INLINE_HPP