1 /*
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   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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   6  * under the terms of the GNU General Public License version 2 only, as
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  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
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  24 
  25 #ifndef CPU_SPARC_MACROASSEMBLER_SPARC_HPP
  26 #define CPU_SPARC_MACROASSEMBLER_SPARC_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 
  31 // <sys/trap.h> promises that the system will not use traps 16-31
  32 #define ST_RESERVED_FOR_USER_0 0x10
  33 
  34 class BiasedLockingCounters;
  35 
  36 
  37 // Register aliases for parts of the system:
  38 
  39 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
  40 // across context switches in V8+ ABI.  Of course, there are no 64 bit regs
  41 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
  42 
  43 // g2-g4 are scratch registers called "application globals".  Their
  44 // meaning is reserved to the "compilation system"--which means us!
  45 // They are are not supposed to be touched by ordinary C code, although
  46 // highly-optimized C code might steal them for temps.  They are safe
  47 // across thread switches, and the ABI requires that they be safe
  48 // across function calls.
  49 //
  50 // g1 and g3 are touched by more modules.  V8 allows g1 to be clobbered
  51 // across func calls, and V8+ also allows g5 to be clobbered across
  52 // func calls.  Also, g1 and g5 can get touched while doing shared
  53 // library loading.
  54 //
  55 // We must not touch g7 (it is the thread-self register) and g6 is
  56 // reserved for certain tools.  g0, of course, is always zero.
  57 //
  58 // (Sources:  SunSoft Compilers Group, thread library engineers.)
  59 
  60 // %%%% The interpreter should be revisited to reduce global scratch regs.
  61 
  62 // This global always holds the current JavaThread pointer:
  63 
  64 REGISTER_DECLARATION(Register, G2_thread , G2);
  65 REGISTER_DECLARATION(Register, G6_heapbase , G6);
  66 
  67 // The following globals are part of the Java calling convention:
  68 
  69 REGISTER_DECLARATION(Register, G5_method             , G5);
  70 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
  71 REGISTER_DECLARATION(Register, G5_inline_cache_reg   , G5_method);
  72 
  73 // The following globals are used for the new C1 & interpreter calling convention:
  74 REGISTER_DECLARATION(Register, Gargs        , G4); // pointing to the last argument
  75 
  76 // This local is used to preserve G2_thread in the interpreter and in stubs:
  77 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
  78 
  79 // These globals are used as scratch registers in the interpreter:
  80 
  81 REGISTER_DECLARATION(Register, Gframe_size   , G1); // SAME REG as G1_scratch
  82 REGISTER_DECLARATION(Register, G1_scratch    , G1); // also SAME
  83 REGISTER_DECLARATION(Register, G3_scratch    , G3);
  84 REGISTER_DECLARATION(Register, G4_scratch    , G4);
  85 
  86 // These globals are used as short-lived scratch registers in the compiler:
  87 
  88 REGISTER_DECLARATION(Register, Gtemp  , G5);
  89 
  90 // JSR 292 fixed register usages:
  91 REGISTER_DECLARATION(Register, G5_method_type        , G5);
  92 REGISTER_DECLARATION(Register, G3_method_handle      , G3);
  93 REGISTER_DECLARATION(Register, L7_mh_SP_save         , L7);
  94 
  95 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
  96 // because a single patchable "set" instruction (NativeMovConstReg,
  97 // or NativeMovConstPatching for compiler1) instruction
  98 // serves to set up either quantity, depending on whether the compiled
  99 // call site is an inline cache or is megamorphic.  See the function
 100 // CompiledIC::set_to_megamorphic.
 101 //
 102 // If a inline cache targets an interpreted method, then the
 103 // G5 register will be used twice during the call.  First,
 104 // the call site will be patched to load a compiledICHolder
 105 // into G5. (This is an ordered pair of ic_klass, method.)
 106 // The c2i adapter will first check the ic_klass, then load
 107 // G5_method with the method part of the pair just before
 108 // jumping into the interpreter.
 109 //
 110 // Note that G5_method is only the method-self for the interpreter,
 111 // and is logically unrelated to G5_megamorphic_method.
 112 //
 113 // Invariants on G2_thread (the JavaThread pointer):
 114 //  - it should not be used for any other purpose anywhere
 115 //  - it must be re-initialized by StubRoutines::call_stub()
 116 //  - it must be preserved around every use of call_VM
 117 
 118 // We can consider using g2/g3/g4 to cache more values than the
 119 // JavaThread, such as the card-marking base or perhaps pointers into
 120 // Eden.  It's something of a waste to use them as scratch temporaries,
 121 // since they are not supposed to be volatile.  (Of course, if we find
 122 // that Java doesn't benefit from application globals, then we can just
 123 // use them as ordinary temporaries.)
 124 //
 125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
 126 // it makes sense to use them routinely for procedure linkage,
 127 // whenever the On registers are not applicable.  Examples:  G5_method,
 128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
 129 // stubs.  This means that compiler stubs, etc., should be kept to a
 130 // maximum of two or three G-register arguments.
 131 
 132 
 133 // stub frames
 134 
 135 REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself
 136 
 137 // Interpreter frames
 138 
 139 REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer
 140 REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode
 141 REGISTER_DECLARATION(Register, Lmethod          , L2);
 142 REGISTER_DECLARATION(Register, Llocals          , L3);
 143 REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler
 144                                                        // must match Llocals in asm interpreter
 145 REGISTER_DECLARATION(Register, Lmonitors        , L4);
 146 REGISTER_DECLARATION(Register, Lbyte_code       , L5);
 147 // When calling out from the interpreter we record SP so that we can remove any extra stack
 148 // space allocated during adapter transitions. This register is only live from the point
 149 // of the call until we return.
 150 REGISTER_DECLARATION(Register, Llast_SP         , L5);
 151 REGISTER_DECLARATION(Register, Lscratch         , L5);
 152 REGISTER_DECLARATION(Register, Lscratch2        , L6);
 153 REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache
 154 
 155 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
 156 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
 157                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
 158                                                        // is added and removed as needed in the frame code.
 159 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
 160 REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data
 161 
 162 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
 163 //       the interpreter code. If Lscratch2 needs to be used for some
 164 //       purpose than LcpoolCache should be restore after that for
 165 //       the interpreter to work right
 166 // (These assignments must be compatible with L7_thread_cache; see above.)
 167 
 168 // Lbcp points into the middle of the method object.
 169 
 170 // Exception processing
 171 // These registers are passed into exception handlers.
 172 // All exception handlers require the exception object being thrown.
 173 // In addition, an nmethod's exception handler must be passed
 174 // the address of the call site within the nmethod, to allow
 175 // proper selection of the applicable catch block.
 176 // (Interpreter frames use their own bcp() for this purpose.)
 177 //
 178 // The Oissuing_pc value is not always needed.  When jumping to a
 179 // handler that is known to be interpreted, the Oissuing_pc value can be
 180 // omitted.  An actual catch block in compiled code receives (from its
 181 // nmethod's exception handler) the thrown exception in the Oexception,
 182 // but it doesn't need the Oissuing_pc.
 183 //
 184 // If an exception handler (either interpreted or compiled)
 185 // discovers there is no applicable catch block, it updates
 186 // the Oissuing_pc to the continuation PC of its own caller,
 187 // pops back to that caller's stack frame, and executes that
 188 // caller's exception handler.  Obviously, this process will
 189 // iterate until the control stack is popped back to a method
 190 // containing an applicable catch block.  A key invariant is
 191 // that the Oissuing_pc value is always a value local to
 192 // the method whose exception handler is currently executing.
 193 //
 194 // Note:  The issuing PC value is __not__ a raw return address (I7 value).
 195 // It is a "return pc", the address __following__ the call.
 196 // Raw return addresses are converted to issuing PCs by frame::pc(),
 197 // or by stubs.  Issuing PCs can be used directly with PC range tables.
 198 //
 199 REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown
 200 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
 201 
 202 // Address is an abstraction used to represent a memory location.
 203 //
 204 // Note: A register location is represented via a Register, not
 205 //       via an address for efficiency & simplicity reasons.
 206 
 207 class Address {
 208  private:
 209   Register           _base;           // Base register.
 210   RegisterOrConstant _index_or_disp;  // Index register or constant displacement.
 211   RelocationHolder   _rspec;
 212 
 213  public:
 214   Address() : _base(noreg), _index_or_disp(noreg) {}
 215 
 216   Address(Register base, RegisterOrConstant index_or_disp)
 217     : _base(base),
 218       _index_or_disp(index_or_disp) {
 219   }
 220 
 221   Address(Register base, Register index)
 222     : _base(base),
 223       _index_or_disp(index) {
 224   }
 225 
 226   Address(Register base, int disp)
 227     : _base(base),
 228       _index_or_disp(disp) {
 229   }
 230 
 231 #ifdef ASSERT
 232   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 233   Address(Register base, ByteSize disp)
 234     : _base(base),
 235       _index_or_disp(in_bytes(disp)) {
 236   }
 237 #endif
 238 
 239   // accessors
 240   Register base()             const { return _base; }
 241   Register index()            const { return _index_or_disp.as_register(); }
 242   int      disp()             const { return _index_or_disp.as_constant(); }
 243 
 244   bool     has_index()        const { return _index_or_disp.is_register(); }
 245   bool     has_disp()         const { return _index_or_disp.is_constant(); }
 246 
 247   bool     uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
 248 
 249   const relocInfo::relocType rtype() { return _rspec.type(); }
 250   const RelocationHolder&    rspec() { return _rspec; }
 251 
 252   RelocationHolder rspec(int offset) const {
 253     return offset == 0 ? _rspec : _rspec.plus(offset);
 254   }
 255 
 256   inline bool is_simm13(int offset = 0);  // check disp+offset for overflow
 257 
 258   Address plus_disp(int plusdisp) const {     // bump disp by a small amount
 259     assert(_index_or_disp.is_constant(), "must have a displacement");
 260     Address a(base(), disp() + plusdisp);
 261     return a;
 262   }
 263   bool is_same_address(Address a) const {
 264     // disregard _rspec
 265     return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp());
 266   }
 267 
 268   Address after_save() const {
 269     Address a = (*this);
 270     a._base = a._base->after_save();
 271     return a;
 272   }
 273 
 274   Address after_restore() const {
 275     Address a = (*this);
 276     a._base = a._base->after_restore();
 277     return a;
 278   }
 279 
 280   // Convert the raw encoding form into the form expected by the
 281   // constructor for Address.
 282   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 283 
 284   friend class Assembler;
 285 };
 286 
 287 
 288 class AddressLiteral {
 289  private:
 290   address          _address;
 291   RelocationHolder _rspec;
 292 
 293   RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
 294     switch (rtype) {
 295     case relocInfo::external_word_type:
 296       return external_word_Relocation::spec(addr);
 297     case relocInfo::internal_word_type:
 298       return internal_word_Relocation::spec(addr);
 299     case relocInfo::opt_virtual_call_type:
 300       return opt_virtual_call_Relocation::spec();
 301     case relocInfo::static_call_type:
 302       return static_call_Relocation::spec();
 303     case relocInfo::runtime_call_type:
 304       return runtime_call_Relocation::spec();
 305     case relocInfo::none:
 306       return RelocationHolder();
 307     default:
 308       ShouldNotReachHere();
 309       return RelocationHolder();
 310     }
 311   }
 312 
 313  protected:
 314   // creation
 315   AddressLiteral() : _address(NULL), _rspec(NULL) {}
 316 
 317  public:
 318   AddressLiteral(address addr, RelocationHolder const& rspec)
 319     : _address(addr),
 320       _rspec(rspec) {}
 321 
 322   // Some constructors to avoid casting at the call site.
 323   AddressLiteral(jobject obj, RelocationHolder const& rspec)
 324     : _address((address) obj),
 325       _rspec(rspec) {}
 326 
 327   AddressLiteral(intptr_t value, RelocationHolder const& rspec)
 328     : _address((address) value),
 329       _rspec(rspec) {}
 330 
 331   AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
 332     : _address((address) addr),
 333     _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 334 
 335   // Some constructors to avoid casting at the call site.
 336   AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
 337     : _address((address) addr),
 338     _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 339 
 340   AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
 341     : _address((address) addr),
 342       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 343 
 344   AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
 345     : _address((address) addr),
 346       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 347 
 348   AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
 349     : _address((address) addr),
 350       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 351 
 352   AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
 353     : _address((address) addr),
 354       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 355 
 356   AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
 357     : _address((address) addr),
 358       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 359 
 360   // 32-bit complains about a multiple declaration for int*.
 361   AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
 362     : _address((address) addr),
 363       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 364 
 365   AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none)
 366     : _address((address) addr),
 367       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 368 
 369   AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none)
 370     : _address((address) addr),
 371       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 372 
 373   AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
 374     : _address((address) addr),
 375       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 376 
 377   AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
 378     : _address((address) addr),
 379       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
 380 
 381   intptr_t value() const { return (intptr_t) _address; }
 382   int      low10() const;
 383 
 384   const relocInfo::relocType rtype() const { return _rspec.type(); }
 385   const RelocationHolder&    rspec() const { return _rspec; }
 386 
 387   RelocationHolder rspec(int offset) const {
 388     return offset == 0 ? _rspec : _rspec.plus(offset);
 389   }
 390 };
 391 
 392 // Convenience classes
 393 class ExternalAddress: public AddressLiteral {
 394  private:
 395   static relocInfo::relocType reloc_for_target(address target) {
 396     // Sometimes ExternalAddress is used for values which aren't
 397     // exactly addresses, like the card table base.
 398     // external_word_type can't be used for values in the first page
 399     // so just skip the reloc in that case.
 400     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 401   }
 402 
 403  public:
 404   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(          target)) {}
 405   ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {}
 406 };
 407 
 408 inline Address RegisterImpl::address_in_saved_window() const {
 409    return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
 410 }
 411 
 412 
 413 
 414 // Argument is an abstraction used to represent an outgoing
 415 // actual argument or an incoming formal parameter, whether
 416 // it resides in memory or in a register, in a manner consistent
 417 // with the SPARC Application Binary Interface, or ABI.  This is
 418 // often referred to as the native or C calling convention.
 419 
 420 class Argument {
 421  private:
 422   int _number;
 423   bool _is_in;
 424 
 425  public:
 426   enum {
 427     n_register_parameters = 6,          // only 6 registers may contain integer parameters
 428     n_float_register_parameters = 16    // Can have up to 16 floating registers
 429   };
 430 
 431   // creation
 432   Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
 433 
 434   int  number() const  { return _number;  }
 435   bool is_in()  const  { return _is_in;   }
 436   bool is_out() const  { return !is_in(); }
 437 
 438   Argument successor() const  { return Argument(number() + 1, is_in()); }
 439   Argument as_in()     const  { return Argument(number(), true ); }
 440   Argument as_out()    const  { return Argument(number(), false); }
 441 
 442   // locating register-based arguments:
 443   bool is_register() const { return _number < n_register_parameters; }
 444 
 445   // locating Floating Point register-based arguments:
 446   bool is_float_register() const { return _number < n_float_register_parameters; }
 447 
 448   FloatRegister as_float_register() const {
 449     assert(is_float_register(), "must be a register argument");
 450     return as_FloatRegister(( number() *2 ) + 1);
 451   }
 452   FloatRegister as_double_register() const {
 453     assert(is_float_register(), "must be a register argument");
 454     return as_FloatRegister(( number() *2 ));
 455   }
 456 
 457   Register as_register() const {
 458     assert(is_register(), "must be a register argument");
 459     return is_in() ? as_iRegister(number()) : as_oRegister(number());
 460   }
 461 
 462   // locating memory-based arguments
 463   Address as_address() const {
 464     assert(!is_register(), "must be a memory argument");
 465     return address_in_frame();
 466   }
 467 
 468   // When applied to a register-based argument, give the corresponding address
 469   // into the 6-word area "into which callee may store register arguments"
 470   // (This is a different place than the corresponding register-save area location.)
 471   Address address_in_frame() const;
 472 
 473   // debugging
 474   const char* name() const;
 475 
 476   friend class Assembler;
 477 };
 478 
 479 
 480 class RegistersForDebugging : public StackObj {
 481  private:
 482   static const RegistersForDebugging& _dummy; // not ODR-used so not defined
 483 
 484  public:
 485   intptr_t i[8], l[8], o[8], g[8];
 486   float    f[32];
 487   double   d[32];
 488 
 489   void print(outputStream* s);
 490 
 491   static int i_offset(int j) { return offset_of(RegistersForDebugging, i) + j * sizeof(_dummy.i[0]); }
 492   static int l_offset(int j) { return offset_of(RegistersForDebugging, l) + j * sizeof(_dummy.l[0]); }
 493   static int o_offset(int j) { return offset_of(RegistersForDebugging, o) + j * sizeof(_dummy.o[0]); }
 494   static int g_offset(int j) { return offset_of(RegistersForDebugging, g) + j * sizeof(_dummy.g[0]); }
 495   static int f_offset(int j) { return offset_of(RegistersForDebugging, f) + j * sizeof(_dummy.f[0]); }
 496   static int d_offset(int j) { return offset_of(RegistersForDebugging, d) + (j / 2) * sizeof(_dummy.d[0]); }
 497 
 498   // gen asm code to save regs
 499   static void save_registers(MacroAssembler* a);
 500 
 501   // restore global registers in case C code disturbed them
 502   static void restore_registers(MacroAssembler* a, Register r);
 503 };
 504 
 505 
 506 // MacroAssembler extends Assembler by a few frequently used macros.
 507 //
 508 // Most of the standard SPARC synthetic ops are defined here.
 509 // Instructions for which a 'better' code sequence exists depending
 510 // on arguments should also go in here.
 511 
 512 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
 513 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
 514 #define JUMP(a, temp, off)     jump(a, temp, off, __FILE__, __LINE__)
 515 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
 516 
 517 
 518 class MacroAssembler : public Assembler {
 519   // code patchers need various routines like inv_wdisp()
 520   friend class NativeInstruction;
 521   friend class NativeGeneralJump;
 522   friend class Relocation;
 523   friend class Label;
 524 
 525  protected:
 526   static int  patched_branch(int dest_pos, int inst, int inst_pos);
 527   static int  branch_destination(int inst, int pos);
 528 
 529   // Support for VM calls
 530   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
 531   // may customize this version by overriding it for its purposes (e.g., to save/restore
 532   // additional registers when doing a VM call).
 533   virtual void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
 534 
 535   //
 536   // It is imperative that all calls into the VM are handled via the call_VM macros.
 537   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 538   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 539   //
 540   // This is the base routine called by the different versions of call_VM. The interpreter
 541   // may customize this version by overriding it for its purposes (e.g., to save/restore
 542   // additional registers when doing a VM call).
 543   //
 544   // A non-volatile java_thread_cache register should be specified so
 545   // that the G2_thread value can be preserved across the call.
 546   // (If java_thread_cache is noreg, then a slow get_thread call
 547   // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
 548   // thread.
 549   //
 550   // If no last_java_sp is specified (noreg) than SP will be used instead.
 551 
 552   virtual void call_VM_base(
 553     Register        oop_result,             // where an oop-result ends up if any; use noreg otherwise
 554     Register        java_thread_cache,      // the thread if computed before     ; use noreg otherwise
 555     Register        last_java_sp,           // to set up last_Java_frame in stubs; use noreg otherwise
 556     address         entry_point,            // the entry point
 557     int             number_of_arguments,    // the number of arguments (w/o thread) to pop after call
 558     bool            check_exception=true    // flag which indicates if exception should be checked
 559   );
 560 
 561  public:
 562   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 563 
 564   // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 565   // The implementation is only non-empty for the InterpreterMacroAssembler,
 566   // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
 567   virtual void check_and_handle_popframe(Register scratch_reg);
 568   virtual void check_and_handle_earlyret(Register scratch_reg);
 569 
 570   // Support for NULL-checks
 571   //
 572   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 573   // If the accessed location is M[reg + offset] and the offset is known, provide the
 574   // offset.  No explicit code generation is needed if the offset is within a certain
 575   // range (0 <= offset <= page_size).
 576   //
 577   // FIXME: Currently not done for SPARC
 578 
 579   void null_check(Register reg, int offset = -1);
 580   static bool needs_explicit_null_check(intptr_t offset);
 581   static bool uses_implicit_null_check(void* address);
 582 
 583   // support for delayed instructions
 584   MacroAssembler* delayed() { Assembler::delayed();  return this; }
 585 
 586   // branches that use right instruction for v8 vs. v9
 587   inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 588   inline void br( Condition c, bool a, Predict p, Label& L );
 589 
 590   inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 591   inline void fb( Condition c, bool a, Predict p, Label& L );
 592 
 593   // compares register with zero (32 bit) and branches (V9 and V8 instructions)
 594   void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
 595   // Compares a pointer register with zero and branches on (not)null.
 596   // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
 597   void br_null   ( Register s1, bool a, Predict p, Label& L );
 598   void br_notnull( Register s1, bool a, Predict p, Label& L );
 599 
 600   //
 601   // Compare registers and branch with nop in delay slot or cbcond without delay slot.
 602   //
 603   // ATTENTION: use these instructions with caution because cbcond instruction
 604   //            has very short distance: 512 instructions (2Kbyte).
 605 
 606   // Compare integer (32 bit) values (icc only).
 607   void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
 608   void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
 609   // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
 610   void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
 611   void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
 612 
 613   // Short branch version for compares a pointer pwith zero.
 614   void br_null_short   ( Register s1, Predict p, Label& L );
 615   void br_notnull_short( Register s1, Predict p, Label& L );
 616 
 617   // unconditional short branch
 618   void ba_short(Label& L);
 619 
 620   // Branch on icc.z (true or not).
 621   void br_icc_zero(bool iszero, Predict p, Label &L);
 622 
 623   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 624   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
 625 
 626   // Branch that tests xcc in LP64 and icc in !LP64
 627   inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 628   inline void brx( Condition c, bool a, Predict p, Label& L );
 629 
 630   // unconditional branch
 631   inline void ba( Label& L );
 632 
 633   // Branch that tests fp condition codes
 634   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 635   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
 636 
 637   // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
 638   inline void cmp( Register s1, Register s2 );
 639   inline void cmp( Register s1, int simm13a );
 640 
 641   inline void jmp( Register s1, Register s2 );
 642   inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
 643 
 644   // Check if the call target is out of wdisp30 range (relative to the code cache)
 645   static inline bool is_far_target(address d);
 646   inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
 647   inline void call( address d, RelocationHolder const& rspec);
 648 
 649   inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
 650   inline void call( Label& L, RelocationHolder const& rspec);
 651 
 652   inline void callr( Register s1, Register s2 );
 653   inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
 654 
 655   inline void tst( Register s );
 656 
 657   inline void ret(  bool trace = false );
 658   inline void retl( bool trace = false );
 659 
 660   // Required platform-specific helpers for Label::patch_instructions.
 661   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 662   void pd_patch_instruction(address branch, address target, const char* file, int line);
 663 
 664   // sethi Macro handles optimizations and relocations
 665 private:
 666   void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
 667 public:
 668   void sethi(const AddressLiteral& addrlit, Register d);
 669   void patchable_sethi(const AddressLiteral& addrlit, Register d);
 670 
 671   // compute the number of instructions for a sethi/set
 672   static int  insts_for_sethi( address a, bool worst_case = false );
 673   static int  worst_case_insts_for_set();
 674 
 675   // set may be either setsw or setuw (high 32 bits may be zero or sign)
 676 private:
 677   void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
 678   static int insts_for_internal_set(intptr_t value);
 679 public:
 680   void set(const AddressLiteral& addrlit, Register d);
 681   void set(intptr_t value, Register d);
 682   void set(address addr, Register d, RelocationHolder const& rspec);
 683   static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
 684 
 685   void patchable_set(const AddressLiteral& addrlit, Register d);
 686   void patchable_set(intptr_t value, Register d);
 687   void set64(jlong value, Register d, Register tmp);
 688   static int insts_for_set64(jlong value);
 689 
 690   // sign-extend 32 to 64
 691   inline void signx( Register s, Register d );
 692   inline void signx( Register d );
 693 
 694   inline void not1( Register s, Register d );
 695   inline void not1( Register d );
 696 
 697   inline void neg( Register s, Register d );
 698   inline void neg( Register d );
 699 
 700   inline void cas(  Register s1, Register s2, Register d);
 701   inline void casx( Register s1, Register s2, Register d);
 702   // Functions for isolating 64 bit atomic swaps for LP64
 703   // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
 704   inline void cas_ptr(  Register s1, Register s2, Register d);
 705 
 706   // Resolve a jobject or jweak
 707   void resolve_jobject(Register value, Register tmp);
 708 
 709   // Functions for isolating 64 bit shifts for LP64
 710   inline void sll_ptr( Register s1, Register s2, Register d );
 711   inline void sll_ptr( Register s1, int imm6a,   Register d );
 712   inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
 713   inline void srl_ptr( Register s1, Register s2, Register d );
 714   inline void srl_ptr( Register s1, int imm6a,   Register d );
 715 
 716   // little-endian
 717   inline void casl(  Register s1, Register s2, Register d);
 718   inline void casxl( Register s1, Register s2, Register d);
 719 
 720   inline void inc(   Register d,  int const13 = 1 );
 721   inline void inccc( Register d,  int const13 = 1 );
 722 
 723   inline void dec(   Register d,  int const13 = 1 );
 724   inline void deccc( Register d,  int const13 = 1 );
 725 
 726   using Assembler::add;
 727   inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype);
 728   inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
 729   inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
 730   inline void add(const Address& a, Register d, int offset = 0);
 731 
 732   using Assembler::andn;
 733   inline void andn(  Register s1, RegisterOrConstant s2, Register d);
 734 
 735   inline void btst( Register s1,  Register s2 );
 736   inline void btst( int simm13a,  Register s );
 737 
 738   inline void bset( Register s1,  Register s2 );
 739   inline void bset( int simm13a,  Register s );
 740 
 741   inline void bclr( Register s1,  Register s2 );
 742   inline void bclr( int simm13a,  Register s );
 743 
 744   inline void btog( Register s1,  Register s2 );
 745   inline void btog( int simm13a,  Register s );
 746 
 747   inline void clr( Register d );
 748 
 749   inline void clrb( Register s1, Register s2);
 750   inline void clrh( Register s1, Register s2);
 751   inline void clr(  Register s1, Register s2);
 752   inline void clrx( Register s1, Register s2);
 753 
 754   inline void clrb( Register s1, int simm13a);
 755   inline void clrh( Register s1, int simm13a);
 756   inline void clr(  Register s1, int simm13a);
 757   inline void clrx( Register s1, int simm13a);
 758 
 759   // copy & clear upper word
 760   inline void clruw( Register s, Register d );
 761   // clear upper word
 762   inline void clruwu( Register d );
 763 
 764   using Assembler::ldsb;
 765   using Assembler::ldsh;
 766   using Assembler::ldsw;
 767   using Assembler::ldub;
 768   using Assembler::lduh;
 769   using Assembler::lduw;
 770   using Assembler::ldx;
 771   using Assembler::ldd;
 772 
 773 #ifdef ASSERT
 774   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 775   inline void ld(Register s1, ByteSize simm13a, Register d);
 776 #endif
 777 
 778   inline void ld(Register s1, Register s2, Register d);
 779   inline void ld(Register s1, int simm13a, Register d);
 780 
 781   inline void ldsb(const Address& a, Register d, int offset = 0);
 782   inline void ldsh(const Address& a, Register d, int offset = 0);
 783   inline void ldsw(const Address& a, Register d, int offset = 0);
 784   inline void ldub(const Address& a, Register d, int offset = 0);
 785   inline void lduh(const Address& a, Register d, int offset = 0);
 786   inline void lduw(const Address& a, Register d, int offset = 0);
 787   inline void ldx( const Address& a, Register d, int offset = 0);
 788   inline void ld(  const Address& a, Register d, int offset = 0);
 789   inline void ldd( const Address& a, Register d, int offset = 0);
 790 
 791   inline void ldub(Register s1, RegisterOrConstant s2, Register d );
 792   inline void ldsb(Register s1, RegisterOrConstant s2, Register d );
 793   inline void lduh(Register s1, RegisterOrConstant s2, Register d );
 794   inline void ldsh(Register s1, RegisterOrConstant s2, Register d );
 795   inline void lduw(Register s1, RegisterOrConstant s2, Register d );
 796   inline void ldsw(Register s1, RegisterOrConstant s2, Register d );
 797   inline void ldx( Register s1, RegisterOrConstant s2, Register d );
 798   inline void ld(  Register s1, RegisterOrConstant s2, Register d );
 799   inline void ldd( Register s1, RegisterOrConstant s2, Register d );
 800 
 801   using Assembler::ldf;
 802   inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
 803   inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
 804 
 805   // little-endian
 806   inline void lduwl(Register s1, Register s2, Register d);
 807   inline void ldswl(Register s1, Register s2, Register d);
 808   inline void ldxl( Register s1, Register s2, Register d);
 809   inline void ldfl(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
 810 
 811   // membar psuedo instruction.  takes into account target memory model.
 812   inline void membar( Assembler::Membar_mask_bits const7a );
 813 
 814   // returns if membar generates anything.
 815   inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
 816 
 817   // mov pseudo instructions
 818   inline void mov( Register s,  Register d);
 819 
 820   inline void mov_or_nop( Register s,  Register d);
 821 
 822   inline void mov( int simm13a, Register d);
 823 
 824   using Assembler::prefetch;
 825   inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
 826 
 827   using Assembler::stb;
 828   using Assembler::sth;
 829   using Assembler::stw;
 830   using Assembler::stx;
 831   using Assembler::std;
 832 
 833 #ifdef ASSERT
 834   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 835   inline void st(Register d, Register s1, ByteSize simm13a);
 836 #endif
 837 
 838   inline void st(Register d, Register s1, Register s2);
 839   inline void st(Register d, Register s1, int simm13a);
 840 
 841   inline void stb(Register d, const Address& a, int offset = 0 );
 842   inline void sth(Register d, const Address& a, int offset = 0 );
 843   inline void stw(Register d, const Address& a, int offset = 0 );
 844   inline void stx(Register d, const Address& a, int offset = 0 );
 845   inline void st( Register d, const Address& a, int offset = 0 );
 846   inline void std(Register d, const Address& a, int offset = 0 );
 847 
 848   inline void stb(Register d, Register s1, RegisterOrConstant s2 );
 849   inline void sth(Register d, Register s1, RegisterOrConstant s2 );
 850   inline void stw(Register d, Register s1, RegisterOrConstant s2 );
 851   inline void stx(Register d, Register s1, RegisterOrConstant s2 );
 852   inline void std(Register d, Register s1, RegisterOrConstant s2 );
 853   inline void st( Register d, Register s1, RegisterOrConstant s2 );
 854 
 855   using Assembler::stf;
 856   inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
 857   inline void stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
 858 
 859   // Note: offset is added to s2.
 860   using Assembler::sub;
 861   inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
 862 
 863   using Assembler::swap;
 864   inline void swap(const Address& a, Register d, int offset = 0);
 865 
 866   // address pseudos: make these names unlike instruction names to avoid confusion
 867   inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
 868   inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
 869   inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
 870   inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
 871   inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
 872   inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
 873   inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
 874   inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
 875   inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
 876 
 877   // ring buffer traceable jumps
 878 
 879   void jmp2( Register r1, Register r2, const char* file, int line );
 880   void jmp ( Register r1, int offset,  const char* file, int line );
 881 
 882   void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
 883   void jump (const AddressLiteral& addrlit, Register temp,             int offset, const char* file, int line);
 884 
 885 
 886   // argument pseudos:
 887 
 888   inline void load_argument( Argument& a, Register  d );
 889   inline void store_argument( Register s, Argument& a );
 890   inline void store_ptr_argument( Register s, Argument& a );
 891   inline void store_float_argument( FloatRegister s, Argument& a );
 892   inline void store_double_argument( FloatRegister s, Argument& a );
 893   inline void store_long_argument( Register s, Argument& a );
 894 
 895   // handy macros:
 896 
 897   inline void round_to( Register r, int modulus );
 898 
 899   // --------------------------------------------------
 900 
 901   // Functions for isolating 64 bit loads for LP64
 902   // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
 903   // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
 904   inline void ld_ptr(Register s1, Register s2, Register d);
 905   inline void ld_ptr(Register s1, int simm13a, Register d);
 906   inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
 907   inline void ld_ptr(const Address& a, Register d, int offset = 0);
 908   inline void st_ptr(Register d, Register s1, Register s2);
 909   inline void st_ptr(Register d, Register s1, int simm13a);
 910   inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
 911   inline void st_ptr(Register d, const Address& a, int offset = 0);
 912 
 913 #ifdef ASSERT
 914   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
 915   inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
 916   inline void st_ptr(Register d, Register s1, ByteSize simm13a);
 917 #endif
 918 
 919   // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
 920   // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
 921   inline void ld_long(Register s1, Register s2, Register d);
 922   inline void ld_long(Register s1, int simm13a, Register d);
 923   inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
 924   inline void ld_long(const Address& a, Register d, int offset = 0);
 925   inline void st_long(Register d, Register s1, Register s2);
 926   inline void st_long(Register d, Register s1, int simm13a);
 927   inline void st_long(Register d, Register s1, RegisterOrConstant s2);
 928   inline void st_long(Register d, const Address& a, int offset = 0);
 929 
 930   // Helpers for address formation.
 931   // - They emit only a move if s2 is a constant zero.
 932   // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
 933   // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
 934   RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
 935   RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
 936   RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
 937 
 938   RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
 939     if (is_simm13(src.constant_or_zero()))
 940       return src;               // register or short constant
 941     guarantee(temp != noreg, "constant offset overflow");
 942     set(src.as_constant(), temp);
 943     return temp;
 944   }
 945 
 946   // --------------------------------------------------
 947 
 948  public:
 949   // traps as per trap.h (SPARC ABI?)
 950 
 951   void breakpoint_trap();
 952   void breakpoint_trap(Condition c, CC cc);
 953 
 954   void safepoint_poll(Label& slow_path, bool a, Register thread_reg, Register temp_reg);
 955 
 956   // Stack frame creation/removal
 957   void enter();
 958   void leave();
 959 
 960   // Manipulation of C++ bools
 961   // These are idioms to flag the need for care with accessing bools but on
 962   // this platform we assume byte size
 963 
 964   inline void stbool(Register d, const Address& a);
 965   inline void ldbool(const Address& a, Register d);
 966   inline void movbool( bool boolconst, Register d);
 967 
 968   void resolve_oop_handle(Register result, Register tmp);
 969   void load_mirror(Register mirror, Register method, Register tmp);
 970 
 971   // klass oop manipulations if compressed
 972   void load_klass(Register src_oop, Register klass);
 973   void store_klass(Register klass, Register dst_oop);
 974   void store_klass_gap(Register s, Register dst_oop);
 975 
 976    // oop manipulations
 977   void access_store_at(BasicType type, DecoratorSet decorators,
 978                        Register src, Address dst, Register tmp);
 979   void access_load_at(BasicType type, DecoratorSet decorators,
 980                       Address src, Register dst, Register tmp);
 981 
 982   void load_heap_oop(const Address& s, Register d,
 983                      Register tmp = noreg, DecoratorSet decorators = 0);
 984   void load_heap_oop(Register s1, Register s2, Register d,
 985                      Register tmp = noreg, DecoratorSet decorators = 0);
 986   void load_heap_oop(Register s1, int simm13a, Register d,
 987                      Register tmp = noreg, DecoratorSet decorators = 0);
 988   void load_heap_oop(Register s1, RegisterOrConstant s2, Register d,
 989                      Register tmp = noreg, DecoratorSet decorators = 0);
 990   void store_heap_oop(Register d, Register s1, Register s2,
 991                       Register tmp = noreg, DecoratorSet decorators = 0);
 992   void store_heap_oop(Register d, Register s1, int simm13a,
 993                       Register tmp = noreg, DecoratorSet decorators = 0);
 994   void store_heap_oop(Register d, const Address& a, int offset = 0,
 995                       Register tmp = noreg, DecoratorSet decorators = 0);
 996 
 997   void encode_heap_oop(Register src, Register dst);
 998   void encode_heap_oop(Register r) {
 999     encode_heap_oop(r, r);
1000   }
1001   void decode_heap_oop(Register src, Register dst);
1002   void decode_heap_oop(Register r) {
1003     decode_heap_oop(r, r);
1004   }
1005   void encode_heap_oop_not_null(Register r);
1006   void decode_heap_oop_not_null(Register r);
1007   void encode_heap_oop_not_null(Register src, Register dst);
1008   void decode_heap_oop_not_null(Register src, Register dst);
1009 
1010   void encode_klass_not_null(Register r);
1011   void decode_klass_not_null(Register r);
1012   void encode_klass_not_null(Register src, Register dst);
1013   void decode_klass_not_null(Register src, Register dst);
1014 
1015   // Support for managing the JavaThread pointer (i.e.; the reference to
1016   // thread-local information).
1017   void get_thread();                                // load G2_thread
1018   void verify_thread();                             // verify G2_thread contents
1019   void save_thread   (const Register threache); // save to cache
1020   void restore_thread(const Register thread_cache); // restore from cache
1021 
1022   // Support for last Java frame (but use call_VM instead where possible)
1023   void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
1024   void reset_last_Java_frame(void);
1025 
1026   // Call into the VM.
1027   // Passes the thread pointer (in O0) as a prepended argument.
1028   // Makes sure oop return values are visible to the GC.
1029   void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1030   void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
1031   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1032   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1033 
1034   // these overloadings are not presently used on SPARC:
1035   void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1036   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1037   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1038   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1039 
1040   void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
1041   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
1042   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
1043   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
1044 
1045   void get_vm_result  (Register oop_result);
1046   void get_vm_result_2(Register metadata_result);
1047 
1048   // vm result is currently getting hijacked to for oop preservation
1049   void set_vm_result(Register oop_result);
1050 
1051   // Emit the CompiledIC call idiom
1052   void ic_call(address entry, bool emit_delay = true, jint method_index = 0);
1053 
1054   // if call_VM_base was called with check_exceptions=false, then call
1055   // check_and_forward_exception to handle exceptions when it is safe
1056   void check_and_forward_exception(Register scratch_reg);
1057 
1058   // Returns the byte size of the instructions generated by decode_klass_not_null().
1059   static int instr_size_for_decode_klass_not_null();
1060 
1061   // if heap base register is used - reinit it with the correct value
1062   void reinit_heapbase();
1063 
1064   // Debugging
1065   void _verify_oop(Register reg, const char * msg, const char * file, int line);
1066   void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
1067 
1068   // TODO: verify_method and klass metadata (compare against vptr?)
1069   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1070   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1071 
1072 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
1073 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
1074 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1075 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1076 
1077   void stop(const char* msg);                          // prints msg, dumps registers and stops execution
1078   void warn(const char* msg);                          // prints msg, but don't stop
1079   void untested(const char* what = "");
1080   void unimplemented(const char* what = "");
1081   void should_not_reach_here()                   { stop("should not reach here"); }
1082 
1083   // oops in code
1084   AddressLiteral allocate_oop_address(jobject obj);                          // allocate_index
1085   AddressLiteral constant_oop_address(jobject obj);                          // find_index
1086   inline void    set_oop             (jobject obj, Register d);              // uses allocate_oop_address
1087   inline void    set_oop_constant    (jobject obj, Register d);              // uses constant_oop_address
1088   inline void    set_oop             (const AddressLiteral& obj_addr, Register d); // same as load_address
1089 
1090   // metadata in code that we have to keep track of
1091   AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
1092   AddressLiteral constant_metadata_address(Metadata* obj); // find_index
1093   inline void    set_metadata             (Metadata* obj, Register d);              // uses allocate_metadata_address
1094   inline void    set_metadata_constant    (Metadata* obj, Register d);              // uses constant_metadata_address
1095   inline void    set_metadata             (const AddressLiteral& obj_addr, Register d); // same as load_address
1096 
1097   void set_narrow_oop( jobject obj, Register d );
1098   void set_narrow_klass( Klass* k, Register d );
1099 
1100   // nop padding
1101   void align(int modulus);
1102 
1103   // declare a safepoint
1104   void safepoint();
1105 
1106   // factor out part of stop into subroutine to save space
1107   void stop_subroutine();
1108   // factor out part of verify_oop into subroutine to save space
1109   void verify_oop_subroutine();
1110 
1111   // side-door communication with signalHandler in os_solaris.cpp
1112   static address _verify_oop_implicit_branch[3];
1113 
1114   int total_frame_size_in_bytes(int extraWords);
1115 
1116   // used when extraWords known statically
1117   void save_frame(int extraWords = 0);
1118   void save_frame_c1(int size_in_bytes);
1119   // make a frame, and simultaneously pass up one or two register value
1120   // into the new register window
1121   void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
1122 
1123   // give no. (outgoing) params, calc # of words will need on frame
1124   void calc_mem_param_words(Register Rparam_words, Register Rresult);
1125 
1126   // used to calculate frame size dynamically
1127   // result is in bytes and must be negated for save inst
1128   void calc_frame_size(Register extraWords, Register resultReg);
1129 
1130   // calc and also save
1131   void calc_frame_size_and_save(Register extraWords, Register resultReg);
1132 
1133   static void debug(char* msg, RegistersForDebugging* outWindow);
1134 
1135   // implementations of bytecodes used by both interpreter and compiler
1136 
1137   void lcmp( Register Ra_hi, Register Ra_low,
1138              Register Rb_hi, Register Rb_low,
1139              Register Rresult);
1140 
1141   void lneg( Register Rhi, Register Rlow );
1142 
1143   void lshl(  Register Rin_high,  Register Rin_low,  Register Rcount,
1144               Register Rout_high, Register Rout_low, Register Rtemp );
1145 
1146   void lshr(  Register Rin_high,  Register Rin_low,  Register Rcount,
1147               Register Rout_high, Register Rout_low, Register Rtemp );
1148 
1149   void lushr( Register Rin_high,  Register Rin_low,  Register Rcount,
1150               Register Rout_high, Register Rout_low, Register Rtemp );
1151 
1152   void lcmp( Register Ra, Register Rb, Register Rresult);
1153 
1154   // Load and store values by size and signed-ness
1155   void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
1156   void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1157 
1158   void float_cmp( bool is_float, int unordered_result,
1159                   FloatRegister Fa, FloatRegister Fb,
1160                   Register Rresult);
1161 
1162   void save_all_globals_into_locals();
1163   void restore_globals_from_locals();
1164 
1165   // These set the icc condition code to equal if the lock succeeded
1166   // and notEqual if it failed and requires a slow case
1167   void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
1168                             Register Rscratch,
1169                             BiasedLockingCounters* counters = NULL,
1170                             bool try_bias = UseBiasedLocking);
1171   void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
1172                               Register Rscratch,
1173                               bool try_bias = UseBiasedLocking);
1174 
1175   // Biased locking support
1176   // Upon entry, lock_reg must point to the lock record on the stack,
1177   // obj_reg must contain the target object, and mark_reg must contain
1178   // the target object's header.
1179   // Destroys mark_reg if an attempt is made to bias an anonymously
1180   // biased lock. In this case a failure will go either to the slow
1181   // case or fall through with the notEqual condition code set with
1182   // the expectation that the slow case in the runtime will be called.
1183   // In the fall-through case where the CAS-based lock is done,
1184   // mark_reg is not destroyed.
1185   void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
1186                             Label& done, Label* slow_case = NULL,
1187                             BiasedLockingCounters* counters = NULL);
1188   // Upon entry, the base register of mark_addr must contain the oop.
1189   // Destroys temp_reg.
1190 
1191   // If allow_delay_slot_filling is set to true, the next instruction
1192   // emitted after this one will go in an annulled delay slot if the
1193   // biased locking exit case failed.
1194   void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
1195 
1196   // allocation
1197   void eden_allocate(
1198     Register obj,                      // result: pointer to object after successful allocation
1199     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
1200     int      con_size_in_bytes,        // object size in bytes if   known at compile time
1201     Register t1,                       // temp register
1202     Register t2,                       // temp register
1203     Label&   slow_case                 // continuation point if fast allocation fails
1204   );
1205   void tlab_allocate(
1206     Register obj,                      // result: pointer to object after successful allocation
1207     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
1208     int      con_size_in_bytes,        // object size in bytes if   known at compile time
1209     Register t1,                       // temp register
1210     Label&   slow_case                 // continuation point if fast allocation fails
1211   );
1212   void zero_memory(Register base, Register index);
1213   void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
1214                             Register t1, Register t2);
1215 
1216   // interface method calling
1217   void lookup_interface_method(Register recv_klass,
1218                                Register intf_klass,
1219                                RegisterOrConstant itable_index,
1220                                Register method_result,
1221                                Register temp_reg, Register temp2_reg,
1222                                Label& no_such_interface,
1223                                bool return_method = true);
1224 
1225   // virtual method calling
1226   void lookup_virtual_method(Register recv_klass,
1227                              RegisterOrConstant vtable_index,
1228                              Register method_result);
1229 
1230   // Test sub_klass against super_klass, with fast and slow paths.
1231 
1232   // The fast path produces a tri-state answer: yes / no / maybe-slow.
1233   // One of the three labels can be NULL, meaning take the fall-through.
1234   // If super_check_offset is -1, the value is loaded up from super_klass.
1235   // No registers are killed, except temp_reg and temp2_reg.
1236   // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
1237   void check_klass_subtype_fast_path(Register sub_klass,
1238                                      Register super_klass,
1239                                      Register temp_reg,
1240                                      Register temp2_reg,
1241                                      Label* L_success,
1242                                      Label* L_failure,
1243                                      Label* L_slow_path,
1244                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1245 
1246   // The rest of the type check; must be wired to a corresponding fast path.
1247   // It does not repeat the fast path logic, so don't use it standalone.
1248   // The temp_reg can be noreg, if no temps are available.
1249   // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
1250   // Updates the sub's secondary super cache as necessary.
1251   void check_klass_subtype_slow_path(Register sub_klass,
1252                                      Register super_klass,
1253                                      Register temp_reg,
1254                                      Register temp2_reg,
1255                                      Register temp3_reg,
1256                                      Register temp4_reg,
1257                                      Label* L_success,
1258                                      Label* L_failure);
1259 
1260   // Simplified, combined version, good for typical uses.
1261   // Falls through on failure.
1262   void check_klass_subtype(Register sub_klass,
1263                            Register super_klass,
1264                            Register temp_reg,
1265                            Register temp2_reg,
1266                            Label& L_success);
1267 
1268   // method handles (JSR 292)
1269   // offset relative to Gargs of argument at tos[arg_slot].
1270   // (arg_slot == 0 means the last argument, not the first).
1271   RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
1272                                      Register temp_reg,
1273                                      int extra_slot_offset = 0);
1274   // Address of Gargs and argument_offset.
1275   Address            argument_address(RegisterOrConstant arg_slot,
1276                                       Register temp_reg = noreg,
1277                                       int extra_slot_offset = 0);
1278 
1279   // Stack overflow checking
1280 
1281   // Note: this clobbers G3_scratch
1282   void bang_stack_with_offset(int offset);
1283 
1284   // Writes to stack successive pages until offset reached to check for
1285   // stack overflow + shadow pages.  Clobbers tsp and scratch registers.
1286   void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
1287 
1288   // Check for reserved stack access in method being exited (for JIT)
1289   void reserved_stack_check();
1290 
1291   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
1292 
1293   void verify_tlab();
1294 
1295   Condition negate_condition(Condition cond);
1296 
1297   // Helper functions for statistics gathering.
1298   // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
1299   void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
1300   // Unconditional increment.
1301   void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
1302   void inc_counter(int*    counter_addr, Register Rtmp1, Register Rtmp2);
1303 
1304   // Use BIS for zeroing
1305   void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
1306 
1307   // Update CRC-32[C] with a byte value according to constants in table
1308   void update_byte_crc32(Register crc, Register val, Register table);
1309 
1310   // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros
1311   void reverse_bytes_32(Register src, Register dst, Register tmp);
1312   void movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2);
1313   void movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2);
1314 
1315   // CRC32 code for java.util.zip.CRC32::updateBytes0() intrinsic.
1316   void kernel_crc32(Register crc, Register buf, Register len, Register table);
1317   // Fold 128-bit data chunk
1318   void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset);
1319   void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo);
1320   // Fold 8-bit data
1321   void fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp);
1322   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1323   // CRC32C code for java.util.zip.CRC32C::updateBytes/updateDirectByteBuffer intrinsic.
1324   void kernel_crc32c(Register crc, Register buf, Register len, Register table);
1325 
1326 };
1327 
1328 /**
1329  * class SkipIfEqual:
1330  *
1331  * Instantiating this class will result in assembly code being output that will
1332  * jump around any code emitted between the creation of the instance and it's
1333  * automatic destruction at the end of a scope block, depending on the value of
1334  * the flag passed to the constructor, which will be checked at run-time.
1335  */
1336 class SkipIfEqual : public StackObj {
1337  private:
1338   MacroAssembler* _masm;
1339   Label _label;
1340 
1341  public:
1342    // 'temp' is a temp register that this object can use (and trash)
1343    SkipIfEqual(MacroAssembler*, Register temp,
1344                const bool* flag_addr, Assembler::Condition condition);
1345    ~SkipIfEqual();
1346 };
1347 
1348 #endif // CPU_SPARC_MACROASSEMBLER_SPARC_HPP