1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "logging/logStream.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "oops/compressedOops.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "runtime/vm_version.hpp"
36
37 #include <sys/mman.h>
38
39 uint VM_Version::_L2_data_cache_line_size = 0;
40
41 void VM_Version::initialize() {
42 assert(_features != 0, "System pre-initialization is not complete.");
43 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
44
45 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
46 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
47 PrefetchFieldsAhead = prefetch_fields_ahead();
48
49 // Allocation prefetch settings
50
51 AllocatePrefetchDistance = allocate_prefetch_distance();
52 AllocatePrefetchStyle = allocate_prefetch_style();
53
54 intx cache_line_size = prefetch_data_size();
55
56 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) {
57 AllocatePrefetchStepSize = MAX2(AllocatePrefetchStepSize, cache_line_size);
58 }
59
60 if (AllocatePrefetchInstr == 1) {
61 if (!has_blk_init()) {
62 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
63 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
64 }
65 if (cache_line_size <= 0) {
66 warning("Cache-line size must be known for AllocatePrefetchInstr 1 to work");
67 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
68 }
69 }
70
71 _supports_cx8 = true; // All SPARC V9 implementations.
72 _supports_atomic_getset4 = true; // Using the 'swap' instruction.
73
74 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseInlineCaches)) {
75 // Indirect and direct branches are cost equivalent.
76 FLAG_SET_DEFAULT(UseInlineCaches, false);
77 }
78 // Align loops on the proper instruction boundary to fill the instruction
79 // fetch buffer.
80 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
81 FLAG_SET_DEFAULT(OptoLoopAlignment, VM_Version::insn_fetch_alignment);
82 }
83
84 // 32-bit oops don't make sense for the 64-bit VM on SPARC since the 32-bit
85 // VM has the same registers and smaller objects.
86 CompressedOops::set_shift(LogMinObjAlignmentInBytes);
87 CompressedKlassPointers::set_shift(LogKlassAlignmentInBytes);
88
89 #ifdef COMPILER2
90 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseJumpTables)) {
91 // Indirect and direct branches are cost equivalent.
92 FLAG_SET_DEFAULT(UseJumpTables, true);
93 }
94 // Entry and loop tops are aligned to fill the instruction fetch buffer.
95 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
96 FLAG_SET_DEFAULT(InteriorEntryAlignment, VM_Version::insn_fetch_alignment);
97 }
98 if (UseTLAB && cache_line_size > 0 &&
99 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
100 if (has_fast_bis()) {
101 // Use BIS instruction for TLAB allocation prefetch.
102 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
103 }
104 else if (has_sparc5()) {
105 // Use prefetch instruction to avoid partial RAW issue on Core C4 processors,
106 // also use prefetch style 3.
107 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
108 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
109 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
110 }
111 }
112 }
113 if (AllocatePrefetchInstr == 1) {
114 // Use allocation prefetch style 3 because BIS instructions require
115 // aligned memory addresses.
116 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
117 }
118 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
119 if (AllocatePrefetchInstr == 0) {
120 // Use different prefetch distance without BIS
121 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
122 } else {
123 // Use smaller prefetch distance with BIS
124 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
125 }
126 }
127
128 // We increase the number of prefetched cache lines, to use just a bit more
129 // aggressive approach, when the L2-cache line size is small (32 bytes), or
130 // when running on newer processor implementations, such as the Core C4.
131 bool inc_prefetch = cache_line_size > 0 && (cache_line_size < 64 || has_sparc5());
132
133 if (inc_prefetch) {
134 // We use a factor two for small cache line sizes (as before) but a slightly
135 // more conservative increase when running on more recent hardware that will
136 // benefit from just a bit more aggressive prefetching.
137 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
138 const int ap_lns = AllocatePrefetchLines;
139 const int ap_inc = cache_line_size < 64 ? ap_lns : (ap_lns + 1) / 2;
140 FLAG_SET_ERGO(AllocatePrefetchLines, ap_lns + ap_inc);
141 }
142 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
143 const int ip_lns = AllocateInstancePrefetchLines;
144 const int ip_inc = cache_line_size < 64 ? ip_lns : (ip_lns + 1) / 2;
145 FLAG_SET_ERGO(AllocateInstancePrefetchLines, ip_lns + ip_inc);
146 }
147 }
148 #endif /* COMPILER2 */
149
150 // Use hardware population count instruction if available.
151 if (has_popc()) {
152 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
153 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
154 }
155 } else if (UsePopCountInstruction) {
156 warning("POPC instruction is not available on this CPU");
157 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
158 }
159
160 // Use compare and branch instructions if available.
161 if (has_cbcond()) {
162 if (FLAG_IS_DEFAULT(UseCBCond)) {
163 FLAG_SET_DEFAULT(UseCBCond, true);
164 }
165 } else if (UseCBCond) {
166 warning("CBCOND instruction is not available on this CPU");
167 FLAG_SET_DEFAULT(UseCBCond, false);
168 }
169
170 // Use 'mpmul' instruction if available.
171 if (has_mpmul()) {
172 if (FLAG_IS_DEFAULT(UseMPMUL)) {
173 FLAG_SET_DEFAULT(UseMPMUL, true);
174 }
175 } else if (UseMPMUL) {
176 warning("MPMUL instruction is not available on this CPU");
177 FLAG_SET_DEFAULT(UseMPMUL, false);
178 }
179
180 assert(BlockZeroingLowLimit > 0, "invalid value");
181
182 if (has_blk_zeroing() && cache_line_size > 0) {
183 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
184 FLAG_SET_DEFAULT(UseBlockZeroing, true);
185 }
186 } else if (UseBlockZeroing) {
187 warning("BIS zeroing instructions are not available on this CPU");
188 FLAG_SET_DEFAULT(UseBlockZeroing, false);
189 }
190
191 assert(BlockCopyLowLimit > 0, "invalid value");
192
193 if (has_blk_zeroing() && cache_line_size > 0) {
194 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
195 FLAG_SET_DEFAULT(UseBlockCopy, true);
196 }
197 } else if (UseBlockCopy) {
198 warning("BIS instructions are not available or expensive on this CPU");
199 FLAG_SET_DEFAULT(UseBlockCopy, false);
200 }
201
202 #ifdef COMPILER2
203 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
204 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
205 }
206
207 // Currently not supported anywhere.
208 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
209
210 MaxVectorSize = 8;
211
212 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
213 #endif
214
215 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
216 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
217
218 char buf[512];
219 jio_snprintf(buf, sizeof(buf),
220 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
221 "%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s"
222 "%s%s%s%s%s%s%s",
223 (has_v9() ? "v9" : ""),
224 (has_popc() ? ", popc" : ""),
225 (has_vis1() ? ", vis1" : ""),
226 (has_vis2() ? ", vis2" : ""),
227 (has_blk_init() ? ", blk_init" : ""),
228 (has_fmaf() ? ", fmaf" : ""),
229 (has_hpc() ? ", hpc" : ""),
230 (has_ima() ? ", ima" : ""),
231 (has_aes() ? ", aes" : ""),
232 (has_des() ? ", des" : ""),
233 (has_kasumi() ? ", kas" : ""),
234 (has_camellia() ? ", cam" : ""),
235 (has_md5() ? ", md5" : ""),
236 (has_sha1() ? ", sha1" : ""),
237 (has_sha256() ? ", sha256" : ""),
238 (has_sha512() ? ", sha512" : ""),
239 (has_mpmul() ? ", mpmul" : ""),
240 (has_mont() ? ", mont" : ""),
241 (has_pause() ? ", pause" : ""),
242 (has_cbcond() ? ", cbcond" : ""),
243 (has_crc32c() ? ", crc32c" : ""),
244
245 (has_athena_plus() ? ", athena_plus" : ""),
246 (has_vis3b() ? ", vis3b" : ""),
247 (has_adi() ? ", adi" : ""),
248 (has_sparc5() ? ", sparc5" : ""),
249 (has_mwait() ? ", mwait" : ""),
250 (has_xmpmul() ? ", xmpmul" : ""),
251 (has_xmont() ? ", xmont" : ""),
252 (has_pause_nsec() ? ", pause_nsec" : ""),
253 (has_vamask() ? ", vamask" : ""),
254
255 (has_sparc6() ? ", sparc6" : ""),
256 (has_dictunp() ? ", dictunp" : ""),
257 (has_fpcmpshl() ? ", fpcmpshl" : ""),
258 (has_rle() ? ", rle" : ""),
259 (has_sha3() ? ", sha3" : ""),
260 (has_athena_plus2()? ", athena_plus2" : ""),
261 (has_vis3c() ? ", vis3c" : ""),
262 (has_sparc5b() ? ", sparc5b" : ""),
263 (has_mme() ? ", mme" : ""),
264
265 (has_fast_idiv() ? ", *idiv" : ""),
266 (has_fast_rdpc() ? ", *rdpc" : ""),
267 (has_fast_bis() ? ", *bis" : ""),
268 (has_fast_ld() ? ", *ld" : ""),
269 (has_fast_cmove() ? ", *cmove" : ""),
270 (has_fast_ind_br() ? ", *ind_br" : ""),
271 (has_blk_zeroing() ? ", *blk_zeroing" : ""));
272
273 assert(strlen(buf) >= 2, "must be");
274
275 _features_string = os::strdup(buf);
276
277 log_info(os, cpu)("SPARC features detected: %s", _features_string);
278
279 // UseVIS is set to the smallest of what hardware supports and what the command
280 // line requires, i.e. you cannot set UseVIS to 3 on older UltraSparc which do
281 // not support it.
282
283 if (UseVIS > 3) UseVIS = 3;
284 if (UseVIS < 0) UseVIS = 0;
285 if (!has_vis3()) // Drop to 2 if no VIS3 support
286 UseVIS = MIN2((intx)2, UseVIS);
287 if (!has_vis2()) // Drop to 1 if no VIS2 support
288 UseVIS = MIN2((intx)1, UseVIS);
289 if (!has_vis1()) // Drop to 0 if no VIS1 support
290 UseVIS = 0;
291
292 if (has_aes()) {
293 if (FLAG_IS_DEFAULT(UseAES)) {
294 FLAG_SET_DEFAULT(UseAES, true);
295 }
296 if (!UseAES) {
297 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
298 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
299 }
300 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
301 } else {
302 // The AES intrinsic stubs require AES instruction support (of course)
303 // but also require VIS3 mode or higher for instructions it use.
304 if (UseVIS > 2) {
305 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
306 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
307 }
308 } else {
309 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
310 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
311 }
312 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
313 }
314 }
315 } else if (UseAES || UseAESIntrinsics) {
316 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
317 warning("AES instructions are not available on this CPU");
318 FLAG_SET_DEFAULT(UseAES, false);
319 }
320 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
321 warning("AES intrinsics are not available on this CPU");
322 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
323 }
324 }
325
326 if (UseAESCTRIntrinsics) {
327 warning("AES/CTR intrinsics are not available on this CPU");
328 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
329 }
330
331 // GHASH/GCM intrinsics
332 if (has_vis3() && (UseVIS > 2)) {
333 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
334 UseGHASHIntrinsics = true;
335 }
336 } else if (UseGHASHIntrinsics) {
337 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
338 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
339 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
340 }
341
342 if (has_fmaf()) {
343 if (FLAG_IS_DEFAULT(UseFMA)) {
344 UseFMA = true;
345 }
346 } else if (UseFMA) {
347 warning("FMA instructions are not available on this CPU");
348 FLAG_SET_DEFAULT(UseFMA, false);
349 }
350
351 // SHA1, SHA256, and SHA512 instructions were added to SPARC at different times
352 if (has_sha1() || has_sha256() || has_sha512()) {
353 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
354 if (FLAG_IS_DEFAULT(UseSHA)) {
355 FLAG_SET_DEFAULT(UseSHA, true);
356 }
357 } else {
358 if (UseSHA) {
359 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
360 FLAG_SET_DEFAULT(UseSHA, false);
361 }
362 }
363 } else if (UseSHA) {
364 warning("SHA instructions are not available on this CPU");
365 FLAG_SET_DEFAULT(UseSHA, false);
366 }
367
368 if (UseSHA && has_sha1()) {
369 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
370 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
371 }
372 } else if (UseSHA1Intrinsics) {
373 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
374 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
375 }
376
377 if (UseSHA && has_sha256()) {
378 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
379 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
380 }
381 } else if (UseSHA256Intrinsics) {
382 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
383 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
384 }
385
386 if (UseSHA && has_sha512()) {
387 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
388 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
389 }
390 } else if (UseSHA512Intrinsics) {
391 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
392 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
393 }
394
395 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
396 FLAG_SET_DEFAULT(UseSHA, false);
397 }
398
399 if (has_crc32c()) {
400 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
401 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
402 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
403 }
404 } else {
405 if (UseCRC32CIntrinsics) {
406 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
407 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
408 }
409 }
410 } else if (UseCRC32CIntrinsics) {
411 warning("CRC32C instruction is not available on this CPU");
412 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
413 }
414
415 if (UseVIS > 2) {
416 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
417 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
418 }
419 } else if (UseAdler32Intrinsics) {
420 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
421 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
422 }
423
424 if (UseVIS > 2) {
425 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
426 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
427 }
428 } else if (UseCRC32Intrinsics) {
429 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
430 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
431 }
432
433 if (UseVIS > 2) {
434 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
435 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, true);
436 }
437 } else if (UseMultiplyToLenIntrinsic) {
438 warning("SPARC multiplyToLen intrinsics require VIS3 instructions support. Intrinsics will be disabled");
439 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
440 }
441
442 if (UseVectorizedMismatchIntrinsic) {
443 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
444 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
445 }
446
447 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
448 (cache_line_size > ContendedPaddingWidth))
449 ContendedPaddingWidth = cache_line_size;
450
451 // This machine does not allow unaligned memory accesses
452 if (UseUnalignedAccesses) {
453 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
454 warning("Unaligned memory access is not available on this CPU");
455 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
456 }
457
458 if (log_is_enabled(Info, os, cpu)) {
459 ResourceMark rm;
460 LogStream ls(Log(os, cpu)::info());
461 outputStream* log = &ls;
462 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
463 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
464 log->print("Allocation");
465 if (AllocatePrefetchStyle <= 0) {
466 log->print(": no prefetching");
467 } else {
468 log->print(" prefetching: ");
469 if (AllocatePrefetchInstr == 0) {
470 log->print("PREFETCH");
471 } else if (AllocatePrefetchInstr == 1) {
472 log->print("BIS");
473 }
474 if (AllocatePrefetchLines > 1) {
475 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
476 } else {
477 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
478 }
479 }
480 if (PrefetchCopyIntervalInBytes > 0) {
481 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
482 }
483 if (PrefetchScanIntervalInBytes > 0) {
484 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
485 }
486 if (PrefetchFieldsAhead > 0) {
487 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
488 }
489 if (ContendedPaddingWidth > 0) {
490 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
491 }
492 }
493 }
494
495 void VM_Version::print_features() {
496 tty->print("ISA features [0x%0" PRIx64 "]:", _features);
497 if (_features_string != NULL) {
498 tty->print(" %s", _features_string);
499 }
500 tty->cr();
501 }
502
503 void VM_Version::determine_features() {
504 platform_features(); // platform_features() is os_arch specific.
505
506 assert(has_v9(), "must be");
507
508 if (UseNiagaraInstrs) { // Limit code generation to Niagara.
509 _features &= niagara1_msk;
510 }
511 }
512
513 static uint64_t saved_features = 0;
514
515 void VM_Version::allow_all() {
516 saved_features = _features;
517 _features = full_feature_msk;
518 }
519
520 void VM_Version::revert() {
521 _features = saved_features;
522 }