1 /* 2 * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_GLOBALDEFINITIONS_X86_HPP 26 #define CPU_X86_GLOBALDEFINITIONS_X86_HPP 27 28 const int StackAlignmentInBytes = 16; 29 30 // Indicates whether the C calling conventions require that 31 // 32-bit integer argument values are extended to 64 bits. 32 const bool CCallingConventionRequiresIntsAsLongs = false; 33 34 #define SUPPORTS_NATIVE_CX8 35 36 #define CPU_MULTI_COPY_ATOMIC 37 38 // The expected size in bytes of a cache line, used to pad data structures. 39 #if defined(TIERED) 40 #ifdef _LP64 41 // tiered, 64-bit, large machine 42 #define DEFAULT_CACHE_LINE_SIZE 128 43 #define OM_CACHE_LINE_SIZE 64 44 #else 45 // tiered, 32-bit, medium machine 46 #define DEFAULT_CACHE_LINE_SIZE 64 47 #endif 48 #elif defined(COMPILER1) 49 // pure C1, 32-bit, small machine 50 // i486 was the last Intel chip with 16-byte cache line size 51 #define DEFAULT_CACHE_LINE_SIZE 32 52 #elif defined(COMPILER2) 53 #ifdef _LP64 54 // pure C2, 64-bit, large machine 55 #define DEFAULT_CACHE_LINE_SIZE 128 56 #define OM_CACHE_LINE_SIZE 64 57 #else 58 // pure C2, 32-bit, medium machine 59 #define DEFAULT_CACHE_LINE_SIZE 64 60 #endif 61 #endif 62 63 #if defined(COMPILER2) 64 // Include Restricted Transactional Memory lock eliding optimization 65 #define INCLUDE_RTM_OPT 1 66 #endif 67 68 #if defined(LINUX) || defined(SOLARIS) || defined(__APPLE__) 69 #define SUPPORT_RESERVED_STACK_AREA 70 #endif 71 72 #endif // CPU_X86_GLOBALDEFINITIONS_X86_HPP