48 #elif defined(COMPILER1)
  49   // pure C1, 32-bit, small machine
  50   // i486 was the last Intel chip with 16-byte cache line size
  51   #define DEFAULT_CACHE_LINE_SIZE 32
  52 #elif defined(COMPILER2)
  53   #ifdef _LP64
  54     // pure C2, 64-bit, large machine
  55     #define DEFAULT_CACHE_LINE_SIZE 128
  56     #define OM_CACHE_LINE_SIZE 64
  57   #else
  58     // pure C2, 32-bit, medium machine
  59     #define DEFAULT_CACHE_LINE_SIZE 64
  60   #endif
  61 #endif
  62 
  63 #if defined(COMPILER2)
  64 // Include Restricted Transactional Memory lock eliding optimization
  65 #define INCLUDE_RTM_OPT 1
  66 #endif
  67 
  68 #if defined(LINUX) || defined(SOLARIS) || defined(__APPLE__)
  69 #define SUPPORT_RESERVED_STACK_AREA
  70 #endif
  71 
  72 #if INCLUDE_JVMCI
  73 #define COMPRESSED_CLASS_POINTERS_DEPENDS_ON_COMPRESSED_OOPS (EnableJVMCI || UseAOT)
  74 #else
  75 #define COMPRESSED_CLASS_POINTERS_DEPENDS_ON_COMPRESSED_OOPS false
  76 #endif
  77 
  78 #endif // CPU_X86_GLOBALDEFINITIONS_X86_HPP

  48 #elif defined(COMPILER1)
  49   // pure C1, 32-bit, small machine
  50   // i486 was the last Intel chip with 16-byte cache line size
  51   #define DEFAULT_CACHE_LINE_SIZE 32
  52 #elif defined(COMPILER2)
  53   #ifdef _LP64
  54     // pure C2, 64-bit, large machine
  55     #define DEFAULT_CACHE_LINE_SIZE 128
  56     #define OM_CACHE_LINE_SIZE 64
  57   #else
  58     // pure C2, 32-bit, medium machine
  59     #define DEFAULT_CACHE_LINE_SIZE 64
  60   #endif
  61 #endif
  62 
  63 #if defined(COMPILER2)
  64 // Include Restricted Transactional Memory lock eliding optimization
  65 #define INCLUDE_RTM_OPT 1
  66 #endif
  67 
  68 #if defined(LINUX) || defined(__APPLE__)
  69 #define SUPPORT_RESERVED_STACK_AREA
  70 #endif
  71 
  72 #if INCLUDE_JVMCI
  73 #define COMPRESSED_CLASS_POINTERS_DEPENDS_ON_COMPRESSED_OOPS (EnableJVMCI || UseAOT)
  74 #else
  75 #define COMPRESSED_CLASS_POINTERS_DEPENDS_ON_COMPRESSED_OOPS false
  76 #endif
  77 
  78 #endif // CPU_X86_GLOBALDEFINITIONS_X86_HPP