1 /*
   2  * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
  26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
  27 
  28 #include "asm/register.hpp"
  29 
  30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
  31 // level; i.e., what you write
  32 // is what you get. The Assembler is generating code into a CodeBuffer.
  33 
  34 class Assembler : public AbstractAssembler  {
  35   friend class AbstractAssembler;
  36   friend class AddressLiteral;
  37 
  38   // code patchers need various routines like inv_wdisp()
  39   friend class NativeInstruction;
  40   friend class NativeGeneralJump;
  41   friend class Relocation;
  42   friend class Label;
  43 
  44  public:
  45   // op carries format info; see page 62 & 267
  46 
  47   enum ops {
  48     call_op   = 1, // fmt 1
  49     branch_op = 0, // also sethi (fmt2)
  50     arith_op  = 2, // fmt 3, arith & misc
  51     ldst_op   = 3  // fmt 3, load/store
  52   };
  53 
  54   enum op2s {
  55     bpr_op2   = 3,
  56     fb_op2    = 6,
  57     fbp_op2   = 5,
  58     br_op2    = 2,
  59     bp_op2    = 1,
  60     sethi_op2 = 4
  61   };
  62 
  63   enum op3s {
  64     // selected op3s
  65     add_op3      = 0x00,
  66     and_op3      = 0x01,
  67     or_op3       = 0x02,
  68     xor_op3      = 0x03,
  69     sub_op3      = 0x04,
  70     andn_op3     = 0x05,
  71     orn_op3      = 0x06,
  72     xnor_op3     = 0x07,
  73     addc_op3     = 0x08,
  74     mulx_op3     = 0x09,
  75     umul_op3     = 0x0a,
  76     smul_op3     = 0x0b,
  77     subc_op3     = 0x0c,
  78     udivx_op3    = 0x0d,
  79     udiv_op3     = 0x0e,
  80     sdiv_op3     = 0x0f,
  81 
  82     addcc_op3    = 0x10,
  83     andcc_op3    = 0x11,
  84     orcc_op3     = 0x12,
  85     xorcc_op3    = 0x13,
  86     subcc_op3    = 0x14,
  87     andncc_op3   = 0x15,
  88     orncc_op3    = 0x16,
  89     xnorcc_op3   = 0x17,
  90     addccc_op3   = 0x18,
  91     umulcc_op3   = 0x1a,
  92     smulcc_op3   = 0x1b,
  93     subccc_op3   = 0x1c,
  94     udivcc_op3   = 0x1e,
  95     sdivcc_op3   = 0x1f,
  96 
  97     taddcc_op3   = 0x20,
  98     tsubcc_op3   = 0x21,
  99     taddcctv_op3 = 0x22,
 100     tsubcctv_op3 = 0x23,
 101     mulscc_op3   = 0x24,
 102     sll_op3      = 0x25,
 103     sllx_op3     = 0x25,
 104     srl_op3      = 0x26,
 105     srlx_op3     = 0x26,
 106     sra_op3      = 0x27,
 107     srax_op3     = 0x27,
 108     rdreg_op3    = 0x28,
 109     membar_op3   = 0x28,
 110 
 111     flushw_op3   = 0x2b,
 112     movcc_op3    = 0x2c,
 113     sdivx_op3    = 0x2d,
 114     popc_op3     = 0x2e,
 115     movr_op3     = 0x2f,
 116 
 117     sir_op3      = 0x30,
 118     wrreg_op3    = 0x30,
 119     saved_op3    = 0x31,
 120 
 121     fpop1_op3    = 0x34,
 122     fpop2_op3    = 0x35,
 123     impdep1_op3  = 0x36,
 124     impdep2_op3  = 0x37,
 125     jmpl_op3     = 0x38,
 126     rett_op3     = 0x39,
 127     trap_op3     = 0x3a,
 128     flush_op3    = 0x3b,
 129     save_op3     = 0x3c,
 130     restore_op3  = 0x3d,
 131     done_op3     = 0x3e,
 132     retry_op3    = 0x3e,
 133 
 134     lduw_op3     = 0x00,
 135     ldub_op3     = 0x01,
 136     lduh_op3     = 0x02,
 137     ldd_op3      = 0x03,
 138     stw_op3      = 0x04,
 139     stb_op3      = 0x05,
 140     sth_op3      = 0x06,
 141     std_op3      = 0x07,
 142     ldsw_op3     = 0x08,
 143     ldsb_op3     = 0x09,
 144     ldsh_op3     = 0x0a,
 145     ldx_op3      = 0x0b,
 146 
 147     stx_op3      = 0x0e,
 148     swap_op3     = 0x0f,
 149 
 150     stwa_op3     = 0x14,
 151     stxa_op3     = 0x1e,
 152 
 153     ldf_op3      = 0x20,
 154     ldfsr_op3    = 0x21,
 155     ldqf_op3     = 0x22,
 156     lddf_op3     = 0x23,
 157     stf_op3      = 0x24,
 158     stfsr_op3    = 0x25,
 159     stqf_op3     = 0x26,
 160     stdf_op3     = 0x27,
 161 
 162     prefetch_op3 = 0x2d,
 163 
 164     casa_op3     = 0x3c,
 165     casxa_op3    = 0x3e,
 166 
 167     mftoi_op3    = 0x36,
 168 
 169     alt_bit_op3  = 0x10,
 170      cc_bit_op3  = 0x10
 171   };
 172 
 173   enum opfs {
 174     // selected opfs
 175     fmovs_opf   = 0x01,
 176     fmovd_opf   = 0x02,
 177 
 178     fnegs_opf   = 0x05,
 179     fnegd_opf   = 0x06,
 180 
 181     fadds_opf   = 0x41,
 182     faddd_opf   = 0x42,
 183     fsubs_opf   = 0x45,
 184     fsubd_opf   = 0x46,
 185 
 186     fmuls_opf   = 0x49,
 187     fmuld_opf   = 0x4a,
 188     fdivs_opf   = 0x4d,
 189     fdivd_opf   = 0x4e,
 190 
 191     fcmps_opf   = 0x51,
 192     fcmpd_opf   = 0x52,
 193 
 194     fstox_opf   = 0x81,
 195     fdtox_opf   = 0x82,
 196     fxtos_opf   = 0x84,
 197     fxtod_opf   = 0x88,
 198     fitos_opf   = 0xc4,
 199     fdtos_opf   = 0xc6,
 200     fitod_opf   = 0xc8,
 201     fstod_opf   = 0xc9,
 202     fstoi_opf   = 0xd1,
 203     fdtoi_opf   = 0xd2,
 204 
 205     mdtox_opf   = 0x110,
 206     mstouw_opf  = 0x111,
 207     mstosw_opf  = 0x113,
 208     mxtod_opf   = 0x118,
 209     mwtos_opf   = 0x119
 210   };
 211 
 212   enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez  };
 213 
 214   enum Condition {
 215      // for FBfcc & FBPfcc instruction
 216     f_never                     = 0,
 217     f_notEqual                  = 1,
 218     f_notZero                   = 1,
 219     f_lessOrGreater             = 2,
 220     f_unorderedOrLess           = 3,
 221     f_less                      = 4,
 222     f_unorderedOrGreater        = 5,
 223     f_greater                   = 6,
 224     f_unordered                 = 7,
 225     f_always                    = 8,
 226     f_equal                     = 9,
 227     f_zero                      = 9,
 228     f_unorderedOrEqual          = 10,
 229     f_greaterOrEqual            = 11,
 230     f_unorderedOrGreaterOrEqual = 12,
 231     f_lessOrEqual               = 13,
 232     f_unorderedOrLessOrEqual    = 14,
 233     f_ordered                   = 15,
 234 
 235     // V8 coproc, pp 123 v8 manual
 236 
 237     cp_always  = 8,
 238     cp_never   = 0,
 239     cp_3       = 7,
 240     cp_2       = 6,
 241     cp_2or3    = 5,
 242     cp_1       = 4,
 243     cp_1or3    = 3,
 244     cp_1or2    = 2,
 245     cp_1or2or3 = 1,
 246     cp_0       = 9,
 247     cp_0or3    = 10,
 248     cp_0or2    = 11,
 249     cp_0or2or3 = 12,
 250     cp_0or1    = 13,
 251     cp_0or1or3 = 14,
 252     cp_0or1or2 = 15,
 253 
 254 
 255     // for integers
 256 
 257     never                 =  0,
 258     equal                 =  1,
 259     zero                  =  1,
 260     lessEqual             =  2,
 261     less                  =  3,
 262     lessEqualUnsigned     =  4,
 263     lessUnsigned          =  5,
 264     carrySet              =  5,
 265     negative              =  6,
 266     overflowSet           =  7,
 267     always                =  8,
 268     notEqual              =  9,
 269     notZero               =  9,
 270     greater               =  10,
 271     greaterEqual          =  11,
 272     greaterUnsigned       =  12,
 273     greaterEqualUnsigned  =  13,
 274     carryClear            =  13,
 275     positive              =  14,
 276     overflowClear         =  15
 277   };
 278 
 279   enum CC {
 280     icc  = 0,  xcc  = 2,
 281     // ptr_cc is the correct condition code for a pointer or intptr_t:
 282     ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
 283     fcc0 = 0,  fcc1 = 1, fcc2 = 2, fcc3 = 3
 284   };
 285 
 286   enum PrefetchFcn {
 287     severalReads = 0,  oneRead = 1,  severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
 288   };
 289 
 290  public:
 291   // Helper functions for groups of instructions
 292 
 293   enum Predict { pt = 1, pn = 0 }; // pt = predict taken
 294 
 295   enum Membar_mask_bits { // page 184, v9
 296     StoreStore = 1 << 3,
 297     LoadStore  = 1 << 2,
 298     StoreLoad  = 1 << 1,
 299     LoadLoad   = 1 << 0,
 300 
 301     Sync       = 1 << 6,
 302     MemIssue   = 1 << 5,
 303     Lookaside  = 1 << 4
 304   };
 305 
 306   static bool is_in_wdisp_range(address a, address b, int nbits) {
 307     intptr_t d = intptr_t(b) - intptr_t(a);
 308     return is_simm(d, nbits + 2);
 309   }
 310 
 311   address target_distance(Label& L) {
 312     // Assembler::target(L) should be called only when
 313     // a branch instruction is emitted since non-bound
 314     // labels record current pc() as a branch address.
 315     if (L.is_bound()) return target(L);
 316     // Return current address for non-bound labels.
 317     return pc();
 318   }
 319 
 320   // test if label is in simm16 range in words (wdisp16).
 321   bool is_in_wdisp16_range(Label& L) {
 322     return is_in_wdisp_range(target_distance(L), pc(), 16);
 323   }
 324   // test if the distance between two addresses fits in simm30 range in words
 325   static bool is_in_wdisp30_range(address a, address b) {
 326     return is_in_wdisp_range(a, b, 30);
 327   }
 328 
 329   enum ASIs { // page 72, v9
 330     ASI_PRIMARY            = 0x80,
 331     ASI_PRIMARY_NOFAULT    = 0x82,
 332     ASI_PRIMARY_LITTLE     = 0x88,
 333     // Block initializing store
 334     ASI_ST_BLKINIT_PRIMARY = 0xE2,
 335     // Most-Recently-Used (MRU) BIS variant
 336     ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
 337     // add more from book as needed
 338   };
 339 
 340  protected:
 341   // helpers
 342 
 343   // x is supposed to fit in a field "nbits" wide
 344   // and be sign-extended. Check the range.
 345 
 346   static void assert_signed_range(intptr_t x, int nbits) {
 347     assert(nbits == 32 || (-(1 << nbits-1) <= x  &&  x < ( 1 << nbits-1)),
 348            err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
 349   }
 350 
 351   static void assert_signed_word_disp_range(intptr_t x, int nbits) {
 352     assert( (x & 3) == 0, "not word aligned");
 353     assert_signed_range(x, nbits + 2);
 354   }
 355 
 356   static void assert_unsigned_const(int x, int nbits) {
 357     assert( juint(x)  <  juint(1 << nbits), "unsigned constant out of range");
 358   }
 359 
 360   // fields: note bits numbered from LSB = 0,
 361   //  fields known by inclusive bit range
 362 
 363   static int fmask(juint hi_bit, juint lo_bit) {
 364     assert( hi_bit >= lo_bit  &&  0 <= lo_bit  &&  hi_bit < 32, "bad bits");
 365     return (1 << ( hi_bit-lo_bit + 1 )) - 1;
 366   }
 367 
 368   // inverse of u_field
 369 
 370   static int inv_u_field(int x, int hi_bit, int lo_bit) {
 371     juint r = juint(x) >> lo_bit;
 372     r &= fmask( hi_bit, lo_bit);
 373     return int(r);
 374   }
 375 
 376 
 377   // signed version: extract from field and sign-extend
 378 
 379   static int inv_s_field(int x, int hi_bit, int lo_bit) {
 380     int sign_shift = 31 - hi_bit;
 381     return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
 382   }
 383 
 384   // given a field that ranges from hi_bit to lo_bit (inclusive,
 385   // LSB = 0), and an unsigned value for the field,
 386   // shift it into the field
 387 
 388 #ifdef ASSERT
 389   static int u_field(int x, int hi_bit, int lo_bit) {
 390     assert( ( x & ~fmask(hi_bit, lo_bit))  == 0,
 391             "value out of range");
 392     int r = x << lo_bit;
 393     assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
 394     return r;
 395   }
 396 #else
 397   // make sure this is inlined as it will reduce code size significantly
 398   #define u_field(x, hi_bit, lo_bit)   ((x) << (lo_bit))
 399 #endif
 400 
 401   static int inv_op(  int x ) { return inv_u_field(x, 31, 30); }
 402   static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
 403   static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
 404   static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
 405 
 406   static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
 407 
 408   static Register inv_rd(  int x ) { return as_Register(inv_u_field(x, 29, 25)); }
 409   static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
 410   static Register inv_rs2( int x ) { return as_Register(inv_u_field(x,  4,  0)); }
 411 
 412   static int op(       int         x)  { return  u_field(x,             31, 30); }
 413   static int rd(       Register    r)  { return  u_field(r->encoding(), 29, 25); }
 414   static int fcn(      int         x)  { return  u_field(x,             29, 25); }
 415   static int op3(      int         x)  { return  u_field(x,             24, 19); }
 416   static int rs1(      Register    r)  { return  u_field(r->encoding(), 18, 14); }
 417   static int rs2(      Register    r)  { return  u_field(r->encoding(),  4,  0); }
 418   static int annul(    bool        a)  { return  u_field(a ? 1 : 0,     29, 29); }
 419   static int cond(     int         x)  { return  u_field(x,             28, 25); }
 420   static int cond_mov( int         x)  { return  u_field(x,             17, 14); }
 421   static int rcond(    RCondition  x)  { return  u_field(x,             12, 10); }
 422   static int op2(      int         x)  { return  u_field(x,             24, 22); }
 423   static int predict(  bool        p)  { return  u_field(p ? 1 : 0,     19, 19); }
 424   static int branchcc( CC       fcca)  { return  u_field(fcca,          21, 20); }
 425   static int cmpcc(    CC       fcca)  { return  u_field(fcca,          26, 25); }
 426   static int imm_asi(  int         x)  { return  u_field(x,             12,  5); }
 427   static int immed(    bool        i)  { return  u_field(i ? 1 : 0,     13, 13); }
 428   static int opf_low6( int         w)  { return  u_field(w,             10,  5); }
 429   static int opf_low5( int         w)  { return  u_field(w,              9,  5); }
 430   static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }
 431   static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit
 432   static int opf(      int         x)  { return  u_field(x,             13,  5); }
 433 
 434   static bool is_cbcond( int x ) {
 435     return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
 436             inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
 437   }
 438   static bool is_cxb( int x ) {
 439     assert(is_cbcond(x), "wrong instruction");
 440     return (x & (1<<21)) != 0;
 441   }
 442   static int cond_cbcond( int         x)  { return  u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
 443   static int inv_cond_cbcond(int      x)  {
 444     assert(is_cbcond(x), "wrong instruction");
 445     return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
 446   }
 447 
 448   static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
 449   static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }
 450 
 451   static int fd( FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
 452   static int fs1(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
 453   static int fs2(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
 454 
 455   // some float instructions use this encoding on the op3 field
 456   static int alt_op3(int op, FloatRegisterImpl::Width w) {
 457     int r;
 458     switch(w) {
 459      case FloatRegisterImpl::S: r = op + 0;  break;
 460      case FloatRegisterImpl::D: r = op + 3;  break;
 461      case FloatRegisterImpl::Q: r = op + 2;  break;
 462      default: ShouldNotReachHere(); break;
 463     }
 464     return op3(r);
 465   }
 466 
 467 
 468   // compute inverse of simm
 469   static int inv_simm(int x, int nbits) {
 470     return (int)(x << (32 - nbits)) >> (32 - nbits);
 471   }
 472 
 473   static int inv_simm13( int x ) { return inv_simm(x, 13); }
 474 
 475   // signed immediate, in low bits, nbits long
 476   static int simm(int x, int nbits) {
 477     assert_signed_range(x, nbits);
 478     return x  &  (( 1 << nbits ) - 1);
 479   }
 480 
 481   // compute inverse of wdisp16
 482   static intptr_t inv_wdisp16(int x, intptr_t pos) {
 483     int lo = x & (( 1 << 14 ) - 1);
 484     int hi = (x >> 20) & 3;
 485     if (hi >= 2) hi |= ~1;
 486     return (((hi << 14) | lo) << 2) + pos;
 487   }
 488 
 489   // word offset, 14 bits at LSend, 2 bits at B21, B20
 490   static int wdisp16(intptr_t x, intptr_t off) {
 491     intptr_t xx = x - off;
 492     assert_signed_word_disp_range(xx, 16);
 493     int r =  (xx >> 2) & ((1 << 14) - 1)
 494            |  (  ( (xx>>(2+14)) & 3 )  <<  20 );
 495     assert( inv_wdisp16(r, off) == x,  "inverse is not inverse");
 496     return r;
 497   }
 498 
 499   // compute inverse of wdisp10
 500   static intptr_t inv_wdisp10(int x, intptr_t pos) {
 501     assert(is_cbcond(x), "wrong instruction");
 502     int lo = inv_u_field(x, 12, 5);
 503     int hi = (x >> 19) & 3;
 504     if (hi >= 2) hi |= ~1;
 505     return (((hi << 8) | lo) << 2) + pos;
 506   }
 507 
 508   // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
 509   static int wdisp10(intptr_t x, intptr_t off) {
 510     assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
 511     intptr_t xx = x - off;
 512     assert_signed_word_disp_range(xx, 10);
 513     int r =  ( ( (xx >>  2   ) & ((1 << 8) - 1) ) <<  5 )
 514            | ( ( (xx >> (2+8)) & 3              ) << 19 );
 515     // Have to fake cbcond instruction to pass assert in inv_wdisp10()
 516     assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x,  "inverse is not inverse");
 517     return r;
 518   }
 519 
 520   // word displacement in low-order nbits bits
 521 
 522   static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
 523     int pre_sign_extend = x & (( 1 << nbits ) - 1);
 524     int r =  pre_sign_extend >= ( 1 << (nbits-1) )
 525        ?   pre_sign_extend | ~(( 1 << nbits ) - 1)
 526        :   pre_sign_extend;
 527     return (r << 2) + pos;
 528   }
 529 
 530   static int wdisp( intptr_t x, intptr_t off, int nbits ) {
 531     intptr_t xx = x - off;
 532     assert_signed_word_disp_range(xx, nbits);
 533     int r =  (xx >> 2) & (( 1 << nbits ) - 1);
 534     assert( inv_wdisp( r, off, nbits )  ==  x, "inverse not inverse");
 535     return r;
 536   }
 537 
 538 
 539   // Extract the top 32 bits in a 64 bit word
 540   static int32_t hi32( int64_t x ) {
 541     int32_t r = int32_t( (uint64_t)x >> 32 );
 542     return r;
 543   }
 544 
 545   // given a sethi instruction, extract the constant, left-justified
 546   static int inv_hi22( int x ) {
 547     return x << 10;
 548   }
 549 
 550   // create an imm22 field, given a 32-bit left-justified constant
 551   static int hi22( int x ) {
 552     int r = int( juint(x) >> 10 );
 553     assert( (r & ~((1 << 22) - 1))  ==  0, "just checkin'");
 554     return r;
 555   }
 556 
 557   // create a low10 __value__ (not a field) for a given a 32-bit constant
 558   static int low10( int x ) {
 559     return x & ((1 << 10) - 1);
 560   }
 561 
 562   // instruction only in VIS3
 563   static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
 564 
 565   // instruction only in v9
 566   static void v9_only() { } // do nothing
 567 
 568   // instruction deprecated in v9
 569   static void v9_dep()  { } // do nothing for now
 570 
 571   // v8 has no CC field
 572   static void v8_no_cc(CC cc)  { if (cc)  v9_only(); }
 573 
 574  protected:
 575   // Simple delay-slot scheme:
 576   // In order to check the programmer, the assembler keeps track of deley slots.
 577   // It forbids CTIs in delay slots (conservative, but should be OK).
 578   // Also, when putting an instruction into a delay slot, you must say
 579   // asm->delayed()->add(...), in order to check that you don't omit
 580   // delay-slot instructions.
 581   // To implement this, we use a simple FSA
 582 
 583 #ifdef ASSERT
 584   #define CHECK_DELAY
 585 #endif
 586 #ifdef CHECK_DELAY
 587   enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
 588 #endif
 589 
 590  public:
 591   // Tells assembler next instruction must NOT be in delay slot.
 592   // Use at start of multinstruction macros.
 593   void assert_not_delayed() {
 594     // This is a separate overloading to avoid creation of string constants
 595     // in non-asserted code--with some compilers this pollutes the object code.
 596 #ifdef CHECK_DELAY
 597     assert_not_delayed("next instruction should not be a delay slot");
 598 #endif
 599   }
 600   void assert_not_delayed(const char* msg) {
 601 #ifdef CHECK_DELAY
 602     assert(delay_state == no_delay, msg);
 603 #endif
 604   }
 605 
 606  protected:
 607   // Delay slot helpers
 608   // cti is called when emitting control-transfer instruction,
 609   // BEFORE doing the emitting.
 610   // Only effective when assertion-checking is enabled.
 611   void cti() {
 612 #ifdef CHECK_DELAY
 613     assert_not_delayed("cti should not be in delay slot");
 614 #endif
 615   }
 616 
 617   // called when emitting cti with a delay slot, AFTER emitting
 618   void has_delay_slot() {
 619 #ifdef CHECK_DELAY
 620     assert_not_delayed("just checking");
 621     delay_state = at_delay_slot;
 622 #endif
 623   }
 624 
 625   // cbcond instruction should not be generated one after an other
 626   bool cbcond_before() {
 627     if (offset() == 0) return false; // it is first instruction
 628     int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
 629     return is_cbcond(x);
 630   }
 631 
 632   void no_cbcond_before() {
 633     assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
 634   }
 635 
 636 public:
 637 
 638   bool use_cbcond(Label& L) {
 639     if (!UseCBCond || cbcond_before()) return false;
 640     intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
 641     assert( (x & 3) == 0, "not word aligned");
 642     return is_simm12(x);
 643   }
 644 
 645   // Tells assembler you know that next instruction is delayed
 646   Assembler* delayed() {
 647 #ifdef CHECK_DELAY
 648     assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
 649     delay_state = filling_delay_slot;
 650 #endif
 651     return this;
 652   }
 653 
 654   void flush() {
 655 #ifdef CHECK_DELAY
 656     assert ( delay_state == no_delay, "ending code with a delay slot");
 657 #endif
 658     AbstractAssembler::flush();
 659   }
 660 
 661   inline void emit_int32(int);  // shadows AbstractAssembler::emit_int32
 662   inline void emit_data(int x) { emit_int32(x); }
 663   inline void emit_data(int, RelocationHolder const&);
 664   inline void emit_data(int, relocInfo::relocType rtype);
 665   // helper for above fcns
 666   inline void check_delay();
 667 
 668 
 669  public:
 670   // instructions, refer to page numbers in the SPARC Architecture Manual, V9
 671 
 672   // pp 135 (addc was addx in v8)
 673 
 674   inline void add(Register s1, Register s2, Register d );
 675   inline void add(Register s1, int simm13a, Register d );
 676 
 677   void addcc(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 678   void addcc(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 679   void addc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | rs2(s2) ); }
 680   void addc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 681   void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 682   void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 683 
 684 
 685   // pp 136
 686 
 687   inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
 688   inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
 689 
 690   // compare and branch
 691   inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
 692   inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
 693 
 694  protected: // use MacroAssembler::br instead
 695 
 696   // pp 138
 697 
 698   inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
 699   inline void fb( Condition c, bool a, Label& L );
 700 
 701   // pp 141
 702 
 703   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 704   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
 705 
 706   // pp 144
 707 
 708   inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
 709   inline void br( Condition c, bool a, Label& L );
 710 
 711   // pp 146
 712 
 713   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 714   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
 715 
 716   // pp 149
 717 
 718   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
 719   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
 720 
 721  public:
 722 
 723   // pp 150
 724 
 725   // These instructions compare the contents of s2 with the contents of
 726   // memory at address in s1. If the values are equal, the contents of memory
 727   // at address s1 is swapped with the data in d. If the values are not equal,
 728   // the the contents of memory at s1 is loaded into d, without the swap.
 729 
 730   void casa(  Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
 731   void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
 732 
 733   // pp 152
 734 
 735   void udiv(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | rs2(s2)); }
 736   void udiv(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 737   void sdiv(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | rs2(s2)); }
 738   void sdiv(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 739   void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
 740   void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 741   void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
 742   void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 743 
 744   // pp 155
 745 
 746   void done()  { v9_only();  cti();  emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
 747   void retry() { v9_only();  cti();  emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
 748 
 749   // pp 156
 750 
 751   void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
 752   void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
 753 
 754   // pp 157
 755 
 756   void fcmp(  FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
 757   void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
 758 
 759   // pp 159
 760 
 761   void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
 762   void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
 763 
 764   // pp 160
 765 
 766   void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
 767 
 768   // pp 161
 769 
 770   void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
 771   void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
 772 
 773   // pp 162
 774 
 775   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
 776 
 777   void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
 778 
 779   void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
 780 
 781   // pp 163
 782 
 783   void fmul( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x48 + w)         | fs2(s2, w)); }
 784   void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw,  FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
 785   void fdiv( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x4c + w)         | fs2(s2, w)); }
 786 
 787   // pp 164
 788 
 789   void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
 790 
 791   // pp 165
 792 
 793   inline void flush( Register s1, Register s2 );
 794   inline void flush( Register s1, int simm13a);
 795 
 796   // pp 167
 797 
 798   void flushw() { v9_only();  emit_int32( op(arith_op) | op3(flushw_op3) ); }
 799 
 800   // pp 168
 801 
 802   void illtrap( int const22a) { if (const22a != 0) v9_only();  emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
 803   // v8 unimp == illtrap(0)
 804 
 805   // pp 169
 806 
 807   void impdep1( int id1, int const19a ) { v9_only();  emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
 808   void impdep2( int id1, int const19a ) { v9_only();  emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
 809 
 810   // pp 170
 811 
 812   void jmpl( Register s1, Register s2, Register d );
 813   void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
 814 
 815   // 171
 816 
 817   inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
 818   inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
 819 
 820 
 821   inline void ldfsr(  Register s1, Register s2 );
 822   inline void ldfsr(  Register s1, int simm13a);
 823   inline void ldxfsr( Register s1, Register s2 );
 824   inline void ldxfsr( Register s1, int simm13a);
 825 
 826   // 173
 827 
 828   void ldfa(  FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only();  emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 829   void ldfa(  FloatRegisterImpl::Width w, Register s1, int simm13a,         FloatRegister d ) { v9_only();  emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 830 
 831   // pp 175, lduw is ld on v8
 832 
 833   inline void ldsb(  Register s1, Register s2, Register d );
 834   inline void ldsb(  Register s1, int simm13a, Register d);
 835   inline void ldsh(  Register s1, Register s2, Register d );
 836   inline void ldsh(  Register s1, int simm13a, Register d);
 837   inline void ldsw(  Register s1, Register s2, Register d );
 838   inline void ldsw(  Register s1, int simm13a, Register d);
 839   inline void ldub(  Register s1, Register s2, Register d );
 840   inline void ldub(  Register s1, int simm13a, Register d);
 841   inline void lduh(  Register s1, Register s2, Register d );
 842   inline void lduh(  Register s1, int simm13a, Register d);
 843   inline void lduw(  Register s1, Register s2, Register d );
 844   inline void lduw(  Register s1, int simm13a, Register d);
 845   inline void ldx(   Register s1, Register s2, Register d );
 846   inline void ldx(   Register s1, int simm13a, Register d);
 847   inline void ldd(   Register s1, Register s2, Register d );
 848   inline void ldd(   Register s1, int simm13a, Register d);
 849 
 850   // pp 177
 851 
 852   void ldsba(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 853   void ldsba(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 854   void ldsha(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 855   void ldsha(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 856   void ldswa(  Register s1, Register s2, int ia, Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 857   void ldswa(  Register s1, int simm13a,         Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 858   void lduba(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 859   void lduba(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 860   void lduha(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 861   void lduha(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 862   void lduwa(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 863   void lduwa(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 864   void ldxa(   Register s1, Register s2, int ia, Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 865   void ldxa(   Register s1, int simm13a,         Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 866 
 867   // pp 181
 868 
 869   void and3(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | rs2(s2) ); }
 870   void and3(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 871   void andcc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 872   void andcc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 873   void andn(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | rs2(s2) ); }
 874   void andn(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 875   void andncc(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 876   void andncc(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 877   void or3(     Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | rs2(s2) ); }
 878   void or3(     Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 879   void orcc(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 880   void orcc(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 881   void orn(     Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
 882   void orn(     Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 883   void orncc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 884   void orncc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 885   void xor3(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | rs2(s2) ); }
 886   void xor3(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 887   void xorcc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 888   void xorcc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 889   void xnor(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3             ) | rs1(s1) | rs2(s2) ); }
 890   void xnor(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 891   void xnorcc(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 892   void xnorcc(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 893 
 894   // pp 183
 895 
 896   void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
 897 
 898   // pp 185
 899 
 900   void fmov( FloatRegisterImpl::Width w, Condition c,  bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only();  emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
 901 
 902   // pp 189
 903 
 904   void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1,  FloatRegister s2, FloatRegister d ) { v9_only();  emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
 905 
 906   // pp 191
 907 
 908   void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
 909   void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
 910 
 911   // pp 195
 912 
 913   void movr( RCondition c, Register s1, Register s2,  Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
 914   void movr( RCondition c, Register s1, int simm10a,  Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
 915 
 916   // pp 196
 917 
 918   void mulx(  Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
 919   void mulx(  Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 920   void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
 921   void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 922   void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
 923   void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 924 
 925   // pp 197
 926 
 927   void umul(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | rs2(s2) ); }
 928   void umul(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 929   void smul(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | rs2(s2) ); }
 930   void smul(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 931   void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 932   void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 933   void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 934   void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 935 
 936   // pp 201
 937 
 938   void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
 939 
 940 
 941   // pp 202
 942 
 943   void popc( Register s,  Register d) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
 944   void popc( int simm13a, Register d) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
 945 
 946   // pp 203
 947 
 948   void prefetch(   Register s1, Register s2, PrefetchFcn f) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
 949   void prefetch(   Register s1, int simm13a, PrefetchFcn f) { v9_only();  emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 950 
 951   void prefetcha(  Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 952   void prefetcha(  Register s1, int simm13a,         PrefetchFcn f ) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 953 
 954   // pp 208
 955 
 956   // not implementing read privileged register
 957 
 958   inline void rdy(    Register d) { v9_dep();  emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
 959   inline void rdccr(  Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
 960   inline void rdasi(  Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
 961   inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
 962   inline void rdpc(   Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
 963   inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
 964 
 965   // pp 213
 966 
 967   inline void rett( Register s1, Register s2);
 968   inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
 969 
 970   // pp 214
 971 
 972   void save(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
 973   void save(    Register s1, int simm13a, Register d ) {
 974     // make sure frame is at least large enough for the register save area
 975     assert(-simm13a >= 16 * wordSize, "frame too small");
 976     emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
 977   }
 978 
 979   void restore( Register s1 = G0,  Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
 980   void restore( Register s1,       int simm13a,      Register d      ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 981 
 982   // pp 216
 983 
 984   void saved()    { v9_only();  emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
 985   void restored() { v9_only();  emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
 986 
 987   // pp 217
 988 
 989   inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
 990   // pp 218
 991 
 992   void sll(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
 993   void sll(  Register s1, int imm5a,   Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
 994   void srl(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
 995   void srl(  Register s1, int imm5a,   Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
 996   void sra(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
 997   void sra(  Register s1, int imm5a,   Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
 998 
 999   void sllx( Register s1, Register s2, Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1000   void sllx( Register s1, int imm6a,   Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1001   void srlx( Register s1, Register s2, Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1002   void srlx( Register s1, int imm6a,   Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1003   void srax( Register s1, Register s2, Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1004   void srax( Register s1, int imm6a,   Register d ) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1005 
1006   // pp 220
1007 
1008   void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1009 
1010   // pp 221
1011 
1012   void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1013 
1014   // pp 222
1015 
1016   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1017   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1018 
1019   inline void stfsr(  Register s1, Register s2 );
1020   inline void stfsr(  Register s1, int simm13a);
1021   inline void stxfsr( Register s1, Register s2 );
1022   inline void stxfsr( Register s1, int simm13a);
1023 
1024   //  pp 224
1025 
1026   void stfa(  FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only();  emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1027   void stfa(  FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a         ) { v9_only();  emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1028 
1029   // p 226
1030 
1031   inline void stb(  Register d, Register s1, Register s2 );
1032   inline void stb(  Register d, Register s1, int simm13a);
1033   inline void sth(  Register d, Register s1, Register s2 );
1034   inline void sth(  Register d, Register s1, int simm13a);
1035   inline void stw(  Register d, Register s1, Register s2 );
1036   inline void stw(  Register d, Register s1, int simm13a);
1037   inline void stx(  Register d, Register s1, Register s2 );
1038   inline void stx(  Register d, Register s1, int simm13a);
1039   inline void std(  Register d, Register s1, Register s2 );
1040   inline void std(  Register d, Register s1, int simm13a);
1041 
1042   // pp 177
1043 
1044   void stba(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1045   void stba(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1046   void stha(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1047   void stha(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1048   void stwa(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1049   void stwa(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1050   void stxa(  Register d, Register s1, Register s2, int ia ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1051   void stxa(  Register d, Register s1, int simm13a         ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1052   void stda(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1053   void stda(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1054 
1055   // pp 230
1056 
1057   void sub(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
1058   void sub(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1059 
1060   void subcc(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1061   void subcc(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1062   void subc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
1063   void subc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1064   void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1065   void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1066 
1067   // pp 231
1068 
1069   inline void swap( Register s1, Register s2, Register d );
1070   inline void swap( Register s1, int simm13a, Register d);
1071 
1072   // pp 232
1073 
1074   void swapa(   Register s1, Register s2, int ia, Register d ) { v9_dep();  emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1075   void swapa(   Register s1, int simm13a,         Register d ) { v9_dep();  emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1076 
1077   // pp 234, note op in book is wrong, see pp 268
1078 
1079   void taddcc(    Register s1, Register s2, Register d ) {            emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | rs2(s2) ); }
1080   void taddcc(    Register s1, int simm13a, Register d ) {            emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1081 
1082   // pp 235
1083 
1084   void tsubcc(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | rs2(s2) ); }
1085   void tsubcc(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1086 
1087   // pp 237
1088 
1089   void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1090   void trap( Condition c, CC cc, Register s1, int trapa   ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1091   // simple uncond. trap
1092   void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1093 
1094   // pp 239 omit write priv register for now
1095 
1096   inline void wry(    Register d) { v9_dep();  emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1097   inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1098   inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1099                                                                            rs1(s) |
1100                                                                            op3(wrreg_op3) |
1101                                                                            u_field(2, 29, 25) |
1102                                                                            immed(true) |
1103                                                                            simm(simm13a, 13)); }
1104   inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1105   // wrasi(d, imm) stores (d xor imm) to asi
1106   inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1107                                                u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1108   inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1109 
1110 
1111   // VIS3 instructions
1112 
1113   void movstosw( FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1114   void movstouw( FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1115   void movdtox(  FloatRegister s, Register d ) { vis3_only();  emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1116 
1117   void movwtos( Register s, FloatRegister d ) { vis3_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1118   void movxtod( Register s, FloatRegister d ) { vis3_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1119 
1120   // Creation
1121   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1122 #ifdef CHECK_DELAY
1123     delay_state = no_delay;
1124 #endif
1125   }
1126 };
1127 
1128 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP