src/cpu/sparc/vm/assembler_sparc.hpp

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  40   friend class NativeGeneralJump;
  41   friend class Relocation;
  42   friend class Label;
  43 
  44  public:
  45   // op carries format info; see page 62 & 267
  46 
  47   enum ops {
  48     call_op   = 1, // fmt 1
  49     branch_op = 0, // also sethi (fmt2)
  50     arith_op  = 2, // fmt 3, arith & misc
  51     ldst_op   = 3  // fmt 3, load/store
  52   };
  53 
  54   enum op2s {
  55     bpr_op2   = 3,
  56     fb_op2    = 6,
  57     fbp_op2   = 5,
  58     br_op2    = 2,
  59     bp_op2    = 1,
  60     cb_op2    = 7, // V8
  61     sethi_op2 = 4
  62   };
  63 
  64   enum op3s {
  65     // selected op3s
  66     add_op3      = 0x00,
  67     and_op3      = 0x01,
  68     or_op3       = 0x02,
  69     xor_op3      = 0x03,
  70     sub_op3      = 0x04,
  71     andn_op3     = 0x05,
  72     orn_op3      = 0x06,
  73     xnor_op3     = 0x07,
  74     addc_op3     = 0x08,
  75     mulx_op3     = 0x09,
  76     umul_op3     = 0x0a,
  77     smul_op3     = 0x0b,
  78     subc_op3     = 0x0c,
  79     udivx_op3    = 0x0d,
  80     udiv_op3     = 0x0e,


 128     trap_op3     = 0x3a,
 129     flush_op3    = 0x3b,
 130     save_op3     = 0x3c,
 131     restore_op3  = 0x3d,
 132     done_op3     = 0x3e,
 133     retry_op3    = 0x3e,
 134 
 135     lduw_op3     = 0x00,
 136     ldub_op3     = 0x01,
 137     lduh_op3     = 0x02,
 138     ldd_op3      = 0x03,
 139     stw_op3      = 0x04,
 140     stb_op3      = 0x05,
 141     sth_op3      = 0x06,
 142     std_op3      = 0x07,
 143     ldsw_op3     = 0x08,
 144     ldsb_op3     = 0x09,
 145     ldsh_op3     = 0x0a,
 146     ldx_op3      = 0x0b,
 147 
 148     ldstub_op3   = 0x0d,
 149     stx_op3      = 0x0e,
 150     swap_op3     = 0x0f,
 151 
 152     stwa_op3     = 0x14,
 153     stxa_op3     = 0x1e,
 154 
 155     ldf_op3      = 0x20,
 156     ldfsr_op3    = 0x21,
 157     ldqf_op3     = 0x22,
 158     lddf_op3     = 0x23,
 159     stf_op3      = 0x24,
 160     stfsr_op3    = 0x25,
 161     stqf_op3     = 0x26,
 162     stdf_op3     = 0x27,
 163 
 164     prefetch_op3 = 0x2d,
 165 
 166 
 167     ldc_op3      = 0x30,
 168     ldcsr_op3    = 0x31,
 169     lddc_op3     = 0x33,
 170     stc_op3      = 0x34,
 171     stcsr_op3    = 0x35,
 172     stdcq_op3    = 0x36,
 173     stdc_op3     = 0x37,
 174 
 175     casa_op3     = 0x3c,
 176     casxa_op3    = 0x3e,
 177 
 178     mftoi_op3    = 0x36,
 179 
 180     alt_bit_op3  = 0x10,
 181      cc_bit_op3  = 0x10
 182   };
 183 
 184   enum opfs {
 185     // selected opfs
 186     fmovs_opf   = 0x01,
 187     fmovd_opf   = 0x02,
 188 
 189     fnegs_opf   = 0x05,
 190     fnegd_opf   = 0x06,
 191 
 192     fadds_opf   = 0x41,
 193     faddd_opf   = 0x42,
 194     fsubs_opf   = 0x45,


 557   static int inv_hi22( int x ) {
 558     return x << 10;
 559   }
 560 
 561   // create an imm22 field, given a 32-bit left-justified constant
 562   static int hi22( int x ) {
 563     int r = int( juint(x) >> 10 );
 564     assert( (r & ~((1 << 22) - 1))  ==  0, "just checkin'");
 565     return r;
 566   }
 567 
 568   // create a low10 __value__ (not a field) for a given a 32-bit constant
 569   static int low10( int x ) {
 570     return x & ((1 << 10) - 1);
 571   }
 572 
 573   // instruction only in VIS3
 574   static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
 575 
 576   // instruction only in v9
 577   static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
 578 
 579   // instruction only in v8
 580   static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
 581 
 582   // instruction deprecated in v9
 583   static void v9_dep()  { } // do nothing for now
 584 
 585   // some float instructions only exist for single prec. on v8
 586   static void v8_s_only(FloatRegisterImpl::Width w)  { if (w != FloatRegisterImpl::S)  v9_only(); }
 587 
 588   // v8 has no CC field
 589   static void v8_no_cc(CC cc)  { if (cc)  v9_only(); }
 590 
 591  protected:
 592   // Simple delay-slot scheme:
 593   // In order to check the programmer, the assembler keeps track of deley slots.
 594   // It forbids CTIs in delay slots (conservative, but should be OK).
 595   // Also, when putting an instruction into a delay slot, you must say
 596   // asm->delayed()->add(...), in order to check that you don't omit
 597   // delay-slot instructions.
 598   // To implement this, we use a simple FSA
 599 
 600 #ifdef ASSERT
 601   #define CHECK_DELAY
 602 #endif
 603 #ifdef CHECK_DELAY
 604   enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
 605 #endif
 606 
 607  public:


 713   // pp 138
 714 
 715   inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
 716   inline void fb( Condition c, bool a, Label& L );
 717 
 718   // pp 141
 719 
 720   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 721   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
 722 
 723   // pp 144
 724 
 725   inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
 726   inline void br( Condition c, bool a, Label& L );
 727 
 728   // pp 146
 729 
 730   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 731   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
 732 
 733   // pp 121 (V8)
 734 
 735   inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
 736   inline void cb( Condition c, bool a, Label& L );
 737 
 738   // pp 149
 739 
 740   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
 741   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
 742 
 743  public:
 744 
 745   // pp 150
 746 
 747   // These instructions compare the contents of s2 with the contents of
 748   // memory at address in s1. If the values are equal, the contents of memory
 749   // at address s1 is swapped with the data in d. If the values are not equal,
 750   // the the contents of memory at s1 is loaded into d, without the swap.
 751 
 752   void casa(  Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
 753   void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
 754 
 755   // pp 152
 756 
 757   void udiv(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | rs2(s2)); }
 758   void udiv(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 759   void sdiv(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | rs2(s2)); }
 760   void sdiv(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 761   void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
 762   void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 763   void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
 764   void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 765 
 766   // pp 155
 767 
 768   void done()  { v9_only();  cti();  emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
 769   void retry() { v9_only();  cti();  emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
 770 
 771   // pp 156
 772 
 773   void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
 774   void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
 775 
 776   // pp 157
 777 
 778   void fcmp(  FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
 779   void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
 780 
 781   // pp 159
 782 
 783   void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
 784   void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
 785 
 786   // pp 160
 787 
 788   void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
 789 
 790   // pp 161
 791 
 792   void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
 793   void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
 794 
 795   // pp 162
 796 
 797   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
 798 
 799   void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
 800 
 801   // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
 802   // on v8 to do negation of single, double and quad precision floats.
 803 
 804   void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) |  opf(0x05) | fs2(sd, w)); }
 805 
 806   void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
 807 
 808   // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
 809   // on v8 to do abs operation on single/double/quad precision floats.
 810 
 811   void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
 812 
 813   // pp 163
 814 
 815   void fmul( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x48 + w)         | fs2(s2, w)); }
 816   void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw,  FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
 817   void fdiv( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x4c + w)         | fs2(s2, w)); }
 818 
 819   // pp 164
 820 
 821   void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
 822 
 823   // pp 165
 824 
 825   inline void flush( Register s1, Register s2 );
 826   inline void flush( Register s1, int simm13a);
 827 
 828   // pp 167
 829 
 830   void flushw() { v9_only();  emit_int32( op(arith_op) | op3(flushw_op3) ); }
 831 
 832   // pp 168
 833 
 834   void illtrap( int const22a) { if (const22a != 0) v9_only();  emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
 835   // v8 unimp == illtrap(0)
 836 
 837   // pp 169
 838 
 839   void impdep1( int id1, int const19a ) { v9_only();  emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
 840   void impdep2( int id1, int const19a ) { v9_only();  emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
 841 
 842   // pp 149 (v8)
 843 
 844   void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only();  emit_int32( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
 845   void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only();  emit_int32( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
 846 
 847   // pp 170
 848 
 849   void jmpl( Register s1, Register s2, Register d );
 850   void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
 851 
 852   // 171
 853 
 854   inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
 855   inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
 856 
 857 
 858   inline void ldfsr(  Register s1, Register s2 );
 859   inline void ldfsr(  Register s1, int simm13a);
 860   inline void ldxfsr( Register s1, Register s2 );
 861   inline void ldxfsr( Register s1, int simm13a);
 862 
 863   // pp 94 (v8)
 864 
 865   inline void ldc(   Register s1, Register s2, int crd );
 866   inline void ldc(   Register s1, int simm13a, int crd);
 867   inline void lddc(  Register s1, Register s2, int crd );
 868   inline void lddc(  Register s1, int simm13a, int crd);
 869   inline void ldcsr( Register s1, Register s2, int crd );
 870   inline void ldcsr( Register s1, int simm13a, int crd);
 871 
 872 
 873   // 173
 874 
 875   void ldfa(  FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only();  emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 876   void ldfa(  FloatRegisterImpl::Width w, Register s1, int simm13a,         FloatRegister d ) { v9_only();  emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 877 
 878   // pp 175, lduw is ld on v8
 879 
 880   inline void ldsb(  Register s1, Register s2, Register d );
 881   inline void ldsb(  Register s1, int simm13a, Register d);
 882   inline void ldsh(  Register s1, Register s2, Register d );
 883   inline void ldsh(  Register s1, int simm13a, Register d);
 884   inline void ldsw(  Register s1, Register s2, Register d );
 885   inline void ldsw(  Register s1, int simm13a, Register d);
 886   inline void ldub(  Register s1, Register s2, Register d );
 887   inline void ldub(  Register s1, int simm13a, Register d);
 888   inline void lduh(  Register s1, Register s2, Register d );
 889   inline void lduh(  Register s1, int simm13a, Register d);
 890   inline void lduw(  Register s1, Register s2, Register d );
 891   inline void lduw(  Register s1, int simm13a, Register d);
 892   inline void ldx(   Register s1, Register s2, Register d );
 893   inline void ldx(   Register s1, int simm13a, Register d);
 894   inline void ldd(   Register s1, Register s2, Register d );
 895   inline void ldd(   Register s1, int simm13a, Register d);
 896 
 897   // pp 177
 898 
 899   void ldsba(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 900   void ldsba(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 901   void ldsha(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 902   void ldsha(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 903   void ldswa(  Register s1, Register s2, int ia, Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 904   void ldswa(  Register s1, int simm13a,         Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 905   void lduba(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 906   void lduba(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 907   void lduha(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 908   void lduha(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 909   void lduwa(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 910   void lduwa(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 911   void ldxa(   Register s1, Register s2, int ia, Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 912   void ldxa(   Register s1, int simm13a,         Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 913   void ldda(   Register s1, Register s2, int ia, Register d ) { v9_dep();   emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 914   void ldda(   Register s1, int simm13a,         Register d ) { v9_dep();   emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 915 
 916   // pp 179
 917 
 918   inline void ldstub(  Register s1, Register s2, Register d );
 919   inline void ldstub(  Register s1, int simm13a, Register d);
 920 
 921   // pp 180
 922 
 923   void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 924   void ldstuba( Register s1, int simm13a,         Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 925 
 926   // pp 181
 927 
 928   void and3(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | rs2(s2) ); }
 929   void and3(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 930   void andcc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 931   void andcc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 932   void andn(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | rs2(s2) ); }
 933   void andn(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 934   void andncc(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 935   void andncc(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 936   void or3(     Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | rs2(s2) ); }
 937   void or3(     Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 938   void orcc(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 939   void orcc(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 940   void orn(     Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
 941   void orn(     Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 942   void orncc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 943   void orncc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 944   void xor3(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | rs2(s2) ); }


 975   // pp 196
 976 
 977   void mulx(  Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
 978   void mulx(  Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 979   void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
 980   void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 981   void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
 982   void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 983 
 984   // pp 197
 985 
 986   void umul(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | rs2(s2) ); }
 987   void umul(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 988   void smul(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | rs2(s2) ); }
 989   void smul(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 990   void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 991   void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 992   void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 993   void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 994 
 995   // pp 199
 996 
 997   void mulscc(   Register s1, Register s2, Register d ) { v9_dep();  emit_int32( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
 998   void mulscc(   Register s1, int simm13a, Register d ) { v9_dep();  emit_int32( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 999 
1000   // pp 201
1001 
1002   void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
1003 
1004 
1005   // pp 202
1006 
1007   void popc( Register s,  Register d) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1008   void popc( int simm13a, Register d) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1009 
1010   // pp 203
1011 
1012   void prefetch(   Register s1, Register s2, PrefetchFcn f) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
1013   void prefetch(   Register s1, int simm13a, PrefetchFcn f) { v9_only();  emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
1014 
1015   void prefetcha(  Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1016   void prefetcha(  Register s1, int simm13a,         PrefetchFcn f ) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1017 
1018   // pp 208
1019 


1099   inline void stw(  Register d, Register s1, Register s2 );
1100   inline void stw(  Register d, Register s1, int simm13a);
1101   inline void stx(  Register d, Register s1, Register s2 );
1102   inline void stx(  Register d, Register s1, int simm13a);
1103   inline void std(  Register d, Register s1, Register s2 );
1104   inline void std(  Register d, Register s1, int simm13a);
1105 
1106   // pp 177
1107 
1108   void stba(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1109   void stba(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1110   void stha(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1111   void stha(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1112   void stwa(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1113   void stwa(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1114   void stxa(  Register d, Register s1, Register s2, int ia ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1115   void stxa(  Register d, Register s1, int simm13a         ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1116   void stda(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1117   void stda(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1118 
1119   // pp 97 (v8)
1120 
1121   inline void stc(   int crd, Register s1, Register s2 );
1122   inline void stc(   int crd, Register s1, int simm13a);
1123   inline void stdc(  int crd, Register s1, Register s2 );
1124   inline void stdc(  int crd, Register s1, int simm13a);
1125   inline void stcsr( int crd, Register s1, Register s2 );
1126   inline void stcsr( int crd, Register s1, int simm13a);
1127   inline void stdcq( int crd, Register s1, Register s2 );
1128   inline void stdcq( int crd, Register s1, int simm13a);
1129 
1130   // pp 230
1131 
1132   void sub(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
1133   void sub(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1134 
1135   void subcc(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1136   void subcc(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1137   void subc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
1138   void subc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1139   void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1140   void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1141 
1142   // pp 231
1143 
1144   inline void swap( Register s1, Register s2, Register d );
1145   inline void swap( Register s1, int simm13a, Register d);
1146 
1147   // pp 232
1148 
1149   void swapa(   Register s1, Register s2, int ia, Register d ) { v9_dep();  emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1150   void swapa(   Register s1, int simm13a,         Register d ) { v9_dep();  emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1151 
1152   // pp 234, note op in book is wrong, see pp 268
1153 
1154   void taddcc(    Register s1, Register s2, Register d ) {            emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | rs2(s2) ); }
1155   void taddcc(    Register s1, int simm13a, Register d ) {            emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1156   void taddcctv(  Register s1, Register s2, Register d ) { v9_dep();  emit_int32( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
1157   void taddcctv(  Register s1, int simm13a, Register d ) { v9_dep();  emit_int32( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1158 
1159   // pp 235
1160 
1161   void tsubcc(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | rs2(s2) ); }
1162   void tsubcc(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1163   void tsubcctv(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
1164   void tsubcctv(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1165 
1166   // pp 237
1167 
1168   void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc);  emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1169   void trap( Condition c, CC cc, Register s1, int trapa   ) { v8_no_cc(cc);  emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1170   // simple uncond. trap
1171   void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1172 
1173   // pp 239 omit write priv register for now
1174 
1175   inline void wry(    Register d) { v9_dep();  emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1176   inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1177   inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1178                                                                            rs1(s) |
1179                                                                            op3(wrreg_op3) |
1180                                                                            u_field(2, 29, 25) |
1181                                                                            immed(true) |
1182                                                                            simm(simm13a, 13)); }
1183   inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1184   // wrasi(d, imm) stores (d xor imm) to asi
1185   inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1186                                                u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1187   inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1188 
1189 


  40   friend class NativeGeneralJump;
  41   friend class Relocation;
  42   friend class Label;
  43 
  44  public:
  45   // op carries format info; see page 62 & 267
  46 
  47   enum ops {
  48     call_op   = 1, // fmt 1
  49     branch_op = 0, // also sethi (fmt2)
  50     arith_op  = 2, // fmt 3, arith & misc
  51     ldst_op   = 3  // fmt 3, load/store
  52   };
  53 
  54   enum op2s {
  55     bpr_op2   = 3,
  56     fb_op2    = 6,
  57     fbp_op2   = 5,
  58     br_op2    = 2,
  59     bp_op2    = 1,

  60     sethi_op2 = 4
  61   };
  62 
  63   enum op3s {
  64     // selected op3s
  65     add_op3      = 0x00,
  66     and_op3      = 0x01,
  67     or_op3       = 0x02,
  68     xor_op3      = 0x03,
  69     sub_op3      = 0x04,
  70     andn_op3     = 0x05,
  71     orn_op3      = 0x06,
  72     xnor_op3     = 0x07,
  73     addc_op3     = 0x08,
  74     mulx_op3     = 0x09,
  75     umul_op3     = 0x0a,
  76     smul_op3     = 0x0b,
  77     subc_op3     = 0x0c,
  78     udivx_op3    = 0x0d,
  79     udiv_op3     = 0x0e,


 127     trap_op3     = 0x3a,
 128     flush_op3    = 0x3b,
 129     save_op3     = 0x3c,
 130     restore_op3  = 0x3d,
 131     done_op3     = 0x3e,
 132     retry_op3    = 0x3e,
 133 
 134     lduw_op3     = 0x00,
 135     ldub_op3     = 0x01,
 136     lduh_op3     = 0x02,
 137     ldd_op3      = 0x03,
 138     stw_op3      = 0x04,
 139     stb_op3      = 0x05,
 140     sth_op3      = 0x06,
 141     std_op3      = 0x07,
 142     ldsw_op3     = 0x08,
 143     ldsb_op3     = 0x09,
 144     ldsh_op3     = 0x0a,
 145     ldx_op3      = 0x0b,
 146 

 147     stx_op3      = 0x0e,
 148     swap_op3     = 0x0f,
 149 
 150     stwa_op3     = 0x14,
 151     stxa_op3     = 0x1e,
 152 
 153     ldf_op3      = 0x20,
 154     ldfsr_op3    = 0x21,
 155     ldqf_op3     = 0x22,
 156     lddf_op3     = 0x23,
 157     stf_op3      = 0x24,
 158     stfsr_op3    = 0x25,
 159     stqf_op3     = 0x26,
 160     stdf_op3     = 0x27,
 161 
 162     prefetch_op3 = 0x2d,
 163 









 164     casa_op3     = 0x3c,
 165     casxa_op3    = 0x3e,
 166 
 167     mftoi_op3    = 0x36,
 168 
 169     alt_bit_op3  = 0x10,
 170      cc_bit_op3  = 0x10
 171   };
 172 
 173   enum opfs {
 174     // selected opfs
 175     fmovs_opf   = 0x01,
 176     fmovd_opf   = 0x02,
 177 
 178     fnegs_opf   = 0x05,
 179     fnegd_opf   = 0x06,
 180 
 181     fadds_opf   = 0x41,
 182     faddd_opf   = 0x42,
 183     fsubs_opf   = 0x45,


 546   static int inv_hi22( int x ) {
 547     return x << 10;
 548   }
 549 
 550   // create an imm22 field, given a 32-bit left-justified constant
 551   static int hi22( int x ) {
 552     int r = int( juint(x) >> 10 );
 553     assert( (r & ~((1 << 22) - 1))  ==  0, "just checkin'");
 554     return r;
 555   }
 556 
 557   // create a low10 __value__ (not a field) for a given a 32-bit constant
 558   static int low10( int x ) {
 559     return x & ((1 << 10) - 1);
 560   }
 561 
 562   // instruction only in VIS3
 563   static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
 564 
 565   // instruction only in v9
 566   static void v9_only() { } // do nothing



 567 
 568   // instruction deprecated in v9
 569   static void v9_dep()  { } // do nothing for now
 570 



 571   // v8 has no CC field
 572   static void v8_no_cc(CC cc)  { if (cc)  v9_only(); }
 573 
 574  protected:
 575   // Simple delay-slot scheme:
 576   // In order to check the programmer, the assembler keeps track of deley slots.
 577   // It forbids CTIs in delay slots (conservative, but should be OK).
 578   // Also, when putting an instruction into a delay slot, you must say
 579   // asm->delayed()->add(...), in order to check that you don't omit
 580   // delay-slot instructions.
 581   // To implement this, we use a simple FSA
 582 
 583 #ifdef ASSERT
 584   #define CHECK_DELAY
 585 #endif
 586 #ifdef CHECK_DELAY
 587   enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
 588 #endif
 589 
 590  public:


 696   // pp 138
 697 
 698   inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
 699   inline void fb( Condition c, bool a, Label& L );
 700 
 701   // pp 141
 702 
 703   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 704   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
 705 
 706   // pp 144
 707 
 708   inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
 709   inline void br( Condition c, bool a, Label& L );
 710 
 711   // pp 146
 712 
 713   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
 714   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
 715 





 716   // pp 149
 717 
 718   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
 719   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
 720 
 721  public:
 722 
 723   // pp 150
 724 
 725   // These instructions compare the contents of s2 with the contents of
 726   // memory at address in s1. If the values are equal, the contents of memory
 727   // at address s1 is swapped with the data in d. If the values are not equal,
 728   // the the contents of memory at s1 is loaded into d, without the swap.
 729 
 730   void casa(  Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
 731   void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
 732 
 733   // pp 152
 734 
 735   void udiv(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | rs2(s2)); }
 736   void udiv(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 737   void sdiv(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | rs2(s2)); }
 738   void sdiv(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 739   void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
 740   void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 741   void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
 742   void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 743 
 744   // pp 155
 745 
 746   void done()  { v9_only();  cti();  emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
 747   void retry() { v9_only();  cti();  emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
 748 
 749   // pp 156
 750 
 751   void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
 752   void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
 753 
 754   // pp 157
 755 
 756   void fcmp(  FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
 757   void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
 758 
 759   // pp 159
 760 
 761   void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
 762   void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
 763 
 764   // pp 160
 765 
 766   void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
 767 
 768   // pp 161
 769 
 770   void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
 771   void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
 772 
 773   // pp 162
 774 
 775   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
 776 
 777   void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
 778 
 779   void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }










 780 
 781   // pp 163
 782 
 783   void fmul( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x48 + w)         | fs2(s2, w)); }
 784   void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw,  FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
 785   void fdiv( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x4c + w)         | fs2(s2, w)); }
 786 
 787   // pp 164
 788 
 789   void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
 790 
 791   // pp 165
 792 
 793   inline void flush( Register s1, Register s2 );
 794   inline void flush( Register s1, int simm13a);
 795 
 796   // pp 167
 797 
 798   void flushw() { v9_only();  emit_int32( op(arith_op) | op3(flushw_op3) ); }
 799 
 800   // pp 168
 801 
 802   void illtrap( int const22a) { if (const22a != 0) v9_only();  emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
 803   // v8 unimp == illtrap(0)
 804 
 805   // pp 169
 806 
 807   void impdep1( int id1, int const19a ) { v9_only();  emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
 808   void impdep2( int id1, int const19a ) { v9_only();  emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
 809 





 810   // pp 170
 811 
 812   void jmpl( Register s1, Register s2, Register d );
 813   void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
 814 
 815   // 171
 816 
 817   inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
 818   inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
 819 
 820 
 821   inline void ldfsr(  Register s1, Register s2 );
 822   inline void ldfsr(  Register s1, int simm13a);
 823   inline void ldxfsr( Register s1, Register s2 );
 824   inline void ldxfsr( Register s1, int simm13a);
 825 










 826   // 173
 827 
 828   void ldfa(  FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only();  emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 829   void ldfa(  FloatRegisterImpl::Width w, Register s1, int simm13a,         FloatRegister d ) { v9_only();  emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 830 
 831   // pp 175, lduw is ld on v8
 832 
 833   inline void ldsb(  Register s1, Register s2, Register d );
 834   inline void ldsb(  Register s1, int simm13a, Register d);
 835   inline void ldsh(  Register s1, Register s2, Register d );
 836   inline void ldsh(  Register s1, int simm13a, Register d);
 837   inline void ldsw(  Register s1, Register s2, Register d );
 838   inline void ldsw(  Register s1, int simm13a, Register d);
 839   inline void ldub(  Register s1, Register s2, Register d );
 840   inline void ldub(  Register s1, int simm13a, Register d);
 841   inline void lduh(  Register s1, Register s2, Register d );
 842   inline void lduh(  Register s1, int simm13a, Register d);
 843   inline void lduw(  Register s1, Register s2, Register d );
 844   inline void lduw(  Register s1, int simm13a, Register d);
 845   inline void ldx(   Register s1, Register s2, Register d );
 846   inline void ldx(   Register s1, int simm13a, Register d);
 847   inline void ldd(   Register s1, Register s2, Register d );
 848   inline void ldd(   Register s1, int simm13a, Register d);
 849 
 850   // pp 177
 851 
 852   void ldsba(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 853   void ldsba(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 854   void ldsha(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 855   void ldsha(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 856   void ldswa(  Register s1, Register s2, int ia, Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 857   void ldswa(  Register s1, int simm13a,         Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 858   void lduba(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 859   void lduba(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 860   void lduha(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 861   void lduha(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 862   void lduwa(  Register s1, Register s2, int ia, Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 863   void lduwa(  Register s1, int simm13a,         Register d ) {             emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 864   void ldxa(   Register s1, Register s2, int ia, Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 865   void ldxa(   Register s1, int simm13a,         Register d ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }












 866 
 867   // pp 181
 868 
 869   void and3(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | rs2(s2) ); }
 870   void and3(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 871   void andcc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 872   void andcc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 873   void andn(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | rs2(s2) ); }
 874   void andn(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 875   void andncc(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 876   void andncc(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 877   void or3(     Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | rs2(s2) ); }
 878   void or3(     Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 879   void orcc(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 880   void orcc(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 881   void orn(     Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
 882   void orn(     Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 883   void orncc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 884   void orncc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 885   void xor3(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | rs2(s2) ); }


 916   // pp 196
 917 
 918   void mulx(  Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
 919   void mulx(  Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 920   void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
 921   void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 922   void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
 923   void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 924 
 925   // pp 197
 926 
 927   void umul(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | rs2(s2) ); }
 928   void umul(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 929   void smul(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | rs2(s2) ); }
 930   void smul(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 931   void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 932   void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 933   void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
 934   void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 935 





 936   // pp 201
 937 
 938   void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
 939 
 940 
 941   // pp 202
 942 
 943   void popc( Register s,  Register d) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
 944   void popc( int simm13a, Register d) { v9_only();  emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
 945 
 946   // pp 203
 947 
 948   void prefetch(   Register s1, Register s2, PrefetchFcn f) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
 949   void prefetch(   Register s1, int simm13a, PrefetchFcn f) { v9_only();  emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
 950 
 951   void prefetcha(  Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
 952   void prefetcha(  Register s1, int simm13a,         PrefetchFcn f ) { v9_only();  emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
 953 
 954   // pp 208
 955 


1035   inline void stw(  Register d, Register s1, Register s2 );
1036   inline void stw(  Register d, Register s1, int simm13a);
1037   inline void stx(  Register d, Register s1, Register s2 );
1038   inline void stx(  Register d, Register s1, int simm13a);
1039   inline void std(  Register d, Register s1, Register s2 );
1040   inline void std(  Register d, Register s1, int simm13a);
1041 
1042   // pp 177
1043 
1044   void stba(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1045   void stba(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1046   void stha(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1047   void stha(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1048   void stwa(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1049   void stwa(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1050   void stxa(  Register d, Register s1, Register s2, int ia ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1051   void stxa(  Register d, Register s1, int simm13a         ) { v9_only();  emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1052   void stda(  Register d, Register s1, Register s2, int ia ) {             emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1053   void stda(  Register d, Register s1, int simm13a         ) {             emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1054 











1055   // pp 230
1056 
1057   void sub(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
1058   void sub(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1059 
1060   void subcc(  Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1061   void subcc(  Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1062   void subc(   Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
1063   void subc(   Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1064   void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1065   void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1066 
1067   // pp 231
1068 
1069   inline void swap( Register s1, Register s2, Register d );
1070   inline void swap( Register s1, int simm13a, Register d);
1071 
1072   // pp 232
1073 
1074   void swapa(   Register s1, Register s2, int ia, Register d ) { v9_dep();  emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1075   void swapa(   Register s1, int simm13a,         Register d ) { v9_dep();  emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1076 
1077   // pp 234, note op in book is wrong, see pp 268
1078 
1079   void taddcc(    Register s1, Register s2, Register d ) {            emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | rs2(s2) ); }
1080   void taddcc(    Register s1, int simm13a, Register d ) {            emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }


1081 
1082   // pp 235
1083 
1084   void tsubcc(    Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | rs2(s2) ); }
1085   void tsubcc(    Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }


1086 
1087   // pp 237
1088 
1089   void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1090   void trap( Condition c, CC cc, Register s1, int trapa   ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1091   // simple uncond. trap
1092   void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1093 
1094   // pp 239 omit write priv register for now
1095 
1096   inline void wry(    Register d) { v9_dep();  emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1097   inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1098   inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1099                                                                            rs1(s) |
1100                                                                            op3(wrreg_op3) |
1101                                                                            u_field(2, 29, 25) |
1102                                                                            immed(true) |
1103                                                                            simm(simm13a, 13)); }
1104   inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1105   // wrasi(d, imm) stores (d xor imm) to asi
1106   inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1107                                                u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1108   inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1109 
1110