src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

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*** 595,611 **** } } __ sra(Rdividend, 31, Rscratch); __ wry(Rscratch); - if (!VM_Version::v9_instructions_work()) { - // v9 doesn't require these nops - __ nop(); - __ nop(); - __ nop(); - __ nop(); - } add_debug_info_for_div0_here(op->info()); if (Rdivisor != noreg) { __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); --- 595,604 ----
*** 650,663 **** case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; default : ShouldNotReachHere(); - }; - - if (!VM_Version::v9_instructions_work()) { - __ nop(); } __ fb( acond, false, Assembler::pn, *(op->label())); } else { assert (op->code() == lir_branch, "just checking"); --- 643,652 ----
*** 723,735 **** FloatRegister rsrc = op->in_opr()->as_float_reg(); Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); Label L; // result must be 0 if value is NaN; test by comparing value to itself __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); - if (!VM_Version::v9_instructions_work()) { - __ nop(); - } __ fb(Assembler::f_unordered, true, Assembler::pn, L); __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); // move integer result from float register to int register __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); --- 712,721 ----
*** 3232,3242 **** int null_check_offset = -1; Register base = mem_addr->base()->as_register(); if (src->is_register() && dest->is_address()) { // G4 is high half, G5 is low half - if (VM_Version::v9_instructions_work()) { // clear the top bits of G5, and scale up G4 __ srl (src->as_register_lo(), 0, G5); __ sllx(src->as_register_hi(), 32, G4); // combine the two halves into the 64 bits of G4 __ or3(G4, G5, G4); --- 3218,3227 ----
*** 3244,3284 **** if (idx == noreg) { __ stx(G4, base, disp); } else { __ stx(G4, base, idx); } - } else { - __ mov (src->as_register_hi(), G4); - __ mov (src->as_register_lo(), G5); - null_check_offset = __ offset(); - if (idx == noreg) { - __ std(G4, base, disp); - } else { - __ std(G4, base, idx); - } - } } else if (src->is_address() && dest->is_register()) { null_check_offset = __ offset(); - if (VM_Version::v9_instructions_work()) { if (idx == noreg) { __ ldx(base, disp, G5); } else { __ ldx(base, idx, G5); } __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi __ mov (G5, dest->as_register_lo()); // copy low half into lo } else { - if (idx == noreg) { - __ ldd(base, disp, G4); - } else { - __ ldd(base, idx, G4); - } - // G4 is high half, G5 is low half - __ mov (G4, dest->as_register_hi()); - __ mov (G5, dest->as_register_lo()); - } - } else { Unimplemented(); } if (info != NULL) { add_debug_info_for_null_check(null_check_offset, info); } --- 3229,3248 ----