1039 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
1040 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1041 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1042 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1043
1044 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
1045 if (is_simm13(src.constant_or_zero()))
1046 return src; // register or short constant
1047 guarantee(temp != noreg, "constant offset overflow");
1048 set(src.as_constant(), temp);
1049 return temp;
1050 }
1051
1052 // --------------------------------------------------
1053
1054 public:
1055 // traps as per trap.h (SPARC ABI?)
1056
1057 void breakpoint_trap();
1058 void breakpoint_trap(Condition c, CC cc);
1059 void flush_windows_trap();
1060 void clean_windows_trap();
1061 void get_psr_trap();
1062 void set_psr_trap();
1063
1064 // V8/V9 flush_windows
1065 void flush_windows();
1066
1067 // Support for serializing memory accesses between threads
1068 void serialize_memory(Register thread, Register tmp1, Register tmp2);
1069
1070 // Stack frame creation/removal
1071 void enter();
1072 void leave();
1073
1074 // V8/V9 integer multiply
1075 void mult(Register s1, Register s2, Register d);
1076 void mult(Register s1, int simm13a, Register d);
1077
1078 // V8/V9 read and write of condition codes.
1079 void read_ccr(Register d);
1080 void write_ccr(Register s);
1081
1082 // Manipulation of C++ bools
1083 // These are idioms to flag the need for care with accessing bools but on
1084 // this platform we assume byte size
1085
1086 inline void stbool(Register d, const Address& a) { stb(d, a); }
1087 inline void ldbool(const Address& a, Register d) { ldub(a, d); }
1088 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
1089
1090 // klass oop manipulations if compressed
1091 void load_klass(Register src_oop, Register klass);
1092 void store_klass(Register klass, Register dst_oop);
1093 void store_klass_gap(Register s, Register dst_oop);
1094
1095 // oop manipulations
1096 void load_heap_oop(const Address& s, Register d);
1097 void load_heap_oop(Register s1, Register s2, Register d);
1098 void load_heap_oop(Register s1, int simm13a, Register d);
1099 void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
1100 void store_heap_oop(Register d, Register s1, Register s2);
1101 void store_heap_oop(Register d, Register s1, int simm13a);
1145 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1146
1147 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
1148 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
1149 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
1150 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
1151
1152 void get_vm_result (Register oop_result);
1153 void get_vm_result_2(Register metadata_result);
1154
1155 // vm result is currently getting hijacked to for oop preservation
1156 void set_vm_result(Register oop_result);
1157
1158 // Emit the CompiledIC call idiom
1159 void ic_call(address entry, bool emit_delay = true);
1160
1161 // if call_VM_base was called with check_exceptions=false, then call
1162 // check_and_forward_exception to handle exceptions when it is safe
1163 void check_and_forward_exception(Register scratch_reg);
1164
1165 private:
1166 // For V8
1167 void read_ccr_trap(Register ccr_save);
1168 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
1169
1170 #ifdef ASSERT
1171 // For V8 debugging. Uses V8 instruction sequence and checks
1172 // result with V9 insturctions rdccr and wrccr.
1173 // Uses Gscatch and Gscatch2
1174 void read_ccr_v8_assert(Register ccr_save);
1175 void write_ccr_v8_assert(Register ccr_save);
1176 #endif // ASSERT
1177
1178 public:
1179
1180 // Write to card table for - register is destroyed afterwards.
1181 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
1182
1183 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
1184
1185 #if INCLUDE_ALL_GCS
1186 // General G1 pre-barrier generator.
1187 void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
1188
1189 // General G1 post-barrier generator
1190 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
1191 #endif // INCLUDE_ALL_GCS
1192
1193 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1194 void push_fTOS();
1195
1196 // pops double TOS element from CPU stack and pushes on FPU stack
1197 void pop_fTOS();
1198
1199 void empty_FPU_stack();
1297 Register Rout_high, Register Rout_low, Register Rtemp );
1298
1299 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
1300 Register Rout_high, Register Rout_low, Register Rtemp );
1301
1302 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
1303 Register Rout_high, Register Rout_low, Register Rtemp );
1304
1305 #ifdef _LP64
1306 void lcmp( Register Ra, Register Rb, Register Rresult);
1307 #endif
1308
1309 // Load and store values by size and signed-ness
1310 void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
1311 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1312
1313 void float_cmp( bool is_float, int unordered_result,
1314 FloatRegister Fa, FloatRegister Fb,
1315 Register Rresult);
1316
1317 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
1318 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
1319 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
1320 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
1321
1322 void save_all_globals_into_locals();
1323 void restore_globals_from_locals();
1324
1325 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
1326 address lock_addr=0, bool use_call_vm=false);
1327 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
1328 address lock_addr=0, bool use_call_vm=false);
1329 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
1330
1331 // These set the icc condition code to equal if the lock succeeded
1332 // and notEqual if it failed and requires a slow case
1333 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
1334 Register Rscratch,
1335 BiasedLockingCounters* counters = NULL,
1336 bool try_bias = UseBiasedLocking);
1337 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
1338 Register Rscratch,
1339 bool try_bias = UseBiasedLocking);
1340
1341 // Biased locking support
1342 // Upon entry, lock_reg must point to the lock record on the stack,
1343 // obj_reg must contain the target object, and mark_reg must contain
1344 // the target object's header.
1345 // Destroys mark_reg if an attempt is made to bias an anonymously
1346 // biased lock. In this case a failure will go either to the slow
1347 // case or fall through with the notEqual condition code set with
1348 // the expectation that the slow case in the runtime will be called.
1349 // In the fall-through case where the CAS-based lock is done,
1350 // mark_reg is not destroyed.
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1039 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
1040 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1041 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1042 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1043
1044 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
1045 if (is_simm13(src.constant_or_zero()))
1046 return src; // register or short constant
1047 guarantee(temp != noreg, "constant offset overflow");
1048 set(src.as_constant(), temp);
1049 return temp;
1050 }
1051
1052 // --------------------------------------------------
1053
1054 public:
1055 // traps as per trap.h (SPARC ABI?)
1056
1057 void breakpoint_trap();
1058 void breakpoint_trap(Condition c, CC cc);
1059
1060 // Support for serializing memory accesses between threads
1061 void serialize_memory(Register thread, Register tmp1, Register tmp2);
1062
1063 // Stack frame creation/removal
1064 void enter();
1065 void leave();
1066
1067 // V8/V9 integer multiply
1068 void mult(Register s1, Register s2, Register d);
1069 void mult(Register s1, int simm13a, Register d);
1070
1071 // Manipulation of C++ bools
1072 // These are idioms to flag the need for care with accessing bools but on
1073 // this platform we assume byte size
1074
1075 inline void stbool(Register d, const Address& a) { stb(d, a); }
1076 inline void ldbool(const Address& a, Register d) { ldub(a, d); }
1077 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
1078
1079 // klass oop manipulations if compressed
1080 void load_klass(Register src_oop, Register klass);
1081 void store_klass(Register klass, Register dst_oop);
1082 void store_klass_gap(Register s, Register dst_oop);
1083
1084 // oop manipulations
1085 void load_heap_oop(const Address& s, Register d);
1086 void load_heap_oop(Register s1, Register s2, Register d);
1087 void load_heap_oop(Register s1, int simm13a, Register d);
1088 void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
1089 void store_heap_oop(Register d, Register s1, Register s2);
1090 void store_heap_oop(Register d, Register s1, int simm13a);
1134 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1135
1136 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
1137 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
1138 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
1139 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
1140
1141 void get_vm_result (Register oop_result);
1142 void get_vm_result_2(Register metadata_result);
1143
1144 // vm result is currently getting hijacked to for oop preservation
1145 void set_vm_result(Register oop_result);
1146
1147 // Emit the CompiledIC call idiom
1148 void ic_call(address entry, bool emit_delay = true);
1149
1150 // if call_VM_base was called with check_exceptions=false, then call
1151 // check_and_forward_exception to handle exceptions when it is safe
1152 void check_and_forward_exception(Register scratch_reg);
1153
1154 // Write to card table for - register is destroyed afterwards.
1155 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
1156
1157 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
1158
1159 #if INCLUDE_ALL_GCS
1160 // General G1 pre-barrier generator.
1161 void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
1162
1163 // General G1 post-barrier generator
1164 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
1165 #endif // INCLUDE_ALL_GCS
1166
1167 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1168 void push_fTOS();
1169
1170 // pops double TOS element from CPU stack and pushes on FPU stack
1171 void pop_fTOS();
1172
1173 void empty_FPU_stack();
1271 Register Rout_high, Register Rout_low, Register Rtemp );
1272
1273 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
1274 Register Rout_high, Register Rout_low, Register Rtemp );
1275
1276 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
1277 Register Rout_high, Register Rout_low, Register Rtemp );
1278
1279 #ifdef _LP64
1280 void lcmp( Register Ra, Register Rb, Register Rresult);
1281 #endif
1282
1283 // Load and store values by size and signed-ness
1284 void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
1285 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1286
1287 void float_cmp( bool is_float, int unordered_result,
1288 FloatRegister Fa, FloatRegister Fb,
1289 Register Rresult);
1290
1291 void save_all_globals_into_locals();
1292 void restore_globals_from_locals();
1293
1294 // These set the icc condition code to equal if the lock succeeded
1295 // and notEqual if it failed and requires a slow case
1296 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
1297 Register Rscratch,
1298 BiasedLockingCounters* counters = NULL,
1299 bool try_bias = UseBiasedLocking);
1300 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
1301 Register Rscratch,
1302 bool try_bias = UseBiasedLocking);
1303
1304 // Biased locking support
1305 // Upon entry, lock_reg must point to the lock record on the stack,
1306 // obj_reg must contain the target object, and mark_reg must contain
1307 // the target object's header.
1308 // Destroys mark_reg if an attempt is made to bias an anonymously
1309 // biased lock. In this case a failure will go either to the slow
1310 // case or fall through with the notEqual condition code set with
1311 // the expectation that the slow case in the runtime will be called.
1312 // In the fall-through case where the CAS-based lock is done,
1313 // mark_reg is not destroyed.
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