src/cpu/sparc/vm/nativeInst_sparc.cpp

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 145 }
 146 
 147 
 148 // MT-safe patching of a call instruction (and following word).
 149 // First patches the second word, and then atomicly replaces
 150 // the first word with the first new instruction word.
 151 // Other processors might briefly see the old first word
 152 // followed by the new second word.  This is OK if the old
 153 // second word is harmless, and the new second word may be
 154 // harmlessly executed in the delay slot of the call.
 155 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
 156   assert(Patching_lock->is_locked() ||
 157          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
 158    assert (instr_addr != NULL, "illegal address for code patching");
 159    NativeCall* n_call =  nativeCall_at (instr_addr); // checking that it is a call
 160    assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8");
 161    int i0 = ((int*)code_buffer)[0];
 162    int i1 = ((int*)code_buffer)[1];
 163    int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord);
 164    assert(inv_op(*contention_addr) == Assembler::arith_op ||
 165           *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
 166           "must not interfere with original call");
 167    // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
 168    n_call->set_long_at(1*BytesPerInstWord, i1);
 169    n_call->set_long_at(0*BytesPerInstWord, i0);
 170    // NOTE:  It is possible that another thread T will execute
 171    // only the second patched word.
 172    // In other words, since the original instruction is this
 173    //    call patching_stub; nop                   (NativeCall)
 174    // and the new sequence from the buffer is this:
 175    //    sethi %hi(K), %r; add %r, %lo(K), %r      (NativeMovConstReg)
 176    // what T will execute is this:
 177    //    call patching_stub; add %r, %lo(K), %r
 178    // thereby putting garbage into %r before calling the patching stub.
 179    // This is OK, because the patching stub ignores the value of %r.
 180 
 181    // Make sure the first-patched instruction, which may co-exist
 182    // briefly with the call, will do something harmless.
 183    assert(inv_op(*contention_addr) == Assembler::arith_op ||
 184           *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
 185           "must not interfere with original call");
 186 }
 187 
 188 // Similar to replace_mt_safe, but just changes the destination.  The
 189 // important thing is that free-running threads are able to execute this
 190 // call instruction at all times.  Thus, the displacement field must be
 191 // instruction-word-aligned.  This is always true on SPARC.
 192 //
 193 // Used in the runtime linkage of calls; see class CompiledIC.
 194 void NativeCall::set_destination_mt_safe(address dest) {
 195   assert(Patching_lock->is_locked() ||
 196          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
 197   // set_destination uses set_long_at which does the ICache::invalidate
 198   set_destination(dest);
 199 }
 200 
 201 // Code for unit testing implementation of NativeCall class
 202 void NativeCall::test() {
 203 #ifdef ASSERT
 204   ResourceMark rm;


 916 }
 917 
 918 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
 919 // The problem: jump_to <dest> is a 3-word instruction (including its delay slot).
 920 // Atomic write can be only with 1 word.
 921 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
 922   // Here's one way to do it:  Pre-allocate a three-word jump sequence somewhere
 923   // in the header of the nmethod, within a short branch's span of the patch point.
 924   // Set up the jump sequence using NativeJump::insert, and then use an annulled
 925   // unconditional branch at the target site (an atomic 1-word update).
 926   // Limitations:  You can only patch nmethods, with any given nmethod patched at
 927   // most once, and the patch must be in the nmethod's header.
 928   // It's messy, but you can ask the CodeCache for the nmethod containing the
 929   // target address.
 930 
 931   // %%%%% For now, do something MT-stupid:
 932   ResourceMark rm;
 933   int code_size = 1 * BytesPerInstWord;
 934   CodeBuffer cb(verified_entry, code_size + 1);
 935   MacroAssembler* a = new MacroAssembler(&cb);
 936   if (VM_Version::v9_instructions_work()) {
 937     a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler
 938   } else {
 939     a->lduw(G0, 0, O7); // "ld" must agree with code in the signal handler
 940   }
 941   ICache::invalidate_range(verified_entry, code_size);
 942 }
 943 
 944 
 945 void NativeIllegalInstruction::insert(address code_pos) {
 946   NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos);
 947   nii->set_long_at(0, illegal_instruction());
 948 }
 949 
 950 static int illegal_instruction_bits = 0;
 951 
 952 int NativeInstruction::illegal_instruction() {
 953   if (illegal_instruction_bits == 0) {
 954     ResourceMark rm;
 955     char buf[40];
 956     CodeBuffer cbuf((address)&buf[0], 20);
 957     MacroAssembler* a = new MacroAssembler(&cbuf);
 958     address ia = a->pc();
 959     a->trap(ST_RESERVED_FOR_USER_0 + 1);
 960     int bits = *(int*)ia;


1007 }
1008 
1009 
1010 // MT-safe patching of a jmp instruction (and following word).
1011 // First patches the second word, and then atomicly replaces
1012 // the first word with the first new instruction word.
1013 // Other processors might briefly see the old first word
1014 // followed by the new second word.  This is OK if the old
1015 // second word is harmless, and the new second word may be
1016 // harmlessly executed in the delay slot of the call.
1017 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
1018    assert(Patching_lock->is_locked() ||
1019          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
1020    assert (instr_addr != NULL, "illegal address for code patching");
1021    NativeGeneralJump* h_jump =  nativeGeneralJump_at (instr_addr); // checking that it is a call
1022    assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8");
1023    int i0 = ((int*)code_buffer)[0];
1024    int i1 = ((int*)code_buffer)[1];
1025    int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord);
1026    assert(inv_op(*contention_addr) == Assembler::arith_op ||
1027           *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
1028           "must not interfere with original call");
1029    // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
1030    h_jump->set_long_at(1*BytesPerInstWord, i1);
1031    h_jump->set_long_at(0*BytesPerInstWord, i0);
1032    // NOTE:  It is possible that another thread T will execute
1033    // only the second patched word.
1034    // In other words, since the original instruction is this
1035    //    jmp patching_stub; nop                    (NativeGeneralJump)
1036    // and the new sequence from the buffer is this:
1037    //    sethi %hi(K), %r; add %r, %lo(K), %r      (NativeMovConstReg)
1038    // what T will execute is this:
1039    //    jmp patching_stub; add %r, %lo(K), %r
1040    // thereby putting garbage into %r before calling the patching stub.
1041    // This is OK, because the patching stub ignores the value of %r.
1042 
1043    // Make sure the first-patched instruction, which may co-exist
1044    // briefly with the call, will do something harmless.
1045    assert(inv_op(*contention_addr) == Assembler::arith_op ||
1046           *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
1047           "must not interfere with original call");
1048 }


 145 }
 146 
 147 
 148 // MT-safe patching of a call instruction (and following word).
 149 // First patches the second word, and then atomicly replaces
 150 // the first word with the first new instruction word.
 151 // Other processors might briefly see the old first word
 152 // followed by the new second word.  This is OK if the old
 153 // second word is harmless, and the new second word may be
 154 // harmlessly executed in the delay slot of the call.
 155 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
 156   assert(Patching_lock->is_locked() ||
 157          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
 158    assert (instr_addr != NULL, "illegal address for code patching");
 159    NativeCall* n_call =  nativeCall_at (instr_addr); // checking that it is a call
 160    assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8");
 161    int i0 = ((int*)code_buffer)[0];
 162    int i1 = ((int*)code_buffer)[1];
 163    int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord);
 164    assert(inv_op(*contention_addr) == Assembler::arith_op ||
 165           *contention_addr == nop_instruction(),
 166           "must not interfere with original call");
 167    // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
 168    n_call->set_long_at(1*BytesPerInstWord, i1);
 169    n_call->set_long_at(0*BytesPerInstWord, i0);
 170    // NOTE:  It is possible that another thread T will execute
 171    // only the second patched word.
 172    // In other words, since the original instruction is this
 173    //    call patching_stub; nop                   (NativeCall)
 174    // and the new sequence from the buffer is this:
 175    //    sethi %hi(K), %r; add %r, %lo(K), %r      (NativeMovConstReg)
 176    // what T will execute is this:
 177    //    call patching_stub; add %r, %lo(K), %r
 178    // thereby putting garbage into %r before calling the patching stub.
 179    // This is OK, because the patching stub ignores the value of %r.
 180 
 181    // Make sure the first-patched instruction, which may co-exist
 182    // briefly with the call, will do something harmless.
 183    assert(inv_op(*contention_addr) == Assembler::arith_op ||
 184           *contention_addr == nop_instruction(),
 185           "must not interfere with original call");
 186 }
 187 
 188 // Similar to replace_mt_safe, but just changes the destination.  The
 189 // important thing is that free-running threads are able to execute this
 190 // call instruction at all times.  Thus, the displacement field must be
 191 // instruction-word-aligned.  This is always true on SPARC.
 192 //
 193 // Used in the runtime linkage of calls; see class CompiledIC.
 194 void NativeCall::set_destination_mt_safe(address dest) {
 195   assert(Patching_lock->is_locked() ||
 196          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
 197   // set_destination uses set_long_at which does the ICache::invalidate
 198   set_destination(dest);
 199 }
 200 
 201 // Code for unit testing implementation of NativeCall class
 202 void NativeCall::test() {
 203 #ifdef ASSERT
 204   ResourceMark rm;


 916 }
 917 
 918 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
 919 // The problem: jump_to <dest> is a 3-word instruction (including its delay slot).
 920 // Atomic write can be only with 1 word.
 921 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
 922   // Here's one way to do it:  Pre-allocate a three-word jump sequence somewhere
 923   // in the header of the nmethod, within a short branch's span of the patch point.
 924   // Set up the jump sequence using NativeJump::insert, and then use an annulled
 925   // unconditional branch at the target site (an atomic 1-word update).
 926   // Limitations:  You can only patch nmethods, with any given nmethod patched at
 927   // most once, and the patch must be in the nmethod's header.
 928   // It's messy, but you can ask the CodeCache for the nmethod containing the
 929   // target address.
 930 
 931   // %%%%% For now, do something MT-stupid:
 932   ResourceMark rm;
 933   int code_size = 1 * BytesPerInstWord;
 934   CodeBuffer cb(verified_entry, code_size + 1);
 935   MacroAssembler* a = new MacroAssembler(&cb);

 936   a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler



 937   ICache::invalidate_range(verified_entry, code_size);
 938 }
 939 
 940 
 941 void NativeIllegalInstruction::insert(address code_pos) {
 942   NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos);
 943   nii->set_long_at(0, illegal_instruction());
 944 }
 945 
 946 static int illegal_instruction_bits = 0;
 947 
 948 int NativeInstruction::illegal_instruction() {
 949   if (illegal_instruction_bits == 0) {
 950     ResourceMark rm;
 951     char buf[40];
 952     CodeBuffer cbuf((address)&buf[0], 20);
 953     MacroAssembler* a = new MacroAssembler(&cbuf);
 954     address ia = a->pc();
 955     a->trap(ST_RESERVED_FOR_USER_0 + 1);
 956     int bits = *(int*)ia;


1003 }
1004 
1005 
1006 // MT-safe patching of a jmp instruction (and following word).
1007 // First patches the second word, and then atomicly replaces
1008 // the first word with the first new instruction word.
1009 // Other processors might briefly see the old first word
1010 // followed by the new second word.  This is OK if the old
1011 // second word is harmless, and the new second word may be
1012 // harmlessly executed in the delay slot of the call.
1013 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
1014    assert(Patching_lock->is_locked() ||
1015          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
1016    assert (instr_addr != NULL, "illegal address for code patching");
1017    NativeGeneralJump* h_jump =  nativeGeneralJump_at (instr_addr); // checking that it is a call
1018    assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8");
1019    int i0 = ((int*)code_buffer)[0];
1020    int i1 = ((int*)code_buffer)[1];
1021    int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord);
1022    assert(inv_op(*contention_addr) == Assembler::arith_op ||
1023           *contention_addr == nop_instruction(),
1024           "must not interfere with original call");
1025    // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
1026    h_jump->set_long_at(1*BytesPerInstWord, i1);
1027    h_jump->set_long_at(0*BytesPerInstWord, i0);
1028    // NOTE:  It is possible that another thread T will execute
1029    // only the second patched word.
1030    // In other words, since the original instruction is this
1031    //    jmp patching_stub; nop                    (NativeGeneralJump)
1032    // and the new sequence from the buffer is this:
1033    //    sethi %hi(K), %r; add %r, %lo(K), %r      (NativeMovConstReg)
1034    // what T will execute is this:
1035    //    jmp patching_stub; add %r, %lo(K), %r
1036    // thereby putting garbage into %r before calling the patching stub.
1037    // This is OK, because the patching stub ignores the value of %r.
1038 
1039    // Make sure the first-patched instruction, which may co-exist
1040    // briefly with the call, will do something harmless.
1041    assert(inv_op(*contention_addr) == Assembler::arith_op ||
1042           *contention_addr == nop_instruction(),
1043           "must not interfere with original call");
1044 }