src/cpu/sparc/vm/nativeInst_sparc.hpp

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  53   };
  54 
  55   bool is_dtrace_trap();
  56   bool is_nop()                        { return long_at(0) == nop_instruction(); }
  57   bool is_call()                       { return is_op(long_at(0), Assembler::call_op); }
  58   bool is_sethi()                      { return (is_op2(long_at(0), Assembler::sethi_op2)
  59                                           && inv_rd(long_at(0)) != G0); }
  60 
  61   bool sets_cc() {
  62     // conservative (returns true for some instructions that do not set the
  63     // the condition code, such as, "save".
  64     // Does not return true for the deprecated tagged instructions, such as, TADDcc
  65     int x = long_at(0);
  66     return (is_op(x, Assembler::arith_op) &&
  67             (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3);
  68   }
  69   bool is_illegal();
  70   bool is_zombie() {
  71     int x = long_at(0);
  72     return is_op3(x,
  73                   VM_Version::v9_instructions_work() ?
  74                     Assembler::ldsw_op3 : Assembler::lduw_op3,
  75                   Assembler::ldst_op)
  76         && Assembler::inv_rs1(x) == G0
  77         && Assembler::inv_rd(x) == O7;
  78   }
  79   bool is_ic_miss_trap();       // Inline-cache uses a trap to detect a miss
  80   bool is_return() {
  81     // is it the output of MacroAssembler::ret or MacroAssembler::retl?
  82     int x = long_at(0);
  83     const int pc_return_offset = 8; // see frame_sparc.hpp
  84     return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
  85         && (inv_rs1(x) == I7 || inv_rs1(x) == O7)
  86         && inv_immed(x) && inv_simm(x, 13) == pc_return_offset
  87         && inv_rd(x) == G0;
  88   }
  89   bool is_int_jump() {
  90     // is it the output of MacroAssembler::b?
  91     int x = long_at(0);
  92     return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2);
  93   }
  94   bool is_float_jump() {




  53   };
  54 
  55   bool is_dtrace_trap();
  56   bool is_nop()                        { return long_at(0) == nop_instruction(); }
  57   bool is_call()                       { return is_op(long_at(0), Assembler::call_op); }
  58   bool is_sethi()                      { return (is_op2(long_at(0), Assembler::sethi_op2)
  59                                           && inv_rd(long_at(0)) != G0); }
  60 
  61   bool sets_cc() {
  62     // conservative (returns true for some instructions that do not set the
  63     // the condition code, such as, "save".
  64     // Does not return true for the deprecated tagged instructions, such as, TADDcc
  65     int x = long_at(0);
  66     return (is_op(x, Assembler::arith_op) &&
  67             (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3);
  68   }
  69   bool is_illegal();
  70   bool is_zombie() {
  71     int x = long_at(0);
  72     return is_op3(x,
  73                   Assembler::ldsw_op3,

  74                   Assembler::ldst_op)
  75         && Assembler::inv_rs1(x) == G0
  76         && Assembler::inv_rd(x) == O7;
  77   }
  78   bool is_ic_miss_trap();       // Inline-cache uses a trap to detect a miss
  79   bool is_return() {
  80     // is it the output of MacroAssembler::ret or MacroAssembler::retl?
  81     int x = long_at(0);
  82     const int pc_return_offset = 8; // see frame_sparc.hpp
  83     return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
  84         && (inv_rs1(x) == I7 || inv_rs1(x) == O7)
  85         && inv_immed(x) && inv_simm(x, 13) == pc_return_offset
  86         && inv_rd(x) == G0;
  87   }
  88   bool is_int_jump() {
  89     // is it the output of MacroAssembler::b?
  90     int x = long_at(0);
  91     return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2);
  92   }
  93   bool is_float_jump() {