1 /*
   2  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "logging/log.hpp"
  28 #include "memory/resourceArea.hpp"
  29 #include "runtime/java.hpp"
  30 #include "runtime/os.hpp"
  31 #include "runtime/stubCodeGenerator.hpp"
  32 #include "vm_version_sparc.hpp"
  33 
  34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
  35 
  36 void VM_Version::initialize() {
  37   assert(_features != 0, "System pre-initialization is not complete.");
  38   guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
  39 
  40   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
  41   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
  42   PrefetchFieldsAhead         = prefetch_fields_ahead();
  43 
  44   // Allocation prefetch settings
  45   intx cache_line_size = prefetch_data_size();
  46   if( cache_line_size > AllocatePrefetchStepSize )
  47     AllocatePrefetchStepSize = cache_line_size;
  48 
  49   AllocatePrefetchDistance = allocate_prefetch_distance();
  50   AllocatePrefetchStyle    = allocate_prefetch_style();
  51 
  52   if (!has_blk_init() || cache_line_size <= 0) {
  53     if (AllocatePrefetchInstr == 1) {
  54       warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
  55       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
  56     }
  57   }
  58 
  59   UseSSE = 0; // Only on x86 and x64
  60 
  61   _supports_cx8 = has_v9();
  62   _supports_atomic_getset4 = true; // swap instruction
  63 
  64   if (is_niagara()) {
  65     // Indirect branch is the same cost as direct
  66     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
  67       FLAG_SET_DEFAULT(UseInlineCaches, false);
  68     }
  69     // Align loops on a single instruction boundary.
  70     if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
  71       FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
  72     }
  73 #ifdef _LP64
  74     // 32-bit oops don't make sense for the 64-bit VM on sparc
  75     // since the 32-bit VM has the same registers and smaller objects.
  76     Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
  77     Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
  78 #endif // _LP64
  79 #ifdef COMPILER2
  80     // Indirect branch is the same cost as direct
  81     if (FLAG_IS_DEFAULT(UseJumpTables)) {
  82       FLAG_SET_DEFAULT(UseJumpTables, true);
  83     }
  84     // Single-issue, so entry and loop tops are
  85     // aligned on a single instruction boundary
  86     if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
  87       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
  88     }
  89     if (is_niagara_plus()) {
  90       if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
  91           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
  92         // Use BIS instruction for TLAB allocation prefetch.
  93         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
  94       }
  95       if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
  96         if (AllocatePrefetchInstr == 0) {
  97           // Use different prefetch distance without BIS
  98           FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
  99         } else {
 100           // Use smaller prefetch distance with BIS
 101           FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
 102         }
 103       }
 104       if (is_T4()) {
 105         // Double number of prefetched cache lines on T4
 106         // since L2 cache line size is smaller (32 bytes).
 107         if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
 108           FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
 109         }
 110         if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
 111           FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
 112         }
 113       }
 114     }
 115 
 116     if (AllocatePrefetchInstr == 1) {
 117       // Use allocation prefetch style 3 because BIS instructions
 118       // require aligned memory addresses.
 119       FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
 120     }
 121 #endif /* COMPILER2 */
 122   }
 123 
 124   // Use hardware population count instruction if available.
 125   if (has_hardware_popc()) {
 126     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 127       FLAG_SET_DEFAULT(UsePopCountInstruction, true);
 128     }
 129   } else if (UsePopCountInstruction) {
 130     warning("POPC instruction is not available on this CPU");
 131     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
 132   }
 133 
 134   // T4 and newer Sparc cpus have new compare and branch instruction.
 135   if (has_cbcond()) {
 136     if (FLAG_IS_DEFAULT(UseCBCond)) {
 137       FLAG_SET_DEFAULT(UseCBCond, true);
 138     }
 139   } else if (UseCBCond) {
 140     warning("CBCOND instruction is not available on this CPU");
 141     FLAG_SET_DEFAULT(UseCBCond, false);
 142   }
 143 
 144   assert(BlockZeroingLowLimit > 0, "invalid value");
 145   if (has_block_zeroing() && cache_line_size > 0) {
 146     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
 147       FLAG_SET_DEFAULT(UseBlockZeroing, true);
 148     }
 149   } else if (UseBlockZeroing) {
 150     warning("BIS zeroing instructions are not available on this CPU");
 151     FLAG_SET_DEFAULT(UseBlockZeroing, false);
 152   }
 153 
 154   assert(BlockCopyLowLimit > 0, "invalid value");
 155   if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
 156     if (FLAG_IS_DEFAULT(UseBlockCopy)) {
 157       FLAG_SET_DEFAULT(UseBlockCopy, true);
 158     }
 159   } else if (UseBlockCopy) {
 160     warning("BIS instructions are not available or expensive on this CPU");
 161     FLAG_SET_DEFAULT(UseBlockCopy, false);
 162   }
 163 
 164 #ifdef COMPILER2
 165   // T4 and newer Sparc cpus have fast RDPC.
 166   if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
 167     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
 168   }
 169 
 170   // Currently not supported anywhere.
 171   FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 172 
 173   MaxVectorSize = 8;
 174 
 175   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 176 #endif
 177 
 178   assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 179   assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 180 
 181   char buf[512];
 182   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 183                (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
 184                (has_hardware_popc() ? ", popc" : ""),
 185                (has_vis1() ? ", vis1" : ""),
 186                (has_vis2() ? ", vis2" : ""),
 187                (has_vis3() ? ", vis3" : ""),
 188                (has_blk_init() ? ", blk_init" : ""),
 189                (has_cbcond() ? ", cbcond" : ""),
 190                (has_aes() ? ", aes" : ""),
 191                (has_sha1() ? ", sha1" : ""),
 192                (has_sha256() ? ", sha256" : ""),
 193                (has_sha512() ? ", sha512" : ""),
 194                (has_crc32c() ? ", crc32c" : ""),
 195                (is_ultra3() ? ", ultra3" : ""),
 196                (has_sparc5_instr() ? ", sparc5" : ""),
 197                (is_sun4v() ? ", sun4v" : ""),
 198                (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
 199                (is_sparc64() ? ", sparc64" : ""),
 200                (!has_hardware_mul32() ? ", no-mul32" : ""),
 201                (!has_hardware_div32() ? ", no-div32" : ""),
 202                (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
 203 
 204   // buf is started with ", " or is empty
 205   _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
 206 
 207   // UseVIS is set to the smallest of what hardware supports and what
 208   // the command line requires.  I.e., you cannot set UseVIS to 3 on
 209   // older UltraSparc which do not support it.
 210   if (UseVIS > 3) UseVIS=3;
 211   if (UseVIS < 0) UseVIS=0;
 212   if (!has_vis3()) // Drop to 2 if no VIS3 support
 213     UseVIS = MIN2((intx)2,UseVIS);
 214   if (!has_vis2()) // Drop to 1 if no VIS2 support
 215     UseVIS = MIN2((intx)1,UseVIS);
 216   if (!has_vis1()) // Drop to 0 if no VIS1 support
 217     UseVIS = 0;
 218 
 219   // SPARC T4 and above should have support for AES instructions
 220   if (has_aes()) {
 221     if (FLAG_IS_DEFAULT(UseAES)) {
 222       FLAG_SET_DEFAULT(UseAES, true);
 223     }
 224     if (!UseAES) {
 225       if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 226         warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
 227       }
 228       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 229     } else {
 230       // The AES intrinsic stubs require AES instruction support (of course)
 231       // but also require VIS3 mode or higher for instructions it use.
 232       if (UseVIS > 2) {
 233         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 234           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 235         }
 236       } else {
 237         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 238           warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
 239         }
 240         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 241       }
 242     }
 243   } else if (UseAES || UseAESIntrinsics) {
 244     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 245       warning("AES instructions are not available on this CPU");
 246       FLAG_SET_DEFAULT(UseAES, false);
 247     }
 248     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 249       warning("AES intrinsics are not available on this CPU");
 250       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 251     }
 252   }
 253 
 254   if (UseAESCTRIntrinsics) {
 255     warning("AES/CTR intrinsics are not available on this CPU");
 256     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 257   }
 258 
 259   // GHASH/GCM intrinsics
 260   if (has_vis3() && (UseVIS > 2)) {
 261     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 262       UseGHASHIntrinsics = true;
 263     }
 264   } else if (UseGHASHIntrinsics) {
 265     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 266       warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
 267     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 268   }
 269 
 270   // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
 271   if (has_sha1() || has_sha256() || has_sha512()) {
 272     if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
 273       if (FLAG_IS_DEFAULT(UseSHA)) {
 274         FLAG_SET_DEFAULT(UseSHA, true);
 275       }
 276     } else {
 277       if (UseSHA) {
 278         warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
 279         FLAG_SET_DEFAULT(UseSHA, false);
 280       }
 281     }
 282   } else if (UseSHA) {
 283     warning("SHA instructions are not available on this CPU");
 284     FLAG_SET_DEFAULT(UseSHA, false);
 285   }
 286 
 287   if (UseSHA && has_sha1()) {
 288     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 289       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 290     }
 291   } else if (UseSHA1Intrinsics) {
 292     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 293     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 294   }
 295 
 296   if (UseSHA && has_sha256()) {
 297     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 298       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 299     }
 300   } else if (UseSHA256Intrinsics) {
 301     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 302     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 303   }
 304 
 305   if (UseSHA && has_sha512()) {
 306     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 307       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 308     }
 309   } else if (UseSHA512Intrinsics) {
 310     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 311     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 312   }
 313 
 314   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 315     FLAG_SET_DEFAULT(UseSHA, false);
 316   }
 317 
 318   // SPARC T4 and above should have support for CRC32C instruction
 319   if (has_crc32c()) {
 320     if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
 321       if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 322         FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 323       }
 324     } else {
 325       if (UseCRC32CIntrinsics) {
 326         warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 327         FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 328       }
 329     }
 330   } else if (UseCRC32CIntrinsics) {
 331     warning("CRC32C instruction is not available on this CPU");
 332     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 333   }
 334 
 335   if (UseVIS > 2) {
 336     if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
 337       FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
 338     }
 339   } else if (UseAdler32Intrinsics) {
 340     warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 341     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 342   }
 343 
 344   if (UseVIS > 2) {
 345     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 346       FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
 347     }
 348   } else if (UseCRC32Intrinsics) {
 349     warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
 350     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 351   }
 352 
 353   if (UseVectorizedMismatchIntrinsic) {
 354     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 355     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 356   }
 357 
 358   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 359     (cache_line_size > ContendedPaddingWidth))
 360     ContendedPaddingWidth = cache_line_size;
 361 
 362   // This machine does not allow unaligned memory accesses
 363   if (UseUnalignedAccesses) {
 364     if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
 365       warning("Unaligned memory access is not available on this CPU");
 366     FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
 367   }
 368 
 369   if (log_is_enabled(Info, os, cpu)) {
 370     ResourceMark rm;
 371     outputStream* log = Log(os, cpu)::info_stream();
 372     log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 373     log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
 374     log->print("Allocation");
 375     if (AllocatePrefetchStyle <= 0) {
 376       log->print(": no prefetching");
 377     } else {
 378       log->print(" prefetching: ");
 379       if (AllocatePrefetchInstr == 0) {
 380           log->print("PREFETCH");
 381       } else if (AllocatePrefetchInstr == 1) {
 382           log->print("BIS");
 383       }
 384       if (AllocatePrefetchLines > 1) {
 385         log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
 386       } else {
 387         log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
 388       }
 389     }
 390     if (PrefetchCopyIntervalInBytes > 0) {
 391       log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
 392     }
 393     if (PrefetchScanIntervalInBytes > 0) {
 394       log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
 395     }
 396     if (PrefetchFieldsAhead > 0) {
 397       log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
 398     }
 399     if (ContendedPaddingWidth > 0) {
 400       log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
 401     }
 402   }
 403 }
 404 
 405 void VM_Version::print_features() {
 406   tty->print_cr("Version:%s", _features);
 407 }
 408 
 409 int VM_Version::determine_features() {
 410   if (UseV8InstrsOnly) {
 411     log_info(os, cpu)("Version is Forced-V8");
 412     return generic_v8_m;
 413   }
 414 
 415   int features = platform_features(unknown_m); // platform_features() is os_arch specific
 416 
 417   if (features == unknown_m) {
 418     features = generic_v9_m;
 419     log_info(os)("Cannot recognize SPARC version. Default to V9");
 420   }
 421 
 422   assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
 423   if (UseNiagaraInstrs) { // Force code generation for Niagara
 424     if (is_T_family(features)) {
 425       // Happy to accomodate...
 426     } else {
 427       log_info(os, cpu)("Version is Forced-Niagara");
 428       features |= T_family_m;
 429     }
 430   } else {
 431     if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
 432       log_info(os, cpu)("Version is Forced-Not-Niagara");
 433       features &= ~(T_family_m | T1_model_m);
 434     } else {
 435       // Happy to accomodate...
 436     }
 437   }
 438 
 439   return features;
 440 }
 441 
 442 static uint64_t saved_features = 0;
 443 
 444 void VM_Version::allow_all() {
 445   saved_features = _features;
 446   _features      = all_features_m;
 447 }
 448 
 449 void VM_Version::revert() {
 450   _features = saved_features;
 451 }
 452 
 453 unsigned int VM_Version::calc_parallel_worker_threads() {
 454   unsigned int result;
 455   if (is_M_series()) {
 456     // for now, use same gc thread calculation for M-series as for niagara-plus
 457     // in future, we may want to tweak parameters for nof_parallel_worker_thread
 458     result = nof_parallel_worker_threads(5, 16, 8);
 459   } else if (is_niagara_plus()) {
 460     result = nof_parallel_worker_threads(5, 16, 8);
 461   } else {
 462     result = nof_parallel_worker_threads(5, 8, 8);
 463   }
 464   return result;
 465 }
 466 
 467 
 468 int VM_Version::parse_features(const char* implementation) {
 469   int features = unknown_m;
 470   // Convert to UPPER case before compare.
 471   char* impl = os::strdup_check_oom(implementation);
 472 
 473   for (int i = 0; impl[i] != 0; i++)
 474     impl[i] = (char)toupper((uint)impl[i]);
 475 
 476   if (strstr(impl, "SPARC64") != NULL) {
 477     features |= sparc64_family_m;
 478   } else if (strstr(impl, "SPARC-M") != NULL) {
 479     // M-series SPARC is based on T-series.
 480     features |= (M_family_m | T_family_m);
 481   } else if (strstr(impl, "SPARC-T") != NULL) {
 482     features |= T_family_m;
 483     if (strstr(impl, "SPARC-T1") != NULL) {
 484       features |= T1_model_m;
 485     }
 486   } else if (strstr(impl, "SUN4V-CPU") != NULL) {
 487     // Generic or migration class LDOM
 488     features |= T_family_m;
 489   } else {
 490     log_info(os, cpu)("Failed to parse CPU implementation = '%s'", impl);
 491   }
 492   os::free((void*)impl);
 493   return features;
 494 }