1276   // That's why we must use the macroassembler to generate a handler.
1277   MacroAssembler _masm(&cbuf);
1278   address base =
1279   __ start_a_stub(size_exception_handler());
1280   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1281   int offset = __ offset();
1282   InternalAddress here(__ pc());
1283   __ pushptr(here.addr());
1284 
1285   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1286   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1287   __ end_a_stub();
1288   return offset;
1289 }
1290 
1291 
1292 const bool Matcher::match_rule_supported(int opcode) {
1293   if (!has_match_rule(opcode))
1294     return false;
1295 








1296   return true;  // Per default match rules are supported.
1297 }
1298 
1299 int Matcher::regnum_to_fpu_offset(int regnum) {
1300   return regnum - 32; // The FP registers are in the second chunk
1301 }
1302 
1303 // This is UltraSparc specific, true just means we have fast l2f conversion
1304 const bool Matcher::convL2FSupported(void) {
1305   return true;
1306 }
1307 
1308 // Vector width in bytes
1309 const uint Matcher::vector_width_in_bytes(void) {
1310   return UseSSE >= 2 ? 8 : 0;
1311 }
1312 
1313 // Vector ideal reg
1314 const uint Matcher::vector_ideal_reg(void) {
1315   return Op_RegD;

1276   // That's why we must use the macroassembler to generate a handler.
1277   MacroAssembler _masm(&cbuf);
1278   address base =
1279   __ start_a_stub(size_exception_handler());
1280   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1281   int offset = __ offset();
1282   InternalAddress here(__ pc());
1283   __ pushptr(here.addr());
1284 
1285   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1286   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1287   __ end_a_stub();
1288   return offset;
1289 }
1290 
1291 
1292 const bool Matcher::match_rule_supported(int opcode) {
1293   if (!has_match_rule(opcode))
1294     return false;
1295 
1296   switch (opcode) {
1297     case Op_PopCountI:
1298     case Op_PopCountL:
1299       if (!UsePopCountInstruction)
1300         return false;
1301     break;
1302   }
1303   
1304   return true;  // Per default match rules are supported.
1305 }
1306 
1307 int Matcher::regnum_to_fpu_offset(int regnum) {
1308   return regnum - 32; // The FP registers are in the second chunk
1309 }
1310 
1311 // This is UltraSparc specific, true just means we have fast l2f conversion
1312 const bool Matcher::convL2FSupported(void) {
1313   return true;
1314 }
1315 
1316 // Vector width in bytes
1317 const uint Matcher::vector_width_in_bytes(void) {
1318   return UseSSE >= 2 ? 8 : 0;
1319 }
1320 
1321 // Vector ideal reg
1322 const uint Matcher::vector_ideal_reg(void) {
1323   return Op_RegD;