1 /*
   2  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "compiler/compileLog.hpp"
  27 #include "compiler/oopMap.hpp"
  28 #include "memory/allocation.inline.hpp"
  29 #include "opto/addnode.hpp"
  30 #include "opto/block.hpp"
  31 #include "opto/callnode.hpp"
  32 #include "opto/cfgnode.hpp"
  33 #include "opto/chaitin.hpp"
  34 #include "opto/coalesce.hpp"
  35 #include "opto/connode.hpp"
  36 #include "opto/idealGraphPrinter.hpp"
  37 #include "opto/indexSet.hpp"
  38 #include "opto/machnode.hpp"
  39 #include "opto/memnode.hpp"
  40 #include "opto/movenode.hpp"
  41 #include "opto/opcodes.hpp"
  42 #include "opto/rootnode.hpp"
  43 
  44 #ifndef PRODUCT
  45 void LRG::dump() const {
  46   ttyLocker ttyl;
  47   tty->print("%d ",num_regs());
  48   _mask.dump();
  49   if( _msize_valid ) {
  50     if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
  51     else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
  52   } else {
  53     tty->print(", #?(%d) ",_mask.Size());
  54   }
  55 
  56   tty->print("EffDeg: ");
  57   if( _degree_valid ) tty->print( "%d ", _eff_degree );
  58   else tty->print("? ");
  59 
  60   if( is_multidef() ) {
  61     tty->print("MultiDef ");
  62     if (_defs != NULL) {
  63       tty->print("(");
  64       for (int i = 0; i < _defs->length(); i++) {
  65         tty->print("N%d ", _defs->at(i)->_idx);
  66       }
  67       tty->print(") ");
  68     }
  69   }
  70   else if( _def == 0 ) tty->print("Dead ");
  71   else tty->print("Def: N%d ",_def->_idx);
  72 
  73   tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
  74   // Flags
  75   if( _is_oop ) tty->print("Oop ");
  76   if( _is_float ) tty->print("Float ");
  77   if( _is_vector ) tty->print("Vector ");
  78   if( _was_spilled1 ) tty->print("Spilled ");
  79   if( _was_spilled2 ) tty->print("Spilled2 ");
  80   if( _direct_conflict ) tty->print("Direct_conflict ");
  81   if( _fat_proj ) tty->print("Fat ");
  82   if( _was_lo ) tty->print("Lo ");
  83   if( _has_copy ) tty->print("Copy ");
  84   if( _at_risk ) tty->print("Risk ");
  85 
  86   if( _must_spill ) tty->print("Must_spill ");
  87   if( _is_bound ) tty->print("Bound ");
  88   if( _msize_valid ) {
  89     if( _degree_valid && lo_degree() ) tty->print("Trivial ");
  90   }
  91 
  92   tty->cr();
  93 }
  94 #endif
  95 
  96 // Compute score from cost and area.  Low score is best to spill.
  97 static double raw_score( double cost, double area ) {
  98   return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
  99 }
 100 
 101 double LRG::score() const {
 102   // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
 103   // Bigger area lowers score, encourages spilling this live range.
 104   // Bigger cost raise score, prevents spilling this live range.
 105   // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
 106   // to turn a divide by a constant into a multiply by the reciprical).
 107   double score = raw_score( _cost, _area);
 108 
 109   // Account for area.  Basically, LRGs covering large areas are better
 110   // to spill because more other LRGs get freed up.
 111   if( _area == 0.0 )            // No area?  Then no progress to spill
 112     return 1e35;
 113 
 114   if( _was_spilled2 )           // If spilled once before, we are unlikely
 115     return score + 1e30;        // to make progress again.
 116 
 117   if( _cost >= _area*3.0 )      // Tiny area relative to cost
 118     return score + 1e17;        // Probably no progress to spill
 119 
 120   if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
 121     return score + 1e10;        // Likely no progress to spill
 122 
 123   return score;
 124 }
 125 
 126 #define NUMBUCKS 3
 127 
 128 // Straight out of Tarjan's union-find algorithm
 129 uint LiveRangeMap::find_compress(uint lrg) {
 130   uint cur = lrg;
 131   uint next = _uf_map.at(cur);
 132   while (next != cur) { // Scan chain of equivalences
 133     assert( next < cur, "always union smaller");
 134     cur = next; // until find a fixed-point
 135     next = _uf_map.at(cur);
 136   }
 137 
 138   // Core of union-find algorithm: update chain of
 139   // equivalences to be equal to the root.
 140   while (lrg != next) {
 141     uint tmp = _uf_map.at(lrg);
 142     _uf_map.at_put(lrg, next);
 143     lrg = tmp;
 144   }
 145   return lrg;
 146 }
 147 
 148 // Reset the Union-Find map to identity
 149 void LiveRangeMap::reset_uf_map(uint max_lrg_id) {
 150   _max_lrg_id= max_lrg_id;
 151   // Force the Union-Find mapping to be at least this large
 152   _uf_map.at_put_grow(_max_lrg_id, 0);
 153   // Initialize it to be the ID mapping.
 154   for (uint i = 0; i < _max_lrg_id; ++i) {
 155     _uf_map.at_put(i, i);
 156   }
 157 }
 158 
 159 // Make all Nodes map directly to their final live range; no need for
 160 // the Union-Find mapping after this call.
 161 void LiveRangeMap::compress_uf_map_for_nodes() {
 162   // For all Nodes, compress mapping
 163   uint unique = _names.length();
 164   for (uint i = 0; i < unique; ++i) {
 165     uint lrg = _names.at(i);
 166     uint compressed_lrg = find(lrg);
 167     if (lrg != compressed_lrg) {
 168       _names.at_put(i, compressed_lrg);
 169     }
 170   }
 171 }
 172 
 173 // Like Find above, but no path compress, so bad asymptotic behavior
 174 uint LiveRangeMap::find_const(uint lrg) const {
 175   if (!lrg) {
 176     return lrg; // Ignore the zero LRG
 177   }
 178 
 179   // Off the end?  This happens during debugging dumps when you got
 180   // brand new live ranges but have not told the allocator yet.
 181   if (lrg >= _max_lrg_id) {
 182     return lrg;
 183   }
 184 
 185   uint next = _uf_map.at(lrg);
 186   while (next != lrg) { // Scan chain of equivalences
 187     assert(next < lrg, "always union smaller");
 188     lrg = next; // until find a fixed-point
 189     next = _uf_map.at(lrg);
 190   }
 191   return next;
 192 }
 193 
 194 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher, bool scheduling_info_generated)
 195   : PhaseRegAlloc(unique, cfg, matcher,
 196 #ifndef PRODUCT
 197        print_chaitin_statistics
 198 #else
 199        NULL
 200 #endif
 201        )
 202   , _lrg_map(Thread::current()->resource_area(), unique)
 203   , _live(0)
 204   , _spilled_once(Thread::current()->resource_area())
 205   , _spilled_twice(Thread::current()->resource_area())
 206   , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0)
 207   , _oldphi(unique)
 208   , _scheduling_info_generated(scheduling_info_generated)
 209   , _sched_int_pressure(0, INTPRESSURE)
 210   , _sched_float_pressure(0, FLOATPRESSURE)
 211   , _scratch_int_pressure(0, INTPRESSURE)
 212   , _scratch_float_pressure(0, FLOATPRESSURE)
 213 #ifndef PRODUCT
 214   , _trace_spilling(C->env()->dirset()->TraceSpillingOption)
 215 #endif
 216 {
 217   Compile::TracePhase tp("ctorChaitin", &timers[_t_ctorChaitin]);
 218 
 219   _high_frequency_lrg = MIN2(double(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
 220 
 221   // Build a list of basic blocks, sorted by frequency
 222   _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
 223   // Experiment with sorting strategies to speed compilation
 224   double  cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
 225   Block **buckets[NUMBUCKS];             // Array of buckets
 226   uint    buckcnt[NUMBUCKS];             // Array of bucket counters
 227   double  buckval[NUMBUCKS];             // Array of bucket value cutoffs
 228   for (uint i = 0; i < NUMBUCKS; i++) {
 229     buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
 230     buckcnt[i] = 0;
 231     // Bump by three orders of magnitude each time
 232     cutoff *= 0.001;
 233     buckval[i] = cutoff;
 234     for (uint j = 0; j < _cfg.number_of_blocks(); j++) {
 235       buckets[i][j] = NULL;
 236     }
 237   }
 238   // Sort blocks into buckets
 239   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
 240     for (uint j = 0; j < NUMBUCKS; j++) {
 241       if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) {
 242         // Assign block to end of list for appropriate bucket
 243         buckets[j][buckcnt[j]++] = _cfg.get_block(i);
 244         break; // kick out of inner loop
 245       }
 246     }
 247   }
 248   // Dump buckets into final block array
 249   uint blkcnt = 0;
 250   for (uint i = 0; i < NUMBUCKS; i++) {
 251     for (uint j = 0; j < buckcnt[i]; j++) {
 252       _blks[blkcnt++] = buckets[i][j];
 253     }
 254   }
 255 
 256   assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled");
 257 }
 258 
 259 // union 2 sets together.
 260 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
 261   uint src = _lrg_map.find(src_n);
 262   uint dst = _lrg_map.find(dst_n);
 263   assert(src, "");
 264   assert(dst, "");
 265   assert(src < _lrg_map.max_lrg_id(), "oob");
 266   assert(dst < _lrg_map.max_lrg_id(), "oob");
 267   assert(src < dst, "always union smaller");
 268   _lrg_map.uf_map(dst, src);
 269 }
 270 
 271 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
 272   // Make the Node->LRG mapping
 273   _lrg_map.extend(x->_idx,lrg);
 274   // Make the Union-Find mapping an identity function
 275   _lrg_map.uf_extend(lrg, lrg);
 276 }
 277 
 278 
 279 int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) {
 280   assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections");
 281   DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); )
 282   int found_projs = 0;
 283   uint cnt = orig->outcnt();
 284   for (uint i = 0; i < cnt; i++) {
 285     Node* proj = orig->raw_out(i);
 286     if (proj->is_MachProj()) {
 287       assert(proj->outcnt() == 0, "only kill projections are expected here");
 288       assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections");
 289       found_projs++;
 290       // Copy kill projections after the cloned node
 291       Node* kills = proj->clone();
 292       kills->set_req(0, copy);
 293       b->insert_node(kills, idx++);
 294       _cfg.map_node_to_block(kills, b);
 295       new_lrg(kills, max_lrg_id++);
 296     }
 297   }
 298   return found_projs;
 299 }
 300 
 301 // Renumber the live ranges to compact them.  Makes the IFG smaller.
 302 void PhaseChaitin::compact() {
 303   Compile::TracePhase tp("chaitinCompact", &timers[_t_chaitinCompact]);
 304 
 305   // Current the _uf_map contains a series of short chains which are headed
 306   // by a self-cycle.  All the chains run from big numbers to little numbers.
 307   // The Find() call chases the chains & shortens them for the next Find call.
 308   // We are going to change this structure slightly.  Numbers above a moving
 309   // wave 'i' are unchanged.  Numbers below 'j' point directly to their
 310   // compacted live range with no further chaining.  There are no chains or
 311   // cycles below 'i', so the Find call no longer works.
 312   uint j=1;
 313   uint i;
 314   for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
 315     uint lr = _lrg_map.uf_live_range_id(i);
 316     // Ignore unallocated live ranges
 317     if (!lr) {
 318       continue;
 319     }
 320     assert(lr <= i, "");
 321     _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr));
 322   }
 323   // Now change the Node->LR mapping to reflect the compacted names
 324   uint unique = _lrg_map.size();
 325   for (i = 0; i < unique; i++) {
 326     uint lrg_id = _lrg_map.live_range_id(i);
 327     _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id));
 328   }
 329 
 330   // Reset the Union-Find mapping
 331   _lrg_map.reset_uf_map(j);
 332 }
 333 
 334 void PhaseChaitin::Register_Allocate() {
 335 
 336   // Above the OLD FP (and in registers) are the incoming arguments.  Stack
 337   // slots in this area are called "arg_slots".  Above the NEW FP (and in
 338   // registers) is the outgoing argument area; above that is the spill/temp
 339   // area.  These are all "frame_slots".  Arg_slots start at the zero
 340   // stack_slots and count up to the known arg_size.  Frame_slots start at
 341   // the stack_slot #arg_size and go up.  After allocation I map stack
 342   // slots to actual offsets.  Stack-slots in the arg_slot area are biased
 343   // by the frame_size; stack-slots in the frame_slot area are biased by 0.
 344 
 345   _trip_cnt = 0;
 346   _alternate = 0;
 347   _matcher._allocation_started = true;
 348 
 349   ResourceArea split_arena;     // Arena for Split local resources
 350   ResourceArea live_arena;      // Arena for liveness & IFG info
 351   ResourceMark rm(&live_arena);
 352 
 353   // Need live-ness for the IFG; need the IFG for coalescing.  If the
 354   // liveness is JUST for coalescing, then I can get some mileage by renaming
 355   // all copy-related live ranges low and then using the max copy-related
 356   // live range as a cut-off for LIVE and the IFG.  In other words, I can
 357   // build a subset of LIVE and IFG just for copies.
 358   PhaseLive live(_cfg, _lrg_map.names(), &live_arena, false);
 359 
 360   // Need IFG for coalescing and coloring
 361   PhaseIFG ifg(&live_arena);
 362   _ifg = &ifg;
 363 
 364   // Come out of SSA world to the Named world.  Assign (virtual) registers to
 365   // Nodes.  Use the same register for all inputs and the output of PhiNodes
 366   // - effectively ending SSA form.  This requires either coalescing live
 367   // ranges or inserting copies.  For the moment, we insert "virtual copies"
 368   // - we pretend there is a copy prior to each Phi in predecessor blocks.
 369   // We will attempt to coalesce such "virtual copies" before we manifest
 370   // them for real.
 371   de_ssa();
 372 
 373 #ifdef ASSERT
 374   // Veify the graph before RA.
 375   verify(&live_arena);
 376 #endif
 377 
 378   {
 379     Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
 380     _live = NULL;                 // Mark live as being not available
 381     rm.reset_to_mark();           // Reclaim working storage
 382     IndexSet::reset_memory(C, &live_arena);
 383     ifg.init(_lrg_map.max_lrg_id()); // Empty IFG
 384     gather_lrg_masks( false );    // Collect LRG masks
 385     live.compute(_lrg_map.max_lrg_id()); // Compute liveness
 386     _live = &live;                // Mark LIVE as being available
 387   }
 388 
 389   // Base pointers are currently "used" by instructions which define new
 390   // derived pointers.  This makes base pointers live up to the where the
 391   // derived pointer is made, but not beyond.  Really, they need to be live
 392   // across any GC point where the derived value is live.  So this code looks
 393   // at all the GC points, and "stretches" the live range of any base pointer
 394   // to the GC point.
 395   if (stretch_base_pointer_live_ranges(&live_arena)) {
 396     Compile::TracePhase tp("computeLive (sbplr)", &timers[_t_computeLive]);
 397     // Since some live range stretched, I need to recompute live
 398     _live = NULL;
 399     rm.reset_to_mark();         // Reclaim working storage
 400     IndexSet::reset_memory(C, &live_arena);
 401     ifg.init(_lrg_map.max_lrg_id());
 402     gather_lrg_masks(false);
 403     live.compute(_lrg_map.max_lrg_id());
 404     _live = &live;
 405   }
 406   // Create the interference graph using virtual copies
 407   build_ifg_virtual();  // Include stack slots this time
 408 
 409   // The IFG is/was triangular.  I am 'squaring it up' so Union can run
 410   // faster.  Union requires a 'for all' operation which is slow on the
 411   // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
 412   // meaning I can visit all the Nodes neighbors less than a Node in time
 413   // O(# of neighbors), but I have to visit all the Nodes greater than a
 414   // given Node and search them for an instance, i.e., time O(#MaxLRG)).
 415   _ifg->SquareUp();
 416 
 417   // Aggressive (but pessimistic) copy coalescing.
 418   // This pass works on virtual copies.  Any virtual copies which are not
 419   // coalesced get manifested as actual copies
 420   {
 421     Compile::TracePhase tp("chaitinCoalesce1", &timers[_t_chaitinCoalesce1]);
 422 
 423     PhaseAggressiveCoalesce coalesce(*this);
 424     coalesce.coalesce_driver();
 425     // Insert un-coalesced copies.  Visit all Phis.  Where inputs to a Phi do
 426     // not match the Phi itself, insert a copy.
 427     coalesce.insert_copies(_matcher);
 428     if (C->failing()) {
 429       return;
 430     }
 431   }
 432 
 433   // After aggressive coalesce, attempt a first cut at coloring.
 434   // To color, we need the IFG and for that we need LIVE.
 435   {
 436     Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
 437     _live = NULL;
 438     rm.reset_to_mark();           // Reclaim working storage
 439     IndexSet::reset_memory(C, &live_arena);
 440     ifg.init(_lrg_map.max_lrg_id());
 441     gather_lrg_masks( true );
 442     live.compute(_lrg_map.max_lrg_id());
 443     _live = &live;
 444   }
 445 
 446   // Build physical interference graph
 447   uint must_spill = 0;
 448   must_spill = build_ifg_physical(&live_arena);
 449   // If we have a guaranteed spill, might as well spill now
 450   if (must_spill) {
 451     if(!_lrg_map.max_lrg_id()) {
 452       return;
 453     }
 454     // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
 455     C->check_node_count(10*must_spill, "out of nodes before split");
 456     if (C->failing()) {
 457       return;
 458     }
 459 
 460     uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena);  // Split spilling LRG everywhere
 461     _lrg_map.set_max_lrg_id(new_max_lrg_id);
 462     // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
 463     // or we failed to split
 464     C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
 465     if (C->failing()) {
 466       return;
 467     }
 468 
 469     NOT_PRODUCT(C->verify_graph_edges();)
 470 
 471     compact();                  // Compact LRGs; return new lower max lrg
 472 
 473     {
 474       Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
 475       _live = NULL;
 476       rm.reset_to_mark();         // Reclaim working storage
 477       IndexSet::reset_memory(C, &live_arena);
 478       ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph
 479       gather_lrg_masks( true );   // Collect intersect mask
 480       live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
 481       _live = &live;
 482     }
 483     build_ifg_physical(&live_arena);
 484     _ifg->SquareUp();
 485     _ifg->Compute_Effective_Degree();
 486     // Only do conservative coalescing if requested
 487     if (OptoCoalesce) {
 488       Compile::TracePhase tp("chaitinCoalesce2", &timers[_t_chaitinCoalesce2]);
 489       // Conservative (and pessimistic) copy coalescing of those spills
 490       PhaseConservativeCoalesce coalesce(*this);
 491       // If max live ranges greater than cutoff, don't color the stack.
 492       // This cutoff can be larger than below since it is only done once.
 493       coalesce.coalesce_driver();
 494     }
 495     _lrg_map.compress_uf_map_for_nodes();
 496 
 497 #ifdef ASSERT
 498     verify(&live_arena, true);
 499 #endif
 500   } else {
 501     ifg.SquareUp();
 502     ifg.Compute_Effective_Degree();
 503 #ifdef ASSERT
 504     set_was_low();
 505 #endif
 506   }
 507 
 508   // Prepare for Simplify & Select
 509   cache_lrg_info();           // Count degree of LRGs
 510 
 511   // Simplify the InterFerence Graph by removing LRGs of low degree.
 512   // LRGs of low degree are trivially colorable.
 513   Simplify();
 514 
 515   // Select colors by re-inserting LRGs back into the IFG in reverse order.
 516   // Return whether or not something spills.
 517   uint spills = Select( );
 518 
 519   // If we spill, split and recycle the entire thing
 520   while( spills ) {
 521     if( _trip_cnt++ > 24 ) {
 522       DEBUG_ONLY( dump_for_spill_split_recycle(); )
 523       if( _trip_cnt > 27 ) {
 524         C->record_method_not_compilable("failed spill-split-recycle sanity check");
 525         return;
 526       }
 527     }
 528 
 529     if (!_lrg_map.max_lrg_id()) {
 530       return;
 531     }
 532     uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena);  // Split spilling LRG everywhere
 533     _lrg_map.set_max_lrg_id(new_max_lrg_id);
 534     // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
 535     C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split");
 536     if (C->failing()) {
 537       return;
 538     }
 539 
 540     compact(); // Compact LRGs; return new lower max lrg
 541 
 542     // Nuke the live-ness and interference graph and LiveRanGe info
 543     {
 544       Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
 545       _live = NULL;
 546       rm.reset_to_mark();         // Reclaim working storage
 547       IndexSet::reset_memory(C, &live_arena);
 548       ifg.init(_lrg_map.max_lrg_id());
 549 
 550       // Create LiveRanGe array.
 551       // Intersect register masks for all USEs and DEFs
 552       gather_lrg_masks(true);
 553       live.compute(_lrg_map.max_lrg_id());
 554       _live = &live;
 555     }
 556     must_spill = build_ifg_physical(&live_arena);
 557     _ifg->SquareUp();
 558     _ifg->Compute_Effective_Degree();
 559 
 560     // Only do conservative coalescing if requested
 561     if (OptoCoalesce) {
 562       Compile::TracePhase tp("chaitinCoalesce3", &timers[_t_chaitinCoalesce3]);
 563       // Conservative (and pessimistic) copy coalescing
 564       PhaseConservativeCoalesce coalesce(*this);
 565       // Check for few live ranges determines how aggressive coalesce is.
 566       coalesce.coalesce_driver();
 567     }
 568     _lrg_map.compress_uf_map_for_nodes();
 569 #ifdef ASSERT
 570     verify(&live_arena, true);
 571 #endif
 572     cache_lrg_info();           // Count degree of LRGs
 573 
 574     // Simplify the InterFerence Graph by removing LRGs of low degree.
 575     // LRGs of low degree are trivially colorable.
 576     Simplify();
 577 
 578     // Select colors by re-inserting LRGs back into the IFG in reverse order.
 579     // Return whether or not something spills.
 580     spills = Select();
 581   }
 582 
 583   // Count number of Simplify-Select trips per coloring success.
 584   _allocator_attempts += _trip_cnt + 1;
 585   _allocator_successes += 1;
 586 
 587   // Peephole remove copies
 588   post_allocate_copy_removal();
 589 
 590   // Merge multidefs if multiple defs representing the same value are used in a single block.
 591   merge_multidefs();
 592 
 593 #ifdef ASSERT
 594   // Veify the graph after RA.
 595   verify(&live_arena);
 596 #endif
 597 
 598   // max_reg is past the largest *register* used.
 599   // Convert that to a frame_slot number.
 600   if (_max_reg <= _matcher._new_SP) {
 601     _framesize = C->out_preserve_stack_slots();
 602   }
 603   else {
 604     _framesize = _max_reg -_matcher._new_SP;
 605   }
 606   assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
 607 
 608   // This frame must preserve the required fp alignment
 609   _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots());
 610   assert(_framesize <= 1000000, "sanity check");
 611 #ifndef PRODUCT
 612   _total_framesize += _framesize;
 613   if ((int)_framesize > _max_framesize) {
 614     _max_framesize = _framesize;
 615   }
 616 #endif
 617 
 618   // Convert CISC spills
 619   fixup_spills();
 620 
 621   // Log regalloc results
 622   CompileLog* log = Compile::current()->log();
 623   if (log != NULL) {
 624     log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
 625   }
 626 
 627   if (C->failing()) {
 628     return;
 629   }
 630 
 631   NOT_PRODUCT(C->verify_graph_edges();)
 632 
 633   // Move important info out of the live_arena to longer lasting storage.
 634   alloc_node_regs(_lrg_map.size());
 635   for (uint i=0; i < _lrg_map.size(); i++) {
 636     if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
 637       LRG &lrg = lrgs(_lrg_map.live_range_id(i));
 638       if (!lrg.alive()) {
 639         set_bad(i);
 640       } else if (lrg.num_regs() == 1) {
 641         set1(i, lrg.reg());
 642       } else {                  // Must be a register-set
 643         if (!lrg._fat_proj) {   // Must be aligned adjacent register set
 644           // Live ranges record the highest register in their mask.
 645           // We want the low register for the AD file writer's convenience.
 646           OptoReg::Name hi = lrg.reg(); // Get hi register
 647           OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo
 648           // We have to use pair [lo,lo+1] even for wide vectors because
 649           // the rest of code generation works only with pairs. It is safe
 650           // since for registers encoding only 'lo' is used.
 651           // Second reg from pair is used in ScheduleAndBundle on SPARC where
 652           // vector max size is 8 which corresponds to registers pair.
 653           // It is also used in BuildOopMaps but oop operations are not
 654           // vectorized.
 655           set2(i, lo);
 656         } else {                // Misaligned; extract 2 bits
 657           OptoReg::Name hi = lrg.reg(); // Get hi register
 658           lrg.Remove(hi);       // Yank from mask
 659           int lo = lrg.mask().find_first_elem(); // Find lo
 660           set_pair(i, hi, lo);
 661         }
 662       }
 663       if( lrg._is_oop ) _node_oops.set(i);
 664     } else {
 665       set_bad(i);
 666     }
 667   }
 668 
 669   // Done!
 670   _live = NULL;
 671   _ifg = NULL;
 672   C->set_indexSet_arena(NULL);  // ResourceArea is at end of scope
 673 }
 674 
 675 void PhaseChaitin::de_ssa() {
 676   // Set initial Names for all Nodes.  Most Nodes get the virtual register
 677   // number.  A few get the ZERO live range number.  These do not
 678   // get allocated, but instead rely on correct scheduling to ensure that
 679   // only one instance is simultaneously live at a time.
 680   uint lr_counter = 1;
 681   for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
 682     Block* block = _cfg.get_block(i);
 683     uint cnt = block->number_of_nodes();
 684 
 685     // Handle all the normal Nodes in the block
 686     for( uint j = 0; j < cnt; j++ ) {
 687       Node *n = block->get_node(j);
 688       // Pre-color to the zero live range, or pick virtual register
 689       const RegMask &rm = n->out_RegMask();
 690       _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
 691     }
 692   }
 693 
 694   // Reset the Union-Find mapping to be identity
 695   _lrg_map.reset_uf_map(lr_counter);
 696 }
 697 
 698 void PhaseChaitin::mark_ssa() {
 699   // Use ssa names to populate the live range maps or if no mask
 700   // is available, use the 0 entry.
 701   uint max_idx = 0;
 702   for ( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
 703     Block* block = _cfg.get_block(i);
 704     uint cnt = block->number_of_nodes();
 705 
 706     // Handle all the normal Nodes in the block
 707     for ( uint j = 0; j < cnt; j++ ) {
 708       Node *n = block->get_node(j);
 709       // Pre-color to the zero live range, or pick virtual register
 710       const RegMask &rm = n->out_RegMask();
 711       _lrg_map.map(n->_idx, rm.is_NotEmpty() ? n->_idx : 0);
 712       max_idx = (n->_idx > max_idx) ? n->_idx : max_idx;
 713     }
 714   }
 715   _lrg_map.set_max_lrg_id(max_idx+1);
 716 
 717   // Reset the Union-Find mapping to be identity
 718   _lrg_map.reset_uf_map(max_idx+1);
 719 }
 720 
 721 
 722 // Gather LiveRanGe information, including register masks.  Modification of
 723 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
 724 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
 725 
 726   // Nail down the frame pointer live range
 727   uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr));
 728   lrgs(fp_lrg)._cost += 1e12;   // Cost is infinite
 729 
 730   // For all blocks
 731   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
 732     Block* block = _cfg.get_block(i);
 733 
 734     // For all instructions
 735     for (uint j = 1; j < block->number_of_nodes(); j++) {
 736       Node* n = block->get_node(j);
 737       uint input_edge_start =1; // Skip control most nodes
 738       bool is_machine_node = false;
 739       if (n->is_Mach()) {
 740         is_machine_node = true;
 741         input_edge_start = n->as_Mach()->oper_input_base();
 742       }
 743       uint idx = n->is_Copy();
 744 
 745       // Get virtual register number, same as LiveRanGe index
 746       uint vreg = _lrg_map.live_range_id(n);
 747       LRG& lrg = lrgs(vreg);
 748       if (vreg) {              // No vreg means un-allocable (e.g. memory)
 749 
 750         // Collect has-copy bit
 751         if (idx) {
 752           lrg._has_copy = 1;
 753           uint clidx = _lrg_map.live_range_id(n->in(idx));
 754           LRG& copy_src = lrgs(clidx);
 755           copy_src._has_copy = 1;
 756         }
 757 
 758         // Check for float-vs-int live range (used in register-pressure
 759         // calculations)
 760         const Type *n_type = n->bottom_type();
 761         if (n_type->is_floatingpoint()) {
 762           lrg._is_float = 1;
 763         }
 764 
 765         // Check for twice prior spilling.  Once prior spilling might have
 766         // spilled 'soft', 2nd prior spill should have spilled 'hard' and
 767         // further spilling is unlikely to make progress.
 768         if (_spilled_once.test(n->_idx)) {
 769           lrg._was_spilled1 = 1;
 770           if (_spilled_twice.test(n->_idx)) {
 771             lrg._was_spilled2 = 1;
 772           }
 773         }
 774 
 775 #ifndef PRODUCT
 776         if (trace_spilling() && lrg._def != NULL) {
 777           // collect defs for MultiDef printing
 778           if (lrg._defs == NULL) {
 779             lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
 780             lrg._defs->append(lrg._def);
 781           }
 782           lrg._defs->append(n);
 783         }
 784 #endif
 785 
 786         // Check for a single def LRG; these can spill nicely
 787         // via rematerialization.  Flag as NULL for no def found
 788         // yet, or 'n' for single def or -1 for many defs.
 789         lrg._def = lrg._def ? NodeSentinel : n;
 790 
 791         // Limit result register mask to acceptable registers
 792         const RegMask &rm = n->out_RegMask();
 793         lrg.AND( rm );
 794 
 795         int ireg = n->ideal_reg();
 796         assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
 797                 "oops must be in Op_RegP's" );
 798 
 799         // Check for vector live range (only if vector register is used).
 800         // On SPARC vector uses RegD which could be misaligned so it is not
 801         // processes as vector in RA.
 802         if (RegMask::is_vector(ireg))
 803           lrg._is_vector = 1;
 804         assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL,
 805                "vector must be in vector registers");
 806 
 807         // Check for bound register masks
 808         const RegMask &lrgmask = lrg.mask();
 809         if (lrgmask.is_bound(ireg)) {
 810           lrg._is_bound = 1;
 811         }
 812 
 813         // Check for maximum frequency value
 814         if (lrg._maxfreq < block->_freq) {
 815           lrg._maxfreq = block->_freq;
 816         }
 817 
 818         // Check for oop-iness, or long/double
 819         // Check for multi-kill projection
 820         switch (ireg) {
 821         case MachProjNode::fat_proj:
 822           // Fat projections have size equal to number of registers killed
 823           lrg.set_num_regs(rm.Size());
 824           lrg.set_reg_pressure(lrg.num_regs());
 825           lrg._fat_proj = 1;
 826           lrg._is_bound = 1;
 827           break;
 828         case Op_RegP:
 829 #ifdef _LP64
 830           lrg.set_num_regs(2);  // Size is 2 stack words
 831 #else
 832           lrg.set_num_regs(1);  // Size is 1 stack word
 833 #endif
 834           // Register pressure is tracked relative to the maximum values
 835           // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
 836           // and relative to other types which compete for the same regs.
 837           //
 838           // The following table contains suggested values based on the
 839           // architectures as defined in each .ad file.
 840           // INTPRESSURE and FLOATPRESSURE may be tuned differently for
 841           // compile-speed or performance.
 842           // Note1:
 843           // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
 844           // since .ad registers are defined as high and low halves.
 845           // These reg_pressure values remain compatible with the code
 846           // in is_high_pressure() which relates get_invalid_mask_size(),
 847           // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
 848           // Note2:
 849           // SPARC -d32 has 24 registers available for integral values,
 850           // but only 10 of these are safe for 64-bit longs.
 851           // Using set_reg_pressure(2) for both int and long means
 852           // the allocator will believe it can fit 26 longs into
 853           // registers.  Using 2 for longs and 1 for ints means the
 854           // allocator will attempt to put 52 integers into registers.
 855           // The settings below limit this problem to methods with
 856           // many long values which are being run on 32-bit SPARC.
 857           //
 858           // ------------------- reg_pressure --------------------
 859           // Each entry is reg_pressure_per_value,number_of_regs
 860           //         RegL  RegI  RegFlags   RegF RegD    INTPRESSURE  FLOATPRESSURE
 861           // IA32     2     1     1          1    1          6           6
 862           // IA64     1     1     1          1    1         50          41
 863           // SPARC    2     2     2          2    2         48 (24)     52 (26)
 864           // SPARCV9  2     2     2          2    2         48 (24)     52 (26)
 865           // AMD64    1     1     1          1    1         14          15
 866           // -----------------------------------------------------
 867 #if defined(SPARC)
 868           lrg.set_reg_pressure(2);  // use for v9 as well
 869 #else
 870           lrg.set_reg_pressure(1);  // normally one value per register
 871 #endif
 872           if( n_type->isa_oop_ptr() ) {
 873             lrg._is_oop = 1;
 874           }
 875           break;
 876         case Op_RegL:           // Check for long or double
 877         case Op_RegD:
 878           lrg.set_num_regs(2);
 879           // Define platform specific register pressure
 880 #if defined(SPARC) || defined(ARM32)
 881           lrg.set_reg_pressure(2);
 882 #elif defined(IA32)
 883           if( ireg == Op_RegL ) {
 884             lrg.set_reg_pressure(2);
 885           } else {
 886             lrg.set_reg_pressure(1);
 887           }
 888 #else
 889           lrg.set_reg_pressure(1);  // normally one value per register
 890 #endif
 891           // If this def of a double forces a mis-aligned double,
 892           // flag as '_fat_proj' - really flag as allowing misalignment
 893           // AND changes how we count interferences.  A mis-aligned
 894           // double can interfere with TWO aligned pairs, or effectively
 895           // FOUR registers!
 896           if (rm.is_misaligned_pair()) {
 897             lrg._fat_proj = 1;
 898             lrg._is_bound = 1;
 899           }
 900           break;
 901         case Op_RegF:
 902         case Op_RegI:
 903         case Op_RegN:
 904         case Op_RegFlags:
 905         case 0:                 // not an ideal register
 906           lrg.set_num_regs(1);
 907 #ifdef SPARC
 908           lrg.set_reg_pressure(2);
 909 #else
 910           lrg.set_reg_pressure(1);
 911 #endif
 912           break;
 913         case Op_VecS:
 914           assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
 915           assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
 916           lrg.set_num_regs(RegMask::SlotsPerVecS);
 917           lrg.set_reg_pressure(1);
 918           break;
 919         case Op_VecD:
 920           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
 921           assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
 922           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
 923           lrg.set_num_regs(RegMask::SlotsPerVecD);
 924           lrg.set_reg_pressure(1);
 925           break;
 926         case Op_VecX:
 927           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
 928           assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
 929           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
 930           lrg.set_num_regs(RegMask::SlotsPerVecX);
 931           lrg.set_reg_pressure(1);
 932           break;
 933         case Op_VecY:
 934           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
 935           assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
 936           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
 937           lrg.set_num_regs(RegMask::SlotsPerVecY);
 938           lrg.set_reg_pressure(1);
 939           break;
 940         case Op_VecZ:
 941           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity");
 942           assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
 943           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
 944           lrg.set_num_regs(RegMask::SlotsPerVecZ);
 945           lrg.set_reg_pressure(1);
 946           break;
 947         default:
 948           ShouldNotReachHere();
 949         }
 950       }
 951 
 952       // Now do the same for inputs
 953       uint cnt = n->req();
 954       // Setup for CISC SPILLING
 955       uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
 956       if( UseCISCSpill && after_aggressive ) {
 957         inp = n->cisc_operand();
 958         if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
 959           // Convert operand number to edge index number
 960           inp = n->as_Mach()->operand_index(inp);
 961       }
 962 
 963       // Prepare register mask for each input
 964       for( uint k = input_edge_start; k < cnt; k++ ) {
 965         uint vreg = _lrg_map.live_range_id(n->in(k));
 966         if (!vreg) {
 967           continue;
 968         }
 969 
 970         // If this instruction is CISC Spillable, add the flags
 971         // bit to its appropriate input
 972         if( UseCISCSpill && after_aggressive && inp == k ) {
 973 #ifndef PRODUCT
 974           if( TraceCISCSpill ) {
 975             tty->print("  use_cisc_RegMask: ");
 976             n->dump();
 977           }
 978 #endif
 979           n->as_Mach()->use_cisc_RegMask();
 980         }
 981 
 982         if (is_machine_node && _scheduling_info_generated) {
 983           MachNode* cur_node = n->as_Mach();
 984           // this is cleaned up by register allocation
 985           if (k >= cur_node->num_opnds()) continue;
 986         }
 987 
 988         LRG &lrg = lrgs(vreg);
 989         // // Testing for floating point code shape
 990         // Node *test = n->in(k);
 991         // if( test->is_Mach() ) {
 992         //   MachNode *m = test->as_Mach();
 993         //   int  op = m->ideal_Opcode();
 994         //   if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
 995         //     int zzz = 1;
 996         //   }
 997         // }
 998 
 999         // Limit result register mask to acceptable registers.
1000         // Do not limit registers from uncommon uses before
1001         // AggressiveCoalesce.  This effectively pre-virtual-splits
1002         // around uncommon uses of common defs.
1003         const RegMask &rm = n->in_RegMask(k);
1004         if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
1005           // Since we are BEFORE aggressive coalesce, leave the register
1006           // mask untrimmed by the call.  This encourages more coalescing.
1007           // Later, AFTER aggressive, this live range will have to spill
1008           // but the spiller handles slow-path calls very nicely.
1009         } else {
1010           lrg.AND( rm );
1011         }
1012 
1013         // Check for bound register masks
1014         const RegMask &lrgmask = lrg.mask();
1015         int kreg = n->in(k)->ideal_reg();
1016         bool is_vect = RegMask::is_vector(kreg);
1017         assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
1018                is_vect || kreg == Op_RegD || kreg == Op_RegL,
1019                "vector must be in vector registers");
1020         if (lrgmask.is_bound(kreg))
1021           lrg._is_bound = 1;
1022 
1023         // If this use of a double forces a mis-aligned double,
1024         // flag as '_fat_proj' - really flag as allowing misalignment
1025         // AND changes how we count interferences.  A mis-aligned
1026         // double can interfere with TWO aligned pairs, or effectively
1027         // FOUR registers!
1028 #ifdef ASSERT
1029         if (is_vect && !_scheduling_info_generated) {
1030           if (lrg.num_regs() != 0) {
1031             assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
1032             assert(!lrg._fat_proj, "sanity");
1033             assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
1034           } else {
1035             assert(n->is_Phi(), "not all inputs processed only if Phi");
1036           }
1037         }
1038 #endif
1039         if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
1040           lrg._fat_proj = 1;
1041           lrg._is_bound = 1;
1042         }
1043         // if the LRG is an unaligned pair, we will have to spill
1044         // so clear the LRG's register mask if it is not already spilled
1045         if (!is_vect && !n->is_SpillCopy() &&
1046             (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
1047             lrgmask.is_misaligned_pair()) {
1048           lrg.Clear();
1049         }
1050 
1051         // Check for maximum frequency value
1052         if (lrg._maxfreq < block->_freq) {
1053           lrg._maxfreq = block->_freq;
1054         }
1055 
1056       } // End for all allocated inputs
1057     } // end for all instructions
1058   } // end for all blocks
1059 
1060   // Final per-liverange setup
1061   for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) {
1062     LRG &lrg = lrgs(i2);
1063     assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
1064     if (lrg.num_regs() > 1 && !lrg._fat_proj) {
1065       lrg.clear_to_sets();
1066     }
1067     lrg.compute_set_mask_size();
1068     if (lrg.not_free()) {      // Handle case where we lose from the start
1069       lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
1070       lrg._direct_conflict = 1;
1071     }
1072     lrg.set_degree(0);          // no neighbors in IFG yet
1073   }
1074 }
1075 
1076 // Set the was-lo-degree bit.  Conservative coalescing should not change the
1077 // colorability of the graph.  If any live range was of low-degree before
1078 // coalescing, it should Simplify.  This call sets the was-lo-degree bit.
1079 // The bit is checked in Simplify.
1080 void PhaseChaitin::set_was_low() {
1081 #ifdef ASSERT
1082   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1083     int size = lrgs(i).num_regs();
1084     uint old_was_lo = lrgs(i)._was_lo;
1085     lrgs(i)._was_lo = 0;
1086     if( lrgs(i).lo_degree() ) {
1087       lrgs(i)._was_lo = 1;      // Trivially of low degree
1088     } else {                    // Else check the Brigg's assertion
1089       // Brigg's observation is that the lo-degree neighbors of a
1090       // hi-degree live range will not interfere with the color choices
1091       // of said hi-degree live range.  The Simplify reverse-stack-coloring
1092       // order takes care of the details.  Hence you do not have to count
1093       // low-degree neighbors when determining if this guy colors.
1094       int briggs_degree = 0;
1095       IndexSet *s = _ifg->neighbors(i);
1096       IndexSetIterator elements(s);
1097       uint lidx;
1098       while((lidx = elements.next()) != 0) {
1099         if( !lrgs(lidx).lo_degree() )
1100           briggs_degree += MAX2(size,lrgs(lidx).num_regs());
1101       }
1102       if( briggs_degree < lrgs(i).degrees_of_freedom() )
1103         lrgs(i)._was_lo = 1;    // Low degree via the briggs assertion
1104     }
1105     assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
1106   }
1107 #endif
1108 }
1109 
1110 #define REGISTER_CONSTRAINED 16
1111 
1112 // Compute cost/area ratio, in case we spill.  Build the lo-degree list.
1113 void PhaseChaitin::cache_lrg_info( ) {
1114   Compile::TracePhase tp("chaitinCacheLRG", &timers[_t_chaitinCacheLRG]);
1115 
1116   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1117     LRG &lrg = lrgs(i);
1118 
1119     // Check for being of low degree: means we can be trivially colored.
1120     // Low degree, dead or must-spill guys just get to simplify right away
1121     if( lrg.lo_degree() ||
1122        !lrg.alive() ||
1123         lrg._must_spill ) {
1124       // Split low degree list into those guys that must get a
1125       // register and those that can go to register or stack.
1126       // The idea is LRGs that can go register or stack color first when
1127       // they have a good chance of getting a register.  The register-only
1128       // lo-degree live ranges always get a register.
1129       OptoReg::Name hi_reg = lrg.mask().find_last_elem();
1130       if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
1131         lrg._next = _lo_stk_degree;
1132         _lo_stk_degree = i;
1133       } else {
1134         lrg._next = _lo_degree;
1135         _lo_degree = i;
1136       }
1137     } else {                    // Else high degree
1138       lrgs(_hi_degree)._prev = i;
1139       lrg._next = _hi_degree;
1140       lrg._prev = 0;
1141       _hi_degree = i;
1142     }
1143   }
1144 }
1145 
1146 // Simplify the IFG by removing LRGs of low degree that have NO copies
1147 void PhaseChaitin::Pre_Simplify( ) {
1148 
1149   // Warm up the lo-degree no-copy list
1150   int lo_no_copy = 0;
1151   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1152     if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
1153         !lrgs(i).alive() ||
1154         lrgs(i)._must_spill) {
1155       lrgs(i)._next = lo_no_copy;
1156       lo_no_copy = i;
1157     }
1158   }
1159 
1160   while( lo_no_copy ) {
1161     uint lo = lo_no_copy;
1162     lo_no_copy = lrgs(lo)._next;
1163     int size = lrgs(lo).num_regs();
1164 
1165     // Put the simplified guy on the simplified list.
1166     lrgs(lo)._next = _simplified;
1167     _simplified = lo;
1168 
1169     // Yank this guy from the IFG.
1170     IndexSet *adj = _ifg->remove_node( lo );
1171 
1172     // If any neighbors' degrees fall below their number of
1173     // allowed registers, then put that neighbor on the low degree
1174     // list.  Note that 'degree' can only fall and 'numregs' is
1175     // unchanged by this action.  Thus the two are equal at most once,
1176     // so LRGs hit the lo-degree worklists at most once.
1177     IndexSetIterator elements(adj);
1178     uint neighbor;
1179     while ((neighbor = elements.next()) != 0) {
1180       LRG *n = &lrgs(neighbor);
1181       assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1182 
1183       // Check for just becoming of-low-degree
1184       if( n->just_lo_degree() && !n->_has_copy ) {
1185         assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1186         // Put on lo-degree list
1187         n->_next = lo_no_copy;
1188         lo_no_copy = neighbor;
1189       }
1190     }
1191   } // End of while lo-degree no_copy worklist not empty
1192 
1193   // No more lo-degree no-copy live ranges to simplify
1194 }
1195 
1196 // Simplify the IFG by removing LRGs of low degree.
1197 void PhaseChaitin::Simplify( ) {
1198   Compile::TracePhase tp("chaitinSimplify", &timers[_t_chaitinSimplify]);
1199 
1200   while( 1 ) {                  // Repeat till simplified it all
1201     // May want to explore simplifying lo_degree before _lo_stk_degree.
1202     // This might result in more spills coloring into registers during
1203     // Select().
1204     while( _lo_degree || _lo_stk_degree ) {
1205       // If possible, pull from lo_stk first
1206       uint lo;
1207       if( _lo_degree ) {
1208         lo = _lo_degree;
1209         _lo_degree = lrgs(lo)._next;
1210       } else {
1211         lo = _lo_stk_degree;
1212         _lo_stk_degree = lrgs(lo)._next;
1213       }
1214 
1215       // Put the simplified guy on the simplified list.
1216       lrgs(lo)._next = _simplified;
1217       _simplified = lo;
1218       // If this guy is "at risk" then mark his current neighbors
1219       if( lrgs(lo)._at_risk ) {
1220         IndexSetIterator elements(_ifg->neighbors(lo));
1221         uint datum;
1222         while ((datum = elements.next()) != 0) {
1223           lrgs(datum)._risk_bias = lo;
1224         }
1225       }
1226 
1227       // Yank this guy from the IFG.
1228       IndexSet *adj = _ifg->remove_node( lo );
1229 
1230       // If any neighbors' degrees fall below their number of
1231       // allowed registers, then put that neighbor on the low degree
1232       // list.  Note that 'degree' can only fall and 'numregs' is
1233       // unchanged by this action.  Thus the two are equal at most once,
1234       // so LRGs hit the lo-degree worklist at most once.
1235       IndexSetIterator elements(adj);
1236       uint neighbor;
1237       while ((neighbor = elements.next()) != 0) {
1238         LRG *n = &lrgs(neighbor);
1239 #ifdef ASSERT
1240         if( VerifyOpto || VerifyRegisterAllocator ) {
1241           assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1242         }
1243 #endif
1244 
1245         // Check for just becoming of-low-degree just counting registers.
1246         // _must_spill live ranges are already on the low degree list.
1247         if( n->just_lo_degree() && !n->_must_spill ) {
1248           assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1249           // Pull from hi-degree list
1250           uint prev = n->_prev;
1251           uint next = n->_next;
1252           if( prev ) lrgs(prev)._next = next;
1253           else _hi_degree = next;
1254           lrgs(next)._prev = prev;
1255           n->_next = _lo_degree;
1256           _lo_degree = neighbor;
1257         }
1258       }
1259     } // End of while lo-degree/lo_stk_degree worklist not empty
1260 
1261     // Check for got everything: is hi-degree list empty?
1262     if( !_hi_degree ) break;
1263 
1264     // Time to pick a potential spill guy
1265     uint lo_score = _hi_degree;
1266     double score = lrgs(lo_score).score();
1267     double area = lrgs(lo_score)._area;
1268     double cost = lrgs(lo_score)._cost;
1269     bool bound = lrgs(lo_score)._is_bound;
1270 
1271     // Find cheapest guy
1272     debug_only( int lo_no_simplify=0; );
1273     for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
1274       assert( !(*_ifg->_yanked)[i], "" );
1275       // It's just vaguely possible to move hi-degree to lo-degree without
1276       // going through a just-lo-degree stage: If you remove a double from
1277       // a float live range it's degree will drop by 2 and you can skip the
1278       // just-lo-degree stage.  It's very rare (shows up after 5000+ methods
1279       // in -Xcomp of Java2Demo).  So just choose this guy to simplify next.
1280       if( lrgs(i).lo_degree() ) {
1281         lo_score = i;
1282         break;
1283       }
1284       debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
1285       double iscore = lrgs(i).score();
1286       double iarea = lrgs(i)._area;
1287       double icost = lrgs(i)._cost;
1288       bool ibound = lrgs(i)._is_bound;
1289 
1290       // Compare cost/area of i vs cost/area of lo_score.  Smaller cost/area
1291       // wins.  Ties happen because all live ranges in question have spilled
1292       // a few times before and the spill-score adds a huge number which
1293       // washes out the low order bits.  We are choosing the lesser of 2
1294       // evils; in this case pick largest area to spill.
1295       // Ties also happen when live ranges are defined and used only inside
1296       // one block. In which case their area is 0 and score set to max.
1297       // In such case choose bound live range over unbound to free registers
1298       // or with smaller cost to spill.
1299       if( iscore < score ||
1300           (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ||
1301           (iscore == score && iarea == area &&
1302            ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) {
1303         lo_score = i;
1304         score = iscore;
1305         area = iarea;
1306         cost = icost;
1307         bound = ibound;
1308       }
1309     }
1310     LRG *lo_lrg = &lrgs(lo_score);
1311     // The live range we choose for spilling is either hi-degree, or very
1312     // rarely it can be low-degree.  If we choose a hi-degree live range
1313     // there better not be any lo-degree choices.
1314     assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
1315 
1316     // Pull from hi-degree list
1317     uint prev = lo_lrg->_prev;
1318     uint next = lo_lrg->_next;
1319     if( prev ) lrgs(prev)._next = next;
1320     else _hi_degree = next;
1321     lrgs(next)._prev = prev;
1322     // Jam him on the lo-degree list, despite his high degree.
1323     // Maybe he'll get a color, and maybe he'll spill.
1324     // Only Select() will know.
1325     lrgs(lo_score)._at_risk = true;
1326     _lo_degree = lo_score;
1327     lo_lrg->_next = 0;
1328 
1329   } // End of while not simplified everything
1330 
1331 }
1332 
1333 // Is 'reg' register legal for 'lrg'?
1334 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
1335   if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
1336       lrg.mask().Member(OptoReg::add(reg,-chunk))) {
1337     // RA uses OptoReg which represent the highest element of a registers set.
1338     // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set
1339     // in which XMMd is used by RA to represent such vectors. A double value
1340     // uses [XMM,XMMb] pairs and XMMb is used by RA for it.
1341     // The register mask uses largest bits set of overlapping register sets.
1342     // On x86 with AVX it uses 8 bits for each XMM registers set.
1343     //
1344     // The 'lrg' already has cleared-to-set register mask (done in Select()
1345     // before calling choose_color()). Passing mask.Member(reg) check above
1346     // indicates that the size (num_regs) of 'reg' set is less or equal to
1347     // 'lrg' set size.
1348     // For set size 1 any register which is member of 'lrg' mask is legal.
1349     if (lrg.num_regs()==1)
1350       return true;
1351     // For larger sets only an aligned register with the same set size is legal.
1352     int mask = lrg.num_regs()-1;
1353     if ((reg&mask) == mask)
1354       return true;
1355   }
1356   return false;
1357 }
1358 
1359 // Choose a color using the biasing heuristic
1360 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1361 
1362   // Check for "at_risk" LRG's
1363   uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1364   if( risk_lrg != 0 ) {
1365     // Walk the colored neighbors of the "at_risk" candidate
1366     // Choose a color which is both legal and already taken by a neighbor
1367     // of the "at_risk" candidate in order to improve the chances of the
1368     // "at_risk" candidate of coloring
1369     IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1370     uint datum;
1371     while ((datum = elements.next()) != 0) {
1372       OptoReg::Name reg = lrgs(datum).reg();
1373       // If this LRG's register is legal for us, choose it
1374       if (is_legal_reg(lrg, reg, chunk))
1375         return reg;
1376     }
1377   }
1378 
1379   uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1380   if( copy_lrg != 0 ) {
1381     // If he has a color,
1382     if( !(*(_ifg->_yanked))[copy_lrg] ) {
1383       OptoReg::Name reg = lrgs(copy_lrg).reg();
1384       //  And it is legal for you,
1385       if (is_legal_reg(lrg, reg, chunk))
1386         return reg;
1387     } else if( chunk == 0 ) {
1388       // Choose a color which is legal for him
1389       RegMask tempmask = lrg.mask();
1390       tempmask.AND(lrgs(copy_lrg).mask());
1391       tempmask.clear_to_sets(lrg.num_regs());
1392       OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
1393       if (OptoReg::is_valid(reg))
1394         return reg;
1395     }
1396   }
1397 
1398   // If no bias info exists, just go with the register selection ordering
1399   if (lrg._is_vector || lrg.num_regs() == 2) {
1400     // Find an aligned set
1401     return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1402   }
1403 
1404   // CNC - Fun hack.  Alternate 1st and 2nd selection.  Enables post-allocate
1405   // copy removal to remove many more copies, by preventing a just-assigned
1406   // register from being repeatedly assigned.
1407   OptoReg::Name reg = lrg.mask().find_first_elem();
1408   if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1409     // This 'Remove; find; Insert' idiom is an expensive way to find the
1410     // SECOND element in the mask.
1411     lrg.Remove(reg);
1412     OptoReg::Name reg2 = lrg.mask().find_first_elem();
1413     lrg.Insert(reg);
1414     if( OptoReg::is_reg(reg2))
1415       reg = reg2;
1416   }
1417   return OptoReg::add( reg, chunk );
1418 }
1419 
1420 // Choose a color in the current chunk
1421 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1422   assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1423   assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1424 
1425   if( lrg.num_regs() == 1 ||    // Common Case
1426       !lrg._fat_proj )          // Aligned+adjacent pairs ok
1427     // Use a heuristic to "bias" the color choice
1428     return bias_color(lrg, chunk);
1429 
1430   assert(!lrg._is_vector, "should be not vector here" );
1431   assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1432 
1433   // Fat-proj case or misaligned double argument.
1434   assert(lrg.compute_mask_size() == lrg.num_regs() ||
1435          lrg.num_regs() == 2,"fat projs exactly color" );
1436   assert( !chunk, "always color in 1st chunk" );
1437   // Return the highest element in the set.
1438   return lrg.mask().find_last_elem();
1439 }
1440 
1441 // Select colors by re-inserting LRGs back into the IFG.  LRGs are re-inserted
1442 // in reverse order of removal.  As long as nothing of hi-degree was yanked,
1443 // everything going back is guaranteed a color.  Select that color.  If some
1444 // hi-degree LRG cannot get a color then we record that we must spill.
1445 uint PhaseChaitin::Select( ) {
1446   Compile::TracePhase tp("chaitinSelect", &timers[_t_chaitinSelect]);
1447 
1448   uint spill_reg = LRG::SPILL_REG;
1449   _max_reg = OptoReg::Name(0);  // Past max register used
1450   while( _simplified ) {
1451     // Pull next LRG from the simplified list - in reverse order of removal
1452     uint lidx = _simplified;
1453     LRG *lrg = &lrgs(lidx);
1454     _simplified = lrg->_next;
1455 
1456 
1457 #ifndef PRODUCT
1458     if (trace_spilling()) {
1459       ttyLocker ttyl;
1460       tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1461                     lrg->degrees_of_freedom());
1462       lrg->dump();
1463     }
1464 #endif
1465 
1466     // Re-insert into the IFG
1467     _ifg->re_insert(lidx);
1468     if( !lrg->alive() ) continue;
1469     // capture allstackedness flag before mask is hacked
1470     const int is_allstack = lrg->mask().is_AllStack();
1471 
1472     // Yeah, yeah, yeah, I know, I know.  I can refactor this
1473     // to avoid the GOTO, although the refactored code will not
1474     // be much clearer.  We arrive here IFF we have a stack-based
1475     // live range that cannot color in the current chunk, and it
1476     // has to move into the next free stack chunk.
1477     int chunk = 0;              // Current chunk is first chunk
1478     retry_next_chunk:
1479 
1480     // Remove neighbor colors
1481     IndexSet *s = _ifg->neighbors(lidx);
1482 
1483     debug_only(RegMask orig_mask = lrg->mask();)
1484     IndexSetIterator elements(s);
1485     uint neighbor;
1486     while ((neighbor = elements.next()) != 0) {
1487       // Note that neighbor might be a spill_reg.  In this case, exclusion
1488       // of its color will be a no-op, since the spill_reg chunk is in outer
1489       // space.  Also, if neighbor is in a different chunk, this exclusion
1490       // will be a no-op.  (Later on, if lrg runs out of possible colors in
1491       // its chunk, a new chunk of color may be tried, in which case
1492       // examination of neighbors is started again, at retry_next_chunk.)
1493       LRG &nlrg = lrgs(neighbor);
1494       OptoReg::Name nreg = nlrg.reg();
1495       // Only subtract masks in the same chunk
1496       if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
1497 #ifndef PRODUCT
1498         uint size = lrg->mask().Size();
1499         RegMask rm = lrg->mask();
1500 #endif
1501         lrg->SUBTRACT(nlrg.mask());
1502 #ifndef PRODUCT
1503         if (trace_spilling() && lrg->mask().Size() != size) {
1504           ttyLocker ttyl;
1505           tty->print("L%d ", lidx);
1506           rm.dump();
1507           tty->print(" intersected L%d ", neighbor);
1508           nlrg.mask().dump();
1509           tty->print(" removed ");
1510           rm.SUBTRACT(lrg->mask());
1511           rm.dump();
1512           tty->print(" leaving ");
1513           lrg->mask().dump();
1514           tty->cr();
1515         }
1516 #endif
1517       }
1518     }
1519     //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1520     // Aligned pairs need aligned masks
1521     assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1522     if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1523       lrg->clear_to_sets();
1524     }
1525 
1526     // Check if a color is available and if so pick the color
1527     OptoReg::Name reg = choose_color( *lrg, chunk );
1528 #ifdef SPARC
1529     debug_only(lrg->compute_set_mask_size());
1530     assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1531 #endif
1532 
1533     //---------------
1534     // If we fail to color and the AllStack flag is set, trigger
1535     // a chunk-rollover event
1536     if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1537       // Bump register mask up to next stack chunk
1538       chunk += RegMask::CHUNK_SIZE;
1539       lrg->Set_All();
1540 
1541       goto retry_next_chunk;
1542     }
1543 
1544     //---------------
1545     // Did we get a color?
1546     else if( OptoReg::is_valid(reg)) {
1547 #ifndef PRODUCT
1548       RegMask avail_rm = lrg->mask();
1549 #endif
1550 
1551       // Record selected register
1552       lrg->set_reg(reg);
1553 
1554       if( reg >= _max_reg )     // Compute max register limit
1555         _max_reg = OptoReg::add(reg,1);
1556       // Fold reg back into normal space
1557       reg = OptoReg::add(reg,-chunk);
1558 
1559       // If the live range is not bound, then we actually had some choices
1560       // to make.  In this case, the mask has more bits in it than the colors
1561       // chosen.  Restrict the mask to just what was picked.
1562       int n_regs = lrg->num_regs();
1563       assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1564       if (n_regs == 1 || !lrg->_fat_proj) {
1565         assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity");
1566         lrg->Clear();           // Clear the mask
1567         lrg->Insert(reg);       // Set regmask to match selected reg
1568         // For vectors and pairs, also insert the low bit of the pair
1569         for (int i = 1; i < n_regs; i++)
1570           lrg->Insert(OptoReg::add(reg,-i));
1571         lrg->set_mask_size(n_regs);
1572       } else {                  // Else fatproj
1573         // mask must be equal to fatproj bits, by definition
1574       }
1575 #ifndef PRODUCT
1576       if (trace_spilling()) {
1577         ttyLocker ttyl;
1578         tty->print("L%d selected ", lidx);
1579         lrg->mask().dump();
1580         tty->print(" from ");
1581         avail_rm.dump();
1582         tty->cr();
1583       }
1584 #endif
1585       // Note that reg is the highest-numbered register in the newly-bound mask.
1586     } // end color available case
1587 
1588     //---------------
1589     // Live range is live and no colors available
1590     else {
1591       assert( lrg->alive(), "" );
1592       assert( !lrg->_fat_proj || lrg->is_multidef() ||
1593               lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1594       assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
1595 
1596       // Assign the special spillreg register
1597       lrg->set_reg(OptoReg::Name(spill_reg++));
1598       // Do not empty the regmask; leave mask_size lying around
1599       // for use during Spilling
1600 #ifndef PRODUCT
1601       if( trace_spilling() ) {
1602         ttyLocker ttyl;
1603         tty->print("L%d spilling with neighbors: ", lidx);
1604         s->dump();
1605         debug_only(tty->print(" original mask: "));
1606         debug_only(orig_mask.dump());
1607         dump_lrg(lidx);
1608       }
1609 #endif
1610     } // end spill case
1611 
1612   }
1613 
1614   return spill_reg-LRG::SPILL_REG;      // Return number of spills
1615 }
1616 
1617 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1618 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1619   if( _spilled_once.test(src->_idx) ) {
1620     _spilled_once.set(dst->_idx);
1621     lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
1622     if( _spilled_twice.test(src->_idx) ) {
1623       _spilled_twice.set(dst->_idx);
1624       lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
1625     }
1626   }
1627 }
1628 
1629 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1630 void PhaseChaitin::set_was_spilled( Node *n ) {
1631   if( _spilled_once.test_set(n->_idx) )
1632     _spilled_twice.set(n->_idx);
1633 }
1634 
1635 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1636 // Stores.  Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1637 void PhaseChaitin::fixup_spills() {
1638   // This function does only cisc spill work.
1639   if( !UseCISCSpill ) return;
1640 
1641   Compile::TracePhase tp("fixupSpills", &timers[_t_fixupSpills]);
1642 
1643   // Grab the Frame Pointer
1644   Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr);
1645 
1646   // For all blocks
1647   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1648     Block* block = _cfg.get_block(i);
1649 
1650     // For all instructions in block
1651     uint last_inst = block->end_idx();
1652     for (uint j = 1; j <= last_inst; j++) {
1653       Node* n = block->get_node(j);
1654 
1655       // Dead instruction???
1656       assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1657               C->top() == n ||  // Or the random TOP node
1658               n->is_Proj(),     // Or a fat-proj kill node
1659               "No dead instructions after post-alloc" );
1660 
1661       int inp = n->cisc_operand();
1662       if( inp != AdlcVMDeps::Not_cisc_spillable ) {
1663         // Convert operand number to edge index number
1664         MachNode *mach = n->as_Mach();
1665         inp = mach->operand_index(inp);
1666         Node *src = n->in(inp);   // Value to load or store
1667         LRG &lrg_cisc = lrgs(_lrg_map.find_const(src));
1668         OptoReg::Name src_reg = lrg_cisc.reg();
1669         // Doubles record the HIGH register of an adjacent pair.
1670         src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
1671         if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1672           // This is a CISC Spill, get stack offset and construct new node
1673 #ifndef PRODUCT
1674           if( TraceCISCSpill ) {
1675             tty->print("    reg-instr:  ");
1676             n->dump();
1677           }
1678 #endif
1679           int stk_offset = reg2offset(src_reg);
1680           // Bailout if we might exceed node limit when spilling this instruction
1681           C->check_node_count(0, "out of nodes fixing spills");
1682           if (C->failing())  return;
1683           // Transform node
1684           MachNode *cisc = mach->cisc_version(stk_offset)->as_Mach();
1685           cisc->set_req(inp,fp);          // Base register is frame pointer
1686           if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1687             assert( cisc->oper_input_base() == 2, "Only adding one edge");
1688             cisc->ins_req(1,src);         // Requires a memory edge
1689           }
1690           block->map_node(cisc, j);          // Insert into basic block
1691           n->subsume_by(cisc, C); // Correct graph
1692           //
1693           ++_used_cisc_instructions;
1694 #ifndef PRODUCT
1695           if( TraceCISCSpill ) {
1696             tty->print("    cisc-instr: ");
1697             cisc->dump();
1698           }
1699 #endif
1700         } else {
1701 #ifndef PRODUCT
1702           if( TraceCISCSpill ) {
1703             tty->print("    using reg-instr: ");
1704             n->dump();
1705           }
1706 #endif
1707           ++_unused_cisc_instructions;    // input can be on stack
1708         }
1709       }
1710 
1711     } // End of for all instructions
1712 
1713   } // End of for all blocks
1714 }
1715 
1716 // Helper to stretch above; recursively discover the base Node for a
1717 // given derived Node.  Easy for AddP-related machine nodes, but needs
1718 // to be recursive for derived Phis.
1719 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
1720   // See if already computed; if so return it
1721   if( derived_base_map[derived->_idx] )
1722     return derived_base_map[derived->_idx];
1723 
1724   // See if this happens to be a base.
1725   // NOTE: we use TypePtr instead of TypeOopPtr because we can have
1726   // pointers derived from NULL!  These are always along paths that
1727   // can't happen at run-time but the optimizer cannot deduce it so
1728   // we have to handle it gracefully.
1729   assert(!derived->bottom_type()->isa_narrowoop() ||
1730           derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1731   const TypePtr *tj = derived->bottom_type()->isa_ptr();
1732   // If its an OOP with a non-zero offset, then it is derived.
1733   if( tj == NULL || tj->_offset == 0 ) {
1734     derived_base_map[derived->_idx] = derived;
1735     return derived;
1736   }
1737   // Derived is NULL+offset?  Base is NULL!
1738   if( derived->is_Con() ) {
1739     Node *base = _matcher.mach_null();
1740     assert(base != NULL, "sanity");
1741     if (base->in(0) == NULL) {
1742       // Initialize it once and make it shared:
1743       // set control to _root and place it into Start block
1744       // (where top() node is placed).
1745       base->init_req(0, _cfg.get_root_node());
1746       Block *startb = _cfg.get_block_for_node(C->top());
1747       uint node_pos = startb->find_node(C->top());
1748       startb->insert_node(base, node_pos);
1749       _cfg.map_node_to_block(base, startb);
1750       assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1751 
1752       // The loadConP0 might have projection nodes depending on architecture
1753       // Add the projection nodes to the CFG
1754       for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) {
1755         Node* use = base->fast_out(i);
1756         if (use->is_MachProj()) {
1757           startb->insert_node(use, ++node_pos);
1758           _cfg.map_node_to_block(use, startb);
1759           new_lrg(use, maxlrg++);
1760         }
1761       }
1762     }
1763     if (_lrg_map.live_range_id(base) == 0) {
1764       new_lrg(base, maxlrg++);
1765     }
1766     assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1767     derived_base_map[derived->_idx] = base;
1768     return base;
1769   }
1770 
1771   // Check for AddP-related opcodes
1772   if (!derived->is_Phi()) {
1773     assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name()));
1774     Node *base = derived->in(AddPNode::Base);
1775     derived_base_map[derived->_idx] = base;
1776     return base;
1777   }
1778 
1779   // Recursively find bases for Phis.
1780   // First check to see if we can avoid a base Phi here.
1781   Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1782   uint i;
1783   for( i = 2; i < derived->req(); i++ )
1784     if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1785       break;
1786   // Went to the end without finding any different bases?
1787   if( i == derived->req() ) {   // No need for a base Phi here
1788     derived_base_map[derived->_idx] = base;
1789     return base;
1790   }
1791 
1792   // Now we see we need a base-Phi here to merge the bases
1793   const Type *t = base->bottom_type();
1794   base = new PhiNode( derived->in(0), t );
1795   for( i = 1; i < derived->req(); i++ ) {
1796     base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1797     t = t->meet(base->in(i)->bottom_type());
1798   }
1799   base->as_Phi()->set_type(t);
1800 
1801   // Search the current block for an existing base-Phi
1802   Block *b = _cfg.get_block_for_node(derived);
1803   for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1804     Node *phi = b->get_node(i);
1805     if( !phi->is_Phi() ) {      // Found end of Phis with no match?
1806       b->insert_node(base,  i); // Must insert created Phi here as base
1807       _cfg.map_node_to_block(base, b);
1808       new_lrg(base,maxlrg++);
1809       break;
1810     }
1811     // See if Phi matches.
1812     uint j;
1813     for( j = 1; j < base->req(); j++ )
1814       if( phi->in(j) != base->in(j) &&
1815           !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1816         break;
1817     if( j == base->req() ) {    // All inputs match?
1818       base = phi;               // Then use existing 'phi' and drop 'base'
1819       break;
1820     }
1821   }
1822 
1823 
1824   // Cache info for later passes
1825   derived_base_map[derived->_idx] = base;
1826   return base;
1827 }
1828 
1829 // At each Safepoint, insert extra debug edges for each pair of derived value/
1830 // base pointer that is live across the Safepoint for oopmap building.  The
1831 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1832 // required edge set.
1833 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) {
1834   int must_recompute_live = false;
1835   uint maxlrg = _lrg_map.max_lrg_id();
1836   Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
1837   memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1838 
1839   // For all blocks in RPO do...
1840   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1841     Block* block = _cfg.get_block(i);
1842     // Note use of deep-copy constructor.  I cannot hammer the original
1843     // liveout bits, because they are needed by the following coalesce pass.
1844     IndexSet liveout(_live->live(block));
1845 
1846     for (uint j = block->end_idx() + 1; j > 1; j--) {
1847       Node* n = block->get_node(j - 1);
1848 
1849       // Pre-split compares of loop-phis.  Loop-phis form a cycle we would
1850       // like to see in the same register.  Compare uses the loop-phi and so
1851       // extends its live range BUT cannot be part of the cycle.  If this
1852       // extended live range overlaps with the update of the loop-phi value
1853       // we need both alive at the same time -- which requires at least 1
1854       // copy.  But because Intel has only 2-address registers we end up with
1855       // at least 2 copies, one before the loop-phi update instruction and
1856       // one after.  Instead we split the input to the compare just after the
1857       // phi.
1858       if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1859         Node *phi = n->in(1);
1860         if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1861           Block *phi_block = _cfg.get_block_for_node(phi);
1862           if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1863             const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1864             Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask);
1865             insert_proj( phi_block, 1, spill, maxlrg++ );
1866             n->set_req(1,spill);
1867             must_recompute_live = true;
1868           }
1869         }
1870       }
1871 
1872       // Get value being defined
1873       uint lidx = _lrg_map.live_range_id(n);
1874       // Ignore the occasional brand-new live range
1875       if (lidx && lidx < _lrg_map.max_lrg_id()) {
1876         // Remove from live-out set
1877         liveout.remove(lidx);
1878 
1879         // Copies do not define a new value and so do not interfere.
1880         // Remove the copies source from the liveout set before interfering.
1881         uint idx = n->is_Copy();
1882         if (idx) {
1883           liveout.remove(_lrg_map.live_range_id(n->in(idx)));
1884         }
1885       }
1886 
1887       // Found a safepoint?
1888       JVMState *jvms = n->jvms();
1889       if( jvms ) {
1890         // Now scan for a live derived pointer
1891         IndexSetIterator elements(&liveout);
1892         uint neighbor;
1893         while ((neighbor = elements.next()) != 0) {
1894           // Find reaching DEF for base and derived values
1895           // This works because we are still in SSA during this call.
1896           Node *derived = lrgs(neighbor)._def;
1897           const TypePtr *tj = derived->bottom_type()->isa_ptr();
1898           assert(!derived->bottom_type()->isa_narrowoop() ||
1899                   derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1900           // If its an OOP with a non-zero offset, then it is derived.
1901           if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1902             Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
1903             assert(base->_idx < _lrg_map.size(), "");
1904             // Add reaching DEFs of derived pointer and base pointer as a
1905             // pair of inputs
1906             n->add_req(derived);
1907             n->add_req(base);
1908 
1909             // See if the base pointer is already live to this point.
1910             // Since I'm working on the SSA form, live-ness amounts to
1911             // reaching def's.  So if I find the base's live range then
1912             // I know the base's def reaches here.
1913             if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1914                  !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1915                  (_lrg_map.live_range_id(base) > 0) && // not a constant
1916                  _cfg.get_block_for_node(base) != block) { // base not def'd in blk)
1917               // Base pointer is not currently live.  Since I stretched
1918               // the base pointer to here and it crosses basic-block
1919               // boundaries, the global live info is now incorrect.
1920               // Recompute live.
1921               must_recompute_live = true;
1922             } // End of if base pointer is not live to debug info
1923           }
1924         } // End of scan all live data for derived ptrs crossing GC point
1925       } // End of if found a GC point
1926 
1927       // Make all inputs live
1928       if (!n->is_Phi()) {      // Phi function uses come from prior block
1929         for (uint k = 1; k < n->req(); k++) {
1930           uint lidx = _lrg_map.live_range_id(n->in(k));
1931           if (lidx < _lrg_map.max_lrg_id()) {
1932             liveout.insert(lidx);
1933           }
1934         }
1935       }
1936 
1937     } // End of forall instructions in block
1938     liveout.clear();  // Free the memory used by liveout.
1939 
1940   } // End of forall blocks
1941   _lrg_map.set_max_lrg_id(maxlrg);
1942 
1943   // If I created a new live range I need to recompute live
1944   if (maxlrg != _ifg->_maxlrg) {
1945     must_recompute_live = true;
1946   }
1947 
1948   return must_recompute_live != 0;
1949 }
1950 
1951 // Extend the node to LRG mapping
1952 
1953 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1954   _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1955 }
1956 
1957 #ifndef PRODUCT
1958 void PhaseChaitin::dump(const Node *n) const {
1959   uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1960   tty->print("L%d",r);
1961   if (r && n->Opcode() != Op_Phi) {
1962     if( _node_regs ) {          // Got a post-allocation copy of allocation?
1963       tty->print("[");
1964       OptoReg::Name second = get_reg_second(n);
1965       if( OptoReg::is_valid(second) ) {
1966         if( OptoReg::is_reg(second) )
1967           tty->print("%s:",Matcher::regName[second]);
1968         else
1969           tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1970       }
1971       OptoReg::Name first = get_reg_first(n);
1972       if( OptoReg::is_reg(first) )
1973         tty->print("%s]",Matcher::regName[first]);
1974       else
1975          tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1976     } else
1977     n->out_RegMask().dump();
1978   }
1979   tty->print("/N%d\t",n->_idx);
1980   tty->print("%s === ", n->Name());
1981   uint k;
1982   for (k = 0; k < n->req(); k++) {
1983     Node *m = n->in(k);
1984     if (!m) {
1985       tty->print("_ ");
1986     }
1987     else {
1988       uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1989       tty->print("L%d",r);
1990       // Data MultiNode's can have projections with no real registers.
1991       // Don't die while dumping them.
1992       int op = n->Opcode();
1993       if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1994         if( _node_regs ) {
1995           tty->print("[");
1996           OptoReg::Name second = get_reg_second(n->in(k));
1997           if( OptoReg::is_valid(second) ) {
1998             if( OptoReg::is_reg(second) )
1999               tty->print("%s:",Matcher::regName[second]);
2000             else
2001               tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
2002                          reg2offset_unchecked(second));
2003           }
2004           OptoReg::Name first = get_reg_first(n->in(k));
2005           if( OptoReg::is_reg(first) )
2006             tty->print("%s]",Matcher::regName[first]);
2007           else
2008             tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
2009                        reg2offset_unchecked(first));
2010         } else
2011           n->in_RegMask(k).dump();
2012       }
2013       tty->print("/N%d ",m->_idx);
2014     }
2015   }
2016   if( k < n->len() && n->in(k) ) tty->print("| ");
2017   for( ; k < n->len(); k++ ) {
2018     Node *m = n->in(k);
2019     if(!m) {
2020       break;
2021     }
2022     uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
2023     tty->print("L%d",r);
2024     tty->print("/N%d ",m->_idx);
2025   }
2026   if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
2027   else n->dump_spec(tty);
2028   if( _spilled_once.test(n->_idx ) ) {
2029     tty->print(" Spill_1");
2030     if( _spilled_twice.test(n->_idx ) )
2031       tty->print(" Spill_2");
2032   }
2033   tty->print("\n");
2034 }
2035 
2036 void PhaseChaitin::dump(const Block *b) const {
2037   b->dump_head(&_cfg);
2038 
2039   // For all instructions
2040   for( uint j = 0; j < b->number_of_nodes(); j++ )
2041     dump(b->get_node(j));
2042   // Print live-out info at end of block
2043   if( _live ) {
2044     tty->print("Liveout: ");
2045     IndexSet *live = _live->live(b);
2046     IndexSetIterator elements(live);
2047     tty->print("{");
2048     uint i;
2049     while ((i = elements.next()) != 0) {
2050       tty->print("L%d ", _lrg_map.find_const(i));
2051     }
2052     tty->print_cr("}");
2053   }
2054   tty->print("\n");
2055 }
2056 
2057 void PhaseChaitin::dump() const {
2058   tty->print( "--- Chaitin -- argsize: %d  framesize: %d ---\n",
2059               _matcher._new_SP, _framesize );
2060 
2061   // For all blocks
2062   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2063     dump(_cfg.get_block(i));
2064   }
2065   // End of per-block dump
2066   tty->print("\n");
2067 
2068   if (!_ifg) {
2069     tty->print("(No IFG.)\n");
2070     return;
2071   }
2072 
2073   // Dump LRG array
2074   tty->print("--- Live RanGe Array ---\n");
2075   for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) {
2076     tty->print("L%d: ",i2);
2077     if (i2 < _ifg->_maxlrg) {
2078       lrgs(i2).dump();
2079     }
2080     else {
2081       tty->print_cr("new LRG");
2082     }
2083   }
2084   tty->cr();
2085 
2086   // Dump lo-degree list
2087   tty->print("Lo degree: ");
2088   for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
2089     tty->print("L%d ",i3);
2090   tty->cr();
2091 
2092   // Dump lo-stk-degree list
2093   tty->print("Lo stk degree: ");
2094   for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
2095     tty->print("L%d ",i4);
2096   tty->cr();
2097 
2098   // Dump lo-degree list
2099   tty->print("Hi degree: ");
2100   for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
2101     tty->print("L%d ",i5);
2102   tty->cr();
2103 }
2104 
2105 void PhaseChaitin::dump_degree_lists() const {
2106   // Dump lo-degree list
2107   tty->print("Lo degree: ");
2108   for( uint i = _lo_degree; i; i = lrgs(i)._next )
2109     tty->print("L%d ",i);
2110   tty->cr();
2111 
2112   // Dump lo-stk-degree list
2113   tty->print("Lo stk degree: ");
2114   for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
2115     tty->print("L%d ",i2);
2116   tty->cr();
2117 
2118   // Dump lo-degree list
2119   tty->print("Hi degree: ");
2120   for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
2121     tty->print("L%d ",i3);
2122   tty->cr();
2123 }
2124 
2125 void PhaseChaitin::dump_simplified() const {
2126   tty->print("Simplified: ");
2127   for( uint i = _simplified; i; i = lrgs(i)._next )
2128     tty->print("L%d ",i);
2129   tty->cr();
2130 }
2131 
2132 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
2133   if ((int)reg < 0)
2134     sprintf(buf, "<OptoReg::%d>", (int)reg);
2135   else if (OptoReg::is_reg(reg))
2136     strcpy(buf, Matcher::regName[reg]);
2137   else
2138     sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
2139             pc->reg2offset(reg));
2140   return buf+strlen(buf);
2141 }
2142 
2143 // Dump a register name into a buffer.  Be intelligent if we get called
2144 // before allocation is complete.
2145 char *PhaseChaitin::dump_register( const Node *n, char *buf  ) const {
2146   if( this == NULL ) {          // Not got anything?
2147     sprintf(buf,"N%d",n->_idx); // Then use Node index
2148   } else if( _node_regs ) {
2149     // Post allocation, use direct mappings, no LRG info available
2150     print_reg( get_reg_first(n), this, buf );
2151   } else {
2152     uint lidx = _lrg_map.find_const(n); // Grab LRG number
2153     if( !_ifg ) {
2154       sprintf(buf,"L%d",lidx);  // No register binding yet
2155     } else if( !lidx ) {        // Special, not allocated value
2156       strcpy(buf,"Special");
2157     } else {
2158       if (lrgs(lidx)._is_vector) {
2159         if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs()))
2160           print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register
2161         else
2162           sprintf(buf,"L%d",lidx); // No register binding yet
2163       } else if( (lrgs(lidx).num_regs() == 1)
2164                  ? lrgs(lidx).mask().is_bound1()
2165                  : lrgs(lidx).mask().is_bound_pair() ) {
2166         // Hah!  We have a bound machine register
2167         print_reg( lrgs(lidx).reg(), this, buf );
2168       } else {
2169         sprintf(buf,"L%d",lidx); // No register binding yet
2170       }
2171     }
2172   }
2173   return buf+strlen(buf);
2174 }
2175 
2176 void PhaseChaitin::dump_for_spill_split_recycle() const {
2177   if( WizardMode && (PrintCompilation || PrintOpto) ) {
2178     // Display which live ranges need to be split and the allocator's state
2179     tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
2180     for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) {
2181       if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
2182         tty->print("L%d: ", bidx);
2183         lrgs(bidx).dump();
2184       }
2185     }
2186     tty->cr();
2187     dump();
2188   }
2189 }
2190 
2191 void PhaseChaitin::dump_frame() const {
2192   const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
2193   const TypeTuple *domain = C->tf()->domain();
2194   const int        argcnt = domain->cnt() - TypeFunc::Parms;
2195 
2196   // Incoming arguments in registers dump
2197   for( int k = 0; k < argcnt; k++ ) {
2198     OptoReg::Name parmreg = _matcher._parm_regs[k].first();
2199     if( OptoReg::is_reg(parmreg))  {
2200       const char *reg_name = OptoReg::regname(parmreg);
2201       tty->print("#r%3.3d %s", parmreg, reg_name);
2202       parmreg = _matcher._parm_regs[k].second();
2203       if( OptoReg::is_reg(parmreg))  {
2204         tty->print(":%s", OptoReg::regname(parmreg));
2205       }
2206       tty->print("   : parm %d: ", k);
2207       domain->field_at(k + TypeFunc::Parms)->dump();
2208       tty->cr();
2209     }
2210   }
2211 
2212   // Check for un-owned padding above incoming args
2213   OptoReg::Name reg = _matcher._new_SP;
2214   if( reg > _matcher._in_arg_limit ) {
2215     reg = OptoReg::add(reg, -1);
2216     tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
2217   }
2218 
2219   // Incoming argument area dump
2220   OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
2221   while( reg > begin_in_arg ) {
2222     reg = OptoReg::add(reg, -1);
2223     tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2224     int j;
2225     for( j = 0; j < argcnt; j++) {
2226       if( _matcher._parm_regs[j].first() == reg ||
2227           _matcher._parm_regs[j].second() == reg ) {
2228         tty->print("parm %d: ",j);
2229         domain->field_at(j + TypeFunc::Parms)->dump();
2230         tty->cr();
2231         break;
2232       }
2233     }
2234     if( j >= argcnt )
2235       tty->print_cr("HOLE, owned by SELF");
2236   }
2237 
2238   // Old outgoing preserve area
2239   while( reg > _matcher._old_SP ) {
2240     reg = OptoReg::add(reg, -1);
2241     tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
2242   }
2243 
2244   // Old SP
2245   tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
2246     reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
2247 
2248   // Preserve area dump
2249   int fixed_slots = C->fixed_slots();
2250   OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots());
2251   OptoReg::Name return_addr = _matcher.return_addr();
2252 
2253   reg = OptoReg::add(reg, -1);
2254   while (OptoReg::is_stack(reg)) {
2255     tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2256     if (return_addr == reg) {
2257       tty->print_cr("return address");
2258     } else if (reg >= begin_in_preserve) {
2259       // Preserved slots are present on x86
2260       if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word))
2261         tty->print_cr("saved fp register");
2262       else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) &&
2263                VerifyStackAtCalls)
2264         tty->print_cr("0xBADB100D   +VerifyStackAtCalls");
2265       else
2266         tty->print_cr("in_preserve");
2267     } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) {
2268       tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
2269     } else {
2270       tty->print_cr("pad2, stack alignment");
2271     }
2272     reg = OptoReg::add(reg, -1);
2273   }
2274 
2275   // Spill area dump
2276   reg = OptoReg::add(_matcher._new_SP, _framesize );
2277   while( reg > _matcher._out_arg_limit ) {
2278     reg = OptoReg::add(reg, -1);
2279     tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
2280   }
2281 
2282   // Outgoing argument area dump
2283   while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
2284     reg = OptoReg::add(reg, -1);
2285     tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
2286   }
2287 
2288   // Outgoing new preserve area
2289   while( reg > _matcher._new_SP ) {
2290     reg = OptoReg::add(reg, -1);
2291     tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
2292   }
2293   tty->print_cr("#");
2294 }
2295 
2296 void PhaseChaitin::dump_bb( uint pre_order ) const {
2297   tty->print_cr("---dump of B%d---",pre_order);
2298   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2299     Block* block = _cfg.get_block(i);
2300     if (block->_pre_order == pre_order) {
2301       dump(block);
2302     }
2303   }
2304 }
2305 
2306 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
2307   tty->print_cr("---dump of L%d---",lidx);
2308 
2309   if (_ifg) {
2310     if (lidx >= _lrg_map.max_lrg_id()) {
2311       tty->print("Attempt to print live range index beyond max live range.\n");
2312       return;
2313     }
2314     tty->print("L%d: ",lidx);
2315     if (lidx < _ifg->_maxlrg) {
2316       lrgs(lidx).dump();
2317     } else {
2318       tty->print_cr("new LRG");
2319     }
2320   }
2321   if( _ifg && lidx < _ifg->_maxlrg) {
2322     tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
2323     _ifg->neighbors(lidx)->dump();
2324     tty->cr();
2325   }
2326   // For all blocks
2327   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2328     Block* block = _cfg.get_block(i);
2329     int dump_once = 0;
2330 
2331     // For all instructions
2332     for( uint j = 0; j < block->number_of_nodes(); j++ ) {
2333       Node *n = block->get_node(j);
2334       if (_lrg_map.find_const(n) == lidx) {
2335         if (!dump_once++) {
2336           tty->cr();
2337           block->dump_head(&_cfg);
2338         }
2339         dump(n);
2340         continue;
2341       }
2342       if (!defs_only) {
2343         uint cnt = n->req();
2344         for( uint k = 1; k < cnt; k++ ) {
2345           Node *m = n->in(k);
2346           if (!m)  {
2347             continue;  // be robust in the dumper
2348           }
2349           if (_lrg_map.find_const(m) == lidx) {
2350             if (!dump_once++) {
2351               tty->cr();
2352               block->dump_head(&_cfg);
2353             }
2354             dump(n);
2355           }
2356         }
2357       }
2358     }
2359   } // End of per-block dump
2360   tty->cr();
2361 }
2362 #endif // not PRODUCT
2363 
2364 int PhaseChaitin::_final_loads  = 0;
2365 int PhaseChaitin::_final_stores = 0;
2366 int PhaseChaitin::_final_memoves= 0;
2367 int PhaseChaitin::_final_copies = 0;
2368 double PhaseChaitin::_final_load_cost  = 0;
2369 double PhaseChaitin::_final_store_cost = 0;
2370 double PhaseChaitin::_final_memove_cost= 0;
2371 double PhaseChaitin::_final_copy_cost  = 0;
2372 int PhaseChaitin::_conserv_coalesce = 0;
2373 int PhaseChaitin::_conserv_coalesce_pair = 0;
2374 int PhaseChaitin::_conserv_coalesce_trie = 0;
2375 int PhaseChaitin::_conserv_coalesce_quad = 0;
2376 int PhaseChaitin::_post_alloc = 0;
2377 int PhaseChaitin::_lost_opp_pp_coalesce = 0;
2378 int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
2379 int PhaseChaitin::_used_cisc_instructions   = 0;
2380 int PhaseChaitin::_unused_cisc_instructions = 0;
2381 int PhaseChaitin::_allocator_attempts       = 0;
2382 int PhaseChaitin::_allocator_successes      = 0;
2383 
2384 #ifndef PRODUCT
2385 uint PhaseChaitin::_high_pressure           = 0;
2386 uint PhaseChaitin::_low_pressure            = 0;
2387 
2388 void PhaseChaitin::print_chaitin_statistics() {
2389   tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
2390   tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
2391   tty->print_cr("Adjusted spill cost = %7.0f.",
2392                 _final_load_cost*4.0 + _final_store_cost  * 2.0 +
2393                 _final_copy_cost*1.0 + _final_memove_cost*12.0);
2394   tty->print("Conservatively coalesced %d copies, %d pairs",
2395                 _conserv_coalesce, _conserv_coalesce_pair);
2396   if( _conserv_coalesce_trie || _conserv_coalesce_quad )
2397     tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
2398   tty->print_cr(", %d post alloc.", _post_alloc);
2399   if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
2400     tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
2401                   _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
2402   if( _used_cisc_instructions || _unused_cisc_instructions )
2403     tty->print_cr("Used cisc instruction  %d,  remained in register %d",
2404                    _used_cisc_instructions, _unused_cisc_instructions);
2405   if( _allocator_successes != 0 )
2406     tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
2407   tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
2408 }
2409 #endif // not PRODUCT