62 _post_visited(arena()), // post visited node set
63 _n_idx_list(arena(), 8), // scratch list of (node,index) pairs
64 _stk(arena(), 8, 0, NULL), // scratch stack of nodes
65 _nlist(arena(), 8, 0, NULL), // scratch list of nodes
66 _lpt(NULL), // loop tree node
67 _lp(NULL), // LoopNode
68 _bb(NULL), // basic block
69 _iv(NULL), // induction var
70 _race_possible(false), // cases where SDMU is true
71 _early_return(true), // analysis evaluations routine
72 _num_work_vecs(0), // amount of vector work we have
73 _num_reductions(0), // amount of reduction work we have
74 _do_vector_loop(phase->C->do_vector_loop()), // whether to do vectorization/simd style
75 _ii_first(-1), // first loop generation index - only if do_vector_loop()
76 _ii_last(-1), // last loop generation index - only if do_vector_loop()
77 _ii_order(arena(), 8, 0, 0)
78 {
79 #ifndef PRODUCT
80 _vector_loop_debug = 0;
81 if (_phase->C->method() != NULL) {
82 _phase->C->method()->has_option_value("VectorizeDebug", _vector_loop_debug);
83 }
84 #endif
85 }
86
87 //------------------------------transform_loop---------------------------
88 void SuperWord::transform_loop(IdealLoopTree* lpt, bool do_optimization) {
89 assert(UseSuperWord, "should be");
90 // Do vectors exist on this architecture?
91 if (Matcher::vector_width_in_bytes(T_BYTE) < 2) return;
92
93 assert(lpt->_head->is_CountedLoop(), "must be");
94 CountedLoopNode *cl = lpt->_head->as_CountedLoop();
95
96 if (!cl->is_valid_counted_loop()) return; // skip malformed counted loop
97
98 if (!cl->is_main_loop() ) return; // skip normal, pre, and post loops
99 // Check for no control flow in body (other than exit)
100 Node *cl_exit = cl->loopexit();
101 if (cl_exit->in(0) != lpt->_head) return;
102
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62 _post_visited(arena()), // post visited node set
63 _n_idx_list(arena(), 8), // scratch list of (node,index) pairs
64 _stk(arena(), 8, 0, NULL), // scratch stack of nodes
65 _nlist(arena(), 8, 0, NULL), // scratch list of nodes
66 _lpt(NULL), // loop tree node
67 _lp(NULL), // LoopNode
68 _bb(NULL), // basic block
69 _iv(NULL), // induction var
70 _race_possible(false), // cases where SDMU is true
71 _early_return(true), // analysis evaluations routine
72 _num_work_vecs(0), // amount of vector work we have
73 _num_reductions(0), // amount of reduction work we have
74 _do_vector_loop(phase->C->do_vector_loop()), // whether to do vectorization/simd style
75 _ii_first(-1), // first loop generation index - only if do_vector_loop()
76 _ii_last(-1), // last loop generation index - only if do_vector_loop()
77 _ii_order(arena(), 8, 0, 0)
78 {
79 #ifndef PRODUCT
80 _vector_loop_debug = 0;
81 if (_phase->C->method() != NULL) {
82 _vector_loop_debug = phase->C->directive()->VectorizeDebugOption;
83 }
84 #endif
85 }
86
87 //------------------------------transform_loop---------------------------
88 void SuperWord::transform_loop(IdealLoopTree* lpt, bool do_optimization) {
89 assert(UseSuperWord, "should be");
90 // Do vectors exist on this architecture?
91 if (Matcher::vector_width_in_bytes(T_BYTE) < 2) return;
92
93 assert(lpt->_head->is_CountedLoop(), "must be");
94 CountedLoopNode *cl = lpt->_head->as_CountedLoop();
95
96 if (!cl->is_valid_counted_loop()) return; // skip malformed counted loop
97
98 if (!cl->is_main_loop() ) return; // skip normal, pre, and post loops
99 // Check for no control flow in body (other than exit)
100 Node *cl_exit = cl->loopexit();
101 if (cl_exit->in(0) != lpt->_head) return;
102
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