1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "logging/log.hpp"
30 #include "logging/logStream.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "vm_version_x86.hpp"
36
37
38 int VM_Version::_cpu;
39 int VM_Version::_model;
40 int VM_Version::_stepping;
41 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
42
43 // Address of instruction which causes SEGV
44 address VM_Version::_cpuinfo_segv_addr = 0;
45 // Address of instruction after the one which causes SEGV
46 address VM_Version::_cpuinfo_cont_addr = 0;
47
48 static BufferBlob* stub_blob;
49 static const int stub_size = 1100;
50
51 extern "C" {
52 typedef void (*get_cpu_info_stub_t)(void*);
53 }
54 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
55
56
57 class VM_Version_StubGenerator: public StubCodeGenerator {
58 public:
59
60 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
61
62 address generate_get_cpu_info() {
63 // Flags to test CPU type.
64 const uint32_t HS_EFL_AC = 0x40000;
65 const uint32_t HS_EFL_ID = 0x200000;
66 // Values for when we don't have a CPUID instruction.
67 const int CPU_FAMILY_SHIFT = 8;
68 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
69 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
70 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
71
72 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
73 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
74 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
75
76 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
77 # define __ _masm->
78
79 address start = __ pc();
80
81 //
82 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
83 //
84 // LP64: rcx and rdx are first and second argument registers on windows
85
86 __ push(rbp);
87 #ifdef _LP64
88 __ mov(rbp, c_rarg0); // cpuid_info address
89 #else
90 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
91 #endif
92 __ push(rbx);
93 __ push(rsi);
94 __ pushf(); // preserve rbx, and flags
95 __ pop(rax);
96 __ push(rax);
97 __ mov(rcx, rax);
98 //
99 // if we are unable to change the AC flag, we have a 386
100 //
101 __ xorl(rax, HS_EFL_AC);
102 __ push(rax);
103 __ popf();
104 __ pushf();
105 __ pop(rax);
106 __ cmpptr(rax, rcx);
107 __ jccb(Assembler::notEqual, detect_486);
108
109 __ movl(rax, CPU_FAMILY_386);
110 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
111 __ jmp(done);
112
113 //
114 // If we are unable to change the ID flag, we have a 486 which does
115 // not support the "cpuid" instruction.
116 //
117 __ bind(detect_486);
118 __ mov(rax, rcx);
119 __ xorl(rax, HS_EFL_ID);
120 __ push(rax);
121 __ popf();
122 __ pushf();
123 __ pop(rax);
124 __ cmpptr(rcx, rax);
125 __ jccb(Assembler::notEqual, detect_586);
126
127 __ bind(cpu486);
128 __ movl(rax, CPU_FAMILY_486);
129 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
130 __ jmp(done);
131
132 //
133 // At this point, we have a chip which supports the "cpuid" instruction
134 //
135 __ bind(detect_586);
136 __ xorl(rax, rax);
137 __ cpuid();
138 __ orl(rax, rax);
139 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
140 // value of at least 1, we give up and
141 // assume a 486
142 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
143 __ movl(Address(rsi, 0), rax);
144 __ movl(Address(rsi, 4), rbx);
145 __ movl(Address(rsi, 8), rcx);
146 __ movl(Address(rsi,12), rdx);
147
148 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
149 __ jccb(Assembler::belowEqual, std_cpuid4);
150
151 //
152 // cpuid(0xB) Processor Topology
153 //
154 __ movl(rax, 0xb);
155 __ xorl(rcx, rcx); // Threads level
156 __ cpuid();
157
158 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
159 __ movl(Address(rsi, 0), rax);
160 __ movl(Address(rsi, 4), rbx);
161 __ movl(Address(rsi, 8), rcx);
162 __ movl(Address(rsi,12), rdx);
163
164 __ movl(rax, 0xb);
165 __ movl(rcx, 1); // Cores level
166 __ cpuid();
167 __ push(rax);
168 __ andl(rax, 0x1f); // Determine if valid topology level
169 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
170 __ andl(rax, 0xffff);
171 __ pop(rax);
172 __ jccb(Assembler::equal, std_cpuid4);
173
174 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
175 __ movl(Address(rsi, 0), rax);
176 __ movl(Address(rsi, 4), rbx);
177 __ movl(Address(rsi, 8), rcx);
178 __ movl(Address(rsi,12), rdx);
179
180 __ movl(rax, 0xb);
181 __ movl(rcx, 2); // Packages level
182 __ cpuid();
183 __ push(rax);
184 __ andl(rax, 0x1f); // Determine if valid topology level
185 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
186 __ andl(rax, 0xffff);
187 __ pop(rax);
188 __ jccb(Assembler::equal, std_cpuid4);
189
190 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
191 __ movl(Address(rsi, 0), rax);
192 __ movl(Address(rsi, 4), rbx);
193 __ movl(Address(rsi, 8), rcx);
194 __ movl(Address(rsi,12), rdx);
195
196 //
197 // cpuid(0x4) Deterministic cache params
198 //
199 __ bind(std_cpuid4);
200 __ movl(rax, 4);
201 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
202 __ jccb(Assembler::greater, std_cpuid1);
203
204 __ xorl(rcx, rcx); // L1 cache
205 __ cpuid();
206 __ push(rax);
207 __ andl(rax, 0x1f); // Determine if valid cache parameters used
208 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
209 __ pop(rax);
210 __ jccb(Assembler::equal, std_cpuid1);
211
212 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
213 __ movl(Address(rsi, 0), rax);
214 __ movl(Address(rsi, 4), rbx);
215 __ movl(Address(rsi, 8), rcx);
216 __ movl(Address(rsi,12), rdx);
217
218 //
219 // Standard cpuid(0x1)
220 //
221 __ bind(std_cpuid1);
222 __ movl(rax, 1);
223 __ cpuid();
224 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
225 __ movl(Address(rsi, 0), rax);
226 __ movl(Address(rsi, 4), rbx);
227 __ movl(Address(rsi, 8), rcx);
228 __ movl(Address(rsi,12), rdx);
229
230 //
231 // Check if OS has enabled XGETBV instruction to access XCR0
232 // (OSXSAVE feature flag) and CPU supports AVX
233 //
234 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
235 __ cmpl(rcx, 0x18000000);
236 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
237
238 //
239 // XCR0, XFEATURE_ENABLED_MASK register
240 //
241 __ xorl(rcx, rcx); // zero for XCR0 register
242 __ xgetbv();
243 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
244 __ movl(Address(rsi, 0), rax);
245 __ movl(Address(rsi, 4), rdx);
246
247 //
248 // cpuid(0x7) Structured Extended Features
249 //
250 __ bind(sef_cpuid);
251 __ movl(rax, 7);
252 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
253 __ jccb(Assembler::greater, ext_cpuid);
254
255 __ xorl(rcx, rcx);
256 __ cpuid();
257 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
258 __ movl(Address(rsi, 0), rax);
259 __ movl(Address(rsi, 4), rbx);
260 __ movl(Address(rsi, 8), rcx);
261 __ movl(Address(rsi, 12), rdx);
262
263 //
264 // Extended cpuid(0x80000000)
265 //
266 __ bind(ext_cpuid);
267 __ movl(rax, 0x80000000);
268 __ cpuid();
269 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
270 __ jcc(Assembler::belowEqual, done);
271 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
272 __ jcc(Assembler::belowEqual, ext_cpuid1);
273 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
274 __ jccb(Assembler::belowEqual, ext_cpuid5);
275 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
276 __ jccb(Assembler::belowEqual, ext_cpuid7);
277 __ cmpl(rax, 0x80000008); // Is cpuid(0x80000009 and above) supported?
278 __ jccb(Assembler::belowEqual, ext_cpuid8);
279 __ cmpl(rax, 0x8000001E); // Is cpuid(0x8000001E) supported?
280 __ jccb(Assembler::below, ext_cpuid8);
281 //
282 // Extended cpuid(0x8000001E)
283 //
284 __ movl(rax, 0x8000001E);
285 __ cpuid();
286 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
287 __ movl(Address(rsi, 0), rax);
288 __ movl(Address(rsi, 4), rbx);
289 __ movl(Address(rsi, 8), rcx);
290 __ movl(Address(rsi,12), rdx);
291
292 //
293 // Extended cpuid(0x80000008)
294 //
295 __ bind(ext_cpuid8);
296 __ movl(rax, 0x80000008);
297 __ cpuid();
298 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
299 __ movl(Address(rsi, 0), rax);
300 __ movl(Address(rsi, 4), rbx);
301 __ movl(Address(rsi, 8), rcx);
302 __ movl(Address(rsi,12), rdx);
303
304 //
305 // Extended cpuid(0x80000007)
306 //
307 __ bind(ext_cpuid7);
308 __ movl(rax, 0x80000007);
309 __ cpuid();
310 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
311 __ movl(Address(rsi, 0), rax);
312 __ movl(Address(rsi, 4), rbx);
313 __ movl(Address(rsi, 8), rcx);
314 __ movl(Address(rsi,12), rdx);
315
316 //
317 // Extended cpuid(0x80000005)
318 //
319 __ bind(ext_cpuid5);
320 __ movl(rax, 0x80000005);
321 __ cpuid();
322 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
323 __ movl(Address(rsi, 0), rax);
324 __ movl(Address(rsi, 4), rbx);
325 __ movl(Address(rsi, 8), rcx);
326 __ movl(Address(rsi,12), rdx);
327
328 //
329 // Extended cpuid(0x80000001)
330 //
331 __ bind(ext_cpuid1);
332 __ movl(rax, 0x80000001);
333 __ cpuid();
334 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
335 __ movl(Address(rsi, 0), rax);
336 __ movl(Address(rsi, 4), rbx);
337 __ movl(Address(rsi, 8), rcx);
338 __ movl(Address(rsi,12), rdx);
339
340 //
341 // Check if OS has enabled XGETBV instruction to access XCR0
342 // (OSXSAVE feature flag) and CPU supports AVX
343 //
344 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
345 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
346 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
347 __ cmpl(rcx, 0x18000000);
348 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
349
350 __ movl(rax, 0x6);
351 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
352 __ cmpl(rax, 0x6);
353 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
354
355 // we need to bridge farther than imm8, so we use this island as a thunk
356 __ bind(done);
357 __ jmp(wrapup);
358
359 __ bind(start_simd_check);
360 //
361 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
362 // registers are not restored after a signal processing.
363 // Generate SEGV here (reference through NULL)
364 // and check upper YMM/ZMM bits after it.
365 //
366 intx saved_useavx = UseAVX;
367 intx saved_usesse = UseSSE;
368 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
369 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
370 __ movl(rax, 0x10000);
371 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
372 __ cmpl(rax, 0x10000);
373 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
374 // check _cpuid_info.xem_xcr0_eax.bits.opmask
375 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
376 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
377 __ movl(rax, 0xE0);
378 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
379 __ cmpl(rax, 0xE0);
380 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
381
382 // If UseAVX is unitialized or is set by the user to include EVEX
383 if (use_evex) {
384 // EVEX setup: run in lowest evex mode
385 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
386 UseAVX = 3;
387 UseSSE = 2;
388 #ifdef _WINDOWS
389 // xmm5-xmm15 are not preserved by caller on windows
390 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
391 __ subptr(rsp, 64);
392 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
393 #ifdef _LP64
394 __ subptr(rsp, 64);
395 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
396 __ subptr(rsp, 64);
397 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
398 #endif // _LP64
399 #endif // _WINDOWS
400
401 // load value into all 64 bytes of zmm7 register
402 __ movl(rcx, VM_Version::ymm_test_value());
403 __ movdl(xmm0, rcx);
404 __ vpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
405 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
406 #ifdef _LP64
407 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
408 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
409 #endif
410 VM_Version::clean_cpuFeatures();
411 __ jmp(save_restore_except);
412 }
413
414 __ bind(legacy_setup);
415 // AVX setup
416 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
417 UseAVX = 1;
418 UseSSE = 2;
419 #ifdef _WINDOWS
420 __ subptr(rsp, 32);
421 __ vmovdqu(Address(rsp, 0), xmm7);
422 #ifdef _LP64
423 __ subptr(rsp, 32);
424 __ vmovdqu(Address(rsp, 0), xmm8);
425 __ subptr(rsp, 32);
426 __ vmovdqu(Address(rsp, 0), xmm15);
427 #endif // _LP64
428 #endif // _WINDOWS
429
430 // load value into all 32 bytes of ymm7 register
431 __ movl(rcx, VM_Version::ymm_test_value());
432
433 __ movdl(xmm0, rcx);
434 __ pshufd(xmm0, xmm0, 0x00);
435 __ vinsertf128_high(xmm0, xmm0);
436 __ vmovdqu(xmm7, xmm0);
437 #ifdef _LP64
438 __ vmovdqu(xmm8, xmm0);
439 __ vmovdqu(xmm15, xmm0);
440 #endif
441 VM_Version::clean_cpuFeatures();
442
443 __ bind(save_restore_except);
444 __ xorl(rsi, rsi);
445 VM_Version::set_cpuinfo_segv_addr(__ pc());
446 // Generate SEGV
447 __ movl(rax, Address(rsi, 0));
448
449 VM_Version::set_cpuinfo_cont_addr(__ pc());
450 // Returns here after signal. Save xmm0 to check it later.
451
452 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
453 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
454 __ movl(rax, 0x10000);
455 __ andl(rax, Address(rsi, 4));
456 __ cmpl(rax, 0x10000);
457 __ jcc(Assembler::notEqual, legacy_save_restore);
458 // check _cpuid_info.xem_xcr0_eax.bits.opmask
459 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
460 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
461 __ movl(rax, 0xE0);
462 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
463 __ cmpl(rax, 0xE0);
464 __ jcc(Assembler::notEqual, legacy_save_restore);
465
466 // If UseAVX is unitialized or is set by the user to include EVEX
467 if (use_evex) {
468 // EVEX check: run in lowest evex mode
469 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
470 UseAVX = 3;
471 UseSSE = 2;
472 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
473 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
474 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
475 #ifdef _LP64
476 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
477 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
478 #endif
479
480 #ifdef _WINDOWS
481 #ifdef _LP64
482 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
483 __ addptr(rsp, 64);
484 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
485 __ addptr(rsp, 64);
486 #endif // _LP64
487 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
488 __ addptr(rsp, 64);
489 #endif // _WINDOWS
490 generate_vzeroupper(wrapup);
491 VM_Version::clean_cpuFeatures();
492 UseAVX = saved_useavx;
493 UseSSE = saved_usesse;
494 __ jmp(wrapup);
495 }
496
497 __ bind(legacy_save_restore);
498 // AVX check
499 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
500 UseAVX = 1;
501 UseSSE = 2;
502 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
503 __ vmovdqu(Address(rsi, 0), xmm0);
504 __ vmovdqu(Address(rsi, 32), xmm7);
505 #ifdef _LP64
506 __ vmovdqu(Address(rsi, 64), xmm8);
507 __ vmovdqu(Address(rsi, 96), xmm15);
508 #endif
509
510 #ifdef _WINDOWS
511 #ifdef _LP64
512 __ vmovdqu(xmm15, Address(rsp, 0));
513 __ addptr(rsp, 32);
514 __ vmovdqu(xmm8, Address(rsp, 0));
515 __ addptr(rsp, 32);
516 #endif // _LP64
517 __ vmovdqu(xmm7, Address(rsp, 0));
518 __ addptr(rsp, 32);
519 #endif // _WINDOWS
520 generate_vzeroupper(wrapup);
521 VM_Version::clean_cpuFeatures();
522 UseAVX = saved_useavx;
523 UseSSE = saved_usesse;
524
525 __ bind(wrapup);
526 __ popf();
527 __ pop(rsi);
528 __ pop(rbx);
529 __ pop(rbp);
530 __ ret(0);
531
532 # undef __
533
534 return start;
535 };
536 void generate_vzeroupper(Label& L_wrapup) {
537 # define __ _masm->
538 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
539 __ cmpl(Address(rsi, 4), 0x756e6547); // 'uneG'
540 __ jcc(Assembler::notEqual, L_wrapup);
541 __ movl(rcx, 0x0FFF0FF0);
542 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
543 __ andl(rcx, Address(rsi, 0));
544 __ cmpl(rcx, 0x00050670); // If it is Xeon Phi 3200/5200/7200
545 __ jcc(Assembler::equal, L_wrapup);
546 __ cmpl(rcx, 0x00080650); // If it is Future Xeon Phi
547 __ jcc(Assembler::equal, L_wrapup);
548 __ vzeroupper();
549 # undef __
550 }
551 };
552
553 void VM_Version::get_processor_features() {
554
555 _cpu = 4; // 486 by default
556 _model = 0;
557 _stepping = 0;
558 _features = 0;
559 _logical_processors_per_package = 1;
560 // i486 internal cache is both I&D and has a 16-byte line size
561 _L1_data_cache_line_size = 16;
562
563 // Get raw processor info
564
565 get_cpu_info_stub(&_cpuid_info);
566
567 assert_is_initialized();
568 _cpu = extended_cpu_family();
569 _model = extended_cpu_model();
570 _stepping = cpu_stepping();
571
572 if (cpu_family() > 4) { // it supports CPUID
573 _features = feature_flags();
574 // Logical processors are only available on P4s and above,
575 // and only if hyperthreading is available.
576 _logical_processors_per_package = logical_processor_count();
577 _L1_data_cache_line_size = L1_line_size();
578 }
579
580 _supports_cx8 = supports_cmpxchg8();
581 // xchg and xadd instructions
582 _supports_atomic_getset4 = true;
583 _supports_atomic_getadd4 = true;
584 LP64_ONLY(_supports_atomic_getset8 = true);
585 LP64_ONLY(_supports_atomic_getadd8 = true);
586
587 #ifdef _LP64
588 // OS should support SSE for x64 and hardware should support at least SSE2.
589 if (!VM_Version::supports_sse2()) {
590 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
591 }
592 // in 64 bit the use of SSE2 is the minimum
593 if (UseSSE < 2) UseSSE = 2;
594 #endif
595
596 #ifdef AMD64
597 // flush_icache_stub have to be generated first.
598 // That is why Icache line size is hard coded in ICache class,
599 // see icache_x86.hpp. It is also the reason why we can't use
600 // clflush instruction in 32-bit VM since it could be running
601 // on CPU which does not support it.
602 //
603 // The only thing we can do is to verify that flushed
604 // ICache::line_size has correct value.
605 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
606 // clflush_size is size in quadwords (8 bytes).
607 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
608 #endif
609
610 // If the OS doesn't support SSE, we can't use this feature even if the HW does
611 if (!os::supports_sse())
612 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
613
614 if (UseSSE < 4) {
615 _features &= ~CPU_SSE4_1;
616 _features &= ~CPU_SSE4_2;
617 }
618
619 if (UseSSE < 3) {
620 _features &= ~CPU_SSE3;
621 _features &= ~CPU_SSSE3;
622 _features &= ~CPU_SSE4A;
623 }
624
625 if (UseSSE < 2)
626 _features &= ~CPU_SSE2;
627
628 if (UseSSE < 1)
629 _features &= ~CPU_SSE;
630
631 //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
632 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
633 UseAVX = 0;
634 }
635
636 // first try initial setting and detect what we can support
637 int use_avx_limit = 0;
638 if (UseAVX > 0) {
639 if (UseAVX > 2 && supports_evex()) {
640 use_avx_limit = 3;
641 } else if (UseAVX > 1 && supports_avx2()) {
642 use_avx_limit = 2;
643 } else if (UseAVX > 0 && supports_avx()) {
644 use_avx_limit = 1;
645 } else {
646 use_avx_limit = 0;
647 }
648 }
649 if (FLAG_IS_DEFAULT(UseAVX)) {
650 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
651 } else if (UseAVX > use_avx_limit) {
652 warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
653 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
654 } else if (UseAVX < 0) {
655 warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
656 FLAG_SET_DEFAULT(UseAVX, 0);
657 }
658
659 if (UseAVX < 3) {
660 _features &= ~CPU_AVX512F;
661 _features &= ~CPU_AVX512DQ;
662 _features &= ~CPU_AVX512CD;
663 _features &= ~CPU_AVX512BW;
664 _features &= ~CPU_AVX512VL;
665 _features &= ~CPU_AVX512_VPOPCNTDQ;
666 _features &= ~CPU_VPCLMULQDQ;
667 _features &= ~CPU_VAES;
668 }
669
670 if (UseAVX < 2)
671 _features &= ~CPU_AVX2;
672
673 if (UseAVX < 1) {
674 _features &= ~CPU_AVX;
675 _features &= ~CPU_VZEROUPPER;
676 }
677
678 if (logical_processors_per_package() == 1) {
679 // HT processor could be installed on a system which doesn't support HT.
680 _features &= ~CPU_HT;
681 }
682
683 if( is_intel() ) { // Intel cpus specific settings
684 if (is_knights_family()) {
685 _features &= ~CPU_VZEROUPPER;
686 }
687 }
688
689 char buf[256];
690 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
691 cores_per_cpu(), threads_per_core(),
692 cpu_family(), _model, _stepping,
693 (supports_cmov() ? ", cmov" : ""),
694 (supports_cmpxchg8() ? ", cx8" : ""),
695 (supports_fxsr() ? ", fxsr" : ""),
696 (supports_mmx() ? ", mmx" : ""),
697 (supports_sse() ? ", sse" : ""),
698 (supports_sse2() ? ", sse2" : ""),
699 (supports_sse3() ? ", sse3" : ""),
700 (supports_ssse3()? ", ssse3": ""),
701 (supports_sse4_1() ? ", sse4.1" : ""),
702 (supports_sse4_2() ? ", sse4.2" : ""),
703 (supports_popcnt() ? ", popcnt" : ""),
704 (supports_avx() ? ", avx" : ""),
705 (supports_avx2() ? ", avx2" : ""),
706 (supports_aes() ? ", aes" : ""),
707 (supports_clmul() ? ", clmul" : ""),
708 (supports_erms() ? ", erms" : ""),
709 (supports_rtm() ? ", rtm" : ""),
710 (supports_mmx_ext() ? ", mmxext" : ""),
711 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
712 (supports_lzcnt() ? ", lzcnt": ""),
713 (supports_sse4a() ? ", sse4a": ""),
714 (supports_ht() ? ", ht": ""),
715 (supports_tsc() ? ", tsc": ""),
716 (supports_tscinv_bit() ? ", tscinvbit": ""),
717 (supports_tscinv() ? ", tscinv": ""),
718 (supports_bmi1() ? ", bmi1" : ""),
719 (supports_bmi2() ? ", bmi2" : ""),
720 (supports_adx() ? ", adx" : ""),
721 (supports_evex() ? ", evex" : ""),
722 (supports_sha() ? ", sha" : ""),
723 (supports_fma() ? ", fma" : ""));
724 _features_string = os::strdup(buf);
725
726 // UseSSE is set to the smaller of what hardware supports and what
727 // the command line requires. I.e., you cannot set UseSSE to 2 on
728 // older Pentiums which do not support it.
729 int use_sse_limit = 0;
730 if (UseSSE > 0) {
731 if (UseSSE > 3 && supports_sse4_1()) {
732 use_sse_limit = 4;
733 } else if (UseSSE > 2 && supports_sse3()) {
734 use_sse_limit = 3;
735 } else if (UseSSE > 1 && supports_sse2()) {
736 use_sse_limit = 2;
737 } else if (UseSSE > 0 && supports_sse()) {
738 use_sse_limit = 1;
739 } else {
740 use_sse_limit = 0;
741 }
742 }
743 if (FLAG_IS_DEFAULT(UseSSE)) {
744 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
745 } else if (UseSSE > use_sse_limit) {
746 warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
747 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
748 } else if (UseSSE < 0) {
749 warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
750 FLAG_SET_DEFAULT(UseSSE, 0);
751 }
752
753 // Use AES instructions if available.
754 if (supports_aes()) {
755 if (FLAG_IS_DEFAULT(UseAES)) {
756 FLAG_SET_DEFAULT(UseAES, true);
757 }
758 if (!UseAES) {
759 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
760 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
761 }
762 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
763 } else {
764 if (UseSSE > 2) {
765 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
766 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
767 }
768 } else {
769 // The AES intrinsic stubs require AES instruction support (of course)
770 // but also require sse3 mode or higher for instructions it use.
771 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
772 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
773 }
774 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
775 }
776
777 // --AES-CTR begins--
778 if (!UseAESIntrinsics) {
779 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
780 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
781 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
782 }
783 } else {
784 if(supports_sse4_1()) {
785 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
786 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
787 }
788 } else {
789 // The AES-CTR intrinsic stubs require AES instruction support (of course)
790 // but also require sse4.1 mode or higher for instructions it use.
791 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
792 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
793 }
794 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
795 }
796 }
797 // --AES-CTR ends--
798 }
799 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
800 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
801 warning("AES instructions are not available on this CPU");
802 FLAG_SET_DEFAULT(UseAES, false);
803 }
804 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
805 warning("AES intrinsics are not available on this CPU");
806 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
807 }
808 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
809 warning("AES-CTR intrinsics are not available on this CPU");
810 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
811 }
812 }
813
814 // Use CLMUL instructions if available.
815 if (supports_clmul()) {
816 if (FLAG_IS_DEFAULT(UseCLMUL)) {
817 UseCLMUL = true;
818 }
819 } else if (UseCLMUL) {
820 if (!FLAG_IS_DEFAULT(UseCLMUL))
821 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
822 FLAG_SET_DEFAULT(UseCLMUL, false);
823 }
824
825 if (UseCLMUL && (UseSSE > 2)) {
826 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
827 UseCRC32Intrinsics = true;
828 }
829 } else if (UseCRC32Intrinsics) {
830 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
831 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
832 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
833 }
834
835 if (supports_sse4_2() && supports_clmul()) {
836 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
837 UseCRC32CIntrinsics = true;
838 }
839 } else if (UseCRC32CIntrinsics) {
840 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
841 warning("CRC32C intrinsics are not available on this CPU");
842 }
843 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
844 }
845
846 // GHASH/GCM intrinsics
847 if (UseCLMUL && (UseSSE > 2)) {
848 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
849 UseGHASHIntrinsics = true;
850 }
851 } else if (UseGHASHIntrinsics) {
852 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
853 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
854 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
855 }
856
857 // Base64 Intrinsics (Check the condition for which the intrinsic will be active)
858 if ((UseAVX > 2) && supports_avx512vl() && supports_avx512bw()) {
859 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
860 UseBASE64Intrinsics = true;
861 }
862 } else if (UseBASE64Intrinsics) {
863 if (!FLAG_IS_DEFAULT(UseBASE64Intrinsics))
864 warning("Base64 intrinsic requires EVEX instructions on this CPU");
865 FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
866 }
867
868 if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
869 if (FLAG_IS_DEFAULT(UseFMA)) {
870 UseFMA = true;
871 }
872 } else if (UseFMA) {
873 warning("FMA instructions are not available on this CPU");
874 FLAG_SET_DEFAULT(UseFMA, false);
875 }
876
877 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
878 if (FLAG_IS_DEFAULT(UseSHA)) {
879 UseSHA = true;
880 }
881 } else if (UseSHA) {
882 warning("SHA instructions are not available on this CPU");
883 FLAG_SET_DEFAULT(UseSHA, false);
884 }
885
886 if (supports_sha() && supports_sse4_1() && UseSHA) {
887 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
888 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
889 }
890 } else if (UseSHA1Intrinsics) {
891 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
892 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
893 }
894
895 if (supports_sse4_1() && UseSHA) {
896 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
897 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
898 }
899 } else if (UseSHA256Intrinsics) {
900 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
901 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
902 }
903
904 if (UseSHA && supports_avx2() && supports_bmi2()) {
905 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
906 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
907 }
908 } else if (UseSHA512Intrinsics) {
909 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
910 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
911 }
912
913 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
914 FLAG_SET_DEFAULT(UseSHA, false);
915 }
916
917 if (UseAdler32Intrinsics) {
918 warning("Adler32Intrinsics not available on this CPU.");
919 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
920 }
921
922 if (!supports_rtm() && UseRTMLocking) {
923 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
924 // setting during arguments processing. See use_biased_locking().
925 // VM_Version_init() is executed after UseBiasedLocking is used
926 // in Thread::allocate().
927 vm_exit_during_initialization("RTM instructions are not available on this CPU");
928 }
929
930 #if INCLUDE_RTM_OPT
931 if (UseRTMLocking) {
932 if (is_client_compilation_mode_vm()) {
933 // Only C2 does RTM locking optimization.
934 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
935 // setting during arguments processing. See use_biased_locking().
936 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
937 }
938 if (is_intel_family_core()) {
939 if ((_model == CPU_MODEL_HASWELL_E3) ||
940 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
941 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
942 // currently a collision between SKL and HSW_E3
943 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
944 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
945 "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
946 } else {
947 warning("UseRTMLocking is only available as experimental option on this platform.");
948 }
949 }
950 }
951 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
952 // RTM locking should be used only for applications with
953 // high lock contention. For now we do not use it by default.
954 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
955 }
956 } else { // !UseRTMLocking
957 if (UseRTMForStackLocks) {
958 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
959 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
960 }
961 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
962 }
963 if (UseRTMDeopt) {
964 FLAG_SET_DEFAULT(UseRTMDeopt, false);
965 }
966 if (PrintPreciseRTMLockingStatistics) {
967 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
968 }
969 }
970 #else
971 if (UseRTMLocking) {
972 // Only C2 does RTM locking optimization.
973 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
974 // setting during arguments processing. See use_biased_locking().
975 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
976 }
977 #endif
978
979 #ifdef COMPILER2
980 if (UseFPUForSpilling) {
981 if (UseSSE < 2) {
982 // Only supported with SSE2+
983 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
984 }
985 }
986 #endif
987
988 #if COMPILER2_OR_JVMCI
989 int mvs_max = 0;
990 if (UseSSE < 2) {
991 // Vectors (in XMM) are only supported with SSE2+
992 // SSE is always 2 on x64.
993 mvs_max = 0;
994 } else if (UseAVX == 0 || !os_supports_avx_vectors()) {
995 // 16 byte vectors (in XMM) are supported with SSE2+
996 mvs_max = 16;
997 } else if (UseAVX == 1 || UseAVX == 2) {
998 // 32 bytes vectors (in YMM) are only supported with AVX+
999 mvs_max = 32;
1000 } else if (UseAVX > 2 ) {
1001 // 64 bytes vectors (in ZMM) are only supported with AVX 3
1002 mvs_max = 64;
1003 }
1004
1005 int mvs_min = 0;
1006 #ifdef _LP64
1007 mvs_min = 4; // We require MaxVectorSize to be at least 4 on 64bit
1008 #endif
1009
1010 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1011 if (MaxVectorSize < mvs_min) {
1012 warning("MaxVectorSize must be at least %i on this platform", mvs_min);
1013 FLAG_SET_DEFAULT(MaxVectorSize, mvs_min);
1014 }
1015 if (MaxVectorSize > mvs_max) {
1016 warning("MaxVectorSize must be at most %i on this platform", mvs_max);
1017 FLAG_SET_DEFAULT(MaxVectorSize, mvs_max);
1018 }
1019 if (!is_power_of_2(MaxVectorSize)) {
1020 warning("MaxVectorSize must be a power of 2, setting to default: %i", mvs_max);
1021 FLAG_SET_DEFAULT(MaxVectorSize, mvs_max);
1022 }
1023 } else {
1024 // If default, use highest supported configuration
1025 FLAG_SET_DEFAULT(MaxVectorSize, mvs_max);
1026 }
1027
1028 #if defined(COMPILER2) && defined(ASSERT)
1029 if (MaxVectorSize > 0) {
1030 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1031 tty->print_cr("State of YMM registers after signal handle:");
1032 int nreg = 2 LP64_ONLY(+2);
1033 const char* ymm_name[4] = {"0", "7", "8", "15"};
1034 for (int i = 0; i < nreg; i++) {
1035 tty->print("YMM%s:", ymm_name[i]);
1036 for (int j = 7; j >=0; j--) {
1037 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1038 }
1039 tty->cr();
1040 }
1041 }
1042 #endif // COMPILER2 && ASSERT
1043 }
1044 #endif // COMPILER2_OR_JVMCI
1045
1046 #ifdef COMPILER2
1047 #ifdef _LP64
1048 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1049 UseMultiplyToLenIntrinsic = true;
1050 }
1051 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1052 UseSquareToLenIntrinsic = true;
1053 }
1054 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1055 UseMulAddIntrinsic = true;
1056 }
1057 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1058 UseMontgomeryMultiplyIntrinsic = true;
1059 }
1060 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1061 UseMontgomerySquareIntrinsic = true;
1062 }
1063 #else
1064 if (UseMultiplyToLenIntrinsic) {
1065 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1066 warning("multiplyToLen intrinsic is not available in 32-bit VM");
1067 }
1068 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1069 }
1070 if (UseMontgomeryMultiplyIntrinsic) {
1071 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1072 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1073 }
1074 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1075 }
1076 if (UseMontgomerySquareIntrinsic) {
1077 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1078 warning("montgomerySquare intrinsic is not available in 32-bit VM");
1079 }
1080 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1081 }
1082 if (UseSquareToLenIntrinsic) {
1083 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1084 warning("squareToLen intrinsic is not available in 32-bit VM");
1085 }
1086 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1087 }
1088 if (UseMulAddIntrinsic) {
1089 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1090 warning("mulAdd intrinsic is not available in 32-bit VM");
1091 }
1092 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1093 }
1094 #endif
1095 #endif // COMPILER2
1096
1097 // On new cpus instructions which update whole XMM register should be used
1098 // to prevent partial register stall due to dependencies on high half.
1099 //
1100 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1101 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1102 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1103 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1104
1105
1106 if (is_zx()) { // ZX cpus specific settings
1107 if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1108 UseStoreImmI16 = false; // don't use it on ZX cpus
1109 }
1110 if ((cpu_family() == 6) || (cpu_family() == 7)) {
1111 if (FLAG_IS_DEFAULT(UseAddressNop)) {
1112 // Use it on all ZX cpus
1113 UseAddressNop = true;
1114 }
1115 }
1116 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1117 UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
1118 }
1119 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1120 if (supports_sse3()) {
1121 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
1122 } else {
1123 UseXmmRegToRegMoveAll = false;
1124 }
1125 }
1126 if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
1127 #ifdef COMPILER2
1128 if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1129 // For new ZX cpus do the next optimization:
1130 // don't align the beginning of a loop if there are enough instructions
1131 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1132 // in current fetch line (OptoLoopAlignment) or the padding
1133 // is big (> MaxLoopPad).
1134 // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
1135 // generated NOP instructions. 11 is the largest size of one
1136 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1137 MaxLoopPad = 11;
1138 }
1139 #endif // COMPILER2
1140 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1141 UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
1142 }
1143 if (supports_sse4_2()) { // new ZX cpus
1144 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1145 UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1146 }
1147 }
1148 if (supports_sse4_2()) {
1149 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1150 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1151 }
1152 } else {
1153 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1154 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1155 }
1156 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1157 }
1158 }
1159
1160 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1161 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1162 }
1163 }
1164
1165 if( is_amd() ) { // AMD cpus specific settings
1166 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1167 // Use it on new AMD cpus starting from Opteron.
1168 UseAddressNop = true;
1169 }
1170 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1171 // Use it on new AMD cpus starting from Opteron.
1172 UseNewLongLShift = true;
1173 }
1174 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1175 if (supports_sse4a()) {
1176 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1177 } else {
1178 UseXmmLoadAndClearUpper = false;
1179 }
1180 }
1181 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1182 if( supports_sse4a() ) {
1183 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1184 } else {
1185 UseXmmRegToRegMoveAll = false;
1186 }
1187 }
1188 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1189 if( supports_sse4a() ) {
1190 UseXmmI2F = true;
1191 } else {
1192 UseXmmI2F = false;
1193 }
1194 }
1195 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1196 if( supports_sse4a() ) {
1197 UseXmmI2D = true;
1198 } else {
1199 UseXmmI2D = false;
1200 }
1201 }
1202 if (supports_sse4_2()) {
1203 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1204 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1205 }
1206 } else {
1207 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1208 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1209 }
1210 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1211 }
1212
1213 // some defaults for AMD family 15h
1214 if ( cpu_family() == 0x15 ) {
1215 // On family 15h processors default is no sw prefetch
1216 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1217 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1218 }
1219 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1220 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1221 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1222 }
1223 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1224 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1225 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1226 }
1227 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1228 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1229 }
1230 }
1231
1232 #ifdef COMPILER2
1233 if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1234 // Limit vectors size to 16 bytes on AMD cpus < 17h.
1235 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1236 }
1237 #endif // COMPILER2
1238
1239 // Some defaults for AMD family 17h
1240 if ( cpu_family() == 0x17 ) {
1241 // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1242 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1243 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1244 }
1245 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1246 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1247 }
1248 #ifdef COMPILER2
1249 if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1250 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1251 }
1252 #endif
1253 }
1254 }
1255
1256 if( is_intel() ) { // Intel cpus specific settings
1257 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1258 UseStoreImmI16 = false; // don't use it on Intel cpus
1259 }
1260 if( cpu_family() == 6 || cpu_family() == 15 ) {
1261 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1262 // Use it on all Intel cpus starting from PentiumPro
1263 UseAddressNop = true;
1264 }
1265 }
1266 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1267 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1268 }
1269 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1270 if( supports_sse3() ) {
1271 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1272 } else {
1273 UseXmmRegToRegMoveAll = false;
1274 }
1275 }
1276 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1277 #ifdef COMPILER2
1278 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1279 // For new Intel cpus do the next optimization:
1280 // don't align the beginning of a loop if there are enough instructions
1281 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1282 // in current fetch line (OptoLoopAlignment) or the padding
1283 // is big (> MaxLoopPad).
1284 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1285 // generated NOP instructions. 11 is the largest size of one
1286 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1287 MaxLoopPad = 11;
1288 }
1289 #endif // COMPILER2
1290 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1291 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1292 }
1293 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1294 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1295 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1296 }
1297 }
1298 if (supports_sse4_2()) {
1299 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1300 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1301 }
1302 } else {
1303 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1304 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1305 }
1306 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1307 }
1308 }
1309 if (is_atom_family() || is_knights_family()) {
1310 #ifdef COMPILER2
1311 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1312 OptoScheduling = true;
1313 }
1314 #endif
1315 if (supports_sse4_2()) { // Silvermont
1316 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1317 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1318 }
1319 }
1320 if (FLAG_IS_DEFAULT(UseIncDec)) {
1321 FLAG_SET_DEFAULT(UseIncDec, false);
1322 }
1323 }
1324 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1325 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1326 }
1327 }
1328
1329 #ifdef _LP64
1330 if (UseSSE42Intrinsics) {
1331 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1332 UseVectorizedMismatchIntrinsic = true;
1333 }
1334 } else if (UseVectorizedMismatchIntrinsic) {
1335 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1336 warning("vectorizedMismatch intrinsics are not available on this CPU");
1337 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1338 }
1339 #else
1340 if (UseVectorizedMismatchIntrinsic) {
1341 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1342 warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1343 }
1344 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1345 }
1346 #endif // _LP64
1347
1348 // Use count leading zeros count instruction if available.
1349 if (supports_lzcnt()) {
1350 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1351 UseCountLeadingZerosInstruction = true;
1352 }
1353 } else if (UseCountLeadingZerosInstruction) {
1354 warning("lzcnt instruction is not available on this CPU");
1355 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1356 }
1357
1358 // Use count trailing zeros instruction if available
1359 if (supports_bmi1()) {
1360 // tzcnt does not require VEX prefix
1361 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1362 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1363 // Don't use tzcnt if BMI1 is switched off on command line.
1364 UseCountTrailingZerosInstruction = false;
1365 } else {
1366 UseCountTrailingZerosInstruction = true;
1367 }
1368 }
1369 } else if (UseCountTrailingZerosInstruction) {
1370 warning("tzcnt instruction is not available on this CPU");
1371 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1372 }
1373
1374 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1375 // VEX prefix is generated only when AVX > 0.
1376 if (supports_bmi1() && supports_avx()) {
1377 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1378 UseBMI1Instructions = true;
1379 }
1380 } else if (UseBMI1Instructions) {
1381 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1382 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1383 }
1384
1385 if (supports_bmi2() && supports_avx()) {
1386 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1387 UseBMI2Instructions = true;
1388 }
1389 } else if (UseBMI2Instructions) {
1390 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1391 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1392 }
1393
1394 // Use population count instruction if available.
1395 if (supports_popcnt()) {
1396 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1397 UsePopCountInstruction = true;
1398 }
1399 } else if (UsePopCountInstruction) {
1400 warning("POPCNT instruction is not available on this CPU");
1401 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1402 }
1403
1404 // Use fast-string operations if available.
1405 if (supports_erms()) {
1406 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1407 UseFastStosb = true;
1408 }
1409 } else if (UseFastStosb) {
1410 warning("fast-string operations are not available on this CPU");
1411 FLAG_SET_DEFAULT(UseFastStosb, false);
1412 }
1413
1414 // Use XMM/YMM MOVDQU instruction for Object Initialization
1415 if (!UseFastStosb && UseSSE >= 2 && UseUnalignedLoadStores) {
1416 if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1417 UseXMMForObjInit = true;
1418 }
1419 } else if (UseXMMForObjInit) {
1420 warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1421 FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1422 }
1423
1424 #ifdef COMPILER2
1425 if (FLAG_IS_DEFAULT(AlignVector)) {
1426 // Modern processors allow misaligned memory operations for vectors.
1427 AlignVector = !UseUnalignedLoadStores;
1428 }
1429 #endif // COMPILER2
1430
1431 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1432 if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1433 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1434 } else if (!supports_sse() && supports_3dnow_prefetch()) {
1435 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1436 }
1437 }
1438
1439 // Allocation prefetch settings
1440 intx cache_line_size = prefetch_data_size();
1441 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1442 (cache_line_size > AllocatePrefetchStepSize)) {
1443 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1444 }
1445
1446 if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1447 assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1448 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1449 warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1450 }
1451 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1452 }
1453
1454 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1455 bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1456 FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1457 }
1458
1459 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1460 if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1461 supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1462 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1463 }
1464 #ifdef COMPILER2
1465 if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1466 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1467 }
1468 #endif
1469 }
1470
1471 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1472 #ifdef COMPILER2
1473 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1474 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1475 }
1476 #endif
1477 }
1478
1479 #ifdef _LP64
1480 // Prefetch settings
1481
1482 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
1483 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1484 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1485 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1486
1487 // gc copy/scan is disabled if prefetchw isn't supported, because
1488 // Prefetch::write emits an inlined prefetchw on Linux.
1489 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
1490 // The used prefetcht0 instruction works for both amd64 and em64t.
1491
1492 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1493 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1494 }
1495 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1496 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1497 }
1498 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1499 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1500 }
1501 #endif
1502
1503 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1504 (cache_line_size > ContendedPaddingWidth))
1505 ContendedPaddingWidth = cache_line_size;
1506
1507 // This machine allows unaligned memory accesses
1508 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1509 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1510 }
1511
1512 #ifndef PRODUCT
1513 if (log_is_enabled(Info, os, cpu)) {
1514 LogStream ls(Log(os, cpu)::info());
1515 outputStream* log = &ls;
1516 log->print_cr("Logical CPUs per core: %u",
1517 logical_processors_per_package());
1518 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1519 log->print("UseSSE=%d", (int) UseSSE);
1520 if (UseAVX > 0) {
1521 log->print(" UseAVX=%d", (int) UseAVX);
1522 }
1523 if (UseAES) {
1524 log->print(" UseAES=1");
1525 }
1526 #ifdef COMPILER2
1527 if (MaxVectorSize > 0) {
1528 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1529 }
1530 #endif
1531 log->cr();
1532 log->print("Allocation");
1533 if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1534 log->print_cr(": no prefetching");
1535 } else {
1536 log->print(" prefetching: ");
1537 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1538 log->print("PREFETCHW");
1539 } else if (UseSSE >= 1) {
1540 if (AllocatePrefetchInstr == 0) {
1541 log->print("PREFETCHNTA");
1542 } else if (AllocatePrefetchInstr == 1) {
1543 log->print("PREFETCHT0");
1544 } else if (AllocatePrefetchInstr == 2) {
1545 log->print("PREFETCHT2");
1546 } else if (AllocatePrefetchInstr == 3) {
1547 log->print("PREFETCHW");
1548 }
1549 }
1550 if (AllocatePrefetchLines > 1) {
1551 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1552 } else {
1553 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1554 }
1555 }
1556
1557 if (PrefetchCopyIntervalInBytes > 0) {
1558 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1559 }
1560 if (PrefetchScanIntervalInBytes > 0) {
1561 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1562 }
1563 if (PrefetchFieldsAhead > 0) {
1564 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1565 }
1566 if (ContendedPaddingWidth > 0) {
1567 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1568 }
1569 }
1570 #endif // !PRODUCT
1571 }
1572
1573 bool VM_Version::use_biased_locking() {
1574 #if INCLUDE_RTM_OPT
1575 // RTM locking is most useful when there is high lock contention and
1576 // low data contention. With high lock contention the lock is usually
1577 // inflated and biased locking is not suitable for that case.
1578 // RTM locking code requires that biased locking is off.
1579 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1580 // because it is used by Thread::allocate() which is called before
1581 // VM_Version::initialize().
1582 if (UseRTMLocking && UseBiasedLocking) {
1583 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1584 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1585 } else {
1586 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1587 UseBiasedLocking = false;
1588 }
1589 }
1590 #endif
1591 return UseBiasedLocking;
1592 }
1593
1594 void VM_Version::initialize() {
1595 ResourceMark rm;
1596 // Making this stub must be FIRST use of assembler
1597
1598 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1599 if (stub_blob == NULL) {
1600 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1601 }
1602 CodeBuffer c(stub_blob);
1603 VM_Version_StubGenerator g(&c);
1604 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1605 g.generate_get_cpu_info());
1606
1607 get_processor_features();
1608 }