896 // double can interfere with TWO aligned pairs, or effectively
897 // FOUR registers!
898 if (rm.is_misaligned_pair()) {
899 lrg._fat_proj = 1;
900 lrg._is_bound = 1;
901 }
902 break;
903 case Op_RegF:
904 case Op_RegI:
905 case Op_RegN:
906 case Op_RegFlags:
907 case 0: // not an ideal register
908 lrg.set_num_regs(1);
909 #ifdef SPARC
910 lrg.set_reg_pressure(2);
911 #else
912 lrg.set_reg_pressure(1);
913 #endif
914 break;
915 case Op_VecS:
916 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
917 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
918 lrg.set_num_regs(RegMask::SlotsPerVecS);
919 lrg.set_reg_pressure(1);
920 break;
921 case Op_VecD:
922 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
923 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
924 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
925 lrg.set_num_regs(RegMask::SlotsPerVecD);
926 lrg.set_reg_pressure(1);
927 break;
928 case Op_VecX:
929 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
930 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
931 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
932 lrg.set_num_regs(RegMask::SlotsPerVecX);
933 lrg.set_reg_pressure(1);
934 break;
935 case Op_VecY:
936 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
937 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
938 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
939 lrg.set_num_regs(RegMask::SlotsPerVecY);
940 lrg.set_reg_pressure(1);
941 break;
942 case Op_VecZ:
943 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity");
944 assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
945 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
946 lrg.set_num_regs(RegMask::SlotsPerVecZ);
947 lrg.set_reg_pressure(1);
948 break;
949 default:
950 ShouldNotReachHere();
951 }
952 }
953
954 // Now do the same for inputs
955 uint cnt = n->req();
956 // Setup for CISC SPILLING
957 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
958 if( UseCISCSpill && after_aggressive ) {
959 inp = n->cisc_operand();
960 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
961 // Convert operand number to edge index number
962 inp = n->as_Mach()->operand_index(inp);
963 }
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896 // double can interfere with TWO aligned pairs, or effectively
897 // FOUR registers!
898 if (rm.is_misaligned_pair()) {
899 lrg._fat_proj = 1;
900 lrg._is_bound = 1;
901 }
902 break;
903 case Op_RegF:
904 case Op_RegI:
905 case Op_RegN:
906 case Op_RegFlags:
907 case 0: // not an ideal register
908 lrg.set_num_regs(1);
909 #ifdef SPARC
910 lrg.set_reg_pressure(2);
911 #else
912 lrg.set_reg_pressure(1);
913 #endif
914 break;
915 case Op_VecS:
916 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
917 lrg.set_num_regs(RegMask::SlotsPerVecS);
918 lrg.set_reg_pressure(1);
919 break;
920 case Op_VecD:
921 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
922 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
923 lrg.set_num_regs(RegMask::SlotsPerVecD);
924 lrg.set_reg_pressure(1);
925 break;
926 case Op_VecX:
927 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
928 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
929 lrg.set_num_regs(RegMask::SlotsPerVecX);
930 lrg.set_reg_pressure(1);
931 break;
932 case Op_VecY:
933 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
934 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
935 lrg.set_num_regs(RegMask::SlotsPerVecY);
936 lrg.set_reg_pressure(1);
937 break;
938 case Op_VecZ:
939 assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
940 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
941 lrg.set_num_regs(RegMask::SlotsPerVecZ);
942 lrg.set_reg_pressure(1);
943 break;
944 default:
945 ShouldNotReachHere();
946 }
947 }
948
949 // Now do the same for inputs
950 uint cnt = n->req();
951 // Setup for CISC SPILLING
952 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
953 if( UseCISCSpill && after_aggressive ) {
954 inp = n->cisc_operand();
955 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
956 // Convert operand number to edge index number
957 inp = n->as_Mach()->operand_index(inp);
958 }
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