1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP 27 28 #include "asm/register.hpp" 29 30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction 31 // level; i.e., what you write is what you get. The Assembler is generating code 32 // into a CodeBuffer. 33 34 class Assembler : public AbstractAssembler { 35 friend class AbstractAssembler; 36 friend class AddressLiteral; 37 38 // code patchers need various routines like inv_wdisp() 39 friend class NativeInstruction; 40 friend class NativeGeneralJump; 41 friend class Relocation; 42 friend class Label; 43 44 public: 45 // op carries format info; see page 62 & 267 46 47 enum ops { 48 call_op = 1, // fmt 1 49 branch_op = 0, // also sethi (fmt2) 50 arith_op = 2, // fmt 3, arith & misc 51 ldst_op = 3 // fmt 3, load/store 52 }; 53 54 enum op2s { 55 bpr_op2 = 3, 56 fb_op2 = 6, 57 fbp_op2 = 5, 58 br_op2 = 2, 59 bp_op2 = 1, 60 sethi_op2 = 4 61 }; 62 63 enum op3s { 64 // selected op3s 65 add_op3 = 0x00, 66 and_op3 = 0x01, 67 or_op3 = 0x02, 68 xor_op3 = 0x03, 69 sub_op3 = 0x04, 70 andn_op3 = 0x05, 71 orn_op3 = 0x06, 72 xnor_op3 = 0x07, 73 addc_op3 = 0x08, 74 mulx_op3 = 0x09, 75 umul_op3 = 0x0a, 76 smul_op3 = 0x0b, 77 subc_op3 = 0x0c, 78 udivx_op3 = 0x0d, 79 udiv_op3 = 0x0e, 80 sdiv_op3 = 0x0f, 81 82 addcc_op3 = 0x10, 83 andcc_op3 = 0x11, 84 orcc_op3 = 0x12, 85 xorcc_op3 = 0x13, 86 subcc_op3 = 0x14, 87 andncc_op3 = 0x15, 88 orncc_op3 = 0x16, 89 xnorcc_op3 = 0x17, 90 addccc_op3 = 0x18, 91 aes4_op3 = 0x19, 92 umulcc_op3 = 0x1a, 93 smulcc_op3 = 0x1b, 94 subccc_op3 = 0x1c, 95 udivcc_op3 = 0x1e, 96 sdivcc_op3 = 0x1f, 97 98 taddcc_op3 = 0x20, 99 tsubcc_op3 = 0x21, 100 taddcctv_op3 = 0x22, 101 tsubcctv_op3 = 0x23, 102 mulscc_op3 = 0x24, 103 sll_op3 = 0x25, 104 sllx_op3 = 0x25, 105 srl_op3 = 0x26, 106 srlx_op3 = 0x26, 107 sra_op3 = 0x27, 108 srax_op3 = 0x27, 109 rdreg_op3 = 0x28, 110 membar_op3 = 0x28, 111 112 flushw_op3 = 0x2b, 113 movcc_op3 = 0x2c, 114 sdivx_op3 = 0x2d, 115 popc_op3 = 0x2e, 116 movr_op3 = 0x2f, 117 118 sir_op3 = 0x30, 119 wrreg_op3 = 0x30, 120 saved_op3 = 0x31, 121 122 fpop1_op3 = 0x34, 123 fpop2_op3 = 0x35, 124 impdep1_op3 = 0x36, 125 aes3_op3 = 0x36, 126 sha_op3 = 0x36, 127 bmask_op3 = 0x36, 128 bshuffle_op3 = 0x36, 129 alignaddr_op3 = 0x36, 130 faligndata_op3 = 0x36, 131 flog3_op3 = 0x36, 132 edge_op3 = 0x36, 133 fzero_op3 = 0x36, 134 fsrc_op3 = 0x36, 135 fnot_op3 = 0x36, 136 xmulx_op3 = 0x36, 137 crc32c_op3 = 0x36, 138 impdep2_op3 = 0x37, 139 stpartialf_op3 = 0x37, 140 jmpl_op3 = 0x38, 141 rett_op3 = 0x39, 142 trap_op3 = 0x3a, 143 flush_op3 = 0x3b, 144 save_op3 = 0x3c, 145 restore_op3 = 0x3d, 146 done_op3 = 0x3e, 147 retry_op3 = 0x3e, 148 149 lduw_op3 = 0x00, 150 ldub_op3 = 0x01, 151 lduh_op3 = 0x02, 152 ldd_op3 = 0x03, 153 stw_op3 = 0x04, 154 stb_op3 = 0x05, 155 sth_op3 = 0x06, 156 std_op3 = 0x07, 157 ldsw_op3 = 0x08, 158 ldsb_op3 = 0x09, 159 ldsh_op3 = 0x0a, 160 ldx_op3 = 0x0b, 161 162 stx_op3 = 0x0e, 163 swap_op3 = 0x0f, 164 165 stwa_op3 = 0x14, 166 stxa_op3 = 0x1e, 167 168 ldf_op3 = 0x20, 169 ldfsr_op3 = 0x21, 170 ldqf_op3 = 0x22, 171 lddf_op3 = 0x23, 172 stf_op3 = 0x24, 173 stfsr_op3 = 0x25, 174 stqf_op3 = 0x26, 175 stdf_op3 = 0x27, 176 177 prefetch_op3 = 0x2d, 178 179 casa_op3 = 0x3c, 180 casxa_op3 = 0x3e, 181 182 mftoi_op3 = 0x36, 183 184 alt_bit_op3 = 0x10, 185 cc_bit_op3 = 0x10 186 }; 187 188 enum opfs { 189 // selected opfs 190 edge8n_opf = 0x01, 191 192 fmovs_opf = 0x01, 193 fmovd_opf = 0x02, 194 195 fnegs_opf = 0x05, 196 fnegd_opf = 0x06, 197 198 alignaddr_opf = 0x18, 199 bmask_opf = 0x19, 200 201 fadds_opf = 0x41, 202 faddd_opf = 0x42, 203 fsubs_opf = 0x45, 204 fsubd_opf = 0x46, 205 206 faligndata_opf = 0x48, 207 208 fmuls_opf = 0x49, 209 fmuld_opf = 0x4a, 210 bshuffle_opf = 0x4c, 211 fdivs_opf = 0x4d, 212 fdivd_opf = 0x4e, 213 214 fcmps_opf = 0x51, 215 fcmpd_opf = 0x52, 216 217 fstox_opf = 0x81, 218 fdtox_opf = 0x82, 219 fxtos_opf = 0x84, 220 fxtod_opf = 0x88, 221 fitos_opf = 0xc4, 222 fdtos_opf = 0xc6, 223 fitod_opf = 0xc8, 224 fstod_opf = 0xc9, 225 fstoi_opf = 0xd1, 226 fdtoi_opf = 0xd2, 227 228 mdtox_opf = 0x110, 229 mstouw_opf = 0x111, 230 mstosw_opf = 0x113, 231 xmulx_opf = 0x115, 232 xmulxhi_opf = 0x116, 233 mxtod_opf = 0x118, 234 mwtos_opf = 0x119, 235 236 aes_kexpand0_opf = 0x130, 237 aes_kexpand2_opf = 0x131, 238 239 sha1_opf = 0x141, 240 sha256_opf = 0x142, 241 sha512_opf = 0x143, 242 243 crc32c_opf = 0x147 244 }; 245 246 enum op5s { 247 aes_eround01_op5 = 0x00, 248 aes_eround23_op5 = 0x01, 249 aes_dround01_op5 = 0x02, 250 aes_dround23_op5 = 0x03, 251 aes_eround01_l_op5 = 0x04, 252 aes_eround23_l_op5 = 0x05, 253 aes_dround01_l_op5 = 0x06, 254 aes_dround23_l_op5 = 0x07, 255 aes_kexpand1_op5 = 0x08 256 }; 257 258 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez }; 259 260 enum Condition { 261 // for FBfcc & FBPfcc instruction 262 f_never = 0, 263 f_notEqual = 1, 264 f_notZero = 1, 265 f_lessOrGreater = 2, 266 f_unorderedOrLess = 3, 267 f_less = 4, 268 f_unorderedOrGreater = 5, 269 f_greater = 6, 270 f_unordered = 7, 271 f_always = 8, 272 f_equal = 9, 273 f_zero = 9, 274 f_unorderedOrEqual = 10, 275 f_greaterOrEqual = 11, 276 f_unorderedOrGreaterOrEqual = 12, 277 f_lessOrEqual = 13, 278 f_unorderedOrLessOrEqual = 14, 279 f_ordered = 15, 280 281 // for integers 282 283 never = 0, 284 equal = 1, 285 zero = 1, 286 lessEqual = 2, 287 less = 3, 288 lessEqualUnsigned = 4, 289 lessUnsigned = 5, 290 carrySet = 5, 291 negative = 6, 292 overflowSet = 7, 293 always = 8, 294 notEqual = 9, 295 notZero = 9, 296 greater = 10, 297 greaterEqual = 11, 298 greaterUnsigned = 12, 299 greaterEqualUnsigned = 13, 300 carryClear = 13, 301 positive = 14, 302 overflowClear = 15 303 }; 304 305 enum CC { 306 // ptr_cc is the correct condition code for a pointer or intptr_t: 307 icc = 0, xcc = 2, ptr_cc = xcc, 308 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 309 }; 310 311 enum PrefetchFcn { 312 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 313 }; 314 315 public: 316 // Helper functions for groups of instructions 317 318 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 319 320 enum Membar_mask_bits { // page 184, v9 321 StoreStore = 1 << 3, 322 LoadStore = 1 << 2, 323 StoreLoad = 1 << 1, 324 LoadLoad = 1 << 0, 325 326 Sync = 1 << 6, 327 MemIssue = 1 << 5, 328 Lookaside = 1 << 4 329 }; 330 331 static bool is_in_wdisp_range(address a, address b, int nbits) { 332 intptr_t d = intptr_t(b) - intptr_t(a); 333 return is_simm(d, nbits + 2); 334 } 335 336 address target_distance(Label &L) { 337 // Assembler::target(L) should be called only when 338 // a branch instruction is emitted since non-bound 339 // labels record current pc() as a branch address. 340 if (L.is_bound()) return target(L); 341 // Return current address for non-bound labels. 342 return pc(); 343 } 344 345 // test if label is in simm16 range in words (wdisp16). 346 bool is_in_wdisp16_range(Label &L) { 347 return is_in_wdisp_range(target_distance(L), pc(), 16); 348 } 349 // test if the distance between two addresses fits in simm30 range in words 350 static bool is_in_wdisp30_range(address a, address b) { 351 return is_in_wdisp_range(a, b, 30); 352 } 353 354 enum ASIs { // page 72, v9 355 ASI_PRIMARY = 0x80, 356 ASI_PRIMARY_NOFAULT = 0x82, 357 ASI_PRIMARY_LITTLE = 0x88, 358 // 8x8-bit partial store 359 ASI_PST8_PRIMARY = 0xC0, 360 // Block initializing store 361 ASI_ST_BLKINIT_PRIMARY = 0xE2, 362 // Most-Recently-Used (MRU) BIS variant 363 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2 364 // add more from book as needed 365 }; 366 367 protected: 368 // helpers 369 370 // x is supposed to fit in a field "nbits" wide 371 // and be sign-extended. Check the range. 372 373 static void assert_signed_range(intptr_t x, int nbits) { 374 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 375 "value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits); 376 } 377 378 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 379 assert((x & 3) == 0, "not word aligned"); 380 assert_signed_range(x, nbits + 2); 381 } 382 383 static void assert_unsigned_const(int x, int nbits) { 384 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); 385 } 386 387 // fields: note bits numbered from LSB = 0, fields known by inclusive bit range 388 389 static int fmask(juint hi_bit, juint lo_bit) { 390 assert(hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); 391 return (1 << (hi_bit-lo_bit + 1)) - 1; 392 } 393 394 // inverse of u_field 395 396 static int inv_u_field(int x, int hi_bit, int lo_bit) { 397 juint r = juint(x) >> lo_bit; 398 r &= fmask(hi_bit, lo_bit); 399 return int(r); 400 } 401 402 // signed version: extract from field and sign-extend 403 404 static int inv_s_field(int x, int hi_bit, int lo_bit) { 405 int sign_shift = 31 - hi_bit; 406 return inv_u_field(((x << sign_shift) >> sign_shift), hi_bit, lo_bit); 407 } 408 409 // given a field that ranges from hi_bit to lo_bit (inclusive, 410 // LSB = 0), and an unsigned value for the field, 411 // shift it into the field 412 413 #ifdef ASSERT 414 static int u_field(int x, int hi_bit, int lo_bit) { 415 assert((x & ~fmask(hi_bit, lo_bit)) == 0, 416 "value out of range"); 417 int r = x << lo_bit; 418 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 419 return r; 420 } 421 #else 422 // make sure this is inlined as it will reduce code size significantly 423 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) 424 #endif 425 426 static int inv_op(int x) { return inv_u_field(x, 31, 30); } 427 static int inv_op2(int x) { return inv_u_field(x, 24, 22); } 428 static int inv_op3(int x) { return inv_u_field(x, 24, 19); } 429 static int inv_cond(int x) { return inv_u_field(x, 28, 25); } 430 431 static bool inv_immed(int x) { return (x & Assembler::immed(true)) != 0; } 432 433 static Register inv_rd(int x) { return as_Register(inv_u_field(x, 29, 25)); } 434 static Register inv_rs1(int x) { return as_Register(inv_u_field(x, 18, 14)); } 435 static Register inv_rs2(int x) { return as_Register(inv_u_field(x, 4, 0)); } 436 437 static int op(int x) { return u_field(x, 31, 30); } 438 static int rd(Register r) { return u_field(r->encoding(), 29, 25); } 439 static int fcn(int x) { return u_field(x, 29, 25); } 440 static int op3(int x) { return u_field(x, 24, 19); } 441 static int rs1(Register r) { return u_field(r->encoding(), 18, 14); } 442 static int rs2(Register r) { return u_field(r->encoding(), 4, 0); } 443 static int annul(bool a) { return u_field(a ? 1 : 0, 29, 29); } 444 static int cond(int x) { return u_field(x, 28, 25); } 445 static int cond_mov(int x) { return u_field(x, 17, 14); } 446 static int rcond(RCondition x) { return u_field(x, 12, 10); } 447 static int op2(int x) { return u_field(x, 24, 22); } 448 static int predict(bool p) { return u_field(p ? 1 : 0, 19, 19); } 449 static int branchcc(CC fcca) { return u_field(fcca, 21, 20); } 450 static int cmpcc(CC fcca) { return u_field(fcca, 26, 25); } 451 static int imm_asi(int x) { return u_field(x, 12, 5); } 452 static int immed(bool i) { return u_field(i ? 1 : 0, 13, 13); } 453 static int opf_low6(int w) { return u_field(w, 10, 5); } 454 static int opf_low5(int w) { return u_field(w, 9, 5); } 455 static int op5(int x) { return u_field(x, 8, 5); } 456 static int trapcc(CC cc) { return u_field(cc, 12, 11); } 457 static int sx(int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit 458 static int opf(int x) { return u_field(x, 13, 5); } 459 460 static bool is_cbcond(int x) { 461 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) && 462 inv_op(x) == branch_op && inv_op2(x) == bpr_op2); 463 } 464 static bool is_cxb(int x) { 465 assert(is_cbcond(x), "wrong instruction"); 466 return (x & (1 << 21)) != 0; 467 } 468 static int cond_cbcond(int x) { return u_field((((x & 8) << 1) + 8 + (x & 7)), 29, 25); } 469 static int inv_cond_cbcond(int x) { 470 assert(is_cbcond(x), "wrong instruction"); 471 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29) << 3); 472 } 473 474 static int opf_cc(CC c, bool useFloat) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } 475 static int mov_cc(CC c, bool useFloat) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } 476 477 static int fd(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; 478 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; 479 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; 480 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); }; 481 482 // some float instructions use this encoding on the op3 field 483 static int alt_op3(int op, FloatRegisterImpl::Width w) { 484 int r; 485 switch(w) { 486 case FloatRegisterImpl::S: r = op + 0; break; 487 case FloatRegisterImpl::D: r = op + 3; break; 488 case FloatRegisterImpl::Q: r = op + 2; break; 489 default: ShouldNotReachHere(); break; 490 } 491 return op3(r); 492 } 493 494 // compute inverse of simm 495 static int inv_simm(int x, int nbits) { 496 return (int)(x << (32 - nbits)) >> (32 - nbits); 497 } 498 499 static int inv_simm13(int x) { return inv_simm(x, 13); } 500 501 // signed immediate, in low bits, nbits long 502 static int simm(int x, int nbits) { 503 assert_signed_range(x, nbits); 504 return x & ((1 << nbits) - 1); 505 } 506 507 // compute inverse of wdisp16 508 static intptr_t inv_wdisp16(int x, intptr_t pos) { 509 int lo = x & ((1 << 14) - 1); 510 int hi = (x >> 20) & 3; 511 if (hi >= 2) hi |= ~1; 512 return (((hi << 14) | lo) << 2) + pos; 513 } 514 515 // word offset, 14 bits at LSend, 2 bits at B21, B20 516 static int wdisp16(intptr_t x, intptr_t off) { 517 intptr_t xx = x - off; 518 assert_signed_word_disp_range(xx, 16); 519 int r = (xx >> 2) & ((1 << 14) - 1) | (((xx >> (2+14)) & 3) << 20); 520 assert(inv_wdisp16(r, off) == x, "inverse is not inverse"); 521 return r; 522 } 523 524 // compute inverse of wdisp10 525 static intptr_t inv_wdisp10(int x, intptr_t pos) { 526 assert(is_cbcond(x), "wrong instruction"); 527 int lo = inv_u_field(x, 12, 5); 528 int hi = (x >> 19) & 3; 529 if (hi >= 2) hi |= ~1; 530 return (((hi << 8) | lo) << 2) + pos; 531 } 532 533 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19] 534 static int wdisp10(intptr_t x, intptr_t off) { 535 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction"); 536 intptr_t xx = x - off; 537 assert_signed_word_disp_range(xx, 10); 538 int r = (((xx >> 2) & ((1 << 8) - 1)) << 5) | (((xx >> (2+8)) & 3) << 19); 539 // Have to fake cbcond instruction to pass assert in inv_wdisp10() 540 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse"); 541 return r; 542 } 543 544 // word displacement in low-order nbits bits 545 546 static intptr_t inv_wdisp(int x, intptr_t pos, int nbits) { 547 int pre_sign_extend = x & ((1 << nbits) - 1); 548 int r = (pre_sign_extend >= (1 << (nbits - 1)) ? 549 pre_sign_extend | ~((1 << nbits) - 1) : pre_sign_extend); 550 return (r << 2) + pos; 551 } 552 553 static int wdisp(intptr_t x, intptr_t off, int nbits) { 554 intptr_t xx = x - off; 555 assert_signed_word_disp_range(xx, nbits); 556 int r = (xx >> 2) & ((1 << nbits) - 1); 557 assert(inv_wdisp(r, off, nbits) == x, "inverse not inverse"); 558 return r; 559 } 560 561 562 // Extract the top 32 bits in a 64 bit word 563 static int32_t hi32(int64_t x) { 564 int32_t r = int32_t((uint64_t)x >> 32); 565 return r; 566 } 567 568 // given a sethi instruction, extract the constant, left-justified 569 static int inv_hi22(int x) { 570 return x << 10; 571 } 572 573 // create an imm22 field, given a 32-bit left-justified constant 574 static int hi22(int x) { 575 int r = int(juint(x) >> 10); 576 assert((r & ~((1 << 22) - 1)) == 0, "just checkin'"); 577 return r; 578 } 579 580 // create a low10 __value__ (not a field) for a given a 32-bit constant 581 static int low10(int x) { 582 return x & ((1 << 10) - 1); 583 } 584 585 // create a low12 __value__ (not a field) for a given a 32-bit constant 586 static int low12(int x) { 587 return x & ((1 << 12) - 1); 588 } 589 590 // AES crypto instructions supported only on certain processors 591 static void aes_only() { assert(VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); } 592 593 // SHA crypto instructions supported only on certain processors 594 static void sha1_only() { assert(VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); } 595 static void sha256_only() { assert(VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); } 596 static void sha512_only() { assert(VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); } 597 598 // CRC32C instruction supported only on certain processors 599 static void crc32c_only() { assert(VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); } 600 601 // instruction only in VIS1 602 static void vis1_only() { assert(VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); } 603 604 // instruction only in VIS2 605 static void vis2_only() { assert(VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); } 606 607 // instruction only in VIS3 608 static void vis3_only() { assert(VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } 609 610 // instruction deprecated in v9 611 static void v9_dep() { } // do nothing for now 612 613 protected: 614 // Simple delay-slot scheme: 615 // In order to check the programmer, the assembler keeps track of delay slots. 616 // It forbids CTIs in delay slots (conservative, but should be OK). 617 // Also, when putting an instruction into a delay slot, you must say 618 // asm->delayed()->add(...), in order to check that you don't omit 619 // delay-slot instructions. 620 // To implement this, we use a simple FSA 621 622 #ifdef ASSERT 623 #define CHECK_DELAY 624 #endif 625 #ifdef CHECK_DELAY 626 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; 627 #endif 628 629 public: 630 // Tells assembler next instruction must NOT be in delay slot. 631 // Use at start of multinstruction macros. 632 void assert_not_delayed() { 633 // This is a separate overloading to avoid creation of string constants 634 // in non-asserted code--with some compilers this pollutes the object code. 635 #ifdef CHECK_DELAY 636 assert_not_delayed("next instruction should not be a delay slot"); 637 #endif 638 } 639 void assert_not_delayed(const char* msg) { 640 #ifdef CHECK_DELAY 641 assert(delay_state == no_delay, msg); 642 #endif 643 } 644 645 protected: 646 // Insert a nop if the previous is cbcond 647 inline void insert_nop_after_cbcond(); 648 649 // Delay slot helpers 650 // cti is called when emitting control-transfer instruction, 651 // BEFORE doing the emitting. 652 // Only effective when assertion-checking is enabled. 653 void cti() { 654 // A cbcond instruction immediately followed by a CTI 655 // instruction introduces pipeline stalls, we need to avoid that. 656 no_cbcond_before(); 657 #ifdef CHECK_DELAY 658 assert_not_delayed("cti should not be in delay slot"); 659 #endif 660 } 661 662 // called when emitting cti with a delay slot, AFTER emitting 663 void has_delay_slot() { 664 #ifdef CHECK_DELAY 665 assert_not_delayed("just checking"); 666 delay_state = at_delay_slot; 667 #endif 668 } 669 670 // cbcond instruction should not be generated one after an other 671 bool cbcond_before() { 672 if (offset() == 0) return false; // it is first instruction 673 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction 674 return is_cbcond(x); 675 } 676 677 void no_cbcond_before() { 678 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond"); 679 } 680 public: 681 682 bool use_cbcond(Label &L) { 683 if (!UseCBCond || cbcond_before()) return false; 684 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc()); 685 assert((x & 3) == 0, "not word aligned"); 686 return is_simm12(x); 687 } 688 689 // Tells assembler you know that next instruction is delayed 690 Assembler* delayed() { 691 #ifdef CHECK_DELAY 692 assert(delay_state == at_delay_slot, "delayed instruction is not in delay slot"); 693 delay_state = filling_delay_slot; 694 #endif 695 return this; 696 } 697 698 void flush() { 699 #ifdef CHECK_DELAY 700 assert(delay_state == no_delay, "ending code with a delay slot"); 701 #endif 702 AbstractAssembler::flush(); 703 } 704 705 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 706 inline void emit_data(int); 707 inline void emit_data(int, RelocationHolder const &rspec); 708 inline void emit_data(int, relocInfo::relocType rtype); 709 // helper for above functions 710 inline void check_delay(); 711 712 713 public: 714 // instructions, refer to page numbers in the SPARC Architecture Manual, V9 715 716 // pp 135 717 718 inline void add(Register s1, Register s2, Register d); 719 inline void add(Register s1, int simm13a, Register d); 720 721 inline void addcc(Register s1, Register s2, Register d); 722 inline void addcc(Register s1, int simm13a, Register d); 723 inline void addc(Register s1, Register s2, Register d); 724 inline void addc(Register s1, int simm13a, Register d); 725 inline void addccc(Register s1, Register s2, Register d); 726 inline void addccc(Register s1, int simm13a, Register d); 727 728 729 // 4-operand AES instructions 730 731 inline void aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); 732 inline void aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); 733 inline void aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); 734 inline void aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); 735 inline void aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); 736 inline void aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); 737 inline void aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); 738 inline void aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); 739 inline void aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d); 740 741 742 // 3-operand AES instructions 743 744 inline void aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d); 745 inline void aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d); 746 747 // pp 136 748 749 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none); 750 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label &L); 751 752 // compare and branch 753 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label &L); 754 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label &L); 755 756 protected: // use MacroAssembler::br instead 757 758 // pp 138 759 760 inline void fb(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none); 761 inline void fb(Condition c, bool a, Label &L); 762 763 // pp 141 764 765 inline void fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none); 766 inline void fbp(Condition c, bool a, CC cc, Predict p, Label &L); 767 768 // pp 144 769 770 inline void br(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none); 771 inline void br(Condition c, bool a, Label &L); 772 773 // pp 146 774 775 inline void bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none); 776 inline void bp(Condition c, bool a, CC cc, Predict p, Label &L); 777 778 // pp 149 779 780 inline void call(address d, relocInfo::relocType rt = relocInfo::runtime_call_type); 781 inline void call(Label &L, relocInfo::relocType rt = relocInfo::runtime_call_type); 782 783 inline void call(address d, RelocationHolder const &rspec); 784 785 public: 786 787 // pp 150 788 789 // These instructions compare the contents of s2 with the contents of 790 // memory at address in s1. If the values are equal, the contents of memory 791 // at address s1 is swapped with the data in d. If the values are not equal, 792 // the the contents of memory at s1 is loaded into d, without the swap. 793 794 inline void casa(Register s1, Register s2, Register d, int ia = -1); 795 inline void casxa(Register s1, Register s2, Register d, int ia = -1); 796 797 // pp 152 798 799 inline void udiv(Register s1, Register s2, Register d); 800 inline void udiv(Register s1, int simm13a, Register d); 801 inline void sdiv(Register s1, Register s2, Register d); 802 inline void sdiv(Register s1, int simm13a, Register d); 803 inline void udivcc(Register s1, Register s2, Register d); 804 inline void udivcc(Register s1, int simm13a, Register d); 805 inline void sdivcc(Register s1, Register s2, Register d); 806 inline void sdivcc(Register s1, int simm13a, Register d); 807 808 // pp 155 809 810 inline void done(); 811 inline void retry(); 812 813 // pp 156 814 815 inline void fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); 816 inline void fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); 817 818 // pp 157 819 820 inline void fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2); 821 inline void fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2); 822 823 // pp 159 824 825 inline void ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 826 inline void ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 827 828 // pp 160 829 830 inline void ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d); 831 832 // pp 161 833 834 inline void fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 835 inline void fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 836 837 // pp 162 838 839 inline void fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 840 841 inline void fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 842 843 inline void fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 844 845 // pp 163 846 847 inline void fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); 848 inline void fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d); 849 inline void fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); 850 851 // FXORs/FXORd instructions 852 853 inline void fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); 854 855 // pp 164 856 857 inline void fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 858 859 // pp 165 860 861 inline void flush(Register s1, Register s2); 862 inline void flush(Register s1, int simm13a); 863 864 // pp 167 865 866 void flushw(); 867 868 // pp 168 869 870 void illtrap(int const22a); 871 872 // pp 169 873 874 void impdep1(int id1, int const19a); 875 void impdep2(int id1, int const19a); 876 877 // pp 170 878 879 void jmpl(Register s1, Register s2, Register d); 880 void jmpl(Register s1, int simm13a, Register d, 881 RelocationHolder const &rspec = RelocationHolder()); 882 883 // 171 884 885 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); 886 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, 887 RelocationHolder const &rspec = RelocationHolder()); 888 889 890 inline void ldfsr(Register s1, Register s2); 891 inline void ldfsr(Register s1, int simm13a); 892 inline void ldxfsr(Register s1, Register s2); 893 inline void ldxfsr(Register s1, int simm13a); 894 895 // 173 896 897 inline void ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d); 898 inline void ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d); 899 900 // pp 175 901 902 inline void ldsb(Register s1, Register s2, Register d); 903 inline void ldsb(Register s1, int simm13a, Register d); 904 inline void ldsh(Register s1, Register s2, Register d); 905 inline void ldsh(Register s1, int simm13a, Register d); 906 inline void ldsw(Register s1, Register s2, Register d); 907 inline void ldsw(Register s1, int simm13a, Register d); 908 inline void ldub(Register s1, Register s2, Register d); 909 inline void ldub(Register s1, int simm13a, Register d); 910 inline void lduh(Register s1, Register s2, Register d); 911 inline void lduh(Register s1, int simm13a, Register d); 912 inline void lduw(Register s1, Register s2, Register d); 913 inline void lduw(Register s1, int simm13a, Register d); 914 inline void ldx(Register s1, Register s2, Register d); 915 inline void ldx(Register s1, int simm13a, Register d); 916 inline void ldd(Register s1, Register s2, Register d); 917 inline void ldd(Register s1, int simm13a, Register d); 918 919 // pp 177 920 921 inline void ldsba(Register s1, Register s2, int ia, Register d); 922 inline void ldsba(Register s1, int simm13a, Register d); 923 inline void ldsha(Register s1, Register s2, int ia, Register d); 924 inline void ldsha(Register s1, int simm13a, Register d); 925 inline void ldswa(Register s1, Register s2, int ia, Register d); 926 inline void ldswa(Register s1, int simm13a, Register d); 927 inline void lduba(Register s1, Register s2, int ia, Register d); 928 inline void lduba(Register s1, int simm13a, Register d); 929 inline void lduha(Register s1, Register s2, int ia, Register d); 930 inline void lduha(Register s1, int simm13a, Register d); 931 inline void lduwa(Register s1, Register s2, int ia, Register d); 932 inline void lduwa(Register s1, int simm13a, Register d); 933 inline void ldxa(Register s1, Register s2, int ia, Register d); 934 inline void ldxa(Register s1, int simm13a, Register d); 935 936 // pp 181 937 938 inline void and3(Register s1, Register s2, Register d); 939 inline void and3(Register s1, int simm13a, Register d); 940 inline void andcc(Register s1, Register s2, Register d); 941 inline void andcc(Register s1, int simm13a, Register d); 942 inline void andn(Register s1, Register s2, Register d); 943 inline void andn(Register s1, int simm13a, Register d); 944 inline void andncc(Register s1, Register s2, Register d); 945 inline void andncc(Register s1, int simm13a, Register d); 946 inline void or3(Register s1, Register s2, Register d); 947 inline void or3(Register s1, int simm13a, Register d); 948 inline void orcc(Register s1, Register s2, Register d); 949 inline void orcc(Register s1, int simm13a, Register d); 950 inline void orn(Register s1, Register s2, Register d); 951 inline void orn(Register s1, int simm13a, Register d); 952 inline void orncc(Register s1, Register s2, Register d); 953 inline void orncc(Register s1, int simm13a, Register d); 954 inline void xor3(Register s1, Register s2, Register d); 955 inline void xor3(Register s1, int simm13a, Register d); 956 inline void xorcc(Register s1, Register s2, Register d); 957 inline void xorcc(Register s1, int simm13a, Register d); 958 inline void xnor(Register s1, Register s2, Register d); 959 inline void xnor(Register s1, int simm13a, Register d); 960 inline void xnorcc(Register s1, Register s2, Register d); 961 inline void xnorcc(Register s1, int simm13a, Register d); 962 963 // pp 183 964 965 inline void membar(Membar_mask_bits const7a); 966 967 // pp 185 968 969 inline void fmov(FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d); 970 971 // pp 189 972 973 inline void fmov(FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d); 974 975 // pp 191 976 977 inline void movcc(Condition c, bool floatCC, CC cca, Register s2, Register d); 978 inline void movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d); 979 980 // pp 195 981 982 inline void movr(RCondition c, Register s1, Register s2, Register d); 983 inline void movr(RCondition c, Register s1, int simm10a, Register d); 984 985 // pp 196 986 987 inline void mulx(Register s1, Register s2, Register d); 988 inline void mulx(Register s1, int simm13a, Register d); 989 inline void sdivx(Register s1, Register s2, Register d); 990 inline void sdivx(Register s1, int simm13a, Register d); 991 inline void udivx(Register s1, Register s2, Register d); 992 inline void udivx(Register s1, int simm13a, Register d); 993 994 // pp 197 995 996 inline void umul(Register s1, Register s2, Register d); 997 inline void umul(Register s1, int simm13a, Register d); 998 inline void smul(Register s1, Register s2, Register d); 999 inline void smul(Register s1, int simm13a, Register d); 1000 inline void umulcc(Register s1, Register s2, Register d); 1001 inline void umulcc(Register s1, int simm13a, Register d); 1002 inline void smulcc(Register s1, Register s2, Register d); 1003 inline void smulcc(Register s1, int simm13a, Register d); 1004 1005 // pp 201 1006 1007 inline void nop(); 1008 1009 inline void sw_count(); 1010 1011 // pp 202 1012 1013 inline void popc(Register s, Register d); 1014 inline void popc(int simm13a, Register d); 1015 1016 // pp 203 1017 1018 inline void prefetch(Register s1, Register s2, PrefetchFcn f); 1019 inline void prefetch(Register s1, int simm13a, PrefetchFcn f); 1020 1021 inline void prefetcha(Register s1, Register s2, int ia, PrefetchFcn f); 1022 inline void prefetcha(Register s1, int simm13a, PrefetchFcn f); 1023 1024 // pp 208 1025 1026 // not implementing read privileged register 1027 1028 inline void rdy(Register d); 1029 inline void rdccr(Register d); 1030 inline void rdasi(Register d); 1031 inline void rdtick(Register d); 1032 inline void rdpc(Register d); 1033 inline void rdfprs(Register d); 1034 1035 // pp 213 1036 1037 inline void rett(Register s1, Register s2); 1038 inline void rett(Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); 1039 1040 // pp 214 1041 1042 inline void save(Register s1, Register s2, Register d); 1043 inline void save(Register s1, int simm13a, Register d); 1044 1045 inline void restore(Register s1 = G0, Register s2 = G0, Register d = G0); 1046 inline void restore(Register s1, int simm13a, Register d); 1047 1048 // pp 216 1049 1050 inline void saved(); 1051 inline void restored(); 1052 1053 // pp 217 1054 1055 inline void sethi(int imm22a, Register d, RelocationHolder const &rspec = RelocationHolder()); 1056 1057 // pp 218 1058 1059 inline void sll(Register s1, Register s2, Register d); 1060 inline void sll(Register s1, int imm5a, Register d); 1061 inline void srl(Register s1, Register s2, Register d); 1062 inline void srl(Register s1, int imm5a, Register d); 1063 inline void sra(Register s1, Register s2, Register d); 1064 inline void sra(Register s1, int imm5a, Register d); 1065 1066 inline void sllx(Register s1, Register s2, Register d); 1067 inline void sllx(Register s1, int imm6a, Register d); 1068 inline void srlx(Register s1, Register s2, Register d); 1069 inline void srlx(Register s1, int imm6a, Register d); 1070 inline void srax(Register s1, Register s2, Register d); 1071 inline void srax(Register s1, int imm6a, Register d); 1072 1073 // pp 220 1074 1075 inline void sir(int simm13a); 1076 1077 // pp 221 1078 1079 inline void stbar(); 1080 1081 // pp 222 1082 1083 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); 1084 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); 1085 1086 inline void stfsr(Register s1, Register s2); 1087 inline void stfsr(Register s1, int simm13a); 1088 inline void stxfsr(Register s1, Register s2); 1089 inline void stxfsr(Register s1, int simm13a); 1090 1091 // pp 224 1092 1093 inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia); 1094 inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); 1095 1096 // pp 226 1097 1098 inline void stb(Register d, Register s1, Register s2); 1099 inline void stb(Register d, Register s1, int simm13a); 1100 inline void sth(Register d, Register s1, Register s2); 1101 inline void sth(Register d, Register s1, int simm13a); 1102 inline void stw(Register d, Register s1, Register s2); 1103 inline void stw(Register d, Register s1, int simm13a); 1104 inline void stx(Register d, Register s1, Register s2); 1105 inline void stx(Register d, Register s1, int simm13a); 1106 inline void std(Register d, Register s1, Register s2); 1107 inline void std(Register d, Register s1, int simm13a); 1108 1109 // pp 177 1110 1111 inline void stba(Register d, Register s1, Register s2, int ia); 1112 inline void stba(Register d, Register s1, int simm13a); 1113 inline void stha(Register d, Register s1, Register s2, int ia); 1114 inline void stha(Register d, Register s1, int simm13a); 1115 inline void stwa(Register d, Register s1, Register s2, int ia); 1116 inline void stwa(Register d, Register s1, int simm13a); 1117 inline void stxa(Register d, Register s1, Register s2, int ia); 1118 inline void stxa(Register d, Register s1, int simm13a); 1119 inline void stda(Register d, Register s1, Register s2, int ia); 1120 inline void stda(Register d, Register s1, int simm13a); 1121 1122 // pp 230 1123 1124 inline void sub(Register s1, Register s2, Register d); 1125 inline void sub(Register s1, int simm13a, Register d); 1126 1127 inline void subcc(Register s1, Register s2, Register d); 1128 inline void subcc(Register s1, int simm13a, Register d); 1129 inline void subc(Register s1, Register s2, Register d); 1130 inline void subc(Register s1, int simm13a, Register d); 1131 inline void subccc(Register s1, Register s2, Register d); 1132 inline void subccc(Register s1, int simm13a, Register d); 1133 1134 // pp 231 1135 1136 inline void swap(Register s1, Register s2, Register d); 1137 inline void swap(Register s1, int simm13a, Register d); 1138 1139 // pp 232 1140 1141 inline void swapa(Register s1, Register s2, int ia, Register d); 1142 inline void swapa(Register s1, int simm13a, Register d); 1143 1144 // pp 234, note op in book is wrong, see pp 268 1145 1146 inline void taddcc(Register s1, Register s2, Register d); 1147 inline void taddcc(Register s1, int simm13a, Register d); 1148 1149 // pp 235 1150 1151 inline void tsubcc(Register s1, Register s2, Register d); 1152 inline void tsubcc(Register s1, int simm13a, Register d); 1153 1154 // pp 237 1155 1156 inline void trap(Condition c, CC cc, Register s1, Register s2); 1157 inline void trap(Condition c, CC cc, Register s1, int trapa); 1158 // simple uncond. trap 1159 inline void trap(int trapa); 1160 1161 // pp 239 omit write priv register for now 1162 1163 inline void wry(Register d); 1164 inline void wrccr(Register s); 1165 inline void wrccr(Register s, int simm13a); 1166 inline void wrasi(Register d); 1167 // wrasi(d, imm) stores (d xor imm) to asi 1168 inline void wrasi(Register d, int simm13a); 1169 inline void wrfprs(Register d); 1170 1171 // VIS1 instructions 1172 1173 inline void alignaddr(Register s1, Register s2, Register d); 1174 1175 inline void faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d); 1176 1177 inline void fzero(FloatRegisterImpl::Width w, FloatRegister d); 1178 1179 inline void fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d); 1180 1181 inline void fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d); 1182 1183 inline void fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d); 1184 1185 inline void stpartialf(Register s1, Register s2, FloatRegister d, int ia = -1); 1186 1187 // VIS2 instructions 1188 1189 inline void edge8n(Register s1, Register s2, Register d); 1190 1191 inline void bmask(Register s1, Register s2, Register d); 1192 inline void bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d); 1193 1194 // VIS3 instructions 1195 1196 inline void movstosw(FloatRegister s, Register d); 1197 inline void movstouw(FloatRegister s, Register d); 1198 inline void movdtox(FloatRegister s, Register d); 1199 1200 inline void movwtos(Register s, FloatRegister d); 1201 inline void movxtod(Register s, FloatRegister d); 1202 1203 inline void xmulx(Register s1, Register s2, Register d); 1204 inline void xmulxhi(Register s1, Register s2, Register d); 1205 1206 // Crypto SHA instructions 1207 1208 inline void sha1(); 1209 inline void sha256(); 1210 inline void sha512(); 1211 1212 // CRC32C instruction 1213 1214 inline void crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d); 1215 1216 // Creation 1217 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 1218 #ifdef CHECK_DELAY 1219 delay_state = no_delay; 1220 #endif 1221 } 1222 }; 1223 1224 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP --- EOF ---