1 // 2 // Copyright (c) 1998, 2017, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 // 64-bit build means 64-bit pointers means hi/lo pairs 315 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 316 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 317 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 318 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 319 // Lock encodings use G3 and G4 internally 320 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 321 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 322 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 323 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 324 // Special class for storeP instructions, which can store SP or RPC to TLS. 325 // It is also used for memory addressing, allowing direct TLS addressing. 326 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 327 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 328 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 329 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 330 // R_L7 is the lowest-priority callee-save (i.e., NS) register 331 // We use it to save R_G2 across calls out of Java. 332 reg_class l7_regP(R_L7H,R_L7); 333 334 // Other special pointer regs 335 reg_class g1_regP(R_G1H,R_G1); 336 reg_class g2_regP(R_G2H,R_G2); 337 reg_class g3_regP(R_G3H,R_G3); 338 reg_class g4_regP(R_G4H,R_G4); 339 reg_class g5_regP(R_G5H,R_G5); 340 reg_class i0_regP(R_I0H,R_I0); 341 reg_class o0_regP(R_O0H,R_O0); 342 reg_class o1_regP(R_O1H,R_O1); 343 reg_class o2_regP(R_O2H,R_O2); 344 reg_class o7_regP(R_O7H,R_O7); 345 346 347 // ---------------------------- 348 // Long Register Classes 349 // ---------------------------- 350 // Longs in 1 register. Aligned adjacent hi/lo pairs. 351 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 352 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 353 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 354 // 64-bit, longs in 1 register: use all 64-bit integer registers 355 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 356 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 357 ); 358 359 reg_class g1_regL(R_G1H,R_G1); 360 reg_class g3_regL(R_G3H,R_G3); 361 reg_class o2_regL(R_O2H,R_O2); 362 reg_class o7_regL(R_O7H,R_O7); 363 364 // ---------------------------- 365 // Special Class for Condition Code Flags Register 366 reg_class int_flags(CCR); 367 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 368 reg_class float_flag0(FCC0); 369 370 371 // ---------------------------- 372 // Float Point Register Classes 373 // ---------------------------- 374 // Skip F30/F31, they are reserved for mem-mem copies 375 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 376 377 // Paired floating point registers--they show up in the same order as the floats, 378 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 379 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 380 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 381 /* Use extra V9 double registers; this AD file does not support V8 */ 382 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 383 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 384 ); 385 386 // Paired floating point registers--they show up in the same order as the floats, 387 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 388 // This class is usable for mis-aligned loads as happen in I2C adapters. 389 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 390 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 391 %} 392 393 //----------DEFINITION BLOCK--------------------------------------------------- 394 // Define name --> value mappings to inform the ADLC of an integer valued name 395 // Current support includes integer values in the range [0, 0x7FFFFFFF] 396 // Format: 397 // int_def <name> ( <int_value>, <expression>); 398 // Generated Code in ad_<arch>.hpp 399 // #define <name> (<expression>) 400 // // value == <int_value> 401 // Generated code in ad_<arch>.cpp adlc_verification() 402 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 403 // 404 definitions %{ 405 // The default cost (of an ALU instruction). 406 int_def DEFAULT_COST ( 100, 100); 407 int_def HUGE_COST (1000000, 1000000); 408 409 // Memory refs are twice as expensive as run-of-the-mill. 410 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 411 412 // Branches are even more expensive. 413 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 414 int_def CALL_COST ( 300, DEFAULT_COST * 3); 415 %} 416 417 418 //----------SOURCE BLOCK------------------------------------------------------- 419 // This is a block of C++ code which provides values, functions, and 420 // definitions necessary in the rest of the architecture description 421 source_hpp %{ 422 // Header information of the source block. 423 // Method declarations/definitions which are used outside 424 // the ad-scope can conveniently be defined here. 425 // 426 // To keep related declarations/definitions/uses close together, 427 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 428 429 // Must be visible to the DFA in dfa_sparc.cpp 430 extern bool can_branch_register( Node *bol, Node *cmp ); 431 432 extern bool use_block_zeroing(Node* count); 433 434 // Macros to extract hi & lo halves from a long pair. 435 // G0 is not part of any long pair, so assert on that. 436 // Prevents accidentally using G1 instead of G0. 437 #define LONG_HI_REG(x) (x) 438 #define LONG_LO_REG(x) (x) 439 440 class CallStubImpl { 441 442 //-------------------------------------------------------------- 443 //---< Used for optimization in Compile::Shorten_branches >--- 444 //-------------------------------------------------------------- 445 446 public: 447 // Size of call trampoline stub. 448 static uint size_call_trampoline() { 449 return 0; // no call trampolines on this platform 450 } 451 452 // number of relocations needed by a call trampoline stub 453 static uint reloc_call_trampoline() { 454 return 0; // no call trampolines on this platform 455 } 456 }; 457 458 class HandlerImpl { 459 460 public: 461 462 static int emit_exception_handler(CodeBuffer &cbuf); 463 static int emit_deopt_handler(CodeBuffer& cbuf); 464 465 static uint size_exception_handler() { 466 return ( NativeJump::instruction_size ); // sethi;jmp;nop 467 } 468 469 static uint size_deopt_handler() { 470 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 471 } 472 }; 473 474 %} 475 476 source %{ 477 #define __ _masm. 478 479 // tertiary op of a LoadP or StoreP encoding 480 #define REGP_OP true 481 482 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 483 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 484 static Register reg_to_register_object(int register_encoding); 485 486 // Used by the DFA in dfa_sparc.cpp. 487 // Check for being able to use a V9 branch-on-register. Requires a 488 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 489 // extended. Doesn't work following an integer ADD, for example, because of 490 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 491 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 492 // replace them with zero, which could become sign-extension in a different OS 493 // release. There's no obvious reason why an interrupt will ever fill these 494 // bits with non-zero junk (the registers are reloaded with standard LD 495 // instructions which either zero-fill or sign-fill). 496 bool can_branch_register( Node *bol, Node *cmp ) { 497 if( !BranchOnRegister ) return false; 498 if( cmp->Opcode() == Op_CmpP ) 499 return true; // No problems with pointer compares 500 if( cmp->Opcode() == Op_CmpL ) 501 return true; // No problems with long compares 502 503 if( !SparcV9RegsHiBitsZero ) return false; 504 if( bol->as_Bool()->_test._test != BoolTest::ne && 505 bol->as_Bool()->_test._test != BoolTest::eq ) 506 return false; 507 508 // Check for comparing against a 'safe' value. Any operation which 509 // clears out the high word is safe. Thus, loads and certain shifts 510 // are safe, as are non-negative constants. Any operation which 511 // preserves zero bits in the high word is safe as long as each of its 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their 513 // inputs are safe. At present, the only important case to recognize 514 // seems to be loads. Constants should fold away, and shifts & 515 // logicals can use the 'cc' forms. 516 Node *x = cmp->in(1); 517 if( x->is_Load() ) return true; 518 if( x->is_Phi() ) { 519 for( uint i = 1; i < x->req(); i++ ) 520 if( !x->in(i)->is_Load() ) 521 return false; 522 return true; 523 } 524 return false; 525 } 526 527 bool use_block_zeroing(Node* count) { 528 // Use BIS for zeroing if count is not constant 529 // or it is >= BlockZeroingLowLimit. 530 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); 531 } 532 533 // **************************************************************************** 534 535 // REQUIRED FUNCTIONALITY 536 537 // !!!!! Special hack to get all type of calls to specify the byte offset 538 // from the start of the call to the point where the return address 539 // will point. 540 // The "return address" is the address of the call instruction, plus 8. 541 542 int MachCallStaticJavaNode::ret_addr_offset() { 543 int offset = NativeCall::instruction_size; // call; delay slot 544 if (_method_handle_invoke) 545 offset += 4; // restore SP 546 return offset; 547 } 548 549 int MachCallDynamicJavaNode::ret_addr_offset() { 550 int vtable_index = this->_vtable_index; 551 if (vtable_index < 0) { 552 // must be invalid_vtable_index, not nonvirtual_vtable_index 553 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 554 return (NativeMovConstReg::instruction_size + 555 NativeCall::instruction_size); // sethi; setlo; call; delay slot 556 } else { 557 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 558 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 559 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 560 int klass_load_size; 561 if (UseCompressedClassPointers) { 562 assert(Universe::heap() != NULL, "java heap should be initialized"); 563 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 564 } else { 565 klass_load_size = 1*BytesPerInstWord; 566 } 567 if (Assembler::is_simm13(v_off)) { 568 return klass_load_size + 569 (2*BytesPerInstWord + // ld_ptr, ld_ptr 570 NativeCall::instruction_size); // call; delay slot 571 } else { 572 return klass_load_size + 573 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 574 NativeCall::instruction_size); // call; delay slot 575 } 576 } 577 } 578 579 int MachCallRuntimeNode::ret_addr_offset() { 580 if (MacroAssembler::is_far_target(entry_point())) { 581 return NativeFarCall::instruction_size; 582 } else { 583 return NativeCall::instruction_size; 584 } 585 } 586 587 // Indicate if the safepoint node needs the polling page as an input. 588 // Since Sparc does not have absolute addressing, it does. 589 bool SafePointNode::needs_polling_address_input() { 590 return true; 591 } 592 593 // emit an interrupt that is caught by the debugger (for debugging compiler) 594 void emit_break(CodeBuffer &cbuf) { 595 MacroAssembler _masm(&cbuf); 596 __ breakpoint_trap(); 597 } 598 599 #ifndef PRODUCT 600 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 601 st->print("TA"); 602 } 603 #endif 604 605 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 606 emit_break(cbuf); 607 } 608 609 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 610 return MachNode::size(ra_); 611 } 612 613 // Traceable jump 614 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 615 MacroAssembler _masm(&cbuf); 616 Register rdest = reg_to_register_object(jump_target); 617 __ JMP(rdest, 0); 618 __ delayed()->nop(); 619 } 620 621 // Traceable jump and set exception pc 622 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 623 MacroAssembler _masm(&cbuf); 624 Register rdest = reg_to_register_object(jump_target); 625 __ JMP(rdest, 0); 626 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 627 } 628 629 void emit_nop(CodeBuffer &cbuf) { 630 MacroAssembler _masm(&cbuf); 631 __ nop(); 632 } 633 634 void emit_illtrap(CodeBuffer &cbuf) { 635 MacroAssembler _masm(&cbuf); 636 __ illtrap(0); 637 } 638 639 640 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 641 assert(n->rule() != loadUB_rule, ""); 642 643 intptr_t offset = 0; 644 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 645 const Node* addr = n->get_base_and_disp(offset, adr_type); 646 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 647 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 648 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 649 atype = atype->add_offset(offset); 650 assert(disp32 == offset, "wrong disp32"); 651 return atype->_offset; 652 } 653 654 655 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 656 assert(n->rule() != loadUB_rule, ""); 657 658 intptr_t offset = 0; 659 Node* addr = n->in(2); 660 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 661 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 662 Node* a = addr->in(2/*AddPNode::Address*/); 663 Node* o = addr->in(3/*AddPNode::Offset*/); 664 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 665 atype = a->bottom_type()->is_ptr()->add_offset(offset); 666 assert(atype->isa_oop_ptr(), "still an oop"); 667 } 668 offset = atype->is_ptr()->_offset; 669 if (offset != Type::OffsetBot) offset += disp32; 670 return offset; 671 } 672 673 static inline jlong replicate_immI(int con, int count, int width) { 674 // Load a constant replicated "count" times with width "width" 675 assert(count*width == 8 && width <= 4, "sanity"); 676 int bit_width = width * 8; 677 jlong val = con; 678 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 679 for (int i = 0; i < count - 1; i++) { 680 val |= (val << bit_width); 681 } 682 return val; 683 } 684 685 static inline jlong replicate_immF(float con) { 686 // Replicate float con 2 times and pack into vector. 687 int val = *((int*)&con); 688 jlong lval = val; 689 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 690 return lval; 691 } 692 693 // Standard Sparc opcode form2 field breakdown 694 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 695 f0 &= (1<<19)-1; // Mask displacement to 19 bits 696 int op = (f30 << 30) | 697 (f29 << 29) | 698 (f25 << 25) | 699 (f22 << 22) | 700 (f20 << 20) | 701 (f19 << 19) | 702 (f0 << 0); 703 cbuf.insts()->emit_int32(op); 704 } 705 706 // Standard Sparc opcode form2 field breakdown 707 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 708 f0 >>= 10; // Drop 10 bits 709 f0 &= (1<<22)-1; // Mask displacement to 22 bits 710 int op = (f30 << 30) | 711 (f25 << 25) | 712 (f22 << 22) | 713 (f0 << 0); 714 cbuf.insts()->emit_int32(op); 715 } 716 717 // Standard Sparc opcode form3 field breakdown 718 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 719 int op = (f30 << 30) | 720 (f25 << 25) | 721 (f19 << 19) | 722 (f14 << 14) | 723 (f5 << 5) | 724 (f0 << 0); 725 cbuf.insts()->emit_int32(op); 726 } 727 728 // Standard Sparc opcode form3 field breakdown 729 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 730 simm13 &= (1<<13)-1; // Mask to 13 bits 731 int op = (f30 << 30) | 732 (f25 << 25) | 733 (f19 << 19) | 734 (f14 << 14) | 735 (1 << 13) | // bit to indicate immediate-mode 736 (simm13<<0); 737 cbuf.insts()->emit_int32(op); 738 } 739 740 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 741 simm10 &= (1<<10)-1; // Mask to 10 bits 742 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 743 } 744 745 #ifdef ASSERT 746 // Helper function for VerifyOops in emit_form3_mem_reg 747 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 748 warning("VerifyOops encountered unexpected instruction:"); 749 n->dump(2); 750 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 751 } 752 #endif 753 754 755 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, 756 int src1_enc, int disp32, int src2_enc, int dst_enc) { 757 758 #ifdef ASSERT 759 // The following code implements the +VerifyOops feature. 760 // It verifies oop values which are loaded into or stored out of 761 // the current method activation. +VerifyOops complements techniques 762 // like ScavengeALot, because it eagerly inspects oops in transit, 763 // as they enter or leave the stack, as opposed to ScavengeALot, 764 // which inspects oops "at rest", in the stack or heap, at safepoints. 765 // For this reason, +VerifyOops can sometimes detect bugs very close 766 // to their point of creation. It can also serve as a cross-check 767 // on the validity of oop maps, when used toegether with ScavengeALot. 768 769 // It would be good to verify oops at other points, especially 770 // when an oop is used as a base pointer for a load or store. 771 // This is presently difficult, because it is hard to know when 772 // a base address is biased or not. (If we had such information, 773 // it would be easy and useful to make a two-argument version of 774 // verify_oop which unbiases the base, and performs verification.) 775 776 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 777 bool is_verified_oop_base = false; 778 bool is_verified_oop_load = false; 779 bool is_verified_oop_store = false; 780 int tmp_enc = -1; 781 if (VerifyOops && src1_enc != R_SP_enc) { 782 // classify the op, mainly for an assert check 783 int st_op = 0, ld_op = 0; 784 switch (primary) { 785 case Assembler::stb_op3: st_op = Op_StoreB; break; 786 case Assembler::sth_op3: st_op = Op_StoreC; break; 787 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 788 case Assembler::stw_op3: st_op = Op_StoreI; break; 789 case Assembler::std_op3: st_op = Op_StoreL; break; 790 case Assembler::stf_op3: st_op = Op_StoreF; break; 791 case Assembler::stdf_op3: st_op = Op_StoreD; break; 792 793 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 794 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; 795 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 796 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 797 case Assembler::ldx_op3: // may become LoadP or stay LoadI 798 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 799 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 800 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 801 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 802 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 803 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 804 805 default: ShouldNotReachHere(); 806 } 807 if (tertiary == REGP_OP) { 808 if (st_op == Op_StoreI) st_op = Op_StoreP; 809 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 810 else ShouldNotReachHere(); 811 if (st_op) { 812 // a store 813 // inputs are (0:control, 1:memory, 2:address, 3:value) 814 Node* n2 = n->in(3); 815 if (n2 != NULL) { 816 const Type* t = n2->bottom_type(); 817 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 818 } 819 } else { 820 // a load 821 const Type* t = n->bottom_type(); 822 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 823 } 824 } 825 826 if (ld_op) { 827 // a Load 828 // inputs are (0:control, 1:memory, 2:address) 829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 830 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 831 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 832 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 833 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 834 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 835 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 836 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 837 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 838 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 839 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 840 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && 841 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && 842 !(n->rule() == loadUB_rule)) { 843 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 844 } 845 } else if (st_op) { 846 // a Store 847 // inputs are (0:control, 1:memory, 2:address, 3:value) 848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 853 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && 854 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 855 verify_oops_warning(n, n->ideal_Opcode(), st_op); 856 } 857 } 858 859 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 860 Node* addr = n->in(2); 861 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 862 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 863 if (atype != NULL) { 864 intptr_t offset = get_offset_from_base(n, atype, disp32); 865 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 866 if (offset != offset_2) { 867 get_offset_from_base(n, atype, disp32); 868 get_offset_from_base_2(n, atype, disp32); 869 } 870 assert(offset == offset_2, "different offsets"); 871 if (offset == disp32) { 872 // we now know that src1 is a true oop pointer 873 is_verified_oop_base = true; 874 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 875 if( primary == Assembler::ldd_op3 ) { 876 is_verified_oop_base = false; // Cannot 'ldd' into O7 877 } else { 878 tmp_enc = dst_enc; 879 dst_enc = R_O7_enc; // Load into O7; preserve source oop 880 assert(src1_enc != dst_enc, ""); 881 } 882 } 883 } 884 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 885 || offset == oopDesc::mark_offset_in_bytes())) { 886 // loading the mark should not be allowed either, but 887 // we don't check this since it conflicts with InlineObjectHash 888 // usage of LoadINode to get the mark. We could keep the 889 // check if we create a new LoadMarkNode 890 // but do not verify the object before its header is initialized 891 ShouldNotReachHere(); 892 } 893 } 894 } 895 } 896 } 897 #endif 898 899 uint instr = (Assembler::ldst_op << 30) 900 | (dst_enc << 25) 901 | (primary << 19) 902 | (src1_enc << 14); 903 904 uint index = src2_enc; 905 int disp = disp32; 906 907 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { 908 disp += STACK_BIAS; 909 // Check that stack offset fits, load into O7 if not 910 if (!Assembler::is_simm13(disp)) { 911 MacroAssembler _masm(&cbuf); 912 __ set(disp, O7); 913 if (index != R_G0_enc) { 914 __ add(O7, reg_to_register_object(index), O7); 915 } 916 index = R_O7_enc; 917 disp = 0; 918 } 919 } 920 921 if( disp == 0 ) { 922 // use reg-reg form 923 // bit 13 is already zero 924 instr |= index; 925 } else { 926 // use reg-imm form 927 instr |= 0x00002000; // set bit 13 to one 928 instr |= disp & 0x1FFF; 929 } 930 931 cbuf.insts()->emit_int32(instr); 932 933 #ifdef ASSERT 934 if (VerifyOops) { 935 MacroAssembler _masm(&cbuf); 936 if (is_verified_oop_base) { 937 __ verify_oop(reg_to_register_object(src1_enc)); 938 } 939 if (is_verified_oop_store) { 940 __ verify_oop(reg_to_register_object(dst_enc)); 941 } 942 if (tmp_enc != -1) { 943 __ mov(O7, reg_to_register_object(tmp_enc)); 944 } 945 if (is_verified_oop_load) { 946 __ verify_oop(reg_to_register_object(dst_enc)); 947 } 948 } 949 #endif 950 } 951 952 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) { 953 // The method which records debug information at every safepoint 954 // expects the call to be the first instruction in the snippet as 955 // it creates a PcDesc structure which tracks the offset of a call 956 // from the start of the codeBlob. This offset is computed as 957 // code_end() - code_begin() of the code which has been emitted 958 // so far. 959 // In this particular case we have skirted around the problem by 960 // putting the "mov" instruction in the delay slot but the problem 961 // may bite us again at some other point and a cleaner/generic 962 // solution using relocations would be needed. 963 MacroAssembler _masm(&cbuf); 964 __ set_inst_mark(); 965 966 // We flush the current window just so that there is a valid stack copy 967 // the fact that the current window becomes active again instantly is 968 // not a problem there is nothing live in it. 969 970 #ifdef ASSERT 971 int startpos = __ offset(); 972 #endif /* ASSERT */ 973 974 __ call((address)entry_point, rspec); 975 976 if (preserve_g2) __ delayed()->mov(G2, L7); 977 else __ delayed()->nop(); 978 979 if (preserve_g2) __ mov(L7, G2); 980 981 #ifdef ASSERT 982 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 983 // Trash argument dump slots. 984 __ set(0xb0b8ac0db0b8ac0d, G1); 985 __ mov(G1, G5); 986 __ stx(G1, SP, STACK_BIAS + 0x80); 987 __ stx(G1, SP, STACK_BIAS + 0x88); 988 __ stx(G1, SP, STACK_BIAS + 0x90); 989 __ stx(G1, SP, STACK_BIAS + 0x98); 990 __ stx(G1, SP, STACK_BIAS + 0xA0); 991 __ stx(G1, SP, STACK_BIAS + 0xA8); 992 } 993 #endif /*ASSERT*/ 994 } 995 996 //============================================================================= 997 // REQUIRED FUNCTIONALITY for encoding 998 void emit_lo(CodeBuffer &cbuf, int val) { } 999 void emit_hi(CodeBuffer &cbuf, int val) { } 1000 1001 1002 //============================================================================= 1003 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); 1004 1005 int Compile::ConstantTable::calculate_table_base_offset() const { 1006 if (UseRDPCForConstantTableBase) { 1007 // The table base offset might be less but then it fits into 1008 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). 1009 return Assembler::min_simm13(); 1010 } else { 1011 int offset = -(size() / 2); 1012 if (!Assembler::is_simm13(offset)) { 1013 offset = Assembler::min_simm13(); 1014 } 1015 return offset; 1016 } 1017 } 1018 1019 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 1020 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1021 ShouldNotReachHere(); 1022 } 1023 1024 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1025 Compile* C = ra_->C; 1026 Compile::ConstantTable& constant_table = C->constant_table(); 1027 MacroAssembler _masm(&cbuf); 1028 1029 Register r = as_Register(ra_->get_encode(this)); 1030 CodeSection* consts_section = __ code()->consts(); 1031 int consts_size = consts_section->align_at_start(consts_section->size()); 1032 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size); 1033 1034 if (UseRDPCForConstantTableBase) { 1035 // For the following RDPC logic to work correctly the consts 1036 // section must be allocated right before the insts section. This 1037 // assert checks for that. The layout and the SECT_* constants 1038 // are defined in src/share/vm/asm/codeBuffer.hpp. 1039 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1040 int insts_offset = __ offset(); 1041 1042 // Layout: 1043 // 1044 // |----------- consts section ------------|----------- insts section -----------... 1045 // |------ constant table -----|- padding -|------------------x---- 1046 // \ current PC (RDPC instruction) 1047 // |<------------- consts_size ----------->|<- insts_offset ->| 1048 // \ table base 1049 // The table base offset is later added to the load displacement 1050 // so it has to be negative. 1051 int table_base_offset = -(consts_size + insts_offset); 1052 int disp; 1053 1054 // If the displacement from the current PC to the constant table 1055 // base fits into simm13 we set the constant table base to the 1056 // current PC. 1057 if (Assembler::is_simm13(table_base_offset)) { 1058 constant_table.set_table_base_offset(table_base_offset); 1059 disp = 0; 1060 } else { 1061 // Otherwise we set the constant table base offset to the 1062 // maximum negative displacement of load instructions to keep 1063 // the disp as small as possible: 1064 // 1065 // |<------------- consts_size ----------->|<- insts_offset ->| 1066 // |<--------- min_simm13 --------->|<-------- disp --------->| 1067 // \ table base 1068 table_base_offset = Assembler::min_simm13(); 1069 constant_table.set_table_base_offset(table_base_offset); 1070 disp = (consts_size + insts_offset) + table_base_offset; 1071 } 1072 1073 __ rdpc(r); 1074 1075 if (disp != 0) { 1076 assert(r != O7, "need temporary"); 1077 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1078 } 1079 } 1080 else { 1081 // Materialize the constant table base. 1082 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1083 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1084 AddressLiteral base(baseaddr, rspec); 1085 __ set(base, r); 1086 } 1087 } 1088 1089 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1090 if (UseRDPCForConstantTableBase) { 1091 // This is really the worst case but generally it's only 1 instruction. 1092 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1093 } else { 1094 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1095 } 1096 } 1097 1098 #ifndef PRODUCT 1099 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1100 char reg[128]; 1101 ra_->dump_register(this, reg); 1102 if (UseRDPCForConstantTableBase) { 1103 st->print("RDPC %s\t! constant table base", reg); 1104 } else { 1105 st->print("SET &constanttable,%s\t! constant table base", reg); 1106 } 1107 } 1108 #endif 1109 1110 1111 //============================================================================= 1112 1113 #ifndef PRODUCT 1114 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1115 Compile* C = ra_->C; 1116 1117 for (int i = 0; i < OptoPrologueNops; i++) { 1118 st->print_cr("NOP"); st->print("\t"); 1119 } 1120 1121 if( VerifyThread ) { 1122 st->print_cr("Verify_Thread"); st->print("\t"); 1123 } 1124 1125 size_t framesize = C->frame_size_in_bytes(); 1126 int bangsize = C->bang_size_in_bytes(); 1127 1128 // Calls to C2R adapters often do not accept exceptional returns. 1129 // We require that their callers must bang for them. But be careful, because 1130 // some VM calls (such as call site linkage) can use several kilobytes of 1131 // stack. But the stack safety zone should account for that. 1132 // See bugs 4446381, 4468289, 4497237. 1133 if (C->need_stack_bang(bangsize)) { 1134 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); 1135 } 1136 1137 if (Assembler::is_simm13(-framesize)) { 1138 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize); 1139 } else { 1140 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1141 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1142 st->print ("SAVE R_SP,R_G3,R_SP"); 1143 } 1144 1145 } 1146 #endif 1147 1148 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1149 Compile* C = ra_->C; 1150 MacroAssembler _masm(&cbuf); 1151 1152 for (int i = 0; i < OptoPrologueNops; i++) { 1153 __ nop(); 1154 } 1155 1156 __ verify_thread(); 1157 1158 size_t framesize = C->frame_size_in_bytes(); 1159 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1160 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1161 int bangsize = C->bang_size_in_bytes(); 1162 1163 // Calls to C2R adapters often do not accept exceptional returns. 1164 // We require that their callers must bang for them. But be careful, because 1165 // some VM calls (such as call site linkage) can use several kilobytes of 1166 // stack. But the stack safety zone should account for that. 1167 // See bugs 4446381, 4468289, 4497237. 1168 if (C->need_stack_bang(bangsize)) { 1169 __ generate_stack_overflow_check(bangsize); 1170 } 1171 1172 if (Assembler::is_simm13(-framesize)) { 1173 __ save(SP, -framesize, SP); 1174 } else { 1175 __ sethi(-framesize & ~0x3ff, G3); 1176 __ add(G3, -framesize & 0x3ff, G3); 1177 __ save(SP, G3, SP); 1178 } 1179 C->set_frame_complete( __ offset() ); 1180 1181 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { 1182 // NOTE: We set the table base offset here because users might be 1183 // emitted before MachConstantBaseNode. 1184 Compile::ConstantTable& constant_table = C->constant_table(); 1185 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 1186 } 1187 } 1188 1189 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1190 return MachNode::size(ra_); 1191 } 1192 1193 int MachPrologNode::reloc() const { 1194 return 10; // a large enough number 1195 } 1196 1197 //============================================================================= 1198 #ifndef PRODUCT 1199 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1200 Compile* C = ra_->C; 1201 1202 if(do_polling() && ra_->C->is_method_compilation()) { 1203 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1204 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1205 } 1206 1207 if(do_polling()) { 1208 if (UseCBCond && !ra_->C->is_method_compilation()) { 1209 st->print("NOP\n\t"); 1210 } 1211 st->print("RET\n\t"); 1212 } 1213 1214 st->print("RESTORE"); 1215 } 1216 #endif 1217 1218 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1219 MacroAssembler _masm(&cbuf); 1220 Compile* C = ra_->C; 1221 1222 __ verify_thread(); 1223 1224 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 1225 __ reserved_stack_check(); 1226 } 1227 1228 // If this does safepoint polling, then do it here 1229 if(do_polling() && ra_->C->is_method_compilation()) { 1230 AddressLiteral polling_page(os::get_polling_page()); 1231 __ sethi(polling_page, L0); 1232 __ relocate(relocInfo::poll_return_type); 1233 __ ld_ptr(L0, 0, G0); 1234 } 1235 1236 // If this is a return, then stuff the restore in the delay slot 1237 if(do_polling()) { 1238 if (UseCBCond && !ra_->C->is_method_compilation()) { 1239 // Insert extra padding for the case when the epilogue is preceded by 1240 // a cbcond jump, which can't be followed by a CTI instruction 1241 __ nop(); 1242 } 1243 __ ret(); 1244 __ delayed()->restore(); 1245 } else { 1246 __ restore(); 1247 } 1248 } 1249 1250 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1251 return MachNode::size(ra_); 1252 } 1253 1254 int MachEpilogNode::reloc() const { 1255 return 16; // a large enough number 1256 } 1257 1258 const Pipeline * MachEpilogNode::pipeline() const { 1259 return MachNode::pipeline_class(); 1260 } 1261 1262 int MachEpilogNode::safepoint_offset() const { 1263 assert( do_polling(), "no return for this epilog node"); 1264 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1265 } 1266 1267 //============================================================================= 1268 1269 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1270 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1271 static enum RC rc_class( OptoReg::Name reg ) { 1272 if (!OptoReg::is_valid(reg)) return rc_bad; 1273 if (OptoReg::is_stack(reg)) return rc_stack; 1274 VMReg r = OptoReg::as_VMReg(reg); 1275 if (r->is_Register()) return rc_int; 1276 assert(r->is_FloatRegister(), "must be"); 1277 return rc_float; 1278 } 1279 1280 #ifndef PRODUCT 1281 ATTRIBUTE_PRINTF(2, 3) 1282 static void print_helper(outputStream* st, const char* format, ...) { 1283 if (st->position() > 0) { 1284 st->cr(); 1285 st->sp(); 1286 } 1287 va_list ap; 1288 va_start(ap, format); 1289 st->vprint(format, ap); 1290 va_end(ap); 1291 } 1292 #endif // !PRODUCT 1293 1294 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) { 1295 if (cbuf) { 1296 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1297 } 1298 #ifndef PRODUCT 1299 else { 1300 if (is_load) { 1301 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg)); 1302 } else { 1303 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset); 1304 } 1305 } 1306 #endif 1307 } 1308 1309 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) { 1310 if (cbuf) { 1311 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]); 1312 } 1313 #ifndef PRODUCT 1314 else { 1315 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst)); 1316 } 1317 #endif 1318 } 1319 1320 static void mach_spill_copy_implementation_helper(const MachNode* mach, 1321 CodeBuffer *cbuf, 1322 PhaseRegAlloc *ra_, 1323 outputStream* st) { 1324 // Get registers to move 1325 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1)); 1326 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1)); 1327 OptoReg::Name dst_second = ra_->get_reg_second(mach); 1328 OptoReg::Name dst_first = ra_->get_reg_first(mach); 1329 1330 enum RC src_second_rc = rc_class(src_second); 1331 enum RC src_first_rc = rc_class(src_first); 1332 enum RC dst_second_rc = rc_class(dst_second); 1333 enum RC dst_first_rc = rc_class(dst_first); 1334 1335 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register"); 1336 1337 if (src_first == dst_first && src_second == dst_second) { 1338 return; // Self copy, no move 1339 } 1340 1341 // -------------------------------------- 1342 // Check for mem-mem move. Load into unused float registers and fall into 1343 // the float-store case. 1344 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) { 1345 int offset = ra_->reg2offset(src_first); 1346 // Further check for aligned-adjacent pair, so we can use a double load 1347 if ((src_first&1) == 0 && src_first+1 == src_second) { 1348 src_second = OptoReg::Name(R_F31_num); 1349 src_second_rc = rc_float; 1350 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st); 1351 } else { 1352 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st); 1353 } 1354 src_first = OptoReg::Name(R_F30_num); 1355 src_first_rc = rc_float; 1356 } 1357 1358 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1359 int offset = ra_->reg2offset(src_second); 1360 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st); 1361 src_second = OptoReg::Name(R_F31_num); 1362 src_second_rc = rc_float; 1363 } 1364 1365 // -------------------------------------- 1366 // Check for float->int copy; requires a trip through memory 1367 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1368 int offset = frame::register_save_words*wordSize; 1369 if (cbuf) { 1370 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16); 1371 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1372 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1373 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16); 1374 } 1375 #ifndef PRODUCT 1376 else { 1377 print_helper(st, "SUB R_SP,16,R_SP"); 1378 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1379 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1380 print_helper(st, "ADD R_SP,16,R_SP"); 1381 } 1382 #endif 1383 } 1384 1385 // Check for float->int copy on T4 1386 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1387 // Further check for aligned-adjacent pair, so we can use a double move 1388 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1389 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st); 1390 return; 1391 } 1392 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st); 1393 } 1394 // Check for int->float copy on T4 1395 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1396 // Further check for aligned-adjacent pair, so we can use a double move 1397 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1398 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st); 1399 return; 1400 } 1401 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st); 1402 } 1403 1404 // -------------------------------------- 1405 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1406 // In such cases, I have to do the big-endian swap. For aligned targets, the 1407 // hardware does the flop for me. Doubles are always aligned, so no problem 1408 // there. Misaligned sources only come from native-long-returns (handled 1409 // special below). 1410 1411 // -------------------------------------- 1412 // Check for integer reg-reg copy 1413 if (src_first_rc == rc_int && dst_first_rc == rc_int) { 1414 // Else normal reg-reg copy 1415 assert(src_second != dst_first, "smashed second before evacuating it"); 1416 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st); 1417 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers"); 1418 // This moves an aligned adjacent pair. 1419 // See if we are done. 1420 if (src_first + 1 == src_second && dst_first + 1 == dst_second) { 1421 return; 1422 } 1423 } 1424 1425 // Check for integer store 1426 if (src_first_rc == rc_int && dst_first_rc == rc_stack) { 1427 int offset = ra_->reg2offset(dst_first); 1428 // Further check for aligned-adjacent pair, so we can use a double store 1429 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1430 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st); 1431 return; 1432 } 1433 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st); 1434 } 1435 1436 // Check for integer load 1437 if (dst_first_rc == rc_int && src_first_rc == rc_stack) { 1438 int offset = ra_->reg2offset(src_first); 1439 // Further check for aligned-adjacent pair, so we can use a double load 1440 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1441 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st); 1442 return; 1443 } 1444 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1445 } 1446 1447 // Check for float reg-reg copy 1448 if (src_first_rc == rc_float && dst_first_rc == rc_float) { 1449 // Further check for aligned-adjacent pair, so we can use a double move 1450 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1451 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st); 1452 return; 1453 } 1454 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st); 1455 } 1456 1457 // Check for float store 1458 if (src_first_rc == rc_float && dst_first_rc == rc_stack) { 1459 int offset = ra_->reg2offset(dst_first); 1460 // Further check for aligned-adjacent pair, so we can use a double store 1461 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1462 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st); 1463 return; 1464 } 1465 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1466 } 1467 1468 // Check for float load 1469 if (dst_first_rc == rc_float && src_first_rc == rc_stack) { 1470 int offset = ra_->reg2offset(src_first); 1471 // Further check for aligned-adjacent pair, so we can use a double load 1472 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1473 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st); 1474 return; 1475 } 1476 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st); 1477 } 1478 1479 // -------------------------------------------------------------------- 1480 // Check for hi bits still needing moving. Only happens for misaligned 1481 // arguments to native calls. 1482 if (src_second == dst_second) { 1483 return; // Self copy; no move 1484 } 1485 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad"); 1486 1487 Unimplemented(); 1488 } 1489 1490 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, 1491 PhaseRegAlloc *ra_, 1492 bool do_size, 1493 outputStream* st) const { 1494 assert(!do_size, "not supported"); 1495 mach_spill_copy_implementation_helper(this, cbuf, ra_, st); 1496 return 0; 1497 } 1498 1499 #ifndef PRODUCT 1500 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1501 implementation( NULL, ra_, false, st ); 1502 } 1503 #endif 1504 1505 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1506 implementation( &cbuf, ra_, false, NULL ); 1507 } 1508 1509 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1510 return MachNode::size(ra_); 1511 } 1512 1513 //============================================================================= 1514 #ifndef PRODUCT 1515 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const { 1516 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1517 } 1518 #endif 1519 1520 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1521 MacroAssembler _masm(&cbuf); 1522 for (int i = 0; i < _count; i += 1) { 1523 __ nop(); 1524 } 1525 } 1526 1527 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1528 return 4 * _count; 1529 } 1530 1531 1532 //============================================================================= 1533 #ifndef PRODUCT 1534 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1535 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1536 int reg = ra_->get_reg_first(this); 1537 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1538 } 1539 #endif 1540 1541 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1542 MacroAssembler _masm(&cbuf); 1543 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1544 int reg = ra_->get_encode(this); 1545 1546 if (Assembler::is_simm13(offset)) { 1547 __ add(SP, offset, reg_to_register_object(reg)); 1548 } else { 1549 __ set(offset, O7); 1550 __ add(SP, O7, reg_to_register_object(reg)); 1551 } 1552 } 1553 1554 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1555 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1556 assert(ra_ == ra_->C->regalloc(), "sanity"); 1557 return ra_->C->scratch_emit_size(this); 1558 } 1559 1560 //============================================================================= 1561 #ifndef PRODUCT 1562 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1563 st->print_cr("\nUEP:"); 1564 if (UseCompressedClassPointers) { 1565 assert(Universe::heap() != NULL, "java heap should be initialized"); 1566 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1567 if (Universe::narrow_klass_base() != 0) { 1568 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); 1569 if (Universe::narrow_klass_shift() != 0) { 1570 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1571 } 1572 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1573 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); 1574 } else { 1575 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1576 } 1577 } else { 1578 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1579 } 1580 st->print_cr("\tCMP R_G5,R_G3" ); 1581 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1582 } 1583 #endif 1584 1585 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1586 MacroAssembler _masm(&cbuf); 1587 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1588 Register temp_reg = G3; 1589 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1590 1591 // Load klass from receiver 1592 __ load_klass(O0, temp_reg); 1593 // Compare against expected klass 1594 __ cmp(temp_reg, G5_ic_reg); 1595 // Branch to miss code, checks xcc or icc depending 1596 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1597 } 1598 1599 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1600 return MachNode::size(ra_); 1601 } 1602 1603 1604 //============================================================================= 1605 1606 1607 // Emit exception handler code. 1608 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { 1609 Register temp_reg = G3; 1610 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1611 MacroAssembler _masm(&cbuf); 1612 1613 address base = __ start_a_stub(size_exception_handler()); 1614 if (base == NULL) { 1615 ciEnv::current()->record_failure("CodeCache is full"); 1616 return 0; // CodeBuffer::expand failed 1617 } 1618 1619 int offset = __ offset(); 1620 1621 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1622 __ delayed()->nop(); 1623 1624 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1625 1626 __ end_a_stub(); 1627 1628 return offset; 1629 } 1630 1631 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1632 // Can't use any of the current frame's registers as we may have deopted 1633 // at a poll and everything (including G3) can be live. 1634 Register temp_reg = L0; 1635 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1636 MacroAssembler _masm(&cbuf); 1637 1638 address base = __ start_a_stub(size_deopt_handler()); 1639 if (base == NULL) { 1640 ciEnv::current()->record_failure("CodeCache is full"); 1641 return 0; // CodeBuffer::expand failed 1642 } 1643 1644 int offset = __ offset(); 1645 __ save_frame(0); 1646 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1647 __ delayed()->restore(); 1648 1649 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1650 1651 __ end_a_stub(); 1652 return offset; 1653 1654 } 1655 1656 // Given a register encoding, produce a Integer Register object 1657 static Register reg_to_register_object(int register_encoding) { 1658 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1659 return as_Register(register_encoding); 1660 } 1661 1662 // Given a register encoding, produce a single-precision Float Register object 1663 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1664 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1665 return as_SingleFloatRegister(register_encoding); 1666 } 1667 1668 // Given a register encoding, produce a double-precision Float Register object 1669 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1670 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1671 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1672 return as_DoubleFloatRegister(register_encoding); 1673 } 1674 1675 const bool Matcher::match_rule_supported(int opcode) { 1676 if (!has_match_rule(opcode)) 1677 return false; 1678 1679 switch (opcode) { 1680 case Op_CountLeadingZerosI: 1681 case Op_CountLeadingZerosL: 1682 case Op_CountTrailingZerosI: 1683 case Op_CountTrailingZerosL: 1684 case Op_PopCountI: 1685 case Op_PopCountL: 1686 if (!UsePopCountInstruction) 1687 return false; 1688 case Op_CompareAndSwapL: 1689 case Op_CompareAndSwapP: 1690 if (!VM_Version::supports_cx8()) 1691 return false; 1692 break; 1693 } 1694 1695 return true; // Per default match rules are supported. 1696 } 1697 1698 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 1699 1700 // TODO 1701 // identify extra cases that we might want to provide match rules for 1702 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 1703 bool ret_value = match_rule_supported(opcode); 1704 // Add rules here. 1705 1706 return ret_value; // Per default match rules are supported. 1707 } 1708 1709 const bool Matcher::has_predicated_vectors(void) { 1710 return false; 1711 } 1712 1713 const int Matcher::float_pressure(int default_pressure_threshold) { 1714 return default_pressure_threshold; 1715 } 1716 1717 int Matcher::regnum_to_fpu_offset(int regnum) { 1718 return regnum - 32; // The FP registers are in the second chunk 1719 } 1720 1721 #ifdef ASSERT 1722 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1723 #endif 1724 1725 // Vector width in bytes 1726 const int Matcher::vector_width_in_bytes(BasicType bt) { 1727 assert(MaxVectorSize == 8, ""); 1728 return 8; 1729 } 1730 1731 // Vector ideal reg 1732 const uint Matcher::vector_ideal_reg(int size) { 1733 assert(MaxVectorSize == 8, ""); 1734 return Op_RegD; 1735 } 1736 1737 const uint Matcher::vector_shift_count_ideal_reg(int size) { 1738 fatal("vector shift is not supported"); 1739 return Node::NotAMachineReg; 1740 } 1741 1742 // Limits on vector size (number of elements) loaded into vector. 1743 const int Matcher::max_vector_size(const BasicType bt) { 1744 assert(is_java_primitive(bt), "only primitive type vectors"); 1745 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1746 } 1747 1748 const int Matcher::min_vector_size(const BasicType bt) { 1749 return max_vector_size(bt); // Same as max. 1750 } 1751 1752 // SPARC doesn't support misaligned vectors store/load. 1753 const bool Matcher::misaligned_vectors_ok() { 1754 return false; 1755 } 1756 1757 // Current (2013) SPARC platforms need to read original key 1758 // to construct decryption expanded key 1759 const bool Matcher::pass_original_key_for_aes() { 1760 return true; 1761 } 1762 1763 // NOTE: All currently supported SPARC HW provides fast conversion. 1764 const bool Matcher::convL2FSupported(void) { return true; } 1765 1766 // Is this branch offset short enough that a short branch can be used? 1767 // 1768 // NOTE: If the platform does not provide any short branch variants, then 1769 // this method should return false for offset 0. 1770 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1771 // The passed offset is relative to address of the branch. 1772 // Don't need to adjust the offset. 1773 return UseCBCond && Assembler::is_simm12(offset); 1774 } 1775 1776 const bool Matcher::isSimpleConstant64(jlong value) { 1777 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1778 // Depends on optimizations in MacroAssembler::setx. 1779 int hi = (int)(value >> 32); 1780 int lo = (int)(value & ~0); 1781 return (hi == 0) || (hi == -1) || (lo == 0); 1782 } 1783 1784 // No scaling for the parameter the ClearArray node. 1785 const bool Matcher::init_array_count_is_in_bytes = true; 1786 1787 // No additional cost for CMOVL. 1788 const int Matcher::long_cmove_cost() { return 0; } 1789 1790 // CMOVF/CMOVD are expensive on e.g., T4 and SPARC64. 1791 const int Matcher::float_cmove_cost() { 1792 return VM_Version::has_fast_cmove() ? 0 : ConditionalMoveLimit; 1793 } 1794 1795 // Does the CPU require late expand (see block.cpp for description of late expand)? 1796 const bool Matcher::require_postalloc_expand = false; 1797 1798 // Do we need to mask the count passed to shift instructions or does 1799 // the cpu only look at the lower 5/6 bits anyway? 1800 const bool Matcher::need_masked_shift_count = false; 1801 1802 bool Matcher::narrow_oop_use_complex_address() { 1803 assert(UseCompressedOops, "only for compressed oops code"); 1804 return false; 1805 } 1806 1807 bool Matcher::narrow_klass_use_complex_address() { 1808 assert(UseCompressedClassPointers, "only for compressed klass code"); 1809 return false; 1810 } 1811 1812 bool Matcher::const_oop_prefer_decode() { 1813 // TODO: Check if loading ConP from TOC in heap-based mode is better: 1814 // Prefer ConN+DecodeN over ConP in simple compressed oops mode. 1815 // return Universe::narrow_oop_base() == NULL; 1816 return true; 1817 } 1818 1819 bool Matcher::const_klass_prefer_decode() { 1820 // TODO: Check if loading ConP from TOC in heap-based mode is better: 1821 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 1822 // return Universe::narrow_klass_base() == NULL; 1823 return true; 1824 } 1825 1826 // Is it better to copy float constants, or load them directly from memory? 1827 // Intel can load a float constant from a direct address, requiring no 1828 // extra registers. Most RISCs will have to materialize an address into a 1829 // register first, so they would do better to copy the constant from stack. 1830 const bool Matcher::rematerialize_float_constants = false; 1831 1832 // If CPU can load and store mis-aligned doubles directly then no fixup is 1833 // needed. Else we split the double into 2 integer pieces and move it 1834 // piece-by-piece. Only happens when passing doubles into C code as the 1835 // Java calling convention forces doubles to be aligned. 1836 const bool Matcher::misaligned_doubles_ok = true; 1837 1838 // No-op on SPARC. 1839 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1840 } 1841 1842 // Advertise here if the CPU requires explicit rounding operations 1843 // to implement the UseStrictFP mode. 1844 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1845 1846 // Are floats converted to double when stored to stack during deoptimization? 1847 // Sparc does not handle callee-save floats. 1848 bool Matcher::float_in_double() { return false; } 1849 1850 // Do ints take an entire long register or just half? 1851 // Note that we if-def off of _LP64. 1852 // The relevant question is how the int is callee-saved. In _LP64 1853 // the whole long is written but de-opt'ing will have to extract 1854 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1855 const bool Matcher::int_in_long = true; 1856 1857 // Return whether or not this register is ever used as an argument. This 1858 // function is used on startup to build the trampoline stubs in generateOptoStub. 1859 // Registers not mentioned will be killed by the VM call in the trampoline, and 1860 // arguments in those registers not be available to the callee. 1861 bool Matcher::can_be_java_arg( int reg ) { 1862 // Standard sparc 6 args in registers 1863 if( reg == R_I0_num || 1864 reg == R_I1_num || 1865 reg == R_I2_num || 1866 reg == R_I3_num || 1867 reg == R_I4_num || 1868 reg == R_I5_num ) return true; 1869 // 64-bit builds can pass 64-bit pointers and longs in 1870 // the high I registers 1871 if( reg == R_I0H_num || 1872 reg == R_I1H_num || 1873 reg == R_I2H_num || 1874 reg == R_I3H_num || 1875 reg == R_I4H_num || 1876 reg == R_I5H_num ) return true; 1877 1878 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1879 return true; 1880 } 1881 1882 // A few float args in registers 1883 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1884 1885 return false; 1886 } 1887 1888 bool Matcher::is_spillable_arg( int reg ) { 1889 return can_be_java_arg(reg); 1890 } 1891 1892 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1893 // Use hardware SDIVX instruction when it is 1894 // faster than a code which use multiply. 1895 return VM_Version::has_fast_idiv(); 1896 } 1897 1898 // Register for DIVI projection of divmodI 1899 RegMask Matcher::divI_proj_mask() { 1900 ShouldNotReachHere(); 1901 return RegMask(); 1902 } 1903 1904 // Register for MODI projection of divmodI 1905 RegMask Matcher::modI_proj_mask() { 1906 ShouldNotReachHere(); 1907 return RegMask(); 1908 } 1909 1910 // Register for DIVL projection of divmodL 1911 RegMask Matcher::divL_proj_mask() { 1912 ShouldNotReachHere(); 1913 return RegMask(); 1914 } 1915 1916 // Register for MODL projection of divmodL 1917 RegMask Matcher::modL_proj_mask() { 1918 ShouldNotReachHere(); 1919 return RegMask(); 1920 } 1921 1922 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1923 return L7_REGP_mask(); 1924 } 1925 1926 1927 const bool Matcher::convi2l_type_required = true; 1928 1929 // Should the Matcher clone shifts on addressing modes, expecting them 1930 // to be subsumed into complex addressing expressions or compute them 1931 // into registers? 1932 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 1933 return clone_base_plus_offset_address(m, mstack, address_visited); 1934 } 1935 1936 void Compile::reshape_address(AddPNode* addp) { 1937 } 1938 1939 %} 1940 1941 1942 // The intptr_t operand types, defined by textual substitution. 1943 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1944 #define immX immL 1945 #define immX13 immL13 1946 #define immX13m7 immL13m7 1947 #define iRegX iRegL 1948 #define g1RegX g1RegL 1949 1950 //----------ENCODING BLOCK----------------------------------------------------- 1951 // This block specifies the encoding classes used by the compiler to output 1952 // byte streams. Encoding classes are parameterized macros used by 1953 // Machine Instruction Nodes in order to generate the bit encoding of the 1954 // instruction. Operands specify their base encoding interface with the 1955 // interface keyword. There are currently supported four interfaces, 1956 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1957 // operand to generate a function which returns its register number when 1958 // queried. CONST_INTER causes an operand to generate a function which 1959 // returns the value of the constant when queried. MEMORY_INTER causes an 1960 // operand to generate four functions which return the Base Register, the 1961 // Index Register, the Scale Value, and the Offset Value of the operand when 1962 // queried. COND_INTER causes an operand to generate six functions which 1963 // return the encoding code (ie - encoding bits for the instruction) 1964 // associated with each basic boolean condition for a conditional instruction. 1965 // 1966 // Instructions specify two basic values for encoding. Again, a function 1967 // is available to check if the constant displacement is an oop. They use the 1968 // ins_encode keyword to specify their encoding classes (which must be 1969 // a sequence of enc_class names, and their parameters, specified in 1970 // the encoding block), and they use the 1971 // opcode keyword to specify, in order, their primary, secondary, and 1972 // tertiary opcode. Only the opcode sections which a particular instruction 1973 // needs for encoding need to be specified. 1974 encode %{ 1975 enc_class enc_untested %{ 1976 #ifdef ASSERT 1977 MacroAssembler _masm(&cbuf); 1978 __ untested("encoding"); 1979 #endif 1980 %} 1981 1982 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1983 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, 1984 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1985 %} 1986 1987 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 1988 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 1989 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1990 %} 1991 1992 enc_class form3_mem_prefetch_read( memory mem ) %{ 1993 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 1994 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 1995 %} 1996 1997 enc_class form3_mem_prefetch_write( memory mem ) %{ 1998 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 1999 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2000 %} 2001 2002 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2003 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2004 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2005 guarantee($mem$$index == R_G0_enc, "double index?"); 2006 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2007 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2008 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2009 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2010 %} 2011 2012 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2013 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2014 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2015 guarantee($mem$$index == R_G0_enc, "double index?"); 2016 // Load long with 2 instructions 2017 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2018 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2019 %} 2020 2021 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2022 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2023 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2024 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2025 %} 2026 2027 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2028 // Encode a reg-reg copy. If it is useless, then empty encoding. 2029 if( $rs2$$reg != $rd$$reg ) 2030 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2031 %} 2032 2033 // Target lo half of long 2034 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2035 // Encode a reg-reg copy. If it is useless, then empty encoding. 2036 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2037 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2038 %} 2039 2040 // Source lo half of long 2041 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2042 // Encode a reg-reg copy. If it is useless, then empty encoding. 2043 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2044 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2045 %} 2046 2047 // Target hi half of long 2048 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2049 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2050 %} 2051 2052 // Source lo half of long, and leave it sign extended. 2053 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2054 // Sign extend low half 2055 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2056 %} 2057 2058 // Source hi half of long, and leave it sign extended. 2059 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2060 // Shift high half to low half 2061 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2062 %} 2063 2064 // Source hi half of long 2065 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2066 // Encode a reg-reg copy. If it is useless, then empty encoding. 2067 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2068 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2069 %} 2070 2071 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2072 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2073 %} 2074 2075 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2076 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2077 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2078 %} 2079 2080 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2081 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2082 // clear if nothing else is happening 2083 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2084 // blt,a,pn done 2085 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2086 // mov dst,-1 in delay slot 2087 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2088 %} 2089 2090 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2091 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2092 %} 2093 2094 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2095 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2096 %} 2097 2098 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2099 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2100 %} 2101 2102 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2103 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2104 %} 2105 2106 enc_class move_return_pc_to_o1() %{ 2107 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2108 %} 2109 2110 /* %%% merge with enc_to_bool */ 2111 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2112 MacroAssembler _masm(&cbuf); 2113 2114 Register src_reg = reg_to_register_object($src$$reg); 2115 Register dst_reg = reg_to_register_object($dst$$reg); 2116 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2117 %} 2118 2119 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2120 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2121 MacroAssembler _masm(&cbuf); 2122 2123 Register p_reg = reg_to_register_object($p$$reg); 2124 Register q_reg = reg_to_register_object($q$$reg); 2125 Register y_reg = reg_to_register_object($y$$reg); 2126 Register tmp_reg = reg_to_register_object($tmp$$reg); 2127 2128 __ subcc( p_reg, q_reg, p_reg ); 2129 __ add ( p_reg, y_reg, tmp_reg ); 2130 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2131 %} 2132 2133 enc_class form_d2i_helper(regD src, regF dst) %{ 2134 // fcmp %fcc0,$src,$src 2135 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2136 // branch %fcc0 not-nan, predict taken 2137 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2138 // fdtoi $src,$dst 2139 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2140 // fitos $dst,$dst (if nan) 2141 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2142 // clear $dst (if nan) 2143 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2144 // carry on here... 2145 %} 2146 2147 enc_class form_d2l_helper(regD src, regD dst) %{ 2148 // fcmp %fcc0,$src,$src check for NAN 2149 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2150 // branch %fcc0 not-nan, predict taken 2151 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2152 // fdtox $src,$dst convert in delay slot 2153 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2154 // fxtod $dst,$dst (if nan) 2155 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2156 // clear $dst (if nan) 2157 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2158 // carry on here... 2159 %} 2160 2161 enc_class form_f2i_helper(regF src, regF dst) %{ 2162 // fcmps %fcc0,$src,$src 2163 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2164 // branch %fcc0 not-nan, predict taken 2165 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2166 // fstoi $src,$dst 2167 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2168 // fitos $dst,$dst (if nan) 2169 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2170 // clear $dst (if nan) 2171 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2172 // carry on here... 2173 %} 2174 2175 enc_class form_f2l_helper(regF src, regD dst) %{ 2176 // fcmps %fcc0,$src,$src 2177 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2178 // branch %fcc0 not-nan, predict taken 2179 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2180 // fstox $src,$dst 2181 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2182 // fxtod $dst,$dst (if nan) 2183 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2184 // clear $dst (if nan) 2185 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2186 // carry on here... 2187 %} 2188 2189 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2190 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2191 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2192 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2193 2194 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2195 2196 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2197 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2198 2199 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2200 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2201 %} 2202 2203 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2204 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2205 %} 2206 2207 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2208 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2209 %} 2210 2211 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2212 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2213 %} 2214 2215 enc_class form3_convI2F(regF rs2, regF rd) %{ 2216 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2217 %} 2218 2219 // Encloding class for traceable jumps 2220 enc_class form_jmpl(g3RegP dest) %{ 2221 emit_jmpl(cbuf, $dest$$reg); 2222 %} 2223 2224 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2225 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2226 %} 2227 2228 enc_class form2_nop() %{ 2229 emit_nop(cbuf); 2230 %} 2231 2232 enc_class form2_illtrap() %{ 2233 emit_illtrap(cbuf); 2234 %} 2235 2236 2237 // Compare longs and convert into -1, 0, 1. 2238 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2239 // CMP $src1,$src2 2240 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2241 // blt,a,pn done 2242 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2243 // mov dst,-1 in delay slot 2244 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2245 // bgt,a,pn done 2246 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2247 // mov dst,1 in delay slot 2248 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2249 // CLR $dst 2250 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2251 %} 2252 2253 enc_class enc_PartialSubtypeCheck() %{ 2254 MacroAssembler _masm(&cbuf); 2255 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2256 __ delayed()->nop(); 2257 %} 2258 2259 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2260 MacroAssembler _masm(&cbuf); 2261 Label* L = $labl$$label; 2262 Assembler::Predict predict_taken = 2263 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2264 2265 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2266 __ delayed()->nop(); 2267 %} 2268 2269 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2270 MacroAssembler _masm(&cbuf); 2271 Label* L = $labl$$label; 2272 Assembler::Predict predict_taken = 2273 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2274 2275 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2276 __ delayed()->nop(); 2277 %} 2278 2279 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2280 int op = (Assembler::arith_op << 30) | 2281 ($dst$$reg << 25) | 2282 (Assembler::movcc_op3 << 19) | 2283 (1 << 18) | // cc2 bit for 'icc' 2284 ($cmp$$cmpcode << 14) | 2285 (0 << 13) | // select register move 2286 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2287 ($src$$reg << 0); 2288 cbuf.insts()->emit_int32(op); 2289 %} 2290 2291 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2292 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2293 int op = (Assembler::arith_op << 30) | 2294 ($dst$$reg << 25) | 2295 (Assembler::movcc_op3 << 19) | 2296 (1 << 18) | // cc2 bit for 'icc' 2297 ($cmp$$cmpcode << 14) | 2298 (1 << 13) | // select immediate move 2299 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2300 (simm11 << 0); 2301 cbuf.insts()->emit_int32(op); 2302 %} 2303 2304 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2305 int op = (Assembler::arith_op << 30) | 2306 ($dst$$reg << 25) | 2307 (Assembler::movcc_op3 << 19) | 2308 (0 << 18) | // cc2 bit for 'fccX' 2309 ($cmp$$cmpcode << 14) | 2310 (0 << 13) | // select register move 2311 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2312 ($src$$reg << 0); 2313 cbuf.insts()->emit_int32(op); 2314 %} 2315 2316 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2317 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2318 int op = (Assembler::arith_op << 30) | 2319 ($dst$$reg << 25) | 2320 (Assembler::movcc_op3 << 19) | 2321 (0 << 18) | // cc2 bit for 'fccX' 2322 ($cmp$$cmpcode << 14) | 2323 (1 << 13) | // select immediate move 2324 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2325 (simm11 << 0); 2326 cbuf.insts()->emit_int32(op); 2327 %} 2328 2329 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2330 int op = (Assembler::arith_op << 30) | 2331 ($dst$$reg << 25) | 2332 (Assembler::fpop2_op3 << 19) | 2333 (0 << 18) | 2334 ($cmp$$cmpcode << 14) | 2335 (1 << 13) | // select register move 2336 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2337 ($primary << 5) | // select single, double or quad 2338 ($src$$reg << 0); 2339 cbuf.insts()->emit_int32(op); 2340 %} 2341 2342 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2343 int op = (Assembler::arith_op << 30) | 2344 ($dst$$reg << 25) | 2345 (Assembler::fpop2_op3 << 19) | 2346 (0 << 18) | 2347 ($cmp$$cmpcode << 14) | 2348 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2349 ($primary << 5) | // select single, double or quad 2350 ($src$$reg << 0); 2351 cbuf.insts()->emit_int32(op); 2352 %} 2353 2354 // Used by the MIN/MAX encodings. Same as a CMOV, but 2355 // the condition comes from opcode-field instead of an argument. 2356 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2357 int op = (Assembler::arith_op << 30) | 2358 ($dst$$reg << 25) | 2359 (Assembler::movcc_op3 << 19) | 2360 (1 << 18) | // cc2 bit for 'icc' 2361 ($primary << 14) | 2362 (0 << 13) | // select register move 2363 (0 << 11) | // cc1, cc0 bits for 'icc' 2364 ($src$$reg << 0); 2365 cbuf.insts()->emit_int32(op); 2366 %} 2367 2368 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2369 int op = (Assembler::arith_op << 30) | 2370 ($dst$$reg << 25) | 2371 (Assembler::movcc_op3 << 19) | 2372 (6 << 16) | // cc2 bit for 'xcc' 2373 ($primary << 14) | 2374 (0 << 13) | // select register move 2375 (0 << 11) | // cc1, cc0 bits for 'icc' 2376 ($src$$reg << 0); 2377 cbuf.insts()->emit_int32(op); 2378 %} 2379 2380 enc_class Set13( immI13 src, iRegI rd ) %{ 2381 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2382 %} 2383 2384 enc_class SetHi22( immI src, iRegI rd ) %{ 2385 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2386 %} 2387 2388 enc_class Set32( immI src, iRegI rd ) %{ 2389 MacroAssembler _masm(&cbuf); 2390 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2391 %} 2392 2393 enc_class call_epilog %{ 2394 if( VerifyStackAtCalls ) { 2395 MacroAssembler _masm(&cbuf); 2396 int framesize = ra_->C->frame_size_in_bytes(); 2397 Register temp_reg = G3; 2398 __ add(SP, framesize, temp_reg); 2399 __ cmp(temp_reg, FP); 2400 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2401 } 2402 %} 2403 2404 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2405 // to G1 so the register allocator will not have to deal with the misaligned register 2406 // pair. 2407 enc_class adjust_long_from_native_call %{ 2408 %} 2409 2410 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2411 // CALL directly to the runtime 2412 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2413 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true); 2414 %} 2415 2416 enc_class preserve_SP %{ 2417 MacroAssembler _masm(&cbuf); 2418 __ mov(SP, L7_mh_SP_save); 2419 %} 2420 2421 enc_class restore_SP %{ 2422 MacroAssembler _masm(&cbuf); 2423 __ mov(L7_mh_SP_save, SP); 2424 %} 2425 2426 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2427 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2428 // who we intended to call. 2429 if (!_method) { 2430 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec()); 2431 } else { 2432 int method_index = resolved_method_index(cbuf); 2433 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 2434 : static_call_Relocation::spec(method_index); 2435 emit_call_reloc(cbuf, $meth$$method, rspec); 2436 2437 // Emit stub for static call. 2438 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2439 if (stub == NULL) { 2440 ciEnv::current()->record_failure("CodeCache is full"); 2441 return; 2442 } 2443 } 2444 %} 2445 2446 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2447 MacroAssembler _masm(&cbuf); 2448 __ set_inst_mark(); 2449 int vtable_index = this->_vtable_index; 2450 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2451 if (vtable_index < 0) { 2452 // must be invalid_vtable_index, not nonvirtual_vtable_index 2453 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 2454 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2455 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2456 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2457 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf)); 2458 } else { 2459 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2460 // Just go thru the vtable 2461 // get receiver klass (receiver already checked for non-null) 2462 // If we end up going thru a c2i adapter interpreter expects method in G5 2463 int off = __ offset(); 2464 __ load_klass(O0, G3_scratch); 2465 int klass_load_size; 2466 if (UseCompressedClassPointers) { 2467 assert(Universe::heap() != NULL, "java heap should be initialized"); 2468 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 2469 } else { 2470 klass_load_size = 1*BytesPerInstWord; 2471 } 2472 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 2473 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2474 if (Assembler::is_simm13(v_off)) { 2475 __ ld_ptr(G3, v_off, G5_method); 2476 } else { 2477 // Generate 2 instructions 2478 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2479 __ or3(G5_method, v_off & 0x3ff, G5_method); 2480 // ld_ptr, set_hi, set 2481 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2482 "Unexpected instruction size(s)"); 2483 __ ld_ptr(G3, G5_method, G5_method); 2484 } 2485 // NOTE: for vtable dispatches, the vtable entry will never be null. 2486 // However it may very well end up in handle_wrong_method if the 2487 // method is abstract for the particular class. 2488 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); 2489 // jump to target (either compiled code or c2iadapter) 2490 __ jmpl(G3_scratch, G0, O7); 2491 __ delayed()->nop(); 2492 } 2493 %} 2494 2495 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2496 MacroAssembler _masm(&cbuf); 2497 2498 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2499 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2500 // we might be calling a C2I adapter which needs it. 2501 2502 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2503 // Load nmethod 2504 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); 2505 2506 // CALL to compiled java, indirect the contents of G3 2507 __ set_inst_mark(); 2508 __ callr(temp_reg, G0); 2509 __ delayed()->nop(); 2510 %} 2511 2512 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2513 MacroAssembler _masm(&cbuf); 2514 Register Rdividend = reg_to_register_object($src1$$reg); 2515 Register Rdivisor = reg_to_register_object($src2$$reg); 2516 Register Rresult = reg_to_register_object($dst$$reg); 2517 2518 __ sra(Rdivisor, 0, Rdivisor); 2519 __ sra(Rdividend, 0, Rdividend); 2520 __ sdivx(Rdividend, Rdivisor, Rresult); 2521 %} 2522 2523 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2524 MacroAssembler _masm(&cbuf); 2525 2526 Register Rdividend = reg_to_register_object($src1$$reg); 2527 int divisor = $imm$$constant; 2528 Register Rresult = reg_to_register_object($dst$$reg); 2529 2530 __ sra(Rdividend, 0, Rdividend); 2531 __ sdivx(Rdividend, divisor, Rresult); 2532 %} 2533 2534 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2535 MacroAssembler _masm(&cbuf); 2536 Register Rsrc1 = reg_to_register_object($src1$$reg); 2537 Register Rsrc2 = reg_to_register_object($src2$$reg); 2538 Register Rdst = reg_to_register_object($dst$$reg); 2539 2540 __ sra( Rsrc1, 0, Rsrc1 ); 2541 __ sra( Rsrc2, 0, Rsrc2 ); 2542 __ mulx( Rsrc1, Rsrc2, Rdst ); 2543 __ srlx( Rdst, 32, Rdst ); 2544 %} 2545 2546 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2547 MacroAssembler _masm(&cbuf); 2548 Register Rdividend = reg_to_register_object($src1$$reg); 2549 Register Rdivisor = reg_to_register_object($src2$$reg); 2550 Register Rresult = reg_to_register_object($dst$$reg); 2551 Register Rscratch = reg_to_register_object($scratch$$reg); 2552 2553 assert(Rdividend != Rscratch, ""); 2554 assert(Rdivisor != Rscratch, ""); 2555 2556 __ sra(Rdividend, 0, Rdividend); 2557 __ sra(Rdivisor, 0, Rdivisor); 2558 __ sdivx(Rdividend, Rdivisor, Rscratch); 2559 __ mulx(Rscratch, Rdivisor, Rscratch); 2560 __ sub(Rdividend, Rscratch, Rresult); 2561 %} 2562 2563 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2564 MacroAssembler _masm(&cbuf); 2565 2566 Register Rdividend = reg_to_register_object($src1$$reg); 2567 int divisor = $imm$$constant; 2568 Register Rresult = reg_to_register_object($dst$$reg); 2569 Register Rscratch = reg_to_register_object($scratch$$reg); 2570 2571 assert(Rdividend != Rscratch, ""); 2572 2573 __ sra(Rdividend, 0, Rdividend); 2574 __ sdivx(Rdividend, divisor, Rscratch); 2575 __ mulx(Rscratch, divisor, Rscratch); 2576 __ sub(Rdividend, Rscratch, Rresult); 2577 %} 2578 2579 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2580 MacroAssembler _masm(&cbuf); 2581 2582 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2583 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2584 2585 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2586 %} 2587 2588 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2589 MacroAssembler _masm(&cbuf); 2590 2591 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2592 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2593 2594 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2595 %} 2596 2597 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2598 MacroAssembler _masm(&cbuf); 2599 2600 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2601 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2602 2603 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2604 %} 2605 2606 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2607 MacroAssembler _masm(&cbuf); 2608 2609 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2610 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2611 2612 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2613 %} 2614 2615 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2616 MacroAssembler _masm(&cbuf); 2617 2618 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2619 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2620 2621 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2622 %} 2623 2624 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2625 MacroAssembler _masm(&cbuf); 2626 2627 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2628 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2629 2630 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2631 %} 2632 2633 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2634 MacroAssembler _masm(&cbuf); 2635 2636 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2637 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2638 2639 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2640 %} 2641 2642 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2643 MacroAssembler _masm(&cbuf); 2644 2645 Register Roop = reg_to_register_object($oop$$reg); 2646 Register Rbox = reg_to_register_object($box$$reg); 2647 Register Rscratch = reg_to_register_object($scratch$$reg); 2648 Register Rmark = reg_to_register_object($scratch2$$reg); 2649 2650 assert(Roop != Rscratch, ""); 2651 assert(Roop != Rmark, ""); 2652 assert(Rbox != Rscratch, ""); 2653 assert(Rbox != Rmark, ""); 2654 2655 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2656 %} 2657 2658 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2659 MacroAssembler _masm(&cbuf); 2660 2661 Register Roop = reg_to_register_object($oop$$reg); 2662 Register Rbox = reg_to_register_object($box$$reg); 2663 Register Rscratch = reg_to_register_object($scratch$$reg); 2664 Register Rmark = reg_to_register_object($scratch2$$reg); 2665 2666 assert(Roop != Rscratch, ""); 2667 assert(Roop != Rmark, ""); 2668 assert(Rbox != Rscratch, ""); 2669 assert(Rbox != Rmark, ""); 2670 2671 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2672 %} 2673 2674 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2675 MacroAssembler _masm(&cbuf); 2676 Register Rmem = reg_to_register_object($mem$$reg); 2677 Register Rold = reg_to_register_object($old$$reg); 2678 Register Rnew = reg_to_register_object($new$$reg); 2679 2680 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2681 __ cmp( Rold, Rnew ); 2682 %} 2683 2684 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2685 Register Rmem = reg_to_register_object($mem$$reg); 2686 Register Rold = reg_to_register_object($old$$reg); 2687 Register Rnew = reg_to_register_object($new$$reg); 2688 2689 MacroAssembler _masm(&cbuf); 2690 __ mov(Rnew, O7); 2691 __ casx(Rmem, Rold, O7); 2692 __ cmp( Rold, O7 ); 2693 %} 2694 2695 // raw int cas, used for compareAndSwap 2696 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2697 Register Rmem = reg_to_register_object($mem$$reg); 2698 Register Rold = reg_to_register_object($old$$reg); 2699 Register Rnew = reg_to_register_object($new$$reg); 2700 2701 MacroAssembler _masm(&cbuf); 2702 __ mov(Rnew, O7); 2703 __ cas(Rmem, Rold, O7); 2704 __ cmp( Rold, O7 ); 2705 %} 2706 2707 // raw int cas without using tmp register for compareAndExchange 2708 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{ 2709 Register Rmem = reg_to_register_object($mem$$reg); 2710 Register Rold = reg_to_register_object($old$$reg); 2711 Register Rnew = reg_to_register_object($new$$reg); 2712 2713 MacroAssembler _masm(&cbuf); 2714 __ cas(Rmem, Rold, Rnew); 2715 %} 2716 2717 // 64-bit cas without using tmp register for compareAndExchange 2718 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{ 2719 Register Rmem = reg_to_register_object($mem$$reg); 2720 Register Rold = reg_to_register_object($old$$reg); 2721 Register Rnew = reg_to_register_object($new$$reg); 2722 2723 MacroAssembler _masm(&cbuf); 2724 __ casx(Rmem, Rold, Rnew); 2725 %} 2726 2727 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2728 Register Rres = reg_to_register_object($res$$reg); 2729 2730 MacroAssembler _masm(&cbuf); 2731 __ mov(1, Rres); 2732 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2733 %} 2734 2735 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2736 Register Rres = reg_to_register_object($res$$reg); 2737 2738 MacroAssembler _masm(&cbuf); 2739 __ mov(1, Rres); 2740 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2741 %} 2742 2743 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2744 MacroAssembler _masm(&cbuf); 2745 Register Rdst = reg_to_register_object($dst$$reg); 2746 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2747 : reg_to_DoubleFloatRegister_object($src1$$reg); 2748 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2749 : reg_to_DoubleFloatRegister_object($src2$$reg); 2750 2751 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2752 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2753 %} 2754 2755 enc_class enc_rethrow() %{ 2756 cbuf.set_insts_mark(); 2757 Register temp_reg = G3; 2758 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 2759 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 2760 MacroAssembler _masm(&cbuf); 2761 #ifdef ASSERT 2762 __ save_frame(0); 2763 AddressLiteral last_rethrow_addrlit(&last_rethrow); 2764 __ sethi(last_rethrow_addrlit, L1); 2765 Address addr(L1, last_rethrow_addrlit.low10()); 2766 __ rdpc(L2); 2767 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 2768 __ st_ptr(L2, addr); 2769 __ restore(); 2770 #endif 2771 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 2772 __ delayed()->nop(); 2773 %} 2774 2775 enc_class emit_mem_nop() %{ 2776 // Generates the instruction LDUXA [o6,g0],#0x82,g0 2777 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 2778 %} 2779 2780 enc_class emit_fadd_nop() %{ 2781 // Generates the instruction FMOVS f31,f31 2782 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 2783 %} 2784 2785 enc_class emit_br_nop() %{ 2786 // Generates the instruction BPN,PN . 2787 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 2788 %} 2789 2790 enc_class enc_membar_acquire %{ 2791 MacroAssembler _masm(&cbuf); 2792 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 2793 %} 2794 2795 enc_class enc_membar_release %{ 2796 MacroAssembler _masm(&cbuf); 2797 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 2798 %} 2799 2800 enc_class enc_membar_volatile %{ 2801 MacroAssembler _masm(&cbuf); 2802 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 2803 %} 2804 2805 %} 2806 2807 //----------FRAME-------------------------------------------------------------- 2808 // Definition of frame structure and management information. 2809 // 2810 // S T A C K L A Y O U T Allocators stack-slot number 2811 // | (to get allocators register number 2812 // G Owned by | | v add VMRegImpl::stack0) 2813 // r CALLER | | 2814 // o | +--------+ pad to even-align allocators stack-slot 2815 // w V | pad0 | numbers; owned by CALLER 2816 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 2817 // h ^ | in | 5 2818 // | | args | 4 Holes in incoming args owned by SELF 2819 // | | | | 3 2820 // | | +--------+ 2821 // V | | old out| Empty on Intel, window on Sparc 2822 // | old |preserve| Must be even aligned. 2823 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 2824 // | | in | 3 area for Intel ret address 2825 // Owned by |preserve| Empty on Sparc. 2826 // SELF +--------+ 2827 // | | pad2 | 2 pad to align old SP 2828 // | +--------+ 1 2829 // | | locks | 0 2830 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 2831 // | | pad1 | 11 pad to align new SP 2832 // | +--------+ 2833 // | | | 10 2834 // | | spills | 9 spills 2835 // V | | 8 (pad0 slot for callee) 2836 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 2837 // ^ | out | 7 2838 // | | args | 6 Holes in outgoing args owned by CALLEE 2839 // Owned by +--------+ 2840 // CALLEE | new out| 6 Empty on Intel, window on Sparc 2841 // | new |preserve| Must be even-aligned. 2842 // | SP-+--------+----> Matcher::_new_SP, even aligned 2843 // | | | 2844 // 2845 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 2846 // known from SELF's arguments and the Java calling convention. 2847 // Region 6-7 is determined per call site. 2848 // Note 2: If the calling convention leaves holes in the incoming argument 2849 // area, those holes are owned by SELF. Holes in the outgoing area 2850 // are owned by the CALLEE. Holes should not be nessecary in the 2851 // incoming area, as the Java calling convention is completely under 2852 // the control of the AD file. Doubles can be sorted and packed to 2853 // avoid holes. Holes in the outgoing arguments may be necessary for 2854 // varargs C calling conventions. 2855 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 2856 // even aligned with pad0 as needed. 2857 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 2858 // region 6-11 is even aligned; it may be padded out more so that 2859 // the region from SP to FP meets the minimum stack alignment. 2860 2861 frame %{ 2862 // What direction does stack grow in (assumed to be same for native & Java) 2863 stack_direction(TOWARDS_LOW); 2864 2865 // These two registers define part of the calling convention 2866 // between compiled code and the interpreter. 2867 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C 2868 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 2869 2870 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 2871 cisc_spilling_operand_name(indOffset); 2872 2873 // Number of stack slots consumed by a Monitor enter 2874 sync_stack_slots(2); 2875 2876 // Compiled code's Frame Pointer 2877 frame_pointer(R_SP); 2878 2879 // Stack alignment requirement 2880 stack_alignment(StackAlignmentInBytes); 2881 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 2882 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 2883 2884 // Number of stack slots between incoming argument block and the start of 2885 // a new frame. The PROLOG must add this many slots to the stack. The 2886 // EPILOG must remove this many slots. 2887 in_preserve_stack_slots(0); 2888 2889 // Number of outgoing stack slots killed above the out_preserve_stack_slots 2890 // for calls to C. Supports the var-args backing area for register parms. 2891 // ADLC doesn't support parsing expressions, so I folded the math by hand. 2892 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 2893 varargs_C_out_slots_killed(12); 2894 2895 // The after-PROLOG location of the return address. Location of 2896 // return address specifies a type (REG or STACK) and a number 2897 // representing the register number (i.e. - use a register name) or 2898 // stack slot. 2899 return_addr(REG R_I7); // Ret Addr is in register I7 2900 2901 // Body of function which returns an OptoRegs array locating 2902 // arguments either in registers or in stack slots for calling 2903 // java 2904 calling_convention %{ 2905 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 2906 2907 %} 2908 2909 // Body of function which returns an OptoRegs array locating 2910 // arguments either in registers or in stack slots for calling 2911 // C. 2912 c_calling_convention %{ 2913 // This is obviously always outgoing 2914 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 2915 %} 2916 2917 // Location of native (C/C++) and interpreter return values. This is specified to 2918 // be the same as Java. In the 32-bit VM, long values are actually returned from 2919 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 2920 // to and from the register pairs is done by the appropriate call and epilog 2921 // opcodes. This simplifies the register allocator. 2922 c_return_value %{ 2923 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 2924 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 2925 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 2926 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 2927 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 2928 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 2929 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 2930 %} 2931 2932 // Location of compiled Java return values. Same as C 2933 return_value %{ 2934 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 2935 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 2936 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 2937 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 2938 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 2939 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 2940 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 2941 %} 2942 2943 %} 2944 2945 2946 //----------ATTRIBUTES--------------------------------------------------------- 2947 //----------Operand Attributes------------------------------------------------- 2948 op_attrib op_cost(1); // Required cost attribute 2949 2950 //----------Instruction Attributes--------------------------------------------- 2951 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 2952 ins_attrib ins_size(32); // Required size attribute (in bits) 2953 2954 // avoid_back_to_back attribute is an expression that must return 2955 // one of the following values defined in MachNode: 2956 // AVOID_NONE - instruction can be placed anywhere 2957 // AVOID_BEFORE - instruction cannot be placed after an 2958 // instruction with MachNode::AVOID_AFTER 2959 // AVOID_AFTER - the next instruction cannot be the one 2960 // with MachNode::AVOID_BEFORE 2961 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 2962 // the same time 2963 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); 2964 2965 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 2966 // non-matching short branch variant of some 2967 // long branch? 2968 2969 //----------OPERANDS----------------------------------------------------------- 2970 // Operand definitions must precede instruction definitions for correct parsing 2971 // in the ADLC because operands constitute user defined types which are used in 2972 // instruction definitions. 2973 2974 //----------Simple Operands---------------------------------------------------- 2975 // Immediate Operands 2976 // Integer Immediate: 32-bit 2977 operand immI() %{ 2978 match(ConI); 2979 2980 op_cost(0); 2981 // formats are generated automatically for constants and base registers 2982 format %{ %} 2983 interface(CONST_INTER); 2984 %} 2985 2986 // Integer Immediate: 0-bit 2987 operand immI0() %{ 2988 predicate(n->get_int() == 0); 2989 match(ConI); 2990 op_cost(0); 2991 2992 format %{ %} 2993 interface(CONST_INTER); 2994 %} 2995 2996 // Integer Immediate: 5-bit 2997 operand immI5() %{ 2998 predicate(Assembler::is_simm5(n->get_int())); 2999 match(ConI); 3000 op_cost(0); 3001 format %{ %} 3002 interface(CONST_INTER); 3003 %} 3004 3005 // Integer Immediate: 8-bit 3006 operand immI8() %{ 3007 predicate(Assembler::is_simm8(n->get_int())); 3008 match(ConI); 3009 op_cost(0); 3010 format %{ %} 3011 interface(CONST_INTER); 3012 %} 3013 3014 // Integer Immediate: the value 10 3015 operand immI10() %{ 3016 predicate(n->get_int() == 10); 3017 match(ConI); 3018 op_cost(0); 3019 3020 format %{ %} 3021 interface(CONST_INTER); 3022 %} 3023 3024 // Integer Immediate: 11-bit 3025 operand immI11() %{ 3026 predicate(Assembler::is_simm11(n->get_int())); 3027 match(ConI); 3028 op_cost(0); 3029 format %{ %} 3030 interface(CONST_INTER); 3031 %} 3032 3033 // Integer Immediate: 13-bit 3034 operand immI13() %{ 3035 predicate(Assembler::is_simm13(n->get_int())); 3036 match(ConI); 3037 op_cost(0); 3038 3039 format %{ %} 3040 interface(CONST_INTER); 3041 %} 3042 3043 // Integer Immediate: 13-bit minus 7 3044 operand immI13m7() %{ 3045 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3046 match(ConI); 3047 op_cost(0); 3048 3049 format %{ %} 3050 interface(CONST_INTER); 3051 %} 3052 3053 // Integer Immediate: 16-bit 3054 operand immI16() %{ 3055 predicate(Assembler::is_simm16(n->get_int())); 3056 match(ConI); 3057 op_cost(0); 3058 format %{ %} 3059 interface(CONST_INTER); 3060 %} 3061 3062 // Integer Immediate: the values 1-31 3063 operand immI_1_31() %{ 3064 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3065 match(ConI); 3066 op_cost(0); 3067 3068 format %{ %} 3069 interface(CONST_INTER); 3070 %} 3071 3072 // Integer Immediate: the values 32-63 3073 operand immI_32_63() %{ 3074 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3075 match(ConI); 3076 op_cost(0); 3077 3078 format %{ %} 3079 interface(CONST_INTER); 3080 %} 3081 3082 // Immediates for special shifts (sign extend) 3083 3084 // Integer Immediate: the value 16 3085 operand immI_16() %{ 3086 predicate(n->get_int() == 16); 3087 match(ConI); 3088 op_cost(0); 3089 3090 format %{ %} 3091 interface(CONST_INTER); 3092 %} 3093 3094 // Integer Immediate: the value 24 3095 operand immI_24() %{ 3096 predicate(n->get_int() == 24); 3097 match(ConI); 3098 op_cost(0); 3099 3100 format %{ %} 3101 interface(CONST_INTER); 3102 %} 3103 // Integer Immediate: the value 255 3104 operand immI_255() %{ 3105 predicate( n->get_int() == 255 ); 3106 match(ConI); 3107 op_cost(0); 3108 3109 format %{ %} 3110 interface(CONST_INTER); 3111 %} 3112 3113 // Integer Immediate: the value 65535 3114 operand immI_65535() %{ 3115 predicate(n->get_int() == 65535); 3116 match(ConI); 3117 op_cost(0); 3118 3119 format %{ %} 3120 interface(CONST_INTER); 3121 %} 3122 3123 // Integer Immediate: the values 0-31 3124 operand immU5() %{ 3125 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3126 match(ConI); 3127 op_cost(0); 3128 3129 format %{ %} 3130 interface(CONST_INTER); 3131 %} 3132 3133 // Integer Immediate: 6-bit 3134 operand immU6() %{ 3135 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3136 match(ConI); 3137 op_cost(0); 3138 format %{ %} 3139 interface(CONST_INTER); 3140 %} 3141 3142 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) 3143 operand immU12() %{ 3144 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3145 match(ConI); 3146 op_cost(0); 3147 3148 format %{ %} 3149 interface(CONST_INTER); 3150 %} 3151 3152 // Integer Immediate non-negative 3153 operand immU31() 3154 %{ 3155 predicate(n->get_int() >= 0); 3156 match(ConI); 3157 3158 op_cost(0); 3159 format %{ %} 3160 interface(CONST_INTER); 3161 %} 3162 3163 // Long Immediate: the value FF 3164 operand immL_FF() %{ 3165 predicate( n->get_long() == 0xFFL ); 3166 match(ConL); 3167 op_cost(0); 3168 3169 format %{ %} 3170 interface(CONST_INTER); 3171 %} 3172 3173 // Long Immediate: the value FFFF 3174 operand immL_FFFF() %{ 3175 predicate( n->get_long() == 0xFFFFL ); 3176 match(ConL); 3177 op_cost(0); 3178 3179 format %{ %} 3180 interface(CONST_INTER); 3181 %} 3182 3183 // Pointer Immediate: 32 or 64-bit 3184 operand immP() %{ 3185 match(ConP); 3186 3187 op_cost(5); 3188 // formats are generated automatically for constants and base registers 3189 format %{ %} 3190 interface(CONST_INTER); 3191 %} 3192 3193 // Pointer Immediate: 64-bit 3194 operand immP_set() %{ 3195 predicate(!VM_Version::has_fast_ld()); 3196 match(ConP); 3197 3198 op_cost(5); 3199 // formats are generated automatically for constants and base registers 3200 format %{ %} 3201 interface(CONST_INTER); 3202 %} 3203 3204 // Pointer Immediate: 64-bit 3205 // From Niagara2 processors on a load should be better than materializing. 3206 operand immP_load() %{ 3207 predicate(VM_Version::has_fast_ld() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3208 match(ConP); 3209 3210 op_cost(5); 3211 // formats are generated automatically for constants and base registers 3212 format %{ %} 3213 interface(CONST_INTER); 3214 %} 3215 3216 // Pointer Immediate: 64-bit 3217 operand immP_no_oop_cheap() %{ 3218 predicate(VM_Version::has_fast_ld() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3219 match(ConP); 3220 3221 op_cost(5); 3222 // formats are generated automatically for constants and base registers 3223 format %{ %} 3224 interface(CONST_INTER); 3225 %} 3226 3227 operand immP13() %{ 3228 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3229 match(ConP); 3230 op_cost(0); 3231 3232 format %{ %} 3233 interface(CONST_INTER); 3234 %} 3235 3236 operand immP0() %{ 3237 predicate(n->get_ptr() == 0); 3238 match(ConP); 3239 op_cost(0); 3240 3241 format %{ %} 3242 interface(CONST_INTER); 3243 %} 3244 3245 operand immP_poll() %{ 3246 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3247 match(ConP); 3248 3249 // formats are generated automatically for constants and base registers 3250 format %{ %} 3251 interface(CONST_INTER); 3252 %} 3253 3254 // Pointer Immediate 3255 operand immN() 3256 %{ 3257 match(ConN); 3258 3259 op_cost(10); 3260 format %{ %} 3261 interface(CONST_INTER); 3262 %} 3263 3264 operand immNKlass() 3265 %{ 3266 match(ConNKlass); 3267 3268 op_cost(10); 3269 format %{ %} 3270 interface(CONST_INTER); 3271 %} 3272 3273 // NULL Pointer Immediate 3274 operand immN0() 3275 %{ 3276 predicate(n->get_narrowcon() == 0); 3277 match(ConN); 3278 3279 op_cost(0); 3280 format %{ %} 3281 interface(CONST_INTER); 3282 %} 3283 3284 operand immL() %{ 3285 match(ConL); 3286 op_cost(40); 3287 // formats are generated automatically for constants and base registers 3288 format %{ %} 3289 interface(CONST_INTER); 3290 %} 3291 3292 operand immL0() %{ 3293 predicate(n->get_long() == 0L); 3294 match(ConL); 3295 op_cost(0); 3296 // formats are generated automatically for constants and base registers 3297 format %{ %} 3298 interface(CONST_INTER); 3299 %} 3300 3301 // Integer Immediate: 5-bit 3302 operand immL5() %{ 3303 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); 3304 match(ConL); 3305 op_cost(0); 3306 format %{ %} 3307 interface(CONST_INTER); 3308 %} 3309 3310 // Long Immediate: 13-bit 3311 operand immL13() %{ 3312 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3313 match(ConL); 3314 op_cost(0); 3315 3316 format %{ %} 3317 interface(CONST_INTER); 3318 %} 3319 3320 // Long Immediate: 13-bit minus 7 3321 operand immL13m7() %{ 3322 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3323 match(ConL); 3324 op_cost(0); 3325 3326 format %{ %} 3327 interface(CONST_INTER); 3328 %} 3329 3330 // Long Immediate: low 32-bit mask 3331 operand immL_32bits() %{ 3332 predicate(n->get_long() == 0xFFFFFFFFL); 3333 match(ConL); 3334 op_cost(0); 3335 3336 format %{ %} 3337 interface(CONST_INTER); 3338 %} 3339 3340 // Long Immediate: cheap (materialize in <= 3 instructions) 3341 operand immL_cheap() %{ 3342 predicate(!VM_Version::has_fast_ld() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3343 match(ConL); 3344 op_cost(0); 3345 3346 format %{ %} 3347 interface(CONST_INTER); 3348 %} 3349 3350 // Long Immediate: expensive (materialize in > 3 instructions) 3351 operand immL_expensive() %{ 3352 predicate(VM_Version::has_fast_ld() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3353 match(ConL); 3354 op_cost(0); 3355 3356 format %{ %} 3357 interface(CONST_INTER); 3358 %} 3359 3360 // Double Immediate 3361 operand immD() %{ 3362 match(ConD); 3363 3364 op_cost(40); 3365 format %{ %} 3366 interface(CONST_INTER); 3367 %} 3368 3369 // Double Immediate: +0.0d 3370 operand immD0() %{ 3371 predicate(jlong_cast(n->getd()) == 0); 3372 match(ConD); 3373 3374 op_cost(0); 3375 format %{ %} 3376 interface(CONST_INTER); 3377 %} 3378 3379 // Float Immediate 3380 operand immF() %{ 3381 match(ConF); 3382 3383 op_cost(20); 3384 format %{ %} 3385 interface(CONST_INTER); 3386 %} 3387 3388 // Float Immediate: +0.0f 3389 operand immF0() %{ 3390 predicate(jint_cast(n->getf()) == 0); 3391 match(ConF); 3392 3393 op_cost(0); 3394 format %{ %} 3395 interface(CONST_INTER); 3396 %} 3397 3398 // Integer Register Operands 3399 // Integer Register 3400 operand iRegI() %{ 3401 constraint(ALLOC_IN_RC(int_reg)); 3402 match(RegI); 3403 3404 match(notemp_iRegI); 3405 match(g1RegI); 3406 match(o0RegI); 3407 match(iRegIsafe); 3408 3409 format %{ %} 3410 interface(REG_INTER); 3411 %} 3412 3413 operand notemp_iRegI() %{ 3414 constraint(ALLOC_IN_RC(notemp_int_reg)); 3415 match(RegI); 3416 3417 match(o0RegI); 3418 3419 format %{ %} 3420 interface(REG_INTER); 3421 %} 3422 3423 operand o0RegI() %{ 3424 constraint(ALLOC_IN_RC(o0_regI)); 3425 match(iRegI); 3426 3427 format %{ %} 3428 interface(REG_INTER); 3429 %} 3430 3431 // Pointer Register 3432 operand iRegP() %{ 3433 constraint(ALLOC_IN_RC(ptr_reg)); 3434 match(RegP); 3435 3436 match(lock_ptr_RegP); 3437 match(g1RegP); 3438 match(g2RegP); 3439 match(g3RegP); 3440 match(g4RegP); 3441 match(i0RegP); 3442 match(o0RegP); 3443 match(o1RegP); 3444 match(l7RegP); 3445 3446 format %{ %} 3447 interface(REG_INTER); 3448 %} 3449 3450 operand sp_ptr_RegP() %{ 3451 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3452 match(RegP); 3453 match(iRegP); 3454 3455 format %{ %} 3456 interface(REG_INTER); 3457 %} 3458 3459 operand lock_ptr_RegP() %{ 3460 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3461 match(RegP); 3462 match(i0RegP); 3463 match(o0RegP); 3464 match(o1RegP); 3465 match(l7RegP); 3466 3467 format %{ %} 3468 interface(REG_INTER); 3469 %} 3470 3471 operand g1RegP() %{ 3472 constraint(ALLOC_IN_RC(g1_regP)); 3473 match(iRegP); 3474 3475 format %{ %} 3476 interface(REG_INTER); 3477 %} 3478 3479 operand g2RegP() %{ 3480 constraint(ALLOC_IN_RC(g2_regP)); 3481 match(iRegP); 3482 3483 format %{ %} 3484 interface(REG_INTER); 3485 %} 3486 3487 operand g3RegP() %{ 3488 constraint(ALLOC_IN_RC(g3_regP)); 3489 match(iRegP); 3490 3491 format %{ %} 3492 interface(REG_INTER); 3493 %} 3494 3495 operand g1RegI() %{ 3496 constraint(ALLOC_IN_RC(g1_regI)); 3497 match(iRegI); 3498 3499 format %{ %} 3500 interface(REG_INTER); 3501 %} 3502 3503 operand g3RegI() %{ 3504 constraint(ALLOC_IN_RC(g3_regI)); 3505 match(iRegI); 3506 3507 format %{ %} 3508 interface(REG_INTER); 3509 %} 3510 3511 operand g4RegI() %{ 3512 constraint(ALLOC_IN_RC(g4_regI)); 3513 match(iRegI); 3514 3515 format %{ %} 3516 interface(REG_INTER); 3517 %} 3518 3519 operand g4RegP() %{ 3520 constraint(ALLOC_IN_RC(g4_regP)); 3521 match(iRegP); 3522 3523 format %{ %} 3524 interface(REG_INTER); 3525 %} 3526 3527 operand i0RegP() %{ 3528 constraint(ALLOC_IN_RC(i0_regP)); 3529 match(iRegP); 3530 3531 format %{ %} 3532 interface(REG_INTER); 3533 %} 3534 3535 operand o0RegP() %{ 3536 constraint(ALLOC_IN_RC(o0_regP)); 3537 match(iRegP); 3538 3539 format %{ %} 3540 interface(REG_INTER); 3541 %} 3542 3543 operand o1RegP() %{ 3544 constraint(ALLOC_IN_RC(o1_regP)); 3545 match(iRegP); 3546 3547 format %{ %} 3548 interface(REG_INTER); 3549 %} 3550 3551 operand o2RegP() %{ 3552 constraint(ALLOC_IN_RC(o2_regP)); 3553 match(iRegP); 3554 3555 format %{ %} 3556 interface(REG_INTER); 3557 %} 3558 3559 operand o7RegP() %{ 3560 constraint(ALLOC_IN_RC(o7_regP)); 3561 match(iRegP); 3562 3563 format %{ %} 3564 interface(REG_INTER); 3565 %} 3566 3567 operand l7RegP() %{ 3568 constraint(ALLOC_IN_RC(l7_regP)); 3569 match(iRegP); 3570 3571 format %{ %} 3572 interface(REG_INTER); 3573 %} 3574 3575 operand o7RegI() %{ 3576 constraint(ALLOC_IN_RC(o7_regI)); 3577 match(iRegI); 3578 3579 format %{ %} 3580 interface(REG_INTER); 3581 %} 3582 3583 operand iRegN() %{ 3584 constraint(ALLOC_IN_RC(int_reg)); 3585 match(RegN); 3586 3587 format %{ %} 3588 interface(REG_INTER); 3589 %} 3590 3591 // Long Register 3592 operand iRegL() %{ 3593 constraint(ALLOC_IN_RC(long_reg)); 3594 match(RegL); 3595 3596 format %{ %} 3597 interface(REG_INTER); 3598 %} 3599 3600 operand o2RegL() %{ 3601 constraint(ALLOC_IN_RC(o2_regL)); 3602 match(iRegL); 3603 3604 format %{ %} 3605 interface(REG_INTER); 3606 %} 3607 3608 operand o7RegL() %{ 3609 constraint(ALLOC_IN_RC(o7_regL)); 3610 match(iRegL); 3611 3612 format %{ %} 3613 interface(REG_INTER); 3614 %} 3615 3616 operand g1RegL() %{ 3617 constraint(ALLOC_IN_RC(g1_regL)); 3618 match(iRegL); 3619 3620 format %{ %} 3621 interface(REG_INTER); 3622 %} 3623 3624 operand g3RegL() %{ 3625 constraint(ALLOC_IN_RC(g3_regL)); 3626 match(iRegL); 3627 3628 format %{ %} 3629 interface(REG_INTER); 3630 %} 3631 3632 // Int Register safe 3633 // This is 64bit safe 3634 operand iRegIsafe() %{ 3635 constraint(ALLOC_IN_RC(long_reg)); 3636 3637 match(iRegI); 3638 3639 format %{ %} 3640 interface(REG_INTER); 3641 %} 3642 3643 // Condition Code Flag Register 3644 operand flagsReg() %{ 3645 constraint(ALLOC_IN_RC(int_flags)); 3646 match(RegFlags); 3647 3648 format %{ "ccr" %} // both ICC and XCC 3649 interface(REG_INTER); 3650 %} 3651 3652 // Condition Code Register, unsigned comparisons. 3653 operand flagsRegU() %{ 3654 constraint(ALLOC_IN_RC(int_flags)); 3655 match(RegFlags); 3656 3657 format %{ "icc_U" %} 3658 interface(REG_INTER); 3659 %} 3660 3661 // Condition Code Register, pointer comparisons. 3662 operand flagsRegP() %{ 3663 constraint(ALLOC_IN_RC(int_flags)); 3664 match(RegFlags); 3665 3666 format %{ "xcc_P" %} 3667 interface(REG_INTER); 3668 %} 3669 3670 // Condition Code Register, long comparisons. 3671 operand flagsRegL() %{ 3672 constraint(ALLOC_IN_RC(int_flags)); 3673 match(RegFlags); 3674 3675 format %{ "xcc_L" %} 3676 interface(REG_INTER); 3677 %} 3678 3679 // Condition Code Register, floating comparisons, unordered same as "less". 3680 operand flagsRegF() %{ 3681 constraint(ALLOC_IN_RC(float_flags)); 3682 match(RegFlags); 3683 match(flagsRegF0); 3684 3685 format %{ %} 3686 interface(REG_INTER); 3687 %} 3688 3689 operand flagsRegF0() %{ 3690 constraint(ALLOC_IN_RC(float_flag0)); 3691 match(RegFlags); 3692 3693 format %{ %} 3694 interface(REG_INTER); 3695 %} 3696 3697 3698 // Condition Code Flag Register used by long compare 3699 operand flagsReg_long_LTGE() %{ 3700 constraint(ALLOC_IN_RC(int_flags)); 3701 match(RegFlags); 3702 format %{ "icc_LTGE" %} 3703 interface(REG_INTER); 3704 %} 3705 operand flagsReg_long_EQNE() %{ 3706 constraint(ALLOC_IN_RC(int_flags)); 3707 match(RegFlags); 3708 format %{ "icc_EQNE" %} 3709 interface(REG_INTER); 3710 %} 3711 operand flagsReg_long_LEGT() %{ 3712 constraint(ALLOC_IN_RC(int_flags)); 3713 match(RegFlags); 3714 format %{ "icc_LEGT" %} 3715 interface(REG_INTER); 3716 %} 3717 3718 3719 operand regD() %{ 3720 constraint(ALLOC_IN_RC(dflt_reg)); 3721 match(RegD); 3722 3723 match(regD_low); 3724 3725 format %{ %} 3726 interface(REG_INTER); 3727 %} 3728 3729 operand regF() %{ 3730 constraint(ALLOC_IN_RC(sflt_reg)); 3731 match(RegF); 3732 3733 format %{ %} 3734 interface(REG_INTER); 3735 %} 3736 3737 operand regD_low() %{ 3738 constraint(ALLOC_IN_RC(dflt_low_reg)); 3739 match(regD); 3740 3741 format %{ %} 3742 interface(REG_INTER); 3743 %} 3744 3745 // Special Registers 3746 3747 // Method Register 3748 operand inline_cache_regP(iRegP reg) %{ 3749 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 3750 match(reg); 3751 format %{ %} 3752 interface(REG_INTER); 3753 %} 3754 3755 operand interpreter_method_oop_regP(iRegP reg) %{ 3756 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 3757 match(reg); 3758 format %{ %} 3759 interface(REG_INTER); 3760 %} 3761 3762 3763 //----------Complex Operands--------------------------------------------------- 3764 // Indirect Memory Reference 3765 operand indirect(sp_ptr_RegP reg) %{ 3766 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3767 match(reg); 3768 3769 op_cost(100); 3770 format %{ "[$reg]" %} 3771 interface(MEMORY_INTER) %{ 3772 base($reg); 3773 index(0x0); 3774 scale(0x0); 3775 disp(0x0); 3776 %} 3777 %} 3778 3779 // Indirect with simm13 Offset 3780 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 3781 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3782 match(AddP reg offset); 3783 3784 op_cost(100); 3785 format %{ "[$reg + $offset]" %} 3786 interface(MEMORY_INTER) %{ 3787 base($reg); 3788 index(0x0); 3789 scale(0x0); 3790 disp($offset); 3791 %} 3792 %} 3793 3794 // Indirect with simm13 Offset minus 7 3795 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 3796 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3797 match(AddP reg offset); 3798 3799 op_cost(100); 3800 format %{ "[$reg + $offset]" %} 3801 interface(MEMORY_INTER) %{ 3802 base($reg); 3803 index(0x0); 3804 scale(0x0); 3805 disp($offset); 3806 %} 3807 %} 3808 3809 // Note: Intel has a swapped version also, like this: 3810 //operand indOffsetX(iRegI reg, immP offset) %{ 3811 // constraint(ALLOC_IN_RC(int_reg)); 3812 // match(AddP offset reg); 3813 // 3814 // op_cost(100); 3815 // format %{ "[$reg + $offset]" %} 3816 // interface(MEMORY_INTER) %{ 3817 // base($reg); 3818 // index(0x0); 3819 // scale(0x0); 3820 // disp($offset); 3821 // %} 3822 //%} 3823 //// However, it doesn't make sense for SPARC, since 3824 // we have no particularly good way to embed oops in 3825 // single instructions. 3826 3827 // Indirect with Register Index 3828 operand indIndex(iRegP addr, iRegX index) %{ 3829 constraint(ALLOC_IN_RC(ptr_reg)); 3830 match(AddP addr index); 3831 3832 op_cost(100); 3833 format %{ "[$addr + $index]" %} 3834 interface(MEMORY_INTER) %{ 3835 base($addr); 3836 index($index); 3837 scale(0x0); 3838 disp(0x0); 3839 %} 3840 %} 3841 3842 //----------Special Memory Operands-------------------------------------------- 3843 // Stack Slot Operand - This operand is used for loading and storing temporary 3844 // values on the stack where a match requires a value to 3845 // flow through memory. 3846 operand stackSlotI(sRegI reg) %{ 3847 constraint(ALLOC_IN_RC(stack_slots)); 3848 op_cost(100); 3849 //match(RegI); 3850 format %{ "[$reg]" %} 3851 interface(MEMORY_INTER) %{ 3852 base(0xE); // R_SP 3853 index(0x0); 3854 scale(0x0); 3855 disp($reg); // Stack Offset 3856 %} 3857 %} 3858 3859 operand stackSlotP(sRegP reg) %{ 3860 constraint(ALLOC_IN_RC(stack_slots)); 3861 op_cost(100); 3862 //match(RegP); 3863 format %{ "[$reg]" %} 3864 interface(MEMORY_INTER) %{ 3865 base(0xE); // R_SP 3866 index(0x0); 3867 scale(0x0); 3868 disp($reg); // Stack Offset 3869 %} 3870 %} 3871 3872 operand stackSlotF(sRegF reg) %{ 3873 constraint(ALLOC_IN_RC(stack_slots)); 3874 op_cost(100); 3875 //match(RegF); 3876 format %{ "[$reg]" %} 3877 interface(MEMORY_INTER) %{ 3878 base(0xE); // R_SP 3879 index(0x0); 3880 scale(0x0); 3881 disp($reg); // Stack Offset 3882 %} 3883 %} 3884 operand stackSlotD(sRegD reg) %{ 3885 constraint(ALLOC_IN_RC(stack_slots)); 3886 op_cost(100); 3887 //match(RegD); 3888 format %{ "[$reg]" %} 3889 interface(MEMORY_INTER) %{ 3890 base(0xE); // R_SP 3891 index(0x0); 3892 scale(0x0); 3893 disp($reg); // Stack Offset 3894 %} 3895 %} 3896 operand stackSlotL(sRegL reg) %{ 3897 constraint(ALLOC_IN_RC(stack_slots)); 3898 op_cost(100); 3899 //match(RegL); 3900 format %{ "[$reg]" %} 3901 interface(MEMORY_INTER) %{ 3902 base(0xE); // R_SP 3903 index(0x0); 3904 scale(0x0); 3905 disp($reg); // Stack Offset 3906 %} 3907 %} 3908 3909 // Operands for expressing Control Flow 3910 // NOTE: Label is a predefined operand which should not be redefined in 3911 // the AD file. It is generically handled within the ADLC. 3912 3913 //----------Conditional Branch Operands---------------------------------------- 3914 // Comparison Op - This is the operation of the comparison, and is limited to 3915 // the following set of codes: 3916 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 3917 // 3918 // Other attributes of the comparison, such as unsignedness, are specified 3919 // by the comparison instruction that sets a condition code flags register. 3920 // That result is represented by a flags operand whose subtype is appropriate 3921 // to the unsignedness (etc.) of the comparison. 3922 // 3923 // Later, the instruction which matches both the Comparison Op (a Bool) and 3924 // the flags (produced by the Cmp) specifies the coding of the comparison op 3925 // by matching a specific subtype of Bool operand below, such as cmpOpU. 3926 3927 operand cmpOp() %{ 3928 match(Bool); 3929 3930 format %{ "" %} 3931 interface(COND_INTER) %{ 3932 equal(0x1); 3933 not_equal(0x9); 3934 less(0x3); 3935 greater_equal(0xB); 3936 less_equal(0x2); 3937 greater(0xA); 3938 overflow(0x7); 3939 no_overflow(0xF); 3940 %} 3941 %} 3942 3943 // Comparison Op, unsigned 3944 operand cmpOpU() %{ 3945 match(Bool); 3946 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 3947 n->as_Bool()->_test._test != BoolTest::no_overflow); 3948 3949 format %{ "u" %} 3950 interface(COND_INTER) %{ 3951 equal(0x1); 3952 not_equal(0x9); 3953 less(0x5); 3954 greater_equal(0xD); 3955 less_equal(0x4); 3956 greater(0xC); 3957 overflow(0x7); 3958 no_overflow(0xF); 3959 %} 3960 %} 3961 3962 // Comparison Op, pointer (same as unsigned) 3963 operand cmpOpP() %{ 3964 match(Bool); 3965 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 3966 n->as_Bool()->_test._test != BoolTest::no_overflow); 3967 3968 format %{ "p" %} 3969 interface(COND_INTER) %{ 3970 equal(0x1); 3971 not_equal(0x9); 3972 less(0x5); 3973 greater_equal(0xD); 3974 less_equal(0x4); 3975 greater(0xC); 3976 overflow(0x7); 3977 no_overflow(0xF); 3978 %} 3979 %} 3980 3981 // Comparison Op, branch-register encoding 3982 operand cmpOp_reg() %{ 3983 match(Bool); 3984 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 3985 n->as_Bool()->_test._test != BoolTest::no_overflow); 3986 3987 format %{ "" %} 3988 interface(COND_INTER) %{ 3989 equal (0x1); 3990 not_equal (0x5); 3991 less (0x3); 3992 greater_equal(0x7); 3993 less_equal (0x2); 3994 greater (0x6); 3995 overflow(0x7); // not supported 3996 no_overflow(0xF); // not supported 3997 %} 3998 %} 3999 4000 // Comparison Code, floating, unordered same as less 4001 operand cmpOpF() %{ 4002 match(Bool); 4003 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4004 n->as_Bool()->_test._test != BoolTest::no_overflow); 4005 4006 format %{ "fl" %} 4007 interface(COND_INTER) %{ 4008 equal(0x9); 4009 not_equal(0x1); 4010 less(0x3); 4011 greater_equal(0xB); 4012 less_equal(0xE); 4013 greater(0x6); 4014 4015 overflow(0x7); // not supported 4016 no_overflow(0xF); // not supported 4017 %} 4018 %} 4019 4020 // Used by long compare 4021 operand cmpOp_commute() %{ 4022 match(Bool); 4023 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4024 n->as_Bool()->_test._test != BoolTest::no_overflow); 4025 4026 format %{ "" %} 4027 interface(COND_INTER) %{ 4028 equal(0x1); 4029 not_equal(0x9); 4030 less(0xA); 4031 greater_equal(0x2); 4032 less_equal(0xB); 4033 greater(0x3); 4034 overflow(0x7); 4035 no_overflow(0xF); 4036 %} 4037 %} 4038 4039 //----------OPERAND CLASSES---------------------------------------------------- 4040 // Operand Classes are groups of operands that are used to simplify 4041 // instruction definitions by not requiring the AD writer to specify separate 4042 // instructions for every form of operand when the instruction accepts 4043 // multiple operand types with the same basic encoding and format. The classic 4044 // case of this is memory operands. 4045 opclass memory( indirect, indOffset13, indIndex ); 4046 opclass indIndexMemory( indIndex ); 4047 4048 //----------PIPELINE----------------------------------------------------------- 4049 pipeline %{ 4050 4051 //----------ATTRIBUTES--------------------------------------------------------- 4052 attributes %{ 4053 fixed_size_instructions; // Fixed size instructions 4054 branch_has_delay_slot; // Branch has delay slot following 4055 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4056 instruction_unit_size = 4; // An instruction is 4 bytes long 4057 instruction_fetch_unit_size = 16; // The processor fetches one line 4058 instruction_fetch_units = 1; // of 16 bytes 4059 4060 // List of nop instructions 4061 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4062 %} 4063 4064 //----------RESOURCES---------------------------------------------------------- 4065 // Resources are the functional units available to the machine 4066 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4067 4068 //----------PIPELINE DESCRIPTION----------------------------------------------- 4069 // Pipeline Description specifies the stages in the machine's pipeline 4070 4071 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4072 4073 //----------PIPELINE CLASSES--------------------------------------------------- 4074 // Pipeline Classes describe the stages in which input and output are 4075 // referenced by the hardware pipeline. 4076 4077 // Integer ALU reg-reg operation 4078 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4079 single_instruction; 4080 dst : E(write); 4081 src1 : R(read); 4082 src2 : R(read); 4083 IALU : R; 4084 %} 4085 4086 // Integer ALU reg-reg long operation 4087 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4088 instruction_count(2); 4089 dst : E(write); 4090 src1 : R(read); 4091 src2 : R(read); 4092 IALU : R; 4093 IALU : R; 4094 %} 4095 4096 // Integer ALU reg-reg long dependent operation 4097 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4098 instruction_count(1); multiple_bundles; 4099 dst : E(write); 4100 src1 : R(read); 4101 src2 : R(read); 4102 cr : E(write); 4103 IALU : R(2); 4104 %} 4105 4106 // Integer ALU reg-imm operaion 4107 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4108 single_instruction; 4109 dst : E(write); 4110 src1 : R(read); 4111 IALU : R; 4112 %} 4113 4114 // Integer ALU reg-reg operation with condition code 4115 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4116 single_instruction; 4117 dst : E(write); 4118 cr : E(write); 4119 src1 : R(read); 4120 src2 : R(read); 4121 IALU : R; 4122 %} 4123 4124 // Integer ALU reg-imm operation with condition code 4125 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4126 single_instruction; 4127 dst : E(write); 4128 cr : E(write); 4129 src1 : R(read); 4130 IALU : R; 4131 %} 4132 4133 // Integer ALU zero-reg operation 4134 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4135 single_instruction; 4136 dst : E(write); 4137 src2 : R(read); 4138 IALU : R; 4139 %} 4140 4141 // Integer ALU zero-reg operation with condition code only 4142 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4143 single_instruction; 4144 cr : E(write); 4145 src : R(read); 4146 IALU : R; 4147 %} 4148 4149 // Integer ALU reg-reg operation with condition code only 4150 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4151 single_instruction; 4152 cr : E(write); 4153 src1 : R(read); 4154 src2 : R(read); 4155 IALU : R; 4156 %} 4157 4158 // Integer ALU reg-imm operation with condition code only 4159 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4160 single_instruction; 4161 cr : E(write); 4162 src1 : R(read); 4163 IALU : R; 4164 %} 4165 4166 // Integer ALU reg-reg-zero operation with condition code only 4167 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4168 single_instruction; 4169 cr : E(write); 4170 src1 : R(read); 4171 src2 : R(read); 4172 IALU : R; 4173 %} 4174 4175 // Integer ALU reg-imm-zero operation with condition code only 4176 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4177 single_instruction; 4178 cr : E(write); 4179 src1 : R(read); 4180 IALU : R; 4181 %} 4182 4183 // Integer ALU reg-reg operation with condition code, src1 modified 4184 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4185 single_instruction; 4186 cr : E(write); 4187 src1 : E(write); 4188 src1 : R(read); 4189 src2 : R(read); 4190 IALU : R; 4191 %} 4192 4193 // Integer ALU reg-imm operation with condition code, src1 modified 4194 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4195 single_instruction; 4196 cr : E(write); 4197 src1 : E(write); 4198 src1 : R(read); 4199 IALU : R; 4200 %} 4201 4202 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4203 multiple_bundles; 4204 dst : E(write)+4; 4205 cr : E(write); 4206 src1 : R(read); 4207 src2 : R(read); 4208 IALU : R(3); 4209 BR : R(2); 4210 %} 4211 4212 // Integer ALU operation 4213 pipe_class ialu_none(iRegI dst) %{ 4214 single_instruction; 4215 dst : E(write); 4216 IALU : R; 4217 %} 4218 4219 // Integer ALU reg operation 4220 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4221 single_instruction; may_have_no_code; 4222 dst : E(write); 4223 src : R(read); 4224 IALU : R; 4225 %} 4226 4227 // Integer ALU reg conditional operation 4228 // This instruction has a 1 cycle stall, and cannot execute 4229 // in the same cycle as the instruction setting the condition 4230 // code. We kludge this by pretending to read the condition code 4231 // 1 cycle earlier, and by marking the functional units as busy 4232 // for 2 cycles with the result available 1 cycle later than 4233 // is really the case. 4234 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4235 single_instruction; 4236 op2_out : C(write); 4237 op1 : R(read); 4238 cr : R(read); // This is really E, with a 1 cycle stall 4239 BR : R(2); 4240 MS : R(2); 4241 %} 4242 4243 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4244 instruction_count(1); multiple_bundles; 4245 dst : C(write)+1; 4246 src : R(read)+1; 4247 IALU : R(1); 4248 BR : E(2); 4249 MS : E(2); 4250 %} 4251 4252 // Integer ALU reg operation 4253 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4254 single_instruction; may_have_no_code; 4255 dst : E(write); 4256 src : R(read); 4257 IALU : R; 4258 %} 4259 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4260 single_instruction; may_have_no_code; 4261 dst : E(write); 4262 src : R(read); 4263 IALU : R; 4264 %} 4265 4266 // Two integer ALU reg operations 4267 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4268 instruction_count(2); 4269 dst : E(write); 4270 src : R(read); 4271 A0 : R; 4272 A1 : R; 4273 %} 4274 4275 // Two integer ALU reg operations 4276 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4277 instruction_count(2); may_have_no_code; 4278 dst : E(write); 4279 src : R(read); 4280 A0 : R; 4281 A1 : R; 4282 %} 4283 4284 // Integer ALU imm operation 4285 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4286 single_instruction; 4287 dst : E(write); 4288 IALU : R; 4289 %} 4290 4291 // Integer ALU reg-reg with carry operation 4292 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4293 single_instruction; 4294 dst : E(write); 4295 src1 : R(read); 4296 src2 : R(read); 4297 IALU : R; 4298 %} 4299 4300 // Integer ALU cc operation 4301 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4302 single_instruction; 4303 dst : E(write); 4304 cc : R(read); 4305 IALU : R; 4306 %} 4307 4308 // Integer ALU cc / second IALU operation 4309 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4310 instruction_count(1); multiple_bundles; 4311 dst : E(write)+1; 4312 src : R(read); 4313 IALU : R; 4314 %} 4315 4316 // Integer ALU cc / second IALU operation 4317 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4318 instruction_count(1); multiple_bundles; 4319 dst : E(write)+1; 4320 p : R(read); 4321 q : R(read); 4322 IALU : R; 4323 %} 4324 4325 // Integer ALU hi-lo-reg operation 4326 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4327 instruction_count(1); multiple_bundles; 4328 dst : E(write)+1; 4329 IALU : R(2); 4330 %} 4331 4332 // Float ALU hi-lo-reg operation (with temp) 4333 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4334 instruction_count(1); multiple_bundles; 4335 dst : E(write)+1; 4336 IALU : R(2); 4337 %} 4338 4339 // Long Constant 4340 pipe_class loadConL( iRegL dst, immL src ) %{ 4341 instruction_count(2); multiple_bundles; 4342 dst : E(write)+1; 4343 IALU : R(2); 4344 IALU : R(2); 4345 %} 4346 4347 // Pointer Constant 4348 pipe_class loadConP( iRegP dst, immP src ) %{ 4349 instruction_count(0); multiple_bundles; 4350 fixed_latency(6); 4351 %} 4352 4353 // Polling Address 4354 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4355 instruction_count(0); multiple_bundles; 4356 fixed_latency(6); 4357 %} 4358 4359 // Long Constant small 4360 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4361 instruction_count(2); 4362 dst : E(write); 4363 IALU : R; 4364 IALU : R; 4365 %} 4366 4367 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4368 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4369 instruction_count(1); multiple_bundles; 4370 src : R(read); 4371 dst : M(write)+1; 4372 IALU : R; 4373 MS : E; 4374 %} 4375 4376 // Integer ALU nop operation 4377 pipe_class ialu_nop() %{ 4378 single_instruction; 4379 IALU : R; 4380 %} 4381 4382 // Integer ALU nop operation 4383 pipe_class ialu_nop_A0() %{ 4384 single_instruction; 4385 A0 : R; 4386 %} 4387 4388 // Integer ALU nop operation 4389 pipe_class ialu_nop_A1() %{ 4390 single_instruction; 4391 A1 : R; 4392 %} 4393 4394 // Integer Multiply reg-reg operation 4395 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4396 single_instruction; 4397 dst : E(write); 4398 src1 : R(read); 4399 src2 : R(read); 4400 MS : R(5); 4401 %} 4402 4403 // Integer Multiply reg-imm operation 4404 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4405 single_instruction; 4406 dst : E(write); 4407 src1 : R(read); 4408 MS : R(5); 4409 %} 4410 4411 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4412 single_instruction; 4413 dst : E(write)+4; 4414 src1 : R(read); 4415 src2 : R(read); 4416 MS : R(6); 4417 %} 4418 4419 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4420 single_instruction; 4421 dst : E(write)+4; 4422 src1 : R(read); 4423 MS : R(6); 4424 %} 4425 4426 // Integer Divide reg-reg 4427 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4428 instruction_count(1); multiple_bundles; 4429 dst : E(write); 4430 temp : E(write); 4431 src1 : R(read); 4432 src2 : R(read); 4433 temp : R(read); 4434 MS : R(38); 4435 %} 4436 4437 // Integer Divide reg-imm 4438 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4439 instruction_count(1); multiple_bundles; 4440 dst : E(write); 4441 temp : E(write); 4442 src1 : R(read); 4443 temp : R(read); 4444 MS : R(38); 4445 %} 4446 4447 // Long Divide 4448 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4449 dst : E(write)+71; 4450 src1 : R(read); 4451 src2 : R(read)+1; 4452 MS : R(70); 4453 %} 4454 4455 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4456 dst : E(write)+71; 4457 src1 : R(read); 4458 MS : R(70); 4459 %} 4460 4461 // Floating Point Add Float 4462 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4463 single_instruction; 4464 dst : X(write); 4465 src1 : E(read); 4466 src2 : E(read); 4467 FA : R; 4468 %} 4469 4470 // Floating Point Add Double 4471 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4472 single_instruction; 4473 dst : X(write); 4474 src1 : E(read); 4475 src2 : E(read); 4476 FA : R; 4477 %} 4478 4479 // Floating Point Conditional Move based on integer flags 4480 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4481 single_instruction; 4482 dst : X(write); 4483 src : E(read); 4484 cr : R(read); 4485 FA : R(2); 4486 BR : R(2); 4487 %} 4488 4489 // Floating Point Conditional Move based on integer flags 4490 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4491 single_instruction; 4492 dst : X(write); 4493 src : E(read); 4494 cr : R(read); 4495 FA : R(2); 4496 BR : R(2); 4497 %} 4498 4499 // Floating Point Multiply Float 4500 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4501 single_instruction; 4502 dst : X(write); 4503 src1 : E(read); 4504 src2 : E(read); 4505 FM : R; 4506 %} 4507 4508 // Floating Point Multiply Double 4509 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4510 single_instruction; 4511 dst : X(write); 4512 src1 : E(read); 4513 src2 : E(read); 4514 FM : R; 4515 %} 4516 4517 // Floating Point Divide Float 4518 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4519 single_instruction; 4520 dst : X(write); 4521 src1 : E(read); 4522 src2 : E(read); 4523 FM : R; 4524 FDIV : C(14); 4525 %} 4526 4527 // Floating Point Divide Double 4528 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4529 single_instruction; 4530 dst : X(write); 4531 src1 : E(read); 4532 src2 : E(read); 4533 FM : R; 4534 FDIV : C(17); 4535 %} 4536 4537 // Floating Point Move/Negate/Abs Float 4538 pipe_class faddF_reg(regF dst, regF src) %{ 4539 single_instruction; 4540 dst : W(write); 4541 src : E(read); 4542 FA : R(1); 4543 %} 4544 4545 // Floating Point Move/Negate/Abs Double 4546 pipe_class faddD_reg(regD dst, regD src) %{ 4547 single_instruction; 4548 dst : W(write); 4549 src : E(read); 4550 FA : R; 4551 %} 4552 4553 // Floating Point Convert F->D 4554 pipe_class fcvtF2D(regD dst, regF src) %{ 4555 single_instruction; 4556 dst : X(write); 4557 src : E(read); 4558 FA : R; 4559 %} 4560 4561 // Floating Point Convert I->D 4562 pipe_class fcvtI2D(regD dst, regF src) %{ 4563 single_instruction; 4564 dst : X(write); 4565 src : E(read); 4566 FA : R; 4567 %} 4568 4569 // Floating Point Convert LHi->D 4570 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4571 single_instruction; 4572 dst : X(write); 4573 src : E(read); 4574 FA : R; 4575 %} 4576 4577 // Floating Point Convert L->D 4578 pipe_class fcvtL2D(regD dst, regF src) %{ 4579 single_instruction; 4580 dst : X(write); 4581 src : E(read); 4582 FA : R; 4583 %} 4584 4585 // Floating Point Convert L->F 4586 pipe_class fcvtL2F(regD dst, regF src) %{ 4587 single_instruction; 4588 dst : X(write); 4589 src : E(read); 4590 FA : R; 4591 %} 4592 4593 // Floating Point Convert D->F 4594 pipe_class fcvtD2F(regD dst, regF src) %{ 4595 single_instruction; 4596 dst : X(write); 4597 src : E(read); 4598 FA : R; 4599 %} 4600 4601 // Floating Point Convert I->L 4602 pipe_class fcvtI2L(regD dst, regF src) %{ 4603 single_instruction; 4604 dst : X(write); 4605 src : E(read); 4606 FA : R; 4607 %} 4608 4609 // Floating Point Convert D->F 4610 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4611 instruction_count(1); multiple_bundles; 4612 dst : X(write)+6; 4613 src : E(read); 4614 FA : R; 4615 %} 4616 4617 // Floating Point Convert D->L 4618 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4619 instruction_count(1); multiple_bundles; 4620 dst : X(write)+6; 4621 src : E(read); 4622 FA : R; 4623 %} 4624 4625 // Floating Point Convert F->I 4626 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4627 instruction_count(1); multiple_bundles; 4628 dst : X(write)+6; 4629 src : E(read); 4630 FA : R; 4631 %} 4632 4633 // Floating Point Convert F->L 4634 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4635 instruction_count(1); multiple_bundles; 4636 dst : X(write)+6; 4637 src : E(read); 4638 FA : R; 4639 %} 4640 4641 // Floating Point Convert I->F 4642 pipe_class fcvtI2F(regF dst, regF src) %{ 4643 single_instruction; 4644 dst : X(write); 4645 src : E(read); 4646 FA : R; 4647 %} 4648 4649 // Floating Point Compare 4650 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4651 single_instruction; 4652 cr : X(write); 4653 src1 : E(read); 4654 src2 : E(read); 4655 FA : R; 4656 %} 4657 4658 // Floating Point Compare 4659 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4660 single_instruction; 4661 cr : X(write); 4662 src1 : E(read); 4663 src2 : E(read); 4664 FA : R; 4665 %} 4666 4667 // Floating Add Nop 4668 pipe_class fadd_nop() %{ 4669 single_instruction; 4670 FA : R; 4671 %} 4672 4673 // Integer Store to Memory 4674 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4675 single_instruction; 4676 mem : R(read); 4677 src : C(read); 4678 MS : R; 4679 %} 4680 4681 // Integer Store to Memory 4682 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4683 single_instruction; 4684 mem : R(read); 4685 src : C(read); 4686 MS : R; 4687 %} 4688 4689 // Integer Store Zero to Memory 4690 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4691 single_instruction; 4692 mem : R(read); 4693 MS : R; 4694 %} 4695 4696 // Special Stack Slot Store 4697 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4698 single_instruction; 4699 stkSlot : R(read); 4700 src : C(read); 4701 MS : R; 4702 %} 4703 4704 // Special Stack Slot Store 4705 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4706 instruction_count(2); multiple_bundles; 4707 stkSlot : R(read); 4708 src : C(read); 4709 MS : R(2); 4710 %} 4711 4712 // Float Store 4713 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4714 single_instruction; 4715 mem : R(read); 4716 src : C(read); 4717 MS : R; 4718 %} 4719 4720 // Float Store 4721 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4722 single_instruction; 4723 mem : R(read); 4724 MS : R; 4725 %} 4726 4727 // Double Store 4728 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4729 instruction_count(1); 4730 mem : R(read); 4731 src : C(read); 4732 MS : R; 4733 %} 4734 4735 // Double Store 4736 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 4737 single_instruction; 4738 mem : R(read); 4739 MS : R; 4740 %} 4741 4742 // Special Stack Slot Float Store 4743 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 4744 single_instruction; 4745 stkSlot : R(read); 4746 src : C(read); 4747 MS : R; 4748 %} 4749 4750 // Special Stack Slot Double Store 4751 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 4752 single_instruction; 4753 stkSlot : R(read); 4754 src : C(read); 4755 MS : R; 4756 %} 4757 4758 // Integer Load (when sign bit propagation not needed) 4759 pipe_class iload_mem(iRegI dst, memory mem) %{ 4760 single_instruction; 4761 mem : R(read); 4762 dst : C(write); 4763 MS : R; 4764 %} 4765 4766 // Integer Load from stack operand 4767 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 4768 single_instruction; 4769 mem : R(read); 4770 dst : C(write); 4771 MS : R; 4772 %} 4773 4774 // Integer Load (when sign bit propagation or masking is needed) 4775 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 4776 single_instruction; 4777 mem : R(read); 4778 dst : M(write); 4779 MS : R; 4780 %} 4781 4782 // Float Load 4783 pipe_class floadF_mem(regF dst, memory mem) %{ 4784 single_instruction; 4785 mem : R(read); 4786 dst : M(write); 4787 MS : R; 4788 %} 4789 4790 // Float Load 4791 pipe_class floadD_mem(regD dst, memory mem) %{ 4792 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 4793 mem : R(read); 4794 dst : M(write); 4795 MS : R; 4796 %} 4797 4798 // Float Load 4799 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 4800 single_instruction; 4801 stkSlot : R(read); 4802 dst : M(write); 4803 MS : R; 4804 %} 4805 4806 // Float Load 4807 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 4808 single_instruction; 4809 stkSlot : R(read); 4810 dst : M(write); 4811 MS : R; 4812 %} 4813 4814 // Memory Nop 4815 pipe_class mem_nop() %{ 4816 single_instruction; 4817 MS : R; 4818 %} 4819 4820 pipe_class sethi(iRegP dst, immI src) %{ 4821 single_instruction; 4822 dst : E(write); 4823 IALU : R; 4824 %} 4825 4826 pipe_class loadPollP(iRegP poll) %{ 4827 single_instruction; 4828 poll : R(read); 4829 MS : R; 4830 %} 4831 4832 pipe_class br(Universe br, label labl) %{ 4833 single_instruction_with_delay_slot; 4834 BR : R; 4835 %} 4836 4837 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 4838 single_instruction_with_delay_slot; 4839 cr : E(read); 4840 BR : R; 4841 %} 4842 4843 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 4844 single_instruction_with_delay_slot; 4845 op1 : E(read); 4846 BR : R; 4847 MS : R; 4848 %} 4849 4850 // Compare and branch 4851 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 4852 instruction_count(2); has_delay_slot; 4853 cr : E(write); 4854 src1 : R(read); 4855 src2 : R(read); 4856 IALU : R; 4857 BR : R; 4858 %} 4859 4860 // Compare and branch 4861 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 4862 instruction_count(2); has_delay_slot; 4863 cr : E(write); 4864 src1 : R(read); 4865 IALU : R; 4866 BR : R; 4867 %} 4868 4869 // Compare and branch using cbcond 4870 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 4871 single_instruction; 4872 src1 : E(read); 4873 src2 : E(read); 4874 IALU : R; 4875 BR : R; 4876 %} 4877 4878 // Compare and branch using cbcond 4879 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 4880 single_instruction; 4881 src1 : E(read); 4882 IALU : R; 4883 BR : R; 4884 %} 4885 4886 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 4887 single_instruction_with_delay_slot; 4888 cr : E(read); 4889 BR : R; 4890 %} 4891 4892 pipe_class br_nop() %{ 4893 single_instruction; 4894 BR : R; 4895 %} 4896 4897 pipe_class simple_call(method meth) %{ 4898 instruction_count(2); multiple_bundles; force_serialization; 4899 fixed_latency(100); 4900 BR : R(1); 4901 MS : R(1); 4902 A0 : R(1); 4903 %} 4904 4905 pipe_class compiled_call(method meth) %{ 4906 instruction_count(1); multiple_bundles; force_serialization; 4907 fixed_latency(100); 4908 MS : R(1); 4909 %} 4910 4911 pipe_class call(method meth) %{ 4912 instruction_count(0); multiple_bundles; force_serialization; 4913 fixed_latency(100); 4914 %} 4915 4916 pipe_class tail_call(Universe ignore, label labl) %{ 4917 single_instruction; has_delay_slot; 4918 fixed_latency(100); 4919 BR : R(1); 4920 MS : R(1); 4921 %} 4922 4923 pipe_class ret(Universe ignore) %{ 4924 single_instruction; has_delay_slot; 4925 BR : R(1); 4926 MS : R(1); 4927 %} 4928 4929 pipe_class ret_poll(g3RegP poll) %{ 4930 instruction_count(3); has_delay_slot; 4931 poll : E(read); 4932 MS : R; 4933 %} 4934 4935 // The real do-nothing guy 4936 pipe_class empty( ) %{ 4937 instruction_count(0); 4938 %} 4939 4940 pipe_class long_memory_op() %{ 4941 instruction_count(0); multiple_bundles; force_serialization; 4942 fixed_latency(25); 4943 MS : R(1); 4944 %} 4945 4946 // Check-cast 4947 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 4948 array : R(read); 4949 match : R(read); 4950 IALU : R(2); 4951 BR : R(2); 4952 MS : R; 4953 %} 4954 4955 // Convert FPU flags into +1,0,-1 4956 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 4957 src1 : E(read); 4958 src2 : E(read); 4959 dst : E(write); 4960 FA : R; 4961 MS : R(2); 4962 BR : R(2); 4963 %} 4964 4965 // Compare for p < q, and conditionally add y 4966 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 4967 p : E(read); 4968 q : E(read); 4969 y : E(read); 4970 IALU : R(3) 4971 %} 4972 4973 // Perform a compare, then move conditionally in a branch delay slot. 4974 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 4975 src2 : E(read); 4976 srcdst : E(read); 4977 IALU : R; 4978 BR : R; 4979 %} 4980 4981 // Define the class for the Nop node 4982 define %{ 4983 MachNop = ialu_nop; 4984 %} 4985 4986 %} 4987 4988 //----------INSTRUCTIONS------------------------------------------------------- 4989 4990 //------------Special Stack Slot instructions - no match rules----------------- 4991 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 4992 // No match rule to avoid chain rule match. 4993 effect(DEF dst, USE src); 4994 ins_cost(MEMORY_REF_COST); 4995 format %{ "LDF $src,$dst\t! stkI to regF" %} 4996 opcode(Assembler::ldf_op3); 4997 ins_encode(simple_form3_mem_reg(src, dst)); 4998 ins_pipe(floadF_stk); 4999 %} 5000 5001 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5002 // No match rule to avoid chain rule match. 5003 effect(DEF dst, USE src); 5004 ins_cost(MEMORY_REF_COST); 5005 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5006 opcode(Assembler::lddf_op3); 5007 ins_encode(simple_form3_mem_reg(src, dst)); 5008 ins_pipe(floadD_stk); 5009 %} 5010 5011 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5012 // No match rule to avoid chain rule match. 5013 effect(DEF dst, USE src); 5014 ins_cost(MEMORY_REF_COST); 5015 format %{ "STF $src,$dst\t! regF to stkI" %} 5016 opcode(Assembler::stf_op3); 5017 ins_encode(simple_form3_mem_reg(dst, src)); 5018 ins_pipe(fstoreF_stk_reg); 5019 %} 5020 5021 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5022 // No match rule to avoid chain rule match. 5023 effect(DEF dst, USE src); 5024 ins_cost(MEMORY_REF_COST); 5025 format %{ "STDF $src,$dst\t! regD to stkL" %} 5026 opcode(Assembler::stdf_op3); 5027 ins_encode(simple_form3_mem_reg(dst, src)); 5028 ins_pipe(fstoreD_stk_reg); 5029 %} 5030 5031 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5032 effect(DEF dst, USE src); 5033 ins_cost(MEMORY_REF_COST*2); 5034 format %{ "STW $src,$dst.hi\t! long\n\t" 5035 "STW R_G0,$dst.lo" %} 5036 opcode(Assembler::stw_op3); 5037 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5038 ins_pipe(lstoreI_stk_reg); 5039 %} 5040 5041 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5042 // No match rule to avoid chain rule match. 5043 effect(DEF dst, USE src); 5044 ins_cost(MEMORY_REF_COST); 5045 format %{ "STX $src,$dst\t! regL to stkD" %} 5046 opcode(Assembler::stx_op3); 5047 ins_encode(simple_form3_mem_reg( dst, src ) ); 5048 ins_pipe(istore_stk_reg); 5049 %} 5050 5051 //---------- Chain stack slots between similar types -------- 5052 5053 // Load integer from stack slot 5054 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5055 match(Set dst src); 5056 ins_cost(MEMORY_REF_COST); 5057 5058 format %{ "LDUW $src,$dst\t!stk" %} 5059 opcode(Assembler::lduw_op3); 5060 ins_encode(simple_form3_mem_reg( src, dst ) ); 5061 ins_pipe(iload_mem); 5062 %} 5063 5064 // Store integer to stack slot 5065 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5066 match(Set dst src); 5067 ins_cost(MEMORY_REF_COST); 5068 5069 format %{ "STW $src,$dst\t!stk" %} 5070 opcode(Assembler::stw_op3); 5071 ins_encode(simple_form3_mem_reg( dst, src ) ); 5072 ins_pipe(istore_mem_reg); 5073 %} 5074 5075 // Load long from stack slot 5076 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5077 match(Set dst src); 5078 5079 ins_cost(MEMORY_REF_COST); 5080 format %{ "LDX $src,$dst\t! long" %} 5081 opcode(Assembler::ldx_op3); 5082 ins_encode(simple_form3_mem_reg( src, dst ) ); 5083 ins_pipe(iload_mem); 5084 %} 5085 5086 // Store long to stack slot 5087 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5088 match(Set dst src); 5089 5090 ins_cost(MEMORY_REF_COST); 5091 format %{ "STX $src,$dst\t! long" %} 5092 opcode(Assembler::stx_op3); 5093 ins_encode(simple_form3_mem_reg( dst, src ) ); 5094 ins_pipe(istore_mem_reg); 5095 %} 5096 5097 // Load pointer from stack slot, 64-bit encoding 5098 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5099 match(Set dst src); 5100 ins_cost(MEMORY_REF_COST); 5101 format %{ "LDX $src,$dst\t!ptr" %} 5102 opcode(Assembler::ldx_op3); 5103 ins_encode(simple_form3_mem_reg( src, dst ) ); 5104 ins_pipe(iload_mem); 5105 %} 5106 5107 // Store pointer to stack slot 5108 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5109 match(Set dst src); 5110 ins_cost(MEMORY_REF_COST); 5111 format %{ "STX $src,$dst\t!ptr" %} 5112 opcode(Assembler::stx_op3); 5113 ins_encode(simple_form3_mem_reg( dst, src ) ); 5114 ins_pipe(istore_mem_reg); 5115 %} 5116 5117 //------------Special Nop instructions for bundling - no match rules----------- 5118 // Nop using the A0 functional unit 5119 instruct Nop_A0() %{ 5120 ins_cost(0); 5121 5122 format %{ "NOP ! Alu Pipeline" %} 5123 opcode(Assembler::or_op3, Assembler::arith_op); 5124 ins_encode( form2_nop() ); 5125 ins_pipe(ialu_nop_A0); 5126 %} 5127 5128 // Nop using the A1 functional unit 5129 instruct Nop_A1( ) %{ 5130 ins_cost(0); 5131 5132 format %{ "NOP ! Alu Pipeline" %} 5133 opcode(Assembler::or_op3, Assembler::arith_op); 5134 ins_encode( form2_nop() ); 5135 ins_pipe(ialu_nop_A1); 5136 %} 5137 5138 // Nop using the memory functional unit 5139 instruct Nop_MS( ) %{ 5140 ins_cost(0); 5141 5142 format %{ "NOP ! Memory Pipeline" %} 5143 ins_encode( emit_mem_nop ); 5144 ins_pipe(mem_nop); 5145 %} 5146 5147 // Nop using the floating add functional unit 5148 instruct Nop_FA( ) %{ 5149 ins_cost(0); 5150 5151 format %{ "NOP ! Floating Add Pipeline" %} 5152 ins_encode( emit_fadd_nop ); 5153 ins_pipe(fadd_nop); 5154 %} 5155 5156 // Nop using the branch functional unit 5157 instruct Nop_BR( ) %{ 5158 ins_cost(0); 5159 5160 format %{ "NOP ! Branch Pipeline" %} 5161 ins_encode( emit_br_nop ); 5162 ins_pipe(br_nop); 5163 %} 5164 5165 //----------Load/Store/Move Instructions--------------------------------------- 5166 //----------Load Instructions-------------------------------------------------- 5167 // Load Byte (8bit signed) 5168 instruct loadB(iRegI dst, memory mem) %{ 5169 match(Set dst (LoadB mem)); 5170 ins_cost(MEMORY_REF_COST); 5171 5172 size(4); 5173 format %{ "LDSB $mem,$dst\t! byte" %} 5174 ins_encode %{ 5175 __ ldsb($mem$$Address, $dst$$Register); 5176 %} 5177 ins_pipe(iload_mask_mem); 5178 %} 5179 5180 // Load Byte (8bit signed) into a Long Register 5181 instruct loadB2L(iRegL dst, memory mem) %{ 5182 match(Set dst (ConvI2L (LoadB mem))); 5183 ins_cost(MEMORY_REF_COST); 5184 5185 size(4); 5186 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5187 ins_encode %{ 5188 __ ldsb($mem$$Address, $dst$$Register); 5189 %} 5190 ins_pipe(iload_mask_mem); 5191 %} 5192 5193 // Load Unsigned Byte (8bit UNsigned) into an int reg 5194 instruct loadUB(iRegI dst, memory mem) %{ 5195 match(Set dst (LoadUB mem)); 5196 ins_cost(MEMORY_REF_COST); 5197 5198 size(4); 5199 format %{ "LDUB $mem,$dst\t! ubyte" %} 5200 ins_encode %{ 5201 __ ldub($mem$$Address, $dst$$Register); 5202 %} 5203 ins_pipe(iload_mem); 5204 %} 5205 5206 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5207 instruct loadUB2L(iRegL dst, memory mem) %{ 5208 match(Set dst (ConvI2L (LoadUB mem))); 5209 ins_cost(MEMORY_REF_COST); 5210 5211 size(4); 5212 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5213 ins_encode %{ 5214 __ ldub($mem$$Address, $dst$$Register); 5215 %} 5216 ins_pipe(iload_mem); 5217 %} 5218 5219 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register 5220 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{ 5221 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5222 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5223 5224 size(2*4); 5225 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t" 5226 "AND $dst,right_n_bits($mask, 8),$dst" %} 5227 ins_encode %{ 5228 __ ldub($mem$$Address, $dst$$Register); 5229 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register); 5230 %} 5231 ins_pipe(iload_mem); 5232 %} 5233 5234 // Load Short (16bit signed) 5235 instruct loadS(iRegI dst, memory mem) %{ 5236 match(Set dst (LoadS mem)); 5237 ins_cost(MEMORY_REF_COST); 5238 5239 size(4); 5240 format %{ "LDSH $mem,$dst\t! short" %} 5241 ins_encode %{ 5242 __ ldsh($mem$$Address, $dst$$Register); 5243 %} 5244 ins_pipe(iload_mask_mem); 5245 %} 5246 5247 // Load Short (16 bit signed) to Byte (8 bit signed) 5248 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5249 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5250 ins_cost(MEMORY_REF_COST); 5251 5252 size(4); 5253 5254 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5255 ins_encode %{ 5256 __ ldsb($mem$$Address, $dst$$Register, 1); 5257 %} 5258 ins_pipe(iload_mask_mem); 5259 %} 5260 5261 // Load Short (16bit signed) into a Long Register 5262 instruct loadS2L(iRegL dst, memory mem) %{ 5263 match(Set dst (ConvI2L (LoadS mem))); 5264 ins_cost(MEMORY_REF_COST); 5265 5266 size(4); 5267 format %{ "LDSH $mem,$dst\t! short -> long" %} 5268 ins_encode %{ 5269 __ ldsh($mem$$Address, $dst$$Register); 5270 %} 5271 ins_pipe(iload_mask_mem); 5272 %} 5273 5274 // Load Unsigned Short/Char (16bit UNsigned) 5275 instruct loadUS(iRegI dst, memory mem) %{ 5276 match(Set dst (LoadUS mem)); 5277 ins_cost(MEMORY_REF_COST); 5278 5279 size(4); 5280 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5281 ins_encode %{ 5282 __ lduh($mem$$Address, $dst$$Register); 5283 %} 5284 ins_pipe(iload_mem); 5285 %} 5286 5287 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5288 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5289 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5290 ins_cost(MEMORY_REF_COST); 5291 5292 size(4); 5293 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5294 ins_encode %{ 5295 __ ldsb($mem$$Address, $dst$$Register, 1); 5296 %} 5297 ins_pipe(iload_mask_mem); 5298 %} 5299 5300 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5301 instruct loadUS2L(iRegL dst, memory mem) %{ 5302 match(Set dst (ConvI2L (LoadUS mem))); 5303 ins_cost(MEMORY_REF_COST); 5304 5305 size(4); 5306 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5307 ins_encode %{ 5308 __ lduh($mem$$Address, $dst$$Register); 5309 %} 5310 ins_pipe(iload_mem); 5311 %} 5312 5313 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5314 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5315 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5316 ins_cost(MEMORY_REF_COST); 5317 5318 size(4); 5319 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5320 ins_encode %{ 5321 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5322 %} 5323 ins_pipe(iload_mem); 5324 %} 5325 5326 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5327 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5328 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5329 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5330 5331 size(2*4); 5332 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5333 "AND $dst,$mask,$dst" %} 5334 ins_encode %{ 5335 Register Rdst = $dst$$Register; 5336 __ lduh($mem$$Address, Rdst); 5337 __ and3(Rdst, $mask$$constant, Rdst); 5338 %} 5339 ins_pipe(iload_mem); 5340 %} 5341 5342 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register 5343 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5344 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5345 effect(TEMP dst, TEMP tmp); 5346 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5347 5348 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t" 5349 "SET right_n_bits($mask, 16),$tmp\n\t" 5350 "AND $dst,$tmp,$dst" %} 5351 ins_encode %{ 5352 Register Rdst = $dst$$Register; 5353 Register Rtmp = $tmp$$Register; 5354 __ lduh($mem$$Address, Rdst); 5355 __ set($mask$$constant & right_n_bits(16), Rtmp); 5356 __ and3(Rdst, Rtmp, Rdst); 5357 %} 5358 ins_pipe(iload_mem); 5359 %} 5360 5361 // Load Integer 5362 instruct loadI(iRegI dst, memory mem) %{ 5363 match(Set dst (LoadI mem)); 5364 ins_cost(MEMORY_REF_COST); 5365 5366 size(4); 5367 format %{ "LDUW $mem,$dst\t! int" %} 5368 ins_encode %{ 5369 __ lduw($mem$$Address, $dst$$Register); 5370 %} 5371 ins_pipe(iload_mem); 5372 %} 5373 5374 // Load Integer to Byte (8 bit signed) 5375 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5376 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5377 ins_cost(MEMORY_REF_COST); 5378 5379 size(4); 5380 5381 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5382 ins_encode %{ 5383 __ ldsb($mem$$Address, $dst$$Register, 3); 5384 %} 5385 ins_pipe(iload_mask_mem); 5386 %} 5387 5388 // Load Integer to Unsigned Byte (8 bit UNsigned) 5389 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5390 match(Set dst (AndI (LoadI mem) mask)); 5391 ins_cost(MEMORY_REF_COST); 5392 5393 size(4); 5394 5395 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5396 ins_encode %{ 5397 __ ldub($mem$$Address, $dst$$Register, 3); 5398 %} 5399 ins_pipe(iload_mask_mem); 5400 %} 5401 5402 // Load Integer to Short (16 bit signed) 5403 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5404 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5405 ins_cost(MEMORY_REF_COST); 5406 5407 size(4); 5408 5409 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5410 ins_encode %{ 5411 __ ldsh($mem$$Address, $dst$$Register, 2); 5412 %} 5413 ins_pipe(iload_mask_mem); 5414 %} 5415 5416 // Load Integer to Unsigned Short (16 bit UNsigned) 5417 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5418 match(Set dst (AndI (LoadI mem) mask)); 5419 ins_cost(MEMORY_REF_COST); 5420 5421 size(4); 5422 5423 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5424 ins_encode %{ 5425 __ lduh($mem$$Address, $dst$$Register, 2); 5426 %} 5427 ins_pipe(iload_mask_mem); 5428 %} 5429 5430 // Load Integer into a Long Register 5431 instruct loadI2L(iRegL dst, memory mem) %{ 5432 match(Set dst (ConvI2L (LoadI mem))); 5433 ins_cost(MEMORY_REF_COST); 5434 5435 size(4); 5436 format %{ "LDSW $mem,$dst\t! int -> long" %} 5437 ins_encode %{ 5438 __ ldsw($mem$$Address, $dst$$Register); 5439 %} 5440 ins_pipe(iload_mask_mem); 5441 %} 5442 5443 // Load Integer with mask 0xFF into a Long Register 5444 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5445 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5446 ins_cost(MEMORY_REF_COST); 5447 5448 size(4); 5449 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5450 ins_encode %{ 5451 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5452 %} 5453 ins_pipe(iload_mem); 5454 %} 5455 5456 // Load Integer with mask 0xFFFF into a Long Register 5457 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5458 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5459 ins_cost(MEMORY_REF_COST); 5460 5461 size(4); 5462 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5463 ins_encode %{ 5464 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5465 %} 5466 ins_pipe(iload_mem); 5467 %} 5468 5469 // Load Integer with a 12-bit mask into a Long Register 5470 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ 5471 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5472 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5473 5474 size(2*4); 5475 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" 5476 "AND $dst,$mask,$dst" %} 5477 ins_encode %{ 5478 Register Rdst = $dst$$Register; 5479 __ lduw($mem$$Address, Rdst); 5480 __ and3(Rdst, $mask$$constant, Rdst); 5481 %} 5482 ins_pipe(iload_mem); 5483 %} 5484 5485 // Load Integer with a 31-bit mask into a Long Register 5486 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ 5487 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5488 effect(TEMP dst, TEMP tmp); 5489 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5490 5491 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" 5492 "SET $mask,$tmp\n\t" 5493 "AND $dst,$tmp,$dst" %} 5494 ins_encode %{ 5495 Register Rdst = $dst$$Register; 5496 Register Rtmp = $tmp$$Register; 5497 __ lduw($mem$$Address, Rdst); 5498 __ set($mask$$constant, Rtmp); 5499 __ and3(Rdst, Rtmp, Rdst); 5500 %} 5501 ins_pipe(iload_mem); 5502 %} 5503 5504 // Load Unsigned Integer into a Long Register 5505 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ 5506 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5507 ins_cost(MEMORY_REF_COST); 5508 5509 size(4); 5510 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5511 ins_encode %{ 5512 __ lduw($mem$$Address, $dst$$Register); 5513 %} 5514 ins_pipe(iload_mem); 5515 %} 5516 5517 // Load Long - aligned 5518 instruct loadL(iRegL dst, memory mem ) %{ 5519 match(Set dst (LoadL mem)); 5520 ins_cost(MEMORY_REF_COST); 5521 5522 size(4); 5523 format %{ "LDX $mem,$dst\t! long" %} 5524 ins_encode %{ 5525 __ ldx($mem$$Address, $dst$$Register); 5526 %} 5527 ins_pipe(iload_mem); 5528 %} 5529 5530 // Load Long - UNaligned 5531 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5532 match(Set dst (LoadL_unaligned mem)); 5533 effect(KILL tmp); 5534 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5535 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5536 "\tLDUW $mem ,$dst\n" 5537 "\tSLLX #32, $dst, $dst\n" 5538 "\tOR $dst, R_O7, $dst" %} 5539 opcode(Assembler::lduw_op3); 5540 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5541 ins_pipe(iload_mem); 5542 %} 5543 5544 // Load Range 5545 instruct loadRange(iRegI dst, memory mem) %{ 5546 match(Set dst (LoadRange mem)); 5547 ins_cost(MEMORY_REF_COST); 5548 5549 format %{ "LDUW $mem,$dst\t! range" %} 5550 opcode(Assembler::lduw_op3); 5551 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5552 ins_pipe(iload_mem); 5553 %} 5554 5555 // Load Integer into %f register (for fitos/fitod) 5556 instruct loadI_freg(regF dst, memory mem) %{ 5557 match(Set dst (LoadI mem)); 5558 ins_cost(MEMORY_REF_COST); 5559 5560 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5561 opcode(Assembler::ldf_op3); 5562 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5563 ins_pipe(floadF_mem); 5564 %} 5565 5566 // Load Pointer 5567 instruct loadP(iRegP dst, memory mem) %{ 5568 match(Set dst (LoadP mem)); 5569 ins_cost(MEMORY_REF_COST); 5570 size(4); 5571 5572 format %{ "LDX $mem,$dst\t! ptr" %} 5573 ins_encode %{ 5574 __ ldx($mem$$Address, $dst$$Register); 5575 %} 5576 ins_pipe(iload_mem); 5577 %} 5578 5579 // Load Compressed Pointer 5580 instruct loadN(iRegN dst, memory mem) %{ 5581 match(Set dst (LoadN mem)); 5582 ins_cost(MEMORY_REF_COST); 5583 size(4); 5584 5585 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5586 ins_encode %{ 5587 __ lduw($mem$$Address, $dst$$Register); 5588 %} 5589 ins_pipe(iload_mem); 5590 %} 5591 5592 // Load Klass Pointer 5593 instruct loadKlass(iRegP dst, memory mem) %{ 5594 match(Set dst (LoadKlass mem)); 5595 ins_cost(MEMORY_REF_COST); 5596 size(4); 5597 5598 format %{ "LDX $mem,$dst\t! klass ptr" %} 5599 ins_encode %{ 5600 __ ldx($mem$$Address, $dst$$Register); 5601 %} 5602 ins_pipe(iload_mem); 5603 %} 5604 5605 // Load narrow Klass Pointer 5606 instruct loadNKlass(iRegN dst, memory mem) %{ 5607 match(Set dst (LoadNKlass mem)); 5608 ins_cost(MEMORY_REF_COST); 5609 size(4); 5610 5611 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5612 ins_encode %{ 5613 __ lduw($mem$$Address, $dst$$Register); 5614 %} 5615 ins_pipe(iload_mem); 5616 %} 5617 5618 // Load Double 5619 instruct loadD(regD dst, memory mem) %{ 5620 match(Set dst (LoadD mem)); 5621 ins_cost(MEMORY_REF_COST); 5622 5623 format %{ "LDDF $mem,$dst" %} 5624 opcode(Assembler::lddf_op3); 5625 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5626 ins_pipe(floadD_mem); 5627 %} 5628 5629 // Load Double - UNaligned 5630 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5631 match(Set dst (LoadD_unaligned mem)); 5632 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5633 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5634 "\tLDF $mem+4,$dst.lo\t!" %} 5635 opcode(Assembler::ldf_op3); 5636 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5637 ins_pipe(iload_mem); 5638 %} 5639 5640 // Load Float 5641 instruct loadF(regF dst, memory mem) %{ 5642 match(Set dst (LoadF mem)); 5643 ins_cost(MEMORY_REF_COST); 5644 5645 format %{ "LDF $mem,$dst" %} 5646 opcode(Assembler::ldf_op3); 5647 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5648 ins_pipe(floadF_mem); 5649 %} 5650 5651 // Load Constant 5652 instruct loadConI( iRegI dst, immI src ) %{ 5653 match(Set dst src); 5654 ins_cost(DEFAULT_COST * 3/2); 5655 format %{ "SET $src,$dst" %} 5656 ins_encode( Set32(src, dst) ); 5657 ins_pipe(ialu_hi_lo_reg); 5658 %} 5659 5660 instruct loadConI13( iRegI dst, immI13 src ) %{ 5661 match(Set dst src); 5662 5663 size(4); 5664 format %{ "MOV $src,$dst" %} 5665 ins_encode( Set13( src, dst ) ); 5666 ins_pipe(ialu_imm); 5667 %} 5668 5669 instruct loadConP_set(iRegP dst, immP_set con) %{ 5670 match(Set dst con); 5671 ins_cost(DEFAULT_COST * 3/2); 5672 format %{ "SET $con,$dst\t! ptr" %} 5673 ins_encode %{ 5674 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 5675 intptr_t val = $con$$constant; 5676 if (constant_reloc == relocInfo::oop_type) { 5677 __ set_oop_constant((jobject) val, $dst$$Register); 5678 } else if (constant_reloc == relocInfo::metadata_type) { 5679 __ set_metadata_constant((Metadata*)val, $dst$$Register); 5680 } else { // non-oop pointers, e.g. card mark base, heap top 5681 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 5682 __ set(val, $dst$$Register); 5683 } 5684 %} 5685 ins_pipe(loadConP); 5686 %} 5687 5688 instruct loadConP_load(iRegP dst, immP_load con) %{ 5689 match(Set dst con); 5690 ins_cost(MEMORY_REF_COST); 5691 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 5692 ins_encode %{ 5693 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 5694 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 5695 %} 5696 ins_pipe(loadConP); 5697 %} 5698 5699 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 5700 match(Set dst con); 5701 ins_cost(DEFAULT_COST * 3/2); 5702 format %{ "SET $con,$dst\t! non-oop ptr" %} 5703 ins_encode %{ 5704 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) { 5705 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register); 5706 } else { 5707 __ set($con$$constant, $dst$$Register); 5708 } 5709 %} 5710 ins_pipe(loadConP); 5711 %} 5712 5713 instruct loadConP0(iRegP dst, immP0 src) %{ 5714 match(Set dst src); 5715 5716 size(4); 5717 format %{ "CLR $dst\t!ptr" %} 5718 ins_encode %{ 5719 __ clr($dst$$Register); 5720 %} 5721 ins_pipe(ialu_imm); 5722 %} 5723 5724 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 5725 match(Set dst src); 5726 ins_cost(DEFAULT_COST); 5727 format %{ "SET $src,$dst\t!ptr" %} 5728 ins_encode %{ 5729 AddressLiteral polling_page(os::get_polling_page()); 5730 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 5731 %} 5732 ins_pipe(loadConP_poll); 5733 %} 5734 5735 instruct loadConN0(iRegN dst, immN0 src) %{ 5736 match(Set dst src); 5737 5738 size(4); 5739 format %{ "CLR $dst\t! compressed NULL ptr" %} 5740 ins_encode %{ 5741 __ clr($dst$$Register); 5742 %} 5743 ins_pipe(ialu_imm); 5744 %} 5745 5746 instruct loadConN(iRegN dst, immN src) %{ 5747 match(Set dst src); 5748 ins_cost(DEFAULT_COST * 3/2); 5749 format %{ "SET $src,$dst\t! compressed ptr" %} 5750 ins_encode %{ 5751 Register dst = $dst$$Register; 5752 __ set_narrow_oop((jobject)$src$$constant, dst); 5753 %} 5754 ins_pipe(ialu_hi_lo_reg); 5755 %} 5756 5757 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 5758 match(Set dst src); 5759 ins_cost(DEFAULT_COST * 3/2); 5760 format %{ "SET $src,$dst\t! compressed klass ptr" %} 5761 ins_encode %{ 5762 Register dst = $dst$$Register; 5763 __ set_narrow_klass((Klass*)$src$$constant, dst); 5764 %} 5765 ins_pipe(ialu_hi_lo_reg); 5766 %} 5767 5768 // Materialize long value (predicated by immL_cheap). 5769 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 5770 match(Set dst con); 5771 effect(KILL tmp); 5772 ins_cost(DEFAULT_COST * 3); 5773 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 5774 ins_encode %{ 5775 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 5776 %} 5777 ins_pipe(loadConL); 5778 %} 5779 5780 // Load long value from constant table (predicated by immL_expensive). 5781 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 5782 match(Set dst con); 5783 ins_cost(MEMORY_REF_COST); 5784 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 5785 ins_encode %{ 5786 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 5787 __ ldx($constanttablebase, con_offset, $dst$$Register); 5788 %} 5789 ins_pipe(loadConL); 5790 %} 5791 5792 instruct loadConL0( iRegL dst, immL0 src ) %{ 5793 match(Set dst src); 5794 ins_cost(DEFAULT_COST); 5795 size(4); 5796 format %{ "CLR $dst\t! long" %} 5797 ins_encode( Set13( src, dst ) ); 5798 ins_pipe(ialu_imm); 5799 %} 5800 5801 instruct loadConL13( iRegL dst, immL13 src ) %{ 5802 match(Set dst src); 5803 ins_cost(DEFAULT_COST * 2); 5804 5805 size(4); 5806 format %{ "MOV $src,$dst\t! long" %} 5807 ins_encode( Set13( src, dst ) ); 5808 ins_pipe(ialu_imm); 5809 %} 5810 5811 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 5812 match(Set dst con); 5813 effect(KILL tmp); 5814 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 5815 ins_encode %{ 5816 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 5817 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 5818 %} 5819 ins_pipe(loadConFD); 5820 %} 5821 5822 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 5823 match(Set dst con); 5824 effect(KILL tmp); 5825 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 5826 ins_encode %{ 5827 // XXX This is a quick fix for 6833573. 5828 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 5829 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 5830 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 5831 %} 5832 ins_pipe(loadConFD); 5833 %} 5834 5835 // Prefetch instructions for allocation. 5836 // Must be safe to execute with invalid address (cannot fault). 5837 5838 instruct prefetchAlloc( memory mem ) %{ 5839 predicate(AllocatePrefetchInstr == 0); 5840 match( PrefetchAllocation mem ); 5841 ins_cost(MEMORY_REF_COST); 5842 5843 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} 5844 opcode(Assembler::prefetch_op3); 5845 ins_encode( form3_mem_prefetch_write( mem ) ); 5846 ins_pipe(iload_mem); 5847 %} 5848 5849 // Use BIS instruction to prefetch for allocation. 5850 // Could fault, need space at the end of TLAB. 5851 instruct prefetchAlloc_bis( iRegP dst ) %{ 5852 predicate(AllocatePrefetchInstr == 1); 5853 match( PrefetchAllocation dst ); 5854 ins_cost(MEMORY_REF_COST); 5855 size(4); 5856 5857 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} 5858 ins_encode %{ 5859 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 5860 %} 5861 ins_pipe(istore_mem_reg); 5862 %} 5863 5864 // Next code is used for finding next cache line address to prefetch. 5865 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ 5866 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 5867 ins_cost(DEFAULT_COST); 5868 size(4); 5869 5870 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 5871 ins_encode %{ 5872 __ and3($src$$Register, $mask$$constant, $dst$$Register); 5873 %} 5874 ins_pipe(ialu_reg_imm); 5875 %} 5876 5877 //----------Store Instructions------------------------------------------------- 5878 // Store Byte 5879 instruct storeB(memory mem, iRegI src) %{ 5880 match(Set mem (StoreB mem src)); 5881 ins_cost(MEMORY_REF_COST); 5882 5883 format %{ "STB $src,$mem\t! byte" %} 5884 opcode(Assembler::stb_op3); 5885 ins_encode(simple_form3_mem_reg( mem, src ) ); 5886 ins_pipe(istore_mem_reg); 5887 %} 5888 5889 instruct storeB0(memory mem, immI0 src) %{ 5890 match(Set mem (StoreB mem src)); 5891 ins_cost(MEMORY_REF_COST); 5892 5893 format %{ "STB $src,$mem\t! byte" %} 5894 opcode(Assembler::stb_op3); 5895 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5896 ins_pipe(istore_mem_zero); 5897 %} 5898 5899 instruct storeCM0(memory mem, immI0 src) %{ 5900 match(Set mem (StoreCM mem src)); 5901 ins_cost(MEMORY_REF_COST); 5902 5903 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 5904 opcode(Assembler::stb_op3); 5905 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5906 ins_pipe(istore_mem_zero); 5907 %} 5908 5909 // Store Char/Short 5910 instruct storeC(memory mem, iRegI src) %{ 5911 match(Set mem (StoreC mem src)); 5912 ins_cost(MEMORY_REF_COST); 5913 5914 format %{ "STH $src,$mem\t! short" %} 5915 opcode(Assembler::sth_op3); 5916 ins_encode(simple_form3_mem_reg( mem, src ) ); 5917 ins_pipe(istore_mem_reg); 5918 %} 5919 5920 instruct storeC0(memory mem, immI0 src) %{ 5921 match(Set mem (StoreC mem src)); 5922 ins_cost(MEMORY_REF_COST); 5923 5924 format %{ "STH $src,$mem\t! short" %} 5925 opcode(Assembler::sth_op3); 5926 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5927 ins_pipe(istore_mem_zero); 5928 %} 5929 5930 // Store Integer 5931 instruct storeI(memory mem, iRegI src) %{ 5932 match(Set mem (StoreI mem src)); 5933 ins_cost(MEMORY_REF_COST); 5934 5935 format %{ "STW $src,$mem" %} 5936 opcode(Assembler::stw_op3); 5937 ins_encode(simple_form3_mem_reg( mem, src ) ); 5938 ins_pipe(istore_mem_reg); 5939 %} 5940 5941 // Store Long 5942 instruct storeL(memory mem, iRegL src) %{ 5943 match(Set mem (StoreL mem src)); 5944 ins_cost(MEMORY_REF_COST); 5945 format %{ "STX $src,$mem\t! long" %} 5946 opcode(Assembler::stx_op3); 5947 ins_encode(simple_form3_mem_reg( mem, src ) ); 5948 ins_pipe(istore_mem_reg); 5949 %} 5950 5951 instruct storeI0(memory mem, immI0 src) %{ 5952 match(Set mem (StoreI mem src)); 5953 ins_cost(MEMORY_REF_COST); 5954 5955 format %{ "STW $src,$mem" %} 5956 opcode(Assembler::stw_op3); 5957 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5958 ins_pipe(istore_mem_zero); 5959 %} 5960 5961 instruct storeL0(memory mem, immL0 src) %{ 5962 match(Set mem (StoreL mem src)); 5963 ins_cost(MEMORY_REF_COST); 5964 5965 format %{ "STX $src,$mem" %} 5966 opcode(Assembler::stx_op3); 5967 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5968 ins_pipe(istore_mem_zero); 5969 %} 5970 5971 // Store Integer from float register (used after fstoi) 5972 instruct storeI_Freg(memory mem, regF src) %{ 5973 match(Set mem (StoreI mem src)); 5974 ins_cost(MEMORY_REF_COST); 5975 5976 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 5977 opcode(Assembler::stf_op3); 5978 ins_encode(simple_form3_mem_reg( mem, src ) ); 5979 ins_pipe(fstoreF_mem_reg); 5980 %} 5981 5982 // Store Pointer 5983 instruct storeP(memory dst, sp_ptr_RegP src) %{ 5984 match(Set dst (StoreP dst src)); 5985 ins_cost(MEMORY_REF_COST); 5986 5987 format %{ "STX $src,$dst\t! ptr" %} 5988 opcode(Assembler::stx_op3, 0, REGP_OP); 5989 ins_encode( form3_mem_reg( dst, src ) ); 5990 ins_pipe(istore_mem_spORreg); 5991 %} 5992 5993 instruct storeP0(memory dst, immP0 src) %{ 5994 match(Set dst (StoreP dst src)); 5995 ins_cost(MEMORY_REF_COST); 5996 5997 format %{ "STX $src,$dst\t! ptr" %} 5998 opcode(Assembler::stx_op3, 0, REGP_OP); 5999 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6000 ins_pipe(istore_mem_zero); 6001 %} 6002 6003 // Store Compressed Pointer 6004 instruct storeN(memory dst, iRegN src) %{ 6005 match(Set dst (StoreN dst src)); 6006 ins_cost(MEMORY_REF_COST); 6007 size(4); 6008 6009 format %{ "STW $src,$dst\t! compressed ptr" %} 6010 ins_encode %{ 6011 Register base = as_Register($dst$$base); 6012 Register index = as_Register($dst$$index); 6013 Register src = $src$$Register; 6014 if (index != G0) { 6015 __ stw(src, base, index); 6016 } else { 6017 __ stw(src, base, $dst$$disp); 6018 } 6019 %} 6020 ins_pipe(istore_mem_spORreg); 6021 %} 6022 6023 instruct storeNKlass(memory dst, iRegN src) %{ 6024 match(Set dst (StoreNKlass dst src)); 6025 ins_cost(MEMORY_REF_COST); 6026 size(4); 6027 6028 format %{ "STW $src,$dst\t! compressed klass ptr" %} 6029 ins_encode %{ 6030 Register base = as_Register($dst$$base); 6031 Register index = as_Register($dst$$index); 6032 Register src = $src$$Register; 6033 if (index != G0) { 6034 __ stw(src, base, index); 6035 } else { 6036 __ stw(src, base, $dst$$disp); 6037 } 6038 %} 6039 ins_pipe(istore_mem_spORreg); 6040 %} 6041 6042 instruct storeN0(memory dst, immN0 src) %{ 6043 match(Set dst (StoreN dst src)); 6044 ins_cost(MEMORY_REF_COST); 6045 size(4); 6046 6047 format %{ "STW $src,$dst\t! compressed ptr" %} 6048 ins_encode %{ 6049 Register base = as_Register($dst$$base); 6050 Register index = as_Register($dst$$index); 6051 if (index != G0) { 6052 __ stw(0, base, index); 6053 } else { 6054 __ stw(0, base, $dst$$disp); 6055 } 6056 %} 6057 ins_pipe(istore_mem_zero); 6058 %} 6059 6060 // Store Double 6061 instruct storeD( memory mem, regD src) %{ 6062 match(Set mem (StoreD mem src)); 6063 ins_cost(MEMORY_REF_COST); 6064 6065 format %{ "STDF $src,$mem" %} 6066 opcode(Assembler::stdf_op3); 6067 ins_encode(simple_form3_mem_reg( mem, src ) ); 6068 ins_pipe(fstoreD_mem_reg); 6069 %} 6070 6071 instruct storeD0( memory mem, immD0 src) %{ 6072 match(Set mem (StoreD mem src)); 6073 ins_cost(MEMORY_REF_COST); 6074 6075 format %{ "STX $src,$mem" %} 6076 opcode(Assembler::stx_op3); 6077 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6078 ins_pipe(fstoreD_mem_zero); 6079 %} 6080 6081 // Store Float 6082 instruct storeF( memory mem, regF src) %{ 6083 match(Set mem (StoreF mem src)); 6084 ins_cost(MEMORY_REF_COST); 6085 6086 format %{ "STF $src,$mem" %} 6087 opcode(Assembler::stf_op3); 6088 ins_encode(simple_form3_mem_reg( mem, src ) ); 6089 ins_pipe(fstoreF_mem_reg); 6090 %} 6091 6092 instruct storeF0( memory mem, immF0 src) %{ 6093 match(Set mem (StoreF mem src)); 6094 ins_cost(MEMORY_REF_COST); 6095 6096 format %{ "STW $src,$mem\t! storeF0" %} 6097 opcode(Assembler::stw_op3); 6098 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6099 ins_pipe(fstoreF_mem_zero); 6100 %} 6101 6102 // Convert oop pointer into compressed form 6103 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6104 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6105 match(Set dst (EncodeP src)); 6106 format %{ "encode_heap_oop $src, $dst" %} 6107 ins_encode %{ 6108 __ encode_heap_oop($src$$Register, $dst$$Register); 6109 %} 6110 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); 6111 ins_pipe(ialu_reg); 6112 %} 6113 6114 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6115 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6116 match(Set dst (EncodeP src)); 6117 format %{ "encode_heap_oop_not_null $src, $dst" %} 6118 ins_encode %{ 6119 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6120 %} 6121 ins_pipe(ialu_reg); 6122 %} 6123 6124 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6125 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6126 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6127 match(Set dst (DecodeN src)); 6128 format %{ "decode_heap_oop $src, $dst" %} 6129 ins_encode %{ 6130 __ decode_heap_oop($src$$Register, $dst$$Register); 6131 %} 6132 ins_pipe(ialu_reg); 6133 %} 6134 6135 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6136 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6137 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6138 match(Set dst (DecodeN src)); 6139 format %{ "decode_heap_oop_not_null $src, $dst" %} 6140 ins_encode %{ 6141 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6142 %} 6143 ins_pipe(ialu_reg); 6144 %} 6145 6146 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ 6147 match(Set dst (EncodePKlass src)); 6148 format %{ "encode_klass_not_null $src, $dst" %} 6149 ins_encode %{ 6150 __ encode_klass_not_null($src$$Register, $dst$$Register); 6151 %} 6152 ins_pipe(ialu_reg); 6153 %} 6154 6155 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ 6156 match(Set dst (DecodeNKlass src)); 6157 format %{ "decode_klass_not_null $src, $dst" %} 6158 ins_encode %{ 6159 __ decode_klass_not_null($src$$Register, $dst$$Register); 6160 %} 6161 ins_pipe(ialu_reg); 6162 %} 6163 6164 //----------MemBar Instructions----------------------------------------------- 6165 // Memory barrier flavors 6166 6167 instruct membar_acquire() %{ 6168 match(MemBarAcquire); 6169 match(LoadFence); 6170 ins_cost(4*MEMORY_REF_COST); 6171 6172 size(0); 6173 format %{ "MEMBAR-acquire" %} 6174 ins_encode( enc_membar_acquire ); 6175 ins_pipe(long_memory_op); 6176 %} 6177 6178 instruct membar_acquire_lock() %{ 6179 match(MemBarAcquireLock); 6180 ins_cost(0); 6181 6182 size(0); 6183 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6184 ins_encode( ); 6185 ins_pipe(empty); 6186 %} 6187 6188 instruct membar_release() %{ 6189 match(MemBarRelease); 6190 match(StoreFence); 6191 ins_cost(4*MEMORY_REF_COST); 6192 6193 size(0); 6194 format %{ "MEMBAR-release" %} 6195 ins_encode( enc_membar_release ); 6196 ins_pipe(long_memory_op); 6197 %} 6198 6199 instruct membar_release_lock() %{ 6200 match(MemBarReleaseLock); 6201 ins_cost(0); 6202 6203 size(0); 6204 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6205 ins_encode( ); 6206 ins_pipe(empty); 6207 %} 6208 6209 instruct membar_volatile() %{ 6210 match(MemBarVolatile); 6211 ins_cost(4*MEMORY_REF_COST); 6212 6213 size(4); 6214 format %{ "MEMBAR-volatile" %} 6215 ins_encode( enc_membar_volatile ); 6216 ins_pipe(long_memory_op); 6217 %} 6218 6219 instruct unnecessary_membar_volatile() %{ 6220 match(MemBarVolatile); 6221 predicate(Matcher::post_store_load_barrier(n)); 6222 ins_cost(0); 6223 6224 size(0); 6225 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6226 ins_encode( ); 6227 ins_pipe(empty); 6228 %} 6229 6230 instruct membar_storestore() %{ 6231 match(MemBarStoreStore); 6232 ins_cost(0); 6233 6234 size(0); 6235 format %{ "!MEMBAR-storestore (empty encoding)" %} 6236 ins_encode( ); 6237 ins_pipe(empty); 6238 %} 6239 6240 //----------Register Move Instructions----------------------------------------- 6241 instruct roundDouble_nop(regD dst) %{ 6242 match(Set dst (RoundDouble dst)); 6243 ins_cost(0); 6244 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6245 ins_encode( ); 6246 ins_pipe(empty); 6247 %} 6248 6249 6250 instruct roundFloat_nop(regF dst) %{ 6251 match(Set dst (RoundFloat dst)); 6252 ins_cost(0); 6253 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6254 ins_encode( ); 6255 ins_pipe(empty); 6256 %} 6257 6258 6259 // Cast Index to Pointer for unsafe natives 6260 instruct castX2P(iRegX src, iRegP dst) %{ 6261 match(Set dst (CastX2P src)); 6262 6263 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6264 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6265 ins_pipe(ialu_reg); 6266 %} 6267 6268 // Cast Pointer to Index for unsafe natives 6269 instruct castP2X(iRegP src, iRegX dst) %{ 6270 match(Set dst (CastP2X src)); 6271 6272 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6273 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6274 ins_pipe(ialu_reg); 6275 %} 6276 6277 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6278 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6279 match(Set stkSlot src); // chain rule 6280 ins_cost(MEMORY_REF_COST); 6281 format %{ "STDF $src,$stkSlot\t!stk" %} 6282 opcode(Assembler::stdf_op3); 6283 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6284 ins_pipe(fstoreD_stk_reg); 6285 %} 6286 6287 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6288 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6289 match(Set dst stkSlot); // chain rule 6290 ins_cost(MEMORY_REF_COST); 6291 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6292 opcode(Assembler::lddf_op3); 6293 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6294 ins_pipe(floadD_stk); 6295 %} 6296 6297 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6298 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6299 match(Set stkSlot src); // chain rule 6300 ins_cost(MEMORY_REF_COST); 6301 format %{ "STF $src,$stkSlot\t!stk" %} 6302 opcode(Assembler::stf_op3); 6303 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6304 ins_pipe(fstoreF_stk_reg); 6305 %} 6306 6307 //----------Conditional Move--------------------------------------------------- 6308 // Conditional move 6309 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6310 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6311 ins_cost(150); 6312 format %{ "MOV$cmp $pcc,$src,$dst" %} 6313 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6314 ins_pipe(ialu_reg); 6315 %} 6316 6317 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6318 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6319 ins_cost(140); 6320 format %{ "MOV$cmp $pcc,$src,$dst" %} 6321 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6322 ins_pipe(ialu_imm); 6323 %} 6324 6325 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6326 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6327 ins_cost(150); 6328 size(4); 6329 format %{ "MOV$cmp $icc,$src,$dst" %} 6330 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6331 ins_pipe(ialu_reg); 6332 %} 6333 6334 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6335 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6336 ins_cost(140); 6337 size(4); 6338 format %{ "MOV$cmp $icc,$src,$dst" %} 6339 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6340 ins_pipe(ialu_imm); 6341 %} 6342 6343 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6344 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6345 ins_cost(150); 6346 size(4); 6347 format %{ "MOV$cmp $icc,$src,$dst" %} 6348 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6349 ins_pipe(ialu_reg); 6350 %} 6351 6352 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6353 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6354 ins_cost(140); 6355 size(4); 6356 format %{ "MOV$cmp $icc,$src,$dst" %} 6357 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6358 ins_pipe(ialu_imm); 6359 %} 6360 6361 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6362 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6363 ins_cost(150); 6364 size(4); 6365 format %{ "MOV$cmp $fcc,$src,$dst" %} 6366 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6367 ins_pipe(ialu_reg); 6368 %} 6369 6370 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6371 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6372 ins_cost(140); 6373 size(4); 6374 format %{ "MOV$cmp $fcc,$src,$dst" %} 6375 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6376 ins_pipe(ialu_imm); 6377 %} 6378 6379 // Conditional move for RegN. Only cmov(reg,reg). 6380 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6381 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6382 ins_cost(150); 6383 format %{ "MOV$cmp $pcc,$src,$dst" %} 6384 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6385 ins_pipe(ialu_reg); 6386 %} 6387 6388 // This instruction also works with CmpN so we don't need cmovNN_reg. 6389 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6390 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6391 ins_cost(150); 6392 size(4); 6393 format %{ "MOV$cmp $icc,$src,$dst" %} 6394 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6395 ins_pipe(ialu_reg); 6396 %} 6397 6398 // This instruction also works with CmpN so we don't need cmovNN_reg. 6399 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6400 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6401 ins_cost(150); 6402 size(4); 6403 format %{ "MOV$cmp $icc,$src,$dst" %} 6404 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6405 ins_pipe(ialu_reg); 6406 %} 6407 6408 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6409 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6410 ins_cost(150); 6411 size(4); 6412 format %{ "MOV$cmp $fcc,$src,$dst" %} 6413 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6414 ins_pipe(ialu_reg); 6415 %} 6416 6417 // Conditional move 6418 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6419 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6420 ins_cost(150); 6421 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6422 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6423 ins_pipe(ialu_reg); 6424 %} 6425 6426 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6427 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6428 ins_cost(140); 6429 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6430 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6431 ins_pipe(ialu_imm); 6432 %} 6433 6434 // This instruction also works with CmpN so we don't need cmovPN_reg. 6435 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6436 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6437 ins_cost(150); 6438 6439 size(4); 6440 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6441 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6442 ins_pipe(ialu_reg); 6443 %} 6444 6445 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6446 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6447 ins_cost(150); 6448 6449 size(4); 6450 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6451 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6452 ins_pipe(ialu_reg); 6453 %} 6454 6455 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6456 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6457 ins_cost(140); 6458 6459 size(4); 6460 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6461 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6462 ins_pipe(ialu_imm); 6463 %} 6464 6465 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6466 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6467 ins_cost(140); 6468 6469 size(4); 6470 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6471 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6472 ins_pipe(ialu_imm); 6473 %} 6474 6475 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6476 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6477 ins_cost(150); 6478 size(4); 6479 format %{ "MOV$cmp $fcc,$src,$dst" %} 6480 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6481 ins_pipe(ialu_imm); 6482 %} 6483 6484 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6485 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6486 ins_cost(140); 6487 size(4); 6488 format %{ "MOV$cmp $fcc,$src,$dst" %} 6489 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6490 ins_pipe(ialu_imm); 6491 %} 6492 6493 // Conditional move 6494 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6495 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6496 ins_cost(150); 6497 opcode(0x101); 6498 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6499 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6500 ins_pipe(int_conditional_float_move); 6501 %} 6502 6503 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6504 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6505 ins_cost(150); 6506 6507 size(4); 6508 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6509 opcode(0x101); 6510 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6511 ins_pipe(int_conditional_float_move); 6512 %} 6513 6514 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6515 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6516 ins_cost(150); 6517 6518 size(4); 6519 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6520 opcode(0x101); 6521 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6522 ins_pipe(int_conditional_float_move); 6523 %} 6524 6525 // Conditional move, 6526 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6527 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6528 ins_cost(150); 6529 size(4); 6530 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6531 opcode(0x1); 6532 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6533 ins_pipe(int_conditional_double_move); 6534 %} 6535 6536 // Conditional move 6537 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6538 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6539 ins_cost(150); 6540 size(4); 6541 opcode(0x102); 6542 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6543 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6544 ins_pipe(int_conditional_double_move); 6545 %} 6546 6547 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6548 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6549 ins_cost(150); 6550 6551 size(4); 6552 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6553 opcode(0x102); 6554 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6555 ins_pipe(int_conditional_double_move); 6556 %} 6557 6558 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 6559 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6560 ins_cost(150); 6561 6562 size(4); 6563 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6564 opcode(0x102); 6565 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6566 ins_pipe(int_conditional_double_move); 6567 %} 6568 6569 // Conditional move, 6570 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6571 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6572 ins_cost(150); 6573 size(4); 6574 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6575 opcode(0x2); 6576 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6577 ins_pipe(int_conditional_double_move); 6578 %} 6579 6580 // Conditional move 6581 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6582 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6583 ins_cost(150); 6584 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6585 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6586 ins_pipe(ialu_reg); 6587 %} 6588 6589 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6590 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6591 ins_cost(140); 6592 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6593 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6594 ins_pipe(ialu_imm); 6595 %} 6596 6597 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6598 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6599 ins_cost(150); 6600 6601 size(4); 6602 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6603 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6604 ins_pipe(ialu_reg); 6605 %} 6606 6607 6608 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 6609 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6610 ins_cost(150); 6611 6612 size(4); 6613 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6614 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6615 ins_pipe(ialu_reg); 6616 %} 6617 6618 6619 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6620 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6621 ins_cost(150); 6622 6623 size(4); 6624 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6625 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6626 ins_pipe(ialu_reg); 6627 %} 6628 6629 6630 6631 //----------OS and Locking Instructions---------------------------------------- 6632 6633 // This name is KNOWN by the ADLC and cannot be changed. 6634 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6635 // for this guy. 6636 instruct tlsLoadP(g2RegP dst) %{ 6637 match(Set dst (ThreadLocal)); 6638 6639 size(0); 6640 ins_cost(0); 6641 format %{ "# TLS is in G2" %} 6642 ins_encode( /*empty encoding*/ ); 6643 ins_pipe(ialu_none); 6644 %} 6645 6646 instruct checkCastPP( iRegP dst ) %{ 6647 match(Set dst (CheckCastPP dst)); 6648 6649 size(0); 6650 format %{ "# checkcastPP of $dst" %} 6651 ins_encode( /*empty encoding*/ ); 6652 ins_pipe(empty); 6653 %} 6654 6655 6656 instruct castPP( iRegP dst ) %{ 6657 match(Set dst (CastPP dst)); 6658 format %{ "# castPP of $dst" %} 6659 ins_encode( /*empty encoding*/ ); 6660 ins_pipe(empty); 6661 %} 6662 6663 instruct castII( iRegI dst ) %{ 6664 match(Set dst (CastII dst)); 6665 format %{ "# castII of $dst" %} 6666 ins_encode( /*empty encoding*/ ); 6667 ins_cost(0); 6668 ins_pipe(empty); 6669 %} 6670 6671 //----------Arithmetic Instructions-------------------------------------------- 6672 // Addition Instructions 6673 // Register Addition 6674 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6675 match(Set dst (AddI src1 src2)); 6676 6677 size(4); 6678 format %{ "ADD $src1,$src2,$dst" %} 6679 ins_encode %{ 6680 __ add($src1$$Register, $src2$$Register, $dst$$Register); 6681 %} 6682 ins_pipe(ialu_reg_reg); 6683 %} 6684 6685 // Immediate Addition 6686 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6687 match(Set dst (AddI src1 src2)); 6688 6689 size(4); 6690 format %{ "ADD $src1,$src2,$dst" %} 6691 opcode(Assembler::add_op3, Assembler::arith_op); 6692 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6693 ins_pipe(ialu_reg_imm); 6694 %} 6695 6696 // Pointer Register Addition 6697 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 6698 match(Set dst (AddP src1 src2)); 6699 6700 size(4); 6701 format %{ "ADD $src1,$src2,$dst" %} 6702 opcode(Assembler::add_op3, Assembler::arith_op); 6703 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6704 ins_pipe(ialu_reg_reg); 6705 %} 6706 6707 // Pointer Immediate Addition 6708 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 6709 match(Set dst (AddP src1 src2)); 6710 6711 size(4); 6712 format %{ "ADD $src1,$src2,$dst" %} 6713 opcode(Assembler::add_op3, Assembler::arith_op); 6714 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6715 ins_pipe(ialu_reg_imm); 6716 %} 6717 6718 // Long Addition 6719 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6720 match(Set dst (AddL src1 src2)); 6721 6722 size(4); 6723 format %{ "ADD $src1,$src2,$dst\t! long" %} 6724 opcode(Assembler::add_op3, Assembler::arith_op); 6725 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6726 ins_pipe(ialu_reg_reg); 6727 %} 6728 6729 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6730 match(Set dst (AddL src1 con)); 6731 6732 size(4); 6733 format %{ "ADD $src1,$con,$dst" %} 6734 opcode(Assembler::add_op3, Assembler::arith_op); 6735 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6736 ins_pipe(ialu_reg_imm); 6737 %} 6738 6739 //----------Conditional_store-------------------------------------------------- 6740 // Conditional-store of the updated heap-top. 6741 // Used during allocation of the shared heap. 6742 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 6743 6744 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 6745 instruct loadPLocked(iRegP dst, memory mem) %{ 6746 match(Set dst (LoadPLocked mem)); 6747 ins_cost(MEMORY_REF_COST); 6748 6749 format %{ "LDX $mem,$dst\t! ptr" %} 6750 opcode(Assembler::ldx_op3, 0, REGP_OP); 6751 ins_encode( form3_mem_reg( mem, dst ) ); 6752 ins_pipe(iload_mem); 6753 %} 6754 6755 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 6756 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 6757 effect( KILL newval ); 6758 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 6759 "CMP R_G3,$oldval\t\t! See if we made progress" %} 6760 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 6761 ins_pipe( long_memory_op ); 6762 %} 6763 6764 // Conditional-store of an int value. 6765 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 6766 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 6767 effect( KILL newval ); 6768 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6769 "CMP $oldval,$newval\t\t! See if we made progress" %} 6770 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6771 ins_pipe( long_memory_op ); 6772 %} 6773 6774 // Conditional-store of a long value. 6775 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 6776 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 6777 effect( KILL newval ); 6778 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6779 "CMP $oldval,$newval\t\t! See if we made progress" %} 6780 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6781 ins_pipe( long_memory_op ); 6782 %} 6783 6784 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 6785 6786 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6787 predicate(VM_Version::supports_cx8()); 6788 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 6789 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval))); 6790 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6791 format %{ 6792 "MOV $newval,O7\n\t" 6793 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6794 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6795 "MOV 1,$res\n\t" 6796 "MOVne xcc,R_G0,$res" 6797 %} 6798 ins_encode( enc_casx(mem_ptr, oldval, newval), 6799 enc_lflags_ne_to_boolean(res) ); 6800 ins_pipe( long_memory_op ); 6801 %} 6802 6803 6804 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6805 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 6806 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval))); 6807 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6808 format %{ 6809 "MOV $newval,O7\n\t" 6810 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6811 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6812 "MOV 1,$res\n\t" 6813 "MOVne icc,R_G0,$res" 6814 %} 6815 ins_encode( enc_casi(mem_ptr, oldval, newval), 6816 enc_iflags_ne_to_boolean(res) ); 6817 ins_pipe( long_memory_op ); 6818 %} 6819 6820 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6821 predicate(VM_Version::supports_cx8()); 6822 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 6823 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); 6824 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6825 format %{ 6826 "MOV $newval,O7\n\t" 6827 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6828 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6829 "MOV 1,$res\n\t" 6830 "MOVne xcc,R_G0,$res" 6831 %} 6832 ins_encode( enc_casx(mem_ptr, oldval, newval), 6833 enc_lflags_ne_to_boolean(res) ); 6834 ins_pipe( long_memory_op ); 6835 %} 6836 6837 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6838 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 6839 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval))); 6840 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6841 format %{ 6842 "MOV $newval,O7\n\t" 6843 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6844 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6845 "MOV 1,$res\n\t" 6846 "MOVne icc,R_G0,$res" 6847 %} 6848 ins_encode( enc_casi(mem_ptr, oldval, newval), 6849 enc_iflags_ne_to_boolean(res) ); 6850 ins_pipe( long_memory_op ); 6851 %} 6852 6853 instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval) 6854 %{ 6855 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval))); 6856 effect( USE mem_ptr ); 6857 6858 format %{ 6859 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6860 %} 6861 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 6862 ins_pipe( long_memory_op ); 6863 %} 6864 6865 instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval) 6866 %{ 6867 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval))); 6868 effect( USE mem_ptr ); 6869 6870 format %{ 6871 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6872 %} 6873 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 6874 ins_pipe( long_memory_op ); 6875 %} 6876 6877 instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval) 6878 %{ 6879 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval))); 6880 effect( USE mem_ptr ); 6881 6882 format %{ 6883 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6884 %} 6885 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 6886 ins_pipe( long_memory_op ); 6887 %} 6888 6889 instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval) 6890 %{ 6891 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval))); 6892 effect( USE mem_ptr ); 6893 6894 format %{ 6895 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6896 %} 6897 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 6898 ins_pipe( long_memory_op ); 6899 %} 6900 6901 instruct xchgI( memory mem, iRegI newval) %{ 6902 match(Set newval (GetAndSetI mem newval)); 6903 format %{ "SWAP [$mem],$newval" %} 6904 size(4); 6905 ins_encode %{ 6906 __ swap($mem$$Address, $newval$$Register); 6907 %} 6908 ins_pipe( long_memory_op ); 6909 %} 6910 6911 6912 instruct xchgN( memory mem, iRegN newval) %{ 6913 match(Set newval (GetAndSetN mem newval)); 6914 format %{ "SWAP [$mem],$newval" %} 6915 size(4); 6916 ins_encode %{ 6917 __ swap($mem$$Address, $newval$$Register); 6918 %} 6919 ins_pipe( long_memory_op ); 6920 %} 6921 6922 //--------------------- 6923 // Subtraction Instructions 6924 // Register Subtraction 6925 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6926 match(Set dst (SubI src1 src2)); 6927 6928 size(4); 6929 format %{ "SUB $src1,$src2,$dst" %} 6930 opcode(Assembler::sub_op3, Assembler::arith_op); 6931 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6932 ins_pipe(ialu_reg_reg); 6933 %} 6934 6935 // Immediate Subtraction 6936 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6937 match(Set dst (SubI src1 src2)); 6938 6939 size(4); 6940 format %{ "SUB $src1,$src2,$dst" %} 6941 opcode(Assembler::sub_op3, Assembler::arith_op); 6942 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6943 ins_pipe(ialu_reg_imm); 6944 %} 6945 6946 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 6947 match(Set dst (SubI zero src2)); 6948 6949 size(4); 6950 format %{ "NEG $src2,$dst" %} 6951 opcode(Assembler::sub_op3, Assembler::arith_op); 6952 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 6953 ins_pipe(ialu_zero_reg); 6954 %} 6955 6956 // Long subtraction 6957 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6958 match(Set dst (SubL src1 src2)); 6959 6960 size(4); 6961 format %{ "SUB $src1,$src2,$dst\t! long" %} 6962 opcode(Assembler::sub_op3, Assembler::arith_op); 6963 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6964 ins_pipe(ialu_reg_reg); 6965 %} 6966 6967 // Immediate Subtraction 6968 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6969 match(Set dst (SubL src1 con)); 6970 6971 size(4); 6972 format %{ "SUB $src1,$con,$dst\t! long" %} 6973 opcode(Assembler::sub_op3, Assembler::arith_op); 6974 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6975 ins_pipe(ialu_reg_imm); 6976 %} 6977 6978 // Long negation 6979 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 6980 match(Set dst (SubL zero src2)); 6981 6982 size(4); 6983 format %{ "NEG $src2,$dst\t! long" %} 6984 opcode(Assembler::sub_op3, Assembler::arith_op); 6985 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 6986 ins_pipe(ialu_zero_reg); 6987 %} 6988 6989 // Multiplication Instructions 6990 // Integer Multiplication 6991 // Register Multiplication 6992 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6993 match(Set dst (MulI src1 src2)); 6994 6995 size(4); 6996 format %{ "MULX $src1,$src2,$dst" %} 6997 opcode(Assembler::mulx_op3, Assembler::arith_op); 6998 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6999 ins_pipe(imul_reg_reg); 7000 %} 7001 7002 // Immediate Multiplication 7003 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7004 match(Set dst (MulI src1 src2)); 7005 7006 size(4); 7007 format %{ "MULX $src1,$src2,$dst" %} 7008 opcode(Assembler::mulx_op3, Assembler::arith_op); 7009 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7010 ins_pipe(imul_reg_imm); 7011 %} 7012 7013 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7014 match(Set dst (MulL src1 src2)); 7015 ins_cost(DEFAULT_COST * 5); 7016 size(4); 7017 format %{ "MULX $src1,$src2,$dst\t! long" %} 7018 opcode(Assembler::mulx_op3, Assembler::arith_op); 7019 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7020 ins_pipe(mulL_reg_reg); 7021 %} 7022 7023 // Immediate Multiplication 7024 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7025 match(Set dst (MulL src1 src2)); 7026 ins_cost(DEFAULT_COST * 5); 7027 size(4); 7028 format %{ "MULX $src1,$src2,$dst" %} 7029 opcode(Assembler::mulx_op3, Assembler::arith_op); 7030 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7031 ins_pipe(mulL_reg_imm); 7032 %} 7033 7034 // Integer Division 7035 // Register Division 7036 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7037 match(Set dst (DivI src1 src2)); 7038 ins_cost((2+71)*DEFAULT_COST); 7039 7040 format %{ "SRA $src2,0,$src2\n\t" 7041 "SRA $src1,0,$src1\n\t" 7042 "SDIVX $src1,$src2,$dst" %} 7043 ins_encode( idiv_reg( src1, src2, dst ) ); 7044 ins_pipe(sdiv_reg_reg); 7045 %} 7046 7047 // Immediate Division 7048 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7049 match(Set dst (DivI src1 src2)); 7050 ins_cost((2+71)*DEFAULT_COST); 7051 7052 format %{ "SRA $src1,0,$src1\n\t" 7053 "SDIVX $src1,$src2,$dst" %} 7054 ins_encode( idiv_imm( src1, src2, dst ) ); 7055 ins_pipe(sdiv_reg_imm); 7056 %} 7057 7058 //----------Div-By-10-Expansion------------------------------------------------ 7059 // Extract hi bits of a 32x32->64 bit multiply. 7060 // Expand rule only, not matched 7061 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7062 effect( DEF dst, USE src1, USE src2 ); 7063 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7064 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7065 ins_encode( enc_mul_hi(dst,src1,src2)); 7066 ins_pipe(sdiv_reg_reg); 7067 %} 7068 7069 // Magic constant, reciprocal of 10 7070 instruct loadConI_x66666667(iRegIsafe dst) %{ 7071 effect( DEF dst ); 7072 7073 size(8); 7074 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7075 ins_encode( Set32(0x66666667, dst) ); 7076 ins_pipe(ialu_hi_lo_reg); 7077 %} 7078 7079 // Register Shift Right Arithmetic Long by 32-63 7080 instruct sra_31( iRegI dst, iRegI src ) %{ 7081 effect( DEF dst, USE src ); 7082 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7083 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7084 ins_pipe(ialu_reg_reg); 7085 %} 7086 7087 // Arithmetic Shift Right by 8-bit immediate 7088 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7089 effect( DEF dst, USE src ); 7090 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7091 opcode(Assembler::sra_op3, Assembler::arith_op); 7092 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7093 ins_pipe(ialu_reg_imm); 7094 %} 7095 7096 // Integer DIV with 10 7097 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7098 match(Set dst (DivI src div)); 7099 ins_cost((6+6)*DEFAULT_COST); 7100 expand %{ 7101 iRegIsafe tmp1; // Killed temps; 7102 iRegIsafe tmp2; // Killed temps; 7103 iRegI tmp3; // Killed temps; 7104 iRegI tmp4; // Killed temps; 7105 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7106 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7107 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7108 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7109 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7110 %} 7111 %} 7112 7113 // Register Long Division 7114 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7115 match(Set dst (DivL src1 src2)); 7116 ins_cost(DEFAULT_COST*71); 7117 size(4); 7118 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7119 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7120 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7121 ins_pipe(divL_reg_reg); 7122 %} 7123 7124 // Register Long Division 7125 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7126 match(Set dst (DivL src1 src2)); 7127 ins_cost(DEFAULT_COST*71); 7128 size(4); 7129 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7130 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7131 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7132 ins_pipe(divL_reg_imm); 7133 %} 7134 7135 // Integer Remainder 7136 // Register Remainder 7137 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7138 match(Set dst (ModI src1 src2)); 7139 effect( KILL ccr, KILL temp); 7140 7141 format %{ "SREM $src1,$src2,$dst" %} 7142 ins_encode( irem_reg(src1, src2, dst, temp) ); 7143 ins_pipe(sdiv_reg_reg); 7144 %} 7145 7146 // Immediate Remainder 7147 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7148 match(Set dst (ModI src1 src2)); 7149 effect( KILL ccr, KILL temp); 7150 7151 format %{ "SREM $src1,$src2,$dst" %} 7152 ins_encode( irem_imm(src1, src2, dst, temp) ); 7153 ins_pipe(sdiv_reg_imm); 7154 %} 7155 7156 // Register Long Remainder 7157 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7158 effect(DEF dst, USE src1, USE src2); 7159 size(4); 7160 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7161 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7162 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7163 ins_pipe(divL_reg_reg); 7164 %} 7165 7166 // Register Long Division 7167 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7168 effect(DEF dst, USE src1, USE src2); 7169 size(4); 7170 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7171 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7172 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7173 ins_pipe(divL_reg_imm); 7174 %} 7175 7176 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7177 effect(DEF dst, USE src1, USE src2); 7178 size(4); 7179 format %{ "MULX $src1,$src2,$dst\t! long" %} 7180 opcode(Assembler::mulx_op3, Assembler::arith_op); 7181 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7182 ins_pipe(mulL_reg_reg); 7183 %} 7184 7185 // Immediate Multiplication 7186 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7187 effect(DEF dst, USE src1, USE src2); 7188 size(4); 7189 format %{ "MULX $src1,$src2,$dst" %} 7190 opcode(Assembler::mulx_op3, Assembler::arith_op); 7191 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7192 ins_pipe(mulL_reg_imm); 7193 %} 7194 7195 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7196 effect(DEF dst, USE src1, USE src2); 7197 size(4); 7198 format %{ "SUB $src1,$src2,$dst\t! long" %} 7199 opcode(Assembler::sub_op3, Assembler::arith_op); 7200 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7201 ins_pipe(ialu_reg_reg); 7202 %} 7203 7204 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7205 effect(DEF dst, USE src1, USE src2); 7206 size(4); 7207 format %{ "SUB $src1,$src2,$dst\t! long" %} 7208 opcode(Assembler::sub_op3, Assembler::arith_op); 7209 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7210 ins_pipe(ialu_reg_reg); 7211 %} 7212 7213 // Register Long Remainder 7214 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7215 match(Set dst (ModL src1 src2)); 7216 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7217 expand %{ 7218 iRegL tmp1; 7219 iRegL tmp2; 7220 divL_reg_reg_1(tmp1, src1, src2); 7221 mulL_reg_reg_1(tmp2, tmp1, src2); 7222 subL_reg_reg_1(dst, src1, tmp2); 7223 %} 7224 %} 7225 7226 // Register Long Remainder 7227 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7228 match(Set dst (ModL src1 src2)); 7229 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7230 expand %{ 7231 iRegL tmp1; 7232 iRegL tmp2; 7233 divL_reg_imm13_1(tmp1, src1, src2); 7234 mulL_reg_imm13_1(tmp2, tmp1, src2); 7235 subL_reg_reg_2 (dst, src1, tmp2); 7236 %} 7237 %} 7238 7239 // Integer Shift Instructions 7240 // Register Shift Left 7241 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7242 match(Set dst (LShiftI src1 src2)); 7243 7244 size(4); 7245 format %{ "SLL $src1,$src2,$dst" %} 7246 opcode(Assembler::sll_op3, Assembler::arith_op); 7247 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7248 ins_pipe(ialu_reg_reg); 7249 %} 7250 7251 // Register Shift Left Immediate 7252 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7253 match(Set dst (LShiftI src1 src2)); 7254 7255 size(4); 7256 format %{ "SLL $src1,$src2,$dst" %} 7257 opcode(Assembler::sll_op3, Assembler::arith_op); 7258 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7259 ins_pipe(ialu_reg_imm); 7260 %} 7261 7262 // Register Shift Left 7263 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7264 match(Set dst (LShiftL src1 src2)); 7265 7266 size(4); 7267 format %{ "SLLX $src1,$src2,$dst" %} 7268 opcode(Assembler::sllx_op3, Assembler::arith_op); 7269 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7270 ins_pipe(ialu_reg_reg); 7271 %} 7272 7273 // Register Shift Left Immediate 7274 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7275 match(Set dst (LShiftL src1 src2)); 7276 7277 size(4); 7278 format %{ "SLLX $src1,$src2,$dst" %} 7279 opcode(Assembler::sllx_op3, Assembler::arith_op); 7280 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7281 ins_pipe(ialu_reg_imm); 7282 %} 7283 7284 // Register Arithmetic Shift Right 7285 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7286 match(Set dst (RShiftI src1 src2)); 7287 size(4); 7288 format %{ "SRA $src1,$src2,$dst" %} 7289 opcode(Assembler::sra_op3, Assembler::arith_op); 7290 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7291 ins_pipe(ialu_reg_reg); 7292 %} 7293 7294 // Register Arithmetic Shift Right Immediate 7295 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7296 match(Set dst (RShiftI src1 src2)); 7297 7298 size(4); 7299 format %{ "SRA $src1,$src2,$dst" %} 7300 opcode(Assembler::sra_op3, Assembler::arith_op); 7301 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7302 ins_pipe(ialu_reg_imm); 7303 %} 7304 7305 // Register Shift Right Arithmatic Long 7306 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7307 match(Set dst (RShiftL src1 src2)); 7308 7309 size(4); 7310 format %{ "SRAX $src1,$src2,$dst" %} 7311 opcode(Assembler::srax_op3, Assembler::arith_op); 7312 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7313 ins_pipe(ialu_reg_reg); 7314 %} 7315 7316 // Register Shift Left Immediate 7317 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7318 match(Set dst (RShiftL src1 src2)); 7319 7320 size(4); 7321 format %{ "SRAX $src1,$src2,$dst" %} 7322 opcode(Assembler::srax_op3, Assembler::arith_op); 7323 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7324 ins_pipe(ialu_reg_imm); 7325 %} 7326 7327 // Register Shift Right 7328 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7329 match(Set dst (URShiftI src1 src2)); 7330 7331 size(4); 7332 format %{ "SRL $src1,$src2,$dst" %} 7333 opcode(Assembler::srl_op3, Assembler::arith_op); 7334 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7335 ins_pipe(ialu_reg_reg); 7336 %} 7337 7338 // Register Shift Right Immediate 7339 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7340 match(Set dst (URShiftI src1 src2)); 7341 7342 size(4); 7343 format %{ "SRL $src1,$src2,$dst" %} 7344 opcode(Assembler::srl_op3, Assembler::arith_op); 7345 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7346 ins_pipe(ialu_reg_imm); 7347 %} 7348 7349 // Register Shift Right 7350 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7351 match(Set dst (URShiftL src1 src2)); 7352 7353 size(4); 7354 format %{ "SRLX $src1,$src2,$dst" %} 7355 opcode(Assembler::srlx_op3, Assembler::arith_op); 7356 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7357 ins_pipe(ialu_reg_reg); 7358 %} 7359 7360 // Register Shift Right Immediate 7361 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7362 match(Set dst (URShiftL src1 src2)); 7363 7364 size(4); 7365 format %{ "SRLX $src1,$src2,$dst" %} 7366 opcode(Assembler::srlx_op3, Assembler::arith_op); 7367 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7368 ins_pipe(ialu_reg_imm); 7369 %} 7370 7371 // Register Shift Right Immediate with a CastP2X 7372 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7373 match(Set dst (URShiftL (CastP2X src1) src2)); 7374 size(4); 7375 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7376 opcode(Assembler::srlx_op3, Assembler::arith_op); 7377 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7378 ins_pipe(ialu_reg_imm); 7379 %} 7380 7381 7382 //----------Floating Point Arithmetic Instructions----------------------------- 7383 7384 // Add float single precision 7385 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7386 match(Set dst (AddF src1 src2)); 7387 7388 size(4); 7389 format %{ "FADDS $src1,$src2,$dst" %} 7390 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7391 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7392 ins_pipe(faddF_reg_reg); 7393 %} 7394 7395 // Add float double precision 7396 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7397 match(Set dst (AddD src1 src2)); 7398 7399 size(4); 7400 format %{ "FADDD $src1,$src2,$dst" %} 7401 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7402 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7403 ins_pipe(faddD_reg_reg); 7404 %} 7405 7406 // Sub float single precision 7407 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7408 match(Set dst (SubF src1 src2)); 7409 7410 size(4); 7411 format %{ "FSUBS $src1,$src2,$dst" %} 7412 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7413 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7414 ins_pipe(faddF_reg_reg); 7415 %} 7416 7417 // Sub float double precision 7418 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7419 match(Set dst (SubD src1 src2)); 7420 7421 size(4); 7422 format %{ "FSUBD $src1,$src2,$dst" %} 7423 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7424 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7425 ins_pipe(faddD_reg_reg); 7426 %} 7427 7428 // Mul float single precision 7429 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7430 match(Set dst (MulF src1 src2)); 7431 7432 size(4); 7433 format %{ "FMULS $src1,$src2,$dst" %} 7434 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7435 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7436 ins_pipe(fmulF_reg_reg); 7437 %} 7438 7439 // Mul float double precision 7440 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7441 match(Set dst (MulD src1 src2)); 7442 7443 size(4); 7444 format %{ "FMULD $src1,$src2,$dst" %} 7445 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7446 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7447 ins_pipe(fmulD_reg_reg); 7448 %} 7449 7450 // Div float single precision 7451 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7452 match(Set dst (DivF src1 src2)); 7453 7454 size(4); 7455 format %{ "FDIVS $src1,$src2,$dst" %} 7456 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7457 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7458 ins_pipe(fdivF_reg_reg); 7459 %} 7460 7461 // Div float double precision 7462 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7463 match(Set dst (DivD src1 src2)); 7464 7465 size(4); 7466 format %{ "FDIVD $src1,$src2,$dst" %} 7467 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7468 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7469 ins_pipe(fdivD_reg_reg); 7470 %} 7471 7472 // Absolute float double precision 7473 instruct absD_reg(regD dst, regD src) %{ 7474 match(Set dst (AbsD src)); 7475 7476 format %{ "FABSd $src,$dst" %} 7477 ins_encode(fabsd(dst, src)); 7478 ins_pipe(faddD_reg); 7479 %} 7480 7481 // Absolute float single precision 7482 instruct absF_reg(regF dst, regF src) %{ 7483 match(Set dst (AbsF src)); 7484 7485 format %{ "FABSs $src,$dst" %} 7486 ins_encode(fabss(dst, src)); 7487 ins_pipe(faddF_reg); 7488 %} 7489 7490 instruct negF_reg(regF dst, regF src) %{ 7491 match(Set dst (NegF src)); 7492 7493 size(4); 7494 format %{ "FNEGs $src,$dst" %} 7495 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7496 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7497 ins_pipe(faddF_reg); 7498 %} 7499 7500 instruct negD_reg(regD dst, regD src) %{ 7501 match(Set dst (NegD src)); 7502 7503 format %{ "FNEGd $src,$dst" %} 7504 ins_encode(fnegd(dst, src)); 7505 ins_pipe(faddD_reg); 7506 %} 7507 7508 // Sqrt float double precision 7509 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7510 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7511 7512 size(4); 7513 format %{ "FSQRTS $src,$dst" %} 7514 ins_encode(fsqrts(dst, src)); 7515 ins_pipe(fdivF_reg_reg); 7516 %} 7517 7518 // Sqrt float double precision 7519 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7520 match(Set dst (SqrtD src)); 7521 7522 size(4); 7523 format %{ "FSQRTD $src,$dst" %} 7524 ins_encode(fsqrtd(dst, src)); 7525 ins_pipe(fdivD_reg_reg); 7526 %} 7527 7528 //----------Logical Instructions----------------------------------------------- 7529 // And Instructions 7530 // Register And 7531 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7532 match(Set dst (AndI src1 src2)); 7533 7534 size(4); 7535 format %{ "AND $src1,$src2,$dst" %} 7536 opcode(Assembler::and_op3, Assembler::arith_op); 7537 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7538 ins_pipe(ialu_reg_reg); 7539 %} 7540 7541 // Immediate And 7542 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7543 match(Set dst (AndI src1 src2)); 7544 7545 size(4); 7546 format %{ "AND $src1,$src2,$dst" %} 7547 opcode(Assembler::and_op3, Assembler::arith_op); 7548 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7549 ins_pipe(ialu_reg_imm); 7550 %} 7551 7552 // Register And Long 7553 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7554 match(Set dst (AndL src1 src2)); 7555 7556 ins_cost(DEFAULT_COST); 7557 size(4); 7558 format %{ "AND $src1,$src2,$dst\t! long" %} 7559 opcode(Assembler::and_op3, Assembler::arith_op); 7560 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7561 ins_pipe(ialu_reg_reg); 7562 %} 7563 7564 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7565 match(Set dst (AndL src1 con)); 7566 7567 ins_cost(DEFAULT_COST); 7568 size(4); 7569 format %{ "AND $src1,$con,$dst\t! long" %} 7570 opcode(Assembler::and_op3, Assembler::arith_op); 7571 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7572 ins_pipe(ialu_reg_imm); 7573 %} 7574 7575 // Or Instructions 7576 // Register Or 7577 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7578 match(Set dst (OrI src1 src2)); 7579 7580 size(4); 7581 format %{ "OR $src1,$src2,$dst" %} 7582 opcode(Assembler::or_op3, Assembler::arith_op); 7583 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7584 ins_pipe(ialu_reg_reg); 7585 %} 7586 7587 // Immediate Or 7588 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7589 match(Set dst (OrI src1 src2)); 7590 7591 size(4); 7592 format %{ "OR $src1,$src2,$dst" %} 7593 opcode(Assembler::or_op3, Assembler::arith_op); 7594 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7595 ins_pipe(ialu_reg_imm); 7596 %} 7597 7598 // Register Or Long 7599 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7600 match(Set dst (OrL src1 src2)); 7601 7602 ins_cost(DEFAULT_COST); 7603 size(4); 7604 format %{ "OR $src1,$src2,$dst\t! long" %} 7605 opcode(Assembler::or_op3, Assembler::arith_op); 7606 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7607 ins_pipe(ialu_reg_reg); 7608 %} 7609 7610 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7611 match(Set dst (OrL src1 con)); 7612 ins_cost(DEFAULT_COST*2); 7613 7614 ins_cost(DEFAULT_COST); 7615 size(4); 7616 format %{ "OR $src1,$con,$dst\t! long" %} 7617 opcode(Assembler::or_op3, Assembler::arith_op); 7618 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7619 ins_pipe(ialu_reg_imm); 7620 %} 7621 7622 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7623 match(Set dst (OrL src1 (CastP2X src2))); 7624 7625 ins_cost(DEFAULT_COST); 7626 size(4); 7627 format %{ "OR $src1,$src2,$dst\t! long" %} 7628 opcode(Assembler::or_op3, Assembler::arith_op); 7629 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7630 ins_pipe(ialu_reg_reg); 7631 %} 7632 7633 // Xor Instructions 7634 // Register Xor 7635 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7636 match(Set dst (XorI src1 src2)); 7637 7638 size(4); 7639 format %{ "XOR $src1,$src2,$dst" %} 7640 opcode(Assembler::xor_op3, Assembler::arith_op); 7641 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7642 ins_pipe(ialu_reg_reg); 7643 %} 7644 7645 // Immediate Xor 7646 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7647 match(Set dst (XorI src1 src2)); 7648 7649 size(4); 7650 format %{ "XOR $src1,$src2,$dst" %} 7651 opcode(Assembler::xor_op3, Assembler::arith_op); 7652 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7653 ins_pipe(ialu_reg_imm); 7654 %} 7655 7656 // Register Xor Long 7657 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7658 match(Set dst (XorL src1 src2)); 7659 7660 ins_cost(DEFAULT_COST); 7661 size(4); 7662 format %{ "XOR $src1,$src2,$dst\t! long" %} 7663 opcode(Assembler::xor_op3, Assembler::arith_op); 7664 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7665 ins_pipe(ialu_reg_reg); 7666 %} 7667 7668 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7669 match(Set dst (XorL src1 con)); 7670 7671 ins_cost(DEFAULT_COST); 7672 size(4); 7673 format %{ "XOR $src1,$con,$dst\t! long" %} 7674 opcode(Assembler::xor_op3, Assembler::arith_op); 7675 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7676 ins_pipe(ialu_reg_imm); 7677 %} 7678 7679 //----------Convert to Boolean------------------------------------------------- 7680 // Nice hack for 32-bit tests but doesn't work for 7681 // 64-bit pointers. 7682 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 7683 match(Set dst (Conv2B src)); 7684 effect( KILL ccr ); 7685 ins_cost(DEFAULT_COST*2); 7686 format %{ "CMP R_G0,$src\n\t" 7687 "ADDX R_G0,0,$dst" %} 7688 ins_encode( enc_to_bool( src, dst ) ); 7689 ins_pipe(ialu_reg_ialu); 7690 %} 7691 7692 instruct convP2B( iRegI dst, iRegP src ) %{ 7693 match(Set dst (Conv2B src)); 7694 ins_cost(DEFAULT_COST*2); 7695 format %{ "MOV $src,$dst\n\t" 7696 "MOVRNZ $src,1,$dst" %} 7697 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 7698 ins_pipe(ialu_clr_and_mover); 7699 %} 7700 7701 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 7702 match(Set dst (CmpLTMask src zero)); 7703 effect(KILL ccr); 7704 size(4); 7705 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 7706 ins_encode %{ 7707 __ sra($src$$Register, 31, $dst$$Register); 7708 %} 7709 ins_pipe(ialu_reg_imm); 7710 %} 7711 7712 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 7713 match(Set dst (CmpLTMask p q)); 7714 effect( KILL ccr ); 7715 ins_cost(DEFAULT_COST*4); 7716 format %{ "CMP $p,$q\n\t" 7717 "MOV #0,$dst\n\t" 7718 "BLT,a .+8\n\t" 7719 "MOV #-1,$dst" %} 7720 ins_encode( enc_ltmask(p,q,dst) ); 7721 ins_pipe(ialu_reg_reg_ialu); 7722 %} 7723 7724 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 7725 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 7726 effect(KILL ccr, TEMP tmp); 7727 ins_cost(DEFAULT_COST*3); 7728 7729 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 7730 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 7731 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 7732 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); 7733 ins_pipe(cadd_cmpltmask); 7734 %} 7735 7736 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ 7737 match(Set p (AndI (CmpLTMask p q) y)); 7738 effect(KILL ccr); 7739 ins_cost(DEFAULT_COST*3); 7740 7741 format %{ "CMP $p,$q\n\t" 7742 "MOV $y,$p\n\t" 7743 "MOVge G0,$p" %} 7744 ins_encode %{ 7745 __ cmp($p$$Register, $q$$Register); 7746 __ mov($y$$Register, $p$$Register); 7747 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); 7748 %} 7749 ins_pipe(ialu_reg_reg_ialu); 7750 %} 7751 7752 //----------------------------------------------------------------- 7753 // Direct raw moves between float and general registers using VIS3. 7754 7755 // ins_pipe(faddF_reg); 7756 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 7757 predicate(UseVIS >= 3); 7758 match(Set dst (MoveF2I src)); 7759 7760 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 7761 ins_encode %{ 7762 __ movstouw($src$$FloatRegister, $dst$$Register); 7763 %} 7764 ins_pipe(ialu_reg_reg); 7765 %} 7766 7767 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 7768 predicate(UseVIS >= 3); 7769 match(Set dst (MoveI2F src)); 7770 7771 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 7772 ins_encode %{ 7773 __ movwtos($src$$Register, $dst$$FloatRegister); 7774 %} 7775 ins_pipe(ialu_reg_reg); 7776 %} 7777 7778 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 7779 predicate(UseVIS >= 3); 7780 match(Set dst (MoveD2L src)); 7781 7782 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 7783 ins_encode %{ 7784 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 7785 %} 7786 ins_pipe(ialu_reg_reg); 7787 %} 7788 7789 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 7790 predicate(UseVIS >= 3); 7791 match(Set dst (MoveL2D src)); 7792 7793 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 7794 ins_encode %{ 7795 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 7796 %} 7797 ins_pipe(ialu_reg_reg); 7798 %} 7799 7800 7801 // Raw moves between float and general registers using stack. 7802 7803 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 7804 match(Set dst (MoveF2I src)); 7805 effect(DEF dst, USE src); 7806 ins_cost(MEMORY_REF_COST); 7807 7808 format %{ "LDUW $src,$dst\t! MoveF2I" %} 7809 opcode(Assembler::lduw_op3); 7810 ins_encode(simple_form3_mem_reg( src, dst ) ); 7811 ins_pipe(iload_mem); 7812 %} 7813 7814 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 7815 match(Set dst (MoveI2F src)); 7816 effect(DEF dst, USE src); 7817 ins_cost(MEMORY_REF_COST); 7818 7819 format %{ "LDF $src,$dst\t! MoveI2F" %} 7820 opcode(Assembler::ldf_op3); 7821 ins_encode(simple_form3_mem_reg(src, dst)); 7822 ins_pipe(floadF_stk); 7823 %} 7824 7825 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 7826 match(Set dst (MoveD2L src)); 7827 effect(DEF dst, USE src); 7828 ins_cost(MEMORY_REF_COST); 7829 7830 format %{ "LDX $src,$dst\t! MoveD2L" %} 7831 opcode(Assembler::ldx_op3); 7832 ins_encode(simple_form3_mem_reg( src, dst ) ); 7833 ins_pipe(iload_mem); 7834 %} 7835 7836 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 7837 match(Set dst (MoveL2D src)); 7838 effect(DEF dst, USE src); 7839 ins_cost(MEMORY_REF_COST); 7840 7841 format %{ "LDDF $src,$dst\t! MoveL2D" %} 7842 opcode(Assembler::lddf_op3); 7843 ins_encode(simple_form3_mem_reg(src, dst)); 7844 ins_pipe(floadD_stk); 7845 %} 7846 7847 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 7848 match(Set dst (MoveF2I src)); 7849 effect(DEF dst, USE src); 7850 ins_cost(MEMORY_REF_COST); 7851 7852 format %{ "STF $src,$dst\t! MoveF2I" %} 7853 opcode(Assembler::stf_op3); 7854 ins_encode(simple_form3_mem_reg(dst, src)); 7855 ins_pipe(fstoreF_stk_reg); 7856 %} 7857 7858 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 7859 match(Set dst (MoveI2F src)); 7860 effect(DEF dst, USE src); 7861 ins_cost(MEMORY_REF_COST); 7862 7863 format %{ "STW $src,$dst\t! MoveI2F" %} 7864 opcode(Assembler::stw_op3); 7865 ins_encode(simple_form3_mem_reg( dst, src ) ); 7866 ins_pipe(istore_mem_reg); 7867 %} 7868 7869 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 7870 match(Set dst (MoveD2L src)); 7871 effect(DEF dst, USE src); 7872 ins_cost(MEMORY_REF_COST); 7873 7874 format %{ "STDF $src,$dst\t! MoveD2L" %} 7875 opcode(Assembler::stdf_op3); 7876 ins_encode(simple_form3_mem_reg(dst, src)); 7877 ins_pipe(fstoreD_stk_reg); 7878 %} 7879 7880 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 7881 match(Set dst (MoveL2D src)); 7882 effect(DEF dst, USE src); 7883 ins_cost(MEMORY_REF_COST); 7884 7885 format %{ "STX $src,$dst\t! MoveL2D" %} 7886 opcode(Assembler::stx_op3); 7887 ins_encode(simple_form3_mem_reg( dst, src ) ); 7888 ins_pipe(istore_mem_reg); 7889 %} 7890 7891 7892 //----------Arithmetic Conversion Instructions--------------------------------- 7893 // The conversions operations are all Alpha sorted. Please keep it that way! 7894 7895 instruct convD2F_reg(regF dst, regD src) %{ 7896 match(Set dst (ConvD2F src)); 7897 size(4); 7898 format %{ "FDTOS $src,$dst" %} 7899 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 7900 ins_encode(form3_opf_rs2D_rdF(src, dst)); 7901 ins_pipe(fcvtD2F); 7902 %} 7903 7904 7905 // Convert a double to an int in a float register. 7906 // If the double is a NAN, stuff a zero in instead. 7907 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 7908 effect(DEF dst, USE src, KILL fcc0); 7909 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 7910 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7911 "FDTOI $src,$dst\t! convert in delay slot\n\t" 7912 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 7913 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 7914 "skip:" %} 7915 ins_encode(form_d2i_helper(src,dst)); 7916 ins_pipe(fcvtD2I); 7917 %} 7918 7919 instruct convD2I_stk(stackSlotI dst, regD src) %{ 7920 match(Set dst (ConvD2I src)); 7921 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7922 expand %{ 7923 regF tmp; 7924 convD2I_helper(tmp, src); 7925 regF_to_stkI(dst, tmp); 7926 %} 7927 %} 7928 7929 instruct convD2I_reg(iRegI dst, regD src) %{ 7930 predicate(UseVIS >= 3); 7931 match(Set dst (ConvD2I src)); 7932 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 7933 expand %{ 7934 regF tmp; 7935 convD2I_helper(tmp, src); 7936 MoveF2I_reg_reg(dst, tmp); 7937 %} 7938 %} 7939 7940 7941 // Convert a double to a long in a double register. 7942 // If the double is a NAN, stuff a zero in instead. 7943 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 7944 effect(DEF dst, USE src, KILL fcc0); 7945 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 7946 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7947 "FDTOX $src,$dst\t! convert in delay slot\n\t" 7948 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 7949 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 7950 "skip:" %} 7951 ins_encode(form_d2l_helper(src,dst)); 7952 ins_pipe(fcvtD2L); 7953 %} 7954 7955 instruct convD2L_stk(stackSlotL dst, regD src) %{ 7956 match(Set dst (ConvD2L src)); 7957 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7958 expand %{ 7959 regD tmp; 7960 convD2L_helper(tmp, src); 7961 regD_to_stkL(dst, tmp); 7962 %} 7963 %} 7964 7965 instruct convD2L_reg(iRegL dst, regD src) %{ 7966 predicate(UseVIS >= 3); 7967 match(Set dst (ConvD2L src)); 7968 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 7969 expand %{ 7970 regD tmp; 7971 convD2L_helper(tmp, src); 7972 MoveD2L_reg_reg(dst, tmp); 7973 %} 7974 %} 7975 7976 7977 instruct convF2D_reg(regD dst, regF src) %{ 7978 match(Set dst (ConvF2D src)); 7979 format %{ "FSTOD $src,$dst" %} 7980 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 7981 ins_encode(form3_opf_rs2F_rdD(src, dst)); 7982 ins_pipe(fcvtF2D); 7983 %} 7984 7985 7986 // Convert a float to an int in a float register. 7987 // If the float is a NAN, stuff a zero in instead. 7988 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 7989 effect(DEF dst, USE src, KILL fcc0); 7990 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 7991 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7992 "FSTOI $src,$dst\t! convert in delay slot\n\t" 7993 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 7994 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 7995 "skip:" %} 7996 ins_encode(form_f2i_helper(src,dst)); 7997 ins_pipe(fcvtF2I); 7998 %} 7999 8000 instruct convF2I_stk(stackSlotI dst, regF src) %{ 8001 match(Set dst (ConvF2I src)); 8002 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8003 expand %{ 8004 regF tmp; 8005 convF2I_helper(tmp, src); 8006 regF_to_stkI(dst, tmp); 8007 %} 8008 %} 8009 8010 instruct convF2I_reg(iRegI dst, regF src) %{ 8011 predicate(UseVIS >= 3); 8012 match(Set dst (ConvF2I src)); 8013 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8014 expand %{ 8015 regF tmp; 8016 convF2I_helper(tmp, src); 8017 MoveF2I_reg_reg(dst, tmp); 8018 %} 8019 %} 8020 8021 8022 // Convert a float to a long in a float register. 8023 // If the float is a NAN, stuff a zero in instead. 8024 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8025 effect(DEF dst, USE src, KILL fcc0); 8026 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8027 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8028 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8029 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8030 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8031 "skip:" %} 8032 ins_encode(form_f2l_helper(src,dst)); 8033 ins_pipe(fcvtF2L); 8034 %} 8035 8036 instruct convF2L_stk(stackSlotL dst, regF src) %{ 8037 match(Set dst (ConvF2L src)); 8038 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8039 expand %{ 8040 regD tmp; 8041 convF2L_helper(tmp, src); 8042 regD_to_stkL(dst, tmp); 8043 %} 8044 %} 8045 8046 instruct convF2L_reg(iRegL dst, regF src) %{ 8047 predicate(UseVIS >= 3); 8048 match(Set dst (ConvF2L src)); 8049 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8050 expand %{ 8051 regD tmp; 8052 convF2L_helper(tmp, src); 8053 MoveD2L_reg_reg(dst, tmp); 8054 %} 8055 %} 8056 8057 8058 instruct convI2D_helper(regD dst, regF tmp) %{ 8059 effect(USE tmp, DEF dst); 8060 format %{ "FITOD $tmp,$dst" %} 8061 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8062 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8063 ins_pipe(fcvtI2D); 8064 %} 8065 8066 instruct convI2D_stk(stackSlotI src, regD dst) %{ 8067 match(Set dst (ConvI2D src)); 8068 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8069 expand %{ 8070 regF tmp; 8071 stkI_to_regF(tmp, src); 8072 convI2D_helper(dst, tmp); 8073 %} 8074 %} 8075 8076 instruct convI2D_reg(regD_low dst, iRegI src) %{ 8077 predicate(UseVIS >= 3); 8078 match(Set dst (ConvI2D src)); 8079 expand %{ 8080 regF tmp; 8081 MoveI2F_reg_reg(tmp, src); 8082 convI2D_helper(dst, tmp); 8083 %} 8084 %} 8085 8086 instruct convI2D_mem(regD_low dst, memory mem) %{ 8087 match(Set dst (ConvI2D (LoadI mem))); 8088 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8089 format %{ "LDF $mem,$dst\n\t" 8090 "FITOD $dst,$dst" %} 8091 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8092 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8093 ins_pipe(floadF_mem); 8094 %} 8095 8096 8097 instruct convI2F_helper(regF dst, regF tmp) %{ 8098 effect(DEF dst, USE tmp); 8099 format %{ "FITOS $tmp,$dst" %} 8100 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8101 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8102 ins_pipe(fcvtI2F); 8103 %} 8104 8105 instruct convI2F_stk(regF dst, stackSlotI src) %{ 8106 match(Set dst (ConvI2F src)); 8107 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8108 expand %{ 8109 regF tmp; 8110 stkI_to_regF(tmp,src); 8111 convI2F_helper(dst, tmp); 8112 %} 8113 %} 8114 8115 instruct convI2F_reg(regF dst, iRegI src) %{ 8116 predicate(UseVIS >= 3); 8117 match(Set dst (ConvI2F src)); 8118 ins_cost(DEFAULT_COST); 8119 expand %{ 8120 regF tmp; 8121 MoveI2F_reg_reg(tmp, src); 8122 convI2F_helper(dst, tmp); 8123 %} 8124 %} 8125 8126 instruct convI2F_mem( regF dst, memory mem ) %{ 8127 match(Set dst (ConvI2F (LoadI mem))); 8128 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8129 format %{ "LDF $mem,$dst\n\t" 8130 "FITOS $dst,$dst" %} 8131 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8132 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8133 ins_pipe(floadF_mem); 8134 %} 8135 8136 8137 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8138 match(Set dst (ConvI2L src)); 8139 size(4); 8140 format %{ "SRA $src,0,$dst\t! int->long" %} 8141 opcode(Assembler::sra_op3, Assembler::arith_op); 8142 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8143 ins_pipe(ialu_reg_reg); 8144 %} 8145 8146 // Zero-extend convert int to long 8147 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8148 match(Set dst (AndL (ConvI2L src) mask) ); 8149 size(4); 8150 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8151 opcode(Assembler::srl_op3, Assembler::arith_op); 8152 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8153 ins_pipe(ialu_reg_reg); 8154 %} 8155 8156 // Zero-extend long 8157 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8158 match(Set dst (AndL src mask) ); 8159 size(4); 8160 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8161 opcode(Assembler::srl_op3, Assembler::arith_op); 8162 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8163 ins_pipe(ialu_reg_reg); 8164 %} 8165 8166 8167 //----------- 8168 // Long to Double conversion using V8 opcodes. 8169 // Still useful because cheetah traps and becomes 8170 // amazingly slow for some common numbers. 8171 8172 // Magic constant, 0x43300000 8173 instruct loadConI_x43300000(iRegI dst) %{ 8174 effect(DEF dst); 8175 size(4); 8176 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8177 ins_encode(SetHi22(0x43300000, dst)); 8178 ins_pipe(ialu_none); 8179 %} 8180 8181 // Magic constant, 0x41f00000 8182 instruct loadConI_x41f00000(iRegI dst) %{ 8183 effect(DEF dst); 8184 size(4); 8185 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8186 ins_encode(SetHi22(0x41f00000, dst)); 8187 ins_pipe(ialu_none); 8188 %} 8189 8190 // Construct a double from two float halves 8191 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8192 effect(DEF dst, USE src1, USE src2); 8193 size(8); 8194 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8195 "FMOVS $src2.lo,$dst.lo" %} 8196 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8197 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8198 ins_pipe(faddD_reg_reg); 8199 %} 8200 8201 // Convert integer in high half of a double register (in the lower half of 8202 // the double register file) to double 8203 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8204 effect(DEF dst, USE src); 8205 size(4); 8206 format %{ "FITOD $src,$dst" %} 8207 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8208 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8209 ins_pipe(fcvtLHi2D); 8210 %} 8211 8212 // Add float double precision 8213 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8214 effect(DEF dst, USE src1, USE src2); 8215 size(4); 8216 format %{ "FADDD $src1,$src2,$dst" %} 8217 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8218 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8219 ins_pipe(faddD_reg_reg); 8220 %} 8221 8222 // Sub float double precision 8223 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8224 effect(DEF dst, USE src1, USE src2); 8225 size(4); 8226 format %{ "FSUBD $src1,$src2,$dst" %} 8227 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8228 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8229 ins_pipe(faddD_reg_reg); 8230 %} 8231 8232 // Mul float double precision 8233 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8234 effect(DEF dst, USE src1, USE src2); 8235 size(4); 8236 format %{ "FMULD $src1,$src2,$dst" %} 8237 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8238 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8239 ins_pipe(fmulD_reg_reg); 8240 %} 8241 8242 // Long to Double conversion using fast fxtof 8243 instruct convL2D_helper(regD dst, regD tmp) %{ 8244 effect(DEF dst, USE tmp); 8245 size(4); 8246 format %{ "FXTOD $tmp,$dst" %} 8247 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8248 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8249 ins_pipe(fcvtL2D); 8250 %} 8251 8252 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8253 match(Set dst (ConvL2D src)); 8254 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8255 expand %{ 8256 regD tmp; 8257 stkL_to_regD(tmp, src); 8258 convL2D_helper(dst, tmp); 8259 %} 8260 %} 8261 8262 instruct convL2D_reg(regD dst, iRegL src) %{ 8263 predicate(UseVIS >= 3); 8264 match(Set dst (ConvL2D src)); 8265 expand %{ 8266 regD tmp; 8267 MoveL2D_reg_reg(tmp, src); 8268 convL2D_helper(dst, tmp); 8269 %} 8270 %} 8271 8272 // Long to Float conversion using fast fxtof 8273 instruct convL2F_helper(regF dst, regD tmp) %{ 8274 effect(DEF dst, USE tmp); 8275 size(4); 8276 format %{ "FXTOS $tmp,$dst" %} 8277 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8278 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8279 ins_pipe(fcvtL2F); 8280 %} 8281 8282 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8283 match(Set dst (ConvL2F src)); 8284 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8285 expand %{ 8286 regD tmp; 8287 stkL_to_regD(tmp, src); 8288 convL2F_helper(dst, tmp); 8289 %} 8290 %} 8291 8292 instruct convL2F_reg(regF dst, iRegL src) %{ 8293 predicate(UseVIS >= 3); 8294 match(Set dst (ConvL2F src)); 8295 ins_cost(DEFAULT_COST); 8296 expand %{ 8297 regD tmp; 8298 MoveL2D_reg_reg(tmp, src); 8299 convL2F_helper(dst, tmp); 8300 %} 8301 %} 8302 8303 //----------- 8304 8305 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8306 match(Set dst (ConvL2I src)); 8307 size(4); 8308 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8309 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8310 ins_pipe(ialu_reg); 8311 %} 8312 8313 // Register Shift Right Immediate 8314 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8315 match(Set dst (ConvL2I (RShiftL src cnt))); 8316 8317 size(4); 8318 format %{ "SRAX $src,$cnt,$dst" %} 8319 opcode(Assembler::srax_op3, Assembler::arith_op); 8320 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8321 ins_pipe(ialu_reg_imm); 8322 %} 8323 8324 //----------Control Flow Instructions------------------------------------------ 8325 // Compare Instructions 8326 // Compare Integers 8327 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8328 match(Set icc (CmpI op1 op2)); 8329 effect( DEF icc, USE op1, USE op2 ); 8330 8331 size(4); 8332 format %{ "CMP $op1,$op2" %} 8333 opcode(Assembler::subcc_op3, Assembler::arith_op); 8334 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8335 ins_pipe(ialu_cconly_reg_reg); 8336 %} 8337 8338 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8339 match(Set icc (CmpU op1 op2)); 8340 8341 size(4); 8342 format %{ "CMP $op1,$op2\t! unsigned" %} 8343 opcode(Assembler::subcc_op3, Assembler::arith_op); 8344 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8345 ins_pipe(ialu_cconly_reg_reg); 8346 %} 8347 8348 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8349 match(Set icc (CmpI op1 op2)); 8350 effect( DEF icc, USE op1 ); 8351 8352 size(4); 8353 format %{ "CMP $op1,$op2" %} 8354 opcode(Assembler::subcc_op3, Assembler::arith_op); 8355 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8356 ins_pipe(ialu_cconly_reg_imm); 8357 %} 8358 8359 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8360 match(Set icc (CmpI (AndI op1 op2) zero)); 8361 8362 size(4); 8363 format %{ "BTST $op2,$op1" %} 8364 opcode(Assembler::andcc_op3, Assembler::arith_op); 8365 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8366 ins_pipe(ialu_cconly_reg_reg_zero); 8367 %} 8368 8369 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8370 match(Set icc (CmpI (AndI op1 op2) zero)); 8371 8372 size(4); 8373 format %{ "BTST $op2,$op1" %} 8374 opcode(Assembler::andcc_op3, Assembler::arith_op); 8375 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8376 ins_pipe(ialu_cconly_reg_imm_zero); 8377 %} 8378 8379 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8380 match(Set xcc (CmpL op1 op2)); 8381 effect( DEF xcc, USE op1, USE op2 ); 8382 8383 size(4); 8384 format %{ "CMP $op1,$op2\t\t! long" %} 8385 opcode(Assembler::subcc_op3, Assembler::arith_op); 8386 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8387 ins_pipe(ialu_cconly_reg_reg); 8388 %} 8389 8390 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8391 match(Set xcc (CmpL op1 con)); 8392 effect( DEF xcc, USE op1, USE con ); 8393 8394 size(4); 8395 format %{ "CMP $op1,$con\t\t! long" %} 8396 opcode(Assembler::subcc_op3, Assembler::arith_op); 8397 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8398 ins_pipe(ialu_cconly_reg_reg); 8399 %} 8400 8401 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8402 match(Set xcc (CmpL (AndL op1 op2) zero)); 8403 effect( DEF xcc, USE op1, USE op2 ); 8404 8405 size(4); 8406 format %{ "BTST $op1,$op2\t\t! long" %} 8407 opcode(Assembler::andcc_op3, Assembler::arith_op); 8408 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8409 ins_pipe(ialu_cconly_reg_reg); 8410 %} 8411 8412 // useful for checking the alignment of a pointer: 8413 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8414 match(Set xcc (CmpL (AndL op1 con) zero)); 8415 effect( DEF xcc, USE op1, USE con ); 8416 8417 size(4); 8418 format %{ "BTST $op1,$con\t\t! long" %} 8419 opcode(Assembler::andcc_op3, Assembler::arith_op); 8420 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8421 ins_pipe(ialu_cconly_reg_reg); 8422 %} 8423 8424 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ 8425 match(Set icc (CmpU op1 op2)); 8426 8427 size(4); 8428 format %{ "CMP $op1,$op2\t! unsigned" %} 8429 opcode(Assembler::subcc_op3, Assembler::arith_op); 8430 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8431 ins_pipe(ialu_cconly_reg_imm); 8432 %} 8433 8434 // Compare Pointers 8435 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8436 match(Set pcc (CmpP op1 op2)); 8437 8438 size(4); 8439 format %{ "CMP $op1,$op2\t! ptr" %} 8440 opcode(Assembler::subcc_op3, Assembler::arith_op); 8441 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8442 ins_pipe(ialu_cconly_reg_reg); 8443 %} 8444 8445 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8446 match(Set pcc (CmpP op1 op2)); 8447 8448 size(4); 8449 format %{ "CMP $op1,$op2\t! ptr" %} 8450 opcode(Assembler::subcc_op3, Assembler::arith_op); 8451 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8452 ins_pipe(ialu_cconly_reg_imm); 8453 %} 8454 8455 // Compare Narrow oops 8456 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8457 match(Set icc (CmpN op1 op2)); 8458 8459 size(4); 8460 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8461 opcode(Assembler::subcc_op3, Assembler::arith_op); 8462 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8463 ins_pipe(ialu_cconly_reg_reg); 8464 %} 8465 8466 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8467 match(Set icc (CmpN op1 op2)); 8468 8469 size(4); 8470 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8471 opcode(Assembler::subcc_op3, Assembler::arith_op); 8472 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8473 ins_pipe(ialu_cconly_reg_imm); 8474 %} 8475 8476 //----------Max and Min-------------------------------------------------------- 8477 // Min Instructions 8478 // Conditional move for min 8479 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8480 effect( USE_DEF op2, USE op1, USE icc ); 8481 8482 size(4); 8483 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8484 opcode(Assembler::less); 8485 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8486 ins_pipe(ialu_reg_flags); 8487 %} 8488 8489 // Min Register with Register. 8490 instruct minI_eReg(iRegI op1, iRegI op2) %{ 8491 match(Set op2 (MinI op1 op2)); 8492 ins_cost(DEFAULT_COST*2); 8493 expand %{ 8494 flagsReg icc; 8495 compI_iReg(icc,op1,op2); 8496 cmovI_reg_lt(op2,op1,icc); 8497 %} 8498 %} 8499 8500 // Max Instructions 8501 // Conditional move for max 8502 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8503 effect( USE_DEF op2, USE op1, USE icc ); 8504 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8505 opcode(Assembler::greater); 8506 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8507 ins_pipe(ialu_reg_flags); 8508 %} 8509 8510 // Max Register with Register 8511 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8512 match(Set op2 (MaxI op1 op2)); 8513 ins_cost(DEFAULT_COST*2); 8514 expand %{ 8515 flagsReg icc; 8516 compI_iReg(icc,op1,op2); 8517 cmovI_reg_gt(op2,op1,icc); 8518 %} 8519 %} 8520 8521 8522 //----------Float Compares---------------------------------------------------- 8523 // Compare floating, generate condition code 8524 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8525 match(Set fcc (CmpF src1 src2)); 8526 8527 size(4); 8528 format %{ "FCMPs $fcc,$src1,$src2" %} 8529 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8530 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8531 ins_pipe(faddF_fcc_reg_reg_zero); 8532 %} 8533 8534 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8535 match(Set fcc (CmpD src1 src2)); 8536 8537 size(4); 8538 format %{ "FCMPd $fcc,$src1,$src2" %} 8539 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8540 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8541 ins_pipe(faddD_fcc_reg_reg_zero); 8542 %} 8543 8544 8545 // Compare floating, generate -1,0,1 8546 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8547 match(Set dst (CmpF3 src1 src2)); 8548 effect(KILL fcc0); 8549 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8550 format %{ "fcmpl $dst,$src1,$src2" %} 8551 // Primary = float 8552 opcode( true ); 8553 ins_encode( floating_cmp( dst, src1, src2 ) ); 8554 ins_pipe( floating_cmp ); 8555 %} 8556 8557 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8558 match(Set dst (CmpD3 src1 src2)); 8559 effect(KILL fcc0); 8560 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8561 format %{ "dcmpl $dst,$src1,$src2" %} 8562 // Primary = double (not float) 8563 opcode( false ); 8564 ins_encode( floating_cmp( dst, src1, src2 ) ); 8565 ins_pipe( floating_cmp ); 8566 %} 8567 8568 //----------Branches--------------------------------------------------------- 8569 // Jump 8570 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8571 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8572 match(Jump switch_val); 8573 effect(TEMP table); 8574 8575 ins_cost(350); 8576 8577 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 8578 "LD [O7 + $switch_val], O7\n\t" 8579 "JUMP O7" %} 8580 ins_encode %{ 8581 // Calculate table address into a register. 8582 Register table_reg; 8583 Register label_reg = O7; 8584 // If we are calculating the size of this instruction don't trust 8585 // zero offsets because they might change when 8586 // MachConstantBaseNode decides to optimize the constant table 8587 // base. 8588 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { 8589 table_reg = $constanttablebase; 8590 } else { 8591 table_reg = O7; 8592 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 8593 __ add($constanttablebase, con_offset, table_reg); 8594 } 8595 8596 // Jump to base address + switch value 8597 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 8598 __ jmp(label_reg, G0); 8599 __ delayed()->nop(); 8600 %} 8601 ins_pipe(ialu_reg_reg); 8602 %} 8603 8604 // Direct Branch. Use V8 version with longer range. 8605 instruct branch(label labl) %{ 8606 match(Goto); 8607 effect(USE labl); 8608 8609 size(8); 8610 ins_cost(BRANCH_COST); 8611 format %{ "BA $labl" %} 8612 ins_encode %{ 8613 Label* L = $labl$$label; 8614 __ ba(*L); 8615 __ delayed()->nop(); 8616 %} 8617 ins_avoid_back_to_back(AVOID_BEFORE); 8618 ins_pipe(br); 8619 %} 8620 8621 // Direct Branch, short with no delay slot 8622 instruct branch_short(label labl) %{ 8623 match(Goto); 8624 predicate(UseCBCond); 8625 effect(USE labl); 8626 8627 size(4); 8628 ins_cost(BRANCH_COST); 8629 format %{ "BA $labl\t! short branch" %} 8630 ins_encode %{ 8631 Label* L = $labl$$label; 8632 assert(__ use_cbcond(*L), "back to back cbcond"); 8633 __ ba_short(*L); 8634 %} 8635 ins_short_branch(1); 8636 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 8637 ins_pipe(cbcond_reg_imm); 8638 %} 8639 8640 // Conditional Direct Branch 8641 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8642 match(If cmp icc); 8643 effect(USE labl); 8644 8645 size(8); 8646 ins_cost(BRANCH_COST); 8647 format %{ "BP$cmp $icc,$labl" %} 8648 // Prim = bits 24-22, Secnd = bits 31-30 8649 ins_encode( enc_bp( labl, cmp, icc ) ); 8650 ins_avoid_back_to_back(AVOID_BEFORE); 8651 ins_pipe(br_cc); 8652 %} 8653 8654 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8655 match(If cmp icc); 8656 effect(USE labl); 8657 8658 ins_cost(BRANCH_COST); 8659 format %{ "BP$cmp $icc,$labl" %} 8660 // Prim = bits 24-22, Secnd = bits 31-30 8661 ins_encode( enc_bp( labl, cmp, icc ) ); 8662 ins_avoid_back_to_back(AVOID_BEFORE); 8663 ins_pipe(br_cc); 8664 %} 8665 8666 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 8667 match(If cmp pcc); 8668 effect(USE labl); 8669 8670 size(8); 8671 ins_cost(BRANCH_COST); 8672 format %{ "BP$cmp $pcc,$labl" %} 8673 ins_encode %{ 8674 Label* L = $labl$$label; 8675 Assembler::Predict predict_taken = 8676 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8677 8678 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 8679 __ delayed()->nop(); 8680 %} 8681 ins_avoid_back_to_back(AVOID_BEFORE); 8682 ins_pipe(br_cc); 8683 %} 8684 8685 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 8686 match(If cmp fcc); 8687 effect(USE labl); 8688 8689 size(8); 8690 ins_cost(BRANCH_COST); 8691 format %{ "FBP$cmp $fcc,$labl" %} 8692 ins_encode %{ 8693 Label* L = $labl$$label; 8694 Assembler::Predict predict_taken = 8695 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8696 8697 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 8698 __ delayed()->nop(); 8699 %} 8700 ins_avoid_back_to_back(AVOID_BEFORE); 8701 ins_pipe(br_fcc); 8702 %} 8703 8704 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 8705 match(CountedLoopEnd cmp icc); 8706 effect(USE labl); 8707 8708 size(8); 8709 ins_cost(BRANCH_COST); 8710 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8711 // Prim = bits 24-22, Secnd = bits 31-30 8712 ins_encode( enc_bp( labl, cmp, icc ) ); 8713 ins_avoid_back_to_back(AVOID_BEFORE); 8714 ins_pipe(br_cc); 8715 %} 8716 8717 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8718 match(CountedLoopEnd cmp icc); 8719 effect(USE labl); 8720 8721 size(8); 8722 ins_cost(BRANCH_COST); 8723 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8724 // Prim = bits 24-22, Secnd = bits 31-30 8725 ins_encode( enc_bp( labl, cmp, icc ) ); 8726 ins_avoid_back_to_back(AVOID_BEFORE); 8727 ins_pipe(br_cc); 8728 %} 8729 8730 // Compare and branch instructions 8731 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 8732 match(If cmp (CmpI op1 op2)); 8733 effect(USE labl, KILL icc); 8734 8735 size(12); 8736 ins_cost(BRANCH_COST); 8737 format %{ "CMP $op1,$op2\t! int\n\t" 8738 "BP$cmp $labl" %} 8739 ins_encode %{ 8740 Label* L = $labl$$label; 8741 Assembler::Predict predict_taken = 8742 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8743 __ cmp($op1$$Register, $op2$$Register); 8744 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8745 __ delayed()->nop(); 8746 %} 8747 ins_pipe(cmp_br_reg_reg); 8748 %} 8749 8750 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 8751 match(If cmp (CmpI op1 op2)); 8752 effect(USE labl, KILL icc); 8753 8754 size(12); 8755 ins_cost(BRANCH_COST); 8756 format %{ "CMP $op1,$op2\t! int\n\t" 8757 "BP$cmp $labl" %} 8758 ins_encode %{ 8759 Label* L = $labl$$label; 8760 Assembler::Predict predict_taken = 8761 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8762 __ cmp($op1$$Register, $op2$$constant); 8763 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8764 __ delayed()->nop(); 8765 %} 8766 ins_pipe(cmp_br_reg_imm); 8767 %} 8768 8769 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 8770 match(If cmp (CmpU op1 op2)); 8771 effect(USE labl, KILL icc); 8772 8773 size(12); 8774 ins_cost(BRANCH_COST); 8775 format %{ "CMP $op1,$op2\t! unsigned\n\t" 8776 "BP$cmp $labl" %} 8777 ins_encode %{ 8778 Label* L = $labl$$label; 8779 Assembler::Predict predict_taken = 8780 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8781 __ cmp($op1$$Register, $op2$$Register); 8782 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8783 __ delayed()->nop(); 8784 %} 8785 ins_pipe(cmp_br_reg_reg); 8786 %} 8787 8788 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 8789 match(If cmp (CmpU op1 op2)); 8790 effect(USE labl, KILL icc); 8791 8792 size(12); 8793 ins_cost(BRANCH_COST); 8794 format %{ "CMP $op1,$op2\t! unsigned\n\t" 8795 "BP$cmp $labl" %} 8796 ins_encode %{ 8797 Label* L = $labl$$label; 8798 Assembler::Predict predict_taken = 8799 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8800 __ cmp($op1$$Register, $op2$$constant); 8801 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8802 __ delayed()->nop(); 8803 %} 8804 ins_pipe(cmp_br_reg_imm); 8805 %} 8806 8807 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 8808 match(If cmp (CmpL op1 op2)); 8809 effect(USE labl, KILL xcc); 8810 8811 size(12); 8812 ins_cost(BRANCH_COST); 8813 format %{ "CMP $op1,$op2\t! long\n\t" 8814 "BP$cmp $labl" %} 8815 ins_encode %{ 8816 Label* L = $labl$$label; 8817 Assembler::Predict predict_taken = 8818 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8819 __ cmp($op1$$Register, $op2$$Register); 8820 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 8821 __ delayed()->nop(); 8822 %} 8823 ins_pipe(cmp_br_reg_reg); 8824 %} 8825 8826 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 8827 match(If cmp (CmpL op1 op2)); 8828 effect(USE labl, KILL xcc); 8829 8830 size(12); 8831 ins_cost(BRANCH_COST); 8832 format %{ "CMP $op1,$op2\t! long\n\t" 8833 "BP$cmp $labl" %} 8834 ins_encode %{ 8835 Label* L = $labl$$label; 8836 Assembler::Predict predict_taken = 8837 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8838 __ cmp($op1$$Register, $op2$$constant); 8839 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 8840 __ delayed()->nop(); 8841 %} 8842 ins_pipe(cmp_br_reg_imm); 8843 %} 8844 8845 // Compare Pointers and branch 8846 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 8847 match(If cmp (CmpP op1 op2)); 8848 effect(USE labl, KILL pcc); 8849 8850 size(12); 8851 ins_cost(BRANCH_COST); 8852 format %{ "CMP $op1,$op2\t! ptr\n\t" 8853 "B$cmp $labl" %} 8854 ins_encode %{ 8855 Label* L = $labl$$label; 8856 Assembler::Predict predict_taken = 8857 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8858 __ cmp($op1$$Register, $op2$$Register); 8859 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 8860 __ delayed()->nop(); 8861 %} 8862 ins_pipe(cmp_br_reg_reg); 8863 %} 8864 8865 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 8866 match(If cmp (CmpP op1 null)); 8867 effect(USE labl, KILL pcc); 8868 8869 size(12); 8870 ins_cost(BRANCH_COST); 8871 format %{ "CMP $op1,0\t! ptr\n\t" 8872 "B$cmp $labl" %} 8873 ins_encode %{ 8874 Label* L = $labl$$label; 8875 Assembler::Predict predict_taken = 8876 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8877 __ cmp($op1$$Register, G0); 8878 // bpr() is not used here since it has shorter distance. 8879 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 8880 __ delayed()->nop(); 8881 %} 8882 ins_pipe(cmp_br_reg_reg); 8883 %} 8884 8885 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 8886 match(If cmp (CmpN op1 op2)); 8887 effect(USE labl, KILL icc); 8888 8889 size(12); 8890 ins_cost(BRANCH_COST); 8891 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 8892 "BP$cmp $labl" %} 8893 ins_encode %{ 8894 Label* L = $labl$$label; 8895 Assembler::Predict predict_taken = 8896 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8897 __ cmp($op1$$Register, $op2$$Register); 8898 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8899 __ delayed()->nop(); 8900 %} 8901 ins_pipe(cmp_br_reg_reg); 8902 %} 8903 8904 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 8905 match(If cmp (CmpN op1 null)); 8906 effect(USE labl, KILL icc); 8907 8908 size(12); 8909 ins_cost(BRANCH_COST); 8910 format %{ "CMP $op1,0\t! compressed ptr\n\t" 8911 "BP$cmp $labl" %} 8912 ins_encode %{ 8913 Label* L = $labl$$label; 8914 Assembler::Predict predict_taken = 8915 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8916 __ cmp($op1$$Register, G0); 8917 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8918 __ delayed()->nop(); 8919 %} 8920 ins_pipe(cmp_br_reg_reg); 8921 %} 8922 8923 // Loop back branch 8924 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 8925 match(CountedLoopEnd cmp (CmpI op1 op2)); 8926 effect(USE labl, KILL icc); 8927 8928 size(12); 8929 ins_cost(BRANCH_COST); 8930 format %{ "CMP $op1,$op2\t! int\n\t" 8931 "BP$cmp $labl\t! Loop end" %} 8932 ins_encode %{ 8933 Label* L = $labl$$label; 8934 Assembler::Predict predict_taken = 8935 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8936 __ cmp($op1$$Register, $op2$$Register); 8937 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8938 __ delayed()->nop(); 8939 %} 8940 ins_pipe(cmp_br_reg_reg); 8941 %} 8942 8943 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 8944 match(CountedLoopEnd cmp (CmpI op1 op2)); 8945 effect(USE labl, KILL icc); 8946 8947 size(12); 8948 ins_cost(BRANCH_COST); 8949 format %{ "CMP $op1,$op2\t! int\n\t" 8950 "BP$cmp $labl\t! Loop end" %} 8951 ins_encode %{ 8952 Label* L = $labl$$label; 8953 Assembler::Predict predict_taken = 8954 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8955 __ cmp($op1$$Register, $op2$$constant); 8956 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8957 __ delayed()->nop(); 8958 %} 8959 ins_pipe(cmp_br_reg_imm); 8960 %} 8961 8962 // Short compare and branch instructions 8963 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 8964 match(If cmp (CmpI op1 op2)); 8965 predicate(UseCBCond); 8966 effect(USE labl, KILL icc); 8967 8968 size(4); 8969 ins_cost(BRANCH_COST); 8970 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 8971 ins_encode %{ 8972 Label* L = $labl$$label; 8973 assert(__ use_cbcond(*L), "back to back cbcond"); 8974 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 8975 %} 8976 ins_short_branch(1); 8977 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 8978 ins_pipe(cbcond_reg_reg); 8979 %} 8980 8981 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 8982 match(If cmp (CmpI op1 op2)); 8983 predicate(UseCBCond); 8984 effect(USE labl, KILL icc); 8985 8986 size(4); 8987 ins_cost(BRANCH_COST); 8988 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 8989 ins_encode %{ 8990 Label* L = $labl$$label; 8991 assert(__ use_cbcond(*L), "back to back cbcond"); 8992 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 8993 %} 8994 ins_short_branch(1); 8995 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 8996 ins_pipe(cbcond_reg_imm); 8997 %} 8998 8999 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9000 match(If cmp (CmpU op1 op2)); 9001 predicate(UseCBCond); 9002 effect(USE labl, KILL icc); 9003 9004 size(4); 9005 ins_cost(BRANCH_COST); 9006 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9007 ins_encode %{ 9008 Label* L = $labl$$label; 9009 assert(__ use_cbcond(*L), "back to back cbcond"); 9010 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9011 %} 9012 ins_short_branch(1); 9013 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9014 ins_pipe(cbcond_reg_reg); 9015 %} 9016 9017 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9018 match(If cmp (CmpU op1 op2)); 9019 predicate(UseCBCond); 9020 effect(USE labl, KILL icc); 9021 9022 size(4); 9023 ins_cost(BRANCH_COST); 9024 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9025 ins_encode %{ 9026 Label* L = $labl$$label; 9027 assert(__ use_cbcond(*L), "back to back cbcond"); 9028 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9029 %} 9030 ins_short_branch(1); 9031 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9032 ins_pipe(cbcond_reg_imm); 9033 %} 9034 9035 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9036 match(If cmp (CmpL op1 op2)); 9037 predicate(UseCBCond); 9038 effect(USE labl, KILL xcc); 9039 9040 size(4); 9041 ins_cost(BRANCH_COST); 9042 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9043 ins_encode %{ 9044 Label* L = $labl$$label; 9045 assert(__ use_cbcond(*L), "back to back cbcond"); 9046 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9047 %} 9048 ins_short_branch(1); 9049 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9050 ins_pipe(cbcond_reg_reg); 9051 %} 9052 9053 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9054 match(If cmp (CmpL op1 op2)); 9055 predicate(UseCBCond); 9056 effect(USE labl, KILL xcc); 9057 9058 size(4); 9059 ins_cost(BRANCH_COST); 9060 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9061 ins_encode %{ 9062 Label* L = $labl$$label; 9063 assert(__ use_cbcond(*L), "back to back cbcond"); 9064 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9065 %} 9066 ins_short_branch(1); 9067 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9068 ins_pipe(cbcond_reg_imm); 9069 %} 9070 9071 // Compare Pointers and branch 9072 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9073 match(If cmp (CmpP op1 op2)); 9074 predicate(UseCBCond); 9075 effect(USE labl, KILL pcc); 9076 9077 size(4); 9078 ins_cost(BRANCH_COST); 9079 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9080 ins_encode %{ 9081 Label* L = $labl$$label; 9082 assert(__ use_cbcond(*L), "back to back cbcond"); 9083 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9084 %} 9085 ins_short_branch(1); 9086 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9087 ins_pipe(cbcond_reg_reg); 9088 %} 9089 9090 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9091 match(If cmp (CmpP op1 null)); 9092 predicate(UseCBCond); 9093 effect(USE labl, KILL pcc); 9094 9095 size(4); 9096 ins_cost(BRANCH_COST); 9097 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9098 ins_encode %{ 9099 Label* L = $labl$$label; 9100 assert(__ use_cbcond(*L), "back to back cbcond"); 9101 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9102 %} 9103 ins_short_branch(1); 9104 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9105 ins_pipe(cbcond_reg_reg); 9106 %} 9107 9108 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9109 match(If cmp (CmpN op1 op2)); 9110 predicate(UseCBCond); 9111 effect(USE labl, KILL icc); 9112 9113 size(4); 9114 ins_cost(BRANCH_COST); 9115 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %} 9116 ins_encode %{ 9117 Label* L = $labl$$label; 9118 assert(__ use_cbcond(*L), "back to back cbcond"); 9119 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9120 %} 9121 ins_short_branch(1); 9122 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9123 ins_pipe(cbcond_reg_reg); 9124 %} 9125 9126 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9127 match(If cmp (CmpN op1 null)); 9128 predicate(UseCBCond); 9129 effect(USE labl, KILL icc); 9130 9131 size(4); 9132 ins_cost(BRANCH_COST); 9133 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9134 ins_encode %{ 9135 Label* L = $labl$$label; 9136 assert(__ use_cbcond(*L), "back to back cbcond"); 9137 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9138 %} 9139 ins_short_branch(1); 9140 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9141 ins_pipe(cbcond_reg_reg); 9142 %} 9143 9144 // Loop back branch 9145 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9146 match(CountedLoopEnd cmp (CmpI op1 op2)); 9147 predicate(UseCBCond); 9148 effect(USE labl, KILL icc); 9149 9150 size(4); 9151 ins_cost(BRANCH_COST); 9152 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9153 ins_encode %{ 9154 Label* L = $labl$$label; 9155 assert(__ use_cbcond(*L), "back to back cbcond"); 9156 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9157 %} 9158 ins_short_branch(1); 9159 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9160 ins_pipe(cbcond_reg_reg); 9161 %} 9162 9163 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9164 match(CountedLoopEnd cmp (CmpI op1 op2)); 9165 predicate(UseCBCond); 9166 effect(USE labl, KILL icc); 9167 9168 size(4); 9169 ins_cost(BRANCH_COST); 9170 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9171 ins_encode %{ 9172 Label* L = $labl$$label; 9173 assert(__ use_cbcond(*L), "back to back cbcond"); 9174 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9175 %} 9176 ins_short_branch(1); 9177 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9178 ins_pipe(cbcond_reg_imm); 9179 %} 9180 9181 // Branch-on-register tests all 64 bits. We assume that values 9182 // in 64-bit registers always remains zero or sign extended 9183 // unless our code munges the high bits. Interrupts can chop 9184 // the high order bits to zero or sign at any time. 9185 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9186 match(If cmp (CmpI op1 zero)); 9187 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9188 effect(USE labl); 9189 9190 size(8); 9191 ins_cost(BRANCH_COST); 9192 format %{ "BR$cmp $op1,$labl" %} 9193 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9194 ins_avoid_back_to_back(AVOID_BEFORE); 9195 ins_pipe(br_reg); 9196 %} 9197 9198 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9199 match(If cmp (CmpP op1 null)); 9200 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9201 effect(USE labl); 9202 9203 size(8); 9204 ins_cost(BRANCH_COST); 9205 format %{ "BR$cmp $op1,$labl" %} 9206 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9207 ins_avoid_back_to_back(AVOID_BEFORE); 9208 ins_pipe(br_reg); 9209 %} 9210 9211 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9212 match(If cmp (CmpL op1 zero)); 9213 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9214 effect(USE labl); 9215 9216 size(8); 9217 ins_cost(BRANCH_COST); 9218 format %{ "BR$cmp $op1,$labl" %} 9219 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9220 ins_avoid_back_to_back(AVOID_BEFORE); 9221 ins_pipe(br_reg); 9222 %} 9223 9224 9225 // ============================================================================ 9226 // Long Compare 9227 // 9228 // Currently we hold longs in 2 registers. Comparing such values efficiently 9229 // is tricky. The flavor of compare used depends on whether we are testing 9230 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9231 // The GE test is the negated LT test. The LE test can be had by commuting 9232 // the operands (yielding a GE test) and then negating; negate again for the 9233 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9234 // NE test is negated from that. 9235 9236 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9237 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9238 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9239 // are collapsed internally in the ADLC's dfa-gen code. The match for 9240 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9241 // foo match ends up with the wrong leaf. One fix is to not match both 9242 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9243 // both forms beat the trinary form of long-compare and both are very useful 9244 // on Intel which has so few registers. 9245 9246 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9247 match(If cmp xcc); 9248 effect(USE labl); 9249 9250 size(8); 9251 ins_cost(BRANCH_COST); 9252 format %{ "BP$cmp $xcc,$labl" %} 9253 ins_encode %{ 9254 Label* L = $labl$$label; 9255 Assembler::Predict predict_taken = 9256 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9257 9258 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9259 __ delayed()->nop(); 9260 %} 9261 ins_avoid_back_to_back(AVOID_BEFORE); 9262 ins_pipe(br_cc); 9263 %} 9264 9265 // Manifest a CmpL3 result in an integer register. Very painful. 9266 // This is the test to avoid. 9267 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9268 match(Set dst (CmpL3 src1 src2) ); 9269 effect( KILL ccr ); 9270 ins_cost(6*DEFAULT_COST); 9271 size(24); 9272 format %{ "CMP $src1,$src2\t\t! long\n" 9273 "\tBLT,a,pn done\n" 9274 "\tMOV -1,$dst\t! delay slot\n" 9275 "\tBGT,a,pn done\n" 9276 "\tMOV 1,$dst\t! delay slot\n" 9277 "\tCLR $dst\n" 9278 "done:" %} 9279 ins_encode( cmpl_flag(src1,src2,dst) ); 9280 ins_pipe(cmpL_reg); 9281 %} 9282 9283 // Conditional move 9284 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9285 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9286 ins_cost(150); 9287 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9288 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9289 ins_pipe(ialu_reg); 9290 %} 9291 9292 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9293 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9294 ins_cost(140); 9295 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9296 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9297 ins_pipe(ialu_imm); 9298 %} 9299 9300 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9301 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9302 ins_cost(150); 9303 format %{ "MOV$cmp $xcc,$src,$dst" %} 9304 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9305 ins_pipe(ialu_reg); 9306 %} 9307 9308 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9309 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9310 ins_cost(140); 9311 format %{ "MOV$cmp $xcc,$src,$dst" %} 9312 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9313 ins_pipe(ialu_imm); 9314 %} 9315 9316 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9317 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9318 ins_cost(150); 9319 format %{ "MOV$cmp $xcc,$src,$dst" %} 9320 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9321 ins_pipe(ialu_reg); 9322 %} 9323 9324 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9325 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9326 ins_cost(150); 9327 format %{ "MOV$cmp $xcc,$src,$dst" %} 9328 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9329 ins_pipe(ialu_reg); 9330 %} 9331 9332 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9333 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9334 ins_cost(140); 9335 format %{ "MOV$cmp $xcc,$src,$dst" %} 9336 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9337 ins_pipe(ialu_imm); 9338 %} 9339 9340 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9341 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9342 ins_cost(150); 9343 opcode(0x101); 9344 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9345 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9346 ins_pipe(int_conditional_float_move); 9347 %} 9348 9349 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9350 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9351 ins_cost(150); 9352 opcode(0x102); 9353 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9354 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9355 ins_pipe(int_conditional_float_move); 9356 %} 9357 9358 // ============================================================================ 9359 // Safepoint Instruction 9360 instruct safePoint_poll(iRegP poll) %{ 9361 match(SafePoint poll); 9362 effect(USE poll); 9363 9364 size(4); 9365 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9366 ins_encode %{ 9367 __ relocate(relocInfo::poll_type); 9368 __ ld_ptr($poll$$Register, 0, G0); 9369 %} 9370 ins_pipe(loadPollP); 9371 %} 9372 9373 // ============================================================================ 9374 // Call Instructions 9375 // Call Java Static Instruction 9376 instruct CallStaticJavaDirect( method meth ) %{ 9377 match(CallStaticJava); 9378 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9379 effect(USE meth); 9380 9381 size(8); 9382 ins_cost(CALL_COST); 9383 format %{ "CALL,static ; NOP ==> " %} 9384 ins_encode( Java_Static_Call( meth ), call_epilog ); 9385 ins_avoid_back_to_back(AVOID_BEFORE); 9386 ins_pipe(simple_call); 9387 %} 9388 9389 // Call Java Static Instruction (method handle version) 9390 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9391 match(CallStaticJava); 9392 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9393 effect(USE meth, KILL l7_mh_SP_save); 9394 9395 size(16); 9396 ins_cost(CALL_COST); 9397 format %{ "CALL,static/MethodHandle" %} 9398 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9399 ins_pipe(simple_call); 9400 %} 9401 9402 // Call Java Dynamic Instruction 9403 instruct CallDynamicJavaDirect( method meth ) %{ 9404 match(CallDynamicJava); 9405 effect(USE meth); 9406 9407 ins_cost(CALL_COST); 9408 format %{ "SET (empty),R_G5\n\t" 9409 "CALL,dynamic ; NOP ==> " %} 9410 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9411 ins_pipe(call); 9412 %} 9413 9414 // Call Runtime Instruction 9415 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9416 match(CallRuntime); 9417 effect(USE meth, KILL l7); 9418 ins_cost(CALL_COST); 9419 format %{ "CALL,runtime" %} 9420 ins_encode( Java_To_Runtime( meth ), 9421 call_epilog, adjust_long_from_native_call ); 9422 ins_avoid_back_to_back(AVOID_BEFORE); 9423 ins_pipe(simple_call); 9424 %} 9425 9426 // Call runtime without safepoint - same as CallRuntime 9427 instruct CallLeafDirect(method meth, l7RegP l7) %{ 9428 match(CallLeaf); 9429 effect(USE meth, KILL l7); 9430 ins_cost(CALL_COST); 9431 format %{ "CALL,runtime leaf" %} 9432 ins_encode( Java_To_Runtime( meth ), 9433 call_epilog, 9434 adjust_long_from_native_call ); 9435 ins_avoid_back_to_back(AVOID_BEFORE); 9436 ins_pipe(simple_call); 9437 %} 9438 9439 // Call runtime without safepoint - same as CallLeaf 9440 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9441 match(CallLeafNoFP); 9442 effect(USE meth, KILL l7); 9443 ins_cost(CALL_COST); 9444 format %{ "CALL,runtime leaf nofp" %} 9445 ins_encode( Java_To_Runtime( meth ), 9446 call_epilog, 9447 adjust_long_from_native_call ); 9448 ins_avoid_back_to_back(AVOID_BEFORE); 9449 ins_pipe(simple_call); 9450 %} 9451 9452 // Tail Call; Jump from runtime stub to Java code. 9453 // Also known as an 'interprocedural jump'. 9454 // Target of jump will eventually return to caller. 9455 // TailJump below removes the return address. 9456 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9457 match(TailCall jump_target method_oop ); 9458 9459 ins_cost(CALL_COST); 9460 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9461 ins_encode(form_jmpl(jump_target)); 9462 ins_avoid_back_to_back(AVOID_BEFORE); 9463 ins_pipe(tail_call); 9464 %} 9465 9466 9467 // Return Instruction 9468 instruct Ret() %{ 9469 match(Return); 9470 9471 // The epilogue node did the ret already. 9472 size(0); 9473 format %{ "! return" %} 9474 ins_encode(); 9475 ins_pipe(empty); 9476 %} 9477 9478 9479 // Tail Jump; remove the return address; jump to target. 9480 // TailCall above leaves the return address around. 9481 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9482 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9483 // "restore" before this instruction (in Epilogue), we need to materialize it 9484 // in %i0. 9485 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9486 match( TailJump jump_target ex_oop ); 9487 ins_cost(CALL_COST); 9488 format %{ "! discard R_O7\n\t" 9489 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9490 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9491 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9492 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9493 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9494 ins_avoid_back_to_back(AVOID_BEFORE); 9495 ins_pipe(tail_call); 9496 %} 9497 9498 // Create exception oop: created by stack-crawling runtime code. 9499 // Created exception is now available to this handler, and is setup 9500 // just prior to jumping to this handler. No code emitted. 9501 instruct CreateException( o0RegP ex_oop ) 9502 %{ 9503 match(Set ex_oop (CreateEx)); 9504 ins_cost(0); 9505 9506 size(0); 9507 // use the following format syntax 9508 format %{ "! exception oop is in R_O0; no code emitted" %} 9509 ins_encode(); 9510 ins_pipe(empty); 9511 %} 9512 9513 9514 // Rethrow exception: 9515 // The exception oop will come in the first argument position. 9516 // Then JUMP (not call) to the rethrow stub code. 9517 instruct RethrowException() 9518 %{ 9519 match(Rethrow); 9520 ins_cost(CALL_COST); 9521 9522 // use the following format syntax 9523 format %{ "Jmp rethrow_stub" %} 9524 ins_encode(enc_rethrow); 9525 ins_avoid_back_to_back(AVOID_BEFORE); 9526 ins_pipe(tail_call); 9527 %} 9528 9529 9530 // Die now 9531 instruct ShouldNotReachHere( ) 9532 %{ 9533 match(Halt); 9534 ins_cost(CALL_COST); 9535 9536 size(4); 9537 // Use the following format syntax 9538 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9539 ins_encode( form2_illtrap() ); 9540 ins_pipe(tail_call); 9541 %} 9542 9543 // ============================================================================ 9544 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9545 // array for an instance of the superklass. Set a hidden internal cache on a 9546 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9547 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9548 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9549 match(Set index (PartialSubtypeCheck sub super)); 9550 effect( KILL pcc, KILL o7 ); 9551 ins_cost(DEFAULT_COST*10); 9552 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9553 ins_encode( enc_PartialSubtypeCheck() ); 9554 ins_avoid_back_to_back(AVOID_BEFORE); 9555 ins_pipe(partial_subtype_check_pipe); 9556 %} 9557 9558 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9559 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9560 effect( KILL idx, KILL o7 ); 9561 ins_cost(DEFAULT_COST*10); 9562 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9563 ins_encode( enc_PartialSubtypeCheck() ); 9564 ins_avoid_back_to_back(AVOID_BEFORE); 9565 ins_pipe(partial_subtype_check_pipe); 9566 %} 9567 9568 9569 // ============================================================================ 9570 // inlined locking and unlocking 9571 9572 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 9573 match(Set pcc (FastLock object box)); 9574 9575 effect(TEMP scratch2, USE_KILL box, KILL scratch); 9576 ins_cost(100); 9577 9578 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 9579 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9580 ins_pipe(long_memory_op); 9581 %} 9582 9583 9584 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 9585 match(Set pcc (FastUnlock object box)); 9586 effect(TEMP scratch2, USE_KILL box, KILL scratch); 9587 ins_cost(100); 9588 9589 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 9590 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9591 ins_pipe(long_memory_op); 9592 %} 9593 9594 // The encodings are generic. 9595 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9596 predicate(!use_block_zeroing(n->in(2)) ); 9597 match(Set dummy (ClearArray cnt base)); 9598 effect(TEMP temp, KILL ccr); 9599 ins_cost(300); 9600 format %{ "MOV $cnt,$temp\n" 9601 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9602 " BRge loop\t\t! Clearing loop\n" 9603 " STX G0,[$base+$temp]\t! delay slot" %} 9604 9605 ins_encode %{ 9606 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 9607 Register nof_bytes_arg = $cnt$$Register; 9608 Register nof_bytes_tmp = $temp$$Register; 9609 Register base_pointer_arg = $base$$Register; 9610 9611 Label loop; 9612 __ mov(nof_bytes_arg, nof_bytes_tmp); 9613 9614 // Loop and clear, walking backwards through the array. 9615 // nof_bytes_tmp (if >0) is always the number of bytes to zero 9616 __ bind(loop); 9617 __ deccc(nof_bytes_tmp, 8); 9618 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 9619 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 9620 // %%%% this mini-loop must not cross a cache boundary! 9621 %} 9622 ins_pipe(long_memory_op); 9623 %} 9624 9625 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ 9626 predicate(use_block_zeroing(n->in(2))); 9627 match(Set dummy (ClearArray cnt base)); 9628 effect(USE_KILL cnt, USE_KILL base, KILL ccr); 9629 ins_cost(300); 9630 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 9631 9632 ins_encode %{ 9633 9634 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 9635 Register to = $base$$Register; 9636 Register count = $cnt$$Register; 9637 9638 Label Ldone; 9639 __ nop(); // Separate short branches 9640 // Use BIS for zeroing (temp is not used). 9641 __ bis_zeroing(to, count, G0, Ldone); 9642 __ bind(Ldone); 9643 9644 %} 9645 ins_pipe(long_memory_op); 9646 %} 9647 9648 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ 9649 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); 9650 match(Set dummy (ClearArray cnt base)); 9651 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); 9652 ins_cost(300); 9653 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 9654 9655 ins_encode %{ 9656 9657 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 9658 Register to = $base$$Register; 9659 Register count = $cnt$$Register; 9660 Register temp = $tmp$$Register; 9661 9662 Label Ldone; 9663 __ nop(); // Separate short branches 9664 // Use BIS for zeroing 9665 __ bis_zeroing(to, count, temp, Ldone); 9666 __ bind(Ldone); 9667 9668 %} 9669 ins_pipe(long_memory_op); 9670 %} 9671 9672 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9673 o7RegI tmp, flagsReg ccr) %{ 9674 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 9675 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9676 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9677 ins_cost(300); 9678 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9679 ins_encode %{ 9680 __ string_compare($str1$$Register, $str2$$Register, 9681 $cnt1$$Register, $cnt2$$Register, 9682 $tmp$$Register, $tmp$$Register, 9683 $result$$Register, StrIntrinsicNode::LL); 9684 %} 9685 ins_pipe(long_memory_op); 9686 %} 9687 9688 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9689 o7RegI tmp, flagsReg ccr) %{ 9690 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU); 9691 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9692 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9693 ins_cost(300); 9694 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9695 ins_encode %{ 9696 __ string_compare($str1$$Register, $str2$$Register, 9697 $cnt1$$Register, $cnt2$$Register, 9698 $tmp$$Register, $tmp$$Register, 9699 $result$$Register, StrIntrinsicNode::UU); 9700 %} 9701 ins_pipe(long_memory_op); 9702 %} 9703 9704 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9705 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 9706 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 9707 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9708 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 9709 ins_cost(300); 9710 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 9711 ins_encode %{ 9712 __ string_compare($str1$$Register, $str2$$Register, 9713 $cnt1$$Register, $cnt2$$Register, 9714 $tmp1$$Register, $tmp2$$Register, 9715 $result$$Register, StrIntrinsicNode::LU); 9716 %} 9717 ins_pipe(long_memory_op); 9718 %} 9719 9720 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9721 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 9722 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 9723 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9724 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 9725 ins_cost(300); 9726 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 9727 ins_encode %{ 9728 __ string_compare($str2$$Register, $str1$$Register, 9729 $cnt2$$Register, $cnt1$$Register, 9730 $tmp1$$Register, $tmp2$$Register, 9731 $result$$Register, StrIntrinsicNode::UL); 9732 %} 9733 ins_pipe(long_memory_op); 9734 %} 9735 9736 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9737 o7RegI tmp, flagsReg ccr) %{ 9738 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 9739 match(Set result (StrEquals (Binary str1 str2) cnt)); 9740 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9741 ins_cost(300); 9742 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 9743 ins_encode %{ 9744 __ array_equals(false, $str1$$Register, $str2$$Register, 9745 $cnt$$Register, $tmp$$Register, 9746 $result$$Register, true /* byte */); 9747 %} 9748 ins_pipe(long_memory_op); 9749 %} 9750 9751 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9752 o7RegI tmp, flagsReg ccr) %{ 9753 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 9754 match(Set result (StrEquals (Binary str1 str2) cnt)); 9755 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9756 ins_cost(300); 9757 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 9758 ins_encode %{ 9759 __ array_equals(false, $str1$$Register, $str2$$Register, 9760 $cnt$$Register, $tmp$$Register, 9761 $result$$Register, false /* byte */); 9762 %} 9763 ins_pipe(long_memory_op); 9764 %} 9765 9766 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9767 o7RegI tmp2, flagsReg ccr) %{ 9768 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 9769 match(Set result (AryEq ary1 ary2)); 9770 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9771 ins_cost(300); 9772 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9773 ins_encode %{ 9774 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9775 $tmp1$$Register, $tmp2$$Register, 9776 $result$$Register, true /* byte */); 9777 %} 9778 ins_pipe(long_memory_op); 9779 %} 9780 9781 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9782 o7RegI tmp2, flagsReg ccr) %{ 9783 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 9784 match(Set result (AryEq ary1 ary2)); 9785 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9786 ins_cost(300); 9787 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9788 ins_encode %{ 9789 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9790 $tmp1$$Register, $tmp2$$Register, 9791 $result$$Register, false /* byte */); 9792 %} 9793 ins_pipe(long_memory_op); 9794 %} 9795 9796 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR, 9797 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L, 9798 flagsReg ccr) 9799 %{ 9800 match(Set resultR (HasNegatives pAryR iSizeR)); 9801 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr); 9802 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %} 9803 ins_encode %{ 9804 __ has_negatives($pAryR$$Register, $iSizeR$$Register, 9805 $resultR$$Register, 9806 $tmp1L$$Register, $tmp2L$$Register, 9807 $tmp3L$$Register, $tmp4L$$Register); 9808 %} 9809 ins_pipe(long_memory_op); 9810 %} 9811 9812 // char[] to byte[] compression 9813 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{ 9814 predicate(UseVIS < 3); 9815 match(Set result (StrCompressedCopy src (Binary dst len))); 9816 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 9817 ins_cost(300); 9818 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %} 9819 ins_encode %{ 9820 Label Ldone; 9821 __ signx($len$$Register); 9822 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn); 9823 __ delayed()->mov($len$$Register, $result$$Register); // copy count 9824 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone); 9825 __ bind(Ldone); 9826 %} 9827 ins_pipe(long_memory_op); 9828 %} 9829 9830 // fast char[] to byte[] compression using VIS instructions 9831 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, 9832 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4, 9833 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{ 9834 predicate(UseVIS >= 3); 9835 match(Set result (StrCompressedCopy src (Binary dst len))); 9836 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 9837 ins_cost(300); 9838 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %} 9839 ins_encode %{ 9840 Label Ldone; 9841 __ signx($len$$Register); 9842 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register, 9843 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, 9844 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone); 9845 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 9846 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone); 9847 __ bind(Ldone); 9848 %} 9849 ins_pipe(long_memory_op); 9850 %} 9851 9852 // byte[] to char[] inflation 9853 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 9854 iRegL tmp, flagsReg ccr) %{ 9855 match(Set dummy (StrInflatedCopy src (Binary dst len))); 9856 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 9857 ins_cost(300); 9858 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %} 9859 ins_encode %{ 9860 Label Ldone; 9861 __ signx($len$$Register); 9862 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 9863 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 9864 __ bind(Ldone); 9865 %} 9866 ins_pipe(long_memory_op); 9867 %} 9868 9869 // fast byte[] to char[] inflation using VIS instructions 9870 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 9871 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{ 9872 predicate(UseVIS >= 3); 9873 match(Set dummy (StrInflatedCopy src (Binary dst len))); 9874 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 9875 ins_cost(300); 9876 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %} 9877 ins_encode %{ 9878 Label Ldone; 9879 __ signx($len$$Register); 9880 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, 9881 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone); 9882 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 9883 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 9884 __ bind(Ldone); 9885 %} 9886 ins_pipe(long_memory_op); 9887 %} 9888 9889 9890 //---------- Zeros Count Instructions ------------------------------------------ 9891 9892 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ 9893 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9894 match(Set dst (CountLeadingZerosI src)); 9895 effect(TEMP dst, TEMP tmp, KILL cr); 9896 9897 // x |= (x >> 1); 9898 // x |= (x >> 2); 9899 // x |= (x >> 4); 9900 // x |= (x >> 8); 9901 // x |= (x >> 16); 9902 // return (WORDBITS - popc(x)); 9903 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 9904 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 9905 "OR $dst,$tmp,$dst\n\t" 9906 "SRL $dst,2,$tmp\n\t" 9907 "OR $dst,$tmp,$dst\n\t" 9908 "SRL $dst,4,$tmp\n\t" 9909 "OR $dst,$tmp,$dst\n\t" 9910 "SRL $dst,8,$tmp\n\t" 9911 "OR $dst,$tmp,$dst\n\t" 9912 "SRL $dst,16,$tmp\n\t" 9913 "OR $dst,$tmp,$dst\n\t" 9914 "POPC $dst,$dst\n\t" 9915 "MOV 32,$tmp\n\t" 9916 "SUB $tmp,$dst,$dst" %} 9917 ins_encode %{ 9918 Register Rdst = $dst$$Register; 9919 Register Rsrc = $src$$Register; 9920 Register Rtmp = $tmp$$Register; 9921 __ srl(Rsrc, 1, Rtmp); 9922 __ srl(Rsrc, 0, Rdst); 9923 __ or3(Rdst, Rtmp, Rdst); 9924 __ srl(Rdst, 2, Rtmp); 9925 __ or3(Rdst, Rtmp, Rdst); 9926 __ srl(Rdst, 4, Rtmp); 9927 __ or3(Rdst, Rtmp, Rdst); 9928 __ srl(Rdst, 8, Rtmp); 9929 __ or3(Rdst, Rtmp, Rdst); 9930 __ srl(Rdst, 16, Rtmp); 9931 __ or3(Rdst, Rtmp, Rdst); 9932 __ popc(Rdst, Rdst); 9933 __ mov(BitsPerInt, Rtmp); 9934 __ sub(Rtmp, Rdst, Rdst); 9935 %} 9936 ins_pipe(ialu_reg); 9937 %} 9938 9939 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 9940 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9941 match(Set dst (CountLeadingZerosL src)); 9942 effect(TEMP dst, TEMP tmp, KILL cr); 9943 9944 // x |= (x >> 1); 9945 // x |= (x >> 2); 9946 // x |= (x >> 4); 9947 // x |= (x >> 8); 9948 // x |= (x >> 16); 9949 // x |= (x >> 32); 9950 // return (WORDBITS - popc(x)); 9951 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 9952 "OR $src,$tmp,$dst\n\t" 9953 "SRLX $dst,2,$tmp\n\t" 9954 "OR $dst,$tmp,$dst\n\t" 9955 "SRLX $dst,4,$tmp\n\t" 9956 "OR $dst,$tmp,$dst\n\t" 9957 "SRLX $dst,8,$tmp\n\t" 9958 "OR $dst,$tmp,$dst\n\t" 9959 "SRLX $dst,16,$tmp\n\t" 9960 "OR $dst,$tmp,$dst\n\t" 9961 "SRLX $dst,32,$tmp\n\t" 9962 "OR $dst,$tmp,$dst\n\t" 9963 "POPC $dst,$dst\n\t" 9964 "MOV 64,$tmp\n\t" 9965 "SUB $tmp,$dst,$dst" %} 9966 ins_encode %{ 9967 Register Rdst = $dst$$Register; 9968 Register Rsrc = $src$$Register; 9969 Register Rtmp = $tmp$$Register; 9970 __ srlx(Rsrc, 1, Rtmp); 9971 __ or3( Rsrc, Rtmp, Rdst); 9972 __ srlx(Rdst, 2, Rtmp); 9973 __ or3( Rdst, Rtmp, Rdst); 9974 __ srlx(Rdst, 4, Rtmp); 9975 __ or3( Rdst, Rtmp, Rdst); 9976 __ srlx(Rdst, 8, Rtmp); 9977 __ or3( Rdst, Rtmp, Rdst); 9978 __ srlx(Rdst, 16, Rtmp); 9979 __ or3( Rdst, Rtmp, Rdst); 9980 __ srlx(Rdst, 32, Rtmp); 9981 __ or3( Rdst, Rtmp, Rdst); 9982 __ popc(Rdst, Rdst); 9983 __ mov(BitsPerLong, Rtmp); 9984 __ sub(Rtmp, Rdst, Rdst); 9985 %} 9986 ins_pipe(ialu_reg); 9987 %} 9988 9989 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ 9990 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9991 match(Set dst (CountTrailingZerosI src)); 9992 effect(TEMP dst, KILL cr); 9993 9994 // return popc(~x & (x - 1)); 9995 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 9996 "ANDN $dst,$src,$dst\n\t" 9997 "SRL $dst,R_G0,$dst\n\t" 9998 "POPC $dst,$dst" %} 9999 ins_encode %{ 10000 Register Rdst = $dst$$Register; 10001 Register Rsrc = $src$$Register; 10002 __ sub(Rsrc, 1, Rdst); 10003 __ andn(Rdst, Rsrc, Rdst); 10004 __ srl(Rdst, G0, Rdst); 10005 __ popc(Rdst, Rdst); 10006 %} 10007 ins_pipe(ialu_reg); 10008 %} 10009 10010 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ 10011 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10012 match(Set dst (CountTrailingZerosL src)); 10013 effect(TEMP dst, KILL cr); 10014 10015 // return popc(~x & (x - 1)); 10016 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10017 "ANDN $dst,$src,$dst\n\t" 10018 "POPC $dst,$dst" %} 10019 ins_encode %{ 10020 Register Rdst = $dst$$Register; 10021 Register Rsrc = $src$$Register; 10022 __ sub(Rsrc, 1, Rdst); 10023 __ andn(Rdst, Rsrc, Rdst); 10024 __ popc(Rdst, Rdst); 10025 %} 10026 ins_pipe(ialu_reg); 10027 %} 10028 10029 10030 //---------- Population Count Instructions ------------------------------------- 10031 10032 instruct popCountI(iRegIsafe dst, iRegI src) %{ 10033 predicate(UsePopCountInstruction); 10034 match(Set dst (PopCountI src)); 10035 10036 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" 10037 "POPC $dst, $dst" %} 10038 ins_encode %{ 10039 __ srl($src$$Register, G0, $dst$$Register); 10040 __ popc($dst$$Register, $dst$$Register); 10041 %} 10042 ins_pipe(ialu_reg); 10043 %} 10044 10045 // Note: Long.bitCount(long) returns an int. 10046 instruct popCountL(iRegIsafe dst, iRegL src) %{ 10047 predicate(UsePopCountInstruction); 10048 match(Set dst (PopCountL src)); 10049 10050 format %{ "POPC $src, $dst" %} 10051 ins_encode %{ 10052 __ popc($src$$Register, $dst$$Register); 10053 %} 10054 ins_pipe(ialu_reg); 10055 %} 10056 10057 10058 // ============================================================================ 10059 //------------Bytes reverse-------------------------------------------------- 10060 10061 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10062 match(Set dst (ReverseBytesI src)); 10063 10064 // Op cost is artificially doubled to make sure that load or store 10065 // instructions are preferred over this one which requires a spill 10066 // onto a stack slot. 10067 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10068 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10069 10070 ins_encode %{ 10071 __ set($src$$disp + STACK_BIAS, O7); 10072 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10073 %} 10074 ins_pipe( iload_mem ); 10075 %} 10076 10077 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10078 match(Set dst (ReverseBytesL src)); 10079 10080 // Op cost is artificially doubled to make sure that load or store 10081 // instructions are preferred over this one which requires a spill 10082 // onto a stack slot. 10083 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10084 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10085 10086 ins_encode %{ 10087 __ set($src$$disp + STACK_BIAS, O7); 10088 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10089 %} 10090 ins_pipe( iload_mem ); 10091 %} 10092 10093 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10094 match(Set dst (ReverseBytesUS src)); 10095 10096 // Op cost is artificially doubled to make sure that load or store 10097 // instructions are preferred over this one which requires a spill 10098 // onto a stack slot. 10099 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10100 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10101 10102 ins_encode %{ 10103 // the value was spilled as an int so bias the load 10104 __ set($src$$disp + STACK_BIAS + 2, O7); 10105 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10106 %} 10107 ins_pipe( iload_mem ); 10108 %} 10109 10110 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10111 match(Set dst (ReverseBytesS src)); 10112 10113 // Op cost is artificially doubled to make sure that load or store 10114 // instructions are preferred over this one which requires a spill 10115 // onto a stack slot. 10116 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10117 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10118 10119 ins_encode %{ 10120 // the value was spilled as an int so bias the load 10121 __ set($src$$disp + STACK_BIAS + 2, O7); 10122 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10123 %} 10124 ins_pipe( iload_mem ); 10125 %} 10126 10127 // Load Integer reversed byte order 10128 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10129 match(Set dst (ReverseBytesI (LoadI src))); 10130 10131 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10132 size(4); 10133 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10134 10135 ins_encode %{ 10136 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10137 %} 10138 ins_pipe(iload_mem); 10139 %} 10140 10141 // Load Long - aligned and reversed 10142 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10143 match(Set dst (ReverseBytesL (LoadL src))); 10144 10145 ins_cost(MEMORY_REF_COST); 10146 size(4); 10147 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10148 10149 ins_encode %{ 10150 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10151 %} 10152 ins_pipe(iload_mem); 10153 %} 10154 10155 // Load unsigned short / char reversed byte order 10156 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10157 match(Set dst (ReverseBytesUS (LoadUS src))); 10158 10159 ins_cost(MEMORY_REF_COST); 10160 size(4); 10161 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10162 10163 ins_encode %{ 10164 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10165 %} 10166 ins_pipe(iload_mem); 10167 %} 10168 10169 // Load short reversed byte order 10170 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10171 match(Set dst (ReverseBytesS (LoadS src))); 10172 10173 ins_cost(MEMORY_REF_COST); 10174 size(4); 10175 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10176 10177 ins_encode %{ 10178 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10179 %} 10180 ins_pipe(iload_mem); 10181 %} 10182 10183 // Store Integer reversed byte order 10184 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10185 match(Set dst (StoreI dst (ReverseBytesI src))); 10186 10187 ins_cost(MEMORY_REF_COST); 10188 size(4); 10189 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10190 10191 ins_encode %{ 10192 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10193 %} 10194 ins_pipe(istore_mem_reg); 10195 %} 10196 10197 // Store Long reversed byte order 10198 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10199 match(Set dst (StoreL dst (ReverseBytesL src))); 10200 10201 ins_cost(MEMORY_REF_COST); 10202 size(4); 10203 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10204 10205 ins_encode %{ 10206 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10207 %} 10208 ins_pipe(istore_mem_reg); 10209 %} 10210 10211 // Store unsighed short/char reversed byte order 10212 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10213 match(Set dst (StoreC dst (ReverseBytesUS src))); 10214 10215 ins_cost(MEMORY_REF_COST); 10216 size(4); 10217 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10218 10219 ins_encode %{ 10220 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10221 %} 10222 ins_pipe(istore_mem_reg); 10223 %} 10224 10225 // Store short reversed byte order 10226 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10227 match(Set dst (StoreC dst (ReverseBytesS src))); 10228 10229 ins_cost(MEMORY_REF_COST); 10230 size(4); 10231 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10232 10233 ins_encode %{ 10234 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10235 %} 10236 ins_pipe(istore_mem_reg); 10237 %} 10238 10239 // ====================VECTOR INSTRUCTIONS===================================== 10240 10241 // Load Aligned Packed values into a Double Register 10242 instruct loadV8(regD dst, memory mem) %{ 10243 predicate(n->as_LoadVector()->memory_size() == 8); 10244 match(Set dst (LoadVector mem)); 10245 ins_cost(MEMORY_REF_COST); 10246 size(4); 10247 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} 10248 ins_encode %{ 10249 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); 10250 %} 10251 ins_pipe(floadD_mem); 10252 %} 10253 10254 // Store Vector in Double register to memory 10255 instruct storeV8(memory mem, regD src) %{ 10256 predicate(n->as_StoreVector()->memory_size() == 8); 10257 match(Set mem (StoreVector mem src)); 10258 ins_cost(MEMORY_REF_COST); 10259 size(4); 10260 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} 10261 ins_encode %{ 10262 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); 10263 %} 10264 ins_pipe(fstoreD_mem_reg); 10265 %} 10266 10267 // Store Zero into vector in memory 10268 instruct storeV8B_zero(memory mem, immI0 zero) %{ 10269 predicate(n->as_StoreVector()->memory_size() == 8); 10270 match(Set mem (StoreVector mem (ReplicateB zero))); 10271 ins_cost(MEMORY_REF_COST); 10272 size(4); 10273 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} 10274 ins_encode %{ 10275 __ stx(G0, $mem$$Address); 10276 %} 10277 ins_pipe(fstoreD_mem_zero); 10278 %} 10279 10280 instruct storeV4S_zero(memory mem, immI0 zero) %{ 10281 predicate(n->as_StoreVector()->memory_size() == 8); 10282 match(Set mem (StoreVector mem (ReplicateS zero))); 10283 ins_cost(MEMORY_REF_COST); 10284 size(4); 10285 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} 10286 ins_encode %{ 10287 __ stx(G0, $mem$$Address); 10288 %} 10289 ins_pipe(fstoreD_mem_zero); 10290 %} 10291 10292 instruct storeV2I_zero(memory mem, immI0 zero) %{ 10293 predicate(n->as_StoreVector()->memory_size() == 8); 10294 match(Set mem (StoreVector mem (ReplicateI zero))); 10295 ins_cost(MEMORY_REF_COST); 10296 size(4); 10297 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} 10298 ins_encode %{ 10299 __ stx(G0, $mem$$Address); 10300 %} 10301 ins_pipe(fstoreD_mem_zero); 10302 %} 10303 10304 instruct storeV2F_zero(memory mem, immF0 zero) %{ 10305 predicate(n->as_StoreVector()->memory_size() == 8); 10306 match(Set mem (StoreVector mem (ReplicateF zero))); 10307 ins_cost(MEMORY_REF_COST); 10308 size(4); 10309 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} 10310 ins_encode %{ 10311 __ stx(G0, $mem$$Address); 10312 %} 10313 ins_pipe(fstoreD_mem_zero); 10314 %} 10315 10316 // Replicate scalar to packed byte values into Double register 10317 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10318 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); 10319 match(Set dst (ReplicateB src)); 10320 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10321 format %{ "SLLX $src,56,$tmp\n\t" 10322 "SRLX $tmp, 8,$tmp2\n\t" 10323 "OR $tmp,$tmp2,$tmp\n\t" 10324 "SRLX $tmp,16,$tmp2\n\t" 10325 "OR $tmp,$tmp2,$tmp\n\t" 10326 "SRLX $tmp,32,$tmp2\n\t" 10327 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10328 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10329 ins_encode %{ 10330 Register Rsrc = $src$$Register; 10331 Register Rtmp = $tmp$$Register; 10332 Register Rtmp2 = $tmp2$$Register; 10333 __ sllx(Rsrc, 56, Rtmp); 10334 __ srlx(Rtmp, 8, Rtmp2); 10335 __ or3 (Rtmp, Rtmp2, Rtmp); 10336 __ srlx(Rtmp, 16, Rtmp2); 10337 __ or3 (Rtmp, Rtmp2, Rtmp); 10338 __ srlx(Rtmp, 32, Rtmp2); 10339 __ or3 (Rtmp, Rtmp2, Rtmp); 10340 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10341 %} 10342 ins_pipe(ialu_reg); 10343 %} 10344 10345 // Replicate scalar to packed byte values into Double stack 10346 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10347 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); 10348 match(Set dst (ReplicateB src)); 10349 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10350 format %{ "SLLX $src,56,$tmp\n\t" 10351 "SRLX $tmp, 8,$tmp2\n\t" 10352 "OR $tmp,$tmp2,$tmp\n\t" 10353 "SRLX $tmp,16,$tmp2\n\t" 10354 "OR $tmp,$tmp2,$tmp\n\t" 10355 "SRLX $tmp,32,$tmp2\n\t" 10356 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10357 "STX $tmp,$dst\t! regL to stkD" %} 10358 ins_encode %{ 10359 Register Rsrc = $src$$Register; 10360 Register Rtmp = $tmp$$Register; 10361 Register Rtmp2 = $tmp2$$Register; 10362 __ sllx(Rsrc, 56, Rtmp); 10363 __ srlx(Rtmp, 8, Rtmp2); 10364 __ or3 (Rtmp, Rtmp2, Rtmp); 10365 __ srlx(Rtmp, 16, Rtmp2); 10366 __ or3 (Rtmp, Rtmp2, Rtmp); 10367 __ srlx(Rtmp, 32, Rtmp2); 10368 __ or3 (Rtmp, Rtmp2, Rtmp); 10369 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10370 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10371 %} 10372 ins_pipe(ialu_reg); 10373 %} 10374 10375 // Replicate scalar constant to packed byte values in Double register 10376 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 10377 predicate(n->as_Vector()->length() == 8); 10378 match(Set dst (ReplicateB con)); 10379 effect(KILL tmp); 10380 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 10381 ins_encode %{ 10382 // XXX This is a quick fix for 6833573. 10383 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 10384 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 10385 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10386 %} 10387 ins_pipe(loadConFD); 10388 %} 10389 10390 // Replicate scalar to packed char/short values into Double register 10391 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10392 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); 10393 match(Set dst (ReplicateS src)); 10394 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10395 format %{ "SLLX $src,48,$tmp\n\t" 10396 "SRLX $tmp,16,$tmp2\n\t" 10397 "OR $tmp,$tmp2,$tmp\n\t" 10398 "SRLX $tmp,32,$tmp2\n\t" 10399 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10400 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10401 ins_encode %{ 10402 Register Rsrc = $src$$Register; 10403 Register Rtmp = $tmp$$Register; 10404 Register Rtmp2 = $tmp2$$Register; 10405 __ sllx(Rsrc, 48, Rtmp); 10406 __ srlx(Rtmp, 16, Rtmp2); 10407 __ or3 (Rtmp, Rtmp2, Rtmp); 10408 __ srlx(Rtmp, 32, Rtmp2); 10409 __ or3 (Rtmp, Rtmp2, Rtmp); 10410 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10411 %} 10412 ins_pipe(ialu_reg); 10413 %} 10414 10415 // Replicate scalar to packed char/short values into Double stack 10416 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10417 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); 10418 match(Set dst (ReplicateS src)); 10419 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10420 format %{ "SLLX $src,48,$tmp\n\t" 10421 "SRLX $tmp,16,$tmp2\n\t" 10422 "OR $tmp,$tmp2,$tmp\n\t" 10423 "SRLX $tmp,32,$tmp2\n\t" 10424 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10425 "STX $tmp,$dst\t! regL to stkD" %} 10426 ins_encode %{ 10427 Register Rsrc = $src$$Register; 10428 Register Rtmp = $tmp$$Register; 10429 Register Rtmp2 = $tmp2$$Register; 10430 __ sllx(Rsrc, 48, Rtmp); 10431 __ srlx(Rtmp, 16, Rtmp2); 10432 __ or3 (Rtmp, Rtmp2, Rtmp); 10433 __ srlx(Rtmp, 32, Rtmp2); 10434 __ or3 (Rtmp, Rtmp2, Rtmp); 10435 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10436 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10437 %} 10438 ins_pipe(ialu_reg); 10439 %} 10440 10441 // Replicate scalar constant to packed char/short values in Double register 10442 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 10443 predicate(n->as_Vector()->length() == 4); 10444 match(Set dst (ReplicateS con)); 10445 effect(KILL tmp); 10446 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 10447 ins_encode %{ 10448 // XXX This is a quick fix for 6833573. 10449 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 10450 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 10451 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10452 %} 10453 ins_pipe(loadConFD); 10454 %} 10455 10456 // Replicate scalar to packed int values into Double register 10457 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10458 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); 10459 match(Set dst (ReplicateI src)); 10460 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10461 format %{ "SLLX $src,32,$tmp\n\t" 10462 "SRLX $tmp,32,$tmp2\n\t" 10463 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10464 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10465 ins_encode %{ 10466 Register Rsrc = $src$$Register; 10467 Register Rtmp = $tmp$$Register; 10468 Register Rtmp2 = $tmp2$$Register; 10469 __ sllx(Rsrc, 32, Rtmp); 10470 __ srlx(Rtmp, 32, Rtmp2); 10471 __ or3 (Rtmp, Rtmp2, Rtmp); 10472 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10473 %} 10474 ins_pipe(ialu_reg); 10475 %} 10476 10477 // Replicate scalar to packed int values into Double stack 10478 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10479 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); 10480 match(Set dst (ReplicateI src)); 10481 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10482 format %{ "SLLX $src,32,$tmp\n\t" 10483 "SRLX $tmp,32,$tmp2\n\t" 10484 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10485 "STX $tmp,$dst\t! regL to stkD" %} 10486 ins_encode %{ 10487 Register Rsrc = $src$$Register; 10488 Register Rtmp = $tmp$$Register; 10489 Register Rtmp2 = $tmp2$$Register; 10490 __ sllx(Rsrc, 32, Rtmp); 10491 __ srlx(Rtmp, 32, Rtmp2); 10492 __ or3 (Rtmp, Rtmp2, Rtmp); 10493 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10494 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10495 %} 10496 ins_pipe(ialu_reg); 10497 %} 10498 10499 // Replicate scalar zero constant to packed int values in Double register 10500 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 10501 predicate(n->as_Vector()->length() == 2); 10502 match(Set dst (ReplicateI con)); 10503 effect(KILL tmp); 10504 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 10505 ins_encode %{ 10506 // XXX This is a quick fix for 6833573. 10507 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 10508 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 10509 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10510 %} 10511 ins_pipe(loadConFD); 10512 %} 10513 10514 // Replicate scalar to packed float values into Double stack 10515 instruct Repl2F_stk(stackSlotD dst, regF src) %{ 10516 predicate(n->as_Vector()->length() == 2); 10517 match(Set dst (ReplicateF src)); 10518 ins_cost(MEMORY_REF_COST*2); 10519 format %{ "STF $src,$dst.hi\t! packed2F\n\t" 10520 "STF $src,$dst.lo" %} 10521 opcode(Assembler::stf_op3); 10522 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); 10523 ins_pipe(fstoreF_stk_reg); 10524 %} 10525 10526 // Replicate scalar zero constant to packed float values in Double register 10527 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ 10528 predicate(n->as_Vector()->length() == 2); 10529 match(Set dst (ReplicateF con)); 10530 effect(KILL tmp); 10531 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} 10532 ins_encode %{ 10533 // XXX This is a quick fix for 6833573. 10534 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); 10535 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); 10536 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10537 %} 10538 ins_pipe(loadConFD); 10539 %} 10540 10541 //----------PEEPHOLE RULES----------------------------------------------------- 10542 // These must follow all instruction definitions as they use the names 10543 // defined in the instructions definitions. 10544 // 10545 // peepmatch ( root_instr_name [preceding_instruction]* ); 10546 // 10547 // peepconstraint %{ 10548 // (instruction_number.operand_name relational_op instruction_number.operand_name 10549 // [, ...] ); 10550 // // instruction numbers are zero-based using left to right order in peepmatch 10551 // 10552 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 10553 // // provide an instruction_number.operand_name for each operand that appears 10554 // // in the replacement instruction's match rule 10555 // 10556 // ---------VM FLAGS--------------------------------------------------------- 10557 // 10558 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10559 // 10560 // Each peephole rule is given an identifying number starting with zero and 10561 // increasing by one in the order seen by the parser. An individual peephole 10562 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10563 // on the command-line. 10564 // 10565 // ---------CURRENT LIMITATIONS---------------------------------------------- 10566 // 10567 // Only match adjacent instructions in same basic block 10568 // Only equality constraints 10569 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10570 // Only one replacement instruction 10571 // 10572 // ---------EXAMPLE---------------------------------------------------------- 10573 // 10574 // // pertinent parts of existing instructions in architecture description 10575 // instruct movI(eRegI dst, eRegI src) %{ 10576 // match(Set dst (CopyI src)); 10577 // %} 10578 // 10579 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10580 // match(Set dst (AddI dst src)); 10581 // effect(KILL cr); 10582 // %} 10583 // 10584 // // Change (inc mov) to lea 10585 // peephole %{ 10586 // // increment preceeded by register-register move 10587 // peepmatch ( incI_eReg movI ); 10588 // // require that the destination register of the increment 10589 // // match the destination register of the move 10590 // peepconstraint ( 0.dst == 1.dst ); 10591 // // construct a replacement instruction that sets 10592 // // the destination to ( move's source register + one ) 10593 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 10594 // %} 10595 // 10596 10597 // // Change load of spilled value to only a spill 10598 // instruct storeI(memory mem, eRegI src) %{ 10599 // match(Set mem (StoreI mem src)); 10600 // %} 10601 // 10602 // instruct loadI(eRegI dst, memory mem) %{ 10603 // match(Set dst (LoadI mem)); 10604 // %} 10605 // 10606 // peephole %{ 10607 // peepmatch ( loadI storeI ); 10608 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 10609 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 10610 // %} 10611 10612 //----------SMARTSPILL RULES--------------------------------------------------- 10613 // These must follow all instruction definitions as they use the names 10614 // defined in the instructions definitions. 10615 // 10616 // SPARC will probably not have any of these rules due to RISC instruction set. 10617 10618 //----------PIPELINE----------------------------------------------------------- 10619 // Rules which define the behavior of the target architectures pipeline.