634 patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg);
635 relocate(rspec);
636 call(entry, relocInfo::none);
637 if (emit_delay) {
638 delayed()->nop();
639 }
640 }
641
642 void MacroAssembler::card_table_write(jbyte* byte_map_base,
643 Register tmp, Register obj) {
644 srlx(obj, CardTableModRefBS::card_shift, obj);
645 assert(tmp != obj, "need separate temp reg");
646 set((address) byte_map_base, tmp);
647 stb(G0, tmp, obj);
648 }
649
650
651 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
652 address save_pc;
653 int shiftcnt;
654 # ifdef CHECK_DELAY
655 assert_not_delayed((char*) "cannot put two instructions in delay slot");
656 # endif
657 v9_dep();
658 save_pc = pc();
659
660 int msb32 = (int) (addrlit.value() >> 32);
661 int lsb32 = (int) (addrlit.value());
662
663 if (msb32 == 0 && lsb32 >= 0) {
664 Assembler::sethi(lsb32, d, addrlit.rspec());
665 }
666 else if (msb32 == -1) {
667 Assembler::sethi(~lsb32, d, addrlit.rspec());
668 xor3(d, ~low10(~0), d);
669 }
670 else {
671 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
672 if (msb32 & 0x3ff) // Any bits?
673 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
674 if (lsb32 & 0xFFFFFC00) { // done?
675 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
676 sllx(d, 12, d); // Make room for next 12 bits
735 int MacroAssembler::worst_case_insts_for_set() {
736 return insts_for_sethi(NULL, true) + 1;
737 }
738
739
740 // Keep in sync with MacroAssembler::insts_for_internal_set
741 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
742 intptr_t value = addrlit.value();
743
744 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
745 // can optimize
746 if (-4096 <= value && value <= 4095) {
747 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
748 return;
749 }
750 if (inv_hi22(hi22(value)) == value) {
751 sethi(addrlit, d);
752 return;
753 }
754 }
755 assert_not_delayed((char*) "cannot put two instructions in delay slot");
756 internal_sethi(addrlit, d, ForceRelocatable);
757 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
758 add(d, addrlit.low10(), d, addrlit.rspec());
759 }
760 }
761
762 // Keep in sync with MacroAssembler::internal_set
763 int MacroAssembler::insts_for_internal_set(intptr_t value) {
764 // can optimize
765 if (-4096 <= value && value <= 4095) {
766 return 1;
767 }
768 if (inv_hi22(hi22(value)) == value) {
769 return insts_for_sethi((address) value);
770 }
771 int count = insts_for_sethi((address) value);
772 AddressLiteral al(value);
773 if (al.low10() != 0) {
774 count++;
775 }
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634 patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg);
635 relocate(rspec);
636 call(entry, relocInfo::none);
637 if (emit_delay) {
638 delayed()->nop();
639 }
640 }
641
642 void MacroAssembler::card_table_write(jbyte* byte_map_base,
643 Register tmp, Register obj) {
644 srlx(obj, CardTableModRefBS::card_shift, obj);
645 assert(tmp != obj, "need separate temp reg");
646 set((address) byte_map_base, tmp);
647 stb(G0, tmp, obj);
648 }
649
650
651 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
652 address save_pc;
653 int shiftcnt;
654 #ifdef VALIDATE_PIPELINE
655 assert_no_delay("Cannot put two instructions in delay-slot.");
656 #endif
657 v9_dep();
658 save_pc = pc();
659
660 int msb32 = (int) (addrlit.value() >> 32);
661 int lsb32 = (int) (addrlit.value());
662
663 if (msb32 == 0 && lsb32 >= 0) {
664 Assembler::sethi(lsb32, d, addrlit.rspec());
665 }
666 else if (msb32 == -1) {
667 Assembler::sethi(~lsb32, d, addrlit.rspec());
668 xor3(d, ~low10(~0), d);
669 }
670 else {
671 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
672 if (msb32 & 0x3ff) // Any bits?
673 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
674 if (lsb32 & 0xFFFFFC00) { // done?
675 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
676 sllx(d, 12, d); // Make room for next 12 bits
735 int MacroAssembler::worst_case_insts_for_set() {
736 return insts_for_sethi(NULL, true) + 1;
737 }
738
739
740 // Keep in sync with MacroAssembler::insts_for_internal_set
741 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
742 intptr_t value = addrlit.value();
743
744 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
745 // can optimize
746 if (-4096 <= value && value <= 4095) {
747 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
748 return;
749 }
750 if (inv_hi22(hi22(value)) == value) {
751 sethi(addrlit, d);
752 return;
753 }
754 }
755 assert_no_delay("Cannot put two instructions in delay-slot.");
756 internal_sethi(addrlit, d, ForceRelocatable);
757 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
758 add(d, addrlit.low10(), d, addrlit.rspec());
759 }
760 }
761
762 // Keep in sync with MacroAssembler::internal_set
763 int MacroAssembler::insts_for_internal_set(intptr_t value) {
764 // can optimize
765 if (-4096 <= value && value <= 4095) {
766 return 1;
767 }
768 if (inv_hi22(hi22(value)) == value) {
769 return insts_for_sethi((address) value);
770 }
771 int count = insts_for_sethi((address) value);
772 AddressLiteral al(value);
773 if (al.low10() != 0) {
774 count++;
775 }
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