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src/cpu/sparc/vm/assembler_sparc.hpp

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 448   static int predict(bool p)     { return u_field(p ? 1 : 0,     19, 19); }
 449   static int branchcc(CC fcca)   { return u_field(fcca,          21, 20); }
 450   static int cmpcc(CC fcca)      { return u_field(fcca,          26, 25); }
 451   static int imm_asi(int x)      { return u_field(x,             12,  5); }
 452   static int immed(bool i)       { return u_field(i ? 1 : 0,     13, 13); }
 453   static int opf_low6(int w)     { return u_field(w,             10,  5); }
 454   static int opf_low5(int w)     { return u_field(w,              9,  5); }
 455   static int op5(int x)          { return u_field(x,              8,  5); }
 456   static int trapcc(CC cc)       { return u_field(cc,            12, 11); }
 457   static int sx(int i)           { return u_field(i,             12, 12); } // shift x=1 means 64-bit
 458   static int opf(int x)          { return u_field(x,             13,  5); }
 459 
 460   static bool is_cbcond(int x) {
 461     return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
 462             inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
 463   }
 464   static bool is_cxb(int x) {
 465     assert(is_cbcond(x), "wrong instruction");
 466     return (x & (1 << 21)) != 0;
 467   }






























 468   static int cond_cbcond(int x) { return  u_field((((x & 8) << 1) + 8 + (x & 7)), 29, 25); }
 469   static int inv_cond_cbcond(int x) {
 470     assert(is_cbcond(x), "wrong instruction");
 471     return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29) << 3);
 472   }
 473 
 474   static int opf_cc(CC c, bool useFloat) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
 475   static int mov_cc(CC c, bool useFloat) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
 476 
 477   static int fd(FloatRegister r, FloatRegisterImpl::Width fwa)  { return u_field(r->encoding(fwa), 29, 25); };
 478   static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
 479   static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
 480   static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13,  9); };
 481 
 482   // some float instructions use this encoding on the op3 field
 483   static int alt_op3(int op, FloatRegisterImpl::Width w) {
 484     int r;
 485     switch(w) {
 486      case FloatRegisterImpl::S: r = op + 0;  break;
 487      case FloatRegisterImpl::D: r = op + 3;  break;


 594   static void sha1_only()   { assert(VM_Version::has_sha1(),   "This instruction only works on SPARC with SHA1"); }
 595   static void sha256_only() { assert(VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
 596   static void sha512_only() { assert(VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
 597 
 598   // CRC32C instruction supported only on certain processors
 599   static void crc32c_only() { assert(VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
 600 
 601   // instruction only in VIS1
 602   static void vis1_only() { assert(VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
 603 
 604   // instruction only in VIS2
 605   static void vis2_only() { assert(VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
 606 
 607   // instruction only in VIS3
 608   static void vis3_only() { assert(VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
 609 
 610   // instruction deprecated in v9
 611   static void v9_dep() { } // do nothing for now
 612 
 613  protected:
 614   // Simple delay-slot scheme:
 615   // In order to check the programmer, the assembler keeps track of delay slots.
 616   // It forbids CTIs in delay slots (conservative, but should be OK).
 617   // Also, when putting an instruction into a delay slot, you must say
 618   // asm->delayed()->add(...), in order to check that you don't omit
 619   // delay-slot instructions.
 620   // To implement this, we use a simple FSA
 621 
 622 #ifdef ASSERT
 623   #define CHECK_DELAY
 624 #endif
 625 #ifdef CHECK_DELAY
 626   enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;














 627 #endif
 628 
 629  public:
 630   // Tells assembler next instruction must NOT be in delay slot.
 631   // Use at start of multinstruction macros.
 632   void assert_not_delayed() {
 633     // This is a separate overloading to avoid creation of string constants
 634     // in non-asserted code--with some compilers this pollutes the object code.
 635 #ifdef CHECK_DELAY
 636     assert_not_delayed("next instruction should not be a delay slot");
 637 #endif
 638   }
 639   void assert_not_delayed(const char* msg) {
 640 #ifdef CHECK_DELAY
 641     assert(delay_state == no_delay, msg);


 642 #endif
 643   }
 644 

















 645  protected:
 646   // Insert a nop if the previous is cbcond
 647   inline void insert_nop_after_cbcond();

 648 
 649   // Delay slot helpers
 650   // cti is called when emitting control-transfer instruction,
 651   // BEFORE doing the emitting.
 652   // Only effective when assertion-checking is enabled.
 653   void cti() {
 654     // A cbcond instruction immediately followed by a CTI
 655     // instruction introduces pipeline stalls, we need to avoid that.
 656     no_cbcond_before();
 657 #ifdef CHECK_DELAY
 658     assert_not_delayed("cti should not be in delay slot");


 659 #endif
 660   }
 661 
 662   // called when emitting cti with a delay slot, AFTER emitting
 663   void has_delay_slot() {
 664 #ifdef CHECK_DELAY
 665     assert_not_delayed("just checking");
 666     delay_state = at_delay_slot;
 667 #endif
 668   }
 669 
 670   // cbcond instruction should not be generated one after an other
 671   bool cbcond_before() {
 672     if (offset() == 0) return false; // it is first instruction
 673     int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
 674     return is_cbcond(x);
 675   }
 676 
 677   void no_cbcond_before() {
 678     assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");




 679   }
 680 public:
 681 






 682   bool use_cbcond(Label &L) {
 683     if (!UseCBCond || cbcond_before()) return false;
 684     intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
 685     assert((x & 3) == 0, "not word aligned");
 686     return is_simm12(x);
 687   }
 688 
 689   // Tells assembler you know that next instruction is delayed
 690   Assembler* delayed() {
 691 #ifdef CHECK_DELAY
 692     assert(delay_state == at_delay_slot, "delayed instruction is not in delay slot");
 693     delay_state = filling_delay_slot;
 694 #endif
 695     return this;
 696   }
 697 
 698   void flush() {
 699 #ifdef CHECK_DELAY
 700     assert(delay_state == no_delay, "ending code with a delay slot");

 701 #endif
 702     AbstractAssembler::flush();
 703   }
 704 
 705   inline void emit_int32(int);  // shadows AbstractAssembler::emit_int32
 706   inline void emit_data(int);
 707   inline void emit_data(int, RelocationHolder const &rspec);
 708   inline void emit_data(int, relocInfo::relocType rtype);
 709   // helper for above functions
 710   inline void check_delay();
 711 
 712 
 713  public:
 714   // instructions, refer to page numbers in the SPARC Architecture Manual, V9
 715 
 716   // pp 135
 717 
 718   inline void add(Register s1, Register s2, Register d);
 719   inline void add(Register s1, int simm13a, Register d);
 720 


1198   inline void movdtox(FloatRegister s, Register d);
1199 
1200   inline void movwtos(Register s, FloatRegister d);
1201   inline void movxtod(Register s, FloatRegister d);
1202 
1203   inline void xmulx(Register s1, Register s2, Register d);
1204   inline void xmulxhi(Register s1, Register s2, Register d);
1205 
1206   // Crypto SHA instructions
1207 
1208   inline void sha1();
1209   inline void sha256();
1210   inline void sha512();
1211 
1212   // CRC32C instruction
1213 
1214   inline void crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d);
1215 
1216   // Creation
1217   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1218 #ifdef CHECK_DELAY
1219     delay_state = no_delay;

1220 #endif
1221   }
1222 };
1223 
1224 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP


 448   static int predict(bool p)     { return u_field(p ? 1 : 0,     19, 19); }
 449   static int branchcc(CC fcca)   { return u_field(fcca,          21, 20); }
 450   static int cmpcc(CC fcca)      { return u_field(fcca,          26, 25); }
 451   static int imm_asi(int x)      { return u_field(x,             12,  5); }
 452   static int immed(bool i)       { return u_field(i ? 1 : 0,     13, 13); }
 453   static int opf_low6(int w)     { return u_field(w,             10,  5); }
 454   static int opf_low5(int w)     { return u_field(w,              9,  5); }
 455   static int op5(int x)          { return u_field(x,              8,  5); }
 456   static int trapcc(CC cc)       { return u_field(cc,            12, 11); }
 457   static int sx(int i)           { return u_field(i,             12, 12); } // shift x=1 means 64-bit
 458   static int opf(int x)          { return u_field(x,             13,  5); }
 459 
 460   static bool is_cbcond(int x) {
 461     return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
 462             inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
 463   }
 464   static bool is_cxb(int x) {
 465     assert(is_cbcond(x), "wrong instruction");
 466     return (x & (1 << 21)) != 0;
 467   }
 468   static bool is_branch(int x) {
 469     if (inv_op(x) != Assembler::branch_op) return false;
 470 
 471     bool is_bpr = inv_op2(x) == Assembler::bpr_op2;
 472     bool is_bp  = inv_op2(x) == Assembler::bp_op2;
 473     bool is_br  = inv_op2(x) == Assembler::br_op2;
 474     bool is_fp  = inv_op2(x) == Assembler::fb_op2;
 475     bool is_fbp = inv_op2(x) == Assembler::fbp_op2;
 476 
 477     return is_bpr || is_bp || is_br || is_fp || is_fbp;
 478   }
 479   static bool is_call(int x) {
 480     return inv_op(x) == Assembler::call_op;
 481   }
 482   static bool is_jump(int x) {
 483     if (inv_op(x) != Assembler::arith_op) return false;
 484 
 485     bool is_jmpl = inv_op3(x) == Assembler::jmpl_op3;
 486     bool is_rett = inv_op3(x) == Assembler::rett_op3;
 487 
 488     return is_jmpl || is_rett;
 489   }
 490   static bool is_rdpc(int x) {
 491     return (inv_op(x) == Assembler::arith_op && inv_op3(x) == Assembler::rdreg_op3 &&
 492             inv_u_field(x, 18, 14) == 5);
 493   }
 494   static bool is_cti(int x) {
 495       return is_branch(x) || is_call(x) || is_jump(x); // Ignoring done/retry
 496   }
 497 
 498   static int cond_cbcond(int x) { return  u_field((((x & 8) << 1) + 8 + (x & 7)), 29, 25); }
 499   static int inv_cond_cbcond(int x) {
 500     assert(is_cbcond(x), "wrong instruction");
 501     return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29) << 3);
 502   }
 503 
 504   static int opf_cc(CC c, bool useFloat) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
 505   static int mov_cc(CC c, bool useFloat) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
 506 
 507   static int fd(FloatRegister r, FloatRegisterImpl::Width fwa)  { return u_field(r->encoding(fwa), 29, 25); };
 508   static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
 509   static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
 510   static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13,  9); };
 511 
 512   // some float instructions use this encoding on the op3 field
 513   static int alt_op3(int op, FloatRegisterImpl::Width w) {
 514     int r;
 515     switch(w) {
 516      case FloatRegisterImpl::S: r = op + 0;  break;
 517      case FloatRegisterImpl::D: r = op + 3;  break;


 624   static void sha1_only()   { assert(VM_Version::has_sha1(),   "This instruction only works on SPARC with SHA1"); }
 625   static void sha256_only() { assert(VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
 626   static void sha512_only() { assert(VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
 627 
 628   // CRC32C instruction supported only on certain processors
 629   static void crc32c_only() { assert(VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
 630 
 631   // instruction only in VIS1
 632   static void vis1_only() { assert(VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
 633 
 634   // instruction only in VIS2
 635   static void vis2_only() { assert(VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
 636 
 637   // instruction only in VIS3
 638   static void vis3_only() { assert(VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
 639 
 640   // instruction deprecated in v9
 641   static void v9_dep() { } // do nothing for now
 642 
 643  protected:








 644 #ifdef ASSERT
 645 #define VALIDATE_PIPELINE
 646 #endif
 647 
 648 #ifdef VALIDATE_PIPELINE
 649   // A simple delay-slot scheme:
 650   // In order to check the programmer, the assembler keeps track of delay-slots.
 651   // It forbids CTIs in delay-slots (conservative, but should be OK). Also, when
 652   // emitting an instruction into a delay-slot, you must do so using delayed(),
 653   // e.g. asm->delayed()->add(...), in order to check that you do not omit the
 654   // delay-slot instruction. To implement this, we use a simple FSA.
 655   enum { NoDelay, AtDelay, FillDelay } _delay_state;
 656 
 657   // A simple hazard scheme:
 658   // In order to avoid pipeline stalls, due to single cycle pipeline hazards, we
 659   // adopt a simplistic state tracking mechanism that will enforce an additional
 660   // 'nop' instruction to be inserted prior to emitting an instruction that can
 661   // expose a given hazard (currently, PC-related hazards only).
 662   enum { NoHazard, PcHazard } _hazard_state;
 663 #endif
 664 
 665  public:
 666   // Tell the assembler that the next instruction must NOT be in delay-slot.
 667   // Use at start of multi-instruction macros.
 668   void assert_not_delayed() {
 669     // This is a separate entry to avoid the creation of string constants in
 670     // non-asserted code, with some compilers this pollutes the object code.
 671 #ifdef VALIDATE_PIPELINE
 672     assert_no_delay("Next instruction should not be in a delay-slot.");
 673 #endif
 674   }
 675 
 676  protected:
 677   void assert_no_delay(const char* msg) {
 678 #ifdef VALIDATE_PIPELINE
 679     assert(_delay_state == NoDelay, msg);
 680 #endif
 681   }
 682 
 683   void assert_no_hazard() {
 684 #ifdef VALIDATE_PIPELINE
 685     assert(_hazard_state == NoHazard, "Unsolicited pipeline hazard.");
 686 #endif
 687   }
 688 
 689  private:
 690   inline int32_t prev_insn() {
 691     assert(offset() > 0, "Interface violation.");
 692     int32_t* addr = (int32_t*)pc() - 1;
 693     return *addr;
 694   }
 695 
 696 #ifdef VALIDATE_PIPELINE
 697   void validate_no_pipeline_hazards();
 698 #endif
 699 
 700  protected:
 701   // Avoid possible pipeline stall by inserting an additional 'nop' instruction,
 702   // if the previous instruction is a 'cbcond' or a 'rdpc'.
 703   inline void avoid_pipeline_stall();
 704 
 705   // A call to cti() is made before emitting a control-transfer instruction (CTI)
 706   // in order to assert a CTI is not emitted right after a 'cbcond', nor in the
 707   // delay-slot of another CTI. Only effective when assertions are enabled.

 708   void cti() {
 709     // A 'cbcond' or 'rdpc' instruction immediately followed by a CTI introduces
 710     // a pipeline stall, which we make sure to prohibit.
 711     assert_no_cbcond_before();
 712     assert_no_rdpc_before();
 713 #ifdef VALIDATE_PIPELINE
 714     assert_no_hazard();
 715     assert_no_delay("CTI in delay-slot.");
 716 #endif
 717   }
 718 
 719   // Called when emitting CTI with a delay-slot, AFTER emitting.
 720   inline void induce_delay_slot() {
 721 #ifdef VALIDATE_PIPELINE
 722     assert_no_delay("Already in delay-slot.");
 723     _delay_state = AtDelay;
 724 #endif
 725   }
 726 
 727   inline void induce_pc_hazard() {
 728 #ifdef VALIDATE_PIPELINE
 729     assert_no_hazard();
 730     _hazard_state = PcHazard;
 731 #endif
 732   }
 733 
 734   bool is_cbcond_before() { return offset() > 0 ? is_cbcond(prev_insn()) : false; }
 735 
 736   bool is_rdpc_before() { return offset() > 0 ? is_rdpc(prev_insn()) : false; }
 737 
 738   void assert_no_cbcond_before() {
 739     assert(offset() == 0 || !is_cbcond_before(), "CBCOND should not be followed by CTI.");
 740   }

 741 
 742   void assert_no_rdpc_before() {
 743     assert(offset() == 0 || !is_rdpc_before(), "RDPC should not be followed by CTI.");
 744   }
 745 
 746  public:
 747 
 748   bool use_cbcond(Label &L) {
 749     if (!UseCBCond || is_cbcond_before()) return false;
 750     intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
 751     assert((x & 3) == 0, "not word aligned");
 752     return is_simm12(x);
 753   }
 754 
 755   // Tells assembler you know that next instruction is delayed
 756   Assembler* delayed() {
 757 #ifdef VALIDATE_PIPELINE
 758     assert(_delay_state == AtDelay, "Delayed instruction not in delay-slot.");
 759     _delay_state = FillDelay;
 760 #endif
 761     return this;
 762   }
 763 
 764   void flush() {
 765 #ifdef VALIDATE_PIPELINE
 766     assert(_delay_state == NoDelay, "Ending code with a delay-slot.");
 767     validate_no_pipeline_hazards();
 768 #endif
 769     AbstractAssembler::flush();
 770   }
 771 
 772   inline void emit_int32(int);  // shadows AbstractAssembler::emit_int32
 773   inline void emit_data(int);
 774   inline void emit_data(int, RelocationHolder const &rspec);
 775   inline void emit_data(int, relocInfo::relocType rtype);
 776   // helper for above functions
 777   inline void check_delay();
 778 
 779 
 780  public:
 781   // instructions, refer to page numbers in the SPARC Architecture Manual, V9
 782 
 783   // pp 135
 784 
 785   inline void add(Register s1, Register s2, Register d);
 786   inline void add(Register s1, int simm13a, Register d);
 787 


1265   inline void movdtox(FloatRegister s, Register d);
1266 
1267   inline void movwtos(Register s, FloatRegister d);
1268   inline void movxtod(Register s, FloatRegister d);
1269 
1270   inline void xmulx(Register s1, Register s2, Register d);
1271   inline void xmulxhi(Register s1, Register s2, Register d);
1272 
1273   // Crypto SHA instructions
1274 
1275   inline void sha1();
1276   inline void sha256();
1277   inline void sha512();
1278 
1279   // CRC32C instruction
1280 
1281   inline void crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d);
1282 
1283   // Creation
1284   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1285 #ifdef VALIDATE_PIPELINE
1286     _delay_state  = NoDelay;
1287     _hazard_state = NoHazard;
1288 #endif
1289   }
1290 };
1291 
1292 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
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