50 nop_instruction_size = 4
51 };
52
53 bool is_nop() { return long_at(0) == nop_instruction(); }
54 bool is_call() { return is_op(long_at(0), Assembler::call_op); }
55 bool is_call_reg() { return is_op(long_at(0), Assembler::arith_op); }
56 bool is_sethi() { return (is_op2(long_at(0), Assembler::sethi_op2)
57 && inv_rd(long_at(0)) != G0); }
58
59 bool sets_cc() {
60 // conservative (returns true for some instructions that do not set the
61 // the condition code, such as, "save".
62 // Does not return true for the deprecated tagged instructions, such as, TADDcc
63 int x = long_at(0);
64 return (is_op(x, Assembler::arith_op) &&
65 (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3);
66 }
67 bool is_illegal();
68 bool is_zombie() {
69 int x = long_at(0);
70 return is_op3(x,
71 Assembler::ldsw_op3,
72 Assembler::ldst_op)
73 && Assembler::inv_rs1(x) == G0
74 && Assembler::inv_rd(x) == O7;
75 }
76 bool is_ic_miss_trap(); // Inline-cache uses a trap to detect a miss
77 bool is_return() {
78 // is it the output of MacroAssembler::ret or MacroAssembler::retl?
79 int x = long_at(0);
80 const int pc_return_offset = 8; // see frame_sparc.hpp
81 return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
82 && (inv_rs1(x) == I7 || inv_rs1(x) == O7)
83 && inv_immed(x) && inv_simm(x, 13) == pc_return_offset
84 && inv_rd(x) == G0;
85 }
86 bool is_int_jump() {
87 // is it the output of MacroAssembler::b?
88 int x = long_at(0);
89 return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2);
90 }
91 bool is_float_jump() {
92 // is it the output of MacroAssembler::fb?
93 int x = long_at(0);
94 return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2);
112 int x = long_at(0);
113 return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op);
114 }
115
116 bool is_membar() {
117 int x = long_at(0);
118 return is_op3(x, Assembler::membar_op3, Assembler::arith_op) &&
119 (inv_rd(x) == G0) && (inv_rs1(x) == O7);
120 }
121
122 bool is_safepoint_poll() {
123 int x = long_at(0);
124 return is_op3(x, Assembler::ldx_op3, Assembler::ldst_op) &&
125 (inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0);
126 }
127
128 bool is_zero_test(Register ®);
129 bool is_load_store_with_small_offset(Register reg);
130
131 public:
132 #ifdef ASSERT
133 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); }
134 #else
135 // Temporary fix: in optimized mode, u_field is a macro for efficiency reasons (see Assembler::u_field) - needs to be fixed
136 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | u_field(5, 18, 14) | Assembler::rd(O7); }
137 #endif
138 static int nop_instruction() { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); }
139 static int illegal_instruction(); // the output of __ breakpoint_trap()
140 static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); }
141
142 static int branch_instruction(Assembler::op2s op2val, Assembler::Condition c, bool a) {
143 return Assembler::op(Assembler::branch_op) | Assembler::op2(op2val) | Assembler::annul(a) | Assembler::cond(c);
144 }
145
146 static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) {
147 return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13);
148 }
149
150 static int sethi_instruction(Register rd, int imm22a) {
151 return Assembler::op(Assembler::branch_op) | Assembler::rd(rd) | Assembler::op2(Assembler::sethi_op2) | Assembler::hi22(imm22a);
152 }
153
154 protected:
155 address addr_at(int offset) const { return address(this) + offset; }
156 int long_at(int offset) const { return *(int*)addr_at(offset); }
157 void set_long_at(int offset, int i); /* deals with I-cache */
158 void set_jlong_at(int offset, jlong i); /* deals with I-cache */
159 void set_addr_at(int offset, address x); /* deals with I-cache */
160
161 address instruction_address() const { return addr_at(0); }
162 address next_instruction_address() const { return addr_at(BytesPerInstWord); }
163
164 static bool is_op( int x, Assembler::ops opval) {
165 return Assembler::inv_op(x) == opval;
166 }
167 static bool is_op2(int x, Assembler::op2s op2val) {
168 return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val;
169 }
170 static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) {
171 return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val;
172 }
173
174 // utilities to help subclasses decode:
|
50 nop_instruction_size = 4
51 };
52
53 bool is_nop() { return long_at(0) == nop_instruction(); }
54 bool is_call() { return is_op(long_at(0), Assembler::call_op); }
55 bool is_call_reg() { return is_op(long_at(0), Assembler::arith_op); }
56 bool is_sethi() { return (is_op2(long_at(0), Assembler::sethi_op2)
57 && inv_rd(long_at(0)) != G0); }
58
59 bool sets_cc() {
60 // conservative (returns true for some instructions that do not set the
61 // the condition code, such as, "save".
62 // Does not return true for the deprecated tagged instructions, such as, TADDcc
63 int x = long_at(0);
64 return (is_op(x, Assembler::arith_op) &&
65 (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3);
66 }
67 bool is_illegal();
68 bool is_zombie() {
69 int x = long_at(0);
70 return (is_op3(x, Assembler::ldsw_op3, Assembler::ldst_op) &&
71 inv_rs1(x) == G0 && inv_rd(x) == O7);
72 }
73 bool is_ic_miss_trap(); // Inline-cache uses a trap to detect a miss
74 bool is_return() {
75 // is it the output of MacroAssembler::ret or MacroAssembler::retl?
76 int x = long_at(0);
77 const int pc_return_offset = 8; // see frame_sparc.hpp
78 return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
79 && (inv_rs1(x) == I7 || inv_rs1(x) == O7)
80 && inv_immed(x) && inv_simm(x, 13) == pc_return_offset
81 && inv_rd(x) == G0;
82 }
83 bool is_int_jump() {
84 // is it the output of MacroAssembler::b?
85 int x = long_at(0);
86 return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2);
87 }
88 bool is_float_jump() {
89 // is it the output of MacroAssembler::fb?
90 int x = long_at(0);
91 return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2);
109 int x = long_at(0);
110 return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op);
111 }
112
113 bool is_membar() {
114 int x = long_at(0);
115 return is_op3(x, Assembler::membar_op3, Assembler::arith_op) &&
116 (inv_rd(x) == G0) && (inv_rs1(x) == O7);
117 }
118
119 bool is_safepoint_poll() {
120 int x = long_at(0);
121 return is_op3(x, Assembler::ldx_op3, Assembler::ldst_op) &&
122 (inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0);
123 }
124
125 bool is_zero_test(Register ®);
126 bool is_load_store_with_small_offset(Register reg);
127
128 public:
129 static int nop_instruction() { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); }
130 static int illegal_instruction(); // the output of __ breakpoint_trap()
131 static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); }
132
133 protected:
134 address addr_at(int offset) const { return address(this) + offset; }
135 int long_at(int offset) const { return *(int*)addr_at(offset); }
136 void set_long_at(int offset, int i); /* deals with I-cache */
137 void set_jlong_at(int offset, jlong i); /* deals with I-cache */
138 void set_addr_at(int offset, address x); /* deals with I-cache */
139
140 address instruction_address() const { return addr_at(0); }
141 address next_instruction_address() const { return addr_at(BytesPerInstWord); }
142
143 static bool is_op( int x, Assembler::ops opval) {
144 return Assembler::inv_op(x) == opval;
145 }
146 static bool is_op2(int x, Assembler::op2s op2val) {
147 return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val;
148 }
149 static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) {
150 return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val;
151 }
152
153 // utilities to help subclasses decode:
|