1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
  26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
  27 
  28 #include "asm/register.hpp"
  29 
  30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
  31 // level; i.e., what you write is what you get. The Assembler is generating code
  32 // into a CodeBuffer.
  33 
  34 class Assembler : public AbstractAssembler {
  35   friend class AbstractAssembler;
  36   friend class AddressLiteral;
  37 
  38   // code patchers need various routines like inv_wdisp()
  39   friend class NativeInstruction;
  40   friend class NativeGeneralJump;
  41   friend class Relocation;
  42   friend class Label;
  43 
  44  public:
  45   // op carries format info; see page 62 & 267
  46 
  47   enum ops {
  48     call_op   = 1, // fmt 1
  49     branch_op = 0, // also sethi (fmt2)
  50     arith_op  = 2, // fmt 3, arith & misc
  51     ldst_op   = 3  // fmt 3, load/store
  52   };
  53 
  54   enum op2s {
  55     bpr_op2   = 3,
  56     fb_op2    = 6,
  57     fbp_op2   = 5,
  58     br_op2    = 2,
  59     bp_op2    = 1,
  60     sethi_op2 = 4
  61   };
  62 
  63   enum op3s {
  64     // selected op3s
  65     add_op3      = 0x00,
  66     and_op3      = 0x01,
  67     or_op3       = 0x02,
  68     xor_op3      = 0x03,
  69     sub_op3      = 0x04,
  70     andn_op3     = 0x05,
  71     orn_op3      = 0x06,
  72     xnor_op3     = 0x07,
  73     addc_op3     = 0x08,
  74     mulx_op3     = 0x09,
  75     umul_op3     = 0x0a,
  76     smul_op3     = 0x0b,
  77     subc_op3     = 0x0c,
  78     udivx_op3    = 0x0d,
  79     udiv_op3     = 0x0e,
  80     sdiv_op3     = 0x0f,
  81 
  82     addcc_op3    = 0x10,
  83     andcc_op3    = 0x11,
  84     orcc_op3     = 0x12,
  85     xorcc_op3    = 0x13,
  86     subcc_op3    = 0x14,
  87     andncc_op3   = 0x15,
  88     orncc_op3    = 0x16,
  89     xnorcc_op3   = 0x17,
  90     addccc_op3   = 0x18,
  91     aes4_op3     = 0x19,
  92     umulcc_op3   = 0x1a,
  93     smulcc_op3   = 0x1b,
  94     subccc_op3   = 0x1c,
  95     udivcc_op3   = 0x1e,
  96     sdivcc_op3   = 0x1f,
  97 
  98     taddcc_op3   = 0x20,
  99     tsubcc_op3   = 0x21,
 100     taddcctv_op3 = 0x22,
 101     tsubcctv_op3 = 0x23,
 102     mulscc_op3   = 0x24,
 103     sll_op3      = 0x25,
 104     sllx_op3     = 0x25,
 105     srl_op3      = 0x26,
 106     srlx_op3     = 0x26,
 107     sra_op3      = 0x27,
 108     srax_op3     = 0x27,
 109     rdreg_op3    = 0x28,
 110     membar_op3   = 0x28,
 111 
 112     flushw_op3   = 0x2b,
 113     movcc_op3    = 0x2c,
 114     sdivx_op3    = 0x2d,
 115     popc_op3     = 0x2e,
 116     movr_op3     = 0x2f,
 117 
 118     sir_op3      = 0x30,
 119     wrreg_op3    = 0x30,
 120     saved_op3    = 0x31,
 121 
 122     fpop1_op3    = 0x34,
 123     fpop2_op3    = 0x35,
 124     impdep1_op3  = 0x36,
 125     aes3_op3     = 0x36,
 126     sha_op3      = 0x36,
 127     bmask_op3    = 0x36,
 128     bshuffle_op3   = 0x36,
 129     alignaddr_op3  = 0x36,
 130     faligndata_op3 = 0x36,
 131     flog3_op3    = 0x36,
 132     edge_op3     = 0x36,
 133     fzero_op3    = 0x36,
 134     fsrc_op3     = 0x36,
 135     fnot_op3     = 0x36,
 136     xmulx_op3    = 0x36,
 137     crc32c_op3   = 0x36,
 138     impdep2_op3  = 0x37,
 139     stpartialf_op3 = 0x37,
 140     jmpl_op3     = 0x38,
 141     rett_op3     = 0x39,
 142     trap_op3     = 0x3a,
 143     flush_op3    = 0x3b,
 144     save_op3     = 0x3c,
 145     restore_op3  = 0x3d,
 146     done_op3     = 0x3e,
 147     retry_op3    = 0x3e,
 148 
 149     lduw_op3     = 0x00,
 150     ldub_op3     = 0x01,
 151     lduh_op3     = 0x02,
 152     ldd_op3      = 0x03,
 153     stw_op3      = 0x04,
 154     stb_op3      = 0x05,
 155     sth_op3      = 0x06,
 156     std_op3      = 0x07,
 157     ldsw_op3     = 0x08,
 158     ldsb_op3     = 0x09,
 159     ldsh_op3     = 0x0a,
 160     ldx_op3      = 0x0b,
 161 
 162     stx_op3      = 0x0e,
 163     swap_op3     = 0x0f,
 164 
 165     stwa_op3     = 0x14,
 166     stxa_op3     = 0x1e,
 167 
 168     ldf_op3      = 0x20,
 169     ldfsr_op3    = 0x21,
 170     ldqf_op3     = 0x22,
 171     lddf_op3     = 0x23,
 172     stf_op3      = 0x24,
 173     stfsr_op3    = 0x25,
 174     stqf_op3     = 0x26,
 175     stdf_op3     = 0x27,
 176 
 177     prefetch_op3 = 0x2d,
 178 
 179     casa_op3     = 0x3c,
 180     casxa_op3    = 0x3e,
 181 
 182     mftoi_op3    = 0x36,
 183 
 184     alt_bit_op3  = 0x10,
 185      cc_bit_op3  = 0x10
 186   };
 187 
 188   enum opfs {
 189     // selected opfs
 190     edge8n_opf         = 0x01,
 191 
 192     fmovs_opf          = 0x01,
 193     fmovd_opf          = 0x02,
 194 
 195     fnegs_opf          = 0x05,
 196     fnegd_opf          = 0x06,
 197 
 198     alignaddr_opf      = 0x18,
 199     bmask_opf          = 0x19,
 200 
 201     fadds_opf          = 0x41,
 202     faddd_opf          = 0x42,
 203     fsubs_opf          = 0x45,
 204     fsubd_opf          = 0x46,
 205 
 206     faligndata_opf     = 0x48,
 207 
 208     fmuls_opf          = 0x49,
 209     fmuld_opf          = 0x4a,
 210     bshuffle_opf       = 0x4c,
 211     fdivs_opf          = 0x4d,
 212     fdivd_opf          = 0x4e,
 213 
 214     fcmps_opf          = 0x51,
 215     fcmpd_opf          = 0x52,
 216 
 217     fstox_opf          = 0x81,
 218     fdtox_opf          = 0x82,
 219     fxtos_opf          = 0x84,
 220     fxtod_opf          = 0x88,
 221     fitos_opf          = 0xc4,
 222     fdtos_opf          = 0xc6,
 223     fitod_opf          = 0xc8,
 224     fstod_opf          = 0xc9,
 225     fstoi_opf          = 0xd1,
 226     fdtoi_opf          = 0xd2,
 227 
 228     mdtox_opf          = 0x110,
 229     mstouw_opf         = 0x111,
 230     mstosw_opf         = 0x113,
 231     xmulx_opf          = 0x115,
 232     xmulxhi_opf        = 0x116,
 233     mxtod_opf          = 0x118,
 234     mwtos_opf          = 0x119,
 235 
 236     aes_kexpand0_opf   = 0x130,
 237     aes_kexpand2_opf   = 0x131,
 238 
 239     sha1_opf           = 0x141,
 240     sha256_opf         = 0x142,
 241     sha512_opf         = 0x143,
 242 
 243     crc32c_opf         = 0x147
 244   };
 245 
 246   enum op5s {
 247     aes_eround01_op5   = 0x00,
 248     aes_eround23_op5   = 0x01,
 249     aes_dround01_op5   = 0x02,
 250     aes_dround23_op5   = 0x03,
 251     aes_eround01_l_op5 = 0x04,
 252     aes_eround23_l_op5 = 0x05,
 253     aes_dround01_l_op5 = 0x06,
 254     aes_dround23_l_op5 = 0x07,
 255     aes_kexpand1_op5   = 0x08
 256   };
 257 
 258   enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
 259 
 260   enum Condition {
 261      // for FBfcc & FBPfcc instruction
 262     f_never                     = 0,
 263     f_notEqual                  = 1,
 264     f_notZero                   = 1,
 265     f_lessOrGreater             = 2,
 266     f_unorderedOrLess           = 3,
 267     f_less                      = 4,
 268     f_unorderedOrGreater        = 5,
 269     f_greater                   = 6,
 270     f_unordered                 = 7,
 271     f_always                    = 8,
 272     f_equal                     = 9,
 273     f_zero                      = 9,
 274     f_unorderedOrEqual          = 10,
 275     f_greaterOrEqual            = 11,
 276     f_unorderedOrGreaterOrEqual = 12,
 277     f_lessOrEqual               = 13,
 278     f_unorderedOrLessOrEqual    = 14,
 279     f_ordered                   = 15,
 280 
 281     // for integers
 282 
 283     never                = 0,
 284     equal                = 1,
 285     zero                 = 1,
 286     lessEqual            = 2,
 287     less                 = 3,
 288     lessEqualUnsigned    = 4,
 289     lessUnsigned         = 5,
 290     carrySet             = 5,
 291     negative             = 6,
 292     overflowSet          = 7,
 293     always               = 8,
 294     notEqual             = 9,
 295     notZero              = 9,
 296     greater              = 10,
 297     greaterEqual         = 11,
 298     greaterUnsigned      = 12,
 299     greaterEqualUnsigned = 13,
 300     carryClear           = 13,
 301     positive             = 14,
 302     overflowClear        = 15
 303   };
 304 
 305   enum CC {
 306     // ptr_cc is the correct condition code for a pointer or intptr_t:
 307     icc  = 0, xcc  = 2, ptr_cc = xcc,
 308     fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
 309   };
 310 
 311   enum PrefetchFcn {
 312     severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
 313   };
 314 
 315  public:
 316   // Helper functions for groups of instructions
 317 
 318   enum Predict { pt = 1, pn = 0 }; // pt = predict taken
 319 
 320   enum Membar_mask_bits { // page 184, v9
 321     StoreStore = 1 << 3,
 322     LoadStore  = 1 << 2,
 323     StoreLoad  = 1 << 1,
 324     LoadLoad   = 1 << 0,
 325 
 326     Sync       = 1 << 6,
 327     MemIssue   = 1 << 5,
 328     Lookaside  = 1 << 4
 329   };
 330 
 331   static bool is_in_wdisp_range(address a, address b, int nbits) {
 332     intptr_t d = intptr_t(b) - intptr_t(a);
 333     return is_simm(d, nbits + 2);
 334   }
 335 
 336   address target_distance(Label &L) {
 337     // Assembler::target(L) should be called only when
 338     // a branch instruction is emitted since non-bound
 339     // labels record current pc() as a branch address.
 340     if (L.is_bound()) return target(L);
 341     // Return current address for non-bound labels.
 342     return pc();
 343   }
 344 
 345   // test if label is in simm16 range in words (wdisp16).
 346   bool is_in_wdisp16_range(Label &L) {
 347     return is_in_wdisp_range(target_distance(L), pc(), 16);
 348   }
 349   // test if the distance between two addresses fits in simm30 range in words
 350   static bool is_in_wdisp30_range(address a, address b) {
 351     return is_in_wdisp_range(a, b, 30);
 352   }
 353 
 354   enum ASIs { // page 72, v9
 355     ASI_PRIMARY            = 0x80,
 356     ASI_PRIMARY_NOFAULT    = 0x82,
 357     ASI_PRIMARY_LITTLE     = 0x88,
 358     // 8x8-bit partial store
 359     ASI_PST8_PRIMARY       = 0xC0,
 360     // Block initializing store
 361     ASI_ST_BLKINIT_PRIMARY = 0xE2,
 362     // Most-Recently-Used (MRU) BIS variant
 363     ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
 364     // add more from book as needed
 365   };
 366 
 367  protected:
 368   // helpers
 369 
 370   // x is supposed to fit in a field "nbits" wide
 371   // and be sign-extended. Check the range.
 372 
 373   static void assert_signed_range(intptr_t x, int nbits) {
 374     assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
 375            "value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits);
 376   }
 377 
 378   static void assert_signed_word_disp_range(intptr_t x, int nbits) {
 379     assert((x & 3) == 0, "not word aligned");
 380     assert_signed_range(x, nbits + 2);
 381   }
 382 
 383   static void assert_unsigned_const(int x, int nbits) {
 384     assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
 385   }
 386 
 387   // fields: note bits numbered from LSB = 0, fields known by inclusive bit range
 388 
 389   static int fmask(juint hi_bit, juint lo_bit) {
 390     assert(hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
 391     return (1 << (hi_bit-lo_bit + 1)) - 1;
 392   }
 393 
 394   // inverse of u_field
 395 
 396   static int inv_u_field(int x, int hi_bit, int lo_bit) {
 397     juint r = juint(x) >> lo_bit;
 398     r &= fmask(hi_bit, lo_bit);
 399     return int(r);
 400   }
 401 
 402   // signed version: extract from field and sign-extend
 403 
 404   static int inv_s_field(int x, int hi_bit, int lo_bit) {
 405     int sign_shift = 31 - hi_bit;
 406     return inv_u_field(((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
 407   }
 408 
 409   // given a field that ranges from hi_bit to lo_bit (inclusive,
 410   // LSB = 0), and an unsigned value for the field,
 411   // shift it into the field
 412 
 413 #ifdef ASSERT
 414   static int u_field(int x, int hi_bit, int lo_bit) {
 415     assert((x & ~fmask(hi_bit, lo_bit)) == 0,
 416             "value out of range");
 417     int r = x << lo_bit;
 418     assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
 419     return r;
 420   }
 421 #else
 422   // make sure this is inlined as it will reduce code size significantly
 423   #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
 424 #endif
 425 
 426   static int inv_op(int x)   { return inv_u_field(x, 31, 30); }
 427   static int inv_op2(int x)  { return inv_u_field(x, 24, 22); }
 428   static int inv_op3(int x)  { return inv_u_field(x, 24, 19); }
 429   static int inv_cond(int x) { return inv_u_field(x, 28, 25); }
 430 
 431   static bool inv_immed(int x)   { return (x & Assembler::immed(true)) != 0; }
 432 
 433   static Register inv_rd(int x)  { return as_Register(inv_u_field(x, 29, 25)); }
 434   static Register inv_rs1(int x) { return as_Register(inv_u_field(x, 18, 14)); }
 435   static Register inv_rs2(int x) { return as_Register(inv_u_field(x,  4,  0)); }
 436 
 437   static int op(int x)           { return u_field(x,             31, 30); }
 438   static int rd(Register r)      { return u_field(r->encoding(), 29, 25); }
 439   static int fcn(int x)          { return u_field(x,             29, 25); }
 440   static int op3(int x)          { return u_field(x,             24, 19); }
 441   static int rs1(Register r)     { return u_field(r->encoding(), 18, 14); }
 442   static int rs2(Register r)     { return u_field(r->encoding(),  4,  0); }
 443   static int annul(bool a)       { return u_field(a ? 1 : 0,     29, 29); }
 444   static int cond(int x)         { return u_field(x,             28, 25); }
 445   static int cond_mov(int x)     { return u_field(x,             17, 14); }
 446   static int rcond(RCondition x) { return u_field(x,             12, 10); }
 447   static int op2(int x)          { return u_field(x,             24, 22); }
 448   static int predict(bool p)     { return u_field(p ? 1 : 0,     19, 19); }
 449   static int branchcc(CC fcca)   { return u_field(fcca,          21, 20); }
 450   static int cmpcc(CC fcca)      { return u_field(fcca,          26, 25); }
 451   static int imm_asi(int x)      { return u_field(x,             12,  5); }
 452   static int immed(bool i)       { return u_field(i ? 1 : 0,     13, 13); }
 453   static int opf_low6(int w)     { return u_field(w,             10,  5); }
 454   static int opf_low5(int w)     { return u_field(w,              9,  5); }
 455   static int op5(int x)          { return u_field(x,              8,  5); }
 456   static int trapcc(CC cc)       { return u_field(cc,            12, 11); }
 457   static int sx(int i)           { return u_field(i,             12, 12); } // shift x=1 means 64-bit
 458   static int opf(int x)          { return u_field(x,             13,  5); }
 459 
 460   static bool is_cbcond(int x) {
 461     return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
 462             inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
 463   }
 464   static bool is_cxb(int x) {
 465     assert(is_cbcond(x), "wrong instruction");
 466     return (x & (1 << 21)) != 0;
 467   }
 468   static bool is_branch(int x) {
 469     if (inv_op(x) != Assembler::branch_op) return false;
 470 
 471     bool is_bpr = inv_op2(x) == Assembler::bpr_op2;
 472     bool is_bp  = inv_op2(x) == Assembler::bp_op2;
 473     bool is_br  = inv_op2(x) == Assembler::br_op2;
 474     bool is_fp  = inv_op2(x) == Assembler::fb_op2;
 475     bool is_fbp = inv_op2(x) == Assembler::fbp_op2;
 476 
 477     return is_bpr || is_bp || is_br || is_fp || is_fbp;
 478   }
 479   static bool is_call(int x) {
 480     return inv_op(x) == Assembler::call_op;
 481   }
 482   static bool is_jump(int x) {
 483     if (inv_op(x) != Assembler::arith_op) return false;
 484 
 485     bool is_jmpl = inv_op3(x) == Assembler::jmpl_op3;
 486     bool is_rett = inv_op3(x) == Assembler::rett_op3;
 487 
 488     return is_jmpl || is_rett;
 489   }
 490   static bool is_rdpc(int x) {
 491     return (inv_op(x) == Assembler::arith_op && inv_op3(x) == Assembler::rdreg_op3 &&
 492             inv_u_field(x, 18, 14) == 5);
 493   }
 494   static bool is_cti(int x) {
 495       return is_branch(x) || is_call(x) || is_jump(x); // Ignoring done/retry
 496   }
 497 
 498   static int cond_cbcond(int x) { return  u_field((((x & 8) << 1) + 8 + (x & 7)), 29, 25); }
 499   static int inv_cond_cbcond(int x) {
 500     assert(is_cbcond(x), "wrong instruction");
 501     return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29) << 3);
 502   }
 503 
 504   static int opf_cc(CC c, bool useFloat) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
 505   static int mov_cc(CC c, bool useFloat) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
 506 
 507   static int fd(FloatRegister r, FloatRegisterImpl::Width fwa)  { return u_field(r->encoding(fwa), 29, 25); };
 508   static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
 509   static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
 510   static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13,  9); };
 511 
 512   // some float instructions use this encoding on the op3 field
 513   static int alt_op3(int op, FloatRegisterImpl::Width w) {
 514     int r;
 515     switch(w) {
 516      case FloatRegisterImpl::S: r = op + 0;  break;
 517      case FloatRegisterImpl::D: r = op + 3;  break;
 518      case FloatRegisterImpl::Q: r = op + 2;  break;
 519      default: ShouldNotReachHere(); break;
 520     }
 521     return op3(r);
 522   }
 523 
 524   // compute inverse of simm
 525   static int inv_simm(int x, int nbits) {
 526     return (int)(x << (32 - nbits)) >> (32 - nbits);
 527   }
 528 
 529   static int inv_simm13(int x) { return inv_simm(x, 13); }
 530 
 531   // signed immediate, in low bits, nbits long
 532   static int simm(int x, int nbits) {
 533     assert_signed_range(x, nbits);
 534     return x & ((1 << nbits) - 1);
 535   }
 536 
 537   // compute inverse of wdisp16
 538   static intptr_t inv_wdisp16(int x, intptr_t pos) {
 539     int lo = x & ((1 << 14) - 1);
 540     int hi = (x >> 20) & 3;
 541     if (hi >= 2) hi |= ~1;
 542     return (((hi << 14) | lo) << 2) + pos;
 543   }
 544 
 545   // word offset, 14 bits at LSend, 2 bits at B21, B20
 546   static int wdisp16(intptr_t x, intptr_t off) {
 547     intptr_t xx = x - off;
 548     assert_signed_word_disp_range(xx, 16);
 549     int r = (xx >> 2) & ((1 << 14) - 1) | (((xx >> (2+14)) & 3) << 20);
 550     assert(inv_wdisp16(r, off) == x, "inverse is not inverse");
 551     return r;
 552   }
 553 
 554   // compute inverse of wdisp10
 555   static intptr_t inv_wdisp10(int x, intptr_t pos) {
 556     assert(is_cbcond(x), "wrong instruction");
 557     int lo = inv_u_field(x, 12, 5);
 558     int hi = (x >> 19) & 3;
 559     if (hi >= 2) hi |= ~1;
 560     return (((hi << 8) | lo) << 2) + pos;
 561   }
 562 
 563   // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
 564   static int wdisp10(intptr_t x, intptr_t off) {
 565     assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
 566     intptr_t xx = x - off;
 567     assert_signed_word_disp_range(xx, 10);
 568     int r = (((xx >> 2) & ((1 << 8) - 1)) << 5) | (((xx >> (2+8)) & 3) << 19);
 569     // Have to fake cbcond instruction to pass assert in inv_wdisp10()
 570     assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
 571     return r;
 572   }
 573 
 574   // word displacement in low-order nbits bits
 575 
 576   static intptr_t inv_wdisp(int x, intptr_t pos, int nbits) {
 577     int pre_sign_extend = x & ((1 << nbits) - 1);
 578     int r = (pre_sign_extend >= (1 << (nbits - 1)) ?
 579              pre_sign_extend | ~((1 << nbits) - 1) : pre_sign_extend);
 580     return (r << 2) + pos;
 581   }
 582 
 583   static int wdisp(intptr_t x, intptr_t off, int nbits) {
 584     intptr_t xx = x - off;
 585     assert_signed_word_disp_range(xx, nbits);
 586     int r = (xx >> 2) & ((1 << nbits) - 1);
 587     assert(inv_wdisp(r, off, nbits) == x, "inverse not inverse");
 588     return r;
 589   }
 590 
 591 
 592   // Extract the top 32 bits in a 64 bit word
 593   static int32_t hi32(int64_t x) {
 594     int32_t r = int32_t((uint64_t)x >> 32);
 595     return r;
 596   }
 597 
 598   // given a sethi instruction, extract the constant, left-justified
 599   static int inv_hi22(int x) {
 600     return x << 10;
 601   }
 602 
 603   // create an imm22 field, given a 32-bit left-justified constant
 604   static int hi22(int x) {
 605     int r = int(juint(x) >> 10);
 606     assert((r & ~((1 << 22) - 1)) == 0, "just checkin'");
 607     return r;
 608   }
 609 
 610   // create a low10 __value__ (not a field) for a given a 32-bit constant
 611   static int low10(int x) {
 612     return x & ((1 << 10) - 1);
 613   }
 614 
 615   // create a low12 __value__ (not a field) for a given a 32-bit constant
 616   static int low12(int x) {
 617     return x & ((1 << 12) - 1);
 618   }
 619 
 620   // AES crypto instructions supported only on certain processors
 621   static void aes_only() { assert(VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
 622 
 623   // SHA crypto instructions supported only on certain processors
 624   static void sha1_only()   { assert(VM_Version::has_sha1(),   "This instruction only works on SPARC with SHA1"); }
 625   static void sha256_only() { assert(VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
 626   static void sha512_only() { assert(VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
 627 
 628   // CRC32C instruction supported only on certain processors
 629   static void crc32c_only() { assert(VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
 630 
 631   // instruction only in VIS1
 632   static void vis1_only() { assert(VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
 633 
 634   // instruction only in VIS2
 635   static void vis2_only() { assert(VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
 636 
 637   // instruction only in VIS3
 638   static void vis3_only() { assert(VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
 639 
 640   // instruction deprecated in v9
 641   static void v9_dep() { } // do nothing for now
 642 
 643  protected:








 644 #ifdef ASSERT
 645 #define VALIDATE_PIPELINE
 646 #endif
 647 
 648 #ifdef VALIDATE_PIPELINE
 649   // A simple delay-slot scheme:
 650   // In order to check the programmer, the assembler keeps track of delay-slots.
 651   // It forbids CTIs in delay-slots (conservative, but should be OK). Also, when
 652   // emitting an instruction into a delay-slot, you must do so using delayed(),
 653   // e.g. asm->delayed()->add(...), in order to check that you do not omit the
 654   // delay-slot instruction. To implement this, we use a simple FSA.
 655   enum { NoDelay, AtDelay, FillDelay } _delay_state;
 656 
 657   // A simple hazard scheme:
 658   // In order to avoid pipeline stalls, due to single cycle pipeline hazards, we
 659   // adopt a simplistic state tracking mechanism that will enforce an additional
 660   // 'nop' instruction to be inserted prior to emitting an instruction that can
 661   // expose a given hazard (currently, PC-related hazards only).
 662   enum { NoHazard, PcHazard } _hazard_state;
 663 #endif
 664 
 665  public:
 666   // Tell the assembler that the next instruction must NOT be in delay-slot.
 667   // Use at start of multi-instruction macros.
 668   void assert_not_delayed() {
 669     // This is a separate entry to avoid the creation of string constants in
 670     // non-asserted code, with some compilers this pollutes the object code.
 671 #ifdef VALIDATE_PIPELINE
 672     assert_no_delay("Next instruction should not be in a delay-slot.");
 673 #endif
 674   }
 675 
 676  protected:
 677   void assert_no_delay(const char* msg) {
 678 #ifdef VALIDATE_PIPELINE
 679     assert(_delay_state == NoDelay, msg);
 680 #endif
 681   }
 682 
 683   void assert_no_hazard() {
 684 #ifdef VALIDATE_PIPELINE
 685     assert(_hazard_state == NoHazard, "Unsolicited pipeline hazard.");
 686 #endif
 687   }
 688 
 689  private:
 690   inline int32_t prev_insn() {
 691     assert(offset() > 0, "Interface violation.");
 692     int32_t* addr = (int32_t*)pc() - 1;
 693     return *addr;
 694   }
 695 
 696 #ifdef VALIDATE_PIPELINE
 697   void validate_no_pipeline_hazards();
 698 #endif
 699 
 700  protected:
 701   // Avoid possible pipeline stall by inserting an additional 'nop' instruction,
 702   // if the previous instruction is a 'cbcond' or a 'rdpc'.
 703   inline void avoid_pipeline_stall();
 704 
 705   // A call to cti() is made before emitting a control-transfer instruction (CTI)
 706   // in order to assert a CTI is not emitted right after a 'cbcond', nor in the
 707   // delay-slot of another CTI. Only effective when assertions are enabled.

 708   void cti() {
 709     // A 'cbcond' or 'rdpc' instruction immediately followed by a CTI introduces
 710     // a pipeline stall, which we make sure to prohibit.
 711     assert_no_cbcond_before();
 712     assert_no_rdpc_before();
 713 #ifdef VALIDATE_PIPELINE
 714     assert_no_hazard();
 715     assert_no_delay("CTI in delay-slot.");
 716 #endif
 717   }
 718 
 719   // Called when emitting CTI with a delay-slot, AFTER emitting.
 720   inline void induce_delay_slot() {
 721 #ifdef VALIDATE_PIPELINE
 722     assert_no_delay("Already in delay-slot.");
 723     _delay_state = AtDelay;
 724 #endif
 725   }
 726 
 727   inline void induce_pc_hazard() {
 728 #ifdef VALIDATE_PIPELINE
 729     assert_no_hazard();
 730     _hazard_state = PcHazard;
 731 #endif
 732   }
 733 
 734   bool is_cbcond_before() { return offset() > 0 ? is_cbcond(prev_insn()) : false; }
 735 
 736   bool is_rdpc_before() { return offset() > 0 ? is_rdpc(prev_insn()) : false; }
 737 
 738   void assert_no_cbcond_before() {
 739     assert(offset() == 0 || !is_cbcond_before(), "CBCOND should not be followed by CTI.");
 740   }

 741 
 742   void assert_no_rdpc_before() {
 743     assert(offset() == 0 || !is_rdpc_before(), "RDPC should not be followed by CTI.");
 744   }
 745 
 746  public:
 747 
 748   bool use_cbcond(Label &L) {
 749     if (!UseCBCond || is_cbcond_before()) return false;
 750     intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
 751     assert((x & 3) == 0, "not word aligned");
 752     return is_simm12(x);
 753   }
 754 
 755   // Tells assembler you know that next instruction is delayed
 756   Assembler* delayed() {
 757 #ifdef VALIDATE_PIPELINE
 758     assert(_delay_state == AtDelay, "Delayed instruction not in delay-slot.");
 759     _delay_state = FillDelay;
 760 #endif
 761     return this;
 762   }
 763 
 764   void flush() {
 765 #ifdef VALIDATE_PIPELINE
 766     assert(_delay_state == NoDelay, "Ending code with a delay-slot.");
 767     validate_no_pipeline_hazards();
 768 #endif
 769     AbstractAssembler::flush();
 770   }
 771 
 772   inline void emit_int32(int);  // shadows AbstractAssembler::emit_int32
 773   inline void emit_data(int);
 774   inline void emit_data(int, RelocationHolder const &rspec);
 775   inline void emit_data(int, relocInfo::relocType rtype);
 776   // helper for above functions
 777   inline void check_delay();
 778 
 779 
 780  public:
 781   // instructions, refer to page numbers in the SPARC Architecture Manual, V9
 782 
 783   // pp 135
 784 
 785   inline void add(Register s1, Register s2, Register d);
 786   inline void add(Register s1, int simm13a, Register d);
 787 
 788   inline void addcc(Register s1, Register s2, Register d);
 789   inline void addcc(Register s1, int simm13a, Register d);
 790   inline void addc(Register s1, Register s2, Register d);
 791   inline void addc(Register s1, int simm13a, Register d);
 792   inline void addccc(Register s1, Register s2, Register d);
 793   inline void addccc(Register s1, int simm13a, Register d);
 794 
 795 
 796   // 4-operand AES instructions
 797 
 798   inline void aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
 799   inline void aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
 800   inline void aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
 801   inline void aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
 802   inline void aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
 803   inline void aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
 804   inline void aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
 805   inline void aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d);
 806   inline void aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d);
 807 
 808 
 809   // 3-operand AES instructions
 810 
 811   inline void aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d);
 812   inline void aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d);
 813 
 814   // pp 136
 815 
 816   inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
 817   inline void bpr(RCondition c, bool a, Predict p, Register s1, Label &L);
 818 
 819   // compare and branch
 820   inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label &L);
 821   inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label &L);
 822 
 823  protected: // use MacroAssembler::br instead
 824 
 825   // pp 138
 826 
 827   inline void fb(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none);
 828   inline void fb(Condition c, bool a, Label &L);
 829 
 830   // pp 141
 831 
 832   inline void fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none);
 833   inline void fbp(Condition c, bool a, CC cc, Predict p, Label &L);
 834 
 835   // pp 144
 836 
 837   inline void br(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none);
 838   inline void br(Condition c, bool a, Label &L);
 839 
 840   // pp 146
 841 
 842   inline void bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none);
 843   inline void bp(Condition c, bool a, CC cc, Predict p, Label &L);
 844 
 845   // pp 149
 846 
 847   inline void call(address d, relocInfo::relocType rt = relocInfo::runtime_call_type);
 848   inline void call(Label &L,  relocInfo::relocType rt = relocInfo::runtime_call_type);
 849 
 850   inline void call(address d, RelocationHolder const &rspec);
 851 
 852  public:
 853 
 854   // pp 150
 855 
 856   // These instructions compare the contents of s2 with the contents of
 857   // memory at address in s1. If the values are equal, the contents of memory
 858   // at address s1 is swapped with the data in d. If the values are not equal,
 859   // the the contents of memory at s1 is loaded into d, without the swap.
 860 
 861   inline void casa(Register s1, Register s2, Register d, int ia = -1);
 862   inline void casxa(Register s1, Register s2, Register d, int ia = -1);
 863 
 864   // pp 152
 865 
 866   inline void udiv(Register s1, Register s2, Register d);
 867   inline void udiv(Register s1, int simm13a, Register d);
 868   inline void sdiv(Register s1, Register s2, Register d);
 869   inline void sdiv(Register s1, int simm13a, Register d);
 870   inline void udivcc(Register s1, Register s2, Register d);
 871   inline void udivcc(Register s1, int simm13a, Register d);
 872   inline void sdivcc(Register s1, Register s2, Register d);
 873   inline void sdivcc(Register s1, int simm13a, Register d);
 874 
 875   // pp 155
 876 
 877   inline void done();
 878   inline void retry();
 879 
 880   // pp 156
 881 
 882   inline void fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
 883   inline void fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
 884 
 885   // pp 157
 886 
 887   inline void fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
 888   inline void fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
 889 
 890   // pp 159
 891 
 892   inline void ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
 893   inline void ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
 894 
 895   // pp 160
 896 
 897   inline void ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d);
 898 
 899   // pp 161
 900 
 901   inline void fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
 902   inline void fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
 903 
 904   // pp 162
 905 
 906   inline void fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
 907 
 908   inline void fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
 909 
 910   inline void fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
 911 
 912   // pp 163
 913 
 914   inline void fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
 915   inline void fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d);
 916   inline void fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
 917 
 918   // FXORs/FXORd instructions
 919 
 920   inline void fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d);
 921 
 922   // pp 164
 923 
 924   inline void fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
 925 
 926   // pp 165
 927 
 928   inline void flush(Register s1, Register s2);
 929   inline void flush(Register s1, int simm13a);
 930 
 931   // pp 167
 932 
 933   void flushw();
 934 
 935   // pp 168
 936 
 937   void illtrap(int const22a);
 938 
 939   // pp 169
 940 
 941   void impdep1(int id1, int const19a);
 942   void impdep2(int id1, int const19a);
 943 
 944   // pp 170
 945 
 946   void jmpl(Register s1, Register s2, Register d);
 947   void jmpl(Register s1, int simm13a, Register d,
 948             RelocationHolder const &rspec = RelocationHolder());
 949 
 950   // 171
 951 
 952   inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
 953   inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d,
 954                   RelocationHolder const &rspec = RelocationHolder());
 955 
 956 
 957   inline void ldfsr(Register s1, Register s2);
 958   inline void ldfsr(Register s1, int simm13a);
 959   inline void ldxfsr(Register s1, Register s2);
 960   inline void ldxfsr(Register s1, int simm13a);
 961 
 962   // 173
 963 
 964   inline void ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d);
 965   inline void ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a,         FloatRegister d);
 966 
 967   // pp 175
 968 
 969   inline void ldsb(Register s1, Register s2, Register d);
 970   inline void ldsb(Register s1, int simm13a, Register d);
 971   inline void ldsh(Register s1, Register s2, Register d);
 972   inline void ldsh(Register s1, int simm13a, Register d);
 973   inline void ldsw(Register s1, Register s2, Register d);
 974   inline void ldsw(Register s1, int simm13a, Register d);
 975   inline void ldub(Register s1, Register s2, Register d);
 976   inline void ldub(Register s1, int simm13a, Register d);
 977   inline void lduh(Register s1, Register s2, Register d);
 978   inline void lduh(Register s1, int simm13a, Register d);
 979   inline void lduw(Register s1, Register s2, Register d);
 980   inline void lduw(Register s1, int simm13a, Register d);
 981   inline void ldx(Register s1, Register s2, Register d);
 982   inline void ldx(Register s1, int simm13a, Register d);
 983   inline void ldd(Register s1, Register s2, Register d);
 984   inline void ldd(Register s1, int simm13a, Register d);
 985 
 986   // pp 177
 987 
 988   inline void ldsba(Register s1, Register s2, int ia, Register d);
 989   inline void ldsba(Register s1, int simm13a,         Register d);
 990   inline void ldsha(Register s1, Register s2, int ia, Register d);
 991   inline void ldsha(Register s1, int simm13a,         Register d);
 992   inline void ldswa(Register s1, Register s2, int ia, Register d);
 993   inline void ldswa(Register s1, int simm13a,         Register d);
 994   inline void lduba(Register s1, Register s2, int ia, Register d);
 995   inline void lduba(Register s1, int simm13a,         Register d);
 996   inline void lduha(Register s1, Register s2, int ia, Register d);
 997   inline void lduha(Register s1, int simm13a,         Register d);
 998   inline void lduwa(Register s1, Register s2, int ia, Register d);
 999   inline void lduwa(Register s1, int simm13a,         Register d);
1000   inline void ldxa(Register s1, Register s2, int ia, Register d);
1001   inline void ldxa(Register s1, int simm13a,         Register d);
1002 
1003   // pp 181
1004 
1005   inline void and3(Register s1, Register s2, Register d);
1006   inline void and3(Register s1, int simm13a, Register d);
1007   inline void andcc(Register s1, Register s2, Register d);
1008   inline void andcc(Register s1, int simm13a, Register d);
1009   inline void andn(Register s1, Register s2, Register d);
1010   inline void andn(Register s1, int simm13a, Register d);
1011   inline void andncc(Register s1, Register s2, Register d);
1012   inline void andncc(Register s1, int simm13a, Register d);
1013   inline void or3(Register s1, Register s2, Register d);
1014   inline void or3(Register s1, int simm13a, Register d);
1015   inline void orcc(Register s1, Register s2, Register d);
1016   inline void orcc(Register s1, int simm13a, Register d);
1017   inline void orn(Register s1, Register s2, Register d);
1018   inline void orn(Register s1, int simm13a, Register d);
1019   inline void orncc(Register s1, Register s2, Register d);
1020   inline void orncc(Register s1, int simm13a, Register d);
1021   inline void xor3(Register s1, Register s2, Register d);
1022   inline void xor3(Register s1, int simm13a, Register d);
1023   inline void xorcc(Register s1, Register s2, Register d);
1024   inline void xorcc(Register s1, int simm13a, Register d);
1025   inline void xnor(Register s1, Register s2, Register d);
1026   inline void xnor(Register s1, int simm13a, Register d);
1027   inline void xnorcc(Register s1, Register s2, Register d);
1028   inline void xnorcc(Register s1, int simm13a, Register d);
1029 
1030   // pp 183
1031 
1032   inline void membar(Membar_mask_bits const7a);
1033 
1034   // pp 185
1035 
1036   inline void fmov(FloatRegisterImpl::Width w, Condition c,  bool floatCC, CC cca, FloatRegister s2, FloatRegister d);
1037 
1038   // pp 189
1039 
1040   inline void fmov(FloatRegisterImpl::Width w, RCondition c, Register s1,  FloatRegister s2, FloatRegister d);
1041 
1042   // pp 191
1043 
1044   inline void movcc(Condition c, bool floatCC, CC cca, Register s2, Register d);
1045   inline void movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d);
1046 
1047   // pp 195
1048 
1049   inline void movr(RCondition c, Register s1, Register s2,  Register d);
1050   inline void movr(RCondition c, Register s1, int simm10a,  Register d);
1051 
1052   // pp 196
1053 
1054   inline void mulx(Register s1, Register s2, Register d);
1055   inline void mulx(Register s1, int simm13a, Register d);
1056   inline void sdivx(Register s1, Register s2, Register d);
1057   inline void sdivx(Register s1, int simm13a, Register d);
1058   inline void udivx(Register s1, Register s2, Register d);
1059   inline void udivx(Register s1, int simm13a, Register d);
1060 
1061   // pp 197
1062 
1063   inline void umul(Register s1, Register s2, Register d);
1064   inline void umul(Register s1, int simm13a, Register d);
1065   inline void smul(Register s1, Register s2, Register d);
1066   inline void smul(Register s1, int simm13a, Register d);
1067   inline void umulcc(Register s1, Register s2, Register d);
1068   inline void umulcc(Register s1, int simm13a, Register d);
1069   inline void smulcc(Register s1, Register s2, Register d);
1070   inline void smulcc(Register s1, int simm13a, Register d);
1071 
1072   // pp 201
1073 
1074   inline void nop();
1075 
1076   inline void sw_count();
1077 
1078   // pp 202
1079 
1080   inline void popc(Register s,  Register d);
1081   inline void popc(int simm13a, Register d);
1082 
1083   // pp 203
1084 
1085   inline void prefetch(Register s1, Register s2, PrefetchFcn f);
1086   inline void prefetch(Register s1, int simm13a, PrefetchFcn f);
1087 
1088   inline void prefetcha(Register s1, Register s2, int ia, PrefetchFcn f);
1089   inline void prefetcha(Register s1, int simm13a,         PrefetchFcn f);
1090 
1091   // pp 208
1092 
1093   // not implementing read privileged register
1094 
1095   inline void rdy(Register d);
1096   inline void rdccr(Register d);
1097   inline void rdasi(Register d);
1098   inline void rdtick(Register d);
1099   inline void rdpc(Register d);
1100   inline void rdfprs(Register d);
1101 
1102   // pp 213
1103 
1104   inline void rett(Register s1, Register s2);
1105   inline void rett(Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1106 
1107   // pp 214
1108 
1109   inline void save(Register s1, Register s2, Register d);
1110   inline void save(Register s1, int simm13a, Register d);
1111 
1112   inline void restore(Register s1 = G0, Register s2 = G0, Register d = G0);
1113   inline void restore(Register s1,      int simm13a,      Register d);
1114 
1115   // pp 216
1116 
1117   inline void saved();
1118   inline void restored();
1119 
1120   // pp 217
1121 
1122   inline void sethi(int imm22a, Register d, RelocationHolder const &rspec = RelocationHolder());
1123 
1124   // pp 218
1125 
1126   inline void sll(Register s1, Register s2, Register d);
1127   inline void sll(Register s1, int imm5a,   Register d);
1128   inline void srl(Register s1, Register s2, Register d);
1129   inline void srl(Register s1, int imm5a,   Register d);
1130   inline void sra(Register s1, Register s2, Register d);
1131   inline void sra(Register s1, int imm5a,   Register d);
1132 
1133   inline void sllx(Register s1, Register s2, Register d);
1134   inline void sllx(Register s1, int imm6a,   Register d);
1135   inline void srlx(Register s1, Register s2, Register d);
1136   inline void srlx(Register s1, int imm6a,   Register d);
1137   inline void srax(Register s1, Register s2, Register d);
1138   inline void srax(Register s1, int imm6a,   Register d);
1139 
1140   // pp 220
1141 
1142   inline void sir(int simm13a);
1143 
1144   // pp 221
1145 
1146   inline void stbar();
1147 
1148   // pp 222
1149 
1150   inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1151   inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1152 
1153   inline void stfsr(Register s1, Register s2);
1154   inline void stfsr(Register s1, int simm13a);
1155   inline void stxfsr(Register s1, Register s2);
1156   inline void stxfsr(Register s1, int simm13a);
1157 
1158   // pp 224
1159 
1160   inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia);
1161   inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1162 
1163   // pp 226
1164 
1165   inline void stb(Register d, Register s1, Register s2);
1166   inline void stb(Register d, Register s1, int simm13a);
1167   inline void sth(Register d, Register s1, Register s2);
1168   inline void sth(Register d, Register s1, int simm13a);
1169   inline void stw(Register d, Register s1, Register s2);
1170   inline void stw(Register d, Register s1, int simm13a);
1171   inline void stx(Register d, Register s1, Register s2);
1172   inline void stx(Register d, Register s1, int simm13a);
1173   inline void std(Register d, Register s1, Register s2);
1174   inline void std(Register d, Register s1, int simm13a);
1175 
1176   // pp 177
1177 
1178   inline void stba(Register d, Register s1, Register s2, int ia);
1179   inline void stba(Register d, Register s1, int simm13a);
1180   inline void stha(Register d, Register s1, Register s2, int ia);
1181   inline void stha(Register d, Register s1, int simm13a);
1182   inline void stwa(Register d, Register s1, Register s2, int ia);
1183   inline void stwa(Register d, Register s1, int simm13a);
1184   inline void stxa(Register d, Register s1, Register s2, int ia);
1185   inline void stxa(Register d, Register s1, int simm13a);
1186   inline void stda(Register d, Register s1, Register s2, int ia);
1187   inline void stda(Register d, Register s1, int simm13a);
1188 
1189   // pp 230
1190 
1191   inline void sub(Register s1, Register s2, Register d);
1192   inline void sub(Register s1, int simm13a, Register d);
1193 
1194   inline void subcc(Register s1, Register s2, Register d);
1195   inline void subcc(Register s1, int simm13a, Register d);
1196   inline void subc(Register s1, Register s2, Register d);
1197   inline void subc(Register s1, int simm13a, Register d);
1198   inline void subccc(Register s1, Register s2, Register d);
1199   inline void subccc(Register s1, int simm13a, Register d);
1200 
1201   // pp 231
1202 
1203   inline void swap(Register s1, Register s2, Register d);
1204   inline void swap(Register s1, int simm13a, Register d);
1205 
1206   // pp 232
1207 
1208   inline void swapa(Register s1, Register s2, int ia, Register d);
1209   inline void swapa(Register s1, int simm13a,         Register d);
1210 
1211   // pp 234, note op in book is wrong, see pp 268
1212 
1213   inline void taddcc(Register s1, Register s2, Register d);
1214   inline void taddcc(Register s1, int simm13a, Register d);
1215 
1216   // pp 235
1217 
1218   inline void tsubcc(Register s1, Register s2, Register d);
1219   inline void tsubcc(Register s1, int simm13a, Register d);
1220 
1221   // pp 237
1222 
1223   inline void trap(Condition c, CC cc, Register s1, Register s2);
1224   inline void trap(Condition c, CC cc, Register s1, int trapa);
1225   // simple uncond. trap
1226   inline void trap(int trapa);
1227 
1228   // pp 239 omit write priv register for now
1229 
1230   inline void wry(Register d);
1231   inline void wrccr(Register s);
1232   inline void wrccr(Register s, int simm13a);
1233   inline void wrasi(Register d);
1234   // wrasi(d, imm) stores (d xor imm) to asi
1235   inline void wrasi(Register d, int simm13a);
1236   inline void wrfprs(Register d);
1237 
1238   // VIS1 instructions
1239 
1240   inline void alignaddr(Register s1, Register s2, Register d);
1241 
1242   inline void faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d);
1243 
1244   inline void fzero(FloatRegisterImpl::Width w, FloatRegister d);
1245 
1246   inline void fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d);
1247 
1248   inline void fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d);
1249 
1250   inline void fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d);
1251 
1252   inline void stpartialf(Register s1, Register s2, FloatRegister d, int ia = -1);
1253 
1254   // VIS2 instructions
1255 
1256   inline void edge8n(Register s1, Register s2, Register d);
1257 
1258   inline void bmask(Register s1, Register s2, Register d);
1259   inline void bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d);
1260 
1261   // VIS3 instructions
1262 
1263   inline void movstosw(FloatRegister s, Register d);
1264   inline void movstouw(FloatRegister s, Register d);
1265   inline void movdtox(FloatRegister s, Register d);
1266 
1267   inline void movwtos(Register s, FloatRegister d);
1268   inline void movxtod(Register s, FloatRegister d);
1269 
1270   inline void xmulx(Register s1, Register s2, Register d);
1271   inline void xmulxhi(Register s1, Register s2, Register d);
1272 
1273   // Crypto SHA instructions
1274 
1275   inline void sha1();
1276   inline void sha256();
1277   inline void sha512();
1278 
1279   // CRC32C instruction
1280 
1281   inline void crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d);
1282 
1283   // Creation
1284   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1285 #ifdef VALIDATE_PIPELINE
1286     _delay_state  = NoDelay;
1287     _hazard_state = NoHazard;
1288 #endif
1289   }
1290 };
1291 
1292 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
--- EOF ---