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src/cpu/sparc/vm/macroAssembler_sparc.inline.hpp

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 168   if (s2.is_register())  sll_ptr(s1, s2.as_register(), d);
 169   else                   sll_ptr(s1, s2.as_constant(), d);
 170 }
 171 
 172 inline void MacroAssembler::casl(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
 173 inline void MacroAssembler::casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
 174 
 175 inline void MacroAssembler::inc(   Register d,  int const13 ) { add(   d, const13, d); }
 176 inline void MacroAssembler::inccc( Register d,  int const13 ) { addcc( d, const13, d); }
 177 
 178 inline void MacroAssembler::dec(   Register d,  int const13 ) { sub(   d, const13, d); }
 179 inline void MacroAssembler::deccc( Register d,  int const13 ) { subcc( d, const13, d); }
 180 
 181 // Use the right branch for the platform
 182 
 183 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 184   Assembler::bp(c, a, icc, p, d, rt);
 185 }
 186 
 187 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
 188   insert_nop_after_cbcond();

 189   br(c, a, p, target(L));
 190 }
 191 
 192 
 193 // Branch that tests either xcc or icc depending on the
 194 // architecture compiled (LP64 or not)
 195 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 196     Assembler::bp(c, a, xcc, p, d, rt);
 197 }
 198 
 199 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
 200   insert_nop_after_cbcond();
 201   brx(c, a, p, target(L));
 202 }
 203 
 204 inline void MacroAssembler::ba( Label& L ) {
 205   br(always, false, pt, L);
 206 }
 207 
 208 // Warning: V9 only functions
 209 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
 210   Assembler::bp(c, a, cc, p, d, rt);
 211 }
 212 
 213 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
 214   Assembler::bp(c, a, cc, p, L);
 215 }
 216 
 217 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 218   fbp(c, a, fcc0, p, d, rt);
 219 }
 220 
 221 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
 222   insert_nop_after_cbcond();
 223   fb(c, a, p, target(L));
 224 }
 225 
 226 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
 227   Assembler::fbp(c, a, cc, p, d, rt);
 228 }
 229 
 230 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
 231   Assembler::fbp(c, a, cc, p, L);
 232 }
 233 
 234 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
 235 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
 236 
 237 inline bool MacroAssembler::is_far_target(address d) {
 238   if (ForceUnreachable) {
 239     // References outside the code cache should be treated as far
 240     return d < CodeCache::low_bound() || d > CodeCache::high_bound();
 241   }
 242   return !is_in_wdisp30_range(d, CodeCache::low_bound()) || !is_in_wdisp30_range(d, CodeCache::high_bound());


 252 inline void MacroAssembler::call( address d, RelocationHolder const& rspec ) {
 253   intptr_t disp;
 254   // NULL is ok because it will be relocated later.
 255   // Must change NULL to a reachable address in order to
 256   // pass asserts here and in wdisp.
 257   if ( d == NULL )
 258     d = pc();
 259 
 260   // Is this address within range of the call instruction?
 261   // If not, use the expensive instruction sequence
 262   if (is_far_target(d)) {
 263     relocate(rspec);
 264     AddressLiteral dest(d);
 265     jumpl_to(dest, O7, O7);
 266   } else {
 267     Assembler::call(d, rspec);
 268   }
 269 }
 270 
 271 inline void MacroAssembler::call( Label& L,   relocInfo::relocType rt ) {
 272   insert_nop_after_cbcond();
 273   MacroAssembler::call( target(L), rt);
 274 }
 275 
 276 
 277 
 278 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
 279 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
 280 
 281 // prefetch instruction
 282 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
 283   Assembler::bp( never, true, xcc, pt, d, rt );
 284     Assembler::bp( never, true, xcc, pt, d, rt );
 285 }
 286 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
 287 
 288 inline void MacroAssembler::tst( Register s ) { orcc( G0, s, G0 ); }
 289 
 290 inline void MacroAssembler::ret( bool trace ) {
 291   if (trace) {
 292     mov(I7, O7); // traceable register
 293     JMP(O7, 2 * BytesPerInstWord);
 294   } else {
 295     jmpl( I7, 2 * BytesPerInstWord, G0 );
 296   }
 297 }
 298 
 299 inline void MacroAssembler::retl( bool trace ) {
 300   if (trace) {
 301     JMP(O7, 2 * BytesPerInstWord);
 302   } else {
 303     jmpl( O7, 2 * BytesPerInstWord, G0 );
 304   }
 305 }
 306 
 307 // clobbers o7 on V8!!
 308 // returns delta from gotten pc to addr after
 309 inline int MacroAssembler::get_pc( Register d ) {
 310   int x = offset();
 311   rdpc(d);
 312   return offset() - x;
 313 }
 314 
 315 inline void MacroAssembler::cmp(  Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
 316 inline void MacroAssembler::cmp(  Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
 317 
 318 // Note:  All MacroAssembler::set_foo functions are defined out-of-line.
 319 
 320 
 321 // Loads the current PC of the following instruction as an immediate value in
 322 // 2 instructions.  All PCs in the CodeCache are within 2 Gig of each other.
 323 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
 324   intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
 325   Unimplemented();
 326   return thepc;
 327 }
 328 
 329 
 330 inline void MacroAssembler::load_contents(const AddressLiteral& addrlit, Register d, int offset) {
 331   assert_not_delayed();
 332   if (ForceUnreachable) {
 333     patchable_sethi(addrlit, d);




 168   if (s2.is_register())  sll_ptr(s1, s2.as_register(), d);
 169   else                   sll_ptr(s1, s2.as_constant(), d);
 170 }
 171 
 172 inline void MacroAssembler::casl(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
 173 inline void MacroAssembler::casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
 174 
 175 inline void MacroAssembler::inc(   Register d,  int const13 ) { add(   d, const13, d); }
 176 inline void MacroAssembler::inccc( Register d,  int const13 ) { addcc( d, const13, d); }
 177 
 178 inline void MacroAssembler::dec(   Register d,  int const13 ) { sub(   d, const13, d); }
 179 inline void MacroAssembler::deccc( Register d,  int const13 ) { subcc( d, const13, d); }
 180 
 181 // Use the right branch for the platform
 182 
 183 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 184   Assembler::bp(c, a, icc, p, d, rt);
 185 }
 186 
 187 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
 188   // See note[+] on 'avoid_pipeline_stalls()', in "assembler_sparc.inline.hpp".
 189   avoid_pipeline_stall();
 190   br(c, a, p, target(L));
 191 }
 192 
 193 
 194 // Branch that tests either xcc or icc depending on the
 195 // architecture compiled (LP64 or not)
 196 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 197     Assembler::bp(c, a, xcc, p, d, rt);
 198 }
 199 
 200 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
 201   avoid_pipeline_stall();
 202   brx(c, a, p, target(L));
 203 }
 204 
 205 inline void MacroAssembler::ba( Label& L ) {
 206   br(always, false, pt, L);
 207 }
 208 
 209 // Warning: V9 only functions
 210 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
 211   Assembler::bp(c, a, cc, p, d, rt);
 212 }
 213 
 214 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
 215   Assembler::bp(c, a, cc, p, L);
 216 }
 217 
 218 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
 219   fbp(c, a, fcc0, p, d, rt);
 220 }
 221 
 222 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
 223   avoid_pipeline_stall();
 224   fb(c, a, p, target(L));
 225 }
 226 
 227 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
 228   Assembler::fbp(c, a, cc, p, d, rt);
 229 }
 230 
 231 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
 232   Assembler::fbp(c, a, cc, p, L);
 233 }
 234 
 235 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
 236 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
 237 
 238 inline bool MacroAssembler::is_far_target(address d) {
 239   if (ForceUnreachable) {
 240     // References outside the code cache should be treated as far
 241     return d < CodeCache::low_bound() || d > CodeCache::high_bound();
 242   }
 243   return !is_in_wdisp30_range(d, CodeCache::low_bound()) || !is_in_wdisp30_range(d, CodeCache::high_bound());


 253 inline void MacroAssembler::call( address d, RelocationHolder const& rspec ) {
 254   intptr_t disp;
 255   // NULL is ok because it will be relocated later.
 256   // Must change NULL to a reachable address in order to
 257   // pass asserts here and in wdisp.
 258   if ( d == NULL )
 259     d = pc();
 260 
 261   // Is this address within range of the call instruction?
 262   // If not, use the expensive instruction sequence
 263   if (is_far_target(d)) {
 264     relocate(rspec);
 265     AddressLiteral dest(d);
 266     jumpl_to(dest, O7, O7);
 267   } else {
 268     Assembler::call(d, rspec);
 269   }
 270 }
 271 
 272 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
 273   avoid_pipeline_stall();
 274   MacroAssembler::call(target(L), rt);
 275 }
 276 
 277 

 278 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
 279 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
 280 
 281 // prefetch instruction
 282 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
 283   Assembler::bp( never, true, xcc, pt, d, rt );
 284     Assembler::bp( never, true, xcc, pt, d, rt );
 285 }
 286 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
 287 
 288 inline void MacroAssembler::tst( Register s ) { orcc( G0, s, G0 ); }
 289 
 290 inline void MacroAssembler::ret( bool trace ) {
 291   if (trace) {
 292     mov(I7, O7); // traceable register
 293     JMP(O7, 2 * BytesPerInstWord);
 294   } else {
 295     jmpl( I7, 2 * BytesPerInstWord, G0 );
 296   }
 297 }
 298 
 299 inline void MacroAssembler::retl( bool trace ) {
 300   if (trace) {
 301     JMP(O7, 2 * BytesPerInstWord);
 302   } else {
 303     jmpl( O7, 2 * BytesPerInstWord, G0 );
 304   }
 305 }
 306 







 307 
 308 inline void MacroAssembler::cmp(  Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
 309 inline void MacroAssembler::cmp(  Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
 310 
 311 // Note:  All MacroAssembler::set_foo functions are defined out-of-line.
 312 
 313 
 314 // Loads the current PC of the following instruction as an immediate value in
 315 // 2 instructions.  All PCs in the CodeCache are within 2 Gig of each other.
 316 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
 317   intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
 318   Unimplemented();
 319   return thepc;
 320 }
 321 
 322 
 323 inline void MacroAssembler::load_contents(const AddressLiteral& addrlit, Register d, int offset) {
 324   assert_not_delayed();
 325   if (ForceUnreachable) {
 326     patchable_sethi(addrlit, d);


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