1 // 2 // Copyright (c) 1998, 2017, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 // 64-bit build means 64-bit pointers means hi/lo pairs 315 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 316 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 317 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 318 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 319 // Lock encodings use G3 and G4 internally 320 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 321 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 322 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 323 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 324 // Special class for storeP instructions, which can store SP or RPC to TLS. 325 // It is also used for memory addressing, allowing direct TLS addressing. 326 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 327 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 328 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 329 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 330 // R_L7 is the lowest-priority callee-save (i.e., NS) register 331 // We use it to save R_G2 across calls out of Java. 332 reg_class l7_regP(R_L7H,R_L7); 333 334 // Other special pointer regs 335 reg_class g1_regP(R_G1H,R_G1); 336 reg_class g2_regP(R_G2H,R_G2); 337 reg_class g3_regP(R_G3H,R_G3); 338 reg_class g4_regP(R_G4H,R_G4); 339 reg_class g5_regP(R_G5H,R_G5); 340 reg_class i0_regP(R_I0H,R_I0); 341 reg_class o0_regP(R_O0H,R_O0); 342 reg_class o1_regP(R_O1H,R_O1); 343 reg_class o2_regP(R_O2H,R_O2); 344 reg_class o7_regP(R_O7H,R_O7); 345 346 347 // ---------------------------- 348 // Long Register Classes 349 // ---------------------------- 350 // Longs in 1 register. Aligned adjacent hi/lo pairs. 351 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 352 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 353 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 354 // 64-bit, longs in 1 register: use all 64-bit integer registers 355 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 356 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 357 ); 358 359 reg_class g1_regL(R_G1H,R_G1); 360 reg_class g3_regL(R_G3H,R_G3); 361 reg_class o2_regL(R_O2H,R_O2); 362 reg_class o7_regL(R_O7H,R_O7); 363 364 // ---------------------------- 365 // Special Class for Condition Code Flags Register 366 reg_class int_flags(CCR); 367 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 368 reg_class float_flag0(FCC0); 369 370 371 // ---------------------------- 372 // Float Point Register Classes 373 // ---------------------------- 374 // Skip F30/F31, they are reserved for mem-mem copies 375 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 376 377 // Paired floating point registers--they show up in the same order as the floats, 378 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 379 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 380 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 381 /* Use extra V9 double registers; this AD file does not support V8 */ 382 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 383 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 384 ); 385 386 // Paired floating point registers--they show up in the same order as the floats, 387 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 388 // This class is usable for mis-aligned loads as happen in I2C adapters. 389 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 390 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 391 %} 392 393 //----------DEFINITION BLOCK--------------------------------------------------- 394 // Define name --> value mappings to inform the ADLC of an integer valued name 395 // Current support includes integer values in the range [0, 0x7FFFFFFF] 396 // Format: 397 // int_def <name> ( <int_value>, <expression>); 398 // Generated Code in ad_<arch>.hpp 399 // #define <name> (<expression>) 400 // // value == <int_value> 401 // Generated code in ad_<arch>.cpp adlc_verification() 402 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 403 // 404 definitions %{ 405 // The default cost (of an ALU instruction). 406 int_def DEFAULT_COST ( 100, 100); 407 int_def HUGE_COST (1000000, 1000000); 408 409 // Memory refs are twice as expensive as run-of-the-mill. 410 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 411 412 // Branches are even more expensive. 413 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 414 int_def CALL_COST ( 300, DEFAULT_COST * 3); 415 %} 416 417 418 //----------SOURCE BLOCK------------------------------------------------------- 419 // This is a block of C++ code which provides values, functions, and 420 // definitions necessary in the rest of the architecture description 421 source_hpp %{ 422 // Header information of the source block. 423 // Method declarations/definitions which are used outside 424 // the ad-scope can conveniently be defined here. 425 // 426 // To keep related declarations/definitions/uses close together, 427 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 428 429 // Must be visible to the DFA in dfa_sparc.cpp 430 extern bool can_branch_register( Node *bol, Node *cmp ); 431 432 extern bool use_block_zeroing(Node* count); 433 434 // Macros to extract hi & lo halves from a long pair. 435 // G0 is not part of any long pair, so assert on that. 436 // Prevents accidentally using G1 instead of G0. 437 #define LONG_HI_REG(x) (x) 438 #define LONG_LO_REG(x) (x) 439 440 class CallStubImpl { 441 442 //-------------------------------------------------------------- 443 //---< Used for optimization in Compile::Shorten_branches >--- 444 //-------------------------------------------------------------- 445 446 public: 447 // Size of call trampoline stub. 448 static uint size_call_trampoline() { 449 return 0; // no call trampolines on this platform 450 } 451 452 // number of relocations needed by a call trampoline stub 453 static uint reloc_call_trampoline() { 454 return 0; // no call trampolines on this platform 455 } 456 }; 457 458 class HandlerImpl { 459 460 public: 461 462 static int emit_exception_handler(CodeBuffer &cbuf); 463 static int emit_deopt_handler(CodeBuffer& cbuf); 464 465 static uint size_exception_handler() { 466 return ( NativeJump::instruction_size ); // sethi;jmp;nop 467 } 468 469 static uint size_deopt_handler() { 470 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 471 } 472 }; 473 474 %} 475 476 source %{ 477 #define __ _masm. 478 479 // tertiary op of a LoadP or StoreP encoding 480 #define REGP_OP true 481 482 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 483 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 484 static Register reg_to_register_object(int register_encoding); 485 486 // Used by the DFA in dfa_sparc.cpp. 487 // Check for being able to use a V9 branch-on-register. Requires a 488 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 489 // extended. Doesn't work following an integer ADD, for example, because of 490 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 491 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 492 // replace them with zero, which could become sign-extension in a different OS 493 // release. There's no obvious reason why an interrupt will ever fill these 494 // bits with non-zero junk (the registers are reloaded with standard LD 495 // instructions which either zero-fill or sign-fill). 496 bool can_branch_register( Node *bol, Node *cmp ) { 497 if( !BranchOnRegister ) return false; 498 if( cmp->Opcode() == Op_CmpP ) 499 return true; // No problems with pointer compares 500 if( cmp->Opcode() == Op_CmpL ) 501 return true; // No problems with long compares 502 503 if( !SparcV9RegsHiBitsZero ) return false; 504 if( bol->as_Bool()->_test._test != BoolTest::ne && 505 bol->as_Bool()->_test._test != BoolTest::eq ) 506 return false; 507 508 // Check for comparing against a 'safe' value. Any operation which 509 // clears out the high word is safe. Thus, loads and certain shifts 510 // are safe, as are non-negative constants. Any operation which 511 // preserves zero bits in the high word is safe as long as each of its 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their 513 // inputs are safe. At present, the only important case to recognize 514 // seems to be loads. Constants should fold away, and shifts & 515 // logicals can use the 'cc' forms. 516 Node *x = cmp->in(1); 517 if( x->is_Load() ) return true; 518 if( x->is_Phi() ) { 519 for( uint i = 1; i < x->req(); i++ ) 520 if( !x->in(i)->is_Load() ) 521 return false; 522 return true; 523 } 524 return false; 525 } 526 527 bool use_block_zeroing(Node* count) { 528 // Use BIS for zeroing if count is not constant 529 // or it is >= BlockZeroingLowLimit. 530 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); 531 } 532 533 // **************************************************************************** 534 535 // REQUIRED FUNCTIONALITY 536 537 // !!!!! Special hack to get all type of calls to specify the byte offset 538 // from the start of the call to the point where the return address 539 // will point. 540 // The "return address" is the address of the call instruction, plus 8. 541 542 int MachCallStaticJavaNode::ret_addr_offset() { 543 int offset = NativeCall::instruction_size; // call; delay slot 544 if (_method_handle_invoke) 545 offset += 4; // restore SP 546 return offset; 547 } 548 549 int MachCallDynamicJavaNode::ret_addr_offset() { 550 int vtable_index = this->_vtable_index; 551 if (vtable_index < 0) { 552 // must be invalid_vtable_index, not nonvirtual_vtable_index 553 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 554 return (NativeMovConstReg::instruction_size + 555 NativeCall::instruction_size); // sethi; setlo; call; delay slot 556 } else { 557 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 558 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 559 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 560 int klass_load_size; 561 if (UseCompressedClassPointers) { 562 assert(Universe::heap() != NULL, "java heap should be initialized"); 563 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 564 } else { 565 klass_load_size = 1*BytesPerInstWord; 566 } 567 if (Assembler::is_simm13(v_off)) { 568 return klass_load_size + 569 (2*BytesPerInstWord + // ld_ptr, ld_ptr 570 NativeCall::instruction_size); // call; delay slot 571 } else { 572 return klass_load_size + 573 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 574 NativeCall::instruction_size); // call; delay slot 575 } 576 } 577 } 578 579 int MachCallRuntimeNode::ret_addr_offset() { 580 if (MacroAssembler::is_far_target(entry_point())) { 581 return NativeFarCall::instruction_size; 582 } else { 583 return NativeCall::instruction_size; 584 } 585 } 586 587 // Indicate if the safepoint node needs the polling page as an input. 588 // Since Sparc does not have absolute addressing, it does. 589 bool SafePointNode::needs_polling_address_input() { 590 return true; 591 } 592 593 // emit an interrupt that is caught by the debugger (for debugging compiler) 594 void emit_break(CodeBuffer &cbuf) { 595 MacroAssembler _masm(&cbuf); 596 __ breakpoint_trap(); 597 } 598 599 #ifndef PRODUCT 600 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 601 st->print("TA"); 602 } 603 #endif 604 605 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 606 emit_break(cbuf); 607 } 608 609 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 610 return MachNode::size(ra_); 611 } 612 613 // Traceable jump 614 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 615 MacroAssembler _masm(&cbuf); 616 Register rdest = reg_to_register_object(jump_target); 617 __ JMP(rdest, 0); 618 __ delayed()->nop(); 619 } 620 621 // Traceable jump and set exception pc 622 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 623 MacroAssembler _masm(&cbuf); 624 Register rdest = reg_to_register_object(jump_target); 625 __ JMP(rdest, 0); 626 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 627 } 628 629 void emit_nop(CodeBuffer &cbuf) { 630 MacroAssembler _masm(&cbuf); 631 __ nop(); 632 } 633 634 void emit_illtrap(CodeBuffer &cbuf) { 635 MacroAssembler _masm(&cbuf); 636 __ illtrap(0); 637 } 638 639 640 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 641 assert(n->rule() != loadUB_rule, ""); 642 643 intptr_t offset = 0; 644 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 645 const Node* addr = n->get_base_and_disp(offset, adr_type); 646 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 647 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 648 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 649 atype = atype->add_offset(offset); 650 assert(disp32 == offset, "wrong disp32"); 651 return atype->_offset; 652 } 653 654 655 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 656 assert(n->rule() != loadUB_rule, ""); 657 658 intptr_t offset = 0; 659 Node* addr = n->in(2); 660 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 661 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 662 Node* a = addr->in(2/*AddPNode::Address*/); 663 Node* o = addr->in(3/*AddPNode::Offset*/); 664 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 665 atype = a->bottom_type()->is_ptr()->add_offset(offset); 666 assert(atype->isa_oop_ptr(), "still an oop"); 667 } 668 offset = atype->is_ptr()->_offset; 669 if (offset != Type::OffsetBot) offset += disp32; 670 return offset; 671 } 672 673 static inline jlong replicate_immI(int con, int count, int width) { 674 // Load a constant replicated "count" times with width "width" 675 assert(count*width == 8 && width <= 4, "sanity"); 676 int bit_width = width * 8; 677 jlong val = con; 678 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 679 for (int i = 0; i < count - 1; i++) { 680 val |= (val << bit_width); 681 } 682 return val; 683 } 684 685 static inline jlong replicate_immF(float con) { 686 // Replicate float con 2 times and pack into vector. 687 int val = *((int*)&con); 688 jlong lval = val; 689 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 690 return lval; 691 } 692 693 // Standard Sparc opcode form2 field breakdown 694 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 695 f0 &= (1<<19)-1; // Mask displacement to 19 bits 696 int op = (f30 << 30) | 697 (f29 << 29) | 698 (f25 << 25) | 699 (f22 << 22) | 700 (f20 << 20) | 701 (f19 << 19) | 702 (f0 << 0); 703 cbuf.insts()->emit_int32(op); 704 } 705 706 // Standard Sparc opcode form2 field breakdown 707 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 708 f0 >>= 10; // Drop 10 bits 709 f0 &= (1<<22)-1; // Mask displacement to 22 bits 710 int op = (f30 << 30) | 711 (f25 << 25) | 712 (f22 << 22) | 713 (f0 << 0); 714 cbuf.insts()->emit_int32(op); 715 } 716 717 // Standard Sparc opcode form3 field breakdown 718 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 719 int op = (f30 << 30) | 720 (f25 << 25) | 721 (f19 << 19) | 722 (f14 << 14) | 723 (f5 << 5) | 724 (f0 << 0); 725 cbuf.insts()->emit_int32(op); 726 } 727 728 // Standard Sparc opcode form3 field breakdown 729 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 730 simm13 &= (1<<13)-1; // Mask to 13 bits 731 int op = (f30 << 30) | 732 (f25 << 25) | 733 (f19 << 19) | 734 (f14 << 14) | 735 (1 << 13) | // bit to indicate immediate-mode 736 (simm13<<0); 737 cbuf.insts()->emit_int32(op); 738 } 739 740 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 741 simm10 &= (1<<10)-1; // Mask to 10 bits 742 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 743 } 744 745 #ifdef ASSERT 746 // Helper function for VerifyOops in emit_form3_mem_reg 747 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 748 warning("VerifyOops encountered unexpected instruction:"); 749 n->dump(2); 750 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 751 } 752 #endif 753 754 755 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, 756 int src1_enc, int disp32, int src2_enc, int dst_enc) { 757 758 #ifdef ASSERT 759 // The following code implements the +VerifyOops feature. 760 // It verifies oop values which are loaded into or stored out of 761 // the current method activation. +VerifyOops complements techniques 762 // like ScavengeALot, because it eagerly inspects oops in transit, 763 // as they enter or leave the stack, as opposed to ScavengeALot, 764 // which inspects oops "at rest", in the stack or heap, at safepoints. 765 // For this reason, +VerifyOops can sometimes detect bugs very close 766 // to their point of creation. It can also serve as a cross-check 767 // on the validity of oop maps, when used toegether with ScavengeALot. 768 769 // It would be good to verify oops at other points, especially 770 // when an oop is used as a base pointer for a load or store. 771 // This is presently difficult, because it is hard to know when 772 // a base address is biased or not. (If we had such information, 773 // it would be easy and useful to make a two-argument version of 774 // verify_oop which unbiases the base, and performs verification.) 775 776 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 777 bool is_verified_oop_base = false; 778 bool is_verified_oop_load = false; 779 bool is_verified_oop_store = false; 780 int tmp_enc = -1; 781 if (VerifyOops && src1_enc != R_SP_enc) { 782 // classify the op, mainly for an assert check 783 int st_op = 0, ld_op = 0; 784 switch (primary) { 785 case Assembler::stb_op3: st_op = Op_StoreB; break; 786 case Assembler::sth_op3: st_op = Op_StoreC; break; 787 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 788 case Assembler::stw_op3: st_op = Op_StoreI; break; 789 case Assembler::std_op3: st_op = Op_StoreL; break; 790 case Assembler::stf_op3: st_op = Op_StoreF; break; 791 case Assembler::stdf_op3: st_op = Op_StoreD; break; 792 793 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 794 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; 795 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 796 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 797 case Assembler::ldx_op3: // may become LoadP or stay LoadI 798 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 799 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 800 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 801 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 802 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 803 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 804 805 default: ShouldNotReachHere(); 806 } 807 if (tertiary == REGP_OP) { 808 if (st_op == Op_StoreI) st_op = Op_StoreP; 809 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 810 else ShouldNotReachHere(); 811 if (st_op) { 812 // a store 813 // inputs are (0:control, 1:memory, 2:address, 3:value) 814 Node* n2 = n->in(3); 815 if (n2 != NULL) { 816 const Type* t = n2->bottom_type(); 817 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 818 } 819 } else { 820 // a load 821 const Type* t = n->bottom_type(); 822 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 823 } 824 } 825 826 if (ld_op) { 827 // a Load 828 // inputs are (0:control, 1:memory, 2:address) 829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 830 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 831 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 832 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 833 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 834 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 835 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 836 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 837 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 838 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 839 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 840 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && 841 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && 842 !(n->rule() == loadUB_rule)) { 843 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 844 } 845 } else if (st_op) { 846 // a Store 847 // inputs are (0:control, 1:memory, 2:address, 3:value) 848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 853 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && 854 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 855 verify_oops_warning(n, n->ideal_Opcode(), st_op); 856 } 857 } 858 859 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 860 Node* addr = n->in(2); 861 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 862 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 863 if (atype != NULL) { 864 intptr_t offset = get_offset_from_base(n, atype, disp32); 865 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 866 if (offset != offset_2) { 867 get_offset_from_base(n, atype, disp32); 868 get_offset_from_base_2(n, atype, disp32); 869 } 870 assert(offset == offset_2, "different offsets"); 871 if (offset == disp32) { 872 // we now know that src1 is a true oop pointer 873 is_verified_oop_base = true; 874 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 875 if( primary == Assembler::ldd_op3 ) { 876 is_verified_oop_base = false; // Cannot 'ldd' into O7 877 } else { 878 tmp_enc = dst_enc; 879 dst_enc = R_O7_enc; // Load into O7; preserve source oop 880 assert(src1_enc != dst_enc, ""); 881 } 882 } 883 } 884 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 885 || offset == oopDesc::mark_offset_in_bytes())) { 886 // loading the mark should not be allowed either, but 887 // we don't check this since it conflicts with InlineObjectHash 888 // usage of LoadINode to get the mark. We could keep the 889 // check if we create a new LoadMarkNode 890 // but do not verify the object before its header is initialized 891 ShouldNotReachHere(); 892 } 893 } 894 } 895 } 896 } 897 #endif 898 899 uint instr = (Assembler::ldst_op << 30) 900 | (dst_enc << 25) 901 | (primary << 19) 902 | (src1_enc << 14); 903 904 uint index = src2_enc; 905 int disp = disp32; 906 907 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { 908 disp += STACK_BIAS; 909 // Check that stack offset fits, load into O7 if not 910 if (!Assembler::is_simm13(disp)) { 911 MacroAssembler _masm(&cbuf); 912 __ set(disp, O7); 913 if (index != R_G0_enc) { 914 __ add(O7, reg_to_register_object(index), O7); 915 } 916 index = R_O7_enc; 917 disp = 0; 918 } 919 } 920 921 if( disp == 0 ) { 922 // use reg-reg form 923 // bit 13 is already zero 924 instr |= index; 925 } else { 926 // use reg-imm form 927 instr |= 0x00002000; // set bit 13 to one 928 instr |= disp & 0x1FFF; 929 } 930 931 cbuf.insts()->emit_int32(instr); 932 933 #ifdef ASSERT 934 if (VerifyOops) { 935 MacroAssembler _masm(&cbuf); 936 if (is_verified_oop_base) { 937 __ verify_oop(reg_to_register_object(src1_enc)); 938 } 939 if (is_verified_oop_store) { 940 __ verify_oop(reg_to_register_object(dst_enc)); 941 } 942 if (tmp_enc != -1) { 943 __ mov(O7, reg_to_register_object(tmp_enc)); 944 } 945 if (is_verified_oop_load) { 946 __ verify_oop(reg_to_register_object(dst_enc)); 947 } 948 } 949 #endif 950 } 951 952 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) { 953 // The method which records debug information at every safepoint 954 // expects the call to be the first instruction in the snippet as 955 // it creates a PcDesc structure which tracks the offset of a call 956 // from the start of the codeBlob. This offset is computed as 957 // code_end() - code_begin() of the code which has been emitted 958 // so far. 959 // In this particular case we have skirted around the problem by 960 // putting the "mov" instruction in the delay slot but the problem 961 // may bite us again at some other point and a cleaner/generic 962 // solution using relocations would be needed. 963 MacroAssembler _masm(&cbuf); 964 __ set_inst_mark(); 965 966 // We flush the current window just so that there is a valid stack copy 967 // the fact that the current window becomes active again instantly is 968 // not a problem there is nothing live in it. 969 970 #ifdef ASSERT 971 int startpos = __ offset(); 972 #endif /* ASSERT */ 973 974 __ call((address)entry_point, rspec); 975 976 if (preserve_g2) __ delayed()->mov(G2, L7); 977 else __ delayed()->nop(); 978 979 if (preserve_g2) __ mov(L7, G2); 980 981 #ifdef ASSERT 982 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 983 // Trash argument dump slots. 984 __ set(0xb0b8ac0db0b8ac0d, G1); 985 __ mov(G1, G5); 986 __ stx(G1, SP, STACK_BIAS + 0x80); 987 __ stx(G1, SP, STACK_BIAS + 0x88); 988 __ stx(G1, SP, STACK_BIAS + 0x90); 989 __ stx(G1, SP, STACK_BIAS + 0x98); 990 __ stx(G1, SP, STACK_BIAS + 0xA0); 991 __ stx(G1, SP, STACK_BIAS + 0xA8); 992 } 993 #endif /*ASSERT*/ 994 } 995 996 //============================================================================= 997 // REQUIRED FUNCTIONALITY for encoding 998 void emit_lo(CodeBuffer &cbuf, int val) { } 999 void emit_hi(CodeBuffer &cbuf, int val) { } 1000 1001 1002 //============================================================================= 1003 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); 1004 1005 int Compile::ConstantTable::calculate_table_base_offset() const { 1006 if (UseRDPCForConstantTableBase) { 1007 // The table base offset might be less but then it fits into 1008 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). 1009 return Assembler::min_simm13(); 1010 } else { 1011 int offset = -(size() / 2); 1012 if (!Assembler::is_simm13(offset)) { 1013 offset = Assembler::min_simm13(); 1014 } 1015 return offset; 1016 } 1017 } 1018 1019 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 1020 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1021 ShouldNotReachHere(); 1022 } 1023 1024 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1025 Compile* C = ra_->C; 1026 Compile::ConstantTable& constant_table = C->constant_table(); 1027 MacroAssembler _masm(&cbuf); 1028 1029 Register r = as_Register(ra_->get_encode(this)); 1030 CodeSection* consts_section = __ code()->consts(); 1031 int consts_size = consts_section->align_at_start(consts_section->size()); 1032 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size); 1033 1034 if (UseRDPCForConstantTableBase) { 1035 // For the following RDPC logic to work correctly the consts 1036 // section must be allocated right before the insts section. This 1037 // assert checks for that. The layout and the SECT_* constants 1038 // are defined in src/share/vm/asm/codeBuffer.hpp. 1039 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1040 int insts_offset = __ offset(); 1041 1042 // Layout: 1043 // 1044 // |----------- consts section ------------|----------- insts section -----------... 1045 // |------ constant table -----|- padding -|------------------x---- 1046 // \ current PC (RDPC instruction) 1047 // |<------------- consts_size ----------->|<- insts_offset ->| 1048 // \ table base 1049 // The table base offset is later added to the load displacement 1050 // so it has to be negative. 1051 int table_base_offset = -(consts_size + insts_offset); 1052 int disp; 1053 1054 // If the displacement from the current PC to the constant table 1055 // base fits into simm13 we set the constant table base to the 1056 // current PC. 1057 if (Assembler::is_simm13(table_base_offset)) { 1058 constant_table.set_table_base_offset(table_base_offset); 1059 disp = 0; 1060 } else { 1061 // Otherwise we set the constant table base offset to the 1062 // maximum negative displacement of load instructions to keep 1063 // the disp as small as possible: 1064 // 1065 // |<------------- consts_size ----------->|<- insts_offset ->| 1066 // |<--------- min_simm13 --------->|<-------- disp --------->| 1067 // \ table base 1068 table_base_offset = Assembler::min_simm13(); 1069 constant_table.set_table_base_offset(table_base_offset); 1070 disp = (consts_size + insts_offset) + table_base_offset; 1071 } 1072 1073 __ rdpc(r); 1074 1075 if (disp == 0) { 1076 // Emitting an additional 'nop' instruction in order not to cause a code 1077 // size adjustment in the code following the table setup (if the instruction 1078 // immediately following after this section is a CTI). 1079 __ nop(); 1080 } 1081 else { 1082 assert(r != O7, "need temporary"); 1083 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1084 } 1085 } 1086 else { 1087 // Materialize the constant table base. 1088 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1089 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1090 AddressLiteral base(baseaddr, rspec); 1091 __ set(base, r); 1092 } 1093 } 1094 1095 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1096 if (UseRDPCForConstantTableBase) { 1097 // This is really the worst case but generally it's only 1 instruction. 1098 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1099 } else { 1100 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1101 } 1102 } 1103 1104 #ifndef PRODUCT 1105 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1106 char reg[128]; 1107 ra_->dump_register(this, reg); 1108 if (UseRDPCForConstantTableBase) { 1109 st->print("RDPC %s\t! constant table base", reg); 1110 } else { 1111 st->print("SET &constanttable,%s\t! constant table base", reg); 1112 } 1113 } 1114 #endif 1115 1116 1117 //============================================================================= 1118 1119 #ifndef PRODUCT 1120 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1121 Compile* C = ra_->C; 1122 1123 for (int i = 0; i < OptoPrologueNops; i++) { 1124 st->print_cr("NOP"); st->print("\t"); 1125 } 1126 1127 if( VerifyThread ) { 1128 st->print_cr("Verify_Thread"); st->print("\t"); 1129 } 1130 1131 size_t framesize = C->frame_size_in_bytes(); 1132 int bangsize = C->bang_size_in_bytes(); 1133 1134 // Calls to C2R adapters often do not accept exceptional returns. 1135 // We require that their callers must bang for them. But be careful, because 1136 // some VM calls (such as call site linkage) can use several kilobytes of 1137 // stack. But the stack safety zone should account for that. 1138 // See bugs 4446381, 4468289, 4497237. 1139 if (C->need_stack_bang(bangsize)) { 1140 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); 1141 } 1142 1143 if (Assembler::is_simm13(-framesize)) { 1144 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize); 1145 } else { 1146 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1147 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1148 st->print ("SAVE R_SP,R_G3,R_SP"); 1149 } 1150 1151 } 1152 #endif 1153 1154 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1155 Compile* C = ra_->C; 1156 MacroAssembler _masm(&cbuf); 1157 1158 for (int i = 0; i < OptoPrologueNops; i++) { 1159 __ nop(); 1160 } 1161 1162 __ verify_thread(); 1163 1164 size_t framesize = C->frame_size_in_bytes(); 1165 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1166 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1167 int bangsize = C->bang_size_in_bytes(); 1168 1169 // Calls to C2R adapters often do not accept exceptional returns. 1170 // We require that their callers must bang for them. But be careful, because 1171 // some VM calls (such as call site linkage) can use several kilobytes of 1172 // stack. But the stack safety zone should account for that. 1173 // See bugs 4446381, 4468289, 4497237. 1174 if (C->need_stack_bang(bangsize)) { 1175 __ generate_stack_overflow_check(bangsize); 1176 } 1177 1178 if (Assembler::is_simm13(-framesize)) { 1179 __ save(SP, -framesize, SP); 1180 } else { 1181 __ sethi(-framesize & ~0x3ff, G3); 1182 __ add(G3, -framesize & 0x3ff, G3); 1183 __ save(SP, G3, SP); 1184 } 1185 C->set_frame_complete( __ offset() ); 1186 1187 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { 1188 // NOTE: We set the table base offset here because users might be 1189 // emitted before MachConstantBaseNode. 1190 Compile::ConstantTable& constant_table = C->constant_table(); 1191 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 1192 } 1193 } 1194 1195 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1196 return MachNode::size(ra_); 1197 } 1198 1199 int MachPrologNode::reloc() const { 1200 return 10; // a large enough number 1201 } 1202 1203 //============================================================================= 1204 #ifndef PRODUCT 1205 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1206 Compile* C = ra_->C; 1207 1208 if(do_polling() && ra_->C->is_method_compilation()) { 1209 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1210 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1211 } 1212 1213 if(do_polling()) { 1214 if (UseCBCond && !ra_->C->is_method_compilation()) { 1215 st->print("NOP\n\t"); 1216 } 1217 st->print("RET\n\t"); 1218 } 1219 1220 st->print("RESTORE"); 1221 } 1222 #endif 1223 1224 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1225 MacroAssembler _masm(&cbuf); 1226 Compile* C = ra_->C; 1227 1228 __ verify_thread(); 1229 1230 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 1231 __ reserved_stack_check(); 1232 } 1233 1234 // If this does safepoint polling, then do it here 1235 if(do_polling() && ra_->C->is_method_compilation()) { 1236 AddressLiteral polling_page(os::get_polling_page()); 1237 __ sethi(polling_page, L0); 1238 __ relocate(relocInfo::poll_return_type); 1239 __ ld_ptr(L0, 0, G0); 1240 } 1241 1242 // If this is a return, then stuff the restore in the delay slot 1243 if(do_polling()) { 1244 if (UseCBCond && !ra_->C->is_method_compilation()) { 1245 // Insert extra padding for the case when the epilogue is preceded by 1246 // a cbcond jump, which can't be followed by a CTI instruction 1247 __ nop(); 1248 } 1249 __ ret(); 1250 __ delayed()->restore(); 1251 } else { 1252 __ restore(); 1253 } 1254 } 1255 1256 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1257 return MachNode::size(ra_); 1258 } 1259 1260 int MachEpilogNode::reloc() const { 1261 return 16; // a large enough number 1262 } 1263 1264 const Pipeline * MachEpilogNode::pipeline() const { 1265 return MachNode::pipeline_class(); 1266 } 1267 1268 int MachEpilogNode::safepoint_offset() const { 1269 assert( do_polling(), "no return for this epilog node"); 1270 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1271 } 1272 1273 //============================================================================= 1274 1275 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1276 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1277 static enum RC rc_class( OptoReg::Name reg ) { 1278 if (!OptoReg::is_valid(reg)) return rc_bad; 1279 if (OptoReg::is_stack(reg)) return rc_stack; 1280 VMReg r = OptoReg::as_VMReg(reg); 1281 if (r->is_Register()) return rc_int; 1282 assert(r->is_FloatRegister(), "must be"); 1283 return rc_float; 1284 } 1285 1286 #ifndef PRODUCT 1287 ATTRIBUTE_PRINTF(2, 3) 1288 static void print_helper(outputStream* st, const char* format, ...) { 1289 if (st->position() > 0) { 1290 st->cr(); 1291 st->sp(); 1292 } 1293 va_list ap; 1294 va_start(ap, format); 1295 st->vprint(format, ap); 1296 va_end(ap); 1297 } 1298 #endif // !PRODUCT 1299 1300 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) { 1301 if (cbuf) { 1302 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1303 } 1304 #ifndef PRODUCT 1305 else { 1306 if (is_load) { 1307 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg)); 1308 } else { 1309 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset); 1310 } 1311 } 1312 #endif 1313 } 1314 1315 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) { 1316 if (cbuf) { 1317 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]); 1318 } 1319 #ifndef PRODUCT 1320 else { 1321 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst)); 1322 } 1323 #endif 1324 } 1325 1326 static void mach_spill_copy_implementation_helper(const MachNode* mach, 1327 CodeBuffer *cbuf, 1328 PhaseRegAlloc *ra_, 1329 outputStream* st) { 1330 // Get registers to move 1331 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1)); 1332 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1)); 1333 OptoReg::Name dst_second = ra_->get_reg_second(mach); 1334 OptoReg::Name dst_first = ra_->get_reg_first(mach); 1335 1336 enum RC src_second_rc = rc_class(src_second); 1337 enum RC src_first_rc = rc_class(src_first); 1338 enum RC dst_second_rc = rc_class(dst_second); 1339 enum RC dst_first_rc = rc_class(dst_first); 1340 1341 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register"); 1342 1343 if (src_first == dst_first && src_second == dst_second) { 1344 return; // Self copy, no move 1345 } 1346 1347 // -------------------------------------- 1348 // Check for mem-mem move. Load into unused float registers and fall into 1349 // the float-store case. 1350 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) { 1351 int offset = ra_->reg2offset(src_first); 1352 // Further check for aligned-adjacent pair, so we can use a double load 1353 if ((src_first&1) == 0 && src_first+1 == src_second) { 1354 src_second = OptoReg::Name(R_F31_num); 1355 src_second_rc = rc_float; 1356 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st); 1357 } else { 1358 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st); 1359 } 1360 src_first = OptoReg::Name(R_F30_num); 1361 src_first_rc = rc_float; 1362 } 1363 1364 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1365 int offset = ra_->reg2offset(src_second); 1366 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st); 1367 src_second = OptoReg::Name(R_F31_num); 1368 src_second_rc = rc_float; 1369 } 1370 1371 // -------------------------------------- 1372 // Check for float->int copy; requires a trip through memory 1373 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1374 int offset = frame::register_save_words*wordSize; 1375 if (cbuf) { 1376 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16); 1377 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1378 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1379 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16); 1380 } 1381 #ifndef PRODUCT 1382 else { 1383 print_helper(st, "SUB R_SP,16,R_SP"); 1384 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1385 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1386 print_helper(st, "ADD R_SP,16,R_SP"); 1387 } 1388 #endif 1389 } 1390 1391 // Check for float->int copy on T4 1392 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1393 // Further check for aligned-adjacent pair, so we can use a double move 1394 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1395 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st); 1396 return; 1397 } 1398 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st); 1399 } 1400 // Check for int->float copy on T4 1401 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1402 // Further check for aligned-adjacent pair, so we can use a double move 1403 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1404 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st); 1405 return; 1406 } 1407 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st); 1408 } 1409 1410 // -------------------------------------- 1411 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1412 // In such cases, I have to do the big-endian swap. For aligned targets, the 1413 // hardware does the flop for me. Doubles are always aligned, so no problem 1414 // there. Misaligned sources only come from native-long-returns (handled 1415 // special below). 1416 1417 // -------------------------------------- 1418 // Check for integer reg-reg copy 1419 if (src_first_rc == rc_int && dst_first_rc == rc_int) { 1420 // Else normal reg-reg copy 1421 assert(src_second != dst_first, "smashed second before evacuating it"); 1422 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st); 1423 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers"); 1424 // This moves an aligned adjacent pair. 1425 // See if we are done. 1426 if (src_first + 1 == src_second && dst_first + 1 == dst_second) { 1427 return; 1428 } 1429 } 1430 1431 // Check for integer store 1432 if (src_first_rc == rc_int && dst_first_rc == rc_stack) { 1433 int offset = ra_->reg2offset(dst_first); 1434 // Further check for aligned-adjacent pair, so we can use a double store 1435 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1436 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st); 1437 return; 1438 } 1439 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st); 1440 } 1441 1442 // Check for integer load 1443 if (dst_first_rc == rc_int && src_first_rc == rc_stack) { 1444 int offset = ra_->reg2offset(src_first); 1445 // Further check for aligned-adjacent pair, so we can use a double load 1446 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1447 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st); 1448 return; 1449 } 1450 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1451 } 1452 1453 // Check for float reg-reg copy 1454 if (src_first_rc == rc_float && dst_first_rc == rc_float) { 1455 // Further check for aligned-adjacent pair, so we can use a double move 1456 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1457 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st); 1458 return; 1459 } 1460 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st); 1461 } 1462 1463 // Check for float store 1464 if (src_first_rc == rc_float && dst_first_rc == rc_stack) { 1465 int offset = ra_->reg2offset(dst_first); 1466 // Further check for aligned-adjacent pair, so we can use a double store 1467 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1468 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st); 1469 return; 1470 } 1471 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1472 } 1473 1474 // Check for float load 1475 if (dst_first_rc == rc_float && src_first_rc == rc_stack) { 1476 int offset = ra_->reg2offset(src_first); 1477 // Further check for aligned-adjacent pair, so we can use a double load 1478 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1479 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st); 1480 return; 1481 } 1482 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st); 1483 } 1484 1485 // -------------------------------------------------------------------- 1486 // Check for hi bits still needing moving. Only happens for misaligned 1487 // arguments to native calls. 1488 if (src_second == dst_second) { 1489 return; // Self copy; no move 1490 } 1491 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad"); 1492 1493 Unimplemented(); 1494 } 1495 1496 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, 1497 PhaseRegAlloc *ra_, 1498 bool do_size, 1499 outputStream* st) const { 1500 assert(!do_size, "not supported"); 1501 mach_spill_copy_implementation_helper(this, cbuf, ra_, st); 1502 return 0; 1503 } 1504 1505 #ifndef PRODUCT 1506 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1507 implementation( NULL, ra_, false, st ); 1508 } 1509 #endif 1510 1511 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1512 implementation( &cbuf, ra_, false, NULL ); 1513 } 1514 1515 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1516 return MachNode::size(ra_); 1517 } 1518 1519 //============================================================================= 1520 #ifndef PRODUCT 1521 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const { 1522 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1523 } 1524 #endif 1525 1526 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1527 MacroAssembler _masm(&cbuf); 1528 for (int i = 0; i < _count; i += 1) { 1529 __ nop(); 1530 } 1531 } 1532 1533 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1534 return 4 * _count; 1535 } 1536 1537 1538 //============================================================================= 1539 #ifndef PRODUCT 1540 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1541 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1542 int reg = ra_->get_reg_first(this); 1543 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1544 } 1545 #endif 1546 1547 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1548 MacroAssembler _masm(&cbuf); 1549 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1550 int reg = ra_->get_encode(this); 1551 1552 if (Assembler::is_simm13(offset)) { 1553 __ add(SP, offset, reg_to_register_object(reg)); 1554 } else { 1555 __ set(offset, O7); 1556 __ add(SP, O7, reg_to_register_object(reg)); 1557 } 1558 } 1559 1560 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1561 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1562 assert(ra_ == ra_->C->regalloc(), "sanity"); 1563 return ra_->C->scratch_emit_size(this); 1564 } 1565 1566 //============================================================================= 1567 #ifndef PRODUCT 1568 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1569 st->print_cr("\nUEP:"); 1570 if (UseCompressedClassPointers) { 1571 assert(Universe::heap() != NULL, "java heap should be initialized"); 1572 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1573 if (Universe::narrow_klass_base() != 0) { 1574 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); 1575 if (Universe::narrow_klass_shift() != 0) { 1576 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1577 } 1578 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1579 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); 1580 } else { 1581 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1582 } 1583 } else { 1584 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1585 } 1586 st->print_cr("\tCMP R_G5,R_G3" ); 1587 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1588 } 1589 #endif 1590 1591 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1592 MacroAssembler _masm(&cbuf); 1593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1594 Register temp_reg = G3; 1595 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1596 1597 // Load klass from receiver 1598 __ load_klass(O0, temp_reg); 1599 // Compare against expected klass 1600 __ cmp(temp_reg, G5_ic_reg); 1601 // Branch to miss code, checks xcc or icc depending 1602 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1603 } 1604 1605 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1606 return MachNode::size(ra_); 1607 } 1608 1609 1610 //============================================================================= 1611 1612 1613 // Emit exception handler code. 1614 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { 1615 Register temp_reg = G3; 1616 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1617 MacroAssembler _masm(&cbuf); 1618 1619 address base = __ start_a_stub(size_exception_handler()); 1620 if (base == NULL) { 1621 ciEnv::current()->record_failure("CodeCache is full"); 1622 return 0; // CodeBuffer::expand failed 1623 } 1624 1625 int offset = __ offset(); 1626 1627 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1628 __ delayed()->nop(); 1629 1630 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1631 1632 __ end_a_stub(); 1633 1634 return offset; 1635 } 1636 1637 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1638 // Can't use any of the current frame's registers as we may have deopted 1639 // at a poll and everything (including G3) can be live. 1640 Register temp_reg = L0; 1641 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1642 MacroAssembler _masm(&cbuf); 1643 1644 address base = __ start_a_stub(size_deopt_handler()); 1645 if (base == NULL) { 1646 ciEnv::current()->record_failure("CodeCache is full"); 1647 return 0; // CodeBuffer::expand failed 1648 } 1649 1650 int offset = __ offset(); 1651 __ save_frame(0); 1652 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1653 __ delayed()->restore(); 1654 1655 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1656 1657 __ end_a_stub(); 1658 return offset; 1659 1660 } 1661 1662 // Given a register encoding, produce a Integer Register object 1663 static Register reg_to_register_object(int register_encoding) { 1664 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1665 return as_Register(register_encoding); 1666 } 1667 1668 // Given a register encoding, produce a single-precision Float Register object 1669 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1670 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1671 return as_SingleFloatRegister(register_encoding); 1672 } 1673 1674 // Given a register encoding, produce a double-precision Float Register object 1675 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1676 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1677 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1678 return as_DoubleFloatRegister(register_encoding); 1679 } 1680 1681 const bool Matcher::match_rule_supported(int opcode) { 1682 if (!has_match_rule(opcode)) 1683 return false; 1684 1685 switch (opcode) { 1686 case Op_CountLeadingZerosI: 1687 case Op_CountLeadingZerosL: 1688 case Op_CountTrailingZerosI: 1689 case Op_CountTrailingZerosL: 1690 case Op_PopCountI: 1691 case Op_PopCountL: 1692 if (!UsePopCountInstruction) 1693 return false; 1694 case Op_CompareAndSwapL: 1695 case Op_CompareAndSwapP: 1696 if (!VM_Version::supports_cx8()) 1697 return false; 1698 break; 1699 } 1700 1701 return true; // Per default match rules are supported. 1702 } 1703 1704 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 1705 1706 // TODO 1707 // identify extra cases that we might want to provide match rules for 1708 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 1709 bool ret_value = match_rule_supported(opcode); 1710 // Add rules here. 1711 1712 return ret_value; // Per default match rules are supported. 1713 } 1714 1715 const bool Matcher::has_predicated_vectors(void) { 1716 return false; 1717 } 1718 1719 const int Matcher::float_pressure(int default_pressure_threshold) { 1720 return default_pressure_threshold; 1721 } 1722 1723 int Matcher::regnum_to_fpu_offset(int regnum) { 1724 return regnum - 32; // The FP registers are in the second chunk 1725 } 1726 1727 #ifdef ASSERT 1728 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1729 #endif 1730 1731 // Vector width in bytes 1732 const int Matcher::vector_width_in_bytes(BasicType bt) { 1733 assert(MaxVectorSize == 8, ""); 1734 return 8; 1735 } 1736 1737 // Vector ideal reg 1738 const uint Matcher::vector_ideal_reg(int size) { 1739 assert(MaxVectorSize == 8, ""); 1740 return Op_RegD; 1741 } 1742 1743 const uint Matcher::vector_shift_count_ideal_reg(int size) { 1744 fatal("vector shift is not supported"); 1745 return Node::NotAMachineReg; 1746 } 1747 1748 // Limits on vector size (number of elements) loaded into vector. 1749 const int Matcher::max_vector_size(const BasicType bt) { 1750 assert(is_java_primitive(bt), "only primitive type vectors"); 1751 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1752 } 1753 1754 const int Matcher::min_vector_size(const BasicType bt) { 1755 return max_vector_size(bt); // Same as max. 1756 } 1757 1758 // SPARC doesn't support misaligned vectors store/load. 1759 const bool Matcher::misaligned_vectors_ok() { 1760 return false; 1761 } 1762 1763 // Current (2013) SPARC platforms need to read original key 1764 // to construct decryption expanded key 1765 const bool Matcher::pass_original_key_for_aes() { 1766 return true; 1767 } 1768 1769 // NOTE: All currently supported SPARC HW provides fast conversion. 1770 const bool Matcher::convL2FSupported(void) { return true; } 1771 1772 // Is this branch offset short enough that a short branch can be used? 1773 // 1774 // NOTE: If the platform does not provide any short branch variants, then 1775 // this method should return false for offset 0. 1776 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1777 // The passed offset is relative to address of the branch. 1778 // Don't need to adjust the offset. 1779 return UseCBCond && Assembler::is_simm12(offset); 1780 } 1781 1782 const bool Matcher::isSimpleConstant64(jlong value) { 1783 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1784 // Depends on optimizations in MacroAssembler::setx. 1785 int hi = (int)(value >> 32); 1786 int lo = (int)(value & ~0); 1787 return (hi == 0) || (hi == -1) || (lo == 0); 1788 } 1789 1790 // No scaling for the parameter the ClearArray node. 1791 const bool Matcher::init_array_count_is_in_bytes = true; 1792 1793 // No additional cost for CMOVL. 1794 const int Matcher::long_cmove_cost() { return 0; } 1795 1796 // CMOVF/CMOVD are expensive on e.g., T4 and SPARC64. 1797 const int Matcher::float_cmove_cost() { 1798 return VM_Version::has_fast_cmove() ? 0 : ConditionalMoveLimit; 1799 } 1800 1801 // Does the CPU require late expand (see block.cpp for description of late expand)? 1802 const bool Matcher::require_postalloc_expand = false; 1803 1804 // Do we need to mask the count passed to shift instructions or does 1805 // the cpu only look at the lower 5/6 bits anyway? 1806 const bool Matcher::need_masked_shift_count = false; 1807 1808 bool Matcher::narrow_oop_use_complex_address() { 1809 assert(UseCompressedOops, "only for compressed oops code"); 1810 return false; 1811 } 1812 1813 bool Matcher::narrow_klass_use_complex_address() { 1814 assert(UseCompressedClassPointers, "only for compressed klass code"); 1815 return false; 1816 } 1817 1818 bool Matcher::const_oop_prefer_decode() { 1819 // TODO: Check if loading ConP from TOC in heap-based mode is better: 1820 // Prefer ConN+DecodeN over ConP in simple compressed oops mode. 1821 // return Universe::narrow_oop_base() == NULL; 1822 return true; 1823 } 1824 1825 bool Matcher::const_klass_prefer_decode() { 1826 // TODO: Check if loading ConP from TOC in heap-based mode is better: 1827 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 1828 // return Universe::narrow_klass_base() == NULL; 1829 return true; 1830 } 1831 1832 // Is it better to copy float constants, or load them directly from memory? 1833 // Intel can load a float constant from a direct address, requiring no 1834 // extra registers. Most RISCs will have to materialize an address into a 1835 // register first, so they would do better to copy the constant from stack. 1836 const bool Matcher::rematerialize_float_constants = false; 1837 1838 // If CPU can load and store mis-aligned doubles directly then no fixup is 1839 // needed. Else we split the double into 2 integer pieces and move it 1840 // piece-by-piece. Only happens when passing doubles into C code as the 1841 // Java calling convention forces doubles to be aligned. 1842 const bool Matcher::misaligned_doubles_ok = true; 1843 1844 // No-op on SPARC. 1845 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1846 } 1847 1848 // Advertise here if the CPU requires explicit rounding operations 1849 // to implement the UseStrictFP mode. 1850 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1851 1852 // Are floats converted to double when stored to stack during deoptimization? 1853 // Sparc does not handle callee-save floats. 1854 bool Matcher::float_in_double() { return false; } 1855 1856 // Do ints take an entire long register or just half? 1857 // Note that we if-def off of _LP64. 1858 // The relevant question is how the int is callee-saved. In _LP64 1859 // the whole long is written but de-opt'ing will have to extract 1860 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1861 const bool Matcher::int_in_long = true; 1862 1863 // Return whether or not this register is ever used as an argument. This 1864 // function is used on startup to build the trampoline stubs in generateOptoStub. 1865 // Registers not mentioned will be killed by the VM call in the trampoline, and 1866 // arguments in those registers not be available to the callee. 1867 bool Matcher::can_be_java_arg( int reg ) { 1868 // Standard sparc 6 args in registers 1869 if( reg == R_I0_num || 1870 reg == R_I1_num || 1871 reg == R_I2_num || 1872 reg == R_I3_num || 1873 reg == R_I4_num || 1874 reg == R_I5_num ) return true; 1875 // 64-bit builds can pass 64-bit pointers and longs in 1876 // the high I registers 1877 if( reg == R_I0H_num || 1878 reg == R_I1H_num || 1879 reg == R_I2H_num || 1880 reg == R_I3H_num || 1881 reg == R_I4H_num || 1882 reg == R_I5H_num ) return true; 1883 1884 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1885 return true; 1886 } 1887 1888 // A few float args in registers 1889 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1890 1891 return false; 1892 } 1893 1894 bool Matcher::is_spillable_arg( int reg ) { 1895 return can_be_java_arg(reg); 1896 } 1897 1898 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1899 // Use hardware SDIVX instruction when it is 1900 // faster than a code which use multiply. 1901 return VM_Version::has_fast_idiv(); 1902 } 1903 1904 // Register for DIVI projection of divmodI 1905 RegMask Matcher::divI_proj_mask() { 1906 ShouldNotReachHere(); 1907 return RegMask(); 1908 } 1909 1910 // Register for MODI projection of divmodI 1911 RegMask Matcher::modI_proj_mask() { 1912 ShouldNotReachHere(); 1913 return RegMask(); 1914 } 1915 1916 // Register for DIVL projection of divmodL 1917 RegMask Matcher::divL_proj_mask() { 1918 ShouldNotReachHere(); 1919 return RegMask(); 1920 } 1921 1922 // Register for MODL projection of divmodL 1923 RegMask Matcher::modL_proj_mask() { 1924 ShouldNotReachHere(); 1925 return RegMask(); 1926 } 1927 1928 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1929 return L7_REGP_mask(); 1930 } 1931 1932 1933 const bool Matcher::convi2l_type_required = true; 1934 1935 // Should the Matcher clone shifts on addressing modes, expecting them 1936 // to be subsumed into complex addressing expressions or compute them 1937 // into registers? 1938 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 1939 return clone_base_plus_offset_address(m, mstack, address_visited); 1940 } 1941 1942 void Compile::reshape_address(AddPNode* addp) { 1943 } 1944 1945 %} 1946 1947 1948 // The intptr_t operand types, defined by textual substitution. 1949 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1950 #define immX immL 1951 #define immX13 immL13 1952 #define immX13m7 immL13m7 1953 #define iRegX iRegL 1954 #define g1RegX g1RegL 1955 1956 //----------ENCODING BLOCK----------------------------------------------------- 1957 // This block specifies the encoding classes used by the compiler to output 1958 // byte streams. Encoding classes are parameterized macros used by 1959 // Machine Instruction Nodes in order to generate the bit encoding of the 1960 // instruction. Operands specify their base encoding interface with the 1961 // interface keyword. There are currently supported four interfaces, 1962 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1963 // operand to generate a function which returns its register number when 1964 // queried. CONST_INTER causes an operand to generate a function which 1965 // returns the value of the constant when queried. MEMORY_INTER causes an 1966 // operand to generate four functions which return the Base Register, the 1967 // Index Register, the Scale Value, and the Offset Value of the operand when 1968 // queried. COND_INTER causes an operand to generate six functions which 1969 // return the encoding code (ie - encoding bits for the instruction) 1970 // associated with each basic boolean condition for a conditional instruction. 1971 // 1972 // Instructions specify two basic values for encoding. Again, a function 1973 // is available to check if the constant displacement is an oop. They use the 1974 // ins_encode keyword to specify their encoding classes (which must be 1975 // a sequence of enc_class names, and their parameters, specified in 1976 // the encoding block), and they use the 1977 // opcode keyword to specify, in order, their primary, secondary, and 1978 // tertiary opcode. Only the opcode sections which a particular instruction 1979 // needs for encoding need to be specified. 1980 encode %{ 1981 enc_class enc_untested %{ 1982 #ifdef ASSERT 1983 MacroAssembler _masm(&cbuf); 1984 __ untested("encoding"); 1985 #endif 1986 %} 1987 1988 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1989 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, 1990 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1991 %} 1992 1993 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 1994 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 1995 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1996 %} 1997 1998 enc_class form3_mem_prefetch_read( memory mem ) %{ 1999 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2000 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2001 %} 2002 2003 enc_class form3_mem_prefetch_write( memory mem ) %{ 2004 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2005 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2006 %} 2007 2008 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2009 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2010 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2011 guarantee($mem$$index == R_G0_enc, "double index?"); 2012 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2013 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2014 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2015 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2016 %} 2017 2018 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2019 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2020 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2021 guarantee($mem$$index == R_G0_enc, "double index?"); 2022 // Load long with 2 instructions 2023 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2024 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2025 %} 2026 2027 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2028 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2029 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2030 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2031 %} 2032 2033 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2034 // Encode a reg-reg copy. If it is useless, then empty encoding. 2035 if( $rs2$$reg != $rd$$reg ) 2036 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2037 %} 2038 2039 // Target lo half of long 2040 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2041 // Encode a reg-reg copy. If it is useless, then empty encoding. 2042 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2043 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2044 %} 2045 2046 // Source lo half of long 2047 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2048 // Encode a reg-reg copy. If it is useless, then empty encoding. 2049 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2050 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2051 %} 2052 2053 // Target hi half of long 2054 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2055 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2056 %} 2057 2058 // Source lo half of long, and leave it sign extended. 2059 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2060 // Sign extend low half 2061 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2062 %} 2063 2064 // Source hi half of long, and leave it sign extended. 2065 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2066 // Shift high half to low half 2067 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2068 %} 2069 2070 // Source hi half of long 2071 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2072 // Encode a reg-reg copy. If it is useless, then empty encoding. 2073 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2074 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2075 %} 2076 2077 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2078 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2079 %} 2080 2081 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2082 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2083 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2084 %} 2085 2086 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2087 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2088 // clear if nothing else is happening 2089 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2090 // blt,a,pn done 2091 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2092 // mov dst,-1 in delay slot 2093 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2094 %} 2095 2096 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2097 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2098 %} 2099 2100 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2101 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2102 %} 2103 2104 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2105 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2106 %} 2107 2108 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2109 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2110 %} 2111 2112 enc_class move_return_pc_to_o1() %{ 2113 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2114 %} 2115 2116 /* %%% merge with enc_to_bool */ 2117 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2118 MacroAssembler _masm(&cbuf); 2119 2120 Register src_reg = reg_to_register_object($src$$reg); 2121 Register dst_reg = reg_to_register_object($dst$$reg); 2122 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2123 %} 2124 2125 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2126 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2127 MacroAssembler _masm(&cbuf); 2128 2129 Register p_reg = reg_to_register_object($p$$reg); 2130 Register q_reg = reg_to_register_object($q$$reg); 2131 Register y_reg = reg_to_register_object($y$$reg); 2132 Register tmp_reg = reg_to_register_object($tmp$$reg); 2133 2134 __ subcc( p_reg, q_reg, p_reg ); 2135 __ add ( p_reg, y_reg, tmp_reg ); 2136 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2137 %} 2138 2139 enc_class form_d2i_helper(regD src, regF dst) %{ 2140 // fcmp %fcc0,$src,$src 2141 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2142 // branch %fcc0 not-nan, predict taken 2143 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2144 // fdtoi $src,$dst 2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2146 // fitos $dst,$dst (if nan) 2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2148 // clear $dst (if nan) 2149 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2150 // carry on here... 2151 %} 2152 2153 enc_class form_d2l_helper(regD src, regD dst) %{ 2154 // fcmp %fcc0,$src,$src check for NAN 2155 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2156 // branch %fcc0 not-nan, predict taken 2157 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2158 // fdtox $src,$dst convert in delay slot 2159 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2160 // fxtod $dst,$dst (if nan) 2161 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2162 // clear $dst (if nan) 2163 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2164 // carry on here... 2165 %} 2166 2167 enc_class form_f2i_helper(regF src, regF dst) %{ 2168 // fcmps %fcc0,$src,$src 2169 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2170 // branch %fcc0 not-nan, predict taken 2171 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2172 // fstoi $src,$dst 2173 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2174 // fitos $dst,$dst (if nan) 2175 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2176 // clear $dst (if nan) 2177 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2178 // carry on here... 2179 %} 2180 2181 enc_class form_f2l_helper(regF src, regD dst) %{ 2182 // fcmps %fcc0,$src,$src 2183 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2184 // branch %fcc0 not-nan, predict taken 2185 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2186 // fstox $src,$dst 2187 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2188 // fxtod $dst,$dst (if nan) 2189 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2190 // clear $dst (if nan) 2191 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2192 // carry on here... 2193 %} 2194 2195 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2196 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2197 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2198 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2199 2200 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2201 2202 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2203 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2204 2205 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2206 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2207 %} 2208 2209 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2210 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2211 %} 2212 2213 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2214 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2215 %} 2216 2217 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2218 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2219 %} 2220 2221 enc_class form3_convI2F(regF rs2, regF rd) %{ 2222 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2223 %} 2224 2225 // Encloding class for traceable jumps 2226 enc_class form_jmpl(g3RegP dest) %{ 2227 emit_jmpl(cbuf, $dest$$reg); 2228 %} 2229 2230 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2231 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2232 %} 2233 2234 enc_class form2_nop() %{ 2235 emit_nop(cbuf); 2236 %} 2237 2238 enc_class form2_illtrap() %{ 2239 emit_illtrap(cbuf); 2240 %} 2241 2242 2243 // Compare longs and convert into -1, 0, 1. 2244 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2245 // CMP $src1,$src2 2246 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2247 // blt,a,pn done 2248 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2249 // mov dst,-1 in delay slot 2250 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2251 // bgt,a,pn done 2252 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2253 // mov dst,1 in delay slot 2254 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2255 // CLR $dst 2256 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2257 %} 2258 2259 enc_class enc_PartialSubtypeCheck() %{ 2260 MacroAssembler _masm(&cbuf); 2261 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2262 __ delayed()->nop(); 2263 %} 2264 2265 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2266 MacroAssembler _masm(&cbuf); 2267 Label* L = $labl$$label; 2268 Assembler::Predict predict_taken = 2269 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2270 2271 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2272 __ delayed()->nop(); 2273 %} 2274 2275 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2276 MacroAssembler _masm(&cbuf); 2277 Label* L = $labl$$label; 2278 Assembler::Predict predict_taken = 2279 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2280 2281 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2282 __ delayed()->nop(); 2283 %} 2284 2285 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2286 int op = (Assembler::arith_op << 30) | 2287 ($dst$$reg << 25) | 2288 (Assembler::movcc_op3 << 19) | 2289 (1 << 18) | // cc2 bit for 'icc' 2290 ($cmp$$cmpcode << 14) | 2291 (0 << 13) | // select register move 2292 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2293 ($src$$reg << 0); 2294 cbuf.insts()->emit_int32(op); 2295 %} 2296 2297 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2298 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2299 int op = (Assembler::arith_op << 30) | 2300 ($dst$$reg << 25) | 2301 (Assembler::movcc_op3 << 19) | 2302 (1 << 18) | // cc2 bit for 'icc' 2303 ($cmp$$cmpcode << 14) | 2304 (1 << 13) | // select immediate move 2305 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2306 (simm11 << 0); 2307 cbuf.insts()->emit_int32(op); 2308 %} 2309 2310 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2311 int op = (Assembler::arith_op << 30) | 2312 ($dst$$reg << 25) | 2313 (Assembler::movcc_op3 << 19) | 2314 (0 << 18) | // cc2 bit for 'fccX' 2315 ($cmp$$cmpcode << 14) | 2316 (0 << 13) | // select register move 2317 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2318 ($src$$reg << 0); 2319 cbuf.insts()->emit_int32(op); 2320 %} 2321 2322 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2323 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2324 int op = (Assembler::arith_op << 30) | 2325 ($dst$$reg << 25) | 2326 (Assembler::movcc_op3 << 19) | 2327 (0 << 18) | // cc2 bit for 'fccX' 2328 ($cmp$$cmpcode << 14) | 2329 (1 << 13) | // select immediate move 2330 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2331 (simm11 << 0); 2332 cbuf.insts()->emit_int32(op); 2333 %} 2334 2335 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2336 int op = (Assembler::arith_op << 30) | 2337 ($dst$$reg << 25) | 2338 (Assembler::fpop2_op3 << 19) | 2339 (0 << 18) | 2340 ($cmp$$cmpcode << 14) | 2341 (1 << 13) | // select register move 2342 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2343 ($primary << 5) | // select single, double or quad 2344 ($src$$reg << 0); 2345 cbuf.insts()->emit_int32(op); 2346 %} 2347 2348 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2349 int op = (Assembler::arith_op << 30) | 2350 ($dst$$reg << 25) | 2351 (Assembler::fpop2_op3 << 19) | 2352 (0 << 18) | 2353 ($cmp$$cmpcode << 14) | 2354 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2355 ($primary << 5) | // select single, double or quad 2356 ($src$$reg << 0); 2357 cbuf.insts()->emit_int32(op); 2358 %} 2359 2360 // Used by the MIN/MAX encodings. Same as a CMOV, but 2361 // the condition comes from opcode-field instead of an argument. 2362 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2363 int op = (Assembler::arith_op << 30) | 2364 ($dst$$reg << 25) | 2365 (Assembler::movcc_op3 << 19) | 2366 (1 << 18) | // cc2 bit for 'icc' 2367 ($primary << 14) | 2368 (0 << 13) | // select register move 2369 (0 << 11) | // cc1, cc0 bits for 'icc' 2370 ($src$$reg << 0); 2371 cbuf.insts()->emit_int32(op); 2372 %} 2373 2374 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2375 int op = (Assembler::arith_op << 30) | 2376 ($dst$$reg << 25) | 2377 (Assembler::movcc_op3 << 19) | 2378 (6 << 16) | // cc2 bit for 'xcc' 2379 ($primary << 14) | 2380 (0 << 13) | // select register move 2381 (0 << 11) | // cc1, cc0 bits for 'icc' 2382 ($src$$reg << 0); 2383 cbuf.insts()->emit_int32(op); 2384 %} 2385 2386 enc_class Set13( immI13 src, iRegI rd ) %{ 2387 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2388 %} 2389 2390 enc_class SetHi22( immI src, iRegI rd ) %{ 2391 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2392 %} 2393 2394 enc_class Set32( immI src, iRegI rd ) %{ 2395 MacroAssembler _masm(&cbuf); 2396 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2397 %} 2398 2399 enc_class call_epilog %{ 2400 if( VerifyStackAtCalls ) { 2401 MacroAssembler _masm(&cbuf); 2402 int framesize = ra_->C->frame_size_in_bytes(); 2403 Register temp_reg = G3; 2404 __ add(SP, framesize, temp_reg); 2405 __ cmp(temp_reg, FP); 2406 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2407 } 2408 %} 2409 2410 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2411 // to G1 so the register allocator will not have to deal with the misaligned register 2412 // pair. 2413 enc_class adjust_long_from_native_call %{ 2414 %} 2415 2416 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2417 // CALL directly to the runtime 2418 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2419 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true); 2420 %} 2421 2422 enc_class preserve_SP %{ 2423 MacroAssembler _masm(&cbuf); 2424 __ mov(SP, L7_mh_SP_save); 2425 %} 2426 2427 enc_class restore_SP %{ 2428 MacroAssembler _masm(&cbuf); 2429 __ mov(L7_mh_SP_save, SP); 2430 %} 2431 2432 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2433 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2434 // who we intended to call. 2435 if (!_method) { 2436 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec()); 2437 } else { 2438 int method_index = resolved_method_index(cbuf); 2439 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 2440 : static_call_Relocation::spec(method_index); 2441 emit_call_reloc(cbuf, $meth$$method, rspec); 2442 2443 // Emit stub for static call. 2444 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2445 if (stub == NULL) { 2446 ciEnv::current()->record_failure("CodeCache is full"); 2447 return; 2448 } 2449 } 2450 %} 2451 2452 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2453 MacroAssembler _masm(&cbuf); 2454 __ set_inst_mark(); 2455 int vtable_index = this->_vtable_index; 2456 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2457 if (vtable_index < 0) { 2458 // must be invalid_vtable_index, not nonvirtual_vtable_index 2459 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 2460 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2461 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2462 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2463 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf)); 2464 } else { 2465 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2466 // Just go thru the vtable 2467 // get receiver klass (receiver already checked for non-null) 2468 // If we end up going thru a c2i adapter interpreter expects method in G5 2469 int off = __ offset(); 2470 __ load_klass(O0, G3_scratch); 2471 int klass_load_size; 2472 if (UseCompressedClassPointers) { 2473 assert(Universe::heap() != NULL, "java heap should be initialized"); 2474 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 2475 } else { 2476 klass_load_size = 1*BytesPerInstWord; 2477 } 2478 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 2479 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2480 if (Assembler::is_simm13(v_off)) { 2481 __ ld_ptr(G3, v_off, G5_method); 2482 } else { 2483 // Generate 2 instructions 2484 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2485 __ or3(G5_method, v_off & 0x3ff, G5_method); 2486 // ld_ptr, set_hi, set 2487 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2488 "Unexpected instruction size(s)"); 2489 __ ld_ptr(G3, G5_method, G5_method); 2490 } 2491 // NOTE: for vtable dispatches, the vtable entry will never be null. 2492 // However it may very well end up in handle_wrong_method if the 2493 // method is abstract for the particular class. 2494 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); 2495 // jump to target (either compiled code or c2iadapter) 2496 __ jmpl(G3_scratch, G0, O7); 2497 __ delayed()->nop(); 2498 } 2499 %} 2500 2501 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2502 MacroAssembler _masm(&cbuf); 2503 2504 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2505 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2506 // we might be calling a C2I adapter which needs it. 2507 2508 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2509 // Load nmethod 2510 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); 2511 2512 // CALL to compiled java, indirect the contents of G3 2513 __ set_inst_mark(); 2514 __ callr(temp_reg, G0); 2515 __ delayed()->nop(); 2516 %} 2517 2518 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2519 MacroAssembler _masm(&cbuf); 2520 Register Rdividend = reg_to_register_object($src1$$reg); 2521 Register Rdivisor = reg_to_register_object($src2$$reg); 2522 Register Rresult = reg_to_register_object($dst$$reg); 2523 2524 __ sra(Rdivisor, 0, Rdivisor); 2525 __ sra(Rdividend, 0, Rdividend); 2526 __ sdivx(Rdividend, Rdivisor, Rresult); 2527 %} 2528 2529 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2530 MacroAssembler _masm(&cbuf); 2531 2532 Register Rdividend = reg_to_register_object($src1$$reg); 2533 int divisor = $imm$$constant; 2534 Register Rresult = reg_to_register_object($dst$$reg); 2535 2536 __ sra(Rdividend, 0, Rdividend); 2537 __ sdivx(Rdividend, divisor, Rresult); 2538 %} 2539 2540 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2541 MacroAssembler _masm(&cbuf); 2542 Register Rsrc1 = reg_to_register_object($src1$$reg); 2543 Register Rsrc2 = reg_to_register_object($src2$$reg); 2544 Register Rdst = reg_to_register_object($dst$$reg); 2545 2546 __ sra( Rsrc1, 0, Rsrc1 ); 2547 __ sra( Rsrc2, 0, Rsrc2 ); 2548 __ mulx( Rsrc1, Rsrc2, Rdst ); 2549 __ srlx( Rdst, 32, Rdst ); 2550 %} 2551 2552 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2553 MacroAssembler _masm(&cbuf); 2554 Register Rdividend = reg_to_register_object($src1$$reg); 2555 Register Rdivisor = reg_to_register_object($src2$$reg); 2556 Register Rresult = reg_to_register_object($dst$$reg); 2557 Register Rscratch = reg_to_register_object($scratch$$reg); 2558 2559 assert(Rdividend != Rscratch, ""); 2560 assert(Rdivisor != Rscratch, ""); 2561 2562 __ sra(Rdividend, 0, Rdividend); 2563 __ sra(Rdivisor, 0, Rdivisor); 2564 __ sdivx(Rdividend, Rdivisor, Rscratch); 2565 __ mulx(Rscratch, Rdivisor, Rscratch); 2566 __ sub(Rdividend, Rscratch, Rresult); 2567 %} 2568 2569 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2570 MacroAssembler _masm(&cbuf); 2571 2572 Register Rdividend = reg_to_register_object($src1$$reg); 2573 int divisor = $imm$$constant; 2574 Register Rresult = reg_to_register_object($dst$$reg); 2575 Register Rscratch = reg_to_register_object($scratch$$reg); 2576 2577 assert(Rdividend != Rscratch, ""); 2578 2579 __ sra(Rdividend, 0, Rdividend); 2580 __ sdivx(Rdividend, divisor, Rscratch); 2581 __ mulx(Rscratch, divisor, Rscratch); 2582 __ sub(Rdividend, Rscratch, Rresult); 2583 %} 2584 2585 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2586 MacroAssembler _masm(&cbuf); 2587 2588 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2589 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2590 2591 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2592 %} 2593 2594 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2595 MacroAssembler _masm(&cbuf); 2596 2597 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2598 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2599 2600 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2601 %} 2602 2603 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2604 MacroAssembler _masm(&cbuf); 2605 2606 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2607 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2608 2609 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2610 %} 2611 2612 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2613 MacroAssembler _masm(&cbuf); 2614 2615 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2616 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2617 2618 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2619 %} 2620 2621 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2622 MacroAssembler _masm(&cbuf); 2623 2624 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2625 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2626 2627 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2628 %} 2629 2630 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2631 MacroAssembler _masm(&cbuf); 2632 2633 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2634 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2635 2636 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2637 %} 2638 2639 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2640 MacroAssembler _masm(&cbuf); 2641 2642 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2643 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2644 2645 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2646 %} 2647 2648 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2649 MacroAssembler _masm(&cbuf); 2650 2651 Register Roop = reg_to_register_object($oop$$reg); 2652 Register Rbox = reg_to_register_object($box$$reg); 2653 Register Rscratch = reg_to_register_object($scratch$$reg); 2654 Register Rmark = reg_to_register_object($scratch2$$reg); 2655 2656 assert(Roop != Rscratch, ""); 2657 assert(Roop != Rmark, ""); 2658 assert(Rbox != Rscratch, ""); 2659 assert(Rbox != Rmark, ""); 2660 2661 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2662 %} 2663 2664 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2665 MacroAssembler _masm(&cbuf); 2666 2667 Register Roop = reg_to_register_object($oop$$reg); 2668 Register Rbox = reg_to_register_object($box$$reg); 2669 Register Rscratch = reg_to_register_object($scratch$$reg); 2670 Register Rmark = reg_to_register_object($scratch2$$reg); 2671 2672 assert(Roop != Rscratch, ""); 2673 assert(Roop != Rmark, ""); 2674 assert(Rbox != Rscratch, ""); 2675 assert(Rbox != Rmark, ""); 2676 2677 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2678 %} 2679 2680 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2681 MacroAssembler _masm(&cbuf); 2682 Register Rmem = reg_to_register_object($mem$$reg); 2683 Register Rold = reg_to_register_object($old$$reg); 2684 Register Rnew = reg_to_register_object($new$$reg); 2685 2686 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2687 __ cmp( Rold, Rnew ); 2688 %} 2689 2690 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2691 Register Rmem = reg_to_register_object($mem$$reg); 2692 Register Rold = reg_to_register_object($old$$reg); 2693 Register Rnew = reg_to_register_object($new$$reg); 2694 2695 MacroAssembler _masm(&cbuf); 2696 __ mov(Rnew, O7); 2697 __ casx(Rmem, Rold, O7); 2698 __ cmp( Rold, O7 ); 2699 %} 2700 2701 // raw int cas, used for compareAndSwap 2702 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2703 Register Rmem = reg_to_register_object($mem$$reg); 2704 Register Rold = reg_to_register_object($old$$reg); 2705 Register Rnew = reg_to_register_object($new$$reg); 2706 2707 MacroAssembler _masm(&cbuf); 2708 __ mov(Rnew, O7); 2709 __ cas(Rmem, Rold, O7); 2710 __ cmp( Rold, O7 ); 2711 %} 2712 2713 // raw int cas without using tmp register for compareAndExchange 2714 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{ 2715 Register Rmem = reg_to_register_object($mem$$reg); 2716 Register Rold = reg_to_register_object($old$$reg); 2717 Register Rnew = reg_to_register_object($new$$reg); 2718 2719 MacroAssembler _masm(&cbuf); 2720 __ cas(Rmem, Rold, Rnew); 2721 %} 2722 2723 // 64-bit cas without using tmp register for compareAndExchange 2724 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{ 2725 Register Rmem = reg_to_register_object($mem$$reg); 2726 Register Rold = reg_to_register_object($old$$reg); 2727 Register Rnew = reg_to_register_object($new$$reg); 2728 2729 MacroAssembler _masm(&cbuf); 2730 __ casx(Rmem, Rold, Rnew); 2731 %} 2732 2733 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2734 Register Rres = reg_to_register_object($res$$reg); 2735 2736 MacroAssembler _masm(&cbuf); 2737 __ mov(1, Rres); 2738 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2739 %} 2740 2741 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2742 Register Rres = reg_to_register_object($res$$reg); 2743 2744 MacroAssembler _masm(&cbuf); 2745 __ mov(1, Rres); 2746 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2747 %} 2748 2749 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2750 MacroAssembler _masm(&cbuf); 2751 Register Rdst = reg_to_register_object($dst$$reg); 2752 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2753 : reg_to_DoubleFloatRegister_object($src1$$reg); 2754 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2755 : reg_to_DoubleFloatRegister_object($src2$$reg); 2756 2757 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2758 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2759 %} 2760 2761 enc_class enc_rethrow() %{ 2762 cbuf.set_insts_mark(); 2763 Register temp_reg = G3; 2764 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 2765 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 2766 MacroAssembler _masm(&cbuf); 2767 #ifdef ASSERT 2768 __ save_frame(0); 2769 AddressLiteral last_rethrow_addrlit(&last_rethrow); 2770 __ sethi(last_rethrow_addrlit, L1); 2771 Address addr(L1, last_rethrow_addrlit.low10()); 2772 __ rdpc(L2); 2773 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 2774 __ st_ptr(L2, addr); 2775 __ restore(); 2776 #endif 2777 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 2778 __ delayed()->nop(); 2779 %} 2780 2781 enc_class emit_mem_nop() %{ 2782 // Generates the instruction LDUXA [o6,g0],#0x82,g0 2783 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 2784 %} 2785 2786 enc_class emit_fadd_nop() %{ 2787 // Generates the instruction FMOVS f31,f31 2788 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 2789 %} 2790 2791 enc_class emit_br_nop() %{ 2792 // Generates the instruction BPN,PN . 2793 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 2794 %} 2795 2796 enc_class enc_membar_acquire %{ 2797 MacroAssembler _masm(&cbuf); 2798 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 2799 %} 2800 2801 enc_class enc_membar_release %{ 2802 MacroAssembler _masm(&cbuf); 2803 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 2804 %} 2805 2806 enc_class enc_membar_volatile %{ 2807 MacroAssembler _masm(&cbuf); 2808 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 2809 %} 2810 2811 %} 2812 2813 //----------FRAME-------------------------------------------------------------- 2814 // Definition of frame structure and management information. 2815 // 2816 // S T A C K L A Y O U T Allocators stack-slot number 2817 // | (to get allocators register number 2818 // G Owned by | | v add VMRegImpl::stack0) 2819 // r CALLER | | 2820 // o | +--------+ pad to even-align allocators stack-slot 2821 // w V | pad0 | numbers; owned by CALLER 2822 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 2823 // h ^ | in | 5 2824 // | | args | 4 Holes in incoming args owned by SELF 2825 // | | | | 3 2826 // | | +--------+ 2827 // V | | old out| Empty on Intel, window on Sparc 2828 // | old |preserve| Must be even aligned. 2829 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 2830 // | | in | 3 area for Intel ret address 2831 // Owned by |preserve| Empty on Sparc. 2832 // SELF +--------+ 2833 // | | pad2 | 2 pad to align old SP 2834 // | +--------+ 1 2835 // | | locks | 0 2836 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 2837 // | | pad1 | 11 pad to align new SP 2838 // | +--------+ 2839 // | | | 10 2840 // | | spills | 9 spills 2841 // V | | 8 (pad0 slot for callee) 2842 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 2843 // ^ | out | 7 2844 // | | args | 6 Holes in outgoing args owned by CALLEE 2845 // Owned by +--------+ 2846 // CALLEE | new out| 6 Empty on Intel, window on Sparc 2847 // | new |preserve| Must be even-aligned. 2848 // | SP-+--------+----> Matcher::_new_SP, even aligned 2849 // | | | 2850 // 2851 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 2852 // known from SELF's arguments and the Java calling convention. 2853 // Region 6-7 is determined per call site. 2854 // Note 2: If the calling convention leaves holes in the incoming argument 2855 // area, those holes are owned by SELF. Holes in the outgoing area 2856 // are owned by the CALLEE. Holes should not be nessecary in the 2857 // incoming area, as the Java calling convention is completely under 2858 // the control of the AD file. Doubles can be sorted and packed to 2859 // avoid holes. Holes in the outgoing arguments may be necessary for 2860 // varargs C calling conventions. 2861 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 2862 // even aligned with pad0 as needed. 2863 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 2864 // region 6-11 is even aligned; it may be padded out more so that 2865 // the region from SP to FP meets the minimum stack alignment. 2866 2867 frame %{ 2868 // What direction does stack grow in (assumed to be same for native & Java) 2869 stack_direction(TOWARDS_LOW); 2870 2871 // These two registers define part of the calling convention 2872 // between compiled code and the interpreter. 2873 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C 2874 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 2875 2876 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 2877 cisc_spilling_operand_name(indOffset); 2878 2879 // Number of stack slots consumed by a Monitor enter 2880 sync_stack_slots(2); 2881 2882 // Compiled code's Frame Pointer 2883 frame_pointer(R_SP); 2884 2885 // Stack alignment requirement 2886 stack_alignment(StackAlignmentInBytes); 2887 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 2888 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 2889 2890 // Number of stack slots between incoming argument block and the start of 2891 // a new frame. The PROLOG must add this many slots to the stack. The 2892 // EPILOG must remove this many slots. 2893 in_preserve_stack_slots(0); 2894 2895 // Number of outgoing stack slots killed above the out_preserve_stack_slots 2896 // for calls to C. Supports the var-args backing area for register parms. 2897 // ADLC doesn't support parsing expressions, so I folded the math by hand. 2898 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 2899 varargs_C_out_slots_killed(12); 2900 2901 // The after-PROLOG location of the return address. Location of 2902 // return address specifies a type (REG or STACK) and a number 2903 // representing the register number (i.e. - use a register name) or 2904 // stack slot. 2905 return_addr(REG R_I7); // Ret Addr is in register I7 2906 2907 // Body of function which returns an OptoRegs array locating 2908 // arguments either in registers or in stack slots for calling 2909 // java 2910 calling_convention %{ 2911 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 2912 2913 %} 2914 2915 // Body of function which returns an OptoRegs array locating 2916 // arguments either in registers or in stack slots for calling 2917 // C. 2918 c_calling_convention %{ 2919 // This is obviously always outgoing 2920 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 2921 %} 2922 2923 // Location of native (C/C++) and interpreter return values. This is specified to 2924 // be the same as Java. In the 32-bit VM, long values are actually returned from 2925 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 2926 // to and from the register pairs is done by the appropriate call and epilog 2927 // opcodes. This simplifies the register allocator. 2928 c_return_value %{ 2929 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 2930 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 2931 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 2932 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 2933 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 2934 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 2935 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 2936 %} 2937 2938 // Location of compiled Java return values. Same as C 2939 return_value %{ 2940 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 2941 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 2942 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 2943 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 2944 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 2945 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 2946 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 2947 %} 2948 2949 %} 2950 2951 2952 //----------ATTRIBUTES--------------------------------------------------------- 2953 //----------Operand Attributes------------------------------------------------- 2954 op_attrib op_cost(1); // Required cost attribute 2955 2956 //----------Instruction Attributes--------------------------------------------- 2957 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 2958 ins_attrib ins_size(32); // Required size attribute (in bits) 2959 2960 // avoid_back_to_back attribute is an expression that must return 2961 // one of the following values defined in MachNode: 2962 // AVOID_NONE - instruction can be placed anywhere 2963 // AVOID_BEFORE - instruction cannot be placed after an 2964 // instruction with MachNode::AVOID_AFTER 2965 // AVOID_AFTER - the next instruction cannot be the one 2966 // with MachNode::AVOID_BEFORE 2967 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 2968 // the same time 2969 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); 2970 2971 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 2972 // non-matching short branch variant of some 2973 // long branch? 2974 2975 //----------OPERANDS----------------------------------------------------------- 2976 // Operand definitions must precede instruction definitions for correct parsing 2977 // in the ADLC because operands constitute user defined types which are used in 2978 // instruction definitions. 2979 2980 //----------Simple Operands---------------------------------------------------- 2981 // Immediate Operands 2982 // Integer Immediate: 32-bit 2983 operand immI() %{ 2984 match(ConI); 2985 2986 op_cost(0); 2987 // formats are generated automatically for constants and base registers 2988 format %{ %} 2989 interface(CONST_INTER); 2990 %} 2991 2992 // Integer Immediate: 0-bit 2993 operand immI0() %{ 2994 predicate(n->get_int() == 0); 2995 match(ConI); 2996 op_cost(0); 2997 2998 format %{ %} 2999 interface(CONST_INTER); 3000 %} 3001 3002 // Integer Immediate: 5-bit 3003 operand immI5() %{ 3004 predicate(Assembler::is_simm5(n->get_int())); 3005 match(ConI); 3006 op_cost(0); 3007 format %{ %} 3008 interface(CONST_INTER); 3009 %} 3010 3011 // Integer Immediate: 8-bit 3012 operand immI8() %{ 3013 predicate(Assembler::is_simm8(n->get_int())); 3014 match(ConI); 3015 op_cost(0); 3016 format %{ %} 3017 interface(CONST_INTER); 3018 %} 3019 3020 // Integer Immediate: the value 10 3021 operand immI10() %{ 3022 predicate(n->get_int() == 10); 3023 match(ConI); 3024 op_cost(0); 3025 3026 format %{ %} 3027 interface(CONST_INTER); 3028 %} 3029 3030 // Integer Immediate: 11-bit 3031 operand immI11() %{ 3032 predicate(Assembler::is_simm11(n->get_int())); 3033 match(ConI); 3034 op_cost(0); 3035 format %{ %} 3036 interface(CONST_INTER); 3037 %} 3038 3039 // Integer Immediate: 13-bit 3040 operand immI13() %{ 3041 predicate(Assembler::is_simm13(n->get_int())); 3042 match(ConI); 3043 op_cost(0); 3044 3045 format %{ %} 3046 interface(CONST_INTER); 3047 %} 3048 3049 // Integer Immediate: 13-bit minus 7 3050 operand immI13m7() %{ 3051 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3052 match(ConI); 3053 op_cost(0); 3054 3055 format %{ %} 3056 interface(CONST_INTER); 3057 %} 3058 3059 // Integer Immediate: 16-bit 3060 operand immI16() %{ 3061 predicate(Assembler::is_simm16(n->get_int())); 3062 match(ConI); 3063 op_cost(0); 3064 format %{ %} 3065 interface(CONST_INTER); 3066 %} 3067 3068 // Integer Immediate: the values 1-31 3069 operand immI_1_31() %{ 3070 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3071 match(ConI); 3072 op_cost(0); 3073 3074 format %{ %} 3075 interface(CONST_INTER); 3076 %} 3077 3078 // Integer Immediate: the values 32-63 3079 operand immI_32_63() %{ 3080 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3081 match(ConI); 3082 op_cost(0); 3083 3084 format %{ %} 3085 interface(CONST_INTER); 3086 %} 3087 3088 // Immediates for special shifts (sign extend) 3089 3090 // Integer Immediate: the value 16 3091 operand immI_16() %{ 3092 predicate(n->get_int() == 16); 3093 match(ConI); 3094 op_cost(0); 3095 3096 format %{ %} 3097 interface(CONST_INTER); 3098 %} 3099 3100 // Integer Immediate: the value 24 3101 operand immI_24() %{ 3102 predicate(n->get_int() == 24); 3103 match(ConI); 3104 op_cost(0); 3105 3106 format %{ %} 3107 interface(CONST_INTER); 3108 %} 3109 // Integer Immediate: the value 255 3110 operand immI_255() %{ 3111 predicate( n->get_int() == 255 ); 3112 match(ConI); 3113 op_cost(0); 3114 3115 format %{ %} 3116 interface(CONST_INTER); 3117 %} 3118 3119 // Integer Immediate: the value 65535 3120 operand immI_65535() %{ 3121 predicate(n->get_int() == 65535); 3122 match(ConI); 3123 op_cost(0); 3124 3125 format %{ %} 3126 interface(CONST_INTER); 3127 %} 3128 3129 // Integer Immediate: the values 0-31 3130 operand immU5() %{ 3131 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3132 match(ConI); 3133 op_cost(0); 3134 3135 format %{ %} 3136 interface(CONST_INTER); 3137 %} 3138 3139 // Integer Immediate: 6-bit 3140 operand immU6() %{ 3141 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3142 match(ConI); 3143 op_cost(0); 3144 format %{ %} 3145 interface(CONST_INTER); 3146 %} 3147 3148 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) 3149 operand immU12() %{ 3150 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3151 match(ConI); 3152 op_cost(0); 3153 3154 format %{ %} 3155 interface(CONST_INTER); 3156 %} 3157 3158 // Integer Immediate non-negative 3159 operand immU31() 3160 %{ 3161 predicate(n->get_int() >= 0); 3162 match(ConI); 3163 3164 op_cost(0); 3165 format %{ %} 3166 interface(CONST_INTER); 3167 %} 3168 3169 // Long Immediate: the value FF 3170 operand immL_FF() %{ 3171 predicate( n->get_long() == 0xFFL ); 3172 match(ConL); 3173 op_cost(0); 3174 3175 format %{ %} 3176 interface(CONST_INTER); 3177 %} 3178 3179 // Long Immediate: the value FFFF 3180 operand immL_FFFF() %{ 3181 predicate( n->get_long() == 0xFFFFL ); 3182 match(ConL); 3183 op_cost(0); 3184 3185 format %{ %} 3186 interface(CONST_INTER); 3187 %} 3188 3189 // Pointer Immediate: 32 or 64-bit 3190 operand immP() %{ 3191 match(ConP); 3192 3193 op_cost(5); 3194 // formats are generated automatically for constants and base registers 3195 format %{ %} 3196 interface(CONST_INTER); 3197 %} 3198 3199 // Pointer Immediate: 64-bit 3200 operand immP_set() %{ 3201 predicate(!VM_Version::has_fast_ld()); 3202 match(ConP); 3203 3204 op_cost(5); 3205 // formats are generated automatically for constants and base registers 3206 format %{ %} 3207 interface(CONST_INTER); 3208 %} 3209 3210 // Pointer Immediate: 64-bit 3211 // From Niagara2 processors on a load should be better than materializing. 3212 operand immP_load() %{ 3213 predicate(VM_Version::has_fast_ld() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3214 match(ConP); 3215 3216 op_cost(5); 3217 // formats are generated automatically for constants and base registers 3218 format %{ %} 3219 interface(CONST_INTER); 3220 %} 3221 3222 // Pointer Immediate: 64-bit 3223 operand immP_no_oop_cheap() %{ 3224 predicate(VM_Version::has_fast_ld() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3225 match(ConP); 3226 3227 op_cost(5); 3228 // formats are generated automatically for constants and base registers 3229 format %{ %} 3230 interface(CONST_INTER); 3231 %} 3232 3233 operand immP13() %{ 3234 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3235 match(ConP); 3236 op_cost(0); 3237 3238 format %{ %} 3239 interface(CONST_INTER); 3240 %} 3241 3242 operand immP0() %{ 3243 predicate(n->get_ptr() == 0); 3244 match(ConP); 3245 op_cost(0); 3246 3247 format %{ %} 3248 interface(CONST_INTER); 3249 %} 3250 3251 operand immP_poll() %{ 3252 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3253 match(ConP); 3254 3255 // formats are generated automatically for constants and base registers 3256 format %{ %} 3257 interface(CONST_INTER); 3258 %} 3259 3260 // Pointer Immediate 3261 operand immN() 3262 %{ 3263 match(ConN); 3264 3265 op_cost(10); 3266 format %{ %} 3267 interface(CONST_INTER); 3268 %} 3269 3270 operand immNKlass() 3271 %{ 3272 match(ConNKlass); 3273 3274 op_cost(10); 3275 format %{ %} 3276 interface(CONST_INTER); 3277 %} 3278 3279 // NULL Pointer Immediate 3280 operand immN0() 3281 %{ 3282 predicate(n->get_narrowcon() == 0); 3283 match(ConN); 3284 3285 op_cost(0); 3286 format %{ %} 3287 interface(CONST_INTER); 3288 %} 3289 3290 operand immL() %{ 3291 match(ConL); 3292 op_cost(40); 3293 // formats are generated automatically for constants and base registers 3294 format %{ %} 3295 interface(CONST_INTER); 3296 %} 3297 3298 operand immL0() %{ 3299 predicate(n->get_long() == 0L); 3300 match(ConL); 3301 op_cost(0); 3302 // formats are generated automatically for constants and base registers 3303 format %{ %} 3304 interface(CONST_INTER); 3305 %} 3306 3307 // Integer Immediate: 5-bit 3308 operand immL5() %{ 3309 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); 3310 match(ConL); 3311 op_cost(0); 3312 format %{ %} 3313 interface(CONST_INTER); 3314 %} 3315 3316 // Long Immediate: 13-bit 3317 operand immL13() %{ 3318 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3319 match(ConL); 3320 op_cost(0); 3321 3322 format %{ %} 3323 interface(CONST_INTER); 3324 %} 3325 3326 // Long Immediate: 13-bit minus 7 3327 operand immL13m7() %{ 3328 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3329 match(ConL); 3330 op_cost(0); 3331 3332 format %{ %} 3333 interface(CONST_INTER); 3334 %} 3335 3336 // Long Immediate: low 32-bit mask 3337 operand immL_32bits() %{ 3338 predicate(n->get_long() == 0xFFFFFFFFL); 3339 match(ConL); 3340 op_cost(0); 3341 3342 format %{ %} 3343 interface(CONST_INTER); 3344 %} 3345 3346 // Long Immediate: cheap (materialize in <= 3 instructions) 3347 operand immL_cheap() %{ 3348 predicate(!VM_Version::has_fast_ld() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3349 match(ConL); 3350 op_cost(0); 3351 3352 format %{ %} 3353 interface(CONST_INTER); 3354 %} 3355 3356 // Long Immediate: expensive (materialize in > 3 instructions) 3357 operand immL_expensive() %{ 3358 predicate(VM_Version::has_fast_ld() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3359 match(ConL); 3360 op_cost(0); 3361 3362 format %{ %} 3363 interface(CONST_INTER); 3364 %} 3365 3366 // Double Immediate 3367 operand immD() %{ 3368 match(ConD); 3369 3370 op_cost(40); 3371 format %{ %} 3372 interface(CONST_INTER); 3373 %} 3374 3375 // Double Immediate: +0.0d 3376 operand immD0() %{ 3377 predicate(jlong_cast(n->getd()) == 0); 3378 match(ConD); 3379 3380 op_cost(0); 3381 format %{ %} 3382 interface(CONST_INTER); 3383 %} 3384 3385 // Float Immediate 3386 operand immF() %{ 3387 match(ConF); 3388 3389 op_cost(20); 3390 format %{ %} 3391 interface(CONST_INTER); 3392 %} 3393 3394 // Float Immediate: +0.0f 3395 operand immF0() %{ 3396 predicate(jint_cast(n->getf()) == 0); 3397 match(ConF); 3398 3399 op_cost(0); 3400 format %{ %} 3401 interface(CONST_INTER); 3402 %} 3403 3404 // Integer Register Operands 3405 // Integer Register 3406 operand iRegI() %{ 3407 constraint(ALLOC_IN_RC(int_reg)); 3408 match(RegI); 3409 3410 match(notemp_iRegI); 3411 match(g1RegI); 3412 match(o0RegI); 3413 match(iRegIsafe); 3414 3415 format %{ %} 3416 interface(REG_INTER); 3417 %} 3418 3419 operand notemp_iRegI() %{ 3420 constraint(ALLOC_IN_RC(notemp_int_reg)); 3421 match(RegI); 3422 3423 match(o0RegI); 3424 3425 format %{ %} 3426 interface(REG_INTER); 3427 %} 3428 3429 operand o0RegI() %{ 3430 constraint(ALLOC_IN_RC(o0_regI)); 3431 match(iRegI); 3432 3433 format %{ %} 3434 interface(REG_INTER); 3435 %} 3436 3437 // Pointer Register 3438 operand iRegP() %{ 3439 constraint(ALLOC_IN_RC(ptr_reg)); 3440 match(RegP); 3441 3442 match(lock_ptr_RegP); 3443 match(g1RegP); 3444 match(g2RegP); 3445 match(g3RegP); 3446 match(g4RegP); 3447 match(i0RegP); 3448 match(o0RegP); 3449 match(o1RegP); 3450 match(l7RegP); 3451 3452 format %{ %} 3453 interface(REG_INTER); 3454 %} 3455 3456 operand sp_ptr_RegP() %{ 3457 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3458 match(RegP); 3459 match(iRegP); 3460 3461 format %{ %} 3462 interface(REG_INTER); 3463 %} 3464 3465 operand lock_ptr_RegP() %{ 3466 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3467 match(RegP); 3468 match(i0RegP); 3469 match(o0RegP); 3470 match(o1RegP); 3471 match(l7RegP); 3472 3473 format %{ %} 3474 interface(REG_INTER); 3475 %} 3476 3477 operand g1RegP() %{ 3478 constraint(ALLOC_IN_RC(g1_regP)); 3479 match(iRegP); 3480 3481 format %{ %} 3482 interface(REG_INTER); 3483 %} 3484 3485 operand g2RegP() %{ 3486 constraint(ALLOC_IN_RC(g2_regP)); 3487 match(iRegP); 3488 3489 format %{ %} 3490 interface(REG_INTER); 3491 %} 3492 3493 operand g3RegP() %{ 3494 constraint(ALLOC_IN_RC(g3_regP)); 3495 match(iRegP); 3496 3497 format %{ %} 3498 interface(REG_INTER); 3499 %} 3500 3501 operand g1RegI() %{ 3502 constraint(ALLOC_IN_RC(g1_regI)); 3503 match(iRegI); 3504 3505 format %{ %} 3506 interface(REG_INTER); 3507 %} 3508 3509 operand g3RegI() %{ 3510 constraint(ALLOC_IN_RC(g3_regI)); 3511 match(iRegI); 3512 3513 format %{ %} 3514 interface(REG_INTER); 3515 %} 3516 3517 operand g4RegI() %{ 3518 constraint(ALLOC_IN_RC(g4_regI)); 3519 match(iRegI); 3520 3521 format %{ %} 3522 interface(REG_INTER); 3523 %} 3524 3525 operand g4RegP() %{ 3526 constraint(ALLOC_IN_RC(g4_regP)); 3527 match(iRegP); 3528 3529 format %{ %} 3530 interface(REG_INTER); 3531 %} 3532 3533 operand i0RegP() %{ 3534 constraint(ALLOC_IN_RC(i0_regP)); 3535 match(iRegP); 3536 3537 format %{ %} 3538 interface(REG_INTER); 3539 %} 3540 3541 operand o0RegP() %{ 3542 constraint(ALLOC_IN_RC(o0_regP)); 3543 match(iRegP); 3544 3545 format %{ %} 3546 interface(REG_INTER); 3547 %} 3548 3549 operand o1RegP() %{ 3550 constraint(ALLOC_IN_RC(o1_regP)); 3551 match(iRegP); 3552 3553 format %{ %} 3554 interface(REG_INTER); 3555 %} 3556 3557 operand o2RegP() %{ 3558 constraint(ALLOC_IN_RC(o2_regP)); 3559 match(iRegP); 3560 3561 format %{ %} 3562 interface(REG_INTER); 3563 %} 3564 3565 operand o7RegP() %{ 3566 constraint(ALLOC_IN_RC(o7_regP)); 3567 match(iRegP); 3568 3569 format %{ %} 3570 interface(REG_INTER); 3571 %} 3572 3573 operand l7RegP() %{ 3574 constraint(ALLOC_IN_RC(l7_regP)); 3575 match(iRegP); 3576 3577 format %{ %} 3578 interface(REG_INTER); 3579 %} 3580 3581 operand o7RegI() %{ 3582 constraint(ALLOC_IN_RC(o7_regI)); 3583 match(iRegI); 3584 3585 format %{ %} 3586 interface(REG_INTER); 3587 %} 3588 3589 operand iRegN() %{ 3590 constraint(ALLOC_IN_RC(int_reg)); 3591 match(RegN); 3592 3593 format %{ %} 3594 interface(REG_INTER); 3595 %} 3596 3597 // Long Register 3598 operand iRegL() %{ 3599 constraint(ALLOC_IN_RC(long_reg)); 3600 match(RegL); 3601 3602 format %{ %} 3603 interface(REG_INTER); 3604 %} 3605 3606 operand o2RegL() %{ 3607 constraint(ALLOC_IN_RC(o2_regL)); 3608 match(iRegL); 3609 3610 format %{ %} 3611 interface(REG_INTER); 3612 %} 3613 3614 operand o7RegL() %{ 3615 constraint(ALLOC_IN_RC(o7_regL)); 3616 match(iRegL); 3617 3618 format %{ %} 3619 interface(REG_INTER); 3620 %} 3621 3622 operand g1RegL() %{ 3623 constraint(ALLOC_IN_RC(g1_regL)); 3624 match(iRegL); 3625 3626 format %{ %} 3627 interface(REG_INTER); 3628 %} 3629 3630 operand g3RegL() %{ 3631 constraint(ALLOC_IN_RC(g3_regL)); 3632 match(iRegL); 3633 3634 format %{ %} 3635 interface(REG_INTER); 3636 %} 3637 3638 // Int Register safe 3639 // This is 64bit safe 3640 operand iRegIsafe() %{ 3641 constraint(ALLOC_IN_RC(long_reg)); 3642 3643 match(iRegI); 3644 3645 format %{ %} 3646 interface(REG_INTER); 3647 %} 3648 3649 // Condition Code Flag Register 3650 operand flagsReg() %{ 3651 constraint(ALLOC_IN_RC(int_flags)); 3652 match(RegFlags); 3653 3654 format %{ "ccr" %} // both ICC and XCC 3655 interface(REG_INTER); 3656 %} 3657 3658 // Condition Code Register, unsigned comparisons. 3659 operand flagsRegU() %{ 3660 constraint(ALLOC_IN_RC(int_flags)); 3661 match(RegFlags); 3662 3663 format %{ "icc_U" %} 3664 interface(REG_INTER); 3665 %} 3666 3667 // Condition Code Register, pointer comparisons. 3668 operand flagsRegP() %{ 3669 constraint(ALLOC_IN_RC(int_flags)); 3670 match(RegFlags); 3671 3672 format %{ "xcc_P" %} 3673 interface(REG_INTER); 3674 %} 3675 3676 // Condition Code Register, long comparisons. 3677 operand flagsRegL() %{ 3678 constraint(ALLOC_IN_RC(int_flags)); 3679 match(RegFlags); 3680 3681 format %{ "xcc_L" %} 3682 interface(REG_INTER); 3683 %} 3684 3685 // Condition Code Register, floating comparisons, unordered same as "less". 3686 operand flagsRegF() %{ 3687 constraint(ALLOC_IN_RC(float_flags)); 3688 match(RegFlags); 3689 match(flagsRegF0); 3690 3691 format %{ %} 3692 interface(REG_INTER); 3693 %} 3694 3695 operand flagsRegF0() %{ 3696 constraint(ALLOC_IN_RC(float_flag0)); 3697 match(RegFlags); 3698 3699 format %{ %} 3700 interface(REG_INTER); 3701 %} 3702 3703 3704 // Condition Code Flag Register used by long compare 3705 operand flagsReg_long_LTGE() %{ 3706 constraint(ALLOC_IN_RC(int_flags)); 3707 match(RegFlags); 3708 format %{ "icc_LTGE" %} 3709 interface(REG_INTER); 3710 %} 3711 operand flagsReg_long_EQNE() %{ 3712 constraint(ALLOC_IN_RC(int_flags)); 3713 match(RegFlags); 3714 format %{ "icc_EQNE" %} 3715 interface(REG_INTER); 3716 %} 3717 operand flagsReg_long_LEGT() %{ 3718 constraint(ALLOC_IN_RC(int_flags)); 3719 match(RegFlags); 3720 format %{ "icc_LEGT" %} 3721 interface(REG_INTER); 3722 %} 3723 3724 3725 operand regD() %{ 3726 constraint(ALLOC_IN_RC(dflt_reg)); 3727 match(RegD); 3728 3729 match(regD_low); 3730 3731 format %{ %} 3732 interface(REG_INTER); 3733 %} 3734 3735 operand regF() %{ 3736 constraint(ALLOC_IN_RC(sflt_reg)); 3737 match(RegF); 3738 3739 format %{ %} 3740 interface(REG_INTER); 3741 %} 3742 3743 operand regD_low() %{ 3744 constraint(ALLOC_IN_RC(dflt_low_reg)); 3745 match(regD); 3746 3747 format %{ %} 3748 interface(REG_INTER); 3749 %} 3750 3751 // Special Registers 3752 3753 // Method Register 3754 operand inline_cache_regP(iRegP reg) %{ 3755 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 3756 match(reg); 3757 format %{ %} 3758 interface(REG_INTER); 3759 %} 3760 3761 operand interpreter_method_oop_regP(iRegP reg) %{ 3762 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 3763 match(reg); 3764 format %{ %} 3765 interface(REG_INTER); 3766 %} 3767 3768 3769 //----------Complex Operands--------------------------------------------------- 3770 // Indirect Memory Reference 3771 operand indirect(sp_ptr_RegP reg) %{ 3772 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3773 match(reg); 3774 3775 op_cost(100); 3776 format %{ "[$reg]" %} 3777 interface(MEMORY_INTER) %{ 3778 base($reg); 3779 index(0x0); 3780 scale(0x0); 3781 disp(0x0); 3782 %} 3783 %} 3784 3785 // Indirect with simm13 Offset 3786 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 3787 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3788 match(AddP reg offset); 3789 3790 op_cost(100); 3791 format %{ "[$reg + $offset]" %} 3792 interface(MEMORY_INTER) %{ 3793 base($reg); 3794 index(0x0); 3795 scale(0x0); 3796 disp($offset); 3797 %} 3798 %} 3799 3800 // Indirect with simm13 Offset minus 7 3801 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 3802 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3803 match(AddP reg offset); 3804 3805 op_cost(100); 3806 format %{ "[$reg + $offset]" %} 3807 interface(MEMORY_INTER) %{ 3808 base($reg); 3809 index(0x0); 3810 scale(0x0); 3811 disp($offset); 3812 %} 3813 %} 3814 3815 // Note: Intel has a swapped version also, like this: 3816 //operand indOffsetX(iRegI reg, immP offset) %{ 3817 // constraint(ALLOC_IN_RC(int_reg)); 3818 // match(AddP offset reg); 3819 // 3820 // op_cost(100); 3821 // format %{ "[$reg + $offset]" %} 3822 // interface(MEMORY_INTER) %{ 3823 // base($reg); 3824 // index(0x0); 3825 // scale(0x0); 3826 // disp($offset); 3827 // %} 3828 //%} 3829 //// However, it doesn't make sense for SPARC, since 3830 // we have no particularly good way to embed oops in 3831 // single instructions. 3832 3833 // Indirect with Register Index 3834 operand indIndex(iRegP addr, iRegX index) %{ 3835 constraint(ALLOC_IN_RC(ptr_reg)); 3836 match(AddP addr index); 3837 3838 op_cost(100); 3839 format %{ "[$addr + $index]" %} 3840 interface(MEMORY_INTER) %{ 3841 base($addr); 3842 index($index); 3843 scale(0x0); 3844 disp(0x0); 3845 %} 3846 %} 3847 3848 //----------Special Memory Operands-------------------------------------------- 3849 // Stack Slot Operand - This operand is used for loading and storing temporary 3850 // values on the stack where a match requires a value to 3851 // flow through memory. 3852 operand stackSlotI(sRegI reg) %{ 3853 constraint(ALLOC_IN_RC(stack_slots)); 3854 op_cost(100); 3855 //match(RegI); 3856 format %{ "[$reg]" %} 3857 interface(MEMORY_INTER) %{ 3858 base(0xE); // R_SP 3859 index(0x0); 3860 scale(0x0); 3861 disp($reg); // Stack Offset 3862 %} 3863 %} 3864 3865 operand stackSlotP(sRegP reg) %{ 3866 constraint(ALLOC_IN_RC(stack_slots)); 3867 op_cost(100); 3868 //match(RegP); 3869 format %{ "[$reg]" %} 3870 interface(MEMORY_INTER) %{ 3871 base(0xE); // R_SP 3872 index(0x0); 3873 scale(0x0); 3874 disp($reg); // Stack Offset 3875 %} 3876 %} 3877 3878 operand stackSlotF(sRegF reg) %{ 3879 constraint(ALLOC_IN_RC(stack_slots)); 3880 op_cost(100); 3881 //match(RegF); 3882 format %{ "[$reg]" %} 3883 interface(MEMORY_INTER) %{ 3884 base(0xE); // R_SP 3885 index(0x0); 3886 scale(0x0); 3887 disp($reg); // Stack Offset 3888 %} 3889 %} 3890 operand stackSlotD(sRegD reg) %{ 3891 constraint(ALLOC_IN_RC(stack_slots)); 3892 op_cost(100); 3893 //match(RegD); 3894 format %{ "[$reg]" %} 3895 interface(MEMORY_INTER) %{ 3896 base(0xE); // R_SP 3897 index(0x0); 3898 scale(0x0); 3899 disp($reg); // Stack Offset 3900 %} 3901 %} 3902 operand stackSlotL(sRegL reg) %{ 3903 constraint(ALLOC_IN_RC(stack_slots)); 3904 op_cost(100); 3905 //match(RegL); 3906 format %{ "[$reg]" %} 3907 interface(MEMORY_INTER) %{ 3908 base(0xE); // R_SP 3909 index(0x0); 3910 scale(0x0); 3911 disp($reg); // Stack Offset 3912 %} 3913 %} 3914 3915 // Operands for expressing Control Flow 3916 // NOTE: Label is a predefined operand which should not be redefined in 3917 // the AD file. It is generically handled within the ADLC. 3918 3919 //----------Conditional Branch Operands---------------------------------------- 3920 // Comparison Op - This is the operation of the comparison, and is limited to 3921 // the following set of codes: 3922 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 3923 // 3924 // Other attributes of the comparison, such as unsignedness, are specified 3925 // by the comparison instruction that sets a condition code flags register. 3926 // That result is represented by a flags operand whose subtype is appropriate 3927 // to the unsignedness (etc.) of the comparison. 3928 // 3929 // Later, the instruction which matches both the Comparison Op (a Bool) and 3930 // the flags (produced by the Cmp) specifies the coding of the comparison op 3931 // by matching a specific subtype of Bool operand below, such as cmpOpU. 3932 3933 operand cmpOp() %{ 3934 match(Bool); 3935 3936 format %{ "" %} 3937 interface(COND_INTER) %{ 3938 equal(0x1); 3939 not_equal(0x9); 3940 less(0x3); 3941 greater_equal(0xB); 3942 less_equal(0x2); 3943 greater(0xA); 3944 overflow(0x7); 3945 no_overflow(0xF); 3946 %} 3947 %} 3948 3949 // Comparison Op, unsigned 3950 operand cmpOpU() %{ 3951 match(Bool); 3952 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 3953 n->as_Bool()->_test._test != BoolTest::no_overflow); 3954 3955 format %{ "u" %} 3956 interface(COND_INTER) %{ 3957 equal(0x1); 3958 not_equal(0x9); 3959 less(0x5); 3960 greater_equal(0xD); 3961 less_equal(0x4); 3962 greater(0xC); 3963 overflow(0x7); 3964 no_overflow(0xF); 3965 %} 3966 %} 3967 3968 // Comparison Op, pointer (same as unsigned) 3969 operand cmpOpP() %{ 3970 match(Bool); 3971 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 3972 n->as_Bool()->_test._test != BoolTest::no_overflow); 3973 3974 format %{ "p" %} 3975 interface(COND_INTER) %{ 3976 equal(0x1); 3977 not_equal(0x9); 3978 less(0x5); 3979 greater_equal(0xD); 3980 less_equal(0x4); 3981 greater(0xC); 3982 overflow(0x7); 3983 no_overflow(0xF); 3984 %} 3985 %} 3986 3987 // Comparison Op, branch-register encoding 3988 operand cmpOp_reg() %{ 3989 match(Bool); 3990 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 3991 n->as_Bool()->_test._test != BoolTest::no_overflow); 3992 3993 format %{ "" %} 3994 interface(COND_INTER) %{ 3995 equal (0x1); 3996 not_equal (0x5); 3997 less (0x3); 3998 greater_equal(0x7); 3999 less_equal (0x2); 4000 greater (0x6); 4001 overflow(0x7); // not supported 4002 no_overflow(0xF); // not supported 4003 %} 4004 %} 4005 4006 // Comparison Code, floating, unordered same as less 4007 operand cmpOpF() %{ 4008 match(Bool); 4009 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4010 n->as_Bool()->_test._test != BoolTest::no_overflow); 4011 4012 format %{ "fl" %} 4013 interface(COND_INTER) %{ 4014 equal(0x9); 4015 not_equal(0x1); 4016 less(0x3); 4017 greater_equal(0xB); 4018 less_equal(0xE); 4019 greater(0x6); 4020 4021 overflow(0x7); // not supported 4022 no_overflow(0xF); // not supported 4023 %} 4024 %} 4025 4026 // Used by long compare 4027 operand cmpOp_commute() %{ 4028 match(Bool); 4029 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4030 n->as_Bool()->_test._test != BoolTest::no_overflow); 4031 4032 format %{ "" %} 4033 interface(COND_INTER) %{ 4034 equal(0x1); 4035 not_equal(0x9); 4036 less(0xA); 4037 greater_equal(0x2); 4038 less_equal(0xB); 4039 greater(0x3); 4040 overflow(0x7); 4041 no_overflow(0xF); 4042 %} 4043 %} 4044 4045 //----------OPERAND CLASSES---------------------------------------------------- 4046 // Operand Classes are groups of operands that are used to simplify 4047 // instruction definitions by not requiring the AD writer to specify separate 4048 // instructions for every form of operand when the instruction accepts 4049 // multiple operand types with the same basic encoding and format. The classic 4050 // case of this is memory operands. 4051 opclass memory( indirect, indOffset13, indIndex ); 4052 opclass indIndexMemory( indIndex ); 4053 4054 //----------PIPELINE----------------------------------------------------------- 4055 pipeline %{ 4056 4057 //----------ATTRIBUTES--------------------------------------------------------- 4058 attributes %{ 4059 fixed_size_instructions; // Fixed size instructions 4060 branch_has_delay_slot; // Branch has delay slot following 4061 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4062 instruction_unit_size = 4; // An instruction is 4 bytes long 4063 instruction_fetch_unit_size = 16; // The processor fetches one line 4064 instruction_fetch_units = 1; // of 16 bytes 4065 4066 // List of nop instructions 4067 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4068 %} 4069 4070 //----------RESOURCES---------------------------------------------------------- 4071 // Resources are the functional units available to the machine 4072 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4073 4074 //----------PIPELINE DESCRIPTION----------------------------------------------- 4075 // Pipeline Description specifies the stages in the machine's pipeline 4076 4077 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4078 4079 //----------PIPELINE CLASSES--------------------------------------------------- 4080 // Pipeline Classes describe the stages in which input and output are 4081 // referenced by the hardware pipeline. 4082 4083 // Integer ALU reg-reg operation 4084 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4085 single_instruction; 4086 dst : E(write); 4087 src1 : R(read); 4088 src2 : R(read); 4089 IALU : R; 4090 %} 4091 4092 // Integer ALU reg-reg long operation 4093 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4094 instruction_count(2); 4095 dst : E(write); 4096 src1 : R(read); 4097 src2 : R(read); 4098 IALU : R; 4099 IALU : R; 4100 %} 4101 4102 // Integer ALU reg-reg long dependent operation 4103 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4104 instruction_count(1); multiple_bundles; 4105 dst : E(write); 4106 src1 : R(read); 4107 src2 : R(read); 4108 cr : E(write); 4109 IALU : R(2); 4110 %} 4111 4112 // Integer ALU reg-imm operaion 4113 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4114 single_instruction; 4115 dst : E(write); 4116 src1 : R(read); 4117 IALU : R; 4118 %} 4119 4120 // Integer ALU reg-reg operation with condition code 4121 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4122 single_instruction; 4123 dst : E(write); 4124 cr : E(write); 4125 src1 : R(read); 4126 src2 : R(read); 4127 IALU : R; 4128 %} 4129 4130 // Integer ALU reg-imm operation with condition code 4131 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4132 single_instruction; 4133 dst : E(write); 4134 cr : E(write); 4135 src1 : R(read); 4136 IALU : R; 4137 %} 4138 4139 // Integer ALU zero-reg operation 4140 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4141 single_instruction; 4142 dst : E(write); 4143 src2 : R(read); 4144 IALU : R; 4145 %} 4146 4147 // Integer ALU zero-reg operation with condition code only 4148 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4149 single_instruction; 4150 cr : E(write); 4151 src : R(read); 4152 IALU : R; 4153 %} 4154 4155 // Integer ALU reg-reg operation with condition code only 4156 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4157 single_instruction; 4158 cr : E(write); 4159 src1 : R(read); 4160 src2 : R(read); 4161 IALU : R; 4162 %} 4163 4164 // Integer ALU reg-imm operation with condition code only 4165 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4166 single_instruction; 4167 cr : E(write); 4168 src1 : R(read); 4169 IALU : R; 4170 %} 4171 4172 // Integer ALU reg-reg-zero operation with condition code only 4173 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4174 single_instruction; 4175 cr : E(write); 4176 src1 : R(read); 4177 src2 : R(read); 4178 IALU : R; 4179 %} 4180 4181 // Integer ALU reg-imm-zero operation with condition code only 4182 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4183 single_instruction; 4184 cr : E(write); 4185 src1 : R(read); 4186 IALU : R; 4187 %} 4188 4189 // Integer ALU reg-reg operation with condition code, src1 modified 4190 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4191 single_instruction; 4192 cr : E(write); 4193 src1 : E(write); 4194 src1 : R(read); 4195 src2 : R(read); 4196 IALU : R; 4197 %} 4198 4199 // Integer ALU reg-imm operation with condition code, src1 modified 4200 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4201 single_instruction; 4202 cr : E(write); 4203 src1 : E(write); 4204 src1 : R(read); 4205 IALU : R; 4206 %} 4207 4208 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4209 multiple_bundles; 4210 dst : E(write)+4; 4211 cr : E(write); 4212 src1 : R(read); 4213 src2 : R(read); 4214 IALU : R(3); 4215 BR : R(2); 4216 %} 4217 4218 // Integer ALU operation 4219 pipe_class ialu_none(iRegI dst) %{ 4220 single_instruction; 4221 dst : E(write); 4222 IALU : R; 4223 %} 4224 4225 // Integer ALU reg operation 4226 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4227 single_instruction; may_have_no_code; 4228 dst : E(write); 4229 src : R(read); 4230 IALU : R; 4231 %} 4232 4233 // Integer ALU reg conditional operation 4234 // This instruction has a 1 cycle stall, and cannot execute 4235 // in the same cycle as the instruction setting the condition 4236 // code. We kludge this by pretending to read the condition code 4237 // 1 cycle earlier, and by marking the functional units as busy 4238 // for 2 cycles with the result available 1 cycle later than 4239 // is really the case. 4240 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4241 single_instruction; 4242 op2_out : C(write); 4243 op1 : R(read); 4244 cr : R(read); // This is really E, with a 1 cycle stall 4245 BR : R(2); 4246 MS : R(2); 4247 %} 4248 4249 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4250 instruction_count(1); multiple_bundles; 4251 dst : C(write)+1; 4252 src : R(read)+1; 4253 IALU : R(1); 4254 BR : E(2); 4255 MS : E(2); 4256 %} 4257 4258 // Integer ALU reg operation 4259 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4260 single_instruction; may_have_no_code; 4261 dst : E(write); 4262 src : R(read); 4263 IALU : R; 4264 %} 4265 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4266 single_instruction; may_have_no_code; 4267 dst : E(write); 4268 src : R(read); 4269 IALU : R; 4270 %} 4271 4272 // Two integer ALU reg operations 4273 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4274 instruction_count(2); 4275 dst : E(write); 4276 src : R(read); 4277 A0 : R; 4278 A1 : R; 4279 %} 4280 4281 // Two integer ALU reg operations 4282 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4283 instruction_count(2); may_have_no_code; 4284 dst : E(write); 4285 src : R(read); 4286 A0 : R; 4287 A1 : R; 4288 %} 4289 4290 // Integer ALU imm operation 4291 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4292 single_instruction; 4293 dst : E(write); 4294 IALU : R; 4295 %} 4296 4297 // Integer ALU reg-reg with carry operation 4298 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4299 single_instruction; 4300 dst : E(write); 4301 src1 : R(read); 4302 src2 : R(read); 4303 IALU : R; 4304 %} 4305 4306 // Integer ALU cc operation 4307 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4308 single_instruction; 4309 dst : E(write); 4310 cc : R(read); 4311 IALU : R; 4312 %} 4313 4314 // Integer ALU cc / second IALU operation 4315 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4316 instruction_count(1); multiple_bundles; 4317 dst : E(write)+1; 4318 src : R(read); 4319 IALU : R; 4320 %} 4321 4322 // Integer ALU cc / second IALU operation 4323 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4324 instruction_count(1); multiple_bundles; 4325 dst : E(write)+1; 4326 p : R(read); 4327 q : R(read); 4328 IALU : R; 4329 %} 4330 4331 // Integer ALU hi-lo-reg operation 4332 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4333 instruction_count(1); multiple_bundles; 4334 dst : E(write)+1; 4335 IALU : R(2); 4336 %} 4337 4338 // Float ALU hi-lo-reg operation (with temp) 4339 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4340 instruction_count(1); multiple_bundles; 4341 dst : E(write)+1; 4342 IALU : R(2); 4343 %} 4344 4345 // Long Constant 4346 pipe_class loadConL( iRegL dst, immL src ) %{ 4347 instruction_count(2); multiple_bundles; 4348 dst : E(write)+1; 4349 IALU : R(2); 4350 IALU : R(2); 4351 %} 4352 4353 // Pointer Constant 4354 pipe_class loadConP( iRegP dst, immP src ) %{ 4355 instruction_count(0); multiple_bundles; 4356 fixed_latency(6); 4357 %} 4358 4359 // Polling Address 4360 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4361 instruction_count(0); multiple_bundles; 4362 fixed_latency(6); 4363 %} 4364 4365 // Long Constant small 4366 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4367 instruction_count(2); 4368 dst : E(write); 4369 IALU : R; 4370 IALU : R; 4371 %} 4372 4373 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4374 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4375 instruction_count(1); multiple_bundles; 4376 src : R(read); 4377 dst : M(write)+1; 4378 IALU : R; 4379 MS : E; 4380 %} 4381 4382 // Integer ALU nop operation 4383 pipe_class ialu_nop() %{ 4384 single_instruction; 4385 IALU : R; 4386 %} 4387 4388 // Integer ALU nop operation 4389 pipe_class ialu_nop_A0() %{ 4390 single_instruction; 4391 A0 : R; 4392 %} 4393 4394 // Integer ALU nop operation 4395 pipe_class ialu_nop_A1() %{ 4396 single_instruction; 4397 A1 : R; 4398 %} 4399 4400 // Integer Multiply reg-reg operation 4401 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4402 single_instruction; 4403 dst : E(write); 4404 src1 : R(read); 4405 src2 : R(read); 4406 MS : R(5); 4407 %} 4408 4409 // Integer Multiply reg-imm operation 4410 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4411 single_instruction; 4412 dst : E(write); 4413 src1 : R(read); 4414 MS : R(5); 4415 %} 4416 4417 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4418 single_instruction; 4419 dst : E(write)+4; 4420 src1 : R(read); 4421 src2 : R(read); 4422 MS : R(6); 4423 %} 4424 4425 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4426 single_instruction; 4427 dst : E(write)+4; 4428 src1 : R(read); 4429 MS : R(6); 4430 %} 4431 4432 // Integer Divide reg-reg 4433 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4434 instruction_count(1); multiple_bundles; 4435 dst : E(write); 4436 temp : E(write); 4437 src1 : R(read); 4438 src2 : R(read); 4439 temp : R(read); 4440 MS : R(38); 4441 %} 4442 4443 // Integer Divide reg-imm 4444 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4445 instruction_count(1); multiple_bundles; 4446 dst : E(write); 4447 temp : E(write); 4448 src1 : R(read); 4449 temp : R(read); 4450 MS : R(38); 4451 %} 4452 4453 // Long Divide 4454 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4455 dst : E(write)+71; 4456 src1 : R(read); 4457 src2 : R(read)+1; 4458 MS : R(70); 4459 %} 4460 4461 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4462 dst : E(write)+71; 4463 src1 : R(read); 4464 MS : R(70); 4465 %} 4466 4467 // Floating Point Add Float 4468 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4469 single_instruction; 4470 dst : X(write); 4471 src1 : E(read); 4472 src2 : E(read); 4473 FA : R; 4474 %} 4475 4476 // Floating Point Add Double 4477 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4478 single_instruction; 4479 dst : X(write); 4480 src1 : E(read); 4481 src2 : E(read); 4482 FA : R; 4483 %} 4484 4485 // Floating Point Conditional Move based on integer flags 4486 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4487 single_instruction; 4488 dst : X(write); 4489 src : E(read); 4490 cr : R(read); 4491 FA : R(2); 4492 BR : R(2); 4493 %} 4494 4495 // Floating Point Conditional Move based on integer flags 4496 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4497 single_instruction; 4498 dst : X(write); 4499 src : E(read); 4500 cr : R(read); 4501 FA : R(2); 4502 BR : R(2); 4503 %} 4504 4505 // Floating Point Multiply Float 4506 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4507 single_instruction; 4508 dst : X(write); 4509 src1 : E(read); 4510 src2 : E(read); 4511 FM : R; 4512 %} 4513 4514 // Floating Point Multiply Double 4515 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4516 single_instruction; 4517 dst : X(write); 4518 src1 : E(read); 4519 src2 : E(read); 4520 FM : R; 4521 %} 4522 4523 // Floating Point Divide Float 4524 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4525 single_instruction; 4526 dst : X(write); 4527 src1 : E(read); 4528 src2 : E(read); 4529 FM : R; 4530 FDIV : C(14); 4531 %} 4532 4533 // Floating Point Divide Double 4534 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4535 single_instruction; 4536 dst : X(write); 4537 src1 : E(read); 4538 src2 : E(read); 4539 FM : R; 4540 FDIV : C(17); 4541 %} 4542 4543 // Floating Point Move/Negate/Abs Float 4544 pipe_class faddF_reg(regF dst, regF src) %{ 4545 single_instruction; 4546 dst : W(write); 4547 src : E(read); 4548 FA : R(1); 4549 %} 4550 4551 // Floating Point Move/Negate/Abs Double 4552 pipe_class faddD_reg(regD dst, regD src) %{ 4553 single_instruction; 4554 dst : W(write); 4555 src : E(read); 4556 FA : R; 4557 %} 4558 4559 // Floating Point Convert F->D 4560 pipe_class fcvtF2D(regD dst, regF src) %{ 4561 single_instruction; 4562 dst : X(write); 4563 src : E(read); 4564 FA : R; 4565 %} 4566 4567 // Floating Point Convert I->D 4568 pipe_class fcvtI2D(regD dst, regF src) %{ 4569 single_instruction; 4570 dst : X(write); 4571 src : E(read); 4572 FA : R; 4573 %} 4574 4575 // Floating Point Convert LHi->D 4576 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4577 single_instruction; 4578 dst : X(write); 4579 src : E(read); 4580 FA : R; 4581 %} 4582 4583 // Floating Point Convert L->D 4584 pipe_class fcvtL2D(regD dst, regF src) %{ 4585 single_instruction; 4586 dst : X(write); 4587 src : E(read); 4588 FA : R; 4589 %} 4590 4591 // Floating Point Convert L->F 4592 pipe_class fcvtL2F(regD dst, regF src) %{ 4593 single_instruction; 4594 dst : X(write); 4595 src : E(read); 4596 FA : R; 4597 %} 4598 4599 // Floating Point Convert D->F 4600 pipe_class fcvtD2F(regD dst, regF src) %{ 4601 single_instruction; 4602 dst : X(write); 4603 src : E(read); 4604 FA : R; 4605 %} 4606 4607 // Floating Point Convert I->L 4608 pipe_class fcvtI2L(regD dst, regF src) %{ 4609 single_instruction; 4610 dst : X(write); 4611 src : E(read); 4612 FA : R; 4613 %} 4614 4615 // Floating Point Convert D->F 4616 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4617 instruction_count(1); multiple_bundles; 4618 dst : X(write)+6; 4619 src : E(read); 4620 FA : R; 4621 %} 4622 4623 // Floating Point Convert D->L 4624 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4625 instruction_count(1); multiple_bundles; 4626 dst : X(write)+6; 4627 src : E(read); 4628 FA : R; 4629 %} 4630 4631 // Floating Point Convert F->I 4632 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4633 instruction_count(1); multiple_bundles; 4634 dst : X(write)+6; 4635 src : E(read); 4636 FA : R; 4637 %} 4638 4639 // Floating Point Convert F->L 4640 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4641 instruction_count(1); multiple_bundles; 4642 dst : X(write)+6; 4643 src : E(read); 4644 FA : R; 4645 %} 4646 4647 // Floating Point Convert I->F 4648 pipe_class fcvtI2F(regF dst, regF src) %{ 4649 single_instruction; 4650 dst : X(write); 4651 src : E(read); 4652 FA : R; 4653 %} 4654 4655 // Floating Point Compare 4656 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4657 single_instruction; 4658 cr : X(write); 4659 src1 : E(read); 4660 src2 : E(read); 4661 FA : R; 4662 %} 4663 4664 // Floating Point Compare 4665 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4666 single_instruction; 4667 cr : X(write); 4668 src1 : E(read); 4669 src2 : E(read); 4670 FA : R; 4671 %} 4672 4673 // Floating Add Nop 4674 pipe_class fadd_nop() %{ 4675 single_instruction; 4676 FA : R; 4677 %} 4678 4679 // Integer Store to Memory 4680 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4681 single_instruction; 4682 mem : R(read); 4683 src : C(read); 4684 MS : R; 4685 %} 4686 4687 // Integer Store to Memory 4688 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4689 single_instruction; 4690 mem : R(read); 4691 src : C(read); 4692 MS : R; 4693 %} 4694 4695 // Integer Store Zero to Memory 4696 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4697 single_instruction; 4698 mem : R(read); 4699 MS : R; 4700 %} 4701 4702 // Special Stack Slot Store 4703 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4704 single_instruction; 4705 stkSlot : R(read); 4706 src : C(read); 4707 MS : R; 4708 %} 4709 4710 // Special Stack Slot Store 4711 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4712 instruction_count(2); multiple_bundles; 4713 stkSlot : R(read); 4714 src : C(read); 4715 MS : R(2); 4716 %} 4717 4718 // Float Store 4719 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4720 single_instruction; 4721 mem : R(read); 4722 src : C(read); 4723 MS : R; 4724 %} 4725 4726 // Float Store 4727 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4728 single_instruction; 4729 mem : R(read); 4730 MS : R; 4731 %} 4732 4733 // Double Store 4734 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4735 instruction_count(1); 4736 mem : R(read); 4737 src : C(read); 4738 MS : R; 4739 %} 4740 4741 // Double Store 4742 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 4743 single_instruction; 4744 mem : R(read); 4745 MS : R; 4746 %} 4747 4748 // Special Stack Slot Float Store 4749 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 4750 single_instruction; 4751 stkSlot : R(read); 4752 src : C(read); 4753 MS : R; 4754 %} 4755 4756 // Special Stack Slot Double Store 4757 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 4758 single_instruction; 4759 stkSlot : R(read); 4760 src : C(read); 4761 MS : R; 4762 %} 4763 4764 // Integer Load (when sign bit propagation not needed) 4765 pipe_class iload_mem(iRegI dst, memory mem) %{ 4766 single_instruction; 4767 mem : R(read); 4768 dst : C(write); 4769 MS : R; 4770 %} 4771 4772 // Integer Load from stack operand 4773 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 4774 single_instruction; 4775 mem : R(read); 4776 dst : C(write); 4777 MS : R; 4778 %} 4779 4780 // Integer Load (when sign bit propagation or masking is needed) 4781 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 4782 single_instruction; 4783 mem : R(read); 4784 dst : M(write); 4785 MS : R; 4786 %} 4787 4788 // Float Load 4789 pipe_class floadF_mem(regF dst, memory mem) %{ 4790 single_instruction; 4791 mem : R(read); 4792 dst : M(write); 4793 MS : R; 4794 %} 4795 4796 // Float Load 4797 pipe_class floadD_mem(regD dst, memory mem) %{ 4798 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 4799 mem : R(read); 4800 dst : M(write); 4801 MS : R; 4802 %} 4803 4804 // Float Load 4805 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 4806 single_instruction; 4807 stkSlot : R(read); 4808 dst : M(write); 4809 MS : R; 4810 %} 4811 4812 // Float Load 4813 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 4814 single_instruction; 4815 stkSlot : R(read); 4816 dst : M(write); 4817 MS : R; 4818 %} 4819 4820 // Memory Nop 4821 pipe_class mem_nop() %{ 4822 single_instruction; 4823 MS : R; 4824 %} 4825 4826 pipe_class sethi(iRegP dst, immI src) %{ 4827 single_instruction; 4828 dst : E(write); 4829 IALU : R; 4830 %} 4831 4832 pipe_class loadPollP(iRegP poll) %{ 4833 single_instruction; 4834 poll : R(read); 4835 MS : R; 4836 %} 4837 4838 pipe_class br(Universe br, label labl) %{ 4839 single_instruction_with_delay_slot; 4840 BR : R; 4841 %} 4842 4843 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 4844 single_instruction_with_delay_slot; 4845 cr : E(read); 4846 BR : R; 4847 %} 4848 4849 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 4850 single_instruction_with_delay_slot; 4851 op1 : E(read); 4852 BR : R; 4853 MS : R; 4854 %} 4855 4856 // Compare and branch 4857 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 4858 instruction_count(2); has_delay_slot; 4859 cr : E(write); 4860 src1 : R(read); 4861 src2 : R(read); 4862 IALU : R; 4863 BR : R; 4864 %} 4865 4866 // Compare and branch 4867 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 4868 instruction_count(2); has_delay_slot; 4869 cr : E(write); 4870 src1 : R(read); 4871 IALU : R; 4872 BR : R; 4873 %} 4874 4875 // Compare and branch using cbcond 4876 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 4877 single_instruction; 4878 src1 : E(read); 4879 src2 : E(read); 4880 IALU : R; 4881 BR : R; 4882 %} 4883 4884 // Compare and branch using cbcond 4885 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 4886 single_instruction; 4887 src1 : E(read); 4888 IALU : R; 4889 BR : R; 4890 %} 4891 4892 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 4893 single_instruction_with_delay_slot; 4894 cr : E(read); 4895 BR : R; 4896 %} 4897 4898 pipe_class br_nop() %{ 4899 single_instruction; 4900 BR : R; 4901 %} 4902 4903 pipe_class simple_call(method meth) %{ 4904 instruction_count(2); multiple_bundles; force_serialization; 4905 fixed_latency(100); 4906 BR : R(1); 4907 MS : R(1); 4908 A0 : R(1); 4909 %} 4910 4911 pipe_class compiled_call(method meth) %{ 4912 instruction_count(1); multiple_bundles; force_serialization; 4913 fixed_latency(100); 4914 MS : R(1); 4915 %} 4916 4917 pipe_class call(method meth) %{ 4918 instruction_count(0); multiple_bundles; force_serialization; 4919 fixed_latency(100); 4920 %} 4921 4922 pipe_class tail_call(Universe ignore, label labl) %{ 4923 single_instruction; has_delay_slot; 4924 fixed_latency(100); 4925 BR : R(1); 4926 MS : R(1); 4927 %} 4928 4929 pipe_class ret(Universe ignore) %{ 4930 single_instruction; has_delay_slot; 4931 BR : R(1); 4932 MS : R(1); 4933 %} 4934 4935 pipe_class ret_poll(g3RegP poll) %{ 4936 instruction_count(3); has_delay_slot; 4937 poll : E(read); 4938 MS : R; 4939 %} 4940 4941 // The real do-nothing guy 4942 pipe_class empty( ) %{ 4943 instruction_count(0); 4944 %} 4945 4946 pipe_class long_memory_op() %{ 4947 instruction_count(0); multiple_bundles; force_serialization; 4948 fixed_latency(25); 4949 MS : R(1); 4950 %} 4951 4952 // Check-cast 4953 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 4954 array : R(read); 4955 match : R(read); 4956 IALU : R(2); 4957 BR : R(2); 4958 MS : R; 4959 %} 4960 4961 // Convert FPU flags into +1,0,-1 4962 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 4963 src1 : E(read); 4964 src2 : E(read); 4965 dst : E(write); 4966 FA : R; 4967 MS : R(2); 4968 BR : R(2); 4969 %} 4970 4971 // Compare for p < q, and conditionally add y 4972 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 4973 p : E(read); 4974 q : E(read); 4975 y : E(read); 4976 IALU : R(3) 4977 %} 4978 4979 // Perform a compare, then move conditionally in a branch delay slot. 4980 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 4981 src2 : E(read); 4982 srcdst : E(read); 4983 IALU : R; 4984 BR : R; 4985 %} 4986 4987 // Define the class for the Nop node 4988 define %{ 4989 MachNop = ialu_nop; 4990 %} 4991 4992 %} 4993 4994 //----------INSTRUCTIONS------------------------------------------------------- 4995 4996 //------------Special Stack Slot instructions - no match rules----------------- 4997 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 4998 // No match rule to avoid chain rule match. 4999 effect(DEF dst, USE src); 5000 ins_cost(MEMORY_REF_COST); 5001 format %{ "LDF $src,$dst\t! stkI to regF" %} 5002 opcode(Assembler::ldf_op3); 5003 ins_encode(simple_form3_mem_reg(src, dst)); 5004 ins_pipe(floadF_stk); 5005 %} 5006 5007 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5008 // No match rule to avoid chain rule match. 5009 effect(DEF dst, USE src); 5010 ins_cost(MEMORY_REF_COST); 5011 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5012 opcode(Assembler::lddf_op3); 5013 ins_encode(simple_form3_mem_reg(src, dst)); 5014 ins_pipe(floadD_stk); 5015 %} 5016 5017 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5018 // No match rule to avoid chain rule match. 5019 effect(DEF dst, USE src); 5020 ins_cost(MEMORY_REF_COST); 5021 format %{ "STF $src,$dst\t! regF to stkI" %} 5022 opcode(Assembler::stf_op3); 5023 ins_encode(simple_form3_mem_reg(dst, src)); 5024 ins_pipe(fstoreF_stk_reg); 5025 %} 5026 5027 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5028 // No match rule to avoid chain rule match. 5029 effect(DEF dst, USE src); 5030 ins_cost(MEMORY_REF_COST); 5031 format %{ "STDF $src,$dst\t! regD to stkL" %} 5032 opcode(Assembler::stdf_op3); 5033 ins_encode(simple_form3_mem_reg(dst, src)); 5034 ins_pipe(fstoreD_stk_reg); 5035 %} 5036 5037 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5038 effect(DEF dst, USE src); 5039 ins_cost(MEMORY_REF_COST*2); 5040 format %{ "STW $src,$dst.hi\t! long\n\t" 5041 "STW R_G0,$dst.lo" %} 5042 opcode(Assembler::stw_op3); 5043 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5044 ins_pipe(lstoreI_stk_reg); 5045 %} 5046 5047 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5048 // No match rule to avoid chain rule match. 5049 effect(DEF dst, USE src); 5050 ins_cost(MEMORY_REF_COST); 5051 format %{ "STX $src,$dst\t! regL to stkD" %} 5052 opcode(Assembler::stx_op3); 5053 ins_encode(simple_form3_mem_reg( dst, src ) ); 5054 ins_pipe(istore_stk_reg); 5055 %} 5056 5057 //---------- Chain stack slots between similar types -------- 5058 5059 // Load integer from stack slot 5060 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5061 match(Set dst src); 5062 ins_cost(MEMORY_REF_COST); 5063 5064 format %{ "LDUW $src,$dst\t!stk" %} 5065 opcode(Assembler::lduw_op3); 5066 ins_encode(simple_form3_mem_reg( src, dst ) ); 5067 ins_pipe(iload_mem); 5068 %} 5069 5070 // Store integer to stack slot 5071 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5072 match(Set dst src); 5073 ins_cost(MEMORY_REF_COST); 5074 5075 format %{ "STW $src,$dst\t!stk" %} 5076 opcode(Assembler::stw_op3); 5077 ins_encode(simple_form3_mem_reg( dst, src ) ); 5078 ins_pipe(istore_mem_reg); 5079 %} 5080 5081 // Load long from stack slot 5082 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5083 match(Set dst src); 5084 5085 ins_cost(MEMORY_REF_COST); 5086 format %{ "LDX $src,$dst\t! long" %} 5087 opcode(Assembler::ldx_op3); 5088 ins_encode(simple_form3_mem_reg( src, dst ) ); 5089 ins_pipe(iload_mem); 5090 %} 5091 5092 // Store long to stack slot 5093 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5094 match(Set dst src); 5095 5096 ins_cost(MEMORY_REF_COST); 5097 format %{ "STX $src,$dst\t! long" %} 5098 opcode(Assembler::stx_op3); 5099 ins_encode(simple_form3_mem_reg( dst, src ) ); 5100 ins_pipe(istore_mem_reg); 5101 %} 5102 5103 // Load pointer from stack slot, 64-bit encoding 5104 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5105 match(Set dst src); 5106 ins_cost(MEMORY_REF_COST); 5107 format %{ "LDX $src,$dst\t!ptr" %} 5108 opcode(Assembler::ldx_op3); 5109 ins_encode(simple_form3_mem_reg( src, dst ) ); 5110 ins_pipe(iload_mem); 5111 %} 5112 5113 // Store pointer to stack slot 5114 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5115 match(Set dst src); 5116 ins_cost(MEMORY_REF_COST); 5117 format %{ "STX $src,$dst\t!ptr" %} 5118 opcode(Assembler::stx_op3); 5119 ins_encode(simple_form3_mem_reg( dst, src ) ); 5120 ins_pipe(istore_mem_reg); 5121 %} 5122 5123 //------------Special Nop instructions for bundling - no match rules----------- 5124 // Nop using the A0 functional unit 5125 instruct Nop_A0() %{ 5126 ins_cost(0); 5127 5128 format %{ "NOP ! Alu Pipeline" %} 5129 opcode(Assembler::or_op3, Assembler::arith_op); 5130 ins_encode( form2_nop() ); 5131 ins_pipe(ialu_nop_A0); 5132 %} 5133 5134 // Nop using the A1 functional unit 5135 instruct Nop_A1( ) %{ 5136 ins_cost(0); 5137 5138 format %{ "NOP ! Alu Pipeline" %} 5139 opcode(Assembler::or_op3, Assembler::arith_op); 5140 ins_encode( form2_nop() ); 5141 ins_pipe(ialu_nop_A1); 5142 %} 5143 5144 // Nop using the memory functional unit 5145 instruct Nop_MS( ) %{ 5146 ins_cost(0); 5147 5148 format %{ "NOP ! Memory Pipeline" %} 5149 ins_encode( emit_mem_nop ); 5150 ins_pipe(mem_nop); 5151 %} 5152 5153 // Nop using the floating add functional unit 5154 instruct Nop_FA( ) %{ 5155 ins_cost(0); 5156 5157 format %{ "NOP ! Floating Add Pipeline" %} 5158 ins_encode( emit_fadd_nop ); 5159 ins_pipe(fadd_nop); 5160 %} 5161 5162 // Nop using the branch functional unit 5163 instruct Nop_BR( ) %{ 5164 ins_cost(0); 5165 5166 format %{ "NOP ! Branch Pipeline" %} 5167 ins_encode( emit_br_nop ); 5168 ins_pipe(br_nop); 5169 %} 5170 5171 //----------Load/Store/Move Instructions--------------------------------------- 5172 //----------Load Instructions-------------------------------------------------- 5173 // Load Byte (8bit signed) 5174 instruct loadB(iRegI dst, memory mem) %{ 5175 match(Set dst (LoadB mem)); 5176 ins_cost(MEMORY_REF_COST); 5177 5178 size(4); 5179 format %{ "LDSB $mem,$dst\t! byte" %} 5180 ins_encode %{ 5181 __ ldsb($mem$$Address, $dst$$Register); 5182 %} 5183 ins_pipe(iload_mask_mem); 5184 %} 5185 5186 // Load Byte (8bit signed) into a Long Register 5187 instruct loadB2L(iRegL dst, memory mem) %{ 5188 match(Set dst (ConvI2L (LoadB mem))); 5189 ins_cost(MEMORY_REF_COST); 5190 5191 size(4); 5192 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5193 ins_encode %{ 5194 __ ldsb($mem$$Address, $dst$$Register); 5195 %} 5196 ins_pipe(iload_mask_mem); 5197 %} 5198 5199 // Load Unsigned Byte (8bit UNsigned) into an int reg 5200 instruct loadUB(iRegI dst, memory mem) %{ 5201 match(Set dst (LoadUB mem)); 5202 ins_cost(MEMORY_REF_COST); 5203 5204 size(4); 5205 format %{ "LDUB $mem,$dst\t! ubyte" %} 5206 ins_encode %{ 5207 __ ldub($mem$$Address, $dst$$Register); 5208 %} 5209 ins_pipe(iload_mem); 5210 %} 5211 5212 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5213 instruct loadUB2L(iRegL dst, memory mem) %{ 5214 match(Set dst (ConvI2L (LoadUB mem))); 5215 ins_cost(MEMORY_REF_COST); 5216 5217 size(4); 5218 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5219 ins_encode %{ 5220 __ ldub($mem$$Address, $dst$$Register); 5221 %} 5222 ins_pipe(iload_mem); 5223 %} 5224 5225 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register 5226 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{ 5227 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5228 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5229 5230 size(2*4); 5231 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t" 5232 "AND $dst,right_n_bits($mask, 8),$dst" %} 5233 ins_encode %{ 5234 __ ldub($mem$$Address, $dst$$Register); 5235 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register); 5236 %} 5237 ins_pipe(iload_mem); 5238 %} 5239 5240 // Load Short (16bit signed) 5241 instruct loadS(iRegI dst, memory mem) %{ 5242 match(Set dst (LoadS mem)); 5243 ins_cost(MEMORY_REF_COST); 5244 5245 size(4); 5246 format %{ "LDSH $mem,$dst\t! short" %} 5247 ins_encode %{ 5248 __ ldsh($mem$$Address, $dst$$Register); 5249 %} 5250 ins_pipe(iload_mask_mem); 5251 %} 5252 5253 // Load Short (16 bit signed) to Byte (8 bit signed) 5254 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5255 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5256 ins_cost(MEMORY_REF_COST); 5257 5258 size(4); 5259 5260 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5261 ins_encode %{ 5262 __ ldsb($mem$$Address, $dst$$Register, 1); 5263 %} 5264 ins_pipe(iload_mask_mem); 5265 %} 5266 5267 // Load Short (16bit signed) into a Long Register 5268 instruct loadS2L(iRegL dst, memory mem) %{ 5269 match(Set dst (ConvI2L (LoadS mem))); 5270 ins_cost(MEMORY_REF_COST); 5271 5272 size(4); 5273 format %{ "LDSH $mem,$dst\t! short -> long" %} 5274 ins_encode %{ 5275 __ ldsh($mem$$Address, $dst$$Register); 5276 %} 5277 ins_pipe(iload_mask_mem); 5278 %} 5279 5280 // Load Unsigned Short/Char (16bit UNsigned) 5281 instruct loadUS(iRegI dst, memory mem) %{ 5282 match(Set dst (LoadUS mem)); 5283 ins_cost(MEMORY_REF_COST); 5284 5285 size(4); 5286 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5287 ins_encode %{ 5288 __ lduh($mem$$Address, $dst$$Register); 5289 %} 5290 ins_pipe(iload_mem); 5291 %} 5292 5293 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5294 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5295 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5296 ins_cost(MEMORY_REF_COST); 5297 5298 size(4); 5299 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5300 ins_encode %{ 5301 __ ldsb($mem$$Address, $dst$$Register, 1); 5302 %} 5303 ins_pipe(iload_mask_mem); 5304 %} 5305 5306 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5307 instruct loadUS2L(iRegL dst, memory mem) %{ 5308 match(Set dst (ConvI2L (LoadUS mem))); 5309 ins_cost(MEMORY_REF_COST); 5310 5311 size(4); 5312 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5313 ins_encode %{ 5314 __ lduh($mem$$Address, $dst$$Register); 5315 %} 5316 ins_pipe(iload_mem); 5317 %} 5318 5319 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5320 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5321 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5322 ins_cost(MEMORY_REF_COST); 5323 5324 size(4); 5325 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5326 ins_encode %{ 5327 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5328 %} 5329 ins_pipe(iload_mem); 5330 %} 5331 5332 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5333 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5334 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5335 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5336 5337 size(2*4); 5338 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5339 "AND $dst,$mask,$dst" %} 5340 ins_encode %{ 5341 Register Rdst = $dst$$Register; 5342 __ lduh($mem$$Address, Rdst); 5343 __ and3(Rdst, $mask$$constant, Rdst); 5344 %} 5345 ins_pipe(iload_mem); 5346 %} 5347 5348 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register 5349 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5350 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5351 effect(TEMP dst, TEMP tmp); 5352 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5353 5354 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t" 5355 "SET right_n_bits($mask, 16),$tmp\n\t" 5356 "AND $dst,$tmp,$dst" %} 5357 ins_encode %{ 5358 Register Rdst = $dst$$Register; 5359 Register Rtmp = $tmp$$Register; 5360 __ lduh($mem$$Address, Rdst); 5361 __ set($mask$$constant & right_n_bits(16), Rtmp); 5362 __ and3(Rdst, Rtmp, Rdst); 5363 %} 5364 ins_pipe(iload_mem); 5365 %} 5366 5367 // Load Integer 5368 instruct loadI(iRegI dst, memory mem) %{ 5369 match(Set dst (LoadI mem)); 5370 ins_cost(MEMORY_REF_COST); 5371 5372 size(4); 5373 format %{ "LDUW $mem,$dst\t! int" %} 5374 ins_encode %{ 5375 __ lduw($mem$$Address, $dst$$Register); 5376 %} 5377 ins_pipe(iload_mem); 5378 %} 5379 5380 // Load Integer to Byte (8 bit signed) 5381 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5382 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5383 ins_cost(MEMORY_REF_COST); 5384 5385 size(4); 5386 5387 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5388 ins_encode %{ 5389 __ ldsb($mem$$Address, $dst$$Register, 3); 5390 %} 5391 ins_pipe(iload_mask_mem); 5392 %} 5393 5394 // Load Integer to Unsigned Byte (8 bit UNsigned) 5395 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5396 match(Set dst (AndI (LoadI mem) mask)); 5397 ins_cost(MEMORY_REF_COST); 5398 5399 size(4); 5400 5401 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5402 ins_encode %{ 5403 __ ldub($mem$$Address, $dst$$Register, 3); 5404 %} 5405 ins_pipe(iload_mask_mem); 5406 %} 5407 5408 // Load Integer to Short (16 bit signed) 5409 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5410 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5411 ins_cost(MEMORY_REF_COST); 5412 5413 size(4); 5414 5415 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5416 ins_encode %{ 5417 __ ldsh($mem$$Address, $dst$$Register, 2); 5418 %} 5419 ins_pipe(iload_mask_mem); 5420 %} 5421 5422 // Load Integer to Unsigned Short (16 bit UNsigned) 5423 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5424 match(Set dst (AndI (LoadI mem) mask)); 5425 ins_cost(MEMORY_REF_COST); 5426 5427 size(4); 5428 5429 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5430 ins_encode %{ 5431 __ lduh($mem$$Address, $dst$$Register, 2); 5432 %} 5433 ins_pipe(iload_mask_mem); 5434 %} 5435 5436 // Load Integer into a Long Register 5437 instruct loadI2L(iRegL dst, memory mem) %{ 5438 match(Set dst (ConvI2L (LoadI mem))); 5439 ins_cost(MEMORY_REF_COST); 5440 5441 size(4); 5442 format %{ "LDSW $mem,$dst\t! int -> long" %} 5443 ins_encode %{ 5444 __ ldsw($mem$$Address, $dst$$Register); 5445 %} 5446 ins_pipe(iload_mask_mem); 5447 %} 5448 5449 // Load Integer with mask 0xFF into a Long Register 5450 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5451 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5452 ins_cost(MEMORY_REF_COST); 5453 5454 size(4); 5455 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5456 ins_encode %{ 5457 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5458 %} 5459 ins_pipe(iload_mem); 5460 %} 5461 5462 // Load Integer with mask 0xFFFF into a Long Register 5463 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5464 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5465 ins_cost(MEMORY_REF_COST); 5466 5467 size(4); 5468 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5469 ins_encode %{ 5470 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5471 %} 5472 ins_pipe(iload_mem); 5473 %} 5474 5475 // Load Integer with a 12-bit mask into a Long Register 5476 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ 5477 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5478 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5479 5480 size(2*4); 5481 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" 5482 "AND $dst,$mask,$dst" %} 5483 ins_encode %{ 5484 Register Rdst = $dst$$Register; 5485 __ lduw($mem$$Address, Rdst); 5486 __ and3(Rdst, $mask$$constant, Rdst); 5487 %} 5488 ins_pipe(iload_mem); 5489 %} 5490 5491 // Load Integer with a 31-bit mask into a Long Register 5492 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ 5493 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5494 effect(TEMP dst, TEMP tmp); 5495 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5496 5497 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" 5498 "SET $mask,$tmp\n\t" 5499 "AND $dst,$tmp,$dst" %} 5500 ins_encode %{ 5501 Register Rdst = $dst$$Register; 5502 Register Rtmp = $tmp$$Register; 5503 __ lduw($mem$$Address, Rdst); 5504 __ set($mask$$constant, Rtmp); 5505 __ and3(Rdst, Rtmp, Rdst); 5506 %} 5507 ins_pipe(iload_mem); 5508 %} 5509 5510 // Load Unsigned Integer into a Long Register 5511 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ 5512 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5513 ins_cost(MEMORY_REF_COST); 5514 5515 size(4); 5516 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5517 ins_encode %{ 5518 __ lduw($mem$$Address, $dst$$Register); 5519 %} 5520 ins_pipe(iload_mem); 5521 %} 5522 5523 // Load Long - aligned 5524 instruct loadL(iRegL dst, memory mem ) %{ 5525 match(Set dst (LoadL mem)); 5526 ins_cost(MEMORY_REF_COST); 5527 5528 size(4); 5529 format %{ "LDX $mem,$dst\t! long" %} 5530 ins_encode %{ 5531 __ ldx($mem$$Address, $dst$$Register); 5532 %} 5533 ins_pipe(iload_mem); 5534 %} 5535 5536 // Load Long - UNaligned 5537 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5538 match(Set dst (LoadL_unaligned mem)); 5539 effect(KILL tmp); 5540 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5541 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5542 "\tLDUW $mem ,$dst\n" 5543 "\tSLLX #32, $dst, $dst\n" 5544 "\tOR $dst, R_O7, $dst" %} 5545 opcode(Assembler::lduw_op3); 5546 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5547 ins_pipe(iload_mem); 5548 %} 5549 5550 // Load Range 5551 instruct loadRange(iRegI dst, memory mem) %{ 5552 match(Set dst (LoadRange mem)); 5553 ins_cost(MEMORY_REF_COST); 5554 5555 format %{ "LDUW $mem,$dst\t! range" %} 5556 opcode(Assembler::lduw_op3); 5557 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5558 ins_pipe(iload_mem); 5559 %} 5560 5561 // Load Integer into %f register (for fitos/fitod) 5562 instruct loadI_freg(regF dst, memory mem) %{ 5563 match(Set dst (LoadI mem)); 5564 ins_cost(MEMORY_REF_COST); 5565 5566 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5567 opcode(Assembler::ldf_op3); 5568 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5569 ins_pipe(floadF_mem); 5570 %} 5571 5572 // Load Pointer 5573 instruct loadP(iRegP dst, memory mem) %{ 5574 match(Set dst (LoadP mem)); 5575 ins_cost(MEMORY_REF_COST); 5576 size(4); 5577 5578 format %{ "LDX $mem,$dst\t! ptr" %} 5579 ins_encode %{ 5580 __ ldx($mem$$Address, $dst$$Register); 5581 %} 5582 ins_pipe(iload_mem); 5583 %} 5584 5585 // Load Compressed Pointer 5586 instruct loadN(iRegN dst, memory mem) %{ 5587 match(Set dst (LoadN mem)); 5588 ins_cost(MEMORY_REF_COST); 5589 size(4); 5590 5591 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5592 ins_encode %{ 5593 __ lduw($mem$$Address, $dst$$Register); 5594 %} 5595 ins_pipe(iload_mem); 5596 %} 5597 5598 // Load Klass Pointer 5599 instruct loadKlass(iRegP dst, memory mem) %{ 5600 match(Set dst (LoadKlass mem)); 5601 ins_cost(MEMORY_REF_COST); 5602 size(4); 5603 5604 format %{ "LDX $mem,$dst\t! klass ptr" %} 5605 ins_encode %{ 5606 __ ldx($mem$$Address, $dst$$Register); 5607 %} 5608 ins_pipe(iload_mem); 5609 %} 5610 5611 // Load narrow Klass Pointer 5612 instruct loadNKlass(iRegN dst, memory mem) %{ 5613 match(Set dst (LoadNKlass mem)); 5614 ins_cost(MEMORY_REF_COST); 5615 size(4); 5616 5617 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5618 ins_encode %{ 5619 __ lduw($mem$$Address, $dst$$Register); 5620 %} 5621 ins_pipe(iload_mem); 5622 %} 5623 5624 // Load Double 5625 instruct loadD(regD dst, memory mem) %{ 5626 match(Set dst (LoadD mem)); 5627 ins_cost(MEMORY_REF_COST); 5628 5629 format %{ "LDDF $mem,$dst" %} 5630 opcode(Assembler::lddf_op3); 5631 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5632 ins_pipe(floadD_mem); 5633 %} 5634 5635 // Load Double - UNaligned 5636 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5637 match(Set dst (LoadD_unaligned mem)); 5638 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5639 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5640 "\tLDF $mem+4,$dst.lo\t!" %} 5641 opcode(Assembler::ldf_op3); 5642 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5643 ins_pipe(iload_mem); 5644 %} 5645 5646 // Load Float 5647 instruct loadF(regF dst, memory mem) %{ 5648 match(Set dst (LoadF mem)); 5649 ins_cost(MEMORY_REF_COST); 5650 5651 format %{ "LDF $mem,$dst" %} 5652 opcode(Assembler::ldf_op3); 5653 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5654 ins_pipe(floadF_mem); 5655 %} 5656 5657 // Load Constant 5658 instruct loadConI( iRegI dst, immI src ) %{ 5659 match(Set dst src); 5660 ins_cost(DEFAULT_COST * 3/2); 5661 format %{ "SET $src,$dst" %} 5662 ins_encode( Set32(src, dst) ); 5663 ins_pipe(ialu_hi_lo_reg); 5664 %} 5665 5666 instruct loadConI13( iRegI dst, immI13 src ) %{ 5667 match(Set dst src); 5668 5669 size(4); 5670 format %{ "MOV $src,$dst" %} 5671 ins_encode( Set13( src, dst ) ); 5672 ins_pipe(ialu_imm); 5673 %} 5674 5675 instruct loadConP_set(iRegP dst, immP_set con) %{ 5676 match(Set dst con); 5677 ins_cost(DEFAULT_COST * 3/2); 5678 format %{ "SET $con,$dst\t! ptr" %} 5679 ins_encode %{ 5680 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 5681 intptr_t val = $con$$constant; 5682 if (constant_reloc == relocInfo::oop_type) { 5683 __ set_oop_constant((jobject) val, $dst$$Register); 5684 } else if (constant_reloc == relocInfo::metadata_type) { 5685 __ set_metadata_constant((Metadata*)val, $dst$$Register); 5686 } else { // non-oop pointers, e.g. card mark base, heap top 5687 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 5688 __ set(val, $dst$$Register); 5689 } 5690 %} 5691 ins_pipe(loadConP); 5692 %} 5693 5694 instruct loadConP_load(iRegP dst, immP_load con) %{ 5695 match(Set dst con); 5696 ins_cost(MEMORY_REF_COST); 5697 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 5698 ins_encode %{ 5699 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 5700 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 5701 %} 5702 ins_pipe(loadConP); 5703 %} 5704 5705 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 5706 match(Set dst con); 5707 ins_cost(DEFAULT_COST * 3/2); 5708 format %{ "SET $con,$dst\t! non-oop ptr" %} 5709 ins_encode %{ 5710 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) { 5711 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register); 5712 } else { 5713 __ set($con$$constant, $dst$$Register); 5714 } 5715 %} 5716 ins_pipe(loadConP); 5717 %} 5718 5719 instruct loadConP0(iRegP dst, immP0 src) %{ 5720 match(Set dst src); 5721 5722 size(4); 5723 format %{ "CLR $dst\t!ptr" %} 5724 ins_encode %{ 5725 __ clr($dst$$Register); 5726 %} 5727 ins_pipe(ialu_imm); 5728 %} 5729 5730 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 5731 match(Set dst src); 5732 ins_cost(DEFAULT_COST); 5733 format %{ "SET $src,$dst\t!ptr" %} 5734 ins_encode %{ 5735 AddressLiteral polling_page(os::get_polling_page()); 5736 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 5737 %} 5738 ins_pipe(loadConP_poll); 5739 %} 5740 5741 instruct loadConN0(iRegN dst, immN0 src) %{ 5742 match(Set dst src); 5743 5744 size(4); 5745 format %{ "CLR $dst\t! compressed NULL ptr" %} 5746 ins_encode %{ 5747 __ clr($dst$$Register); 5748 %} 5749 ins_pipe(ialu_imm); 5750 %} 5751 5752 instruct loadConN(iRegN dst, immN src) %{ 5753 match(Set dst src); 5754 ins_cost(DEFAULT_COST * 3/2); 5755 format %{ "SET $src,$dst\t! compressed ptr" %} 5756 ins_encode %{ 5757 Register dst = $dst$$Register; 5758 __ set_narrow_oop((jobject)$src$$constant, dst); 5759 %} 5760 ins_pipe(ialu_hi_lo_reg); 5761 %} 5762 5763 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 5764 match(Set dst src); 5765 ins_cost(DEFAULT_COST * 3/2); 5766 format %{ "SET $src,$dst\t! compressed klass ptr" %} 5767 ins_encode %{ 5768 Register dst = $dst$$Register; 5769 __ set_narrow_klass((Klass*)$src$$constant, dst); 5770 %} 5771 ins_pipe(ialu_hi_lo_reg); 5772 %} 5773 5774 // Materialize long value (predicated by immL_cheap). 5775 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 5776 match(Set dst con); 5777 effect(KILL tmp); 5778 ins_cost(DEFAULT_COST * 3); 5779 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 5780 ins_encode %{ 5781 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 5782 %} 5783 ins_pipe(loadConL); 5784 %} 5785 5786 // Load long value from constant table (predicated by immL_expensive). 5787 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 5788 match(Set dst con); 5789 ins_cost(MEMORY_REF_COST); 5790 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 5791 ins_encode %{ 5792 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 5793 __ ldx($constanttablebase, con_offset, $dst$$Register); 5794 %} 5795 ins_pipe(loadConL); 5796 %} 5797 5798 instruct loadConL0( iRegL dst, immL0 src ) %{ 5799 match(Set dst src); 5800 ins_cost(DEFAULT_COST); 5801 size(4); 5802 format %{ "CLR $dst\t! long" %} 5803 ins_encode( Set13( src, dst ) ); 5804 ins_pipe(ialu_imm); 5805 %} 5806 5807 instruct loadConL13( iRegL dst, immL13 src ) %{ 5808 match(Set dst src); 5809 ins_cost(DEFAULT_COST * 2); 5810 5811 size(4); 5812 format %{ "MOV $src,$dst\t! long" %} 5813 ins_encode( Set13( src, dst ) ); 5814 ins_pipe(ialu_imm); 5815 %} 5816 5817 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 5818 match(Set dst con); 5819 effect(KILL tmp); 5820 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 5821 ins_encode %{ 5822 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 5823 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 5824 %} 5825 ins_pipe(loadConFD); 5826 %} 5827 5828 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 5829 match(Set dst con); 5830 effect(KILL tmp); 5831 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 5832 ins_encode %{ 5833 // XXX This is a quick fix for 6833573. 5834 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 5835 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 5836 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 5837 %} 5838 ins_pipe(loadConFD); 5839 %} 5840 5841 // Prefetch instructions for allocation. 5842 // Must be safe to execute with invalid address (cannot fault). 5843 5844 instruct prefetchAlloc( memory mem ) %{ 5845 predicate(AllocatePrefetchInstr == 0); 5846 match( PrefetchAllocation mem ); 5847 ins_cost(MEMORY_REF_COST); 5848 5849 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} 5850 opcode(Assembler::prefetch_op3); 5851 ins_encode( form3_mem_prefetch_write( mem ) ); 5852 ins_pipe(iload_mem); 5853 %} 5854 5855 // Use BIS instruction to prefetch for allocation. 5856 // Could fault, need space at the end of TLAB. 5857 instruct prefetchAlloc_bis( iRegP dst ) %{ 5858 predicate(AllocatePrefetchInstr == 1); 5859 match( PrefetchAllocation dst ); 5860 ins_cost(MEMORY_REF_COST); 5861 size(4); 5862 5863 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} 5864 ins_encode %{ 5865 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 5866 %} 5867 ins_pipe(istore_mem_reg); 5868 %} 5869 5870 // Next code is used for finding next cache line address to prefetch. 5871 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ 5872 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 5873 ins_cost(DEFAULT_COST); 5874 size(4); 5875 5876 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 5877 ins_encode %{ 5878 __ and3($src$$Register, $mask$$constant, $dst$$Register); 5879 %} 5880 ins_pipe(ialu_reg_imm); 5881 %} 5882 5883 //----------Store Instructions------------------------------------------------- 5884 // Store Byte 5885 instruct storeB(memory mem, iRegI src) %{ 5886 match(Set mem (StoreB mem src)); 5887 ins_cost(MEMORY_REF_COST); 5888 5889 format %{ "STB $src,$mem\t! byte" %} 5890 opcode(Assembler::stb_op3); 5891 ins_encode(simple_form3_mem_reg( mem, src ) ); 5892 ins_pipe(istore_mem_reg); 5893 %} 5894 5895 instruct storeB0(memory mem, immI0 src) %{ 5896 match(Set mem (StoreB mem src)); 5897 ins_cost(MEMORY_REF_COST); 5898 5899 format %{ "STB $src,$mem\t! byte" %} 5900 opcode(Assembler::stb_op3); 5901 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5902 ins_pipe(istore_mem_zero); 5903 %} 5904 5905 instruct storeCM0(memory mem, immI0 src) %{ 5906 match(Set mem (StoreCM mem src)); 5907 ins_cost(MEMORY_REF_COST); 5908 5909 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 5910 opcode(Assembler::stb_op3); 5911 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5912 ins_pipe(istore_mem_zero); 5913 %} 5914 5915 // Store Char/Short 5916 instruct storeC(memory mem, iRegI src) %{ 5917 match(Set mem (StoreC mem src)); 5918 ins_cost(MEMORY_REF_COST); 5919 5920 format %{ "STH $src,$mem\t! short" %} 5921 opcode(Assembler::sth_op3); 5922 ins_encode(simple_form3_mem_reg( mem, src ) ); 5923 ins_pipe(istore_mem_reg); 5924 %} 5925 5926 instruct storeC0(memory mem, immI0 src) %{ 5927 match(Set mem (StoreC mem src)); 5928 ins_cost(MEMORY_REF_COST); 5929 5930 format %{ "STH $src,$mem\t! short" %} 5931 opcode(Assembler::sth_op3); 5932 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5933 ins_pipe(istore_mem_zero); 5934 %} 5935 5936 // Store Integer 5937 instruct storeI(memory mem, iRegI src) %{ 5938 match(Set mem (StoreI mem src)); 5939 ins_cost(MEMORY_REF_COST); 5940 5941 format %{ "STW $src,$mem" %} 5942 opcode(Assembler::stw_op3); 5943 ins_encode(simple_form3_mem_reg( mem, src ) ); 5944 ins_pipe(istore_mem_reg); 5945 %} 5946 5947 // Store Long 5948 instruct storeL(memory mem, iRegL src) %{ 5949 match(Set mem (StoreL mem src)); 5950 ins_cost(MEMORY_REF_COST); 5951 format %{ "STX $src,$mem\t! long" %} 5952 opcode(Assembler::stx_op3); 5953 ins_encode(simple_form3_mem_reg( mem, src ) ); 5954 ins_pipe(istore_mem_reg); 5955 %} 5956 5957 instruct storeI0(memory mem, immI0 src) %{ 5958 match(Set mem (StoreI mem src)); 5959 ins_cost(MEMORY_REF_COST); 5960 5961 format %{ "STW $src,$mem" %} 5962 opcode(Assembler::stw_op3); 5963 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5964 ins_pipe(istore_mem_zero); 5965 %} 5966 5967 instruct storeL0(memory mem, immL0 src) %{ 5968 match(Set mem (StoreL mem src)); 5969 ins_cost(MEMORY_REF_COST); 5970 5971 format %{ "STX $src,$mem" %} 5972 opcode(Assembler::stx_op3); 5973 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5974 ins_pipe(istore_mem_zero); 5975 %} 5976 5977 // Store Integer from float register (used after fstoi) 5978 instruct storeI_Freg(memory mem, regF src) %{ 5979 match(Set mem (StoreI mem src)); 5980 ins_cost(MEMORY_REF_COST); 5981 5982 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 5983 opcode(Assembler::stf_op3); 5984 ins_encode(simple_form3_mem_reg( mem, src ) ); 5985 ins_pipe(fstoreF_mem_reg); 5986 %} 5987 5988 // Store Pointer 5989 instruct storeP(memory dst, sp_ptr_RegP src) %{ 5990 match(Set dst (StoreP dst src)); 5991 ins_cost(MEMORY_REF_COST); 5992 5993 format %{ "STX $src,$dst\t! ptr" %} 5994 opcode(Assembler::stx_op3, 0, REGP_OP); 5995 ins_encode( form3_mem_reg( dst, src ) ); 5996 ins_pipe(istore_mem_spORreg); 5997 %} 5998 5999 instruct storeP0(memory dst, immP0 src) %{ 6000 match(Set dst (StoreP dst src)); 6001 ins_cost(MEMORY_REF_COST); 6002 6003 format %{ "STX $src,$dst\t! ptr" %} 6004 opcode(Assembler::stx_op3, 0, REGP_OP); 6005 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6006 ins_pipe(istore_mem_zero); 6007 %} 6008 6009 // Store Compressed Pointer 6010 instruct storeN(memory dst, iRegN src) %{ 6011 match(Set dst (StoreN dst src)); 6012 ins_cost(MEMORY_REF_COST); 6013 size(4); 6014 6015 format %{ "STW $src,$dst\t! compressed ptr" %} 6016 ins_encode %{ 6017 Register base = as_Register($dst$$base); 6018 Register index = as_Register($dst$$index); 6019 Register src = $src$$Register; 6020 if (index != G0) { 6021 __ stw(src, base, index); 6022 } else { 6023 __ stw(src, base, $dst$$disp); 6024 } 6025 %} 6026 ins_pipe(istore_mem_spORreg); 6027 %} 6028 6029 instruct storeNKlass(memory dst, iRegN src) %{ 6030 match(Set dst (StoreNKlass dst src)); 6031 ins_cost(MEMORY_REF_COST); 6032 size(4); 6033 6034 format %{ "STW $src,$dst\t! compressed klass ptr" %} 6035 ins_encode %{ 6036 Register base = as_Register($dst$$base); 6037 Register index = as_Register($dst$$index); 6038 Register src = $src$$Register; 6039 if (index != G0) { 6040 __ stw(src, base, index); 6041 } else { 6042 __ stw(src, base, $dst$$disp); 6043 } 6044 %} 6045 ins_pipe(istore_mem_spORreg); 6046 %} 6047 6048 instruct storeN0(memory dst, immN0 src) %{ 6049 match(Set dst (StoreN dst src)); 6050 ins_cost(MEMORY_REF_COST); 6051 size(4); 6052 6053 format %{ "STW $src,$dst\t! compressed ptr" %} 6054 ins_encode %{ 6055 Register base = as_Register($dst$$base); 6056 Register index = as_Register($dst$$index); 6057 if (index != G0) { 6058 __ stw(0, base, index); 6059 } else { 6060 __ stw(0, base, $dst$$disp); 6061 } 6062 %} 6063 ins_pipe(istore_mem_zero); 6064 %} 6065 6066 // Store Double 6067 instruct storeD( memory mem, regD src) %{ 6068 match(Set mem (StoreD mem src)); 6069 ins_cost(MEMORY_REF_COST); 6070 6071 format %{ "STDF $src,$mem" %} 6072 opcode(Assembler::stdf_op3); 6073 ins_encode(simple_form3_mem_reg( mem, src ) ); 6074 ins_pipe(fstoreD_mem_reg); 6075 %} 6076 6077 instruct storeD0( memory mem, immD0 src) %{ 6078 match(Set mem (StoreD mem src)); 6079 ins_cost(MEMORY_REF_COST); 6080 6081 format %{ "STX $src,$mem" %} 6082 opcode(Assembler::stx_op3); 6083 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6084 ins_pipe(fstoreD_mem_zero); 6085 %} 6086 6087 // Store Float 6088 instruct storeF( memory mem, regF src) %{ 6089 match(Set mem (StoreF mem src)); 6090 ins_cost(MEMORY_REF_COST); 6091 6092 format %{ "STF $src,$mem" %} 6093 opcode(Assembler::stf_op3); 6094 ins_encode(simple_form3_mem_reg( mem, src ) ); 6095 ins_pipe(fstoreF_mem_reg); 6096 %} 6097 6098 instruct storeF0( memory mem, immF0 src) %{ 6099 match(Set mem (StoreF mem src)); 6100 ins_cost(MEMORY_REF_COST); 6101 6102 format %{ "STW $src,$mem\t! storeF0" %} 6103 opcode(Assembler::stw_op3); 6104 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6105 ins_pipe(fstoreF_mem_zero); 6106 %} 6107 6108 // Convert oop pointer into compressed form 6109 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6110 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6111 match(Set dst (EncodeP src)); 6112 format %{ "encode_heap_oop $src, $dst" %} 6113 ins_encode %{ 6114 __ encode_heap_oop($src$$Register, $dst$$Register); 6115 %} 6116 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); 6117 ins_pipe(ialu_reg); 6118 %} 6119 6120 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6121 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6122 match(Set dst (EncodeP src)); 6123 format %{ "encode_heap_oop_not_null $src, $dst" %} 6124 ins_encode %{ 6125 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6126 %} 6127 ins_pipe(ialu_reg); 6128 %} 6129 6130 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6131 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6132 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6133 match(Set dst (DecodeN src)); 6134 format %{ "decode_heap_oop $src, $dst" %} 6135 ins_encode %{ 6136 __ decode_heap_oop($src$$Register, $dst$$Register); 6137 %} 6138 ins_pipe(ialu_reg); 6139 %} 6140 6141 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6142 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6143 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6144 match(Set dst (DecodeN src)); 6145 format %{ "decode_heap_oop_not_null $src, $dst" %} 6146 ins_encode %{ 6147 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6148 %} 6149 ins_pipe(ialu_reg); 6150 %} 6151 6152 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ 6153 match(Set dst (EncodePKlass src)); 6154 format %{ "encode_klass_not_null $src, $dst" %} 6155 ins_encode %{ 6156 __ encode_klass_not_null($src$$Register, $dst$$Register); 6157 %} 6158 ins_pipe(ialu_reg); 6159 %} 6160 6161 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ 6162 match(Set dst (DecodeNKlass src)); 6163 format %{ "decode_klass_not_null $src, $dst" %} 6164 ins_encode %{ 6165 __ decode_klass_not_null($src$$Register, $dst$$Register); 6166 %} 6167 ins_pipe(ialu_reg); 6168 %} 6169 6170 //----------MemBar Instructions----------------------------------------------- 6171 // Memory barrier flavors 6172 6173 instruct membar_acquire() %{ 6174 match(MemBarAcquire); 6175 match(LoadFence); 6176 ins_cost(4*MEMORY_REF_COST); 6177 6178 size(0); 6179 format %{ "MEMBAR-acquire" %} 6180 ins_encode( enc_membar_acquire ); 6181 ins_pipe(long_memory_op); 6182 %} 6183 6184 instruct membar_acquire_lock() %{ 6185 match(MemBarAcquireLock); 6186 ins_cost(0); 6187 6188 size(0); 6189 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6190 ins_encode( ); 6191 ins_pipe(empty); 6192 %} 6193 6194 instruct membar_release() %{ 6195 match(MemBarRelease); 6196 match(StoreFence); 6197 ins_cost(4*MEMORY_REF_COST); 6198 6199 size(0); 6200 format %{ "MEMBAR-release" %} 6201 ins_encode( enc_membar_release ); 6202 ins_pipe(long_memory_op); 6203 %} 6204 6205 instruct membar_release_lock() %{ 6206 match(MemBarReleaseLock); 6207 ins_cost(0); 6208 6209 size(0); 6210 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6211 ins_encode( ); 6212 ins_pipe(empty); 6213 %} 6214 6215 instruct membar_volatile() %{ 6216 match(MemBarVolatile); 6217 ins_cost(4*MEMORY_REF_COST); 6218 6219 size(4); 6220 format %{ "MEMBAR-volatile" %} 6221 ins_encode( enc_membar_volatile ); 6222 ins_pipe(long_memory_op); 6223 %} 6224 6225 instruct unnecessary_membar_volatile() %{ 6226 match(MemBarVolatile); 6227 predicate(Matcher::post_store_load_barrier(n)); 6228 ins_cost(0); 6229 6230 size(0); 6231 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6232 ins_encode( ); 6233 ins_pipe(empty); 6234 %} 6235 6236 instruct membar_storestore() %{ 6237 match(MemBarStoreStore); 6238 ins_cost(0); 6239 6240 size(0); 6241 format %{ "!MEMBAR-storestore (empty encoding)" %} 6242 ins_encode( ); 6243 ins_pipe(empty); 6244 %} 6245 6246 //----------Register Move Instructions----------------------------------------- 6247 instruct roundDouble_nop(regD dst) %{ 6248 match(Set dst (RoundDouble dst)); 6249 ins_cost(0); 6250 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6251 ins_encode( ); 6252 ins_pipe(empty); 6253 %} 6254 6255 6256 instruct roundFloat_nop(regF dst) %{ 6257 match(Set dst (RoundFloat dst)); 6258 ins_cost(0); 6259 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6260 ins_encode( ); 6261 ins_pipe(empty); 6262 %} 6263 6264 6265 // Cast Index to Pointer for unsafe natives 6266 instruct castX2P(iRegX src, iRegP dst) %{ 6267 match(Set dst (CastX2P src)); 6268 6269 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6270 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6271 ins_pipe(ialu_reg); 6272 %} 6273 6274 // Cast Pointer to Index for unsafe natives 6275 instruct castP2X(iRegP src, iRegX dst) %{ 6276 match(Set dst (CastP2X src)); 6277 6278 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6279 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6280 ins_pipe(ialu_reg); 6281 %} 6282 6283 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6284 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6285 match(Set stkSlot src); // chain rule 6286 ins_cost(MEMORY_REF_COST); 6287 format %{ "STDF $src,$stkSlot\t!stk" %} 6288 opcode(Assembler::stdf_op3); 6289 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6290 ins_pipe(fstoreD_stk_reg); 6291 %} 6292 6293 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6294 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6295 match(Set dst stkSlot); // chain rule 6296 ins_cost(MEMORY_REF_COST); 6297 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6298 opcode(Assembler::lddf_op3); 6299 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6300 ins_pipe(floadD_stk); 6301 %} 6302 6303 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6304 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6305 match(Set stkSlot src); // chain rule 6306 ins_cost(MEMORY_REF_COST); 6307 format %{ "STF $src,$stkSlot\t!stk" %} 6308 opcode(Assembler::stf_op3); 6309 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6310 ins_pipe(fstoreF_stk_reg); 6311 %} 6312 6313 //----------Conditional Move--------------------------------------------------- 6314 // Conditional move 6315 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6316 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6317 ins_cost(150); 6318 format %{ "MOV$cmp $pcc,$src,$dst" %} 6319 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6320 ins_pipe(ialu_reg); 6321 %} 6322 6323 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6324 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6325 ins_cost(140); 6326 format %{ "MOV$cmp $pcc,$src,$dst" %} 6327 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6328 ins_pipe(ialu_imm); 6329 %} 6330 6331 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6332 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6333 ins_cost(150); 6334 size(4); 6335 format %{ "MOV$cmp $icc,$src,$dst" %} 6336 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6337 ins_pipe(ialu_reg); 6338 %} 6339 6340 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6341 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6342 ins_cost(140); 6343 size(4); 6344 format %{ "MOV$cmp $icc,$src,$dst" %} 6345 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6346 ins_pipe(ialu_imm); 6347 %} 6348 6349 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6350 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6351 ins_cost(150); 6352 size(4); 6353 format %{ "MOV$cmp $icc,$src,$dst" %} 6354 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6355 ins_pipe(ialu_reg); 6356 %} 6357 6358 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6359 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6360 ins_cost(140); 6361 size(4); 6362 format %{ "MOV$cmp $icc,$src,$dst" %} 6363 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6364 ins_pipe(ialu_imm); 6365 %} 6366 6367 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6368 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6369 ins_cost(150); 6370 size(4); 6371 format %{ "MOV$cmp $fcc,$src,$dst" %} 6372 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6373 ins_pipe(ialu_reg); 6374 %} 6375 6376 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6377 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6378 ins_cost(140); 6379 size(4); 6380 format %{ "MOV$cmp $fcc,$src,$dst" %} 6381 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6382 ins_pipe(ialu_imm); 6383 %} 6384 6385 // Conditional move for RegN. Only cmov(reg,reg). 6386 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6387 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6388 ins_cost(150); 6389 format %{ "MOV$cmp $pcc,$src,$dst" %} 6390 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6391 ins_pipe(ialu_reg); 6392 %} 6393 6394 // This instruction also works with CmpN so we don't need cmovNN_reg. 6395 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6396 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6397 ins_cost(150); 6398 size(4); 6399 format %{ "MOV$cmp $icc,$src,$dst" %} 6400 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6401 ins_pipe(ialu_reg); 6402 %} 6403 6404 // This instruction also works with CmpN so we don't need cmovNN_reg. 6405 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6406 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6407 ins_cost(150); 6408 size(4); 6409 format %{ "MOV$cmp $icc,$src,$dst" %} 6410 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6411 ins_pipe(ialu_reg); 6412 %} 6413 6414 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6415 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6416 ins_cost(150); 6417 size(4); 6418 format %{ "MOV$cmp $fcc,$src,$dst" %} 6419 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6420 ins_pipe(ialu_reg); 6421 %} 6422 6423 // Conditional move 6424 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6425 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6426 ins_cost(150); 6427 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6428 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6429 ins_pipe(ialu_reg); 6430 %} 6431 6432 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6433 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6434 ins_cost(140); 6435 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6436 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6437 ins_pipe(ialu_imm); 6438 %} 6439 6440 // This instruction also works with CmpN so we don't need cmovPN_reg. 6441 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6442 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6443 ins_cost(150); 6444 6445 size(4); 6446 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6447 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6448 ins_pipe(ialu_reg); 6449 %} 6450 6451 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6452 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6453 ins_cost(150); 6454 6455 size(4); 6456 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6457 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6458 ins_pipe(ialu_reg); 6459 %} 6460 6461 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6462 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6463 ins_cost(140); 6464 6465 size(4); 6466 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6467 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6468 ins_pipe(ialu_imm); 6469 %} 6470 6471 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6472 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6473 ins_cost(140); 6474 6475 size(4); 6476 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6477 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6478 ins_pipe(ialu_imm); 6479 %} 6480 6481 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6482 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6483 ins_cost(150); 6484 size(4); 6485 format %{ "MOV$cmp $fcc,$src,$dst" %} 6486 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6487 ins_pipe(ialu_imm); 6488 %} 6489 6490 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6491 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6492 ins_cost(140); 6493 size(4); 6494 format %{ "MOV$cmp $fcc,$src,$dst" %} 6495 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6496 ins_pipe(ialu_imm); 6497 %} 6498 6499 // Conditional move 6500 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6501 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6502 ins_cost(150); 6503 opcode(0x101); 6504 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6505 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6506 ins_pipe(int_conditional_float_move); 6507 %} 6508 6509 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6510 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6511 ins_cost(150); 6512 6513 size(4); 6514 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6515 opcode(0x101); 6516 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6517 ins_pipe(int_conditional_float_move); 6518 %} 6519 6520 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6521 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6522 ins_cost(150); 6523 6524 size(4); 6525 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6526 opcode(0x101); 6527 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6528 ins_pipe(int_conditional_float_move); 6529 %} 6530 6531 // Conditional move, 6532 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6533 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6534 ins_cost(150); 6535 size(4); 6536 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6537 opcode(0x1); 6538 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6539 ins_pipe(int_conditional_double_move); 6540 %} 6541 6542 // Conditional move 6543 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6544 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6545 ins_cost(150); 6546 size(4); 6547 opcode(0x102); 6548 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6549 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6550 ins_pipe(int_conditional_double_move); 6551 %} 6552 6553 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6554 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6555 ins_cost(150); 6556 6557 size(4); 6558 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6559 opcode(0x102); 6560 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6561 ins_pipe(int_conditional_double_move); 6562 %} 6563 6564 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 6565 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6566 ins_cost(150); 6567 6568 size(4); 6569 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6570 opcode(0x102); 6571 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6572 ins_pipe(int_conditional_double_move); 6573 %} 6574 6575 // Conditional move, 6576 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6577 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6578 ins_cost(150); 6579 size(4); 6580 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6581 opcode(0x2); 6582 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6583 ins_pipe(int_conditional_double_move); 6584 %} 6585 6586 // Conditional move 6587 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6588 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6589 ins_cost(150); 6590 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6591 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6592 ins_pipe(ialu_reg); 6593 %} 6594 6595 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6596 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6597 ins_cost(140); 6598 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6599 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6600 ins_pipe(ialu_imm); 6601 %} 6602 6603 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6604 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6605 ins_cost(150); 6606 6607 size(4); 6608 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6609 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6610 ins_pipe(ialu_reg); 6611 %} 6612 6613 6614 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 6615 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6616 ins_cost(150); 6617 6618 size(4); 6619 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6620 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6621 ins_pipe(ialu_reg); 6622 %} 6623 6624 6625 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6626 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6627 ins_cost(150); 6628 6629 size(4); 6630 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6631 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6632 ins_pipe(ialu_reg); 6633 %} 6634 6635 6636 6637 //----------OS and Locking Instructions---------------------------------------- 6638 6639 // This name is KNOWN by the ADLC and cannot be changed. 6640 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6641 // for this guy. 6642 instruct tlsLoadP(g2RegP dst) %{ 6643 match(Set dst (ThreadLocal)); 6644 6645 size(0); 6646 ins_cost(0); 6647 format %{ "# TLS is in G2" %} 6648 ins_encode( /*empty encoding*/ ); 6649 ins_pipe(ialu_none); 6650 %} 6651 6652 instruct checkCastPP( iRegP dst ) %{ 6653 match(Set dst (CheckCastPP dst)); 6654 6655 size(0); 6656 format %{ "# checkcastPP of $dst" %} 6657 ins_encode( /*empty encoding*/ ); 6658 ins_pipe(empty); 6659 %} 6660 6661 6662 instruct castPP( iRegP dst ) %{ 6663 match(Set dst (CastPP dst)); 6664 format %{ "# castPP of $dst" %} 6665 ins_encode( /*empty encoding*/ ); 6666 ins_pipe(empty); 6667 %} 6668 6669 instruct castII( iRegI dst ) %{ 6670 match(Set dst (CastII dst)); 6671 format %{ "# castII of $dst" %} 6672 ins_encode( /*empty encoding*/ ); 6673 ins_cost(0); 6674 ins_pipe(empty); 6675 %} 6676 6677 //----------Arithmetic Instructions-------------------------------------------- 6678 // Addition Instructions 6679 // Register Addition 6680 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6681 match(Set dst (AddI src1 src2)); 6682 6683 size(4); 6684 format %{ "ADD $src1,$src2,$dst" %} 6685 ins_encode %{ 6686 __ add($src1$$Register, $src2$$Register, $dst$$Register); 6687 %} 6688 ins_pipe(ialu_reg_reg); 6689 %} 6690 6691 // Immediate Addition 6692 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6693 match(Set dst (AddI src1 src2)); 6694 6695 size(4); 6696 format %{ "ADD $src1,$src2,$dst" %} 6697 opcode(Assembler::add_op3, Assembler::arith_op); 6698 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6699 ins_pipe(ialu_reg_imm); 6700 %} 6701 6702 // Pointer Register Addition 6703 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 6704 match(Set dst (AddP src1 src2)); 6705 6706 size(4); 6707 format %{ "ADD $src1,$src2,$dst" %} 6708 opcode(Assembler::add_op3, Assembler::arith_op); 6709 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6710 ins_pipe(ialu_reg_reg); 6711 %} 6712 6713 // Pointer Immediate Addition 6714 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 6715 match(Set dst (AddP src1 src2)); 6716 6717 size(4); 6718 format %{ "ADD $src1,$src2,$dst" %} 6719 opcode(Assembler::add_op3, Assembler::arith_op); 6720 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6721 ins_pipe(ialu_reg_imm); 6722 %} 6723 6724 // Long Addition 6725 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6726 match(Set dst (AddL src1 src2)); 6727 6728 size(4); 6729 format %{ "ADD $src1,$src2,$dst\t! long" %} 6730 opcode(Assembler::add_op3, Assembler::arith_op); 6731 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6732 ins_pipe(ialu_reg_reg); 6733 %} 6734 6735 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6736 match(Set dst (AddL src1 con)); 6737 6738 size(4); 6739 format %{ "ADD $src1,$con,$dst" %} 6740 opcode(Assembler::add_op3, Assembler::arith_op); 6741 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6742 ins_pipe(ialu_reg_imm); 6743 %} 6744 6745 //----------Conditional_store-------------------------------------------------- 6746 // Conditional-store of the updated heap-top. 6747 // Used during allocation of the shared heap. 6748 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 6749 6750 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 6751 instruct loadPLocked(iRegP dst, memory mem) %{ 6752 match(Set dst (LoadPLocked mem)); 6753 ins_cost(MEMORY_REF_COST); 6754 6755 format %{ "LDX $mem,$dst\t! ptr" %} 6756 opcode(Assembler::ldx_op3, 0, REGP_OP); 6757 ins_encode( form3_mem_reg( mem, dst ) ); 6758 ins_pipe(iload_mem); 6759 %} 6760 6761 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 6762 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 6763 effect( KILL newval ); 6764 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 6765 "CMP R_G3,$oldval\t\t! See if we made progress" %} 6766 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 6767 ins_pipe( long_memory_op ); 6768 %} 6769 6770 // Conditional-store of an int value. 6771 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 6772 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 6773 effect( KILL newval ); 6774 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6775 "CMP $oldval,$newval\t\t! See if we made progress" %} 6776 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6777 ins_pipe( long_memory_op ); 6778 %} 6779 6780 // Conditional-store of a long value. 6781 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 6782 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 6783 effect( KILL newval ); 6784 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6785 "CMP $oldval,$newval\t\t! See if we made progress" %} 6786 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6787 ins_pipe( long_memory_op ); 6788 %} 6789 6790 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 6791 6792 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6793 predicate(VM_Version::supports_cx8()); 6794 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 6795 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval))); 6796 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6797 format %{ 6798 "MOV $newval,O7\n\t" 6799 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6800 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6801 "MOV 1,$res\n\t" 6802 "MOVne xcc,R_G0,$res" 6803 %} 6804 ins_encode( enc_casx(mem_ptr, oldval, newval), 6805 enc_lflags_ne_to_boolean(res) ); 6806 ins_pipe( long_memory_op ); 6807 %} 6808 6809 6810 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6811 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 6812 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval))); 6813 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6814 format %{ 6815 "MOV $newval,O7\n\t" 6816 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6817 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6818 "MOV 1,$res\n\t" 6819 "MOVne icc,R_G0,$res" 6820 %} 6821 ins_encode( enc_casi(mem_ptr, oldval, newval), 6822 enc_iflags_ne_to_boolean(res) ); 6823 ins_pipe( long_memory_op ); 6824 %} 6825 6826 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6827 predicate(VM_Version::supports_cx8()); 6828 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 6829 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); 6830 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6831 format %{ 6832 "MOV $newval,O7\n\t" 6833 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6834 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6835 "MOV 1,$res\n\t" 6836 "MOVne xcc,R_G0,$res" 6837 %} 6838 ins_encode( enc_casx(mem_ptr, oldval, newval), 6839 enc_lflags_ne_to_boolean(res) ); 6840 ins_pipe( long_memory_op ); 6841 %} 6842 6843 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6844 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 6845 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval))); 6846 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6847 format %{ 6848 "MOV $newval,O7\n\t" 6849 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6850 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6851 "MOV 1,$res\n\t" 6852 "MOVne icc,R_G0,$res" 6853 %} 6854 ins_encode( enc_casi(mem_ptr, oldval, newval), 6855 enc_iflags_ne_to_boolean(res) ); 6856 ins_pipe( long_memory_op ); 6857 %} 6858 6859 instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval) 6860 %{ 6861 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval))); 6862 effect( USE mem_ptr ); 6863 6864 format %{ 6865 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6866 %} 6867 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 6868 ins_pipe( long_memory_op ); 6869 %} 6870 6871 instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval) 6872 %{ 6873 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval))); 6874 effect( USE mem_ptr ); 6875 6876 format %{ 6877 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6878 %} 6879 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 6880 ins_pipe( long_memory_op ); 6881 %} 6882 6883 instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval) 6884 %{ 6885 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval))); 6886 effect( USE mem_ptr ); 6887 6888 format %{ 6889 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6890 %} 6891 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 6892 ins_pipe( long_memory_op ); 6893 %} 6894 6895 instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval) 6896 %{ 6897 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval))); 6898 effect( USE mem_ptr ); 6899 6900 format %{ 6901 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6902 %} 6903 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 6904 ins_pipe( long_memory_op ); 6905 %} 6906 6907 instruct xchgI( memory mem, iRegI newval) %{ 6908 match(Set newval (GetAndSetI mem newval)); 6909 format %{ "SWAP [$mem],$newval" %} 6910 size(4); 6911 ins_encode %{ 6912 __ swap($mem$$Address, $newval$$Register); 6913 %} 6914 ins_pipe( long_memory_op ); 6915 %} 6916 6917 6918 instruct xchgN( memory mem, iRegN newval) %{ 6919 match(Set newval (GetAndSetN mem newval)); 6920 format %{ "SWAP [$mem],$newval" %} 6921 size(4); 6922 ins_encode %{ 6923 __ swap($mem$$Address, $newval$$Register); 6924 %} 6925 ins_pipe( long_memory_op ); 6926 %} 6927 6928 //--------------------- 6929 // Subtraction Instructions 6930 // Register Subtraction 6931 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6932 match(Set dst (SubI src1 src2)); 6933 6934 size(4); 6935 format %{ "SUB $src1,$src2,$dst" %} 6936 opcode(Assembler::sub_op3, Assembler::arith_op); 6937 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6938 ins_pipe(ialu_reg_reg); 6939 %} 6940 6941 // Immediate Subtraction 6942 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6943 match(Set dst (SubI src1 src2)); 6944 6945 size(4); 6946 format %{ "SUB $src1,$src2,$dst" %} 6947 opcode(Assembler::sub_op3, Assembler::arith_op); 6948 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6949 ins_pipe(ialu_reg_imm); 6950 %} 6951 6952 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 6953 match(Set dst (SubI zero src2)); 6954 6955 size(4); 6956 format %{ "NEG $src2,$dst" %} 6957 opcode(Assembler::sub_op3, Assembler::arith_op); 6958 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 6959 ins_pipe(ialu_zero_reg); 6960 %} 6961 6962 // Long subtraction 6963 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6964 match(Set dst (SubL src1 src2)); 6965 6966 size(4); 6967 format %{ "SUB $src1,$src2,$dst\t! long" %} 6968 opcode(Assembler::sub_op3, Assembler::arith_op); 6969 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6970 ins_pipe(ialu_reg_reg); 6971 %} 6972 6973 // Immediate Subtraction 6974 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6975 match(Set dst (SubL src1 con)); 6976 6977 size(4); 6978 format %{ "SUB $src1,$con,$dst\t! long" %} 6979 opcode(Assembler::sub_op3, Assembler::arith_op); 6980 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6981 ins_pipe(ialu_reg_imm); 6982 %} 6983 6984 // Long negation 6985 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 6986 match(Set dst (SubL zero src2)); 6987 6988 size(4); 6989 format %{ "NEG $src2,$dst\t! long" %} 6990 opcode(Assembler::sub_op3, Assembler::arith_op); 6991 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 6992 ins_pipe(ialu_zero_reg); 6993 %} 6994 6995 // Multiplication Instructions 6996 // Integer Multiplication 6997 // Register Multiplication 6998 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6999 match(Set dst (MulI src1 src2)); 7000 7001 size(4); 7002 format %{ "MULX $src1,$src2,$dst" %} 7003 opcode(Assembler::mulx_op3, Assembler::arith_op); 7004 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7005 ins_pipe(imul_reg_reg); 7006 %} 7007 7008 // Immediate Multiplication 7009 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7010 match(Set dst (MulI src1 src2)); 7011 7012 size(4); 7013 format %{ "MULX $src1,$src2,$dst" %} 7014 opcode(Assembler::mulx_op3, Assembler::arith_op); 7015 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7016 ins_pipe(imul_reg_imm); 7017 %} 7018 7019 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7020 match(Set dst (MulL src1 src2)); 7021 ins_cost(DEFAULT_COST * 5); 7022 size(4); 7023 format %{ "MULX $src1,$src2,$dst\t! long" %} 7024 opcode(Assembler::mulx_op3, Assembler::arith_op); 7025 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7026 ins_pipe(mulL_reg_reg); 7027 %} 7028 7029 // Immediate Multiplication 7030 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7031 match(Set dst (MulL src1 src2)); 7032 ins_cost(DEFAULT_COST * 5); 7033 size(4); 7034 format %{ "MULX $src1,$src2,$dst" %} 7035 opcode(Assembler::mulx_op3, Assembler::arith_op); 7036 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7037 ins_pipe(mulL_reg_imm); 7038 %} 7039 7040 // Integer Division 7041 // Register Division 7042 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7043 match(Set dst (DivI src1 src2)); 7044 ins_cost((2+71)*DEFAULT_COST); 7045 7046 format %{ "SRA $src2,0,$src2\n\t" 7047 "SRA $src1,0,$src1\n\t" 7048 "SDIVX $src1,$src2,$dst" %} 7049 ins_encode( idiv_reg( src1, src2, dst ) ); 7050 ins_pipe(sdiv_reg_reg); 7051 %} 7052 7053 // Immediate Division 7054 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7055 match(Set dst (DivI src1 src2)); 7056 ins_cost((2+71)*DEFAULT_COST); 7057 7058 format %{ "SRA $src1,0,$src1\n\t" 7059 "SDIVX $src1,$src2,$dst" %} 7060 ins_encode( idiv_imm( src1, src2, dst ) ); 7061 ins_pipe(sdiv_reg_imm); 7062 %} 7063 7064 //----------Div-By-10-Expansion------------------------------------------------ 7065 // Extract hi bits of a 32x32->64 bit multiply. 7066 // Expand rule only, not matched 7067 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7068 effect( DEF dst, USE src1, USE src2 ); 7069 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7070 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7071 ins_encode( enc_mul_hi(dst,src1,src2)); 7072 ins_pipe(sdiv_reg_reg); 7073 %} 7074 7075 // Magic constant, reciprocal of 10 7076 instruct loadConI_x66666667(iRegIsafe dst) %{ 7077 effect( DEF dst ); 7078 7079 size(8); 7080 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7081 ins_encode( Set32(0x66666667, dst) ); 7082 ins_pipe(ialu_hi_lo_reg); 7083 %} 7084 7085 // Register Shift Right Arithmetic Long by 32-63 7086 instruct sra_31( iRegI dst, iRegI src ) %{ 7087 effect( DEF dst, USE src ); 7088 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7089 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7090 ins_pipe(ialu_reg_reg); 7091 %} 7092 7093 // Arithmetic Shift Right by 8-bit immediate 7094 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7095 effect( DEF dst, USE src ); 7096 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7097 opcode(Assembler::sra_op3, Assembler::arith_op); 7098 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7099 ins_pipe(ialu_reg_imm); 7100 %} 7101 7102 // Integer DIV with 10 7103 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7104 match(Set dst (DivI src div)); 7105 ins_cost((6+6)*DEFAULT_COST); 7106 expand %{ 7107 iRegIsafe tmp1; // Killed temps; 7108 iRegIsafe tmp2; // Killed temps; 7109 iRegI tmp3; // Killed temps; 7110 iRegI tmp4; // Killed temps; 7111 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7112 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7113 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7114 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7115 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7116 %} 7117 %} 7118 7119 // Register Long Division 7120 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7121 match(Set dst (DivL src1 src2)); 7122 ins_cost(DEFAULT_COST*71); 7123 size(4); 7124 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7125 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7126 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7127 ins_pipe(divL_reg_reg); 7128 %} 7129 7130 // Register Long Division 7131 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7132 match(Set dst (DivL src1 src2)); 7133 ins_cost(DEFAULT_COST*71); 7134 size(4); 7135 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7136 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7137 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7138 ins_pipe(divL_reg_imm); 7139 %} 7140 7141 // Integer Remainder 7142 // Register Remainder 7143 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7144 match(Set dst (ModI src1 src2)); 7145 effect( KILL ccr, KILL temp); 7146 7147 format %{ "SREM $src1,$src2,$dst" %} 7148 ins_encode( irem_reg(src1, src2, dst, temp) ); 7149 ins_pipe(sdiv_reg_reg); 7150 %} 7151 7152 // Immediate Remainder 7153 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7154 match(Set dst (ModI src1 src2)); 7155 effect( KILL ccr, KILL temp); 7156 7157 format %{ "SREM $src1,$src2,$dst" %} 7158 ins_encode( irem_imm(src1, src2, dst, temp) ); 7159 ins_pipe(sdiv_reg_imm); 7160 %} 7161 7162 // Register Long Remainder 7163 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7164 effect(DEF dst, USE src1, USE src2); 7165 size(4); 7166 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7167 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7168 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7169 ins_pipe(divL_reg_reg); 7170 %} 7171 7172 // Register Long Division 7173 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7174 effect(DEF dst, USE src1, USE src2); 7175 size(4); 7176 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7177 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7178 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7179 ins_pipe(divL_reg_imm); 7180 %} 7181 7182 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7183 effect(DEF dst, USE src1, USE src2); 7184 size(4); 7185 format %{ "MULX $src1,$src2,$dst\t! long" %} 7186 opcode(Assembler::mulx_op3, Assembler::arith_op); 7187 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7188 ins_pipe(mulL_reg_reg); 7189 %} 7190 7191 // Immediate Multiplication 7192 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7193 effect(DEF dst, USE src1, USE src2); 7194 size(4); 7195 format %{ "MULX $src1,$src2,$dst" %} 7196 opcode(Assembler::mulx_op3, Assembler::arith_op); 7197 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7198 ins_pipe(mulL_reg_imm); 7199 %} 7200 7201 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7202 effect(DEF dst, USE src1, USE src2); 7203 size(4); 7204 format %{ "SUB $src1,$src2,$dst\t! long" %} 7205 opcode(Assembler::sub_op3, Assembler::arith_op); 7206 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7207 ins_pipe(ialu_reg_reg); 7208 %} 7209 7210 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7211 effect(DEF dst, USE src1, USE src2); 7212 size(4); 7213 format %{ "SUB $src1,$src2,$dst\t! long" %} 7214 opcode(Assembler::sub_op3, Assembler::arith_op); 7215 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7216 ins_pipe(ialu_reg_reg); 7217 %} 7218 7219 // Register Long Remainder 7220 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7221 match(Set dst (ModL src1 src2)); 7222 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7223 expand %{ 7224 iRegL tmp1; 7225 iRegL tmp2; 7226 divL_reg_reg_1(tmp1, src1, src2); 7227 mulL_reg_reg_1(tmp2, tmp1, src2); 7228 subL_reg_reg_1(dst, src1, tmp2); 7229 %} 7230 %} 7231 7232 // Register Long Remainder 7233 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7234 match(Set dst (ModL src1 src2)); 7235 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7236 expand %{ 7237 iRegL tmp1; 7238 iRegL tmp2; 7239 divL_reg_imm13_1(tmp1, src1, src2); 7240 mulL_reg_imm13_1(tmp2, tmp1, src2); 7241 subL_reg_reg_2 (dst, src1, tmp2); 7242 %} 7243 %} 7244 7245 // Integer Shift Instructions 7246 // Register Shift Left 7247 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7248 match(Set dst (LShiftI src1 src2)); 7249 7250 size(4); 7251 format %{ "SLL $src1,$src2,$dst" %} 7252 opcode(Assembler::sll_op3, Assembler::arith_op); 7253 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7254 ins_pipe(ialu_reg_reg); 7255 %} 7256 7257 // Register Shift Left Immediate 7258 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7259 match(Set dst (LShiftI src1 src2)); 7260 7261 size(4); 7262 format %{ "SLL $src1,$src2,$dst" %} 7263 opcode(Assembler::sll_op3, Assembler::arith_op); 7264 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7265 ins_pipe(ialu_reg_imm); 7266 %} 7267 7268 // Register Shift Left 7269 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7270 match(Set dst (LShiftL src1 src2)); 7271 7272 size(4); 7273 format %{ "SLLX $src1,$src2,$dst" %} 7274 opcode(Assembler::sllx_op3, Assembler::arith_op); 7275 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7276 ins_pipe(ialu_reg_reg); 7277 %} 7278 7279 // Register Shift Left Immediate 7280 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7281 match(Set dst (LShiftL src1 src2)); 7282 7283 size(4); 7284 format %{ "SLLX $src1,$src2,$dst" %} 7285 opcode(Assembler::sllx_op3, Assembler::arith_op); 7286 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7287 ins_pipe(ialu_reg_imm); 7288 %} 7289 7290 // Register Arithmetic Shift Right 7291 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7292 match(Set dst (RShiftI src1 src2)); 7293 size(4); 7294 format %{ "SRA $src1,$src2,$dst" %} 7295 opcode(Assembler::sra_op3, Assembler::arith_op); 7296 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7297 ins_pipe(ialu_reg_reg); 7298 %} 7299 7300 // Register Arithmetic Shift Right Immediate 7301 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7302 match(Set dst (RShiftI src1 src2)); 7303 7304 size(4); 7305 format %{ "SRA $src1,$src2,$dst" %} 7306 opcode(Assembler::sra_op3, Assembler::arith_op); 7307 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7308 ins_pipe(ialu_reg_imm); 7309 %} 7310 7311 // Register Shift Right Arithmatic Long 7312 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7313 match(Set dst (RShiftL src1 src2)); 7314 7315 size(4); 7316 format %{ "SRAX $src1,$src2,$dst" %} 7317 opcode(Assembler::srax_op3, Assembler::arith_op); 7318 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7319 ins_pipe(ialu_reg_reg); 7320 %} 7321 7322 // Register Shift Left Immediate 7323 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7324 match(Set dst (RShiftL src1 src2)); 7325 7326 size(4); 7327 format %{ "SRAX $src1,$src2,$dst" %} 7328 opcode(Assembler::srax_op3, Assembler::arith_op); 7329 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7330 ins_pipe(ialu_reg_imm); 7331 %} 7332 7333 // Register Shift Right 7334 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7335 match(Set dst (URShiftI src1 src2)); 7336 7337 size(4); 7338 format %{ "SRL $src1,$src2,$dst" %} 7339 opcode(Assembler::srl_op3, Assembler::arith_op); 7340 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7341 ins_pipe(ialu_reg_reg); 7342 %} 7343 7344 // Register Shift Right Immediate 7345 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7346 match(Set dst (URShiftI src1 src2)); 7347 7348 size(4); 7349 format %{ "SRL $src1,$src2,$dst" %} 7350 opcode(Assembler::srl_op3, Assembler::arith_op); 7351 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7352 ins_pipe(ialu_reg_imm); 7353 %} 7354 7355 // Register Shift Right 7356 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7357 match(Set dst (URShiftL src1 src2)); 7358 7359 size(4); 7360 format %{ "SRLX $src1,$src2,$dst" %} 7361 opcode(Assembler::srlx_op3, Assembler::arith_op); 7362 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7363 ins_pipe(ialu_reg_reg); 7364 %} 7365 7366 // Register Shift Right Immediate 7367 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7368 match(Set dst (URShiftL src1 src2)); 7369 7370 size(4); 7371 format %{ "SRLX $src1,$src2,$dst" %} 7372 opcode(Assembler::srlx_op3, Assembler::arith_op); 7373 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7374 ins_pipe(ialu_reg_imm); 7375 %} 7376 7377 // Register Shift Right Immediate with a CastP2X 7378 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7379 match(Set dst (URShiftL (CastP2X src1) src2)); 7380 size(4); 7381 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7382 opcode(Assembler::srlx_op3, Assembler::arith_op); 7383 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7384 ins_pipe(ialu_reg_imm); 7385 %} 7386 7387 7388 //----------Floating Point Arithmetic Instructions----------------------------- 7389 7390 // Add float single precision 7391 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7392 match(Set dst (AddF src1 src2)); 7393 7394 size(4); 7395 format %{ "FADDS $src1,$src2,$dst" %} 7396 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7397 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7398 ins_pipe(faddF_reg_reg); 7399 %} 7400 7401 // Add float double precision 7402 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7403 match(Set dst (AddD src1 src2)); 7404 7405 size(4); 7406 format %{ "FADDD $src1,$src2,$dst" %} 7407 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7408 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7409 ins_pipe(faddD_reg_reg); 7410 %} 7411 7412 // Sub float single precision 7413 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7414 match(Set dst (SubF src1 src2)); 7415 7416 size(4); 7417 format %{ "FSUBS $src1,$src2,$dst" %} 7418 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7419 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7420 ins_pipe(faddF_reg_reg); 7421 %} 7422 7423 // Sub float double precision 7424 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7425 match(Set dst (SubD src1 src2)); 7426 7427 size(4); 7428 format %{ "FSUBD $src1,$src2,$dst" %} 7429 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7430 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7431 ins_pipe(faddD_reg_reg); 7432 %} 7433 7434 // Mul float single precision 7435 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7436 match(Set dst (MulF src1 src2)); 7437 7438 size(4); 7439 format %{ "FMULS $src1,$src2,$dst" %} 7440 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7441 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7442 ins_pipe(fmulF_reg_reg); 7443 %} 7444 7445 // Mul float double precision 7446 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7447 match(Set dst (MulD src1 src2)); 7448 7449 size(4); 7450 format %{ "FMULD $src1,$src2,$dst" %} 7451 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7452 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7453 ins_pipe(fmulD_reg_reg); 7454 %} 7455 7456 // Div float single precision 7457 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7458 match(Set dst (DivF src1 src2)); 7459 7460 size(4); 7461 format %{ "FDIVS $src1,$src2,$dst" %} 7462 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7463 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7464 ins_pipe(fdivF_reg_reg); 7465 %} 7466 7467 // Div float double precision 7468 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7469 match(Set dst (DivD src1 src2)); 7470 7471 size(4); 7472 format %{ "FDIVD $src1,$src2,$dst" %} 7473 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7474 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7475 ins_pipe(fdivD_reg_reg); 7476 %} 7477 7478 // Absolute float double precision 7479 instruct absD_reg(regD dst, regD src) %{ 7480 match(Set dst (AbsD src)); 7481 7482 format %{ "FABSd $src,$dst" %} 7483 ins_encode(fabsd(dst, src)); 7484 ins_pipe(faddD_reg); 7485 %} 7486 7487 // Absolute float single precision 7488 instruct absF_reg(regF dst, regF src) %{ 7489 match(Set dst (AbsF src)); 7490 7491 format %{ "FABSs $src,$dst" %} 7492 ins_encode(fabss(dst, src)); 7493 ins_pipe(faddF_reg); 7494 %} 7495 7496 instruct negF_reg(regF dst, regF src) %{ 7497 match(Set dst (NegF src)); 7498 7499 size(4); 7500 format %{ "FNEGs $src,$dst" %} 7501 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7502 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7503 ins_pipe(faddF_reg); 7504 %} 7505 7506 instruct negD_reg(regD dst, regD src) %{ 7507 match(Set dst (NegD src)); 7508 7509 format %{ "FNEGd $src,$dst" %} 7510 ins_encode(fnegd(dst, src)); 7511 ins_pipe(faddD_reg); 7512 %} 7513 7514 // Sqrt float double precision 7515 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7516 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7517 7518 size(4); 7519 format %{ "FSQRTS $src,$dst" %} 7520 ins_encode(fsqrts(dst, src)); 7521 ins_pipe(fdivF_reg_reg); 7522 %} 7523 7524 // Sqrt float double precision 7525 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7526 match(Set dst (SqrtD src)); 7527 7528 size(4); 7529 format %{ "FSQRTD $src,$dst" %} 7530 ins_encode(fsqrtd(dst, src)); 7531 ins_pipe(fdivD_reg_reg); 7532 %} 7533 7534 //----------Logical Instructions----------------------------------------------- 7535 // And Instructions 7536 // Register And 7537 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7538 match(Set dst (AndI src1 src2)); 7539 7540 size(4); 7541 format %{ "AND $src1,$src2,$dst" %} 7542 opcode(Assembler::and_op3, Assembler::arith_op); 7543 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7544 ins_pipe(ialu_reg_reg); 7545 %} 7546 7547 // Immediate And 7548 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7549 match(Set dst (AndI src1 src2)); 7550 7551 size(4); 7552 format %{ "AND $src1,$src2,$dst" %} 7553 opcode(Assembler::and_op3, Assembler::arith_op); 7554 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7555 ins_pipe(ialu_reg_imm); 7556 %} 7557 7558 // Register And Long 7559 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7560 match(Set dst (AndL src1 src2)); 7561 7562 ins_cost(DEFAULT_COST); 7563 size(4); 7564 format %{ "AND $src1,$src2,$dst\t! long" %} 7565 opcode(Assembler::and_op3, Assembler::arith_op); 7566 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7567 ins_pipe(ialu_reg_reg); 7568 %} 7569 7570 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7571 match(Set dst (AndL src1 con)); 7572 7573 ins_cost(DEFAULT_COST); 7574 size(4); 7575 format %{ "AND $src1,$con,$dst\t! long" %} 7576 opcode(Assembler::and_op3, Assembler::arith_op); 7577 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7578 ins_pipe(ialu_reg_imm); 7579 %} 7580 7581 // Or Instructions 7582 // Register Or 7583 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7584 match(Set dst (OrI src1 src2)); 7585 7586 size(4); 7587 format %{ "OR $src1,$src2,$dst" %} 7588 opcode(Assembler::or_op3, Assembler::arith_op); 7589 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7590 ins_pipe(ialu_reg_reg); 7591 %} 7592 7593 // Immediate Or 7594 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7595 match(Set dst (OrI src1 src2)); 7596 7597 size(4); 7598 format %{ "OR $src1,$src2,$dst" %} 7599 opcode(Assembler::or_op3, Assembler::arith_op); 7600 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7601 ins_pipe(ialu_reg_imm); 7602 %} 7603 7604 // Register Or Long 7605 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7606 match(Set dst (OrL src1 src2)); 7607 7608 ins_cost(DEFAULT_COST); 7609 size(4); 7610 format %{ "OR $src1,$src2,$dst\t! long" %} 7611 opcode(Assembler::or_op3, Assembler::arith_op); 7612 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7613 ins_pipe(ialu_reg_reg); 7614 %} 7615 7616 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7617 match(Set dst (OrL src1 con)); 7618 ins_cost(DEFAULT_COST*2); 7619 7620 ins_cost(DEFAULT_COST); 7621 size(4); 7622 format %{ "OR $src1,$con,$dst\t! long" %} 7623 opcode(Assembler::or_op3, Assembler::arith_op); 7624 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7625 ins_pipe(ialu_reg_imm); 7626 %} 7627 7628 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7629 match(Set dst (OrL src1 (CastP2X src2))); 7630 7631 ins_cost(DEFAULT_COST); 7632 size(4); 7633 format %{ "OR $src1,$src2,$dst\t! long" %} 7634 opcode(Assembler::or_op3, Assembler::arith_op); 7635 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7636 ins_pipe(ialu_reg_reg); 7637 %} 7638 7639 // Xor Instructions 7640 // Register Xor 7641 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7642 match(Set dst (XorI src1 src2)); 7643 7644 size(4); 7645 format %{ "XOR $src1,$src2,$dst" %} 7646 opcode(Assembler::xor_op3, Assembler::arith_op); 7647 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7648 ins_pipe(ialu_reg_reg); 7649 %} 7650 7651 // Immediate Xor 7652 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7653 match(Set dst (XorI src1 src2)); 7654 7655 size(4); 7656 format %{ "XOR $src1,$src2,$dst" %} 7657 opcode(Assembler::xor_op3, Assembler::arith_op); 7658 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7659 ins_pipe(ialu_reg_imm); 7660 %} 7661 7662 // Register Xor Long 7663 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7664 match(Set dst (XorL src1 src2)); 7665 7666 ins_cost(DEFAULT_COST); 7667 size(4); 7668 format %{ "XOR $src1,$src2,$dst\t! long" %} 7669 opcode(Assembler::xor_op3, Assembler::arith_op); 7670 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7671 ins_pipe(ialu_reg_reg); 7672 %} 7673 7674 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7675 match(Set dst (XorL src1 con)); 7676 7677 ins_cost(DEFAULT_COST); 7678 size(4); 7679 format %{ "XOR $src1,$con,$dst\t! long" %} 7680 opcode(Assembler::xor_op3, Assembler::arith_op); 7681 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7682 ins_pipe(ialu_reg_imm); 7683 %} 7684 7685 //----------Convert to Boolean------------------------------------------------- 7686 // Nice hack for 32-bit tests but doesn't work for 7687 // 64-bit pointers. 7688 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 7689 match(Set dst (Conv2B src)); 7690 effect( KILL ccr ); 7691 ins_cost(DEFAULT_COST*2); 7692 format %{ "CMP R_G0,$src\n\t" 7693 "ADDX R_G0,0,$dst" %} 7694 ins_encode( enc_to_bool( src, dst ) ); 7695 ins_pipe(ialu_reg_ialu); 7696 %} 7697 7698 instruct convP2B( iRegI dst, iRegP src ) %{ 7699 match(Set dst (Conv2B src)); 7700 ins_cost(DEFAULT_COST*2); 7701 format %{ "MOV $src,$dst\n\t" 7702 "MOVRNZ $src,1,$dst" %} 7703 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 7704 ins_pipe(ialu_clr_and_mover); 7705 %} 7706 7707 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 7708 match(Set dst (CmpLTMask src zero)); 7709 effect(KILL ccr); 7710 size(4); 7711 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 7712 ins_encode %{ 7713 __ sra($src$$Register, 31, $dst$$Register); 7714 %} 7715 ins_pipe(ialu_reg_imm); 7716 %} 7717 7718 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 7719 match(Set dst (CmpLTMask p q)); 7720 effect( KILL ccr ); 7721 ins_cost(DEFAULT_COST*4); 7722 format %{ "CMP $p,$q\n\t" 7723 "MOV #0,$dst\n\t" 7724 "BLT,a .+8\n\t" 7725 "MOV #-1,$dst" %} 7726 ins_encode( enc_ltmask(p,q,dst) ); 7727 ins_pipe(ialu_reg_reg_ialu); 7728 %} 7729 7730 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 7731 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 7732 effect(KILL ccr, TEMP tmp); 7733 ins_cost(DEFAULT_COST*3); 7734 7735 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 7736 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 7737 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 7738 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); 7739 ins_pipe(cadd_cmpltmask); 7740 %} 7741 7742 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ 7743 match(Set p (AndI (CmpLTMask p q) y)); 7744 effect(KILL ccr); 7745 ins_cost(DEFAULT_COST*3); 7746 7747 format %{ "CMP $p,$q\n\t" 7748 "MOV $y,$p\n\t" 7749 "MOVge G0,$p" %} 7750 ins_encode %{ 7751 __ cmp($p$$Register, $q$$Register); 7752 __ mov($y$$Register, $p$$Register); 7753 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); 7754 %} 7755 ins_pipe(ialu_reg_reg_ialu); 7756 %} 7757 7758 //----------------------------------------------------------------- 7759 // Direct raw moves between float and general registers using VIS3. 7760 7761 // ins_pipe(faddF_reg); 7762 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 7763 predicate(UseVIS >= 3); 7764 match(Set dst (MoveF2I src)); 7765 7766 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 7767 ins_encode %{ 7768 __ movstouw($src$$FloatRegister, $dst$$Register); 7769 %} 7770 ins_pipe(ialu_reg_reg); 7771 %} 7772 7773 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 7774 predicate(UseVIS >= 3); 7775 match(Set dst (MoveI2F src)); 7776 7777 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 7778 ins_encode %{ 7779 __ movwtos($src$$Register, $dst$$FloatRegister); 7780 %} 7781 ins_pipe(ialu_reg_reg); 7782 %} 7783 7784 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 7785 predicate(UseVIS >= 3); 7786 match(Set dst (MoveD2L src)); 7787 7788 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 7789 ins_encode %{ 7790 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 7791 %} 7792 ins_pipe(ialu_reg_reg); 7793 %} 7794 7795 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 7796 predicate(UseVIS >= 3); 7797 match(Set dst (MoveL2D src)); 7798 7799 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 7800 ins_encode %{ 7801 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 7802 %} 7803 ins_pipe(ialu_reg_reg); 7804 %} 7805 7806 7807 // Raw moves between float and general registers using stack. 7808 7809 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 7810 match(Set dst (MoveF2I src)); 7811 effect(DEF dst, USE src); 7812 ins_cost(MEMORY_REF_COST); 7813 7814 format %{ "LDUW $src,$dst\t! MoveF2I" %} 7815 opcode(Assembler::lduw_op3); 7816 ins_encode(simple_form3_mem_reg( src, dst ) ); 7817 ins_pipe(iload_mem); 7818 %} 7819 7820 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 7821 match(Set dst (MoveI2F src)); 7822 effect(DEF dst, USE src); 7823 ins_cost(MEMORY_REF_COST); 7824 7825 format %{ "LDF $src,$dst\t! MoveI2F" %} 7826 opcode(Assembler::ldf_op3); 7827 ins_encode(simple_form3_mem_reg(src, dst)); 7828 ins_pipe(floadF_stk); 7829 %} 7830 7831 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 7832 match(Set dst (MoveD2L src)); 7833 effect(DEF dst, USE src); 7834 ins_cost(MEMORY_REF_COST); 7835 7836 format %{ "LDX $src,$dst\t! MoveD2L" %} 7837 opcode(Assembler::ldx_op3); 7838 ins_encode(simple_form3_mem_reg( src, dst ) ); 7839 ins_pipe(iload_mem); 7840 %} 7841 7842 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 7843 match(Set dst (MoveL2D src)); 7844 effect(DEF dst, USE src); 7845 ins_cost(MEMORY_REF_COST); 7846 7847 format %{ "LDDF $src,$dst\t! MoveL2D" %} 7848 opcode(Assembler::lddf_op3); 7849 ins_encode(simple_form3_mem_reg(src, dst)); 7850 ins_pipe(floadD_stk); 7851 %} 7852 7853 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 7854 match(Set dst (MoveF2I src)); 7855 effect(DEF dst, USE src); 7856 ins_cost(MEMORY_REF_COST); 7857 7858 format %{ "STF $src,$dst\t! MoveF2I" %} 7859 opcode(Assembler::stf_op3); 7860 ins_encode(simple_form3_mem_reg(dst, src)); 7861 ins_pipe(fstoreF_stk_reg); 7862 %} 7863 7864 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 7865 match(Set dst (MoveI2F src)); 7866 effect(DEF dst, USE src); 7867 ins_cost(MEMORY_REF_COST); 7868 7869 format %{ "STW $src,$dst\t! MoveI2F" %} 7870 opcode(Assembler::stw_op3); 7871 ins_encode(simple_form3_mem_reg( dst, src ) ); 7872 ins_pipe(istore_mem_reg); 7873 %} 7874 7875 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 7876 match(Set dst (MoveD2L src)); 7877 effect(DEF dst, USE src); 7878 ins_cost(MEMORY_REF_COST); 7879 7880 format %{ "STDF $src,$dst\t! MoveD2L" %} 7881 opcode(Assembler::stdf_op3); 7882 ins_encode(simple_form3_mem_reg(dst, src)); 7883 ins_pipe(fstoreD_stk_reg); 7884 %} 7885 7886 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 7887 match(Set dst (MoveL2D src)); 7888 effect(DEF dst, USE src); 7889 ins_cost(MEMORY_REF_COST); 7890 7891 format %{ "STX $src,$dst\t! MoveL2D" %} 7892 opcode(Assembler::stx_op3); 7893 ins_encode(simple_form3_mem_reg( dst, src ) ); 7894 ins_pipe(istore_mem_reg); 7895 %} 7896 7897 7898 //----------Arithmetic Conversion Instructions--------------------------------- 7899 // The conversions operations are all Alpha sorted. Please keep it that way! 7900 7901 instruct convD2F_reg(regF dst, regD src) %{ 7902 match(Set dst (ConvD2F src)); 7903 size(4); 7904 format %{ "FDTOS $src,$dst" %} 7905 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 7906 ins_encode(form3_opf_rs2D_rdF(src, dst)); 7907 ins_pipe(fcvtD2F); 7908 %} 7909 7910 7911 // Convert a double to an int in a float register. 7912 // If the double is a NAN, stuff a zero in instead. 7913 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 7914 effect(DEF dst, USE src, KILL fcc0); 7915 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 7916 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7917 "FDTOI $src,$dst\t! convert in delay slot\n\t" 7918 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 7919 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 7920 "skip:" %} 7921 ins_encode(form_d2i_helper(src,dst)); 7922 ins_pipe(fcvtD2I); 7923 %} 7924 7925 instruct convD2I_stk(stackSlotI dst, regD src) %{ 7926 match(Set dst (ConvD2I src)); 7927 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7928 expand %{ 7929 regF tmp; 7930 convD2I_helper(tmp, src); 7931 regF_to_stkI(dst, tmp); 7932 %} 7933 %} 7934 7935 instruct convD2I_reg(iRegI dst, regD src) %{ 7936 predicate(UseVIS >= 3); 7937 match(Set dst (ConvD2I src)); 7938 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 7939 expand %{ 7940 regF tmp; 7941 convD2I_helper(tmp, src); 7942 MoveF2I_reg_reg(dst, tmp); 7943 %} 7944 %} 7945 7946 7947 // Convert a double to a long in a double register. 7948 // If the double is a NAN, stuff a zero in instead. 7949 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 7950 effect(DEF dst, USE src, KILL fcc0); 7951 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 7952 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7953 "FDTOX $src,$dst\t! convert in delay slot\n\t" 7954 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 7955 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 7956 "skip:" %} 7957 ins_encode(form_d2l_helper(src,dst)); 7958 ins_pipe(fcvtD2L); 7959 %} 7960 7961 instruct convD2L_stk(stackSlotL dst, regD src) %{ 7962 match(Set dst (ConvD2L src)); 7963 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 7964 expand %{ 7965 regD tmp; 7966 convD2L_helper(tmp, src); 7967 regD_to_stkL(dst, tmp); 7968 %} 7969 %} 7970 7971 instruct convD2L_reg(iRegL dst, regD src) %{ 7972 predicate(UseVIS >= 3); 7973 match(Set dst (ConvD2L src)); 7974 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 7975 expand %{ 7976 regD tmp; 7977 convD2L_helper(tmp, src); 7978 MoveD2L_reg_reg(dst, tmp); 7979 %} 7980 %} 7981 7982 7983 instruct convF2D_reg(regD dst, regF src) %{ 7984 match(Set dst (ConvF2D src)); 7985 format %{ "FSTOD $src,$dst" %} 7986 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 7987 ins_encode(form3_opf_rs2F_rdD(src, dst)); 7988 ins_pipe(fcvtF2D); 7989 %} 7990 7991 7992 // Convert a float to an int in a float register. 7993 // If the float is a NAN, stuff a zero in instead. 7994 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 7995 effect(DEF dst, USE src, KILL fcc0); 7996 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 7997 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 7998 "FSTOI $src,$dst\t! convert in delay slot\n\t" 7999 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8000 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8001 "skip:" %} 8002 ins_encode(form_f2i_helper(src,dst)); 8003 ins_pipe(fcvtF2I); 8004 %} 8005 8006 instruct convF2I_stk(stackSlotI dst, regF src) %{ 8007 match(Set dst (ConvF2I src)); 8008 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8009 expand %{ 8010 regF tmp; 8011 convF2I_helper(tmp, src); 8012 regF_to_stkI(dst, tmp); 8013 %} 8014 %} 8015 8016 instruct convF2I_reg(iRegI dst, regF src) %{ 8017 predicate(UseVIS >= 3); 8018 match(Set dst (ConvF2I src)); 8019 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8020 expand %{ 8021 regF tmp; 8022 convF2I_helper(tmp, src); 8023 MoveF2I_reg_reg(dst, tmp); 8024 %} 8025 %} 8026 8027 8028 // Convert a float to a long in a float register. 8029 // If the float is a NAN, stuff a zero in instead. 8030 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8031 effect(DEF dst, USE src, KILL fcc0); 8032 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8033 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8034 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8035 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8036 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8037 "skip:" %} 8038 ins_encode(form_f2l_helper(src,dst)); 8039 ins_pipe(fcvtF2L); 8040 %} 8041 8042 instruct convF2L_stk(stackSlotL dst, regF src) %{ 8043 match(Set dst (ConvF2L src)); 8044 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8045 expand %{ 8046 regD tmp; 8047 convF2L_helper(tmp, src); 8048 regD_to_stkL(dst, tmp); 8049 %} 8050 %} 8051 8052 instruct convF2L_reg(iRegL dst, regF src) %{ 8053 predicate(UseVIS >= 3); 8054 match(Set dst (ConvF2L src)); 8055 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8056 expand %{ 8057 regD tmp; 8058 convF2L_helper(tmp, src); 8059 MoveD2L_reg_reg(dst, tmp); 8060 %} 8061 %} 8062 8063 8064 instruct convI2D_helper(regD dst, regF tmp) %{ 8065 effect(USE tmp, DEF dst); 8066 format %{ "FITOD $tmp,$dst" %} 8067 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8068 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8069 ins_pipe(fcvtI2D); 8070 %} 8071 8072 instruct convI2D_stk(stackSlotI src, regD dst) %{ 8073 match(Set dst (ConvI2D src)); 8074 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8075 expand %{ 8076 regF tmp; 8077 stkI_to_regF(tmp, src); 8078 convI2D_helper(dst, tmp); 8079 %} 8080 %} 8081 8082 instruct convI2D_reg(regD_low dst, iRegI src) %{ 8083 predicate(UseVIS >= 3); 8084 match(Set dst (ConvI2D src)); 8085 expand %{ 8086 regF tmp; 8087 MoveI2F_reg_reg(tmp, src); 8088 convI2D_helper(dst, tmp); 8089 %} 8090 %} 8091 8092 instruct convI2D_mem(regD_low dst, memory mem) %{ 8093 match(Set dst (ConvI2D (LoadI mem))); 8094 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8095 format %{ "LDF $mem,$dst\n\t" 8096 "FITOD $dst,$dst" %} 8097 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8098 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8099 ins_pipe(floadF_mem); 8100 %} 8101 8102 8103 instruct convI2F_helper(regF dst, regF tmp) %{ 8104 effect(DEF dst, USE tmp); 8105 format %{ "FITOS $tmp,$dst" %} 8106 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8107 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8108 ins_pipe(fcvtI2F); 8109 %} 8110 8111 instruct convI2F_stk(regF dst, stackSlotI src) %{ 8112 match(Set dst (ConvI2F src)); 8113 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8114 expand %{ 8115 regF tmp; 8116 stkI_to_regF(tmp,src); 8117 convI2F_helper(dst, tmp); 8118 %} 8119 %} 8120 8121 instruct convI2F_reg(regF dst, iRegI src) %{ 8122 predicate(UseVIS >= 3); 8123 match(Set dst (ConvI2F src)); 8124 ins_cost(DEFAULT_COST); 8125 expand %{ 8126 regF tmp; 8127 MoveI2F_reg_reg(tmp, src); 8128 convI2F_helper(dst, tmp); 8129 %} 8130 %} 8131 8132 instruct convI2F_mem( regF dst, memory mem ) %{ 8133 match(Set dst (ConvI2F (LoadI mem))); 8134 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8135 format %{ "LDF $mem,$dst\n\t" 8136 "FITOS $dst,$dst" %} 8137 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8138 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8139 ins_pipe(floadF_mem); 8140 %} 8141 8142 8143 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8144 match(Set dst (ConvI2L src)); 8145 size(4); 8146 format %{ "SRA $src,0,$dst\t! int->long" %} 8147 opcode(Assembler::sra_op3, Assembler::arith_op); 8148 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8149 ins_pipe(ialu_reg_reg); 8150 %} 8151 8152 // Zero-extend convert int to long 8153 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8154 match(Set dst (AndL (ConvI2L src) mask) ); 8155 size(4); 8156 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8157 opcode(Assembler::srl_op3, Assembler::arith_op); 8158 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8159 ins_pipe(ialu_reg_reg); 8160 %} 8161 8162 // Zero-extend long 8163 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8164 match(Set dst (AndL src mask) ); 8165 size(4); 8166 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8167 opcode(Assembler::srl_op3, Assembler::arith_op); 8168 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8169 ins_pipe(ialu_reg_reg); 8170 %} 8171 8172 8173 //----------- 8174 // Long to Double conversion using V8 opcodes. 8175 // Still useful because cheetah traps and becomes 8176 // amazingly slow for some common numbers. 8177 8178 // Magic constant, 0x43300000 8179 instruct loadConI_x43300000(iRegI dst) %{ 8180 effect(DEF dst); 8181 size(4); 8182 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8183 ins_encode(SetHi22(0x43300000, dst)); 8184 ins_pipe(ialu_none); 8185 %} 8186 8187 // Magic constant, 0x41f00000 8188 instruct loadConI_x41f00000(iRegI dst) %{ 8189 effect(DEF dst); 8190 size(4); 8191 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8192 ins_encode(SetHi22(0x41f00000, dst)); 8193 ins_pipe(ialu_none); 8194 %} 8195 8196 // Construct a double from two float halves 8197 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8198 effect(DEF dst, USE src1, USE src2); 8199 size(8); 8200 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8201 "FMOVS $src2.lo,$dst.lo" %} 8202 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8203 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8204 ins_pipe(faddD_reg_reg); 8205 %} 8206 8207 // Convert integer in high half of a double register (in the lower half of 8208 // the double register file) to double 8209 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8210 effect(DEF dst, USE src); 8211 size(4); 8212 format %{ "FITOD $src,$dst" %} 8213 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8214 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8215 ins_pipe(fcvtLHi2D); 8216 %} 8217 8218 // Add float double precision 8219 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8220 effect(DEF dst, USE src1, USE src2); 8221 size(4); 8222 format %{ "FADDD $src1,$src2,$dst" %} 8223 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8224 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8225 ins_pipe(faddD_reg_reg); 8226 %} 8227 8228 // Sub float double precision 8229 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8230 effect(DEF dst, USE src1, USE src2); 8231 size(4); 8232 format %{ "FSUBD $src1,$src2,$dst" %} 8233 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8234 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8235 ins_pipe(faddD_reg_reg); 8236 %} 8237 8238 // Mul float double precision 8239 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8240 effect(DEF dst, USE src1, USE src2); 8241 size(4); 8242 format %{ "FMULD $src1,$src2,$dst" %} 8243 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8244 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8245 ins_pipe(fmulD_reg_reg); 8246 %} 8247 8248 // Long to Double conversion using fast fxtof 8249 instruct convL2D_helper(regD dst, regD tmp) %{ 8250 effect(DEF dst, USE tmp); 8251 size(4); 8252 format %{ "FXTOD $tmp,$dst" %} 8253 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8254 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8255 ins_pipe(fcvtL2D); 8256 %} 8257 8258 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8259 match(Set dst (ConvL2D src)); 8260 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8261 expand %{ 8262 regD tmp; 8263 stkL_to_regD(tmp, src); 8264 convL2D_helper(dst, tmp); 8265 %} 8266 %} 8267 8268 instruct convL2D_reg(regD dst, iRegL src) %{ 8269 predicate(UseVIS >= 3); 8270 match(Set dst (ConvL2D src)); 8271 expand %{ 8272 regD tmp; 8273 MoveL2D_reg_reg(tmp, src); 8274 convL2D_helper(dst, tmp); 8275 %} 8276 %} 8277 8278 // Long to Float conversion using fast fxtof 8279 instruct convL2F_helper(regF dst, regD tmp) %{ 8280 effect(DEF dst, USE tmp); 8281 size(4); 8282 format %{ "FXTOS $tmp,$dst" %} 8283 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8284 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8285 ins_pipe(fcvtL2F); 8286 %} 8287 8288 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8289 match(Set dst (ConvL2F src)); 8290 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8291 expand %{ 8292 regD tmp; 8293 stkL_to_regD(tmp, src); 8294 convL2F_helper(dst, tmp); 8295 %} 8296 %} 8297 8298 instruct convL2F_reg(regF dst, iRegL src) %{ 8299 predicate(UseVIS >= 3); 8300 match(Set dst (ConvL2F src)); 8301 ins_cost(DEFAULT_COST); 8302 expand %{ 8303 regD tmp; 8304 MoveL2D_reg_reg(tmp, src); 8305 convL2F_helper(dst, tmp); 8306 %} 8307 %} 8308 8309 //----------- 8310 8311 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8312 match(Set dst (ConvL2I src)); 8313 size(4); 8314 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8315 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8316 ins_pipe(ialu_reg); 8317 %} 8318 8319 // Register Shift Right Immediate 8320 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8321 match(Set dst (ConvL2I (RShiftL src cnt))); 8322 8323 size(4); 8324 format %{ "SRAX $src,$cnt,$dst" %} 8325 opcode(Assembler::srax_op3, Assembler::arith_op); 8326 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8327 ins_pipe(ialu_reg_imm); 8328 %} 8329 8330 //----------Control Flow Instructions------------------------------------------ 8331 // Compare Instructions 8332 // Compare Integers 8333 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8334 match(Set icc (CmpI op1 op2)); 8335 effect( DEF icc, USE op1, USE op2 ); 8336 8337 size(4); 8338 format %{ "CMP $op1,$op2" %} 8339 opcode(Assembler::subcc_op3, Assembler::arith_op); 8340 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8341 ins_pipe(ialu_cconly_reg_reg); 8342 %} 8343 8344 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8345 match(Set icc (CmpU op1 op2)); 8346 8347 size(4); 8348 format %{ "CMP $op1,$op2\t! unsigned" %} 8349 opcode(Assembler::subcc_op3, Assembler::arith_op); 8350 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8351 ins_pipe(ialu_cconly_reg_reg); 8352 %} 8353 8354 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8355 match(Set icc (CmpI op1 op2)); 8356 effect( DEF icc, USE op1 ); 8357 8358 size(4); 8359 format %{ "CMP $op1,$op2" %} 8360 opcode(Assembler::subcc_op3, Assembler::arith_op); 8361 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8362 ins_pipe(ialu_cconly_reg_imm); 8363 %} 8364 8365 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8366 match(Set icc (CmpI (AndI op1 op2) zero)); 8367 8368 size(4); 8369 format %{ "BTST $op2,$op1" %} 8370 opcode(Assembler::andcc_op3, Assembler::arith_op); 8371 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8372 ins_pipe(ialu_cconly_reg_reg_zero); 8373 %} 8374 8375 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8376 match(Set icc (CmpI (AndI op1 op2) zero)); 8377 8378 size(4); 8379 format %{ "BTST $op2,$op1" %} 8380 opcode(Assembler::andcc_op3, Assembler::arith_op); 8381 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8382 ins_pipe(ialu_cconly_reg_imm_zero); 8383 %} 8384 8385 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8386 match(Set xcc (CmpL op1 op2)); 8387 effect( DEF xcc, USE op1, USE op2 ); 8388 8389 size(4); 8390 format %{ "CMP $op1,$op2\t\t! long" %} 8391 opcode(Assembler::subcc_op3, Assembler::arith_op); 8392 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8393 ins_pipe(ialu_cconly_reg_reg); 8394 %} 8395 8396 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8397 match(Set xcc (CmpL op1 con)); 8398 effect( DEF xcc, USE op1, USE con ); 8399 8400 size(4); 8401 format %{ "CMP $op1,$con\t\t! long" %} 8402 opcode(Assembler::subcc_op3, Assembler::arith_op); 8403 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8404 ins_pipe(ialu_cconly_reg_reg); 8405 %} 8406 8407 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8408 match(Set xcc (CmpL (AndL op1 op2) zero)); 8409 effect( DEF xcc, USE op1, USE op2 ); 8410 8411 size(4); 8412 format %{ "BTST $op1,$op2\t\t! long" %} 8413 opcode(Assembler::andcc_op3, Assembler::arith_op); 8414 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8415 ins_pipe(ialu_cconly_reg_reg); 8416 %} 8417 8418 // useful for checking the alignment of a pointer: 8419 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8420 match(Set xcc (CmpL (AndL op1 con) zero)); 8421 effect( DEF xcc, USE op1, USE con ); 8422 8423 size(4); 8424 format %{ "BTST $op1,$con\t\t! long" %} 8425 opcode(Assembler::andcc_op3, Assembler::arith_op); 8426 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8427 ins_pipe(ialu_cconly_reg_reg); 8428 %} 8429 8430 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ 8431 match(Set icc (CmpU op1 op2)); 8432 8433 size(4); 8434 format %{ "CMP $op1,$op2\t! unsigned" %} 8435 opcode(Assembler::subcc_op3, Assembler::arith_op); 8436 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8437 ins_pipe(ialu_cconly_reg_imm); 8438 %} 8439 8440 // Compare Pointers 8441 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8442 match(Set pcc (CmpP op1 op2)); 8443 8444 size(4); 8445 format %{ "CMP $op1,$op2\t! ptr" %} 8446 opcode(Assembler::subcc_op3, Assembler::arith_op); 8447 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8448 ins_pipe(ialu_cconly_reg_reg); 8449 %} 8450 8451 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8452 match(Set pcc (CmpP op1 op2)); 8453 8454 size(4); 8455 format %{ "CMP $op1,$op2\t! ptr" %} 8456 opcode(Assembler::subcc_op3, Assembler::arith_op); 8457 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8458 ins_pipe(ialu_cconly_reg_imm); 8459 %} 8460 8461 // Compare Narrow oops 8462 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8463 match(Set icc (CmpN op1 op2)); 8464 8465 size(4); 8466 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8467 opcode(Assembler::subcc_op3, Assembler::arith_op); 8468 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8469 ins_pipe(ialu_cconly_reg_reg); 8470 %} 8471 8472 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8473 match(Set icc (CmpN op1 op2)); 8474 8475 size(4); 8476 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8477 opcode(Assembler::subcc_op3, Assembler::arith_op); 8478 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8479 ins_pipe(ialu_cconly_reg_imm); 8480 %} 8481 8482 //----------Max and Min-------------------------------------------------------- 8483 // Min Instructions 8484 // Conditional move for min 8485 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8486 effect( USE_DEF op2, USE op1, USE icc ); 8487 8488 size(4); 8489 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8490 opcode(Assembler::less); 8491 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8492 ins_pipe(ialu_reg_flags); 8493 %} 8494 8495 // Min Register with Register. 8496 instruct minI_eReg(iRegI op1, iRegI op2) %{ 8497 match(Set op2 (MinI op1 op2)); 8498 ins_cost(DEFAULT_COST*2); 8499 expand %{ 8500 flagsReg icc; 8501 compI_iReg(icc,op1,op2); 8502 cmovI_reg_lt(op2,op1,icc); 8503 %} 8504 %} 8505 8506 // Max Instructions 8507 // Conditional move for max 8508 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8509 effect( USE_DEF op2, USE op1, USE icc ); 8510 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8511 opcode(Assembler::greater); 8512 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8513 ins_pipe(ialu_reg_flags); 8514 %} 8515 8516 // Max Register with Register 8517 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8518 match(Set op2 (MaxI op1 op2)); 8519 ins_cost(DEFAULT_COST*2); 8520 expand %{ 8521 flagsReg icc; 8522 compI_iReg(icc,op1,op2); 8523 cmovI_reg_gt(op2,op1,icc); 8524 %} 8525 %} 8526 8527 8528 //----------Float Compares---------------------------------------------------- 8529 // Compare floating, generate condition code 8530 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8531 match(Set fcc (CmpF src1 src2)); 8532 8533 size(4); 8534 format %{ "FCMPs $fcc,$src1,$src2" %} 8535 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8536 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8537 ins_pipe(faddF_fcc_reg_reg_zero); 8538 %} 8539 8540 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8541 match(Set fcc (CmpD src1 src2)); 8542 8543 size(4); 8544 format %{ "FCMPd $fcc,$src1,$src2" %} 8545 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8546 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8547 ins_pipe(faddD_fcc_reg_reg_zero); 8548 %} 8549 8550 8551 // Compare floating, generate -1,0,1 8552 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8553 match(Set dst (CmpF3 src1 src2)); 8554 effect(KILL fcc0); 8555 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8556 format %{ "fcmpl $dst,$src1,$src2" %} 8557 // Primary = float 8558 opcode( true ); 8559 ins_encode( floating_cmp( dst, src1, src2 ) ); 8560 ins_pipe( floating_cmp ); 8561 %} 8562 8563 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8564 match(Set dst (CmpD3 src1 src2)); 8565 effect(KILL fcc0); 8566 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8567 format %{ "dcmpl $dst,$src1,$src2" %} 8568 // Primary = double (not float) 8569 opcode( false ); 8570 ins_encode( floating_cmp( dst, src1, src2 ) ); 8571 ins_pipe( floating_cmp ); 8572 %} 8573 8574 //----------Branches--------------------------------------------------------- 8575 // Jump 8576 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8577 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8578 match(Jump switch_val); 8579 effect(TEMP table); 8580 8581 ins_cost(350); 8582 8583 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 8584 "LD [O7 + $switch_val], O7\n\t" 8585 "JUMP O7" %} 8586 ins_encode %{ 8587 // Calculate table address into a register. 8588 Register table_reg; 8589 Register label_reg = O7; 8590 // If we are calculating the size of this instruction don't trust 8591 // zero offsets because they might change when 8592 // MachConstantBaseNode decides to optimize the constant table 8593 // base. 8594 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { 8595 table_reg = $constanttablebase; 8596 } else { 8597 table_reg = O7; 8598 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 8599 __ add($constanttablebase, con_offset, table_reg); 8600 } 8601 8602 // Jump to base address + switch value 8603 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 8604 __ jmp(label_reg, G0); 8605 __ delayed()->nop(); 8606 %} 8607 ins_pipe(ialu_reg_reg); 8608 %} 8609 8610 // Direct Branch. Use V8 version with longer range. 8611 instruct branch(label labl) %{ 8612 match(Goto); 8613 effect(USE labl); 8614 8615 size(8); 8616 ins_cost(BRANCH_COST); 8617 format %{ "BA $labl" %} 8618 ins_encode %{ 8619 Label* L = $labl$$label; 8620 __ ba(*L); 8621 __ delayed()->nop(); 8622 %} 8623 ins_avoid_back_to_back(AVOID_BEFORE); 8624 ins_pipe(br); 8625 %} 8626 8627 // Direct Branch, short with no delay slot 8628 instruct branch_short(label labl) %{ 8629 match(Goto); 8630 predicate(UseCBCond); 8631 effect(USE labl); 8632 8633 size(4); // Assuming no NOP inserted. 8634 ins_cost(BRANCH_COST); 8635 format %{ "BA $labl\t! short branch" %} 8636 ins_encode %{ 8637 Label* L = $labl$$label; 8638 assert(__ use_cbcond(*L), "back to back cbcond"); 8639 __ ba_short(*L); 8640 %} 8641 ins_short_branch(1); 8642 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 8643 ins_pipe(cbcond_reg_imm); 8644 %} 8645 8646 // Conditional Direct Branch 8647 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8648 match(If cmp icc); 8649 effect(USE labl); 8650 8651 size(8); 8652 ins_cost(BRANCH_COST); 8653 format %{ "BP$cmp $icc,$labl" %} 8654 // Prim = bits 24-22, Secnd = bits 31-30 8655 ins_encode( enc_bp( labl, cmp, icc ) ); 8656 ins_avoid_back_to_back(AVOID_BEFORE); 8657 ins_pipe(br_cc); 8658 %} 8659 8660 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8661 match(If cmp icc); 8662 effect(USE labl); 8663 8664 ins_cost(BRANCH_COST); 8665 format %{ "BP$cmp $icc,$labl" %} 8666 // Prim = bits 24-22, Secnd = bits 31-30 8667 ins_encode( enc_bp( labl, cmp, icc ) ); 8668 ins_avoid_back_to_back(AVOID_BEFORE); 8669 ins_pipe(br_cc); 8670 %} 8671 8672 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 8673 match(If cmp pcc); 8674 effect(USE labl); 8675 8676 size(8); 8677 ins_cost(BRANCH_COST); 8678 format %{ "BP$cmp $pcc,$labl" %} 8679 ins_encode %{ 8680 Label* L = $labl$$label; 8681 Assembler::Predict predict_taken = 8682 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8683 8684 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 8685 __ delayed()->nop(); 8686 %} 8687 ins_avoid_back_to_back(AVOID_BEFORE); 8688 ins_pipe(br_cc); 8689 %} 8690 8691 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 8692 match(If cmp fcc); 8693 effect(USE labl); 8694 8695 size(8); 8696 ins_cost(BRANCH_COST); 8697 format %{ "FBP$cmp $fcc,$labl" %} 8698 ins_encode %{ 8699 Label* L = $labl$$label; 8700 Assembler::Predict predict_taken = 8701 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8702 8703 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 8704 __ delayed()->nop(); 8705 %} 8706 ins_avoid_back_to_back(AVOID_BEFORE); 8707 ins_pipe(br_fcc); 8708 %} 8709 8710 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 8711 match(CountedLoopEnd cmp icc); 8712 effect(USE labl); 8713 8714 size(8); 8715 ins_cost(BRANCH_COST); 8716 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8717 // Prim = bits 24-22, Secnd = bits 31-30 8718 ins_encode( enc_bp( labl, cmp, icc ) ); 8719 ins_avoid_back_to_back(AVOID_BEFORE); 8720 ins_pipe(br_cc); 8721 %} 8722 8723 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8724 match(CountedLoopEnd cmp icc); 8725 effect(USE labl); 8726 8727 size(8); 8728 ins_cost(BRANCH_COST); 8729 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8730 // Prim = bits 24-22, Secnd = bits 31-30 8731 ins_encode( enc_bp( labl, cmp, icc ) ); 8732 ins_avoid_back_to_back(AVOID_BEFORE); 8733 ins_pipe(br_cc); 8734 %} 8735 8736 // Compare and branch instructions 8737 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 8738 match(If cmp (CmpI op1 op2)); 8739 effect(USE labl, KILL icc); 8740 8741 size(12); 8742 ins_cost(BRANCH_COST); 8743 format %{ "CMP $op1,$op2\t! int\n\t" 8744 "BP$cmp $labl" %} 8745 ins_encode %{ 8746 Label* L = $labl$$label; 8747 Assembler::Predict predict_taken = 8748 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8749 __ cmp($op1$$Register, $op2$$Register); 8750 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8751 __ delayed()->nop(); 8752 %} 8753 ins_pipe(cmp_br_reg_reg); 8754 %} 8755 8756 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 8757 match(If cmp (CmpI op1 op2)); 8758 effect(USE labl, KILL icc); 8759 8760 size(12); 8761 ins_cost(BRANCH_COST); 8762 format %{ "CMP $op1,$op2\t! int\n\t" 8763 "BP$cmp $labl" %} 8764 ins_encode %{ 8765 Label* L = $labl$$label; 8766 Assembler::Predict predict_taken = 8767 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8768 __ cmp($op1$$Register, $op2$$constant); 8769 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8770 __ delayed()->nop(); 8771 %} 8772 ins_pipe(cmp_br_reg_imm); 8773 %} 8774 8775 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 8776 match(If cmp (CmpU op1 op2)); 8777 effect(USE labl, KILL icc); 8778 8779 size(12); 8780 ins_cost(BRANCH_COST); 8781 format %{ "CMP $op1,$op2\t! unsigned\n\t" 8782 "BP$cmp $labl" %} 8783 ins_encode %{ 8784 Label* L = $labl$$label; 8785 Assembler::Predict predict_taken = 8786 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8787 __ cmp($op1$$Register, $op2$$Register); 8788 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8789 __ delayed()->nop(); 8790 %} 8791 ins_pipe(cmp_br_reg_reg); 8792 %} 8793 8794 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 8795 match(If cmp (CmpU op1 op2)); 8796 effect(USE labl, KILL icc); 8797 8798 size(12); 8799 ins_cost(BRANCH_COST); 8800 format %{ "CMP $op1,$op2\t! unsigned\n\t" 8801 "BP$cmp $labl" %} 8802 ins_encode %{ 8803 Label* L = $labl$$label; 8804 Assembler::Predict predict_taken = 8805 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8806 __ cmp($op1$$Register, $op2$$constant); 8807 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8808 __ delayed()->nop(); 8809 %} 8810 ins_pipe(cmp_br_reg_imm); 8811 %} 8812 8813 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 8814 match(If cmp (CmpL op1 op2)); 8815 effect(USE labl, KILL xcc); 8816 8817 size(12); 8818 ins_cost(BRANCH_COST); 8819 format %{ "CMP $op1,$op2\t! long\n\t" 8820 "BP$cmp $labl" %} 8821 ins_encode %{ 8822 Label* L = $labl$$label; 8823 Assembler::Predict predict_taken = 8824 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8825 __ cmp($op1$$Register, $op2$$Register); 8826 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 8827 __ delayed()->nop(); 8828 %} 8829 ins_pipe(cmp_br_reg_reg); 8830 %} 8831 8832 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 8833 match(If cmp (CmpL op1 op2)); 8834 effect(USE labl, KILL xcc); 8835 8836 size(12); 8837 ins_cost(BRANCH_COST); 8838 format %{ "CMP $op1,$op2\t! long\n\t" 8839 "BP$cmp $labl" %} 8840 ins_encode %{ 8841 Label* L = $labl$$label; 8842 Assembler::Predict predict_taken = 8843 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8844 __ cmp($op1$$Register, $op2$$constant); 8845 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 8846 __ delayed()->nop(); 8847 %} 8848 ins_pipe(cmp_br_reg_imm); 8849 %} 8850 8851 // Compare Pointers and branch 8852 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 8853 match(If cmp (CmpP op1 op2)); 8854 effect(USE labl, KILL pcc); 8855 8856 size(12); 8857 ins_cost(BRANCH_COST); 8858 format %{ "CMP $op1,$op2\t! ptr\n\t" 8859 "B$cmp $labl" %} 8860 ins_encode %{ 8861 Label* L = $labl$$label; 8862 Assembler::Predict predict_taken = 8863 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8864 __ cmp($op1$$Register, $op2$$Register); 8865 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 8866 __ delayed()->nop(); 8867 %} 8868 ins_pipe(cmp_br_reg_reg); 8869 %} 8870 8871 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 8872 match(If cmp (CmpP op1 null)); 8873 effect(USE labl, KILL pcc); 8874 8875 size(12); 8876 ins_cost(BRANCH_COST); 8877 format %{ "CMP $op1,0\t! ptr\n\t" 8878 "B$cmp $labl" %} 8879 ins_encode %{ 8880 Label* L = $labl$$label; 8881 Assembler::Predict predict_taken = 8882 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8883 __ cmp($op1$$Register, G0); 8884 // bpr() is not used here since it has shorter distance. 8885 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 8886 __ delayed()->nop(); 8887 %} 8888 ins_pipe(cmp_br_reg_reg); 8889 %} 8890 8891 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 8892 match(If cmp (CmpN op1 op2)); 8893 effect(USE labl, KILL icc); 8894 8895 size(12); 8896 ins_cost(BRANCH_COST); 8897 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 8898 "BP$cmp $labl" %} 8899 ins_encode %{ 8900 Label* L = $labl$$label; 8901 Assembler::Predict predict_taken = 8902 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8903 __ cmp($op1$$Register, $op2$$Register); 8904 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8905 __ delayed()->nop(); 8906 %} 8907 ins_pipe(cmp_br_reg_reg); 8908 %} 8909 8910 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 8911 match(If cmp (CmpN op1 null)); 8912 effect(USE labl, KILL icc); 8913 8914 size(12); 8915 ins_cost(BRANCH_COST); 8916 format %{ "CMP $op1,0\t! compressed ptr\n\t" 8917 "BP$cmp $labl" %} 8918 ins_encode %{ 8919 Label* L = $labl$$label; 8920 Assembler::Predict predict_taken = 8921 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8922 __ cmp($op1$$Register, G0); 8923 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8924 __ delayed()->nop(); 8925 %} 8926 ins_pipe(cmp_br_reg_reg); 8927 %} 8928 8929 // Loop back branch 8930 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 8931 match(CountedLoopEnd cmp (CmpI op1 op2)); 8932 effect(USE labl, KILL icc); 8933 8934 size(12); 8935 ins_cost(BRANCH_COST); 8936 format %{ "CMP $op1,$op2\t! int\n\t" 8937 "BP$cmp $labl\t! Loop end" %} 8938 ins_encode %{ 8939 Label* L = $labl$$label; 8940 Assembler::Predict predict_taken = 8941 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8942 __ cmp($op1$$Register, $op2$$Register); 8943 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8944 __ delayed()->nop(); 8945 %} 8946 ins_pipe(cmp_br_reg_reg); 8947 %} 8948 8949 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 8950 match(CountedLoopEnd cmp (CmpI op1 op2)); 8951 effect(USE labl, KILL icc); 8952 8953 size(12); 8954 ins_cost(BRANCH_COST); 8955 format %{ "CMP $op1,$op2\t! int\n\t" 8956 "BP$cmp $labl\t! Loop end" %} 8957 ins_encode %{ 8958 Label* L = $labl$$label; 8959 Assembler::Predict predict_taken = 8960 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8961 __ cmp($op1$$Register, $op2$$constant); 8962 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8963 __ delayed()->nop(); 8964 %} 8965 ins_pipe(cmp_br_reg_imm); 8966 %} 8967 8968 // Short compare and branch instructions 8969 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 8970 match(If cmp (CmpI op1 op2)); 8971 predicate(UseCBCond); 8972 effect(USE labl, KILL icc); 8973 8974 size(4); // Assuming no NOP inserted. 8975 ins_cost(BRANCH_COST); 8976 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 8977 ins_encode %{ 8978 Label* L = $labl$$label; 8979 assert(__ use_cbcond(*L), "back to back cbcond"); 8980 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 8981 %} 8982 ins_short_branch(1); 8983 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 8984 ins_pipe(cbcond_reg_reg); 8985 %} 8986 8987 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 8988 match(If cmp (CmpI op1 op2)); 8989 predicate(UseCBCond); 8990 effect(USE labl, KILL icc); 8991 8992 size(4); // Assuming no NOP inserted. 8993 ins_cost(BRANCH_COST); 8994 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 8995 ins_encode %{ 8996 Label* L = $labl$$label; 8997 assert(__ use_cbcond(*L), "back to back cbcond"); 8998 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 8999 %} 9000 ins_short_branch(1); 9001 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9002 ins_pipe(cbcond_reg_imm); 9003 %} 9004 9005 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9006 match(If cmp (CmpU op1 op2)); 9007 predicate(UseCBCond); 9008 effect(USE labl, KILL icc); 9009 9010 size(4); // Assuming no NOP inserted. 9011 ins_cost(BRANCH_COST); 9012 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9013 ins_encode %{ 9014 Label* L = $labl$$label; 9015 assert(__ use_cbcond(*L), "back to back cbcond"); 9016 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9017 %} 9018 ins_short_branch(1); 9019 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9020 ins_pipe(cbcond_reg_reg); 9021 %} 9022 9023 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9024 match(If cmp (CmpU op1 op2)); 9025 predicate(UseCBCond); 9026 effect(USE labl, KILL icc); 9027 9028 size(4); // Assuming no NOP inserted. 9029 ins_cost(BRANCH_COST); 9030 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9031 ins_encode %{ 9032 Label* L = $labl$$label; 9033 assert(__ use_cbcond(*L), "back to back cbcond"); 9034 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9035 %} 9036 ins_short_branch(1); 9037 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9038 ins_pipe(cbcond_reg_imm); 9039 %} 9040 9041 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9042 match(If cmp (CmpL op1 op2)); 9043 predicate(UseCBCond); 9044 effect(USE labl, KILL xcc); 9045 9046 size(4); // Assuming no NOP inserted. 9047 ins_cost(BRANCH_COST); 9048 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9049 ins_encode %{ 9050 Label* L = $labl$$label; 9051 assert(__ use_cbcond(*L), "back to back cbcond"); 9052 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9053 %} 9054 ins_short_branch(1); 9055 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9056 ins_pipe(cbcond_reg_reg); 9057 %} 9058 9059 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9060 match(If cmp (CmpL op1 op2)); 9061 predicate(UseCBCond); 9062 effect(USE labl, KILL xcc); 9063 9064 size(4); // Assuming no NOP inserted. 9065 ins_cost(BRANCH_COST); 9066 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9067 ins_encode %{ 9068 Label* L = $labl$$label; 9069 assert(__ use_cbcond(*L), "back to back cbcond"); 9070 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9071 %} 9072 ins_short_branch(1); 9073 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9074 ins_pipe(cbcond_reg_imm); 9075 %} 9076 9077 // Compare Pointers and branch 9078 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9079 match(If cmp (CmpP op1 op2)); 9080 predicate(UseCBCond); 9081 effect(USE labl, KILL pcc); 9082 9083 size(4); // Assuming no NOP inserted. 9084 ins_cost(BRANCH_COST); 9085 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9086 ins_encode %{ 9087 Label* L = $labl$$label; 9088 assert(__ use_cbcond(*L), "back to back cbcond"); 9089 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9090 %} 9091 ins_short_branch(1); 9092 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9093 ins_pipe(cbcond_reg_reg); 9094 %} 9095 9096 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9097 match(If cmp (CmpP op1 null)); 9098 predicate(UseCBCond); 9099 effect(USE labl, KILL pcc); 9100 9101 size(4); // Assuming no NOP inserted. 9102 ins_cost(BRANCH_COST); 9103 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9104 ins_encode %{ 9105 Label* L = $labl$$label; 9106 assert(__ use_cbcond(*L), "back to back cbcond"); 9107 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9108 %} 9109 ins_short_branch(1); 9110 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9111 ins_pipe(cbcond_reg_reg); 9112 %} 9113 9114 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9115 match(If cmp (CmpN op1 op2)); 9116 predicate(UseCBCond); 9117 effect(USE labl, KILL icc); 9118 9119 size(4); // Assuming no NOP inserted. 9120 ins_cost(BRANCH_COST); 9121 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %} 9122 ins_encode %{ 9123 Label* L = $labl$$label; 9124 assert(__ use_cbcond(*L), "back to back cbcond"); 9125 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9126 %} 9127 ins_short_branch(1); 9128 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9129 ins_pipe(cbcond_reg_reg); 9130 %} 9131 9132 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9133 match(If cmp (CmpN op1 null)); 9134 predicate(UseCBCond); 9135 effect(USE labl, KILL icc); 9136 9137 size(4); // Assuming no NOP inserted. 9138 ins_cost(BRANCH_COST); 9139 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9140 ins_encode %{ 9141 Label* L = $labl$$label; 9142 assert(__ use_cbcond(*L), "back to back cbcond"); 9143 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9144 %} 9145 ins_short_branch(1); 9146 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9147 ins_pipe(cbcond_reg_reg); 9148 %} 9149 9150 // Loop back branch 9151 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9152 match(CountedLoopEnd cmp (CmpI op1 op2)); 9153 predicate(UseCBCond); 9154 effect(USE labl, KILL icc); 9155 9156 size(4); // Assuming no NOP inserted. 9157 ins_cost(BRANCH_COST); 9158 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9159 ins_encode %{ 9160 Label* L = $labl$$label; 9161 assert(__ use_cbcond(*L), "back to back cbcond"); 9162 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9163 %} 9164 ins_short_branch(1); 9165 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9166 ins_pipe(cbcond_reg_reg); 9167 %} 9168 9169 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9170 match(CountedLoopEnd cmp (CmpI op1 op2)); 9171 predicate(UseCBCond); 9172 effect(USE labl, KILL icc); 9173 9174 size(4); // Assuming no NOP inserted. 9175 ins_cost(BRANCH_COST); 9176 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9177 ins_encode %{ 9178 Label* L = $labl$$label; 9179 assert(__ use_cbcond(*L), "back to back cbcond"); 9180 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9181 %} 9182 ins_short_branch(1); 9183 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9184 ins_pipe(cbcond_reg_imm); 9185 %} 9186 9187 // Branch-on-register tests all 64 bits. We assume that values 9188 // in 64-bit registers always remains zero or sign extended 9189 // unless our code munges the high bits. Interrupts can chop 9190 // the high order bits to zero or sign at any time. 9191 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9192 match(If cmp (CmpI op1 zero)); 9193 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9194 effect(USE labl); 9195 9196 size(8); 9197 ins_cost(BRANCH_COST); 9198 format %{ "BR$cmp $op1,$labl" %} 9199 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9200 ins_avoid_back_to_back(AVOID_BEFORE); 9201 ins_pipe(br_reg); 9202 %} 9203 9204 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9205 match(If cmp (CmpP op1 null)); 9206 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9207 effect(USE labl); 9208 9209 size(8); 9210 ins_cost(BRANCH_COST); 9211 format %{ "BR$cmp $op1,$labl" %} 9212 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9213 ins_avoid_back_to_back(AVOID_BEFORE); 9214 ins_pipe(br_reg); 9215 %} 9216 9217 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9218 match(If cmp (CmpL op1 zero)); 9219 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9220 effect(USE labl); 9221 9222 size(8); 9223 ins_cost(BRANCH_COST); 9224 format %{ "BR$cmp $op1,$labl" %} 9225 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9226 ins_avoid_back_to_back(AVOID_BEFORE); 9227 ins_pipe(br_reg); 9228 %} 9229 9230 9231 // ============================================================================ 9232 // Long Compare 9233 // 9234 // Currently we hold longs in 2 registers. Comparing such values efficiently 9235 // is tricky. The flavor of compare used depends on whether we are testing 9236 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9237 // The GE test is the negated LT test. The LE test can be had by commuting 9238 // the operands (yielding a GE test) and then negating; negate again for the 9239 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9240 // NE test is negated from that. 9241 9242 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9243 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9244 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9245 // are collapsed internally in the ADLC's dfa-gen code. The match for 9246 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9247 // foo match ends up with the wrong leaf. One fix is to not match both 9248 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9249 // both forms beat the trinary form of long-compare and both are very useful 9250 // on Intel which has so few registers. 9251 9252 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9253 match(If cmp xcc); 9254 effect(USE labl); 9255 9256 size(8); 9257 ins_cost(BRANCH_COST); 9258 format %{ "BP$cmp $xcc,$labl" %} 9259 ins_encode %{ 9260 Label* L = $labl$$label; 9261 Assembler::Predict predict_taken = 9262 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9263 9264 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9265 __ delayed()->nop(); 9266 %} 9267 ins_avoid_back_to_back(AVOID_BEFORE); 9268 ins_pipe(br_cc); 9269 %} 9270 9271 // Manifest a CmpL3 result in an integer register. Very painful. 9272 // This is the test to avoid. 9273 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9274 match(Set dst (CmpL3 src1 src2) ); 9275 effect( KILL ccr ); 9276 ins_cost(6*DEFAULT_COST); 9277 size(24); 9278 format %{ "CMP $src1,$src2\t\t! long\n" 9279 "\tBLT,a,pn done\n" 9280 "\tMOV -1,$dst\t! delay slot\n" 9281 "\tBGT,a,pn done\n" 9282 "\tMOV 1,$dst\t! delay slot\n" 9283 "\tCLR $dst\n" 9284 "done:" %} 9285 ins_encode( cmpl_flag(src1,src2,dst) ); 9286 ins_pipe(cmpL_reg); 9287 %} 9288 9289 // Conditional move 9290 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9291 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9292 ins_cost(150); 9293 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9294 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9295 ins_pipe(ialu_reg); 9296 %} 9297 9298 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9299 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9300 ins_cost(140); 9301 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9302 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9303 ins_pipe(ialu_imm); 9304 %} 9305 9306 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9307 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9308 ins_cost(150); 9309 format %{ "MOV$cmp $xcc,$src,$dst" %} 9310 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9311 ins_pipe(ialu_reg); 9312 %} 9313 9314 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9315 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9316 ins_cost(140); 9317 format %{ "MOV$cmp $xcc,$src,$dst" %} 9318 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9319 ins_pipe(ialu_imm); 9320 %} 9321 9322 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9323 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9324 ins_cost(150); 9325 format %{ "MOV$cmp $xcc,$src,$dst" %} 9326 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9327 ins_pipe(ialu_reg); 9328 %} 9329 9330 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9331 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9332 ins_cost(150); 9333 format %{ "MOV$cmp $xcc,$src,$dst" %} 9334 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9335 ins_pipe(ialu_reg); 9336 %} 9337 9338 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9339 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9340 ins_cost(140); 9341 format %{ "MOV$cmp $xcc,$src,$dst" %} 9342 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9343 ins_pipe(ialu_imm); 9344 %} 9345 9346 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9347 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9348 ins_cost(150); 9349 opcode(0x101); 9350 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9351 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9352 ins_pipe(int_conditional_float_move); 9353 %} 9354 9355 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9356 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9357 ins_cost(150); 9358 opcode(0x102); 9359 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9360 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9361 ins_pipe(int_conditional_float_move); 9362 %} 9363 9364 // ============================================================================ 9365 // Safepoint Instruction 9366 instruct safePoint_poll(iRegP poll) %{ 9367 match(SafePoint poll); 9368 effect(USE poll); 9369 9370 size(4); 9371 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9372 ins_encode %{ 9373 __ relocate(relocInfo::poll_type); 9374 __ ld_ptr($poll$$Register, 0, G0); 9375 %} 9376 ins_pipe(loadPollP); 9377 %} 9378 9379 // ============================================================================ 9380 // Call Instructions 9381 // Call Java Static Instruction 9382 instruct CallStaticJavaDirect( method meth ) %{ 9383 match(CallStaticJava); 9384 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9385 effect(USE meth); 9386 9387 size(8); 9388 ins_cost(CALL_COST); 9389 format %{ "CALL,static ; NOP ==> " %} 9390 ins_encode( Java_Static_Call( meth ), call_epilog ); 9391 ins_avoid_back_to_back(AVOID_BEFORE); 9392 ins_pipe(simple_call); 9393 %} 9394 9395 // Call Java Static Instruction (method handle version) 9396 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9397 match(CallStaticJava); 9398 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9399 effect(USE meth, KILL l7_mh_SP_save); 9400 9401 size(16); 9402 ins_cost(CALL_COST); 9403 format %{ "CALL,static/MethodHandle" %} 9404 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9405 ins_pipe(simple_call); 9406 %} 9407 9408 // Call Java Dynamic Instruction 9409 instruct CallDynamicJavaDirect( method meth ) %{ 9410 match(CallDynamicJava); 9411 effect(USE meth); 9412 9413 ins_cost(CALL_COST); 9414 format %{ "SET (empty),R_G5\n\t" 9415 "CALL,dynamic ; NOP ==> " %} 9416 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9417 ins_pipe(call); 9418 %} 9419 9420 // Call Runtime Instruction 9421 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9422 match(CallRuntime); 9423 effect(USE meth, KILL l7); 9424 ins_cost(CALL_COST); 9425 format %{ "CALL,runtime" %} 9426 ins_encode( Java_To_Runtime( meth ), 9427 call_epilog, adjust_long_from_native_call ); 9428 ins_avoid_back_to_back(AVOID_BEFORE); 9429 ins_pipe(simple_call); 9430 %} 9431 9432 // Call runtime without safepoint - same as CallRuntime 9433 instruct CallLeafDirect(method meth, l7RegP l7) %{ 9434 match(CallLeaf); 9435 effect(USE meth, KILL l7); 9436 ins_cost(CALL_COST); 9437 format %{ "CALL,runtime leaf" %} 9438 ins_encode( Java_To_Runtime( meth ), 9439 call_epilog, 9440 adjust_long_from_native_call ); 9441 ins_avoid_back_to_back(AVOID_BEFORE); 9442 ins_pipe(simple_call); 9443 %} 9444 9445 // Call runtime without safepoint - same as CallLeaf 9446 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9447 match(CallLeafNoFP); 9448 effect(USE meth, KILL l7); 9449 ins_cost(CALL_COST); 9450 format %{ "CALL,runtime leaf nofp" %} 9451 ins_encode( Java_To_Runtime( meth ), 9452 call_epilog, 9453 adjust_long_from_native_call ); 9454 ins_avoid_back_to_back(AVOID_BEFORE); 9455 ins_pipe(simple_call); 9456 %} 9457 9458 // Tail Call; Jump from runtime stub to Java code. 9459 // Also known as an 'interprocedural jump'. 9460 // Target of jump will eventually return to caller. 9461 // TailJump below removes the return address. 9462 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9463 match(TailCall jump_target method_oop ); 9464 9465 ins_cost(CALL_COST); 9466 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9467 ins_encode(form_jmpl(jump_target)); 9468 ins_avoid_back_to_back(AVOID_BEFORE); 9469 ins_pipe(tail_call); 9470 %} 9471 9472 9473 // Return Instruction 9474 instruct Ret() %{ 9475 match(Return); 9476 9477 // The epilogue node did the ret already. 9478 size(0); 9479 format %{ "! return" %} 9480 ins_encode(); 9481 ins_pipe(empty); 9482 %} 9483 9484 9485 // Tail Jump; remove the return address; jump to target. 9486 // TailCall above leaves the return address around. 9487 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9488 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9489 // "restore" before this instruction (in Epilogue), we need to materialize it 9490 // in %i0. 9491 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9492 match( TailJump jump_target ex_oop ); 9493 ins_cost(CALL_COST); 9494 format %{ "! discard R_O7\n\t" 9495 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9496 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9497 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9498 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9499 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9500 ins_avoid_back_to_back(AVOID_BEFORE); 9501 ins_pipe(tail_call); 9502 %} 9503 9504 // Create exception oop: created by stack-crawling runtime code. 9505 // Created exception is now available to this handler, and is setup 9506 // just prior to jumping to this handler. No code emitted. 9507 instruct CreateException( o0RegP ex_oop ) 9508 %{ 9509 match(Set ex_oop (CreateEx)); 9510 ins_cost(0); 9511 9512 size(0); 9513 // use the following format syntax 9514 format %{ "! exception oop is in R_O0; no code emitted" %} 9515 ins_encode(); 9516 ins_pipe(empty); 9517 %} 9518 9519 9520 // Rethrow exception: 9521 // The exception oop will come in the first argument position. 9522 // Then JUMP (not call) to the rethrow stub code. 9523 instruct RethrowException() 9524 %{ 9525 match(Rethrow); 9526 ins_cost(CALL_COST); 9527 9528 // use the following format syntax 9529 format %{ "Jmp rethrow_stub" %} 9530 ins_encode(enc_rethrow); 9531 ins_avoid_back_to_back(AVOID_BEFORE); 9532 ins_pipe(tail_call); 9533 %} 9534 9535 9536 // Die now 9537 instruct ShouldNotReachHere( ) 9538 %{ 9539 match(Halt); 9540 ins_cost(CALL_COST); 9541 9542 size(4); 9543 // Use the following format syntax 9544 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9545 ins_encode( form2_illtrap() ); 9546 ins_pipe(tail_call); 9547 %} 9548 9549 // ============================================================================ 9550 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9551 // array for an instance of the superklass. Set a hidden internal cache on a 9552 // hit (cache is checked with exposed code in gen_subtype_check()). Return 9553 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9554 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9555 match(Set index (PartialSubtypeCheck sub super)); 9556 effect( KILL pcc, KILL o7 ); 9557 ins_cost(DEFAULT_COST*10); 9558 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9559 ins_encode( enc_PartialSubtypeCheck() ); 9560 ins_avoid_back_to_back(AVOID_BEFORE); 9561 ins_pipe(partial_subtype_check_pipe); 9562 %} 9563 9564 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9565 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9566 effect( KILL idx, KILL o7 ); 9567 ins_cost(DEFAULT_COST*10); 9568 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9569 ins_encode( enc_PartialSubtypeCheck() ); 9570 ins_avoid_back_to_back(AVOID_BEFORE); 9571 ins_pipe(partial_subtype_check_pipe); 9572 %} 9573 9574 9575 // ============================================================================ 9576 // inlined locking and unlocking 9577 9578 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 9579 match(Set pcc (FastLock object box)); 9580 9581 effect(TEMP scratch2, USE_KILL box, KILL scratch); 9582 ins_cost(100); 9583 9584 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 9585 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9586 ins_pipe(long_memory_op); 9587 %} 9588 9589 9590 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 9591 match(Set pcc (FastUnlock object box)); 9592 effect(TEMP scratch2, USE_KILL box, KILL scratch); 9593 ins_cost(100); 9594 9595 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 9596 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9597 ins_pipe(long_memory_op); 9598 %} 9599 9600 // The encodings are generic. 9601 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9602 predicate(!use_block_zeroing(n->in(2)) ); 9603 match(Set dummy (ClearArray cnt base)); 9604 effect(TEMP temp, KILL ccr); 9605 ins_cost(300); 9606 format %{ "MOV $cnt,$temp\n" 9607 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9608 " BRge loop\t\t! Clearing loop\n" 9609 " STX G0,[$base+$temp]\t! delay slot" %} 9610 9611 ins_encode %{ 9612 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 9613 Register nof_bytes_arg = $cnt$$Register; 9614 Register nof_bytes_tmp = $temp$$Register; 9615 Register base_pointer_arg = $base$$Register; 9616 9617 Label loop; 9618 __ mov(nof_bytes_arg, nof_bytes_tmp); 9619 9620 // Loop and clear, walking backwards through the array. 9621 // nof_bytes_tmp (if >0) is always the number of bytes to zero 9622 __ bind(loop); 9623 __ deccc(nof_bytes_tmp, 8); 9624 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 9625 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 9626 // %%%% this mini-loop must not cross a cache boundary! 9627 %} 9628 ins_pipe(long_memory_op); 9629 %} 9630 9631 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ 9632 predicate(use_block_zeroing(n->in(2))); 9633 match(Set dummy (ClearArray cnt base)); 9634 effect(USE_KILL cnt, USE_KILL base, KILL ccr); 9635 ins_cost(300); 9636 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 9637 9638 ins_encode %{ 9639 9640 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 9641 Register to = $base$$Register; 9642 Register count = $cnt$$Register; 9643 9644 Label Ldone; 9645 __ nop(); // Separate short branches 9646 // Use BIS for zeroing (temp is not used). 9647 __ bis_zeroing(to, count, G0, Ldone); 9648 __ bind(Ldone); 9649 9650 %} 9651 ins_pipe(long_memory_op); 9652 %} 9653 9654 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ 9655 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); 9656 match(Set dummy (ClearArray cnt base)); 9657 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); 9658 ins_cost(300); 9659 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 9660 9661 ins_encode %{ 9662 9663 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 9664 Register to = $base$$Register; 9665 Register count = $cnt$$Register; 9666 Register temp = $tmp$$Register; 9667 9668 Label Ldone; 9669 __ nop(); // Separate short branches 9670 // Use BIS for zeroing 9671 __ bis_zeroing(to, count, temp, Ldone); 9672 __ bind(Ldone); 9673 9674 %} 9675 ins_pipe(long_memory_op); 9676 %} 9677 9678 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9679 o7RegI tmp, flagsReg ccr) %{ 9680 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 9681 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9682 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9683 ins_cost(300); 9684 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9685 ins_encode %{ 9686 __ string_compare($str1$$Register, $str2$$Register, 9687 $cnt1$$Register, $cnt2$$Register, 9688 $tmp$$Register, $tmp$$Register, 9689 $result$$Register, StrIntrinsicNode::LL); 9690 %} 9691 ins_pipe(long_memory_op); 9692 %} 9693 9694 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9695 o7RegI tmp, flagsReg ccr) %{ 9696 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU); 9697 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9698 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9699 ins_cost(300); 9700 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9701 ins_encode %{ 9702 __ string_compare($str1$$Register, $str2$$Register, 9703 $cnt1$$Register, $cnt2$$Register, 9704 $tmp$$Register, $tmp$$Register, 9705 $result$$Register, StrIntrinsicNode::UU); 9706 %} 9707 ins_pipe(long_memory_op); 9708 %} 9709 9710 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9711 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 9712 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 9713 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9714 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 9715 ins_cost(300); 9716 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 9717 ins_encode %{ 9718 __ string_compare($str1$$Register, $str2$$Register, 9719 $cnt1$$Register, $cnt2$$Register, 9720 $tmp1$$Register, $tmp2$$Register, 9721 $result$$Register, StrIntrinsicNode::LU); 9722 %} 9723 ins_pipe(long_memory_op); 9724 %} 9725 9726 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9727 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 9728 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 9729 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9730 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 9731 ins_cost(300); 9732 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 9733 ins_encode %{ 9734 __ string_compare($str2$$Register, $str1$$Register, 9735 $cnt2$$Register, $cnt1$$Register, 9736 $tmp1$$Register, $tmp2$$Register, 9737 $result$$Register, StrIntrinsicNode::UL); 9738 %} 9739 ins_pipe(long_memory_op); 9740 %} 9741 9742 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9743 o7RegI tmp, flagsReg ccr) %{ 9744 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 9745 match(Set result (StrEquals (Binary str1 str2) cnt)); 9746 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9747 ins_cost(300); 9748 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 9749 ins_encode %{ 9750 __ array_equals(false, $str1$$Register, $str2$$Register, 9751 $cnt$$Register, $tmp$$Register, 9752 $result$$Register, true /* byte */); 9753 %} 9754 ins_pipe(long_memory_op); 9755 %} 9756 9757 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9758 o7RegI tmp, flagsReg ccr) %{ 9759 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 9760 match(Set result (StrEquals (Binary str1 str2) cnt)); 9761 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9762 ins_cost(300); 9763 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 9764 ins_encode %{ 9765 __ array_equals(false, $str1$$Register, $str2$$Register, 9766 $cnt$$Register, $tmp$$Register, 9767 $result$$Register, false /* byte */); 9768 %} 9769 ins_pipe(long_memory_op); 9770 %} 9771 9772 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9773 o7RegI tmp2, flagsReg ccr) %{ 9774 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 9775 match(Set result (AryEq ary1 ary2)); 9776 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9777 ins_cost(300); 9778 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9779 ins_encode %{ 9780 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9781 $tmp1$$Register, $tmp2$$Register, 9782 $result$$Register, true /* byte */); 9783 %} 9784 ins_pipe(long_memory_op); 9785 %} 9786 9787 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9788 o7RegI tmp2, flagsReg ccr) %{ 9789 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 9790 match(Set result (AryEq ary1 ary2)); 9791 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9792 ins_cost(300); 9793 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9794 ins_encode %{ 9795 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9796 $tmp1$$Register, $tmp2$$Register, 9797 $result$$Register, false /* byte */); 9798 %} 9799 ins_pipe(long_memory_op); 9800 %} 9801 9802 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR, 9803 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L, 9804 flagsReg ccr) 9805 %{ 9806 match(Set resultR (HasNegatives pAryR iSizeR)); 9807 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr); 9808 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %} 9809 ins_encode %{ 9810 __ has_negatives($pAryR$$Register, $iSizeR$$Register, 9811 $resultR$$Register, 9812 $tmp1L$$Register, $tmp2L$$Register, 9813 $tmp3L$$Register, $tmp4L$$Register); 9814 %} 9815 ins_pipe(long_memory_op); 9816 %} 9817 9818 // char[] to byte[] compression 9819 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{ 9820 predicate(UseVIS < 3); 9821 match(Set result (StrCompressedCopy src (Binary dst len))); 9822 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 9823 ins_cost(300); 9824 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %} 9825 ins_encode %{ 9826 Label Ldone; 9827 __ signx($len$$Register); 9828 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn); 9829 __ delayed()->mov($len$$Register, $result$$Register); // copy count 9830 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone); 9831 __ bind(Ldone); 9832 %} 9833 ins_pipe(long_memory_op); 9834 %} 9835 9836 // fast char[] to byte[] compression using VIS instructions 9837 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, 9838 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4, 9839 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{ 9840 predicate(UseVIS >= 3); 9841 match(Set result (StrCompressedCopy src (Binary dst len))); 9842 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 9843 ins_cost(300); 9844 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %} 9845 ins_encode %{ 9846 Label Ldone; 9847 __ signx($len$$Register); 9848 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register, 9849 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, 9850 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone); 9851 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 9852 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone); 9853 __ bind(Ldone); 9854 %} 9855 ins_pipe(long_memory_op); 9856 %} 9857 9858 // byte[] to char[] inflation 9859 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 9860 iRegL tmp, flagsReg ccr) %{ 9861 match(Set dummy (StrInflatedCopy src (Binary dst len))); 9862 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 9863 ins_cost(300); 9864 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %} 9865 ins_encode %{ 9866 Label Ldone; 9867 __ signx($len$$Register); 9868 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 9869 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 9870 __ bind(Ldone); 9871 %} 9872 ins_pipe(long_memory_op); 9873 %} 9874 9875 // fast byte[] to char[] inflation using VIS instructions 9876 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 9877 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{ 9878 predicate(UseVIS >= 3); 9879 match(Set dummy (StrInflatedCopy src (Binary dst len))); 9880 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 9881 ins_cost(300); 9882 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %} 9883 ins_encode %{ 9884 Label Ldone; 9885 __ signx($len$$Register); 9886 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, 9887 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone); 9888 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 9889 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 9890 __ bind(Ldone); 9891 %} 9892 ins_pipe(long_memory_op); 9893 %} 9894 9895 9896 //---------- Zeros Count Instructions ------------------------------------------ 9897 9898 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ 9899 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9900 match(Set dst (CountLeadingZerosI src)); 9901 effect(TEMP dst, TEMP tmp, KILL cr); 9902 9903 // x |= (x >> 1); 9904 // x |= (x >> 2); 9905 // x |= (x >> 4); 9906 // x |= (x >> 8); 9907 // x |= (x >> 16); 9908 // return (WORDBITS - popc(x)); 9909 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 9910 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 9911 "OR $dst,$tmp,$dst\n\t" 9912 "SRL $dst,2,$tmp\n\t" 9913 "OR $dst,$tmp,$dst\n\t" 9914 "SRL $dst,4,$tmp\n\t" 9915 "OR $dst,$tmp,$dst\n\t" 9916 "SRL $dst,8,$tmp\n\t" 9917 "OR $dst,$tmp,$dst\n\t" 9918 "SRL $dst,16,$tmp\n\t" 9919 "OR $dst,$tmp,$dst\n\t" 9920 "POPC $dst,$dst\n\t" 9921 "MOV 32,$tmp\n\t" 9922 "SUB $tmp,$dst,$dst" %} 9923 ins_encode %{ 9924 Register Rdst = $dst$$Register; 9925 Register Rsrc = $src$$Register; 9926 Register Rtmp = $tmp$$Register; 9927 __ srl(Rsrc, 1, Rtmp); 9928 __ srl(Rsrc, 0, Rdst); 9929 __ or3(Rdst, Rtmp, Rdst); 9930 __ srl(Rdst, 2, Rtmp); 9931 __ or3(Rdst, Rtmp, Rdst); 9932 __ srl(Rdst, 4, Rtmp); 9933 __ or3(Rdst, Rtmp, Rdst); 9934 __ srl(Rdst, 8, Rtmp); 9935 __ or3(Rdst, Rtmp, Rdst); 9936 __ srl(Rdst, 16, Rtmp); 9937 __ or3(Rdst, Rtmp, Rdst); 9938 __ popc(Rdst, Rdst); 9939 __ mov(BitsPerInt, Rtmp); 9940 __ sub(Rtmp, Rdst, Rdst); 9941 %} 9942 ins_pipe(ialu_reg); 9943 %} 9944 9945 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 9946 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9947 match(Set dst (CountLeadingZerosL src)); 9948 effect(TEMP dst, TEMP tmp, KILL cr); 9949 9950 // x |= (x >> 1); 9951 // x |= (x >> 2); 9952 // x |= (x >> 4); 9953 // x |= (x >> 8); 9954 // x |= (x >> 16); 9955 // x |= (x >> 32); 9956 // return (WORDBITS - popc(x)); 9957 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 9958 "OR $src,$tmp,$dst\n\t" 9959 "SRLX $dst,2,$tmp\n\t" 9960 "OR $dst,$tmp,$dst\n\t" 9961 "SRLX $dst,4,$tmp\n\t" 9962 "OR $dst,$tmp,$dst\n\t" 9963 "SRLX $dst,8,$tmp\n\t" 9964 "OR $dst,$tmp,$dst\n\t" 9965 "SRLX $dst,16,$tmp\n\t" 9966 "OR $dst,$tmp,$dst\n\t" 9967 "SRLX $dst,32,$tmp\n\t" 9968 "OR $dst,$tmp,$dst\n\t" 9969 "POPC $dst,$dst\n\t" 9970 "MOV 64,$tmp\n\t" 9971 "SUB $tmp,$dst,$dst" %} 9972 ins_encode %{ 9973 Register Rdst = $dst$$Register; 9974 Register Rsrc = $src$$Register; 9975 Register Rtmp = $tmp$$Register; 9976 __ srlx(Rsrc, 1, Rtmp); 9977 __ or3( Rsrc, Rtmp, Rdst); 9978 __ srlx(Rdst, 2, Rtmp); 9979 __ or3( Rdst, Rtmp, Rdst); 9980 __ srlx(Rdst, 4, Rtmp); 9981 __ or3( Rdst, Rtmp, Rdst); 9982 __ srlx(Rdst, 8, Rtmp); 9983 __ or3( Rdst, Rtmp, Rdst); 9984 __ srlx(Rdst, 16, Rtmp); 9985 __ or3( Rdst, Rtmp, Rdst); 9986 __ srlx(Rdst, 32, Rtmp); 9987 __ or3( Rdst, Rtmp, Rdst); 9988 __ popc(Rdst, Rdst); 9989 __ mov(BitsPerLong, Rtmp); 9990 __ sub(Rtmp, Rdst, Rdst); 9991 %} 9992 ins_pipe(ialu_reg); 9993 %} 9994 9995 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ 9996 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9997 match(Set dst (CountTrailingZerosI src)); 9998 effect(TEMP dst, KILL cr); 9999 10000 // return popc(~x & (x - 1)); 10001 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 10002 "ANDN $dst,$src,$dst\n\t" 10003 "SRL $dst,R_G0,$dst\n\t" 10004 "POPC $dst,$dst" %} 10005 ins_encode %{ 10006 Register Rdst = $dst$$Register; 10007 Register Rsrc = $src$$Register; 10008 __ sub(Rsrc, 1, Rdst); 10009 __ andn(Rdst, Rsrc, Rdst); 10010 __ srl(Rdst, G0, Rdst); 10011 __ popc(Rdst, Rdst); 10012 %} 10013 ins_pipe(ialu_reg); 10014 %} 10015 10016 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ 10017 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10018 match(Set dst (CountTrailingZerosL src)); 10019 effect(TEMP dst, KILL cr); 10020 10021 // return popc(~x & (x - 1)); 10022 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10023 "ANDN $dst,$src,$dst\n\t" 10024 "POPC $dst,$dst" %} 10025 ins_encode %{ 10026 Register Rdst = $dst$$Register; 10027 Register Rsrc = $src$$Register; 10028 __ sub(Rsrc, 1, Rdst); 10029 __ andn(Rdst, Rsrc, Rdst); 10030 __ popc(Rdst, Rdst); 10031 %} 10032 ins_pipe(ialu_reg); 10033 %} 10034 10035 10036 //---------- Population Count Instructions ------------------------------------- 10037 10038 instruct popCountI(iRegIsafe dst, iRegI src) %{ 10039 predicate(UsePopCountInstruction); 10040 match(Set dst (PopCountI src)); 10041 10042 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" 10043 "POPC $dst, $dst" %} 10044 ins_encode %{ 10045 __ srl($src$$Register, G0, $dst$$Register); 10046 __ popc($dst$$Register, $dst$$Register); 10047 %} 10048 ins_pipe(ialu_reg); 10049 %} 10050 10051 // Note: Long.bitCount(long) returns an int. 10052 instruct popCountL(iRegIsafe dst, iRegL src) %{ 10053 predicate(UsePopCountInstruction); 10054 match(Set dst (PopCountL src)); 10055 10056 format %{ "POPC $src, $dst" %} 10057 ins_encode %{ 10058 __ popc($src$$Register, $dst$$Register); 10059 %} 10060 ins_pipe(ialu_reg); 10061 %} 10062 10063 10064 // ============================================================================ 10065 //------------Bytes reverse-------------------------------------------------- 10066 10067 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10068 match(Set dst (ReverseBytesI src)); 10069 10070 // Op cost is artificially doubled to make sure that load or store 10071 // instructions are preferred over this one which requires a spill 10072 // onto a stack slot. 10073 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10074 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10075 10076 ins_encode %{ 10077 __ set($src$$disp + STACK_BIAS, O7); 10078 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10079 %} 10080 ins_pipe( iload_mem ); 10081 %} 10082 10083 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10084 match(Set dst (ReverseBytesL src)); 10085 10086 // Op cost is artificially doubled to make sure that load or store 10087 // instructions are preferred over this one which requires a spill 10088 // onto a stack slot. 10089 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10090 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10091 10092 ins_encode %{ 10093 __ set($src$$disp + STACK_BIAS, O7); 10094 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10095 %} 10096 ins_pipe( iload_mem ); 10097 %} 10098 10099 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10100 match(Set dst (ReverseBytesUS src)); 10101 10102 // Op cost is artificially doubled to make sure that load or store 10103 // instructions are preferred over this one which requires a spill 10104 // onto a stack slot. 10105 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10106 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10107 10108 ins_encode %{ 10109 // the value was spilled as an int so bias the load 10110 __ set($src$$disp + STACK_BIAS + 2, O7); 10111 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10112 %} 10113 ins_pipe( iload_mem ); 10114 %} 10115 10116 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10117 match(Set dst (ReverseBytesS src)); 10118 10119 // Op cost is artificially doubled to make sure that load or store 10120 // instructions are preferred over this one which requires a spill 10121 // onto a stack slot. 10122 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10123 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10124 10125 ins_encode %{ 10126 // the value was spilled as an int so bias the load 10127 __ set($src$$disp + STACK_BIAS + 2, O7); 10128 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10129 %} 10130 ins_pipe( iload_mem ); 10131 %} 10132 10133 // Load Integer reversed byte order 10134 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10135 match(Set dst (ReverseBytesI (LoadI src))); 10136 10137 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10138 size(4); 10139 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10140 10141 ins_encode %{ 10142 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10143 %} 10144 ins_pipe(iload_mem); 10145 %} 10146 10147 // Load Long - aligned and reversed 10148 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10149 match(Set dst (ReverseBytesL (LoadL src))); 10150 10151 ins_cost(MEMORY_REF_COST); 10152 size(4); 10153 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10154 10155 ins_encode %{ 10156 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10157 %} 10158 ins_pipe(iload_mem); 10159 %} 10160 10161 // Load unsigned short / char reversed byte order 10162 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10163 match(Set dst (ReverseBytesUS (LoadUS src))); 10164 10165 ins_cost(MEMORY_REF_COST); 10166 size(4); 10167 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10168 10169 ins_encode %{ 10170 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10171 %} 10172 ins_pipe(iload_mem); 10173 %} 10174 10175 // Load short reversed byte order 10176 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10177 match(Set dst (ReverseBytesS (LoadS src))); 10178 10179 ins_cost(MEMORY_REF_COST); 10180 size(4); 10181 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10182 10183 ins_encode %{ 10184 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10185 %} 10186 ins_pipe(iload_mem); 10187 %} 10188 10189 // Store Integer reversed byte order 10190 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10191 match(Set dst (StoreI dst (ReverseBytesI src))); 10192 10193 ins_cost(MEMORY_REF_COST); 10194 size(4); 10195 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10196 10197 ins_encode %{ 10198 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10199 %} 10200 ins_pipe(istore_mem_reg); 10201 %} 10202 10203 // Store Long reversed byte order 10204 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10205 match(Set dst (StoreL dst (ReverseBytesL src))); 10206 10207 ins_cost(MEMORY_REF_COST); 10208 size(4); 10209 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10210 10211 ins_encode %{ 10212 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10213 %} 10214 ins_pipe(istore_mem_reg); 10215 %} 10216 10217 // Store unsighed short/char reversed byte order 10218 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10219 match(Set dst (StoreC dst (ReverseBytesUS src))); 10220 10221 ins_cost(MEMORY_REF_COST); 10222 size(4); 10223 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10224 10225 ins_encode %{ 10226 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10227 %} 10228 ins_pipe(istore_mem_reg); 10229 %} 10230 10231 // Store short reversed byte order 10232 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10233 match(Set dst (StoreC dst (ReverseBytesS src))); 10234 10235 ins_cost(MEMORY_REF_COST); 10236 size(4); 10237 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10238 10239 ins_encode %{ 10240 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10241 %} 10242 ins_pipe(istore_mem_reg); 10243 %} 10244 10245 // ====================VECTOR INSTRUCTIONS===================================== 10246 10247 // Load Aligned Packed values into a Double Register 10248 instruct loadV8(regD dst, memory mem) %{ 10249 predicate(n->as_LoadVector()->memory_size() == 8); 10250 match(Set dst (LoadVector mem)); 10251 ins_cost(MEMORY_REF_COST); 10252 size(4); 10253 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} 10254 ins_encode %{ 10255 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); 10256 %} 10257 ins_pipe(floadD_mem); 10258 %} 10259 10260 // Store Vector in Double register to memory 10261 instruct storeV8(memory mem, regD src) %{ 10262 predicate(n->as_StoreVector()->memory_size() == 8); 10263 match(Set mem (StoreVector mem src)); 10264 ins_cost(MEMORY_REF_COST); 10265 size(4); 10266 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} 10267 ins_encode %{ 10268 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); 10269 %} 10270 ins_pipe(fstoreD_mem_reg); 10271 %} 10272 10273 // Store Zero into vector in memory 10274 instruct storeV8B_zero(memory mem, immI0 zero) %{ 10275 predicate(n->as_StoreVector()->memory_size() == 8); 10276 match(Set mem (StoreVector mem (ReplicateB zero))); 10277 ins_cost(MEMORY_REF_COST); 10278 size(4); 10279 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} 10280 ins_encode %{ 10281 __ stx(G0, $mem$$Address); 10282 %} 10283 ins_pipe(fstoreD_mem_zero); 10284 %} 10285 10286 instruct storeV4S_zero(memory mem, immI0 zero) %{ 10287 predicate(n->as_StoreVector()->memory_size() == 8); 10288 match(Set mem (StoreVector mem (ReplicateS zero))); 10289 ins_cost(MEMORY_REF_COST); 10290 size(4); 10291 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} 10292 ins_encode %{ 10293 __ stx(G0, $mem$$Address); 10294 %} 10295 ins_pipe(fstoreD_mem_zero); 10296 %} 10297 10298 instruct storeV2I_zero(memory mem, immI0 zero) %{ 10299 predicate(n->as_StoreVector()->memory_size() == 8); 10300 match(Set mem (StoreVector mem (ReplicateI zero))); 10301 ins_cost(MEMORY_REF_COST); 10302 size(4); 10303 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} 10304 ins_encode %{ 10305 __ stx(G0, $mem$$Address); 10306 %} 10307 ins_pipe(fstoreD_mem_zero); 10308 %} 10309 10310 instruct storeV2F_zero(memory mem, immF0 zero) %{ 10311 predicate(n->as_StoreVector()->memory_size() == 8); 10312 match(Set mem (StoreVector mem (ReplicateF zero))); 10313 ins_cost(MEMORY_REF_COST); 10314 size(4); 10315 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} 10316 ins_encode %{ 10317 __ stx(G0, $mem$$Address); 10318 %} 10319 ins_pipe(fstoreD_mem_zero); 10320 %} 10321 10322 // Replicate scalar to packed byte values into Double register 10323 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10324 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); 10325 match(Set dst (ReplicateB src)); 10326 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10327 format %{ "SLLX $src,56,$tmp\n\t" 10328 "SRLX $tmp, 8,$tmp2\n\t" 10329 "OR $tmp,$tmp2,$tmp\n\t" 10330 "SRLX $tmp,16,$tmp2\n\t" 10331 "OR $tmp,$tmp2,$tmp\n\t" 10332 "SRLX $tmp,32,$tmp2\n\t" 10333 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10334 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10335 ins_encode %{ 10336 Register Rsrc = $src$$Register; 10337 Register Rtmp = $tmp$$Register; 10338 Register Rtmp2 = $tmp2$$Register; 10339 __ sllx(Rsrc, 56, Rtmp); 10340 __ srlx(Rtmp, 8, Rtmp2); 10341 __ or3 (Rtmp, Rtmp2, Rtmp); 10342 __ srlx(Rtmp, 16, Rtmp2); 10343 __ or3 (Rtmp, Rtmp2, Rtmp); 10344 __ srlx(Rtmp, 32, Rtmp2); 10345 __ or3 (Rtmp, Rtmp2, Rtmp); 10346 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10347 %} 10348 ins_pipe(ialu_reg); 10349 %} 10350 10351 // Replicate scalar to packed byte values into Double stack 10352 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10353 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); 10354 match(Set dst (ReplicateB src)); 10355 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10356 format %{ "SLLX $src,56,$tmp\n\t" 10357 "SRLX $tmp, 8,$tmp2\n\t" 10358 "OR $tmp,$tmp2,$tmp\n\t" 10359 "SRLX $tmp,16,$tmp2\n\t" 10360 "OR $tmp,$tmp2,$tmp\n\t" 10361 "SRLX $tmp,32,$tmp2\n\t" 10362 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10363 "STX $tmp,$dst\t! regL to stkD" %} 10364 ins_encode %{ 10365 Register Rsrc = $src$$Register; 10366 Register Rtmp = $tmp$$Register; 10367 Register Rtmp2 = $tmp2$$Register; 10368 __ sllx(Rsrc, 56, Rtmp); 10369 __ srlx(Rtmp, 8, Rtmp2); 10370 __ or3 (Rtmp, Rtmp2, Rtmp); 10371 __ srlx(Rtmp, 16, Rtmp2); 10372 __ or3 (Rtmp, Rtmp2, Rtmp); 10373 __ srlx(Rtmp, 32, Rtmp2); 10374 __ or3 (Rtmp, Rtmp2, Rtmp); 10375 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10376 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10377 %} 10378 ins_pipe(ialu_reg); 10379 %} 10380 10381 // Replicate scalar constant to packed byte values in Double register 10382 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 10383 predicate(n->as_Vector()->length() == 8); 10384 match(Set dst (ReplicateB con)); 10385 effect(KILL tmp); 10386 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 10387 ins_encode %{ 10388 // XXX This is a quick fix for 6833573. 10389 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 10390 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 10391 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10392 %} 10393 ins_pipe(loadConFD); 10394 %} 10395 10396 // Replicate scalar to packed char/short values into Double register 10397 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10398 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); 10399 match(Set dst (ReplicateS src)); 10400 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10401 format %{ "SLLX $src,48,$tmp\n\t" 10402 "SRLX $tmp,16,$tmp2\n\t" 10403 "OR $tmp,$tmp2,$tmp\n\t" 10404 "SRLX $tmp,32,$tmp2\n\t" 10405 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10406 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10407 ins_encode %{ 10408 Register Rsrc = $src$$Register; 10409 Register Rtmp = $tmp$$Register; 10410 Register Rtmp2 = $tmp2$$Register; 10411 __ sllx(Rsrc, 48, Rtmp); 10412 __ srlx(Rtmp, 16, Rtmp2); 10413 __ or3 (Rtmp, Rtmp2, Rtmp); 10414 __ srlx(Rtmp, 32, Rtmp2); 10415 __ or3 (Rtmp, Rtmp2, Rtmp); 10416 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10417 %} 10418 ins_pipe(ialu_reg); 10419 %} 10420 10421 // Replicate scalar to packed char/short values into Double stack 10422 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10423 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); 10424 match(Set dst (ReplicateS src)); 10425 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10426 format %{ "SLLX $src,48,$tmp\n\t" 10427 "SRLX $tmp,16,$tmp2\n\t" 10428 "OR $tmp,$tmp2,$tmp\n\t" 10429 "SRLX $tmp,32,$tmp2\n\t" 10430 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10431 "STX $tmp,$dst\t! regL to stkD" %} 10432 ins_encode %{ 10433 Register Rsrc = $src$$Register; 10434 Register Rtmp = $tmp$$Register; 10435 Register Rtmp2 = $tmp2$$Register; 10436 __ sllx(Rsrc, 48, Rtmp); 10437 __ srlx(Rtmp, 16, Rtmp2); 10438 __ or3 (Rtmp, Rtmp2, Rtmp); 10439 __ srlx(Rtmp, 32, Rtmp2); 10440 __ or3 (Rtmp, Rtmp2, Rtmp); 10441 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10442 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10443 %} 10444 ins_pipe(ialu_reg); 10445 %} 10446 10447 // Replicate scalar constant to packed char/short values in Double register 10448 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 10449 predicate(n->as_Vector()->length() == 4); 10450 match(Set dst (ReplicateS con)); 10451 effect(KILL tmp); 10452 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 10453 ins_encode %{ 10454 // XXX This is a quick fix for 6833573. 10455 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 10456 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 10457 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10458 %} 10459 ins_pipe(loadConFD); 10460 %} 10461 10462 // Replicate scalar to packed int values into Double register 10463 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10464 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); 10465 match(Set dst (ReplicateI src)); 10466 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10467 format %{ "SLLX $src,32,$tmp\n\t" 10468 "SRLX $tmp,32,$tmp2\n\t" 10469 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10470 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10471 ins_encode %{ 10472 Register Rsrc = $src$$Register; 10473 Register Rtmp = $tmp$$Register; 10474 Register Rtmp2 = $tmp2$$Register; 10475 __ sllx(Rsrc, 32, Rtmp); 10476 __ srlx(Rtmp, 32, Rtmp2); 10477 __ or3 (Rtmp, Rtmp2, Rtmp); 10478 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10479 %} 10480 ins_pipe(ialu_reg); 10481 %} 10482 10483 // Replicate scalar to packed int values into Double stack 10484 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10485 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); 10486 match(Set dst (ReplicateI src)); 10487 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10488 format %{ "SLLX $src,32,$tmp\n\t" 10489 "SRLX $tmp,32,$tmp2\n\t" 10490 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10491 "STX $tmp,$dst\t! regL to stkD" %} 10492 ins_encode %{ 10493 Register Rsrc = $src$$Register; 10494 Register Rtmp = $tmp$$Register; 10495 Register Rtmp2 = $tmp2$$Register; 10496 __ sllx(Rsrc, 32, Rtmp); 10497 __ srlx(Rtmp, 32, Rtmp2); 10498 __ or3 (Rtmp, Rtmp2, Rtmp); 10499 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10500 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10501 %} 10502 ins_pipe(ialu_reg); 10503 %} 10504 10505 // Replicate scalar zero constant to packed int values in Double register 10506 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 10507 predicate(n->as_Vector()->length() == 2); 10508 match(Set dst (ReplicateI con)); 10509 effect(KILL tmp); 10510 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 10511 ins_encode %{ 10512 // XXX This is a quick fix for 6833573. 10513 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 10514 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 10515 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10516 %} 10517 ins_pipe(loadConFD); 10518 %} 10519 10520 // Replicate scalar to packed float values into Double stack 10521 instruct Repl2F_stk(stackSlotD dst, regF src) %{ 10522 predicate(n->as_Vector()->length() == 2); 10523 match(Set dst (ReplicateF src)); 10524 ins_cost(MEMORY_REF_COST*2); 10525 format %{ "STF $src,$dst.hi\t! packed2F\n\t" 10526 "STF $src,$dst.lo" %} 10527 opcode(Assembler::stf_op3); 10528 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); 10529 ins_pipe(fstoreF_stk_reg); 10530 %} 10531 10532 // Replicate scalar zero constant to packed float values in Double register 10533 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ 10534 predicate(n->as_Vector()->length() == 2); 10535 match(Set dst (ReplicateF con)); 10536 effect(KILL tmp); 10537 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} 10538 ins_encode %{ 10539 // XXX This is a quick fix for 6833573. 10540 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); 10541 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); 10542 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10543 %} 10544 ins_pipe(loadConFD); 10545 %} 10546 10547 //----------PEEPHOLE RULES----------------------------------------------------- 10548 // These must follow all instruction definitions as they use the names 10549 // defined in the instructions definitions. 10550 // 10551 // peepmatch ( root_instr_name [preceding_instruction]* ); 10552 // 10553 // peepconstraint %{ 10554 // (instruction_number.operand_name relational_op instruction_number.operand_name 10555 // [, ...] ); 10556 // // instruction numbers are zero-based using left to right order in peepmatch 10557 // 10558 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 10559 // // provide an instruction_number.operand_name for each operand that appears 10560 // // in the replacement instruction's match rule 10561 // 10562 // ---------VM FLAGS--------------------------------------------------------- 10563 // 10564 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10565 // 10566 // Each peephole rule is given an identifying number starting with zero and 10567 // increasing by one in the order seen by the parser. An individual peephole 10568 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10569 // on the command-line. 10570 // 10571 // ---------CURRENT LIMITATIONS---------------------------------------------- 10572 // 10573 // Only match adjacent instructions in same basic block 10574 // Only equality constraints 10575 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10576 // Only one replacement instruction 10577 // 10578 // ---------EXAMPLE---------------------------------------------------------- 10579 // 10580 // // pertinent parts of existing instructions in architecture description 10581 // instruct movI(eRegI dst, eRegI src) %{ 10582 // match(Set dst (CopyI src)); 10583 // %} 10584 // 10585 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10586 // match(Set dst (AddI dst src)); 10587 // effect(KILL cr); 10588 // %} 10589 // 10590 // // Change (inc mov) to lea 10591 // peephole %{ 10592 // // increment preceeded by register-register move 10593 // peepmatch ( incI_eReg movI ); 10594 // // require that the destination register of the increment 10595 // // match the destination register of the move 10596 // peepconstraint ( 0.dst == 1.dst ); 10597 // // construct a replacement instruction that sets 10598 // // the destination to ( move's source register + one ) 10599 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 10600 // %} 10601 // 10602 10603 // // Change load of spilled value to only a spill 10604 // instruct storeI(memory mem, eRegI src) %{ 10605 // match(Set mem (StoreI mem src)); 10606 // %} 10607 // 10608 // instruct loadI(eRegI dst, memory mem) %{ 10609 // match(Set dst (LoadI mem)); 10610 // %} 10611 // 10612 // peephole %{ 10613 // peepmatch ( loadI storeI ); 10614 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 10615 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 10616 // %} 10617 10618 //----------SMARTSPILL RULES--------------------------------------------------- 10619 // These must follow all instruction definitions as they use the names 10620 // defined in the instructions definitions. 10621 // 10622 // SPARC will probably not have any of these rules due to RISC instruction set. 10623 10624 //----------PIPELINE----------------------------------------------------------- 10625 // Rules which define the behavior of the target architectures pipeline.