1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP 27 28 #include "asm/assembler.hpp" 29 30 31 inline void Assembler::avoid_pipeline_stall() { 32 #ifdef VALIDATE_PIPELINE 33 if (_hazard_state == PcHazard) { 34 assert(is_cbcond_before() || is_rdpc_before(), "PC-hazard not preceeded by CBCOND or RDPC."); 35 assert_no_delay("Must not have PC-hazard state in delay-slot."); 36 nop(); 37 _hazard_state = NoHazard; 38 } 39 #endif 40 41 bool post_cond = is_cbcond_before(); 42 bool post_rdpc = is_rdpc_before(); 43 44 if (post_cond || post_rdpc) { 45 nop(); 46 #ifdef VALIDATE_PIPELINE 47 if (_hazard_state != PcHazard) { 48 assert(post_cond, "CBCOND before when no hazard @0x%p\n", pc()); 49 assert(post_rdpc, "RDPC before when no hazard @0x%p\n", pc()); 50 } 51 #endif 52 } 53 } 54 55 inline void Assembler::check_delay() { 56 #ifdef VALIDATE_PIPELINE 57 guarantee(_delay_state != AtDelay, "Use delayed() when filling delay-slot"); 58 _delay_state = NoDelay; 59 #endif 60 } 61 62 inline void Assembler::emit_int32(int x) { 63 check_delay(); 64 #ifdef VALIDATE_PIPELINE 65 _hazard_state = NoHazard; 66 #endif 67 AbstractAssembler::emit_int32(x); 68 } 69 70 inline void Assembler::emit_data(int x) { 71 emit_int32(x); 72 } 73 74 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { 75 relocate(rtype); 76 emit_int32(x); 77 } 78 79 inline void Assembler::emit_data(int x, RelocationHolder const &rspec) { 80 relocate(rspec); 81 emit_int32(x); 82 } 83 84 85 inline void Assembler::add(Register s1, Register s2, Register d) { 86 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2)); 87 } 88 inline void Assembler::add(Register s1, int simm13a, Register d) { 89 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 90 } 91 92 inline void Assembler::addcc(Register s1, Register s2, Register d) { 93 emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 94 } 95 inline void Assembler::addcc(Register s1, int simm13a, Register d) { 96 emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 97 } 98 inline void Assembler::addc(Register s1, Register s2, Register d) { 99 emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | rs2(s2)); 100 } 101 inline void Assembler::addc(Register s1, int simm13a, Register d) { 102 emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 103 } 104 inline void Assembler::addccc(Register s1, Register s2, Register d) { 105 emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 106 } 107 inline void Assembler::addccc(Register s1, int simm13a, Register d) { 108 emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 109 } 110 111 inline void Assembler::aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 112 aes_only(); 113 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D)); 114 } 115 inline void Assembler::aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 116 aes_only(); 117 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D)); 118 } 119 inline void Assembler::aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 120 aes_only(); 121 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D)); 122 } 123 inline void Assembler::aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 124 aes_only(); 125 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D)); 126 } 127 inline void Assembler::aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 128 aes_only(); 129 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D)); 130 } 131 inline void Assembler::aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 132 aes_only(); 133 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D)); 134 } 135 inline void Assembler::aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 136 aes_only(); 137 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D)); 138 } 139 inline void Assembler::aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 140 aes_only(); 141 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D)); 142 } 143 inline void Assembler::aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d) { 144 aes_only(); 145 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D)); 146 } 147 148 // 3-operand AES instructions 149 150 inline void Assembler::aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d) { 151 aes_only(); 152 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D)); 153 } 154 inline void Assembler::aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d) { 155 aes_only(); 156 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D)); 157 } 158 159 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt) { 160 avoid_pipeline_stall(); 161 cti(); 162 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); 163 induce_delay_slot(); 164 } 165 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, Label &L) { 166 // Note[+]: All assembly emit routines using the 'target()' branch back-patch 167 // resolver must call 'avoid_pipeline_stall()' prior to calling 'target()' 168 // (we must do so even though the call will be made, as here, in the above 169 // implementation of 'bpr()', invoked below). The reason is the assumption 170 // made in 'target()', where using the current PC as the address for back- 171 // patching prevents any additional code to be emitted _after_ the address 172 // has been set (implicitly) in order to refer to the correct instruction. 173 avoid_pipeline_stall(); 174 bpr(c, a, p, s1, target(L)); 175 } 176 177 inline void Assembler::fb(Condition c, bool a, address d, relocInfo::relocType rt) { 178 v9_dep(); 179 avoid_pipeline_stall(); 180 cti(); 181 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 182 induce_delay_slot(); 183 } 184 inline void Assembler::fb(Condition c, bool a, Label &L) { 185 avoid_pipeline_stall(); 186 fb(c, a, target(L)); 187 } 188 189 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 190 avoid_pipeline_stall(); 191 cti(); 192 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 193 induce_delay_slot(); 194 } 195 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, Label &L) { 196 avoid_pipeline_stall(); 197 fbp(c, a, cc, p, target(L)); 198 } 199 200 inline void Assembler::br(Condition c, bool a, address d, relocInfo::relocType rt) { 201 v9_dep(); 202 avoid_pipeline_stall(); 203 cti(); 204 emit_data(op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 205 induce_delay_slot(); 206 } 207 inline void Assembler::br(Condition c, bool a, Label &L) { 208 avoid_pipeline_stall(); 209 br(c, a, target(L)); 210 } 211 212 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 213 avoid_pipeline_stall(); 214 cti(); 215 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 216 induce_delay_slot(); 217 } 218 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, Label &L) { 219 avoid_pipeline_stall(); 220 bp(c, a, cc, p, target(L)); 221 } 222 223 // compare and branch 224 inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label &L) { 225 avoid_pipeline_stall(); 226 cti(); 227 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); 228 induce_pc_hazard(); 229 } 230 inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label &L) { 231 avoid_pipeline_stall(); 232 cti(); 233 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); 234 induce_pc_hazard(); 235 } 236 237 inline void Assembler::call(address d, relocInfo::relocType rt) { 238 avoid_pipeline_stall(); 239 cti(); 240 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); 241 induce_delay_slot(); 242 assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 243 } 244 inline void Assembler::call(Label &L, relocInfo::relocType rt) { 245 avoid_pipeline_stall(); 246 call(target(L), rt); 247 } 248 249 inline void Assembler::call(address d, RelocationHolder const &rspec) { 250 avoid_pipeline_stall(); 251 cti(); 252 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rspec); 253 induce_delay_slot(); 254 assert(rspec.type() != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 255 } 256 257 inline void Assembler::casa(Register s1, Register s2, Register d, int ia) { 258 emit_int32(op(ldst_op) | rd(d) | op3(casa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 259 } 260 inline void Assembler::casxa(Register s1, Register s2, Register d, int ia) { 261 emit_int32(op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 262 } 263 264 inline void Assembler::udiv(Register s1, Register s2, Register d) { 265 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | rs2(s2)); 266 } 267 inline void Assembler::udiv(Register s1, int simm13a, Register d) { 268 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 269 } 270 inline void Assembler::sdiv(Register s1, Register s2, Register d) { 271 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | rs2(s2)); 272 } 273 inline void Assembler::sdiv(Register s1, int simm13a, Register d) { 274 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 275 } 276 inline void Assembler::udivcc(Register s1, Register s2, Register d) { 277 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 278 } 279 inline void Assembler::udivcc(Register s1, int simm13a, Register d) { 280 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 281 } 282 inline void Assembler::sdivcc(Register s1, Register s2, Register d) { 283 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 284 } 285 inline void Assembler::sdivcc(Register s1, int simm13a, Register d) { 286 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 287 } 288 289 inline void Assembler::done() { 290 cti(); 291 emit_int32(op(arith_op) | fcn(0) | op3(done_op3)); 292 } 293 inline void Assembler::retry() { 294 cti(); 295 emit_int32(op(arith_op) | fcn(1) | op3(retry_op3)); 296 } 297 298 inline void Assembler::fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 299 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); 300 } 301 inline void Assembler::fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 302 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); 303 } 304 305 inline void Assembler::fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { 306 emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); 307 } 308 inline void Assembler::fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { 309 emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); 310 } 311 312 inline void Assembler::ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 313 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); 314 } 315 inline void Assembler::ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 316 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); 317 } 318 319 inline void Assembler::ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d) { 320 emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); 321 } 322 323 inline void Assembler::fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 324 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); 325 } 326 inline void Assembler::fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 327 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); 328 } 329 330 inline void Assembler::fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 331 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); 332 } 333 inline void Assembler::fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 334 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); 335 } 336 inline void Assembler::fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 337 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); 338 } 339 inline void Assembler::fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 340 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); 341 } 342 inline void Assembler::fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d) { 343 emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); 344 } 345 inline void Assembler::fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 346 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); 347 } 348 349 inline void Assembler::fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 350 vis1_only(); 351 emit_int32(op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); 352 } 353 354 inline void Assembler::fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 355 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); 356 } 357 358 inline void Assembler::flush(Register s1, Register s2) { 359 emit_int32(op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); 360 } 361 inline void Assembler::flush(Register s1, int simm13a) { 362 emit_data(op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 363 } 364 365 inline void Assembler::flushw() { 366 emit_int32(op(arith_op) | op3(flushw_op3)); 367 } 368 369 inline void Assembler::illtrap(int const22a) { 370 emit_int32(op(branch_op) | u_field(const22a, 21, 0)); 371 } 372 373 inline void Assembler::impdep1(int id1, int const19a) { 374 emit_int32(op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); 375 } 376 inline void Assembler::impdep2(int id1, int const19a) { 377 emit_int32(op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); 378 } 379 380 inline void Assembler::jmpl(Register s1, Register s2, Register d) { 381 avoid_pipeline_stall(); 382 cti(); 383 emit_int32(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); 384 induce_delay_slot(); 385 } 386 inline void Assembler::jmpl(Register s1, int simm13a, Register d, RelocationHolder const &rspec) { 387 avoid_pipeline_stall(); 388 cti(); 389 emit_data(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 390 induce_delay_slot(); 391 } 392 393 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { 394 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2)); 395 } 396 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const &rspec) { 397 emit_data(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 398 } 399 400 inline void Assembler::ldxfsr(Register s1, Register s2) { 401 emit_int32(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2)); 402 } 403 inline void Assembler::ldxfsr(Register s1, int simm13a) { 404 emit_data(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 405 } 406 407 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d) { 408 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2)); 409 } 410 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { 411 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 412 } 413 414 inline void Assembler::ldsb(Register s1, Register s2, Register d) { 415 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2)); 416 } 417 inline void Assembler::ldsb(Register s1, int simm13a, Register d) { 418 emit_data(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 419 } 420 421 inline void Assembler::ldsh(Register s1, Register s2, Register d) { 422 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2)); 423 } 424 inline void Assembler::ldsh(Register s1, int simm13a, Register d) { 425 emit_data(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 426 } 427 inline void Assembler::ldsw(Register s1, Register s2, Register d) { 428 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2)); 429 } 430 inline void Assembler::ldsw(Register s1, int simm13a, Register d) { 431 emit_data(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 432 } 433 inline void Assembler::ldub(Register s1, Register s2, Register d) { 434 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2)); 435 } 436 inline void Assembler::ldub(Register s1, int simm13a, Register d) { 437 emit_data(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 438 } 439 inline void Assembler::lduh(Register s1, Register s2, Register d) { 440 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2)); 441 } 442 inline void Assembler::lduh(Register s1, int simm13a, Register d) { 443 emit_data(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 444 } 445 inline void Assembler::lduw(Register s1, Register s2, Register d) { 446 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2)); 447 } 448 inline void Assembler::lduw(Register s1, int simm13a, Register d) { 449 emit_data(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 450 } 451 452 inline void Assembler::ldx(Register s1, Register s2, Register d) { 453 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2)); 454 } 455 inline void Assembler::ldx(Register s1, int simm13a, Register d) { 456 emit_data(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 457 } 458 inline void Assembler::ldd(Register s1, Register s2, Register d) { 459 v9_dep(); 460 assert(d->is_even(), "not even"); 461 emit_int32(op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2)); 462 } 463 inline void Assembler::ldd(Register s1, int simm13a, Register d) { 464 v9_dep(); 465 assert(d->is_even(), "not even"); 466 emit_data(op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 467 } 468 469 inline void Assembler::ldsba(Register s1, Register s2, int ia, Register d) { 470 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 471 } 472 inline void Assembler::ldsba(Register s1, int simm13a, Register d) { 473 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 474 } 475 inline void Assembler::ldsha(Register s1, Register s2, int ia, Register d) { 476 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 477 } 478 inline void Assembler::ldsha(Register s1, int simm13a, Register d) { 479 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 480 } 481 inline void Assembler::ldswa(Register s1, Register s2, int ia, Register d) { 482 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 483 } 484 inline void Assembler::ldswa(Register s1, int simm13a, Register d) { 485 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 486 } 487 inline void Assembler::lduba(Register s1, Register s2, int ia, Register d) { 488 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 489 } 490 inline void Assembler::lduba(Register s1, int simm13a, Register d) { 491 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 492 } 493 inline void Assembler::lduha(Register s1, Register s2, int ia, Register d) { 494 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 495 } 496 inline void Assembler::lduha(Register s1, int simm13a, Register d) { 497 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 498 } 499 inline void Assembler::lduwa(Register s1, Register s2, int ia, Register d) { 500 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 501 } 502 inline void Assembler::lduwa(Register s1, int simm13a, Register d) { 503 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 504 } 505 inline void Assembler::ldxa(Register s1, Register s2, int ia, Register d) { 506 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 507 } 508 inline void Assembler::ldxa(Register s1, int simm13a, Register d) { 509 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 510 } 511 512 inline void Assembler::and3(Register s1, Register s2, Register d) { 513 emit_int32(op(arith_op) | rd(d) | op3(and_op3) | rs1(s1) | rs2(s2)); 514 } 515 inline void Assembler::and3(Register s1, int simm13a, Register d) { 516 emit_int32(op(arith_op) | rd(d) | op3(and_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 517 } 518 inline void Assembler::andcc(Register s1, Register s2, Register d) { 519 emit_int32(op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 520 } 521 inline void Assembler::andcc(Register s1, int simm13a, Register d) { 522 emit_int32(op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 523 } 524 inline void Assembler::andn(Register s1, Register s2, Register d) { 525 emit_int32(op(arith_op) | rd(d) | op3(andn_op3) | rs1(s1) | rs2(s2)); 526 } 527 inline void Assembler::andn(Register s1, int simm13a, Register d) { 528 emit_int32(op(arith_op) | rd(d) | op3(andn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 529 } 530 inline void Assembler::andncc(Register s1, Register s2, Register d) { 531 emit_int32(op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 532 } 533 inline void Assembler::andncc(Register s1, int simm13a, Register d) { 534 emit_int32(op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 535 } 536 inline void Assembler::or3(Register s1, Register s2, Register d) { 537 emit_int32(op(arith_op) | rd(d) | op3(or_op3) | rs1(s1) | rs2(s2)); 538 } 539 inline void Assembler::or3(Register s1, int simm13a, Register d) { 540 emit_int32(op(arith_op) | rd(d) | op3(or_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 541 } 542 inline void Assembler::orcc(Register s1, Register s2, Register d) { 543 emit_int32(op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 544 } 545 inline void Assembler::orcc(Register s1, int simm13a, Register d) { 546 emit_int32(op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 547 } 548 inline void Assembler::orn(Register s1, Register s2, Register d) { 549 emit_int32(op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2)); 550 } 551 inline void Assembler::orn(Register s1, int simm13a, Register d) { 552 emit_int32(op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 553 } 554 inline void Assembler::orncc(Register s1, Register s2, Register d) { 555 emit_int32(op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 556 } 557 inline void Assembler::orncc(Register s1, int simm13a, Register d) { 558 emit_int32(op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 559 } 560 inline void Assembler::xor3(Register s1, Register s2, Register d) { 561 emit_int32(op(arith_op) | rd(d) | op3(xor_op3) | rs1(s1) | rs2(s2)); 562 } 563 inline void Assembler::xor3(Register s1, int simm13a, Register d) { 564 emit_int32(op(arith_op) | rd(d) | op3(xor_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 565 } 566 inline void Assembler::xorcc(Register s1, Register s2, Register d) { 567 emit_int32(op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 568 } 569 inline void Assembler::xorcc(Register s1, int simm13a, Register d) { 570 emit_int32(op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 571 } 572 inline void Assembler::xnor(Register s1, Register s2, Register d) { 573 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3) | rs1(s1) | rs2(s2)); 574 } 575 inline void Assembler::xnor(Register s1, int simm13a, Register d) { 576 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 577 } 578 inline void Assembler::xnorcc(Register s1, Register s2, Register d) { 579 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 580 } 581 inline void Assembler::xnorcc(Register s1, int simm13a, Register d) { 582 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 583 } 584 585 inline void Assembler::membar(Membar_mask_bits const7a) { 586 emit_int32(op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field(int(const7a), 6, 0)); 587 } 588 589 inline void Assembler::fmov(FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d) { 590 emit_int32(op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); 591 } 592 593 inline void Assembler::fmov(FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d) { 594 emit_int32(op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); 595 } 596 597 inline void Assembler::movcc(Condition c, bool floatCC, CC cca, Register s2, Register d) { 598 emit_int32(op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2)); 599 } 600 inline void Assembler::movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d) { 601 emit_int32(op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11)); 602 } 603 604 inline void Assembler::movr(RCondition c, Register s1, Register s2, Register d) { 605 emit_int32(op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2)); 606 } 607 inline void Assembler::movr(RCondition c, Register s1, int simm10a, Register d) { 608 emit_int32(op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10)); 609 } 610 611 inline void Assembler::mulx(Register s1, Register s2, Register d) { 612 emit_int32(op(arith_op) | rd(d) | op3(mulx_op3) | rs1(s1) | rs2(s2)); 613 } 614 inline void Assembler::mulx(Register s1, int simm13a, Register d) { 615 emit_int32(op(arith_op) | rd(d) | op3(mulx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 616 } 617 inline void Assembler::sdivx(Register s1, Register s2, Register d) { 618 emit_int32(op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2)); 619 } 620 inline void Assembler::sdivx(Register s1, int simm13a, Register d) { 621 emit_int32(op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 622 } 623 inline void Assembler::udivx(Register s1, Register s2, Register d) { 624 emit_int32(op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2)); 625 } 626 inline void Assembler::udivx(Register s1, int simm13a, Register d) { 627 emit_int32(op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 628 } 629 630 inline void Assembler::umul(Register s1, Register s2, Register d) { 631 emit_int32(op(arith_op) | rd(d) | op3(umul_op3) | rs1(s1) | rs2(s2)); 632 } 633 inline void Assembler::umul(Register s1, int simm13a, Register d) { 634 emit_int32(op(arith_op) | rd(d) | op3(umul_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 635 } 636 inline void Assembler::smul(Register s1, Register s2, Register d) { 637 emit_int32(op(arith_op) | rd(d) | op3(smul_op3) | rs1(s1) | rs2(s2)); 638 } 639 inline void Assembler::smul(Register s1, int simm13a, Register d) { 640 emit_int32(op(arith_op) | rd(d) | op3(smul_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 641 } 642 inline void Assembler::umulcc(Register s1, Register s2, Register d) { 643 emit_int32(op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 644 } 645 inline void Assembler::umulcc(Register s1, int simm13a, Register d) { 646 emit_int32(op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 647 } 648 inline void Assembler::smulcc(Register s1, Register s2, Register d) { 649 emit_int32(op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 650 } 651 inline void Assembler::smulcc(Register s1, int simm13a, Register d) { 652 emit_int32(op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 653 } 654 655 inline void Assembler::nop() { 656 emit_int32(op(branch_op) | op2(sethi_op2)); 657 } 658 659 inline void Assembler::sw_count() { 660 emit_int32(op(branch_op) | op2(sethi_op2) | 0x3f0); 661 } 662 663 inline void Assembler::popc(Register s, Register d) { 664 emit_int32(op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); 665 } 666 inline void Assembler::popc(int simm13a, Register d) { 667 emit_int32(op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); 668 } 669 670 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { 671 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2)); 672 } 673 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { 674 emit_data(op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 675 } 676 677 inline void Assembler::prefetcha(Register s1, Register s2, int ia, PrefetchFcn f) { 678 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 679 } 680 inline void Assembler::prefetcha(Register s1, int simm13a, PrefetchFcn f) { 681 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 682 } 683 684 inline void Assembler::rdy(Register d) { 685 v9_dep(); 686 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); 687 } 688 inline void Assembler::rdccr(Register d) { 689 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); 690 } 691 inline void Assembler::rdasi(Register d) { 692 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); 693 } 694 inline void Assembler::rdtick(Register d) { 695 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); 696 } 697 inline void Assembler::rdpc(Register d) { 698 avoid_pipeline_stall(); 699 cti(); 700 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); 701 induce_pc_hazard(); 702 } 703 inline void Assembler::rdfprs(Register d) { 704 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); 705 } 706 707 inline void Assembler::rett(Register s1, Register s2) { 708 cti(); 709 emit_int32(op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); 710 induce_delay_slot(); 711 } 712 inline void Assembler::rett(Register s1, int simm13a, relocInfo::relocType rt) { 713 cti(); 714 emit_data(op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); 715 induce_delay_slot(); 716 } 717 718 inline void Assembler::save(Register s1, Register s2, Register d) { 719 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2)); 720 } 721 inline void Assembler::save(Register s1, int simm13a, Register d) { 722 // make sure frame is at least large enough for the register save area 723 assert(-simm13a >= 16 * wordSize, "frame too small"); 724 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 725 } 726 727 inline void Assembler::restore(Register s1, Register s2, Register d) { 728 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2)); 729 } 730 inline void Assembler::restore(Register s1, int simm13a, Register d) { 731 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 732 } 733 734 // pp 216 735 736 inline void Assembler::saved() { 737 emit_int32(op(arith_op) | fcn(0) | op3(saved_op3)); 738 } 739 inline void Assembler::restored() { 740 emit_int32(op(arith_op) | fcn(1) | op3(saved_op3)); 741 } 742 743 inline void Assembler::sethi(int imm22a, Register d, RelocationHolder const &rspec) { 744 emit_data(op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); 745 } 746 747 inline void Assembler::sll(Register s1, Register s2, Register d) { 748 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2)); 749 } 750 inline void Assembler::sll(Register s1, int imm5a, Register d) { 751 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 752 } 753 inline void Assembler::srl(Register s1, Register s2, Register d) { 754 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2)); 755 } 756 inline void Assembler::srl(Register s1, int imm5a, Register d) { 757 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 758 } 759 inline void Assembler::sra(Register s1, Register s2, Register d) { 760 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2)); 761 } 762 inline void Assembler::sra(Register s1, int imm5a, Register d) { 763 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 764 } 765 766 inline void Assembler::sllx(Register s1, Register s2, Register d) { 767 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2)); 768 } 769 inline void Assembler::sllx(Register s1, int imm6a, Register d) { 770 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 771 } 772 inline void Assembler::srlx(Register s1, Register s2, Register d) { 773 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2)); 774 } 775 inline void Assembler::srlx(Register s1, int imm6a, Register d) { 776 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 777 } 778 inline void Assembler::srax(Register s1, Register s2, Register d) { 779 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2)); 780 } 781 inline void Assembler::srax(Register s1, int imm6a, Register d) { 782 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 783 } 784 785 inline void Assembler::sir(int simm13a) { 786 emit_int32(op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); 787 } 788 789 // pp 221 790 791 inline void Assembler::stbar() { 792 emit_int32(op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); 793 } 794 795 // pp 222 796 797 inline void Assembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { 798 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2)); 799 } 800 inline void Assembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { 801 emit_data(op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 802 } 803 804 inline void Assembler::stxfsr(Register s1, Register s2) { 805 emit_int32(op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2)); 806 } 807 inline void Assembler::stxfsr(Register s1, int simm13a) { 808 emit_data(op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 809 } 810 811 inline void Assembler::stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia) { 812 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2)); 813 } 814 inline void Assembler::stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { 815 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 816 } 817 818 // p 226 819 820 inline void Assembler::stb(Register d, Register s1, Register s2) { 821 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2)); 822 } 823 inline void Assembler::stb(Register d, Register s1, int simm13a) { 824 emit_data(op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 825 } 826 inline void Assembler::sth(Register d, Register s1, Register s2) { 827 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2)); 828 } 829 inline void Assembler::sth(Register d, Register s1, int simm13a) { 830 emit_data(op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 831 } 832 inline void Assembler::stw(Register d, Register s1, Register s2) { 833 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2)); 834 } 835 inline void Assembler::stw(Register d, Register s1, int simm13a) { 836 emit_data(op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 837 } 838 839 840 inline void Assembler::stx(Register d, Register s1, Register s2) { 841 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2)); 842 } 843 inline void Assembler::stx(Register d, Register s1, int simm13a) { 844 emit_data(op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 845 } 846 inline void Assembler::std(Register d, Register s1, Register s2) { 847 v9_dep(); 848 assert(d->is_even(), "not even"); 849 emit_int32(op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2)); 850 } 851 inline void Assembler::std(Register d, Register s1, int simm13a) { 852 v9_dep(); 853 assert(d->is_even(), "not even"); 854 emit_data(op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 855 } 856 857 inline void Assembler::stba(Register d, Register s1, Register s2, int ia) { 858 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 859 } 860 inline void Assembler::stba(Register d, Register s1, int simm13a) { 861 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 862 } 863 inline void Assembler::stha(Register d, Register s1, Register s2, int ia) { 864 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 865 } 866 inline void Assembler::stha(Register d, Register s1, int simm13a) { 867 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 868 } 869 inline void Assembler::stwa(Register d, Register s1, Register s2, int ia) { 870 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 871 } 872 inline void Assembler::stwa(Register d, Register s1, int simm13a) { 873 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 874 } 875 inline void Assembler::stxa(Register d, Register s1, Register s2, int ia) { 876 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 877 } 878 inline void Assembler::stxa(Register d, Register s1, int simm13a) { 879 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 880 } 881 inline void Assembler::stda(Register d, Register s1, Register s2, int ia) { 882 emit_int32(op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 883 } 884 inline void Assembler::stda(Register d, Register s1, int simm13a) { 885 emit_int32(op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 886 } 887 888 // pp 230 889 890 inline void Assembler::sub(Register s1, Register s2, Register d) { 891 emit_int32(op(arith_op) | rd(d) | op3(sub_op3) | rs1(s1) | rs2(s2)); 892 } 893 inline void Assembler::sub(Register s1, int simm13a, Register d) { 894 emit_int32(op(arith_op) | rd(d) | op3(sub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 895 } 896 897 inline void Assembler::subcc(Register s1, Register s2, Register d) { 898 emit_int32(op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 899 } 900 inline void Assembler::subcc(Register s1, int simm13a, Register d) { 901 emit_int32(op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 902 } 903 inline void Assembler::subc(Register s1, Register s2, Register d) { 904 emit_int32(op(arith_op) | rd(d) | op3(subc_op3) | rs1(s1) | rs2(s2)); 905 } 906 inline void Assembler::subc(Register s1, int simm13a, Register d) { 907 emit_int32(op(arith_op) | rd(d) | op3(subc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 908 } 909 inline void Assembler::subccc(Register s1, Register s2, Register d) { 910 emit_int32(op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 911 } 912 inline void Assembler::subccc(Register s1, int simm13a, Register d) { 913 emit_int32(op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 914 } 915 916 // pp 231 917 918 inline void Assembler::swap(Register s1, Register s2, Register d) { 919 v9_dep(); 920 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2)); 921 } 922 inline void Assembler::swap(Register s1, int simm13a, Register d) { 923 v9_dep(); 924 emit_data(op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 925 } 926 927 inline void Assembler::swapa(Register s1, Register s2, int ia, Register d) { 928 v9_dep(); 929 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 930 } 931 inline void Assembler::swapa(Register s1, int simm13a, Register d) { 932 v9_dep(); 933 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 934 } 935 936 // pp 234, note op in book is wrong, see pp 268 937 938 inline void Assembler::taddcc(Register s1, Register s2, Register d) { 939 emit_int32(op(arith_op) | rd(d) | op3(taddcc_op3) | rs1(s1) | rs2(s2)); 940 } 941 inline void Assembler::taddcc(Register s1, int simm13a, Register d) { 942 emit_int32(op(arith_op) | rd(d) | op3(taddcc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 943 } 944 945 // pp 235 946 947 inline void Assembler::tsubcc(Register s1, Register s2, Register d) { 948 emit_int32(op(arith_op) | rd(d) | op3(tsubcc_op3) | rs1(s1) | rs2(s2)); 949 } 950 inline void Assembler::tsubcc(Register s1, int simm13a, Register d) { 951 emit_int32(op(arith_op) | rd(d) | op3(tsubcc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 952 } 953 954 // pp 237 955 956 inline void Assembler::trap(Condition c, CC cc, Register s1, Register s2) { 957 emit_int32(op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); 958 } 959 inline void Assembler::trap(Condition c, CC cc, Register s1, int trapa) { 960 emit_int32(op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); 961 } 962 // simple uncond. trap 963 inline void Assembler::trap(int trapa) { 964 trap(always, icc, G0, trapa); 965 } 966 967 inline void Assembler::wry(Register d) { 968 v9_dep(); 969 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); 970 } 971 inline void Assembler::wrccr(Register s) { 972 emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); 973 } 974 inline void Assembler::wrccr(Register s, int simm13a) { 975 emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25) | immed(true) | simm(simm13a, 13)); 976 } 977 inline void Assembler::wrasi(Register d) { 978 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); 979 } 980 // wrasi(d, imm) stores (d xor imm) to asi 981 inline void Assembler::wrasi(Register d, int simm13a) { 982 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); 983 } 984 inline void Assembler::wrfprs(Register d) { 985 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); 986 } 987 988 inline void Assembler::alignaddr(Register s1, Register s2, Register d) { 989 vis1_only(); 990 emit_int32(op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); 991 } 992 993 inline void Assembler::faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d) { 994 vis1_only(); 995 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); 996 } 997 998 inline void Assembler::fzero(FloatRegisterImpl::Width w, FloatRegister d) { 999 vis1_only(); 1000 emit_int32(op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); 1001 } 1002 1003 inline void Assembler::fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d) { 1004 vis1_only(); 1005 emit_int32(op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); 1006 } 1007 1008 inline void Assembler::fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d) { 1009 vis1_only(); 1010 emit_int32(op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); 1011 } 1012 1013 inline void Assembler::fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d) { 1014 vis1_only(); 1015 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); 1016 } 1017 1018 inline void Assembler::stpartialf(Register s1, Register s2, FloatRegister d, int ia) { 1019 vis1_only(); 1020 emit_int32(op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 1021 } 1022 1023 // VIS2 instructions 1024 1025 inline void Assembler::edge8n(Register s1, Register s2, Register d) { 1026 vis2_only(); 1027 emit_int32(op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); 1028 } 1029 1030 inline void Assembler::bmask(Register s1, Register s2, Register d) { 1031 vis2_only(); 1032 emit_int32(op(arith_op) | rd(d) | op3(bmask_op3) | rs1(s1) | opf(bmask_opf) | rs2(s2)); 1033 } 1034 inline void Assembler::bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d) { 1035 vis2_only(); 1036 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(bshuffle_op3) | fs1(s1, FloatRegisterImpl::D) | opf(bshuffle_opf) | fs2(s2, FloatRegisterImpl::D)); 1037 } 1038 1039 // VIS3 instructions 1040 1041 inline void Assembler::movstosw(FloatRegister s, Register d) { 1042 vis3_only(); 1043 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); 1044 } 1045 inline void Assembler::movstouw(FloatRegister s, Register d) { 1046 vis3_only(); 1047 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); 1048 } 1049 inline void Assembler::movdtox(FloatRegister s, Register d) { 1050 vis3_only(); 1051 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); 1052 } 1053 1054 inline void Assembler::movwtos(Register s, FloatRegister d) { 1055 vis3_only(); 1056 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); 1057 } 1058 inline void Assembler::movxtod(Register s, FloatRegister d) { 1059 vis3_only(); 1060 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); 1061 } 1062 1063 inline void Assembler::xmulx(Register s1, Register s2, Register d) { 1064 vis3_only(); 1065 emit_int32(op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); 1066 } 1067 inline void Assembler::xmulxhi(Register s1, Register s2, Register d) { 1068 vis3_only(); 1069 emit_int32(op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); 1070 } 1071 1072 // Crypto SHA instructions 1073 1074 inline void Assembler::sha1() { 1075 sha1_only(); 1076 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha1_opf)); 1077 } 1078 inline void Assembler::sha256() { 1079 sha256_only(); 1080 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha256_opf)); 1081 } 1082 inline void Assembler::sha512() { 1083 sha512_only(); 1084 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha512_opf)); 1085 } 1086 1087 // CRC32C instruction 1088 1089 inline void Assembler::crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d) { 1090 crc32c_only(); 1091 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D)); 1092 } 1093 1094 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP