11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP 27 28 #include "asm/assembler.hpp" 29 30 31 inline void Assembler::insert_nop_after_cbcond() { 32 if (UseCBCond && cbcond_before()) { 33 nop(); 34 } 35 } 36 37 inline void Assembler::check_delay() { 38 #ifdef CHECK_DELAY 39 guarantee(delay_state != at_delay_slot, "must say delayed() when filling delay slot"); 40 delay_state = no_delay; 41 #endif 42 } 43 44 inline void Assembler::emit_int32(int x) { 45 check_delay(); 46 AbstractAssembler::emit_int32(x); 47 } 48 49 inline void Assembler::emit_data(int x) { 50 emit_int32(x); 51 } 52 53 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { 54 relocate(rtype); 55 emit_int32(x); 56 } 57 58 inline void Assembler::emit_data(int x, RelocationHolder const &rspec) { 59 relocate(rspec); 60 emit_int32(x); 61 } 62 63 64 inline void Assembler::add(Register s1, Register s2, Register d) { 65 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2)); 119 aes_only(); 120 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D)); 121 } 122 inline void Assembler::aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d) { 123 aes_only(); 124 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D)); 125 } 126 127 // 3-operand AES instructions 128 129 inline void Assembler::aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d) { 130 aes_only(); 131 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D)); 132 } 133 inline void Assembler::aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d) { 134 aes_only(); 135 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D)); 136 } 137 138 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt) { 139 insert_nop_after_cbcond(); cti(); 140 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); 141 has_delay_slot(); 142 } 143 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, Label &L) { 144 insert_nop_after_cbcond(); 145 bpr(c, a, p, s1, target(L)); 146 } 147 148 inline void Assembler::fb(Condition c, bool a, address d, relocInfo::relocType rt) { 149 v9_dep(); 150 insert_nop_after_cbcond(); cti(); 151 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 152 has_delay_slot(); 153 } 154 inline void Assembler::fb(Condition c, bool a, Label &L) { 155 insert_nop_after_cbcond(); 156 fb(c, a, target(L)); 157 } 158 159 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 160 insert_nop_after_cbcond(); cti(); 161 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 162 has_delay_slot(); 163 } 164 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, Label &L) { 165 insert_nop_after_cbcond(); 166 fbp(c, a, cc, p, target(L)); 167 } 168 169 inline void Assembler::br(Condition c, bool a, address d, relocInfo::relocType rt) { 170 v9_dep(); 171 insert_nop_after_cbcond(); cti(); 172 emit_data(op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 173 has_delay_slot(); 174 } 175 inline void Assembler::br(Condition c, bool a, Label &L) { 176 insert_nop_after_cbcond(); 177 br(c, a, target(L)); 178 } 179 180 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 181 insert_nop_after_cbcond(); cti(); 182 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 183 has_delay_slot(); 184 } 185 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, Label &L) { 186 insert_nop_after_cbcond(); 187 bp(c, a, cc, p, target(L)); 188 } 189 190 // compare and branch 191 inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label &L) { 192 cti(); no_cbcond_before(); 193 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); 194 } 195 inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label &L) { 196 cti(); no_cbcond_before(); 197 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); 198 } 199 200 inline void Assembler::call(address d, relocInfo::relocType rt) { 201 insert_nop_after_cbcond(); cti(); 202 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); 203 has_delay_slot(); 204 assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 205 } 206 inline void Assembler::call(Label &L, relocInfo::relocType rt) { 207 insert_nop_after_cbcond(); 208 call(target(L), rt); 209 } 210 211 inline void Assembler::call(address d, RelocationHolder const &rspec) { 212 insert_nop_after_cbcond(); cti(); 213 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rspec); 214 has_delay_slot(); 215 assert(rspec.type() != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 216 } 217 218 inline void Assembler::casa(Register s1, Register s2, Register d, int ia) { 219 emit_int32(op(ldst_op) | rd(d) | op3(casa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 220 } 221 inline void Assembler::casxa(Register s1, Register s2, Register d, int ia) { 222 emit_int32(op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 223 } 224 225 inline void Assembler::udiv(Register s1, Register s2, Register d) { 226 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | rs2(s2)); 227 } 228 inline void Assembler::udiv(Register s1, int simm13a, Register d) { 229 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 230 } 231 inline void Assembler::sdiv(Register s1, Register s2, Register d) { 232 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | rs2(s2)); 233 } 234 inline void Assembler::sdiv(Register s1, int simm13a, Register d) { 322 inline void Assembler::flush(Register s1, int simm13a) { 323 emit_data(op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 324 } 325 326 inline void Assembler::flushw() { 327 emit_int32(op(arith_op) | op3(flushw_op3)); 328 } 329 330 inline void Assembler::illtrap(int const22a) { 331 emit_int32(op(branch_op) | u_field(const22a, 21, 0)); 332 } 333 334 inline void Assembler::impdep1(int id1, int const19a) { 335 emit_int32(op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); 336 } 337 inline void Assembler::impdep2(int id1, int const19a) { 338 emit_int32(op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); 339 } 340 341 inline void Assembler::jmpl(Register s1, Register s2, Register d) { 342 insert_nop_after_cbcond(); cti(); 343 emit_int32(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); 344 has_delay_slot(); 345 } 346 inline void Assembler::jmpl(Register s1, int simm13a, Register d, RelocationHolder const &rspec) { 347 insert_nop_after_cbcond(); cti(); 348 emit_data(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 349 has_delay_slot(); 350 } 351 352 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { 353 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2)); 354 } 355 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const &rspec) { 356 emit_data(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 357 } 358 359 inline void Assembler::ldxfsr(Register s1, Register s2) { 360 emit_int32(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2)); 361 } 362 inline void Assembler::ldxfsr(Register s1, int simm13a) { 363 emit_data(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 364 } 365 366 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d) { 367 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2)); 368 } 369 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { 637 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 638 } 639 inline void Assembler::prefetcha(Register s1, int simm13a, PrefetchFcn f) { 640 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 641 } 642 643 inline void Assembler::rdy(Register d) { 644 v9_dep(); 645 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); 646 } 647 inline void Assembler::rdccr(Register d) { 648 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); 649 } 650 inline void Assembler::rdasi(Register d) { 651 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); 652 } 653 inline void Assembler::rdtick(Register d) { 654 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); 655 } 656 inline void Assembler::rdpc(Register d) { 657 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); 658 } 659 inline void Assembler::rdfprs(Register d) { 660 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); 661 } 662 663 inline void Assembler::rett(Register s1, Register s2) { 664 cti(); 665 emit_int32(op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); 666 has_delay_slot(); 667 } 668 inline void Assembler::rett(Register s1, int simm13a, relocInfo::relocType rt) { 669 cti(); 670 emit_data(op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); 671 has_delay_slot(); 672 } 673 674 inline void Assembler::save(Register s1, Register s2, Register d) { 675 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2)); 676 } 677 inline void Assembler::save(Register s1, int simm13a, Register d) { 678 // make sure frame is at least large enough for the register save area 679 assert(-simm13a >= 16 * wordSize, "frame too small"); 680 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 681 } 682 683 inline void Assembler::restore(Register s1, Register s2, Register d) { 684 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2)); 685 } 686 inline void Assembler::restore(Register s1, int simm13a, Register d) { 687 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 688 } 689 690 // pp 216 691 | 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP 27 28 #include "asm/assembler.hpp" 29 30 31 inline void Assembler::avoid_pipeline_stall() { 32 #ifdef VALIDATE_PIPELINE 33 if (_hazard_state == PcHazard) { 34 assert(is_cbcond_before() || is_rdpc_before(), "PC-hazard not preceeded by CBCOND or RDPC."); 35 assert_no_delay("Must not have PC-hazard state in delay-slot."); 36 nop(); 37 _hazard_state = NoHazard; 38 } 39 #endif 40 41 bool post_cond = is_cbcond_before(); 42 bool post_rdpc = is_rdpc_before(); 43 44 if (post_cond || post_rdpc) { 45 nop(); 46 #ifdef VALIDATE_PIPELINE 47 if (_hazard_state != PcHazard) { 48 assert(post_cond, "CBCOND before when no hazard @0x%p\n", pc()); 49 assert(post_rdpc, "RDPC before when no hazard @0x%p\n", pc()); 50 } 51 #endif 52 } 53 } 54 55 inline void Assembler::check_delay() { 56 #ifdef VALIDATE_PIPELINE 57 guarantee(_delay_state != AtDelay, "Use delayed() when filling delay-slot"); 58 _delay_state = NoDelay; 59 #endif 60 } 61 62 inline void Assembler::emit_int32(int x) { 63 check_delay(); 64 #ifdef VALIDATE_PIPELINE 65 _hazard_state = NoHazard; 66 #endif 67 AbstractAssembler::emit_int32(x); 68 } 69 70 inline void Assembler::emit_data(int x) { 71 emit_int32(x); 72 } 73 74 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { 75 relocate(rtype); 76 emit_int32(x); 77 } 78 79 inline void Assembler::emit_data(int x, RelocationHolder const &rspec) { 80 relocate(rspec); 81 emit_int32(x); 82 } 83 84 85 inline void Assembler::add(Register s1, Register s2, Register d) { 86 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2)); 140 aes_only(); 141 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D)); 142 } 143 inline void Assembler::aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d) { 144 aes_only(); 145 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D)); 146 } 147 148 // 3-operand AES instructions 149 150 inline void Assembler::aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d) { 151 aes_only(); 152 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D)); 153 } 154 inline void Assembler::aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d) { 155 aes_only(); 156 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D)); 157 } 158 159 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt) { 160 avoid_pipeline_stall(); 161 cti(); 162 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); 163 induce_delay_slot(); 164 } 165 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, Label &L) { 166 // Note[+]: All assembly emit routines using the 'target()' branch back-patch 167 // resolver must call 'avoid_pipeline_stall()' prior to calling 'target()' 168 // (we must do so even though the call will be made, as here, in the above 169 // implementation of 'bpr()', invoked below). The reason is the assumption 170 // made in 'target()', where using the current PC as the address for back- 171 // patching prevents any additional code to be emitted _after_ the address 172 // has been set (implicitly) in order to refer to the correct instruction. 173 avoid_pipeline_stall(); 174 bpr(c, a, p, s1, target(L)); 175 } 176 177 inline void Assembler::fb(Condition c, bool a, address d, relocInfo::relocType rt) { 178 v9_dep(); 179 avoid_pipeline_stall(); 180 cti(); 181 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 182 induce_delay_slot(); 183 } 184 inline void Assembler::fb(Condition c, bool a, Label &L) { 185 avoid_pipeline_stall(); 186 fb(c, a, target(L)); 187 } 188 189 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 190 avoid_pipeline_stall(); 191 cti(); 192 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 193 induce_delay_slot(); 194 } 195 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, Label &L) { 196 avoid_pipeline_stall(); 197 fbp(c, a, cc, p, target(L)); 198 } 199 200 inline void Assembler::br(Condition c, bool a, address d, relocInfo::relocType rt) { 201 v9_dep(); 202 avoid_pipeline_stall(); 203 cti(); 204 emit_data(op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 205 induce_delay_slot(); 206 } 207 inline void Assembler::br(Condition c, bool a, Label &L) { 208 avoid_pipeline_stall(); 209 br(c, a, target(L)); 210 } 211 212 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 213 avoid_pipeline_stall(); 214 cti(); 215 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 216 induce_delay_slot(); 217 } 218 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, Label &L) { 219 avoid_pipeline_stall(); 220 bp(c, a, cc, p, target(L)); 221 } 222 223 // compare and branch 224 inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label &L) { 225 avoid_pipeline_stall(); 226 cti(); 227 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); 228 induce_pc_hazard(); 229 } 230 inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label &L) { 231 avoid_pipeline_stall(); 232 cti(); 233 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); 234 induce_pc_hazard(); 235 } 236 237 inline void Assembler::call(address d, relocInfo::relocType rt) { 238 avoid_pipeline_stall(); 239 cti(); 240 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); 241 induce_delay_slot(); 242 assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 243 } 244 inline void Assembler::call(Label &L, relocInfo::relocType rt) { 245 avoid_pipeline_stall(); 246 call(target(L), rt); 247 } 248 249 inline void Assembler::call(address d, RelocationHolder const &rspec) { 250 avoid_pipeline_stall(); 251 cti(); 252 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rspec); 253 induce_delay_slot(); 254 assert(rspec.type() != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 255 } 256 257 inline void Assembler::casa(Register s1, Register s2, Register d, int ia) { 258 emit_int32(op(ldst_op) | rd(d) | op3(casa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 259 } 260 inline void Assembler::casxa(Register s1, Register s2, Register d, int ia) { 261 emit_int32(op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 262 } 263 264 inline void Assembler::udiv(Register s1, Register s2, Register d) { 265 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | rs2(s2)); 266 } 267 inline void Assembler::udiv(Register s1, int simm13a, Register d) { 268 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 269 } 270 inline void Assembler::sdiv(Register s1, Register s2, Register d) { 271 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | rs2(s2)); 272 } 273 inline void Assembler::sdiv(Register s1, int simm13a, Register d) { 361 inline void Assembler::flush(Register s1, int simm13a) { 362 emit_data(op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 363 } 364 365 inline void Assembler::flushw() { 366 emit_int32(op(arith_op) | op3(flushw_op3)); 367 } 368 369 inline void Assembler::illtrap(int const22a) { 370 emit_int32(op(branch_op) | u_field(const22a, 21, 0)); 371 } 372 373 inline void Assembler::impdep1(int id1, int const19a) { 374 emit_int32(op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); 375 } 376 inline void Assembler::impdep2(int id1, int const19a) { 377 emit_int32(op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); 378 } 379 380 inline void Assembler::jmpl(Register s1, Register s2, Register d) { 381 avoid_pipeline_stall(); 382 cti(); 383 emit_int32(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); 384 induce_delay_slot(); 385 } 386 inline void Assembler::jmpl(Register s1, int simm13a, Register d, RelocationHolder const &rspec) { 387 avoid_pipeline_stall(); 388 cti(); 389 emit_data(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 390 induce_delay_slot(); 391 } 392 393 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { 394 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2)); 395 } 396 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const &rspec) { 397 emit_data(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 398 } 399 400 inline void Assembler::ldxfsr(Register s1, Register s2) { 401 emit_int32(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2)); 402 } 403 inline void Assembler::ldxfsr(Register s1, int simm13a) { 404 emit_data(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 405 } 406 407 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d) { 408 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2)); 409 } 410 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { 678 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 679 } 680 inline void Assembler::prefetcha(Register s1, int simm13a, PrefetchFcn f) { 681 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 682 } 683 684 inline void Assembler::rdy(Register d) { 685 v9_dep(); 686 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); 687 } 688 inline void Assembler::rdccr(Register d) { 689 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); 690 } 691 inline void Assembler::rdasi(Register d) { 692 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); 693 } 694 inline void Assembler::rdtick(Register d) { 695 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); 696 } 697 inline void Assembler::rdpc(Register d) { 698 avoid_pipeline_stall(); 699 cti(); 700 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); 701 induce_pc_hazard(); 702 } 703 inline void Assembler::rdfprs(Register d) { 704 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); 705 } 706 707 inline void Assembler::rett(Register s1, Register s2) { 708 cti(); 709 emit_int32(op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); 710 induce_delay_slot(); 711 } 712 inline void Assembler::rett(Register s1, int simm13a, relocInfo::relocType rt) { 713 cti(); 714 emit_data(op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); 715 induce_delay_slot(); 716 } 717 718 inline void Assembler::save(Register s1, Register s2, Register d) { 719 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2)); 720 } 721 inline void Assembler::save(Register s1, int simm13a, Register d) { 722 // make sure frame is at least large enough for the register save area 723 assert(-simm13a >= 16 * wordSize, "frame too small"); 724 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 725 } 726 727 inline void Assembler::restore(Register s1, Register s2, Register d) { 728 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2)); 729 } 730 inline void Assembler::restore(Register s1, int simm13a, Register d) { 731 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 732 } 733 734 // pp 216 735 |