1055 // base fits into simm13 we set the constant table base to the
1056 // current PC.
1057 if (Assembler::is_simm13(table_base_offset)) {
1058 constant_table.set_table_base_offset(table_base_offset);
1059 disp = 0;
1060 } else {
1061 // Otherwise we set the constant table base offset to the
1062 // maximum negative displacement of load instructions to keep
1063 // the disp as small as possible:
1064 //
1065 // |<------------- consts_size ----------->|<- insts_offset ->|
1066 // |<--------- min_simm13 --------->|<-------- disp --------->|
1067 // \ table base
1068 table_base_offset = Assembler::min_simm13();
1069 constant_table.set_table_base_offset(table_base_offset);
1070 disp = (consts_size + insts_offset) + table_base_offset;
1071 }
1072
1073 __ rdpc(r);
1074
1075 if (disp != 0) {
1076 assert(r != O7, "need temporary");
1077 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1078 }
1079 }
1080 else {
1081 // Materialize the constant table base.
1082 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1083 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1084 AddressLiteral base(baseaddr, rspec);
1085 __ set(base, r);
1086 }
1087 }
1088
1089 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1090 if (UseRDPCForConstantTableBase) {
1091 // This is really the worst case but generally it's only 1 instruction.
1092 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1093 } else {
1094 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1095 }
8607 effect(USE labl);
8608
8609 size(8);
8610 ins_cost(BRANCH_COST);
8611 format %{ "BA $labl" %}
8612 ins_encode %{
8613 Label* L = $labl$$label;
8614 __ ba(*L);
8615 __ delayed()->nop();
8616 %}
8617 ins_avoid_back_to_back(AVOID_BEFORE);
8618 ins_pipe(br);
8619 %}
8620
8621 // Direct Branch, short with no delay slot
8622 instruct branch_short(label labl) %{
8623 match(Goto);
8624 predicate(UseCBCond);
8625 effect(USE labl);
8626
8627 size(4);
8628 ins_cost(BRANCH_COST);
8629 format %{ "BA $labl\t! short branch" %}
8630 ins_encode %{
8631 Label* L = $labl$$label;
8632 assert(__ use_cbcond(*L), "back to back cbcond");
8633 __ ba_short(*L);
8634 %}
8635 ins_short_branch(1);
8636 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
8637 ins_pipe(cbcond_reg_imm);
8638 %}
8639
8640 // Conditional Direct Branch
8641 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8642 match(If cmp icc);
8643 effect(USE labl);
8644
8645 size(8);
8646 ins_cost(BRANCH_COST);
8647 format %{ "BP$cmp $icc,$labl" %}
8948 ins_cost(BRANCH_COST);
8949 format %{ "CMP $op1,$op2\t! int\n\t"
8950 "BP$cmp $labl\t! Loop end" %}
8951 ins_encode %{
8952 Label* L = $labl$$label;
8953 Assembler::Predict predict_taken =
8954 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8955 __ cmp($op1$$Register, $op2$$constant);
8956 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8957 __ delayed()->nop();
8958 %}
8959 ins_pipe(cmp_br_reg_imm);
8960 %}
8961
8962 // Short compare and branch instructions
8963 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
8964 match(If cmp (CmpI op1 op2));
8965 predicate(UseCBCond);
8966 effect(USE labl, KILL icc);
8967
8968 size(4);
8969 ins_cost(BRANCH_COST);
8970 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
8971 ins_encode %{
8972 Label* L = $labl$$label;
8973 assert(__ use_cbcond(*L), "back to back cbcond");
8974 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
8975 %}
8976 ins_short_branch(1);
8977 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
8978 ins_pipe(cbcond_reg_reg);
8979 %}
8980
8981 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
8982 match(If cmp (CmpI op1 op2));
8983 predicate(UseCBCond);
8984 effect(USE labl, KILL icc);
8985
8986 size(4);
8987 ins_cost(BRANCH_COST);
8988 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
8989 ins_encode %{
8990 Label* L = $labl$$label;
8991 assert(__ use_cbcond(*L), "back to back cbcond");
8992 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
8993 %}
8994 ins_short_branch(1);
8995 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
8996 ins_pipe(cbcond_reg_imm);
8997 %}
8998
8999 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9000 match(If cmp (CmpU op1 op2));
9001 predicate(UseCBCond);
9002 effect(USE labl, KILL icc);
9003
9004 size(4);
9005 ins_cost(BRANCH_COST);
9006 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9007 ins_encode %{
9008 Label* L = $labl$$label;
9009 assert(__ use_cbcond(*L), "back to back cbcond");
9010 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9011 %}
9012 ins_short_branch(1);
9013 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9014 ins_pipe(cbcond_reg_reg);
9015 %}
9016
9017 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9018 match(If cmp (CmpU op1 op2));
9019 predicate(UseCBCond);
9020 effect(USE labl, KILL icc);
9021
9022 size(4);
9023 ins_cost(BRANCH_COST);
9024 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9025 ins_encode %{
9026 Label* L = $labl$$label;
9027 assert(__ use_cbcond(*L), "back to back cbcond");
9028 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9029 %}
9030 ins_short_branch(1);
9031 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9032 ins_pipe(cbcond_reg_imm);
9033 %}
9034
9035 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9036 match(If cmp (CmpL op1 op2));
9037 predicate(UseCBCond);
9038 effect(USE labl, KILL xcc);
9039
9040 size(4);
9041 ins_cost(BRANCH_COST);
9042 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9043 ins_encode %{
9044 Label* L = $labl$$label;
9045 assert(__ use_cbcond(*L), "back to back cbcond");
9046 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9047 %}
9048 ins_short_branch(1);
9049 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9050 ins_pipe(cbcond_reg_reg);
9051 %}
9052
9053 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9054 match(If cmp (CmpL op1 op2));
9055 predicate(UseCBCond);
9056 effect(USE labl, KILL xcc);
9057
9058 size(4);
9059 ins_cost(BRANCH_COST);
9060 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9061 ins_encode %{
9062 Label* L = $labl$$label;
9063 assert(__ use_cbcond(*L), "back to back cbcond");
9064 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9065 %}
9066 ins_short_branch(1);
9067 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9068 ins_pipe(cbcond_reg_imm);
9069 %}
9070
9071 // Compare Pointers and branch
9072 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9073 match(If cmp (CmpP op1 op2));
9074 predicate(UseCBCond);
9075 effect(USE labl, KILL pcc);
9076
9077 size(4);
9078 ins_cost(BRANCH_COST);
9079 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9080 ins_encode %{
9081 Label* L = $labl$$label;
9082 assert(__ use_cbcond(*L), "back to back cbcond");
9083 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9084 %}
9085 ins_short_branch(1);
9086 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9087 ins_pipe(cbcond_reg_reg);
9088 %}
9089
9090 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9091 match(If cmp (CmpP op1 null));
9092 predicate(UseCBCond);
9093 effect(USE labl, KILL pcc);
9094
9095 size(4);
9096 ins_cost(BRANCH_COST);
9097 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9098 ins_encode %{
9099 Label* L = $labl$$label;
9100 assert(__ use_cbcond(*L), "back to back cbcond");
9101 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9102 %}
9103 ins_short_branch(1);
9104 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9105 ins_pipe(cbcond_reg_reg);
9106 %}
9107
9108 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9109 match(If cmp (CmpN op1 op2));
9110 predicate(UseCBCond);
9111 effect(USE labl, KILL icc);
9112
9113 size(4);
9114 ins_cost(BRANCH_COST);
9115 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9116 ins_encode %{
9117 Label* L = $labl$$label;
9118 assert(__ use_cbcond(*L), "back to back cbcond");
9119 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9120 %}
9121 ins_short_branch(1);
9122 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9123 ins_pipe(cbcond_reg_reg);
9124 %}
9125
9126 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9127 match(If cmp (CmpN op1 null));
9128 predicate(UseCBCond);
9129 effect(USE labl, KILL icc);
9130
9131 size(4);
9132 ins_cost(BRANCH_COST);
9133 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9134 ins_encode %{
9135 Label* L = $labl$$label;
9136 assert(__ use_cbcond(*L), "back to back cbcond");
9137 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9138 %}
9139 ins_short_branch(1);
9140 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9141 ins_pipe(cbcond_reg_reg);
9142 %}
9143
9144 // Loop back branch
9145 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9146 match(CountedLoopEnd cmp (CmpI op1 op2));
9147 predicate(UseCBCond);
9148 effect(USE labl, KILL icc);
9149
9150 size(4);
9151 ins_cost(BRANCH_COST);
9152 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9153 ins_encode %{
9154 Label* L = $labl$$label;
9155 assert(__ use_cbcond(*L), "back to back cbcond");
9156 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9157 %}
9158 ins_short_branch(1);
9159 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9160 ins_pipe(cbcond_reg_reg);
9161 %}
9162
9163 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9164 match(CountedLoopEnd cmp (CmpI op1 op2));
9165 predicate(UseCBCond);
9166 effect(USE labl, KILL icc);
9167
9168 size(4);
9169 ins_cost(BRANCH_COST);
9170 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9171 ins_encode %{
9172 Label* L = $labl$$label;
9173 assert(__ use_cbcond(*L), "back to back cbcond");
9174 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9175 %}
9176 ins_short_branch(1);
9177 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9178 ins_pipe(cbcond_reg_imm);
9179 %}
9180
9181 // Branch-on-register tests all 64 bits. We assume that values
9182 // in 64-bit registers always remains zero or sign extended
9183 // unless our code munges the high bits. Interrupts can chop
9184 // the high order bits to zero or sign at any time.
9185 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9186 match(If cmp (CmpI op1 zero));
9187 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9188 effect(USE labl);
|
1055 // base fits into simm13 we set the constant table base to the
1056 // current PC.
1057 if (Assembler::is_simm13(table_base_offset)) {
1058 constant_table.set_table_base_offset(table_base_offset);
1059 disp = 0;
1060 } else {
1061 // Otherwise we set the constant table base offset to the
1062 // maximum negative displacement of load instructions to keep
1063 // the disp as small as possible:
1064 //
1065 // |<------------- consts_size ----------->|<- insts_offset ->|
1066 // |<--------- min_simm13 --------->|<-------- disp --------->|
1067 // \ table base
1068 table_base_offset = Assembler::min_simm13();
1069 constant_table.set_table_base_offset(table_base_offset);
1070 disp = (consts_size + insts_offset) + table_base_offset;
1071 }
1072
1073 __ rdpc(r);
1074
1075 if (disp == 0) {
1076 // Emitting an additional 'nop' instruction in order not to cause a code
1077 // size adjustment in the code following the table setup (if the instruction
1078 // immediately following after this section is a CTI).
1079 __ nop();
1080 }
1081 else {
1082 assert(r != O7, "need temporary");
1083 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1084 }
1085 }
1086 else {
1087 // Materialize the constant table base.
1088 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1089 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1090 AddressLiteral base(baseaddr, rspec);
1091 __ set(base, r);
1092 }
1093 }
1094
1095 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1096 if (UseRDPCForConstantTableBase) {
1097 // This is really the worst case but generally it's only 1 instruction.
1098 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1099 } else {
1100 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1101 }
8613 effect(USE labl);
8614
8615 size(8);
8616 ins_cost(BRANCH_COST);
8617 format %{ "BA $labl" %}
8618 ins_encode %{
8619 Label* L = $labl$$label;
8620 __ ba(*L);
8621 __ delayed()->nop();
8622 %}
8623 ins_avoid_back_to_back(AVOID_BEFORE);
8624 ins_pipe(br);
8625 %}
8626
8627 // Direct Branch, short with no delay slot
8628 instruct branch_short(label labl) %{
8629 match(Goto);
8630 predicate(UseCBCond);
8631 effect(USE labl);
8632
8633 size(4); // Assuming no NOP inserted.
8634 ins_cost(BRANCH_COST);
8635 format %{ "BA $labl\t! short branch" %}
8636 ins_encode %{
8637 Label* L = $labl$$label;
8638 assert(__ use_cbcond(*L), "back to back cbcond");
8639 __ ba_short(*L);
8640 %}
8641 ins_short_branch(1);
8642 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
8643 ins_pipe(cbcond_reg_imm);
8644 %}
8645
8646 // Conditional Direct Branch
8647 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8648 match(If cmp icc);
8649 effect(USE labl);
8650
8651 size(8);
8652 ins_cost(BRANCH_COST);
8653 format %{ "BP$cmp $icc,$labl" %}
8954 ins_cost(BRANCH_COST);
8955 format %{ "CMP $op1,$op2\t! int\n\t"
8956 "BP$cmp $labl\t! Loop end" %}
8957 ins_encode %{
8958 Label* L = $labl$$label;
8959 Assembler::Predict predict_taken =
8960 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
8961 __ cmp($op1$$Register, $op2$$constant);
8962 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
8963 __ delayed()->nop();
8964 %}
8965 ins_pipe(cmp_br_reg_imm);
8966 %}
8967
8968 // Short compare and branch instructions
8969 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
8970 match(If cmp (CmpI op1 op2));
8971 predicate(UseCBCond);
8972 effect(USE labl, KILL icc);
8973
8974 size(4); // Assuming no NOP inserted.
8975 ins_cost(BRANCH_COST);
8976 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
8977 ins_encode %{
8978 Label* L = $labl$$label;
8979 assert(__ use_cbcond(*L), "back to back cbcond");
8980 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
8981 %}
8982 ins_short_branch(1);
8983 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
8984 ins_pipe(cbcond_reg_reg);
8985 %}
8986
8987 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
8988 match(If cmp (CmpI op1 op2));
8989 predicate(UseCBCond);
8990 effect(USE labl, KILL icc);
8991
8992 size(4); // Assuming no NOP inserted.
8993 ins_cost(BRANCH_COST);
8994 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
8995 ins_encode %{
8996 Label* L = $labl$$label;
8997 assert(__ use_cbcond(*L), "back to back cbcond");
8998 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
8999 %}
9000 ins_short_branch(1);
9001 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9002 ins_pipe(cbcond_reg_imm);
9003 %}
9004
9005 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9006 match(If cmp (CmpU op1 op2));
9007 predicate(UseCBCond);
9008 effect(USE labl, KILL icc);
9009
9010 size(4); // Assuming no NOP inserted.
9011 ins_cost(BRANCH_COST);
9012 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9013 ins_encode %{
9014 Label* L = $labl$$label;
9015 assert(__ use_cbcond(*L), "back to back cbcond");
9016 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9017 %}
9018 ins_short_branch(1);
9019 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9020 ins_pipe(cbcond_reg_reg);
9021 %}
9022
9023 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9024 match(If cmp (CmpU op1 op2));
9025 predicate(UseCBCond);
9026 effect(USE labl, KILL icc);
9027
9028 size(4); // Assuming no NOP inserted.
9029 ins_cost(BRANCH_COST);
9030 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9031 ins_encode %{
9032 Label* L = $labl$$label;
9033 assert(__ use_cbcond(*L), "back to back cbcond");
9034 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9035 %}
9036 ins_short_branch(1);
9037 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9038 ins_pipe(cbcond_reg_imm);
9039 %}
9040
9041 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9042 match(If cmp (CmpL op1 op2));
9043 predicate(UseCBCond);
9044 effect(USE labl, KILL xcc);
9045
9046 size(4); // Assuming no NOP inserted.
9047 ins_cost(BRANCH_COST);
9048 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9049 ins_encode %{
9050 Label* L = $labl$$label;
9051 assert(__ use_cbcond(*L), "back to back cbcond");
9052 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9053 %}
9054 ins_short_branch(1);
9055 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9056 ins_pipe(cbcond_reg_reg);
9057 %}
9058
9059 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9060 match(If cmp (CmpL op1 op2));
9061 predicate(UseCBCond);
9062 effect(USE labl, KILL xcc);
9063
9064 size(4); // Assuming no NOP inserted.
9065 ins_cost(BRANCH_COST);
9066 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9067 ins_encode %{
9068 Label* L = $labl$$label;
9069 assert(__ use_cbcond(*L), "back to back cbcond");
9070 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9071 %}
9072 ins_short_branch(1);
9073 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9074 ins_pipe(cbcond_reg_imm);
9075 %}
9076
9077 // Compare Pointers and branch
9078 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9079 match(If cmp (CmpP op1 op2));
9080 predicate(UseCBCond);
9081 effect(USE labl, KILL pcc);
9082
9083 size(4); // Assuming no NOP inserted.
9084 ins_cost(BRANCH_COST);
9085 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9086 ins_encode %{
9087 Label* L = $labl$$label;
9088 assert(__ use_cbcond(*L), "back to back cbcond");
9089 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9090 %}
9091 ins_short_branch(1);
9092 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9093 ins_pipe(cbcond_reg_reg);
9094 %}
9095
9096 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9097 match(If cmp (CmpP op1 null));
9098 predicate(UseCBCond);
9099 effect(USE labl, KILL pcc);
9100
9101 size(4); // Assuming no NOP inserted.
9102 ins_cost(BRANCH_COST);
9103 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9104 ins_encode %{
9105 Label* L = $labl$$label;
9106 assert(__ use_cbcond(*L), "back to back cbcond");
9107 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9108 %}
9109 ins_short_branch(1);
9110 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9111 ins_pipe(cbcond_reg_reg);
9112 %}
9113
9114 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9115 match(If cmp (CmpN op1 op2));
9116 predicate(UseCBCond);
9117 effect(USE labl, KILL icc);
9118
9119 size(4); // Assuming no NOP inserted.
9120 ins_cost(BRANCH_COST);
9121 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9122 ins_encode %{
9123 Label* L = $labl$$label;
9124 assert(__ use_cbcond(*L), "back to back cbcond");
9125 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9126 %}
9127 ins_short_branch(1);
9128 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9129 ins_pipe(cbcond_reg_reg);
9130 %}
9131
9132 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9133 match(If cmp (CmpN op1 null));
9134 predicate(UseCBCond);
9135 effect(USE labl, KILL icc);
9136
9137 size(4); // Assuming no NOP inserted.
9138 ins_cost(BRANCH_COST);
9139 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9140 ins_encode %{
9141 Label* L = $labl$$label;
9142 assert(__ use_cbcond(*L), "back to back cbcond");
9143 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9144 %}
9145 ins_short_branch(1);
9146 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9147 ins_pipe(cbcond_reg_reg);
9148 %}
9149
9150 // Loop back branch
9151 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9152 match(CountedLoopEnd cmp (CmpI op1 op2));
9153 predicate(UseCBCond);
9154 effect(USE labl, KILL icc);
9155
9156 size(4); // Assuming no NOP inserted.
9157 ins_cost(BRANCH_COST);
9158 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9159 ins_encode %{
9160 Label* L = $labl$$label;
9161 assert(__ use_cbcond(*L), "back to back cbcond");
9162 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9163 %}
9164 ins_short_branch(1);
9165 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9166 ins_pipe(cbcond_reg_reg);
9167 %}
9168
9169 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9170 match(CountedLoopEnd cmp (CmpI op1 op2));
9171 predicate(UseCBCond);
9172 effect(USE labl, KILL icc);
9173
9174 size(4); // Assuming no NOP inserted.
9175 ins_cost(BRANCH_COST);
9176 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9177 ins_encode %{
9178 Label* L = $labl$$label;
9179 assert(__ use_cbcond(*L), "back to back cbcond");
9180 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9181 %}
9182 ins_short_branch(1);
9183 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9184 ins_pipe(cbcond_reg_imm);
9185 %}
9186
9187 // Branch-on-register tests all 64 bits. We assume that values
9188 // in 64-bit registers always remains zero or sign extended
9189 // unless our code munges the high bits. Interrupts can chop
9190 // the high order bits to zero or sign at any time.
9191 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9192 match(If cmp (CmpI op1 zero));
9193 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9194 effect(USE labl);
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