1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP 27 28 #include "asm/assembler.hpp" 29 30 31 inline void Assembler::insert_nop_after_cbcond() { 32 if (UseCBCond && cbcond_before()) { 33 nop(); 34 } 35 } 36 37 inline void Assembler::check_delay() { 38 #ifdef CHECK_DELAY 39 guarantee(delay_state != at_delay_slot, "must say delayed() when filling delay slot"); 40 delay_state = no_delay; 41 #endif 42 } 43 44 inline void Assembler::emit_int32(int x) { 45 check_delay(); 46 AbstractAssembler::emit_int32(x); 47 } 48 49 inline void Assembler::emit_data(int x) { 50 emit_int32(x); 51 } 52 53 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { 54 relocate(rtype); 55 emit_int32(x); 56 } 57 58 inline void Assembler::emit_data(int x, RelocationHolder const &rspec) { 59 relocate(rspec); 60 emit_int32(x); 61 } 62 63 64 inline void Assembler::add(Register s1, Register s2, Register d) { 65 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2)); 66 } 67 inline void Assembler::add(Register s1, int simm13a, Register d) { 68 emit_int32(op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 69 } 70 71 inline void Assembler::addcc(Register s1, Register s2, Register d) { 72 emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 73 } 74 inline void Assembler::addcc(Register s1, int simm13a, Register d) { 75 emit_int32(op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 76 } 77 inline void Assembler::addc(Register s1, Register s2, Register d) { 78 emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | rs2(s2)); 79 } 80 inline void Assembler::addc(Register s1, int simm13a, Register d) { 81 emit_int32(op(arith_op) | rd(d) | op3(addc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 82 } 83 inline void Assembler::addccc(Register s1, Register s2, Register d) { 84 emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 85 } 86 inline void Assembler::addccc(Register s1, int simm13a, Register d) { 87 emit_int32(op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 88 } 89 90 inline void Assembler::aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 91 aes_only(); 92 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D)); 93 } 94 inline void Assembler::aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 95 aes_only(); 96 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D)); 97 } 98 inline void Assembler::aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 99 aes_only(); 100 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D)); 101 } 102 inline void Assembler::aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 103 aes_only(); 104 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D)); 105 } 106 inline void Assembler::aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 107 aes_only(); 108 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D)); 109 } 110 inline void Assembler::aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 111 aes_only(); 112 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D)); 113 } 114 inline void Assembler::aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 115 aes_only(); 116 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D)); 117 } 118 inline void Assembler::aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d) { 119 aes_only(); 120 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D)); 121 } 122 inline void Assembler::aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d) { 123 aes_only(); 124 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D)); 125 } 126 127 // 3-operand AES instructions 128 129 inline void Assembler::aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d) { 130 aes_only(); 131 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D)); 132 } 133 inline void Assembler::aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d) { 134 aes_only(); 135 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D)); 136 } 137 138 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt) { 139 insert_nop_after_cbcond(); cti(); 140 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); 141 has_delay_slot(); 142 } 143 inline void Assembler::bpr(RCondition c, bool a, Predict p, Register s1, Label &L) { 144 insert_nop_after_cbcond(); 145 bpr(c, a, p, s1, target(L)); 146 } 147 148 inline void Assembler::fb(Condition c, bool a, address d, relocInfo::relocType rt) { 149 v9_dep(); 150 insert_nop_after_cbcond(); cti(); 151 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 152 has_delay_slot(); 153 } 154 inline void Assembler::fb(Condition c, bool a, Label &L) { 155 insert_nop_after_cbcond(); 156 fb(c, a, target(L)); 157 } 158 159 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 160 insert_nop_after_cbcond(); cti(); 161 emit_data(op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 162 has_delay_slot(); 163 } 164 inline void Assembler::fbp(Condition c, bool a, CC cc, Predict p, Label &L) { 165 insert_nop_after_cbcond(); 166 fbp(c, a, cc, p, target(L)); 167 } 168 169 inline void Assembler::br(Condition c, bool a, address d, relocInfo::relocType rt) { 170 v9_dep(); 171 insert_nop_after_cbcond(); cti(); 172 emit_data(op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); 173 has_delay_slot(); 174 } 175 inline void Assembler::br(Condition c, bool a, Label &L) { 176 insert_nop_after_cbcond(); 177 br(c, a, target(L)); 178 } 179 180 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt) { 181 insert_nop_after_cbcond(); cti(); 182 emit_data(op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); 183 has_delay_slot(); 184 } 185 inline void Assembler::bp(Condition c, bool a, CC cc, Predict p, Label &L) { 186 insert_nop_after_cbcond(); 187 bp(c, a, cc, p, target(L)); 188 } 189 190 // compare and branch 191 inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label &L) { 192 cti(); no_cbcond_before(); 193 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); 194 } 195 inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label &L) { 196 cti(); no_cbcond_before(); 197 emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); 198 } 199 200 inline void Assembler::call(address d, relocInfo::relocType rt) { 201 insert_nop_after_cbcond(); cti(); 202 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); 203 has_delay_slot(); 204 assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 205 } 206 inline void Assembler::call(Label &L, relocInfo::relocType rt) { 207 insert_nop_after_cbcond(); 208 call(target(L), rt); 209 } 210 211 inline void Assembler::call(address d, RelocationHolder const &rspec) { 212 insert_nop_after_cbcond(); cti(); 213 emit_data(op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rspec); 214 has_delay_slot(); 215 assert(rspec.type() != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); 216 } 217 218 inline void Assembler::casa(Register s1, Register s2, Register d, int ia) { 219 emit_int32(op(ldst_op) | rd(d) | op3(casa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 220 } 221 inline void Assembler::casxa(Register s1, Register s2, Register d, int ia) { 222 emit_int32(op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); 223 } 224 225 inline void Assembler::udiv(Register s1, Register s2, Register d) { 226 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | rs2(s2)); 227 } 228 inline void Assembler::udiv(Register s1, int simm13a, Register d) { 229 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 230 } 231 inline void Assembler::sdiv(Register s1, Register s2, Register d) { 232 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | rs2(s2)); 233 } 234 inline void Assembler::sdiv(Register s1, int simm13a, Register d) { 235 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 236 } 237 inline void Assembler::udivcc(Register s1, Register s2, Register d) { 238 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 239 } 240 inline void Assembler::udivcc(Register s1, int simm13a, Register d) { 241 emit_int32(op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 242 } 243 inline void Assembler::sdivcc(Register s1, Register s2, Register d) { 244 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 245 } 246 inline void Assembler::sdivcc(Register s1, int simm13a, Register d) { 247 emit_int32(op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 248 } 249 250 inline void Assembler::done() { 251 cti(); 252 emit_int32(op(arith_op) | fcn(0) | op3(done_op3)); 253 } 254 inline void Assembler::retry() { 255 cti(); 256 emit_int32(op(arith_op) | fcn(1) | op3(retry_op3)); 257 } 258 259 inline void Assembler::fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 260 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); 261 } 262 inline void Assembler::fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 263 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); 264 } 265 266 inline void Assembler::fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { 267 emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); 268 } 269 inline void Assembler::fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { 270 emit_int32(op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); 271 } 272 273 inline void Assembler::ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 274 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); 275 } 276 inline void Assembler::ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 277 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); 278 } 279 280 inline void Assembler::ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d) { 281 emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); 282 } 283 284 inline void Assembler::fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 285 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); 286 } 287 inline void Assembler::fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 288 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); 289 } 290 291 inline void Assembler::fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 292 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); 293 } 294 inline void Assembler::fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 295 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); 296 } 297 inline void Assembler::fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 298 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); 299 } 300 inline void Assembler::fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 301 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); 302 } 303 inline void Assembler::fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d) { 304 emit_int32(op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); 305 } 306 inline void Assembler::fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 307 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); 308 } 309 310 inline void Assembler::fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d) { 311 vis1_only(); 312 emit_int32(op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); 313 } 314 315 inline void Assembler::fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) { 316 emit_int32(op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); 317 } 318 319 inline void Assembler::flush(Register s1, Register s2) { 320 emit_int32(op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); 321 } 322 inline void Assembler::flush(Register s1, int simm13a) { 323 emit_data(op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 324 } 325 326 inline void Assembler::flushw() { 327 emit_int32(op(arith_op) | op3(flushw_op3)); 328 } 329 330 inline void Assembler::illtrap(int const22a) { 331 emit_int32(op(branch_op) | u_field(const22a, 21, 0)); 332 } 333 334 inline void Assembler::impdep1(int id1, int const19a) { 335 emit_int32(op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); 336 } 337 inline void Assembler::impdep2(int id1, int const19a) { 338 emit_int32(op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); 339 } 340 341 inline void Assembler::jmpl(Register s1, Register s2, Register d) { 342 insert_nop_after_cbcond(); cti(); 343 emit_int32(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); 344 has_delay_slot(); 345 } 346 inline void Assembler::jmpl(Register s1, int simm13a, Register d, RelocationHolder const &rspec) { 347 insert_nop_after_cbcond(); cti(); 348 emit_data(op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 349 has_delay_slot(); 350 } 351 352 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { 353 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2)); 354 } 355 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const &rspec) { 356 emit_data(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); 357 } 358 359 inline void Assembler::ldxfsr(Register s1, Register s2) { 360 emit_int32(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2)); 361 } 362 inline void Assembler::ldxfsr(Register s1, int simm13a) { 363 emit_data(op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 364 } 365 366 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d) { 367 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2)); 368 } 369 inline void Assembler::ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { 370 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 371 } 372 373 inline void Assembler::ldsb(Register s1, Register s2, Register d) { 374 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2)); 375 } 376 inline void Assembler::ldsb(Register s1, int simm13a, Register d) { 377 emit_data(op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 378 } 379 380 inline void Assembler::ldsh(Register s1, Register s2, Register d) { 381 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2)); 382 } 383 inline void Assembler::ldsh(Register s1, int simm13a, Register d) { 384 emit_data(op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 385 } 386 inline void Assembler::ldsw(Register s1, Register s2, Register d) { 387 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2)); 388 } 389 inline void Assembler::ldsw(Register s1, int simm13a, Register d) { 390 emit_data(op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 391 } 392 inline void Assembler::ldub(Register s1, Register s2, Register d) { 393 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2)); 394 } 395 inline void Assembler::ldub(Register s1, int simm13a, Register d) { 396 emit_data(op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 397 } 398 inline void Assembler::lduh(Register s1, Register s2, Register d) { 399 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2)); 400 } 401 inline void Assembler::lduh(Register s1, int simm13a, Register d) { 402 emit_data(op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 403 } 404 inline void Assembler::lduw(Register s1, Register s2, Register d) { 405 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2)); 406 } 407 inline void Assembler::lduw(Register s1, int simm13a, Register d) { 408 emit_data(op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 409 } 410 411 inline void Assembler::ldx(Register s1, Register s2, Register d) { 412 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2)); 413 } 414 inline void Assembler::ldx(Register s1, int simm13a, Register d) { 415 emit_data(op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 416 } 417 inline void Assembler::ldd(Register s1, Register s2, Register d) { 418 v9_dep(); 419 assert(d->is_even(), "not even"); 420 emit_int32(op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2)); 421 } 422 inline void Assembler::ldd(Register s1, int simm13a, Register d) { 423 v9_dep(); 424 assert(d->is_even(), "not even"); 425 emit_data(op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 426 } 427 428 inline void Assembler::ldsba(Register s1, Register s2, int ia, Register d) { 429 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 430 } 431 inline void Assembler::ldsba(Register s1, int simm13a, Register d) { 432 emit_int32(op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 433 } 434 inline void Assembler::ldsha(Register s1, Register s2, int ia, Register d) { 435 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 436 } 437 inline void Assembler::ldsha(Register s1, int simm13a, Register d) { 438 emit_int32(op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 439 } 440 inline void Assembler::ldswa(Register s1, Register s2, int ia, Register d) { 441 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 442 } 443 inline void Assembler::ldswa(Register s1, int simm13a, Register d) { 444 emit_int32(op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 445 } 446 inline void Assembler::lduba(Register s1, Register s2, int ia, Register d) { 447 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 448 } 449 inline void Assembler::lduba(Register s1, int simm13a, Register d) { 450 emit_int32(op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 451 } 452 inline void Assembler::lduha(Register s1, Register s2, int ia, Register d) { 453 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 454 } 455 inline void Assembler::lduha(Register s1, int simm13a, Register d) { 456 emit_int32(op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 457 } 458 inline void Assembler::lduwa(Register s1, Register s2, int ia, Register d) { 459 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 460 } 461 inline void Assembler::lduwa(Register s1, int simm13a, Register d) { 462 emit_int32(op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 463 } 464 inline void Assembler::ldxa(Register s1, Register s2, int ia, Register d) { 465 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 466 } 467 inline void Assembler::ldxa(Register s1, int simm13a, Register d) { 468 emit_int32(op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 469 } 470 471 inline void Assembler::and3(Register s1, Register s2, Register d) { 472 emit_int32(op(arith_op) | rd(d) | op3(and_op3) | rs1(s1) | rs2(s2)); 473 } 474 inline void Assembler::and3(Register s1, int simm13a, Register d) { 475 emit_int32(op(arith_op) | rd(d) | op3(and_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 476 } 477 inline void Assembler::andcc(Register s1, Register s2, Register d) { 478 emit_int32(op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 479 } 480 inline void Assembler::andcc(Register s1, int simm13a, Register d) { 481 emit_int32(op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 482 } 483 inline void Assembler::andn(Register s1, Register s2, Register d) { 484 emit_int32(op(arith_op) | rd(d) | op3(andn_op3) | rs1(s1) | rs2(s2)); 485 } 486 inline void Assembler::andn(Register s1, int simm13a, Register d) { 487 emit_int32(op(arith_op) | rd(d) | op3(andn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 488 } 489 inline void Assembler::andncc(Register s1, Register s2, Register d) { 490 emit_int32(op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 491 } 492 inline void Assembler::andncc(Register s1, int simm13a, Register d) { 493 emit_int32(op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 494 } 495 inline void Assembler::or3(Register s1, Register s2, Register d) { 496 emit_int32(op(arith_op) | rd(d) | op3(or_op3) | rs1(s1) | rs2(s2)); 497 } 498 inline void Assembler::or3(Register s1, int simm13a, Register d) { 499 emit_int32(op(arith_op) | rd(d) | op3(or_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 500 } 501 inline void Assembler::orcc(Register s1, Register s2, Register d) { 502 emit_int32(op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 503 } 504 inline void Assembler::orcc(Register s1, int simm13a, Register d) { 505 emit_int32(op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 506 } 507 inline void Assembler::orn(Register s1, Register s2, Register d) { 508 emit_int32(op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2)); 509 } 510 inline void Assembler::orn(Register s1, int simm13a, Register d) { 511 emit_int32(op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 512 } 513 inline void Assembler::orncc(Register s1, Register s2, Register d) { 514 emit_int32(op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 515 } 516 inline void Assembler::orncc(Register s1, int simm13a, Register d) { 517 emit_int32(op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 518 } 519 inline void Assembler::xor3(Register s1, Register s2, Register d) { 520 emit_int32(op(arith_op) | rd(d) | op3(xor_op3) | rs1(s1) | rs2(s2)); 521 } 522 inline void Assembler::xor3(Register s1, int simm13a, Register d) { 523 emit_int32(op(arith_op) | rd(d) | op3(xor_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 524 } 525 inline void Assembler::xorcc(Register s1, Register s2, Register d) { 526 emit_int32(op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 527 } 528 inline void Assembler::xorcc(Register s1, int simm13a, Register d) { 529 emit_int32(op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 530 } 531 inline void Assembler::xnor(Register s1, Register s2, Register d) { 532 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3) | rs1(s1) | rs2(s2)); 533 } 534 inline void Assembler::xnor(Register s1, int simm13a, Register d) { 535 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 536 } 537 inline void Assembler::xnorcc(Register s1, Register s2, Register d) { 538 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 539 } 540 inline void Assembler::xnorcc(Register s1, int simm13a, Register d) { 541 emit_int32(op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 542 } 543 544 inline void Assembler::membar(Membar_mask_bits const7a) { 545 emit_int32(op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field(int(const7a), 6, 0)); 546 } 547 548 inline void Assembler::fmov(FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d) { 549 emit_int32(op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); 550 } 551 552 inline void Assembler::fmov(FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d) { 553 emit_int32(op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); 554 } 555 556 inline void Assembler::movcc(Condition c, bool floatCC, CC cca, Register s2, Register d) { 557 emit_int32(op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2)); 558 } 559 inline void Assembler::movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d) { 560 emit_int32(op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11)); 561 } 562 563 inline void Assembler::movr(RCondition c, Register s1, Register s2, Register d) { 564 emit_int32(op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2)); 565 } 566 inline void Assembler::movr(RCondition c, Register s1, int simm10a, Register d) { 567 emit_int32(op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10)); 568 } 569 570 inline void Assembler::mulx(Register s1, Register s2, Register d) { 571 emit_int32(op(arith_op) | rd(d) | op3(mulx_op3) | rs1(s1) | rs2(s2)); 572 } 573 inline void Assembler::mulx(Register s1, int simm13a, Register d) { 574 emit_int32(op(arith_op) | rd(d) | op3(mulx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 575 } 576 inline void Assembler::sdivx(Register s1, Register s2, Register d) { 577 emit_int32(op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2)); 578 } 579 inline void Assembler::sdivx(Register s1, int simm13a, Register d) { 580 emit_int32(op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 581 } 582 inline void Assembler::udivx(Register s1, Register s2, Register d) { 583 emit_int32(op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2)); 584 } 585 inline void Assembler::udivx(Register s1, int simm13a, Register d) { 586 emit_int32(op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 587 } 588 589 inline void Assembler::umul(Register s1, Register s2, Register d) { 590 emit_int32(op(arith_op) | rd(d) | op3(umul_op3) | rs1(s1) | rs2(s2)); 591 } 592 inline void Assembler::umul(Register s1, int simm13a, Register d) { 593 emit_int32(op(arith_op) | rd(d) | op3(umul_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 594 } 595 inline void Assembler::smul(Register s1, Register s2, Register d) { 596 emit_int32(op(arith_op) | rd(d) | op3(smul_op3) | rs1(s1) | rs2(s2)); 597 } 598 inline void Assembler::smul(Register s1, int simm13a, Register d) { 599 emit_int32(op(arith_op) | rd(d) | op3(smul_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 600 } 601 inline void Assembler::umulcc(Register s1, Register s2, Register d) { 602 emit_int32(op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 603 } 604 inline void Assembler::umulcc(Register s1, int simm13a, Register d) { 605 emit_int32(op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 606 } 607 inline void Assembler::smulcc(Register s1, Register s2, Register d) { 608 emit_int32(op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 609 } 610 inline void Assembler::smulcc(Register s1, int simm13a, Register d) { 611 emit_int32(op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 612 } 613 614 inline void Assembler::nop() { 615 emit_int32(op(branch_op) | op2(sethi_op2)); 616 } 617 618 inline void Assembler::sw_count() { 619 emit_int32(op(branch_op) | op2(sethi_op2) | 0x3f0); 620 } 621 622 inline void Assembler::popc(Register s, Register d) { 623 emit_int32(op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); 624 } 625 inline void Assembler::popc(int simm13a, Register d) { 626 emit_int32(op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); 627 } 628 629 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { 630 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2)); 631 } 632 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { 633 emit_data(op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 634 } 635 636 inline void Assembler::prefetcha(Register s1, Register s2, int ia, PrefetchFcn f) { 637 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 638 } 639 inline void Assembler::prefetcha(Register s1, int simm13a, PrefetchFcn f) { 640 emit_int32(op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 641 } 642 643 inline void Assembler::rdy(Register d) { 644 v9_dep(); 645 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); 646 } 647 inline void Assembler::rdccr(Register d) { 648 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); 649 } 650 inline void Assembler::rdasi(Register d) { 651 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); 652 } 653 inline void Assembler::rdtick(Register d) { 654 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); 655 } 656 inline void Assembler::rdpc(Register d) { 657 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); 658 } 659 inline void Assembler::rdfprs(Register d) { 660 emit_int32(op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); 661 } 662 663 inline void Assembler::rett(Register s1, Register s2) { 664 cti(); 665 emit_int32(op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); 666 has_delay_slot(); 667 } 668 inline void Assembler::rett(Register s1, int simm13a, relocInfo::relocType rt) { 669 cti(); 670 emit_data(op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); 671 has_delay_slot(); 672 } 673 674 inline void Assembler::save(Register s1, Register s2, Register d) { 675 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2)); 676 } 677 inline void Assembler::save(Register s1, int simm13a, Register d) { 678 // make sure frame is at least large enough for the register save area 679 assert(-simm13a >= 16 * wordSize, "frame too small"); 680 emit_int32(op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 681 } 682 683 inline void Assembler::restore(Register s1, Register s2, Register d) { 684 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2)); 685 } 686 inline void Assembler::restore(Register s1, int simm13a, Register d) { 687 emit_int32(op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 688 } 689 690 // pp 216 691 692 inline void Assembler::saved() { 693 emit_int32(op(arith_op) | fcn(0) | op3(saved_op3)); 694 } 695 inline void Assembler::restored() { 696 emit_int32(op(arith_op) | fcn(1) | op3(saved_op3)); 697 } 698 699 inline void Assembler::sethi(int imm22a, Register d, RelocationHolder const &rspec) { 700 emit_data(op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); 701 } 702 703 inline void Assembler::sll(Register s1, Register s2, Register d) { 704 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2)); 705 } 706 inline void Assembler::sll(Register s1, int imm5a, Register d) { 707 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 708 } 709 inline void Assembler::srl(Register s1, Register s2, Register d) { 710 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2)); 711 } 712 inline void Assembler::srl(Register s1, int imm5a, Register d) { 713 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 714 } 715 inline void Assembler::sra(Register s1, Register s2, Register d) { 716 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2)); 717 } 718 inline void Assembler::sra(Register s1, int imm5a, Register d) { 719 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0)); 720 } 721 722 inline void Assembler::sllx(Register s1, Register s2, Register d) { 723 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2)); 724 } 725 inline void Assembler::sllx(Register s1, int imm6a, Register d) { 726 emit_int32(op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 727 } 728 inline void Assembler::srlx(Register s1, Register s2, Register d) { 729 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2)); 730 } 731 inline void Assembler::srlx(Register s1, int imm6a, Register d) { 732 emit_int32(op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 733 } 734 inline void Assembler::srax(Register s1, Register s2, Register d) { 735 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2)); 736 } 737 inline void Assembler::srax(Register s1, int imm6a, Register d) { 738 emit_int32(op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0)); 739 } 740 741 inline void Assembler::sir(int simm13a) { 742 emit_int32(op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); 743 } 744 745 // pp 221 746 747 inline void Assembler::stbar() { 748 emit_int32(op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); 749 } 750 751 // pp 222 752 753 inline void Assembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { 754 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2)); 755 } 756 inline void Assembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { 757 emit_data(op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 758 } 759 760 inline void Assembler::stxfsr(Register s1, Register s2) { 761 emit_int32(op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2)); 762 } 763 inline void Assembler::stxfsr(Register s1, int simm13a) { 764 emit_data(op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 765 } 766 767 inline void Assembler::stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia) { 768 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2)); 769 } 770 inline void Assembler::stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { 771 emit_int32(op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); 772 } 773 774 // p 226 775 776 inline void Assembler::stb(Register d, Register s1, Register s2) { 777 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2)); 778 } 779 inline void Assembler::stb(Register d, Register s1, int simm13a) { 780 emit_data(op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 781 } 782 inline void Assembler::sth(Register d, Register s1, Register s2) { 783 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2)); 784 } 785 inline void Assembler::sth(Register d, Register s1, int simm13a) { 786 emit_data(op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 787 } 788 inline void Assembler::stw(Register d, Register s1, Register s2) { 789 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2)); 790 } 791 inline void Assembler::stw(Register d, Register s1, int simm13a) { 792 emit_data(op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 793 } 794 795 796 inline void Assembler::stx(Register d, Register s1, Register s2) { 797 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2)); 798 } 799 inline void Assembler::stx(Register d, Register s1, int simm13a) { 800 emit_data(op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 801 } 802 inline void Assembler::std(Register d, Register s1, Register s2) { 803 v9_dep(); 804 assert(d->is_even(), "not even"); 805 emit_int32(op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2)); 806 } 807 inline void Assembler::std(Register d, Register s1, int simm13a) { 808 v9_dep(); 809 assert(d->is_even(), "not even"); 810 emit_data(op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 811 } 812 813 inline void Assembler::stba(Register d, Register s1, Register s2, int ia) { 814 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 815 } 816 inline void Assembler::stba(Register d, Register s1, int simm13a) { 817 emit_int32(op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 818 } 819 inline void Assembler::stha(Register d, Register s1, Register s2, int ia) { 820 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 821 } 822 inline void Assembler::stha(Register d, Register s1, int simm13a) { 823 emit_int32(op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 824 } 825 inline void Assembler::stwa(Register d, Register s1, Register s2, int ia) { 826 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 827 } 828 inline void Assembler::stwa(Register d, Register s1, int simm13a) { 829 emit_int32(op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 830 } 831 inline void Assembler::stxa(Register d, Register s1, Register s2, int ia) { 832 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 833 } 834 inline void Assembler::stxa(Register d, Register s1, int simm13a) { 835 emit_int32(op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 836 } 837 inline void Assembler::stda(Register d, Register s1, Register s2, int ia) { 838 emit_int32(op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 839 } 840 inline void Assembler::stda(Register d, Register s1, int simm13a) { 841 emit_int32(op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 842 } 843 844 // pp 230 845 846 inline void Assembler::sub(Register s1, Register s2, Register d) { 847 emit_int32(op(arith_op) | rd(d) | op3(sub_op3) | rs1(s1) | rs2(s2)); 848 } 849 inline void Assembler::sub(Register s1, int simm13a, Register d) { 850 emit_int32(op(arith_op) | rd(d) | op3(sub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 851 } 852 853 inline void Assembler::subcc(Register s1, Register s2, Register d) { 854 emit_int32(op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 855 } 856 inline void Assembler::subcc(Register s1, int simm13a, Register d) { 857 emit_int32(op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 858 } 859 inline void Assembler::subc(Register s1, Register s2, Register d) { 860 emit_int32(op(arith_op) | rd(d) | op3(subc_op3) | rs1(s1) | rs2(s2)); 861 } 862 inline void Assembler::subc(Register s1, int simm13a, Register d) { 863 emit_int32(op(arith_op) | rd(d) | op3(subc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 864 } 865 inline void Assembler::subccc(Register s1, Register s2, Register d) { 866 emit_int32(op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); 867 } 868 inline void Assembler::subccc(Register s1, int simm13a, Register d) { 869 emit_int32(op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 870 } 871 872 // pp 231 873 874 inline void Assembler::swap(Register s1, Register s2, Register d) { 875 v9_dep(); 876 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2)); 877 } 878 inline void Assembler::swap(Register s1, int simm13a, Register d) { 879 v9_dep(); 880 emit_data(op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 881 } 882 883 inline void Assembler::swapa(Register s1, Register s2, int ia, Register d) { 884 v9_dep(); 885 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 886 } 887 inline void Assembler::swapa(Register s1, int simm13a, Register d) { 888 v9_dep(); 889 emit_int32(op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 890 } 891 892 // pp 234, note op in book is wrong, see pp 268 893 894 inline void Assembler::taddcc(Register s1, Register s2, Register d) { 895 emit_int32(op(arith_op) | rd(d) | op3(taddcc_op3) | rs1(s1) | rs2(s2)); 896 } 897 inline void Assembler::taddcc(Register s1, int simm13a, Register d) { 898 emit_int32(op(arith_op) | rd(d) | op3(taddcc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 899 } 900 901 // pp 235 902 903 inline void Assembler::tsubcc(Register s1, Register s2, Register d) { 904 emit_int32(op(arith_op) | rd(d) | op3(tsubcc_op3) | rs1(s1) | rs2(s2)); 905 } 906 inline void Assembler::tsubcc(Register s1, int simm13a, Register d) { 907 emit_int32(op(arith_op) | rd(d) | op3(tsubcc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); 908 } 909 910 // pp 237 911 912 inline void Assembler::trap(Condition c, CC cc, Register s1, Register s2) { 913 emit_int32(op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); 914 } 915 inline void Assembler::trap(Condition c, CC cc, Register s1, int trapa) { 916 emit_int32(op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); 917 } 918 // simple uncond. trap 919 inline void Assembler::trap(int trapa) { 920 trap(always, icc, G0, trapa); 921 } 922 923 inline void Assembler::wry(Register d) { 924 v9_dep(); 925 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); 926 } 927 inline void Assembler::wrccr(Register s) { 928 emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); 929 } 930 inline void Assembler::wrccr(Register s, int simm13a) { 931 emit_int32(op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25) | immed(true) | simm(simm13a, 13)); 932 } 933 inline void Assembler::wrasi(Register d) { 934 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); 935 } 936 // wrasi(d, imm) stores (d xor imm) to asi 937 inline void Assembler::wrasi(Register d, int simm13a) { 938 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); 939 } 940 inline void Assembler::wrfprs(Register d) { 941 emit_int32(op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); 942 } 943 944 inline void Assembler::alignaddr(Register s1, Register s2, Register d) { 945 vis1_only(); 946 emit_int32(op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); 947 } 948 949 inline void Assembler::faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d) { 950 vis1_only(); 951 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); 952 } 953 954 inline void Assembler::fzero(FloatRegisterImpl::Width w, FloatRegister d) { 955 vis1_only(); 956 emit_int32(op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); 957 } 958 959 inline void Assembler::fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d) { 960 vis1_only(); 961 emit_int32(op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); 962 } 963 964 inline void Assembler::fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d) { 965 vis1_only(); 966 emit_int32(op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); 967 } 968 969 inline void Assembler::fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d) { 970 vis1_only(); 971 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); 972 } 973 974 inline void Assembler::stpartialf(Register s1, Register s2, FloatRegister d, int ia) { 975 vis1_only(); 976 emit_int32(op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); 977 } 978 979 // VIS2 instructions 980 981 inline void Assembler::edge8n(Register s1, Register s2, Register d) { 982 vis2_only(); 983 emit_int32(op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); 984 } 985 986 inline void Assembler::bmask(Register s1, Register s2, Register d) { 987 vis2_only(); 988 emit_int32(op(arith_op) | rd(d) | op3(bmask_op3) | rs1(s1) | opf(bmask_opf) | rs2(s2)); 989 } 990 inline void Assembler::bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d) { 991 vis2_only(); 992 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(bshuffle_op3) | fs1(s1, FloatRegisterImpl::D) | opf(bshuffle_opf) | fs2(s2, FloatRegisterImpl::D)); 993 } 994 995 // VIS3 instructions 996 997 inline void Assembler::movstosw(FloatRegister s, Register d) { 998 vis3_only(); 999 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); 1000 } 1001 inline void Assembler::movstouw(FloatRegister s, Register d) { 1002 vis3_only(); 1003 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); 1004 } 1005 inline void Assembler::movdtox(FloatRegister s, Register d) { 1006 vis3_only(); 1007 emit_int32(op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); 1008 } 1009 1010 inline void Assembler::movwtos(Register s, FloatRegister d) { 1011 vis3_only(); 1012 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); 1013 } 1014 inline void Assembler::movxtod(Register s, FloatRegister d) { 1015 vis3_only(); 1016 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); 1017 } 1018 1019 inline void Assembler::xmulx(Register s1, Register s2, Register d) { 1020 vis3_only(); 1021 emit_int32(op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); 1022 } 1023 inline void Assembler::xmulxhi(Register s1, Register s2, Register d) { 1024 vis3_only(); 1025 emit_int32(op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); 1026 } 1027 1028 // Crypto SHA instructions 1029 1030 inline void Assembler::sha1() { 1031 sha1_only(); 1032 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha1_opf)); 1033 } 1034 inline void Assembler::sha256() { 1035 sha256_only(); 1036 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha256_opf)); 1037 } 1038 inline void Assembler::sha512() { 1039 sha512_only(); 1040 emit_int32(op(arith_op) | op3(sha_op3) | opf(sha512_opf)); 1041 } 1042 1043 // CRC32C instruction 1044 1045 inline void Assembler::crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d) { 1046 crc32c_only(); 1047 emit_int32(op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D)); 1048 } 1049 1050 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP --- EOF ---