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src/cpu/sparc/vm/vm_version_sparc.hpp

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*** 65,74 **** --- 65,84 ---- ISA_XMPMUL, ISA_XMONT, ISA_PAUSE_NSEC, ISA_VAMASK, + ISA_SPARC6, + ISA_DICTUNP, + ISA_FPCMPSHL, + ISA_RLE, + ISA_SHA3, + ISA_FJATHPLUS2, + ISA_VIS3C, + ISA_SPARC5B, + ISA_MME, + // Synthesised properties: CPU_FAST_IDIV, CPU_FAST_RDPC, CPU_FAST_BIS,
*** 77,87 **** CPU_FAST_IND_BR, CPU_BLK_ZEROING }; private: ! enum { ISA_last_feature = ISA_VAMASK, CPU_last_feature = CPU_BLK_ZEROING }; enum { ISA_unknown_msk = 0, --- 87,97 ---- CPU_FAST_IND_BR, CPU_BLK_ZEROING }; private: ! enum { ISA_last_feature = ISA_MME, CPU_last_feature = CPU_BLK_ZEROING }; enum { ISA_unknown_msk = 0,
*** 117,126 **** --- 127,146 ---- ISA_xmpmul_msk = UINT64_C(1) << ISA_XMPMUL, ISA_xmont_msk = UINT64_C(1) << ISA_XMONT, ISA_pause_nsec_msk = UINT64_C(1) << ISA_PAUSE_NSEC, ISA_vamask_msk = UINT64_C(1) << ISA_VAMASK, + ISA_sparc6_msk = UINT64_C(1) << ISA_SPARC6, + ISA_dictunp_msk = UINT64_C(1) << ISA_DICTUNP, + ISA_fpcmpshl_msk = UINT64_C(1) << ISA_FPCMPSHL, + ISA_rle_msk = UINT64_C(1) << ISA_RLE, + ISA_sha3_msk = UINT64_C(1) << ISA_SHA3, + ISA_fjathplus2_msk = UINT64_C(1) << ISA_FJATHPLUS2, + ISA_vis3c_msk = UINT64_C(1) << ISA_VIS3C, + ISA_sparc5b_msk = UINT64_C(1) << ISA_SPARC5B, + ISA_mme_msk = UINT64_C(1) << ISA_MME, + CPU_fast_idiv_msk = UINT64_C(1) << CPU_FAST_IDIV, CPU_fast_rdpc_msk = UINT64_C(1) << CPU_FAST_RDPC, CPU_fast_bis_msk = UINT64_C(1) << CPU_FAST_BIS, CPU_fast_ld_msk = UINT64_C(1) << CPU_FAST_LD, CPU_fast_cmove_msk = UINT64_C(1) << CPU_FAST_CMOVE,
*** 163,172 **** --- 183,199 ---- * Oracle SPARC M7: (Core S4) * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND, * AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b, * ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK * + * Oracle SPARC M8: (Core S5) + * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND, + * AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b, + * ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK, SPARC6, FPCMPSHL, + * DICTUNP, RLE, SHA3, MME + * + * NOTE: Oracle Number support ignored. */ enum { niagara1_msk = ISA_v9_msk | ISA_vis1_msk | ISA_blk_init_msk, niagara2_msk = niagara1_msk | ISA_popc_msk,
*** 180,194 **** core_S4_msk = core_S3_msk - ISA_kasumi_msk | ISA_vis3b_msk | ISA_adi_msk | ISA_sparc5_msk | ISA_mwait_msk | ISA_xmpmul_msk | ISA_xmont_msk | ISA_pause_nsec_msk | ISA_vamask_msk, ultra_sparc_t1_msk = niagara1_msk, ultra_sparc_t2_msk = niagara2_msk, ultra_sparc_t3_msk = core_S2_msk, ultra_sparc_m5_msk = core_S3_msk, // NOTE: First out-of-order pipeline. ! ultra_sparc_m7_msk = core_S4_msk }; static uint _L2_data_cache_line_size; static uint L2_data_cache_line_size() { return _L2_data_cache_line_size; } --- 207,225 ---- core_S4_msk = core_S3_msk - ISA_kasumi_msk | ISA_vis3b_msk | ISA_adi_msk | ISA_sparc5_msk | ISA_mwait_msk | ISA_xmpmul_msk | ISA_xmont_msk | ISA_pause_nsec_msk | ISA_vamask_msk, + core_S5_msk = core_S4_msk | ISA_sparc6_msk | ISA_dictunp_msk | + ISA_fpcmpshl_msk | ISA_rle_msk | ISA_sha3_msk | ISA_mme_msk, + ultra_sparc_t1_msk = niagara1_msk, ultra_sparc_t2_msk = niagara2_msk, ultra_sparc_t3_msk = core_S2_msk, ultra_sparc_m5_msk = core_S3_msk, // NOTE: First out-of-order pipeline. ! ultra_sparc_m7_msk = core_S4_msk, ! ultra_sparc_m8_msk = core_S5_msk }; static uint _L2_data_cache_line_size; static uint L2_data_cache_line_size() { return _L2_data_cache_line_size; }
*** 245,254 **** --- 276,295 ---- static bool has_xmpmul() { return (_features & ISA_xmpmul_msk) != 0; } static bool has_xmont() { return (_features & ISA_xmont_msk) != 0; } static bool has_pause_nsec() { return (_features & ISA_pause_nsec_msk) != 0; } static bool has_vamask() { return (_features & ISA_vamask_msk) != 0; } + static bool has_sparc6() { return (_features & ISA_sparc6_msk) != 0; } + static bool has_dictunp() { return (_features & ISA_dictunp_msk) != 0; } + static bool has_fpcmpshl() { return (_features & ISA_fpcmpshl_msk) != 0; } + static bool has_rle() { return (_features & ISA_rle_msk) != 0; } + static bool has_sha3() { return (_features & ISA_sha3_msk) != 0; } + static bool has_athena_plus2() { return (_features & ISA_fjathplus2_msk) != 0; } + static bool has_vis3c() { return (_features & ISA_vis3c_msk) != 0; } + static bool has_sparc5b() { return (_features & ISA_sparc5b_msk) != 0; } + static bool has_mme() { return (_features & ISA_mme_msk) != 0; } + static bool has_fast_idiv() { return (_features & CPU_fast_idiv_msk) != 0; } static bool has_fast_rdpc() { return (_features & CPU_fast_rdpc_msk) != 0; } static bool has_fast_bis() { return (_features & CPU_fast_bis_msk) != 0; } static bool has_fast_ld() { return (_features & CPU_fast_ld_msk) != 0; } static bool has_fast_cmove() { return (_features & CPU_fast_cmove_msk) != 0; }
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