1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
27
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class VM_Version: public Abstract_VM_Version {
32 friend class VMStructs;
33 friend class JVMCIVMStructs;
34
35 protected:
36 enum {
37 ISA_V9,
38 ISA_POPC,
39 ISA_VIS1,
40 ISA_VIS2,
41 ISA_BLK_INIT,
42 ISA_FMAF,
43 ISA_VIS3,
44 ISA_HPC,
45 ISA_IMA,
46 ISA_AES,
47 ISA_DES,
48 ISA_KASUMI,
49 ISA_CAMELLIA,
50 ISA_MD5,
51 ISA_SHA1,
52 ISA_SHA256,
53 ISA_SHA512,
54 ISA_MPMUL,
55 ISA_MONT,
56 ISA_PAUSE,
57 ISA_CBCOND,
58 ISA_CRC32C,
59
60 ISA_FJATHPLUS,
61 ISA_VIS3B,
62 ISA_ADI,
63 ISA_SPARC5,
64 ISA_MWAIT,
65 ISA_XMPMUL,
66 ISA_XMONT,
67 ISA_PAUSE_NSEC,
68 ISA_VAMASK,
69
70 // Synthesised properties:
71
72 CPU_FAST_IDIV,
73 CPU_FAST_RDPC,
74 CPU_FAST_BIS,
75 CPU_FAST_LD,
76 CPU_FAST_CMOVE,
77 CPU_FAST_IND_BR,
78 CPU_BLK_ZEROING
79 };
80
81 private:
82 enum { ISA_last_feature = ISA_VAMASK,
83 CPU_last_feature = CPU_BLK_ZEROING };
84
85 enum {
86 ISA_unknown_msk = 0,
87
88 ISA_v9_msk = UINT64_C(1) << ISA_V9,
89
90 ISA_popc_msk = UINT64_C(1) << ISA_POPC,
91 ISA_vis1_msk = UINT64_C(1) << ISA_VIS1,
92 ISA_vis2_msk = UINT64_C(1) << ISA_VIS2,
93 ISA_blk_init_msk = UINT64_C(1) << ISA_BLK_INIT,
94 ISA_fmaf_msk = UINT64_C(1) << ISA_FMAF,
95 ISA_vis3_msk = UINT64_C(1) << ISA_VIS3,
96 ISA_hpc_msk = UINT64_C(1) << ISA_HPC,
97 ISA_ima_msk = UINT64_C(1) << ISA_IMA,
98 ISA_aes_msk = UINT64_C(1) << ISA_AES,
99 ISA_des_msk = UINT64_C(1) << ISA_DES,
100 ISA_kasumi_msk = UINT64_C(1) << ISA_KASUMI,
101 ISA_camellia_msk = UINT64_C(1) << ISA_CAMELLIA,
102 ISA_md5_msk = UINT64_C(1) << ISA_MD5,
103 ISA_sha1_msk = UINT64_C(1) << ISA_SHA1,
104 ISA_sha256_msk = UINT64_C(1) << ISA_SHA256,
105 ISA_sha512_msk = UINT64_C(1) << ISA_SHA512,
106 ISA_mpmul_msk = UINT64_C(1) << ISA_MPMUL,
107 ISA_mont_msk = UINT64_C(1) << ISA_MONT,
108 ISA_pause_msk = UINT64_C(1) << ISA_PAUSE,
109 ISA_cbcond_msk = UINT64_C(1) << ISA_CBCOND,
110 ISA_crc32c_msk = UINT64_C(1) << ISA_CRC32C,
111
112 ISA_fjathplus_msk = UINT64_C(1) << ISA_FJATHPLUS,
113 ISA_vis3b_msk = UINT64_C(1) << ISA_VIS3B,
114 ISA_adi_msk = UINT64_C(1) << ISA_ADI,
115 ISA_sparc5_msk = UINT64_C(1) << ISA_SPARC5,
116 ISA_mwait_msk = UINT64_C(1) << ISA_MWAIT,
117 ISA_xmpmul_msk = UINT64_C(1) << ISA_XMPMUL,
118 ISA_xmont_msk = UINT64_C(1) << ISA_XMONT,
119 ISA_pause_nsec_msk = UINT64_C(1) << ISA_PAUSE_NSEC,
120 ISA_vamask_msk = UINT64_C(1) << ISA_VAMASK,
121
122 CPU_fast_idiv_msk = UINT64_C(1) << CPU_FAST_IDIV,
123 CPU_fast_rdpc_msk = UINT64_C(1) << CPU_FAST_RDPC,
124 CPU_fast_bis_msk = UINT64_C(1) << CPU_FAST_BIS,
125 CPU_fast_ld_msk = UINT64_C(1) << CPU_FAST_LD,
126 CPU_fast_cmove_msk = UINT64_C(1) << CPU_FAST_CMOVE,
127 CPU_fast_ind_br_msk = UINT64_C(1) << CPU_FAST_IND_BR,
128 CPU_blk_zeroing_msk = UINT64_C(1) << CPU_BLK_ZEROING,
129
130 last_feature_msk = CPU_blk_zeroing_msk,
131 full_feature_msk = (last_feature_msk << 1) - 1
132 };
133
134 /* The following, previously supported, SPARC implementations are no longer
135 * supported.
136 *
137 * UltraSPARC I/II:
138 * SPARC-V9, VIS
139 * UltraSPARC III/+: (Cheetah/+)
140 * SPARC-V9, VIS
141 * UltraSPARC IV: (Jaguar)
142 * SPARC-V9, VIS
143 * UltraSPARC IV+: (Panther)
144 * SPARC-V9, VIS, POPC
145 *
146 * The currently supported SPARC implementations are listed below (including
147 * generic V9 support).
148 *
149 * UltraSPARC T1: (Niagara)
150 * SPARC-V9, VIS, ASI_BIS (Crypto/hash in SPU)
151 * UltraSPARC T2: (Niagara-2)
152 * SPARC-V9, VIS, ASI_BIS, POPC (Crypto/hash in SPU)
153 * UltraSPARC T2+: (Victoria Falls, etc.)
154 * SPARC-V9, VIS, VIS2, ASI_BIS, POPC (Crypto/hash in SPU)
155 *
156 * UltraSPARC T3: (Rainbow Falls/S2)
157 * SPARC-V9, VIS, VIS2, ASI_BIS, POPC (Crypto/hash in SPU)
158 *
159 * Oracle SPARC T4/T5/M5: (Core S3)
160 * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
161 * AES, DES, Kasumi, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL
162 *
163 * Oracle SPARC M7: (Core S4)
164 * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
165 * AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b,
166 * ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK
167 *
168 */
169 enum {
170 niagara1_msk = ISA_v9_msk | ISA_vis1_msk | ISA_blk_init_msk,
171 niagara2_msk = niagara1_msk | ISA_popc_msk,
172
173 core_S2_msk = niagara2_msk | ISA_vis2_msk,
174
175 core_S3_msk = core_S2_msk | ISA_fmaf_msk | ISA_vis3_msk | ISA_hpc_msk |
176 ISA_ima_msk | ISA_aes_msk | ISA_des_msk | ISA_kasumi_msk |
177 ISA_camellia_msk | ISA_md5_msk | ISA_sha1_msk | ISA_sha256_msk |
178 ISA_sha512_msk | ISA_mpmul_msk | ISA_mont_msk | ISA_pause_msk |
179 ISA_cbcond_msk | ISA_crc32c_msk,
180
181 core_S4_msk = core_S3_msk - ISA_kasumi_msk |
182 ISA_vis3b_msk | ISA_adi_msk | ISA_sparc5_msk | ISA_mwait_msk |
183 ISA_xmpmul_msk | ISA_xmont_msk | ISA_pause_nsec_msk | ISA_vamask_msk,
184
185 ultra_sparc_t1_msk = niagara1_msk,
186 ultra_sparc_t2_msk = niagara2_msk,
187 ultra_sparc_t3_msk = core_S2_msk,
188 ultra_sparc_m5_msk = core_S3_msk, // NOTE: First out-of-order pipeline.
189 ultra_sparc_m7_msk = core_S4_msk
190 };
191
192 static uint _L2_data_cache_line_size;
193 static uint L2_data_cache_line_size() { return _L2_data_cache_line_size; }
194
195 static void determine_features();
196 static void platform_features();
197 static void print_features();
198
199 public:
200 enum {
201 // Adopt a conservative behaviour (modelling single-insn-fetch-n-issue) for
202 // Niagara (and SPARC64). While there are at least two entries/slots in the
203 // instruction fetch buffer on any Niagara core (and as many as eight on a
204 // SPARC64), the performance improvement from keeping hot branch targets on
205 // optimally aligned addresses is such a small one (if any) that we choose
206 // not to use the extra code space required.
207
208 insn_fetch_alignment = 4 // Byte alignment in L1 insn. cache.
209 };
210
211 static void initialize();
212
213 static void init_before_ergo() { determine_features(); }
214
215 // Instruction feature support:
216
217 static bool has_v9() { return (_features & ISA_v9_msk) != 0; }
218 static bool has_popc() { return (_features & ISA_popc_msk) != 0; }
219 static bool has_vis1() { return (_features & ISA_vis1_msk) != 0; }
220 static bool has_vis2() { return (_features & ISA_vis2_msk) != 0; }
221 static bool has_blk_init() { return (_features & ISA_blk_init_msk) != 0; }
222 static bool has_fmaf() { return (_features & ISA_fmaf_msk) != 0; }
223 static bool has_vis3() { return (_features & ISA_vis3_msk) != 0; }
224 static bool has_hpc() { return (_features & ISA_hpc_msk) != 0; }
225 static bool has_ima() { return (_features & ISA_ima_msk) != 0; }
226 static bool has_aes() { return (_features & ISA_aes_msk) != 0; }
227 static bool has_des() { return (_features & ISA_des_msk) != 0; }
228 static bool has_kasumi() { return (_features & ISA_kasumi_msk) != 0; }
229 static bool has_camellia() { return (_features & ISA_camellia_msk) != 0; }
230 static bool has_md5() { return (_features & ISA_md5_msk) != 0; }
231 static bool has_sha1() { return (_features & ISA_sha1_msk) != 0; }
232 static bool has_sha256() { return (_features & ISA_sha256_msk) != 0; }
233 static bool has_sha512() { return (_features & ISA_sha512_msk) != 0; }
234 static bool has_mpmul() { return (_features & ISA_mpmul_msk) != 0; }
235 static bool has_mont() { return (_features & ISA_mont_msk) != 0; }
236 static bool has_pause() { return (_features & ISA_pause_msk) != 0; }
237 static bool has_cbcond() { return (_features & ISA_cbcond_msk) != 0; }
238 static bool has_crc32c() { return (_features & ISA_crc32c_msk) != 0; }
239
240 static bool has_athena_plus() { return (_features & ISA_fjathplus_msk) != 0; }
241 static bool has_vis3b() { return (_features & ISA_vis3b_msk) != 0; }
242 static bool has_adi() { return (_features & ISA_adi_msk) != 0; }
243 static bool has_sparc5() { return (_features & ISA_sparc5_msk) != 0; }
244 static bool has_mwait() { return (_features & ISA_mwait_msk) != 0; }
245 static bool has_xmpmul() { return (_features & ISA_xmpmul_msk) != 0; }
246 static bool has_xmont() { return (_features & ISA_xmont_msk) != 0; }
247 static bool has_pause_nsec() { return (_features & ISA_pause_nsec_msk) != 0; }
248 static bool has_vamask() { return (_features & ISA_vamask_msk) != 0; }
249
250 static bool has_fast_idiv() { return (_features & CPU_fast_idiv_msk) != 0; }
251 static bool has_fast_rdpc() { return (_features & CPU_fast_rdpc_msk) != 0; }
252 static bool has_fast_bis() { return (_features & CPU_fast_bis_msk) != 0; }
253 static bool has_fast_ld() { return (_features & CPU_fast_ld_msk) != 0; }
254 static bool has_fast_cmove() { return (_features & CPU_fast_cmove_msk) != 0; }
255
256 // If indirect and direct branching is equally fast.
257 static bool has_fast_ind_br() { return (_features & CPU_fast_ind_br_msk) != 0; }
258 // If SPARC BIS to the beginning of cache line always zeros it.
259 static bool has_blk_zeroing() { return (_features & CPU_blk_zeroing_msk) != 0; }
260
261 static bool supports_compare_and_exchange() { return true; }
262
263 // FIXME: To be removed.
264 static bool is_post_niagara() {
265 return (_features & niagara2_msk) == niagara2_msk;
266 }
267
268 // Default prefetch block size on SPARC.
269 static uint prefetch_data_size() { return L2_data_cache_line_size(); }
270
271 private:
272 // Prefetch policy and characteristics:
273 //
274 // These support routines are used in order to isolate any CPU/core specific
275 // logic from the actual flag/option processing. They should reflect the HW
276 // characteristics for the associated options on the current platform.
277 //
278 // The three Prefetch* options below (assigned -1 in the configuration) are
279 // treated according to (given the accepted range [-1..<maxint>]):
280 // -1: Determine a proper HW-specific value for the current HW.
281 // 0: Off
282 // >0: Command-line supplied value to use.
283 //
284 // FIXME: The documentation string in the configuration is wrong, saying that
285 // -1 is also interpreted as off.
286 //
287 static intx prefetch_copy_interval_in_bytes() {
288 intx bytes = PrefetchCopyIntervalInBytes;
289 return bytes < 0 ? 512 : bytes;
290 }
291 static intx prefetch_scan_interval_in_bytes() {
292 intx bytes = PrefetchScanIntervalInBytes;
293 return bytes < 0 ? 512 : bytes;
294 }
295 static intx prefetch_fields_ahead() {
296 intx count = PrefetchFieldsAhead;
297 return count < 0 ? 1 : count;
298 }
299
300 // AllocatePrefetchDistance is treated under the same interpretation as the
301 // Prefetch* options above (i.e., -1, 0, >0).
302 static intx allocate_prefetch_distance() {
303 intx count = AllocatePrefetchDistance;
304 return count < 0 ? 512 : count;
305 }
306
307 // AllocatePrefetchStyle is guaranteed to be in range [0..3] defined by the
308 // configuration.
309 static intx allocate_prefetch_style() {
310 intx distance = allocate_prefetch_distance();
311 // Return 0 (off/none) if AllocatePrefetchDistance was not defined.
312 return distance > 0 ? AllocatePrefetchStyle : 0;
313 }
314
315 public:
316 // Assembler testing
317 static void allow_all();
318 static void revert();
319
320 // Override the Abstract_VM_Version implementation.
321 //
322 // FIXME: Removed broken test on sun4v (always false when invoked prior to the
323 // proper capability setup), thus always returning 2. Still need to fix
324 // this properly in order to enable complete page size support.
325 static uint page_size_count() { return 2; }
326
327 // Calculates the number of parallel threads
328 static unsigned int calc_parallel_worker_threads();
329 };
330
331 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP