363 if (av & AV_SPARC_ASI_BLK_INIT) features |= ISA_blk_init_msk; 364 if (av & AV_SPARC_FMAF) features |= ISA_fmaf_msk; 365 if (av & AV_SPARC_VIS3) features |= ISA_vis3_msk; 366 if (av & AV_SPARC_HPC) features |= ISA_hpc_msk; 367 if (av & AV_SPARC_IMA) features |= ISA_ima_msk; 368 if (av & AV_SPARC_AES) features |= ISA_aes_msk; 369 if (av & AV_SPARC_DES) features |= ISA_des_msk; 370 if (av & AV_SPARC_KASUMI) features |= ISA_kasumi_msk; 371 if (av & AV_SPARC_CAMELLIA) features |= ISA_camellia_msk; 372 if (av & AV_SPARC_MD5) features |= ISA_md5_msk; 373 if (av & AV_SPARC_SHA1) features |= ISA_sha1_msk; 374 if (av & AV_SPARC_SHA256) features |= ISA_sha256_msk; 375 if (av & AV_SPARC_SHA512) features |= ISA_sha512_msk; 376 if (av & AV_SPARC_MPMUL) features |= ISA_mpmul_msk; 377 if (av & AV_SPARC_MONT) features |= ISA_mont_msk; 378 if (av & AV_SPARC_PAUSE) features |= ISA_pause_msk; 379 if (av & AV_SPARC_CBCOND) features |= ISA_cbcond_msk; 380 if (av & AV_SPARC_CRC32C) features |= ISA_crc32c_msk; 381 382 #ifndef AV2_SPARC_FJATHPLUS 383 #define AV2_SPARC_FJATHPLUS 0x00000001 // Fujitsu Athena+ 384 #endif 385 #ifndef AV2_SPARC_VIS3B 386 #define AV2_SPARC_VIS3B 0x00000002 // VIS3 present on multiple chips 387 #endif 388 #ifndef AV2_SPARC_ADI 389 #define AV2_SPARC_ADI 0x00000004 // Application Data Integrity 390 #endif 391 #ifndef AV2_SPARC_SPARC5 392 #define AV2_SPARC_SPARC5 0x00000008 // The 29 new fp and sub instructions 393 #endif 394 #ifndef AV2_SPARC_MWAIT 395 #define AV2_SPARC_MWAIT 0x00000010 // mwait instruction and load/monitor ASIs 396 #endif 397 #ifndef AV2_SPARC_XMPMUL 398 #define AV2_SPARC_XMPMUL 0x00000020 // XOR multiple precision multiply 399 #endif 400 #ifndef AV2_SPARC_XMONT 401 #define AV2_SPARC_XMONT 0x00000040 // XOR Montgomery mult/sqr instructions 402 #endif 403 #ifndef AV2_SPARC_PAUSE_NSEC 404 #define AV2_SPARC_PAUSE_NSEC 0x00000080 // pause instruction with support for nsec timings 405 #endif 406 #ifndef AV2_SPARC_VAMASK 407 #define AV2_SPARC_VAMASK 0x00000100 // Virtual Address masking 408 #endif 409 410 if (avn > 1) { 411 uint32_t av2 = avs[AV_HW2_IDX]; 412 413 if (av2 & AV2_SPARC_FJATHPLUS) features |= ISA_fjathplus_msk; 414 if (av2 & AV2_SPARC_VIS3B) features |= ISA_vis3b_msk; 415 if (av2 & AV2_SPARC_ADI) features |= ISA_adi_msk; 416 if (av2 & AV2_SPARC_SPARC5) features |= ISA_sparc5_msk; 417 if (av2 & AV2_SPARC_MWAIT) features |= ISA_mwait_msk; 418 if (av2 & AV2_SPARC_XMPMUL) features |= ISA_xmpmul_msk; 419 if (av2 & AV2_SPARC_XMONT) features |= ISA_xmont_msk; 420 if (av2 & AV2_SPARC_PAUSE_NSEC) features |= ISA_pause_nsec_msk; 421 if (av2 & AV2_SPARC_VAMASK) features |= ISA_vamask_msk; 422 } 423 424 _features = features; // ISA feature set completed, update state. 425 426 Sysinfo machine(SI_MACHINE); 427 428 bool is_sun4v = machine.match("sun4v"); // All Oracle SPARC + Fujitsu Athena+ 429 bool is_sun4u = machine.match("sun4u"); // All other Fujitsu 430 431 // Handle Athena+ conservatively (simply because we are lacking info.). 432 433 bool do_sun4v = is_sun4v && !has_athena_plus(); 434 bool do_sun4u = is_sun4u || has_athena_plus(); 435 436 uint64_t synthetic = 0; 437 438 if (do_sun4v) { 439 // Indirect and direct branches are equally fast. 440 synthetic = CPU_fast_ind_br_msk; 441 // Fast IDIV, BIS and LD available on Niagara Plus. 442 if (has_vis2()) { 443 synthetic |= (CPU_fast_idiv_msk | CPU_fast_ld_msk); 444 // ...on Core S4 however, we prefer not to use BIS. 445 if (!has_sparc5()) { 446 synthetic |= CPU_fast_bis_msk; 447 } 448 } 449 // Niagara Core S3 supports fast RDPC and block zeroing. 450 if (has_ima()) { 451 synthetic |= (CPU_fast_rdpc_msk | CPU_blk_zeroing_msk); 452 } 453 // Niagara Core S3 and S4 have slow CMOVE. 454 if (!has_ima()) { | 363 if (av & AV_SPARC_ASI_BLK_INIT) features |= ISA_blk_init_msk; 364 if (av & AV_SPARC_FMAF) features |= ISA_fmaf_msk; 365 if (av & AV_SPARC_VIS3) features |= ISA_vis3_msk; 366 if (av & AV_SPARC_HPC) features |= ISA_hpc_msk; 367 if (av & AV_SPARC_IMA) features |= ISA_ima_msk; 368 if (av & AV_SPARC_AES) features |= ISA_aes_msk; 369 if (av & AV_SPARC_DES) features |= ISA_des_msk; 370 if (av & AV_SPARC_KASUMI) features |= ISA_kasumi_msk; 371 if (av & AV_SPARC_CAMELLIA) features |= ISA_camellia_msk; 372 if (av & AV_SPARC_MD5) features |= ISA_md5_msk; 373 if (av & AV_SPARC_SHA1) features |= ISA_sha1_msk; 374 if (av & AV_SPARC_SHA256) features |= ISA_sha256_msk; 375 if (av & AV_SPARC_SHA512) features |= ISA_sha512_msk; 376 if (av & AV_SPARC_MPMUL) features |= ISA_mpmul_msk; 377 if (av & AV_SPARC_MONT) features |= ISA_mont_msk; 378 if (av & AV_SPARC_PAUSE) features |= ISA_pause_msk; 379 if (av & AV_SPARC_CBCOND) features |= ISA_cbcond_msk; 380 if (av & AV_SPARC_CRC32C) features |= ISA_crc32c_msk; 381 382 #ifndef AV2_SPARC_FJATHPLUS 383 #define AV2_SPARC_FJATHPLUS 0x00000001 // Fujitsu Athena+ insns 384 #endif 385 #ifndef AV2_SPARC_VIS3B 386 #define AV2_SPARC_VIS3B 0x00000002 // VIS3 present on multiple chips 387 #endif 388 #ifndef AV2_SPARC_ADI 389 #define AV2_SPARC_ADI 0x00000004 // Application Data Integrity 390 #endif 391 #ifndef AV2_SPARC_SPARC5 392 #define AV2_SPARC_SPARC5 0x00000008 // The 29 new fp and sub instructions 393 #endif 394 #ifndef AV2_SPARC_MWAIT 395 #define AV2_SPARC_MWAIT 0x00000010 // mwait instruction and load/monitor ASIs 396 #endif 397 #ifndef AV2_SPARC_XMPMUL 398 #define AV2_SPARC_XMPMUL 0x00000020 // XOR multiple precision multiply 399 #endif 400 #ifndef AV2_SPARC_XMONT 401 #define AV2_SPARC_XMONT 0x00000040 // XOR Montgomery mult/sqr instructions 402 #endif 403 #ifndef AV2_SPARC_PAUSE_NSEC 404 #define AV2_SPARC_PAUSE_NSEC 0x00000080 // pause instruction with support for nsec timings 405 #endif 406 #ifndef AV2_SPARC_VAMASK 407 #define AV2_SPARC_VAMASK 0x00000100 // Virtual Address masking 408 #endif 409 410 #ifndef AV2_SPARC_SPARC6 411 #define AV2_SPARC_SPARC6 0x00000200 // REVB*, FPSLL*, RDENTROPY, LDM* and STM* 412 #endif 413 #ifndef AV2_SPARC_DICTUNP 414 #define AV2_SPARC_DICTUNP 0x00002000 // Dictionary unpack instruction 415 #endif 416 #ifndef AV2_SPARC_FPCMPSHL 417 #define AV2_SPARC_FPCMPSHL 0x00004000 // Partition compare with shifted result 418 #endif 419 #ifndef AV2_SPARC_RLE 420 #define AV2_SPARC_RLE 0x00008000 // Run-length encoded burst and length 421 #endif 422 #ifndef AV2_SPARC_SHA3 423 #define AV2_SPARC_SHA3 0x00010000 // SHA3 instructions 424 #endif 425 #ifndef AV2_SPARC_FJATHPLUS2 426 #define AV2_SPARC_FJATHPLUS2 0x00020000 // Fujitsu Athena++ insns 427 #endif 428 #ifndef AV2_SPARC_VIS3C 429 #define AV2_SPARC_VIS3C 0x00040000 // Subset of VIS3 insns provided by Athena++ 430 #endif 431 #ifndef AV2_SPARC_SPARC5B 432 #define AV2_SPARC_SPARC5B 0x00080000 // subset of SPARC5 insns (fpadd8, fpsub8) 433 #endif 434 #ifndef AV2_SPARC_MME 435 #define AV2_SPARC_MME 0x00100000 // Misaligned Mitigation Enable 436 #endif 437 438 if (avn > 1) { 439 uint32_t av2 = avs[AV_HW2_IDX]; 440 441 if (av2 & AV2_SPARC_FJATHPLUS) features |= ISA_fjathplus_msk; 442 if (av2 & AV2_SPARC_VIS3B) features |= ISA_vis3b_msk; 443 if (av2 & AV2_SPARC_ADI) features |= ISA_adi_msk; 444 if (av2 & AV2_SPARC_SPARC5) features |= ISA_sparc5_msk; 445 if (av2 & AV2_SPARC_MWAIT) features |= ISA_mwait_msk; 446 if (av2 & AV2_SPARC_XMPMUL) features |= ISA_xmpmul_msk; 447 if (av2 & AV2_SPARC_XMONT) features |= ISA_xmont_msk; 448 if (av2 & AV2_SPARC_PAUSE_NSEC) features |= ISA_pause_nsec_msk; 449 if (av2 & AV2_SPARC_VAMASK) features |= ISA_vamask_msk; 450 451 if (av2 & AV2_SPARC_SPARC6) features |= ISA_sparc6_msk; 452 if (av2 & AV2_SPARC_DICTUNP) features |= ISA_dictunp_msk; 453 if (av2 & AV2_SPARC_FPCMPSHL) features |= ISA_fpcmpshl_msk; 454 if (av2 & AV2_SPARC_RLE) features |= ISA_rle_msk; 455 if (av2 & AV2_SPARC_SHA3) features |= ISA_sha3_msk; 456 if (av2 & AV2_SPARC_FJATHPLUS2) features |= ISA_fjathplus2_msk; 457 if (av2 & AV2_SPARC_VIS3C) features |= ISA_vis3c_msk; 458 if (av2 & AV2_SPARC_SPARC5B) features |= ISA_sparc5b_msk; 459 if (av2 & AV2_SPARC_MME) features |= ISA_mme_msk; 460 } 461 462 _features = features; // ISA feature set completed, update state. 463 464 Sysinfo machine(SI_MACHINE); 465 466 bool is_sun4v = machine.match("sun4v"); // All Oracle SPARC + Fujitsu Athena+/++ 467 bool is_sun4u = machine.match("sun4u"); // All other Fujitsu 468 469 // Handle Athena+/++ conservatively (simply because we are lacking info.). 470 471 bool an_athena = has_athena_plus() || has_athena_plus2(); 472 bool do_sun4v = is_sun4v && !an_athena; 473 bool do_sun4u = is_sun4u || an_athena; 474 475 uint64_t synthetic = 0; 476 477 if (do_sun4v) { 478 // Indirect and direct branches are equally fast. 479 synthetic = CPU_fast_ind_br_msk; 480 // Fast IDIV, BIS and LD available on Niagara Plus. 481 if (has_vis2()) { 482 synthetic |= (CPU_fast_idiv_msk | CPU_fast_ld_msk); 483 // ...on Core S4 however, we prefer not to use BIS. 484 if (!has_sparc5()) { 485 synthetic |= CPU_fast_bis_msk; 486 } 487 } 488 // Niagara Core S3 supports fast RDPC and block zeroing. 489 if (has_ima()) { 490 synthetic |= (CPU_fast_rdpc_msk | CPU_blk_zeroing_msk); 491 } 492 // Niagara Core S3 and S4 have slow CMOVE. 493 if (!has_ima()) { |