1 /*
2 * Copyright 1999-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_FrameMap_sparc.cpp.incl"
27
28
29 const int FrameMap::pd_c_runtime_reserved_arg_size = 7;
30
31
32 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
33 LIR_Opr opr = LIR_OprFact::illegalOpr;
34 VMReg r_1 = reg->first();
35 VMReg r_2 = reg->second();
36 if (r_1->is_stack()) {
37 // Convert stack slot to an SP offset
38 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
39 // so we must add it in here.
40 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
41 opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
42 } else if (r_1->is_Register()) {
43 Register reg = r_1->as_Register();
44 if (outgoing) {
45 assert(!reg->is_in(), "should be using I regs");
46 } else {
47 assert(!reg->is_out(), "should be using O regs");
48 }
49 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
50 opr = as_long_opr(reg);
51 } else if (type == T_OBJECT || type == T_ARRAY) {
52 opr = as_oop_opr(reg);
53 } else {
54 opr = as_opr(reg);
55 }
56 } else if (r_1->is_FloatRegister()) {
57 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
58 FloatRegister f = r_1->as_FloatRegister();
59 if (type == T_DOUBLE) {
60 opr = as_double_opr(f);
61 } else {
62 opr = as_float_opr(f);
63 }
64 }
65 return opr;
66 }
67
68 // FrameMap
69 //--------------------------------------------------------
70
71 FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
72
73 // some useful constant RInfo's:
74 LIR_Opr FrameMap::in_long_opr;
75 LIR_Opr FrameMap::out_long_opr;
76
77 LIR_Opr FrameMap::F0_opr;
78 LIR_Opr FrameMap::F0_double_opr;
79
80 LIR_Opr FrameMap::G0_opr;
81 LIR_Opr FrameMap::G1_opr;
82 LIR_Opr FrameMap::G2_opr;
83 LIR_Opr FrameMap::G3_opr;
84 LIR_Opr FrameMap::G4_opr;
85 LIR_Opr FrameMap::G5_opr;
86 LIR_Opr FrameMap::G6_opr;
87 LIR_Opr FrameMap::G7_opr;
88 LIR_Opr FrameMap::O0_opr;
89 LIR_Opr FrameMap::O1_opr;
90 LIR_Opr FrameMap::O2_opr;
91 LIR_Opr FrameMap::O3_opr;
92 LIR_Opr FrameMap::O4_opr;
93 LIR_Opr FrameMap::O5_opr;
94 LIR_Opr FrameMap::O6_opr;
95 LIR_Opr FrameMap::O7_opr;
96 LIR_Opr FrameMap::L0_opr;
97 LIR_Opr FrameMap::L1_opr;
98 LIR_Opr FrameMap::L2_opr;
99 LIR_Opr FrameMap::L3_opr;
100 LIR_Opr FrameMap::L4_opr;
101 LIR_Opr FrameMap::L5_opr;
102 LIR_Opr FrameMap::L6_opr;
103 LIR_Opr FrameMap::L7_opr;
104 LIR_Opr FrameMap::I0_opr;
105 LIR_Opr FrameMap::I1_opr;
106 LIR_Opr FrameMap::I2_opr;
107 LIR_Opr FrameMap::I3_opr;
108 LIR_Opr FrameMap::I4_opr;
109 LIR_Opr FrameMap::I5_opr;
110 LIR_Opr FrameMap::I6_opr;
111 LIR_Opr FrameMap::I7_opr;
112
113 LIR_Opr FrameMap::G0_oop_opr;
114 LIR_Opr FrameMap::G1_oop_opr;
115 LIR_Opr FrameMap::G2_oop_opr;
116 LIR_Opr FrameMap::G3_oop_opr;
117 LIR_Opr FrameMap::G4_oop_opr;
118 LIR_Opr FrameMap::G5_oop_opr;
119 LIR_Opr FrameMap::G6_oop_opr;
120 LIR_Opr FrameMap::G7_oop_opr;
121 LIR_Opr FrameMap::O0_oop_opr;
122 LIR_Opr FrameMap::O1_oop_opr;
123 LIR_Opr FrameMap::O2_oop_opr;
124 LIR_Opr FrameMap::O3_oop_opr;
125 LIR_Opr FrameMap::O4_oop_opr;
126 LIR_Opr FrameMap::O5_oop_opr;
127 LIR_Opr FrameMap::O6_oop_opr;
128 LIR_Opr FrameMap::O7_oop_opr;
129 LIR_Opr FrameMap::L0_oop_opr;
130 LIR_Opr FrameMap::L1_oop_opr;
131 LIR_Opr FrameMap::L2_oop_opr;
132 LIR_Opr FrameMap::L3_oop_opr;
133 LIR_Opr FrameMap::L4_oop_opr;
134 LIR_Opr FrameMap::L5_oop_opr;
135 LIR_Opr FrameMap::L6_oop_opr;
136 LIR_Opr FrameMap::L7_oop_opr;
137 LIR_Opr FrameMap::I0_oop_opr;
138 LIR_Opr FrameMap::I1_oop_opr;
139 LIR_Opr FrameMap::I2_oop_opr;
140 LIR_Opr FrameMap::I3_oop_opr;
141 LIR_Opr FrameMap::I4_oop_opr;
142 LIR_Opr FrameMap::I5_oop_opr;
143 LIR_Opr FrameMap::I6_oop_opr;
144 LIR_Opr FrameMap::I7_oop_opr;
145
146 LIR_Opr FrameMap::SP_opr;
147 LIR_Opr FrameMap::FP_opr;
148
149 LIR_Opr FrameMap::Oexception_opr;
150 LIR_Opr FrameMap::Oissuing_pc_opr;
151
152 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
153 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
154
155
156 FloatRegister FrameMap::nr2floatreg (int rnr) {
157 assert(_init_done, "tables not initialized");
158 debug_only(fpu_range_check(rnr);)
159 return _fpu_regs[rnr];
160 }
161
162
163 // returns true if reg could be smashed by a callee.
164 bool FrameMap::is_caller_save_register (LIR_Opr reg) {
165 if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; }
166 if (reg->is_double_cpu()) {
167 return is_caller_save_register(reg->as_register_lo()) ||
168 is_caller_save_register(reg->as_register_hi());
169 }
170 return is_caller_save_register(reg->as_register());
171 }
172
173
174 NEEDS_CLEANUP // once the new calling convention is enabled, we no
175 // longer need to treat I5, I4 and L0 specially
176 // Because the interpreter destroys caller's I5, I4 and L0,
177 // we must spill them before doing a Java call as we may land in
178 // interpreter.
179 bool FrameMap::is_caller_save_register (Register r) {
180 return (r->is_global() && (r != G0)) || r->is_out();
181 }
182
183
184 void FrameMap::init () {
185 if (_init_done) return;
186
187 int i=0;
188 // Register usage:
189 // O6: sp
190 // I6: fp
191 // I7: return address
192 // G0: zero
193 // G2: thread
194 // G7: not available
195 // G6: not available
196 /* 0 */ map_register(i++, L0);
197 /* 1 */ map_register(i++, L1);
198 /* 2 */ map_register(i++, L2);
199 /* 3 */ map_register(i++, L3);
200 /* 4 */ map_register(i++, L4);
201 /* 5 */ map_register(i++, L5);
202 /* 6 */ map_register(i++, L6);
203 /* 7 */ map_register(i++, L7);
204
205 /* 8 */ map_register(i++, I0);
206 /* 9 */ map_register(i++, I1);
207 /* 10 */ map_register(i++, I2);
208 /* 11 */ map_register(i++, I3);
209 /* 12 */ map_register(i++, I4);
210 /* 13 */ map_register(i++, I5);
211 /* 14 */ map_register(i++, O0);
212 /* 15 */ map_register(i++, O1);
213 /* 16 */ map_register(i++, O2);
214 /* 17 */ map_register(i++, O3);
215 /* 18 */ map_register(i++, O4);
216 /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs)
217 /* 20 */ map_register(i++, G1);
218 /* 21 */ map_register(i++, G3);
219 /* 22 */ map_register(i++, G4);
220 /* 23 */ map_register(i++, G5);
221 /* 24 */ map_register(i++, G0);
222
223 // the following registers are not normally available
224 /* 25 */ map_register(i++, O7);
225 /* 26 */ map_register(i++, G2);
226 /* 27 */ map_register(i++, O6);
227 /* 28 */ map_register(i++, I6);
228 /* 29 */ map_register(i++, I7);
229 /* 30 */ map_register(i++, G6);
230 /* 31 */ map_register(i++, G7);
231 assert(i == nof_cpu_regs, "number of CPU registers");
232
233 for (i = 0; i < nof_fpu_regs; i++) {
234 _fpu_regs[i] = as_FloatRegister(i);
235 }
236
237 _init_done = true;
238
239 in_long_opr = as_long_opr(I0);
240 out_long_opr = as_long_opr(O0);
241
242 G0_opr = as_opr(G0);
243 G1_opr = as_opr(G1);
244 G2_opr = as_opr(G2);
245 G3_opr = as_opr(G3);
246 G4_opr = as_opr(G4);
247 G5_opr = as_opr(G5);
248 G6_opr = as_opr(G6);
249 G7_opr = as_opr(G7);
250 O0_opr = as_opr(O0);
251 O1_opr = as_opr(O1);
252 O2_opr = as_opr(O2);
253 O3_opr = as_opr(O3);
254 O4_opr = as_opr(O4);
255 O5_opr = as_opr(O5);
256 O6_opr = as_opr(O6);
257 O7_opr = as_opr(O7);
258 L0_opr = as_opr(L0);
259 L1_opr = as_opr(L1);
260 L2_opr = as_opr(L2);
261 L3_opr = as_opr(L3);
262 L4_opr = as_opr(L4);
263 L5_opr = as_opr(L5);
264 L6_opr = as_opr(L6);
265 L7_opr = as_opr(L7);
266 I0_opr = as_opr(I0);
267 I1_opr = as_opr(I1);
268 I2_opr = as_opr(I2);
269 I3_opr = as_opr(I3);
270 I4_opr = as_opr(I4);
271 I5_opr = as_opr(I5);
272 I6_opr = as_opr(I6);
273 I7_opr = as_opr(I7);
274
275 G0_oop_opr = as_oop_opr(G0);
276 G1_oop_opr = as_oop_opr(G1);
277 G2_oop_opr = as_oop_opr(G2);
278 G3_oop_opr = as_oop_opr(G3);
279 G4_oop_opr = as_oop_opr(G4);
280 G5_oop_opr = as_oop_opr(G5);
281 G6_oop_opr = as_oop_opr(G6);
282 G7_oop_opr = as_oop_opr(G7);
283 O0_oop_opr = as_oop_opr(O0);
284 O1_oop_opr = as_oop_opr(O1);
285 O2_oop_opr = as_oop_opr(O2);
286 O3_oop_opr = as_oop_opr(O3);
287 O4_oop_opr = as_oop_opr(O4);
288 O5_oop_opr = as_oop_opr(O5);
289 O6_oop_opr = as_oop_opr(O6);
290 O7_oop_opr = as_oop_opr(O7);
291 L0_oop_opr = as_oop_opr(L0);
292 L1_oop_opr = as_oop_opr(L1);
293 L2_oop_opr = as_oop_opr(L2);
294 L3_oop_opr = as_oop_opr(L3);
295 L4_oop_opr = as_oop_opr(L4);
296 L5_oop_opr = as_oop_opr(L5);
297 L6_oop_opr = as_oop_opr(L6);
298 L7_oop_opr = as_oop_opr(L7);
299 I0_oop_opr = as_oop_opr(I0);
300 I1_oop_opr = as_oop_opr(I1);
301 I2_oop_opr = as_oop_opr(I2);
302 I3_oop_opr = as_oop_opr(I3);
303 I4_oop_opr = as_oop_opr(I4);
304 I5_oop_opr = as_oop_opr(I5);
305 I6_oop_opr = as_oop_opr(I6);
306 I7_oop_opr = as_oop_opr(I7);
307
308 FP_opr = as_pointer_opr(FP);
309 SP_opr = as_pointer_opr(SP);
310
311 F0_opr = as_float_opr(F0);
312 F0_double_opr = as_double_opr(F0);
313
314 Oexception_opr = as_oop_opr(Oexception);
315 Oissuing_pc_opr = as_opr(Oissuing_pc);
316
317 _caller_save_cpu_regs[0] = FrameMap::O0_opr;
318 _caller_save_cpu_regs[1] = FrameMap::O1_opr;
319 _caller_save_cpu_regs[2] = FrameMap::O2_opr;
320 _caller_save_cpu_regs[3] = FrameMap::O3_opr;
321 _caller_save_cpu_regs[4] = FrameMap::O4_opr;
322 _caller_save_cpu_regs[5] = FrameMap::O5_opr;
323 _caller_save_cpu_regs[6] = FrameMap::G1_opr;
324 _caller_save_cpu_regs[7] = FrameMap::G3_opr;
325 _caller_save_cpu_regs[8] = FrameMap::G4_opr;
326 _caller_save_cpu_regs[9] = FrameMap::G5_opr;
327 for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
328 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
329 }
330 }
331
332
333 Address FrameMap::make_new_address(ByteSize sp_offset) const {
334 return Address(SP, STACK_BIAS + in_bytes(sp_offset));
335 }
336
337
338 VMReg FrameMap::fpu_regname (int n) {
339 return as_FloatRegister(n)->as_VMReg();
340 }
341
342
343 LIR_Opr FrameMap::stack_pointer() {
344 return SP_opr;
345 }
346
347
348 bool FrameMap::validate_frame() {
349 int max_offset = in_bytes(framesize_in_bytes());
350 int java_index = 0;
351 for (int i = 0; i < _incoming_arguments->length(); i++) {
352 LIR_Opr opr = _incoming_arguments->at(i);
353 if (opr->is_stack()) {
354 max_offset = MAX2(_argument_locations->at(java_index), max_offset);
355 }
356 java_index += type2size[opr->type()];
357 }
358 return Assembler::is_simm13(max_offset + STACK_BIAS);
359 }