2939   build_intervals();
2940   CHECK_BAILOUT();
2941   sort_intervals_before_allocation();
2942 
2943   NOT_PRODUCT(print_intervals("Before Register Allocation"));
2944   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
2945 
2946   allocate_registers();
2947   CHECK_BAILOUT();
2948 
2949   resolve_data_flow();
2950   if (compilation()->has_exception_handlers()) {
2951     resolve_exception_handlers();
2952   }
2953   // fill in number of spill slots into frame_map
2954   propagate_spill_slots();
2955   CHECK_BAILOUT();
2956 
2957   NOT_PRODUCT(print_intervals("After Register Allocation"));
2958   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
2959   DEBUG_ONLY(verify());
2960 
2961   sort_intervals_after_allocation();



2962   eliminate_spill_moves();
2963   assign_reg_num();
2964   CHECK_BAILOUT();
2965 
2966   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
2967   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
2968 
2969   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
2970 
2971     if (use_fpu_stack_allocation()) {
2972       allocate_fpu_stack(); // Only has effect on Intel
2973       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
2974     }
2975   }
2976 
2977   { TIME_LINEAR_SCAN(timer_optimize_lir);
2978 
2979     EdgeMoveOptimizer::optimize(ir()->code());
2980     ControlFlowOptimizer::optimize(ir()->code());
2981     // check that cfg is still correct after optimizations

3130       if (i2->from() == 1 && i2->to() == 2) continue;
3131 
3132       int r1 = i1->assigned_reg();
3133       int r1Hi = i1->assigned_regHi();
3134       int r2 = i2->assigned_reg();
3135       int r2Hi = i2->assigned_regHi();
3136       if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
3137         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3138         i1->print(); tty->cr();
3139         i2->print(); tty->cr();
3140         has_error = true;
3141       }
3142     }
3143   }
3144 
3145   assert(has_error == false, "register allocation invalid");
3146 }
3147 
3148 
3149 void LinearScan::verify_no_oops_in_fixed_intervals() {










3150   LIR_OpVisitState visitor;
3151   for (int i = 0; i < block_count(); i++) {
3152     BlockBegin* block = block_at(i);
3153 
3154     LIR_OpList* instructions = block->lir()->instructions_list();
3155 
3156     for (int j = 0; j < instructions->length(); j++) {
3157       LIR_Op* op = instructions->at(j);
3158       int op_id = op->id();
3159 
3160       visitor.visit(op);
3161 








































3162       // oop-maps at calls do not contain registers, so check is not needed
3163       if (!visitor.has_call()) {
3164 
3165         for_each_visitor_mode(mode) {
3166           int n = visitor.opr_count(mode);
3167           for (int k = 0; k < n; k++) {
3168             LIR_Opr opr = visitor.opr_at(mode, k);
3169 
3170             if (opr->is_fixed_cpu() && opr->is_oop()) {
3171               // operand is a non-virtual cpu register and contains an oop
3172               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3173 
3174               Interval* interval = interval_at(reg_num(opr));
3175               assert(interval != NULL, "no interval");
3176 
3177               if (mode == LIR_OpVisitState::inputMode) {
3178                 if (interval->to() >= op_id + 1) {
3179                   assert(interval->to() < op_id + 2 ||
3180                          interval->has_hole_between(op_id, op_id + 2),
3181                          "oop input operand live after instruction");

2939   build_intervals();
2940   CHECK_BAILOUT();
2941   sort_intervals_before_allocation();
2942 
2943   NOT_PRODUCT(print_intervals("Before Register Allocation"));
2944   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
2945 
2946   allocate_registers();
2947   CHECK_BAILOUT();
2948 
2949   resolve_data_flow();
2950   if (compilation()->has_exception_handlers()) {
2951     resolve_exception_handlers();
2952   }
2953   // fill in number of spill slots into frame_map
2954   propagate_spill_slots();
2955   CHECK_BAILOUT();
2956 
2957   NOT_PRODUCT(print_intervals("After Register Allocation"));
2958   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));

2959 
2960   sort_intervals_after_allocation();
2961 
2962   DEBUG_ONLY(verify());
2963 
2964   eliminate_spill_moves();
2965   assign_reg_num();
2966   CHECK_BAILOUT();
2967 
2968   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
2969   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
2970 
2971   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
2972 
2973     if (use_fpu_stack_allocation()) {
2974       allocate_fpu_stack(); // Only has effect on Intel
2975       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
2976     }
2977   }
2978 
2979   { TIME_LINEAR_SCAN(timer_optimize_lir);
2980 
2981     EdgeMoveOptimizer::optimize(ir()->code());
2982     ControlFlowOptimizer::optimize(ir()->code());
2983     // check that cfg is still correct after optimizations

3132       if (i2->from() == 1 && i2->to() == 2) continue;
3133 
3134       int r1 = i1->assigned_reg();
3135       int r1Hi = i1->assigned_regHi();
3136       int r2 = i2->assigned_reg();
3137       int r2Hi = i2->assigned_regHi();
3138       if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
3139         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3140         i1->print(); tty->cr();
3141         i2->print(); tty->cr();
3142         has_error = true;
3143       }
3144     }
3145   }
3146 
3147   assert(has_error == false, "register allocation invalid");
3148 }
3149 
3150 
3151 void LinearScan::verify_no_oops_in_fixed_intervals() {
3152   Interval* fixed_intervals;
3153   Interval* other_intervals;
3154   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3155 
3156   // to ensure a walking until the last instruction id, add a dummy interval
3157   // with a high operation id
3158   other_intervals = new Interval(any_reg);
3159   other_intervals->add_range(max_jint - 2, max_jint - 1);
3160   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3161 
3162   LIR_OpVisitState visitor;
3163   for (int i = 0; i < block_count(); i++) {
3164     BlockBegin* block = block_at(i);
3165 
3166     LIR_OpList* instructions = block->lir()->instructions_list();
3167 
3168     for (int j = 0; j < instructions->length(); j++) {
3169       LIR_Op* op = instructions->at(j);
3170       int op_id = op->id();
3171 
3172       visitor.visit(op);
3173 
3174       if (visitor.info_count() > 0) {
3175         iw->walk_before(op->id());
3176         bool check_live = true;
3177         if (op->code() == lir_move) {
3178           LIR_Op1* move = (LIR_Op1*)op;
3179           check_live = move->patch_code() == lir_patch_none;
3180         }
3181         LIR_OpBranch* branch = op->as_OpBranch();
3182         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3183           check_live = false;
3184         }
3185 
3186         // Make sure none of the fixed registers is live across an oopmap since we can't handle that correctly
3187         if (check_live) {
3188           for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
3189             if (interval->current_to() > op->id() + 1) {
3190               bool ok = false;
3191               for_each_visitor_mode(mode) {
3192                 int n = visitor.opr_count(mode);
3193                 for (int k = 0; k < n; k++) {
3194                   LIR_Opr opr = visitor.opr_at(mode, k);
3195                   if (opr->is_fixed_cpu()) {
3196                     if (interval_at(reg_num(opr)) == interval) {
3197                       ok = true;
3198                       break;
3199                     }
3200                     int hi = reg_numHi(opr);
3201                     if (hi != -1 && interval_at(hi) == interval) {
3202                       ok = true;
3203                       break;
3204                     }
3205                   }
3206                 }
3207               }
3208               assert(ok, "fixed intervals should never be live across an oopmap point");
3209             }
3210           }
3211         }
3212       }
3213 
3214       // oop-maps at calls do not contain registers, so check is not needed
3215       if (!visitor.has_call()) {
3216 
3217         for_each_visitor_mode(mode) {
3218           int n = visitor.opr_count(mode);
3219           for (int k = 0; k < n; k++) {
3220             LIR_Opr opr = visitor.opr_at(mode, k);
3221 
3222             if (opr->is_fixed_cpu() && opr->is_oop()) {
3223               // operand is a non-virtual cpu register and contains an oop
3224               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3225 
3226               Interval* interval = interval_at(reg_num(opr));
3227               assert(interval != NULL, "no interval");
3228 
3229               if (mode == LIR_OpVisitState::inputMode) {
3230                 if (interval->to() >= op_id + 1) {
3231                   assert(interval->to() < op_id + 2 ||
3232                          interval->has_hole_between(op_id, op_id + 2),
3233                          "oop input operand live after instruction");