src/cpu/sparc/vm/sparc.ad

*** 6666,6685 ****
    format %{ "MOV$cmp  $icc,$src,$dst" %}
    ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(ialu_imm);
  %}
  
! instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
    match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
    ins_cost(150);
    size(4);
    format %{ "MOV$cmp  $icc,$src,$dst" %}
    ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(ialu_reg);
  %}
  
! instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
    match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
    ins_cost(140);
    size(4);
    format %{ "MOV$cmp  $icc,$src,$dst" %}
    ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
--- 6666,6685 ----
    format %{ "MOV$cmp  $icc,$src,$dst" %}
    ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(ialu_imm);
  %}
  
! instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
    match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
    ins_cost(150);
    size(4);
    format %{ "MOV$cmp  $icc,$src,$dst" %}
    ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(ialu_reg);
  %}
  
! instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
    match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
    ins_cost(140);
    size(4);
    format %{ "MOV$cmp  $icc,$src,$dst" %}
    ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
*** 6721,6730 ****
--- 6721,6740 ----
    format %{ "MOV$cmp  $icc,$src,$dst" %}
    ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(ialu_reg);
  %}
  
+ // This instruction also works with CmpN so we don't need cmovNN_reg.
+ instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
+   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
+   ins_cost(150);
+   size(4);
+   format %{ "MOV$cmp  $icc,$src,$dst" %}
+   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
+   ins_pipe(ialu_reg);
+ %}
+ 
  instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
    match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
    ins_cost(150);
    size(4);
    format %{ "MOV$cmp $fcc,$src,$dst" %}
*** 6758,6767 ****
--- 6768,6787 ----
    format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
    ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(ialu_reg);
  %}
  
+ instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
+   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
+   ins_cost(150);
+ 
+   size(4);
+   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
+   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
+   ins_pipe(ialu_reg);
+ %}
+ 
  instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
    match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
    ins_cost(140);
  
    size(4);
*** 6768,6777 ****
--- 6788,6807 ----
    format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
    ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(ialu_imm);
  %}
  
+ instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
+   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
+   ins_cost(140);
+ 
+   size(4);
+   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
+   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
+   ins_pipe(ialu_imm);
+ %}
+ 
  instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
    match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
    ins_cost(150);
    size(4);
    format %{ "MOV$cmp $fcc,$src,$dst" %}
*** 6807,6816 ****
--- 6837,6857 ----
    opcode(0x101);
    ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(int_conditional_float_move);
  %}
  
+ instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
+   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
+   ins_cost(150);
+ 
+   size(4);
+   format %{ "FMOVS$cmp $icc,$src,$dst" %}
+   opcode(0x101);
+   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
+   ins_pipe(int_conditional_float_move);
+ %}
+ 
  // Conditional move,
  instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
    match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
    ins_cost(150);
    size(4);
*** 6840,6849 ****
--- 6881,6901 ----
    opcode(0x102);
    ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(int_conditional_double_move);
  %}
  
+ instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
+   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
+   ins_cost(150);
+ 
+   size(4);
+   format %{ "FMOVD$cmp $icc,$src,$dst" %}
+   opcode(0x102);
+   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
+   ins_pipe(int_conditional_double_move);
+ %}
+ 
  // Conditional move,
  instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
    match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
    ins_cost(150);
    size(4);
*** 6871,6880 ****
--- 6923,6943 ----
  %}
  
  instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
    match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
    ins_cost(150);
+ 
+   size(4);
+   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
+   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
+   ins_pipe(ialu_reg);
+ %}
+ 
+ 
+ instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
+   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
+   ins_cost(150);
  
    size(4);
    format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
    ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
    ins_pipe(ialu_reg);